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rtl-llm
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chisel-verilog-pairs

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prompt stringlengths 162 4.26M	response stringlengths 109 5.16M
Generate the Verilog code corresponding to this FIRRTL code module ALU_5 : input clock : Clock input reset : Reset output io : { flip dw : UInt<1>, flip fn : UInt<5>, flip in2 : UInt<64>, flip in1 : UInt<64>, out : UInt<64>, adder_out : UInt<64>, cmp_out : UInt<1>} node _in2_inv_T = bits(io.fn, 3, 3) node _in2_inv_T_1 = not(io.in2) node in2_inv = mux(_in2_inv_T, _in2_inv_T_1, io.in2) node in1_xor_in2 = xor(io.in1, in2_inv) node in1_and_in2 = and(io.in1, in2_inv) node _io_adder_out_T = add(io.in1, in2_inv) node _io_adder_out_T_1 = tail(_io_adder_out_T, 1) node _io_adder_out_T_2 = bits(io.fn, 3, 3) node _io_adder_out_T_3 = add(_io_adder_out_T_1, _io_adder_out_T_2) node _io_adder_out_T_4 = tail(_io_adder_out_T_3, 1) connect io.adder_out, _io_adder_out_T_4 node _slt_T = bits(io.in1, 63, 63) node _slt_T_1 = bits(io.in2, 63, 63) node _slt_T_2 = eq(_slt_T, _slt_T_1) node _slt_T_3 = bits(io.adder_out, 63, 63) node _slt_T_4 = bits(io.fn, 1, 1) node _slt_T_5 = bits(io.in2, 63, 63) node _slt_T_6 = bits(io.in1, 63, 63) node _slt_T_7 = mux(_slt_T_4, _slt_T_5, _slt_T_6) node slt = mux(_slt_T_2, _slt_T_3, _slt_T_7) node _io_cmp_out_T = bits(io.fn, 0, 0) node _io_cmp_out_T_1 = bits(io.fn, 3, 3) node _io_cmp_out_T_2 = eq(_io_cmp_out_T_1, UInt<1>(0h0)) node _io_cmp_out_T_3 = eq(in1_xor_in2, UInt<1>(0h0)) node _io_cmp_out_T_4 = mux(_io_cmp_out_T_2, _io_cmp_out_T_3, slt) node _io_cmp_out_T_5 = xor(_io_cmp_out_T, _io_cmp_out_T_4) connect io.cmp_out, _io_cmp_out_T_5 node _shin_hi_32_T = bits(io.fn, 3, 3) node _shin_hi_32_T_1 = bits(io.in1, 31, 31) node _shin_hi_32_T_2 = and(_shin_hi_32_T, _shin_hi_32_T_1) node shin_hi_32 = mux(_shin_hi_32_T_2, UInt<32>(0hffffffff), UInt<32>(0h0)) node _shin_hi_T = eq(io.dw, UInt<1>(0h1)) node _shin_hi_T_1 = bits(io.in1, 63, 32) node shin_hi = mux(_shin_hi_T, _shin_hi_T_1, shin_hi_32) node _shamt_T = bits(io.in2, 5, 5) node _shamt_T_1 = eq(io.dw, UInt<1>(0h1)) node _shamt_T_2 = and(_shamt_T, _shamt_T_1) node _shamt_T_3 = bits(io.in2, 4, 0) node shamt = cat(_shamt_T_2, _shamt_T_3) node _T = bits(io.in1, 31, 0) node shin_r = cat(shin_hi, _T) node _shin_T = eq(io.fn, UInt<3>(0h5)) node _shin_T_1 = eq(io.fn, UInt<4>(0hb)) node _shin_T_2 = eq(io.fn, UInt<5>(0h12)) node _shin_T_3 = eq(io.fn, UInt<5>(0h13)) node _shin_T_4 = or(_shin_T, _shin_T_1) node _shin_T_5 = or(_shin_T_4, _shin_T_2) node _shin_T_6 = or(_shin_T_5, _shin_T_3) node _shin_T_7 = eq(_shin_T_6, UInt<1>(0h0)) node _shin_T_8 = shl(UInt<32>(0hffffffff), 32) node _shin_T_9 = xor(UInt<64>(0hffffffffffffffff), _shin_T_8) node _shin_T_10 = shr(shin_r, 32) node _shin_T_11 = and(_shin_T_10, _shin_T_9) node _shin_T_12 = bits(shin_r, 31, 0) node _shin_T_13 = shl(_shin_T_12, 32) node _shin_T_14 = not(_shin_T_9) node _shin_T_15 = and(_shin_T_13, _shin_T_14) node _shin_T_16 = or(_shin_T_11, _shin_T_15) node _shin_T_17 = bits(_shin_T_9, 47, 0) node _shin_T_18 = shl(_shin_T_17, 16) node _shin_T_19 = xor(_shin_T_9, _shin_T_18) node _shin_T_20 = shr(_shin_T_16, 16) node _shin_T_21 = and(_shin_T_20, _shin_T_19) node _shin_T_22 = bits(_shin_T_16, 47, 0) node _shin_T_23 = shl(_shin_T_22, 16) node _shin_T_24 = not(_shin_T_19) node _shin_T_25 = and(_shin_T_23, _shin_T_24) node _shin_T_26 = or(_shin_T_21, _shin_T_25) node _shin_T_27 = bits(_shin_T_19, 55, 0) node _shin_T_28 = shl(_shin_T_27, 8) node _shin_T_29 = xor(_shin_T_19, _shin_T_28) node _shin_T_30 = shr(_shin_T_26, 8) node _shin_T_31 = and(_shin_T_30, _shin_T_29) node _shin_T_32 = bits(_shin_T_26, 55, 0) node _shin_T_33 = shl(_shin_T_32, 8) node _shin_T_34 = not(_shin_T_29) node _shin_T_35 = and(_shin_T_33, _shin_T_34) node _shin_T_36 = or(_shin_T_31, _shin_T_35) node _shin_T_37 = bits(_shin_T_29, 59, 0) node _shin_T_38 = shl(_shin_T_37, 4) node _shin_T_39 = xor(_shin_T_29, _shin_T_38) node _shin_T_40 = shr(_shin_T_36, 4) node _shin_T_41 = and(_shin_T_40, _shin_T_39) node _shin_T_42 = bits(_shin_T_36, 59, 0) node _shin_T_43 = shl(_shin_T_42, 4) node _shin_T_44 = not(_shin_T_39) node _shin_T_45 = and(_shin_T_43, _shin_T_44) node _shin_T_46 = or(_shin_T_41, _shin_T_45) node _shin_T_47 = bits(_shin_T_39, 61, 0) node _shin_T_48 = shl(_shin_T_47, 2) node _shin_T_49 = xor(_shin_T_39, _shin_T_48) node _shin_T_50 = shr(_shin_T_46, 2) node _shin_T_51 = and(_shin_T_50, _shin_T_49) node _shin_T_52 = bits(_shin_T_46, 61, 0) node _shin_T_53 = shl(_shin_T_52, 2) node _shin_T_54 = not(_shin_T_49) node _shin_T_55 = and(_shin_T_53, _shin_T_54) node _shin_T_56 = or(_shin_T_51, _shin_T_55) node _shin_T_57 = bits(_shin_T_49, 62, 0) node _shin_T_58 = shl(_shin_T_57, 1) node _shin_T_59 = xor(_shin_T_49, _shin_T_58) node _shin_T_60 = shr(_shin_T_56, 1) node _shin_T_61 = and(_shin_T_60, _shin_T_59) node _shin_T_62 = bits(_shin_T_56, 62, 0) node _shin_T_63 = shl(_shin_T_62, 1) node _shin_T_64 = not(_shin_T_59) node _shin_T_65 = and(_shin_T_63, _shin_T_64) node _shin_T_66 = or(_shin_T_61, _shin_T_65) node shin = mux(_shin_T_7, _shin_T_66, shin_r) node _shout_r_T = bits(io.fn, 3, 3) node _shout_r_T_1 = bits(shin, 63, 63) node _shout_r_T_2 = and(_shout_r_T, _shout_r_T_1) node _shout_r_T_3 = cat(_shout_r_T_2, shin) node _shout_r_T_4 = asSInt(_shout_r_T_3) node _shout_r_T_5 = dshr(_shout_r_T_4, shamt) node shout_r = bits(_shout_r_T_5, 63, 0) node _shout_l_T = shl(UInt<32>(0hffffffff), 32) node _shout_l_T_1 = xor(UInt<64>(0hffffffffffffffff), _shout_l_T) node _shout_l_T_2 = shr(shout_r, 32) node _shout_l_T_3 = and(_shout_l_T_2, _shout_l_T_1) node _shout_l_T_4 = bits(shout_r, 31, 0) node _shout_l_T_5 = shl(_shout_l_T_4, 32) node _shout_l_T_6 = not(_shout_l_T_1) node _shout_l_T_7 = and(_shout_l_T_5, _shout_l_T_6) node _shout_l_T_8 = or(_shout_l_T_3, _shout_l_T_7) node _shout_l_T_9 = bits(_shout_l_T_1, 47, 0) node _shout_l_T_10 = shl(_shout_l_T_9, 16) node _shout_l_T_11 = xor(_shout_l_T_1, _shout_l_T_10) node _shout_l_T_12 = shr(_shout_l_T_8, 16) node _shout_l_T_13 = and(_shout_l_T_12, _shout_l_T_11) node _shout_l_T_14 = bits(_shout_l_T_8, 47, 0) node _shout_l_T_15 = shl(_shout_l_T_14, 16) node _shout_l_T_16 = not(_shout_l_T_11) node _shout_l_T_17 = and(_shout_l_T_15, _shout_l_T_16) node _shout_l_T_18 = or(_shout_l_T_13, _shout_l_T_17) node _shout_l_T_19 = bits(_shout_l_T_11, 55, 0) node _shout_l_T_20 = shl(_shout_l_T_19, 8) node _shout_l_T_21 = xor(_shout_l_T_11, _shout_l_T_20) node _shout_l_T_22 = shr(_shout_l_T_18, 8) node _shout_l_T_23 = and(_shout_l_T_22, _shout_l_T_21) node _shout_l_T_24 = bits(_shout_l_T_18, 55, 0) node _shout_l_T_25 = shl(_shout_l_T_24, 8) node _shout_l_T_26 = not(_shout_l_T_21) node _shout_l_T_27 = and(_shout_l_T_25, _shout_l_T_26) node _shout_l_T_28 = or(_shout_l_T_23, _shout_l_T_27) node _shout_l_T_29 = bits(_shout_l_T_21, 59, 0) node _shout_l_T_30 = shl(_shout_l_T_29, 4) node _shout_l_T_31 = xor(_shout_l_T_21, _shout_l_T_30) node _shout_l_T_32 = shr(_shout_l_T_28, 4) node _shout_l_T_33 = and(_shout_l_T_32, _shout_l_T_31) node _shout_l_T_34 = bits(_shout_l_T_28, 59, 0) node _shout_l_T_35 = shl(_shout_l_T_34, 4) node _shout_l_T_36 = not(_shout_l_T_31) node _shout_l_T_37 = and(_shout_l_T_35, _shout_l_T_36) node _shout_l_T_38 = or(_shout_l_T_33, _shout_l_T_37) node _shout_l_T_39 = bits(_shout_l_T_31, 61, 0) node _shout_l_T_40 = shl(_shout_l_T_39, 2) node _shout_l_T_41 = xor(_shout_l_T_31, _shout_l_T_40) node _shout_l_T_42 = shr(_shout_l_T_38, 2) node _shout_l_T_43 = and(_shout_l_T_42, _shout_l_T_41) node _shout_l_T_44 = bits(_shout_l_T_38, 61, 0) node _shout_l_T_45 = shl(_shout_l_T_44, 2) node _shout_l_T_46 = not(_shout_l_T_41) node _shout_l_T_47 = and(_shout_l_T_45, _shout_l_T_46) node _shout_l_T_48 = or(_shout_l_T_43, _shout_l_T_47) node _shout_l_T_49 = bits(_shout_l_T_41, 62, 0) node _shout_l_T_50 = shl(_shout_l_T_49, 1) node _shout_l_T_51 = xor(_shout_l_T_41, _shout_l_T_50) node _shout_l_T_52 = shr(_shout_l_T_48, 1) node _shout_l_T_53 = and(_shout_l_T_52, _shout_l_T_51) node _shout_l_T_54 = bits(_shout_l_T_48, 62, 0) node _shout_l_T_55 = shl(_shout_l_T_54, 1) node _shout_l_T_56 = not(_shout_l_T_51) node _shout_l_T_57 = and(_shout_l_T_55, _shout_l_T_56) node shout_l = or(_shout_l_T_53, _shout_l_T_57) node _shout_T = eq(io.fn, UInt<3>(0h5)) node _shout_T_1 = eq(io.fn, UInt<4>(0hb)) node _shout_T_2 = or(_shout_T, _shout_T_1) node _shout_T_3 = eq(io.fn, UInt<5>(0h13)) node _shout_T_4 = or(_shout_T_2, _shout_T_3) node _shout_T_5 = mux(_shout_T_4, shout_r, UInt<1>(0h0)) node _shout_T_6 = eq(io.fn, UInt<1>(0h1)) node _shout_T_7 = mux(_shout_T_6, shout_l, UInt<1>(0h0)) node shout = or(_shout_T_5, _shout_T_7) node in2_not_zero = orr(io.in2) node _logic_T = eq(io.fn, UInt<3>(0h4)) node _logic_T_1 = eq(io.fn, UInt<3>(0h6)) node _logic_T_2 = or(_logic_T, _logic_T_1) node _logic_T_3 = eq(io.fn, UInt<5>(0h19)) node _logic_T_4 = or(_logic_T_2, _logic_T_3) node _logic_T_5 = eq(io.fn, UInt<5>(0h1a)) node _logic_T_6 = or(_logic_T_4, _logic_T_5) node _logic_T_7 = mux(_logic_T_6, in1_xor_in2, UInt<1>(0h0)) node _logic_T_8 = eq(io.fn, UInt<3>(0h6)) node _logic_T_9 = eq(io.fn, UInt<3>(0h7)) node _logic_T_10 = or(_logic_T_8, _logic_T_9) node _logic_T_11 = eq(io.fn, UInt<5>(0h19)) node _logic_T_12 = or(_logic_T_10, _logic_T_11) node _logic_T_13 = eq(io.fn, UInt<5>(0h18)) node _logic_T_14 = or(_logic_T_12, _logic_T_13) node _logic_T_15 = mux(_logic_T_14, in1_and_in2, UInt<1>(0h0)) node logic = or(_logic_T_7, _logic_T_15) node _bext_mask_T = eq(io.fn, UInt<5>(0h13)) node _bext_mask_T_1 = and(UInt<1>(0h1), _bext_mask_T) node _bext_mask_T_2 = not(UInt<64>(0h0)) node bext_mask = mux(_bext_mask_T_1, UInt<1>(0h1), _bext_mask_T_2) node _shift_logic_T = geq(io.fn, UInt<4>(0hc)) node _shift_logic_T_1 = leq(io.fn, UInt<4>(0hf)) node _shift_logic_T_2 = and(_shift_logic_T, _shift_logic_T_1) node _shift_logic_T_3 = and(_shift_logic_T_2, slt) node _shift_logic_T_4 = or(_shift_logic_T_3, logic) node _shift_logic_T_5 = and(shout, bext_mask) node shift_logic = or(_shift_logic_T_4, _shift_logic_T_5) node _tz_in_T = eq(io.dw, UInt<1>(0h0)) node _tz_in_T_1 = bits(io.in2, 0, 0) node _tz_in_T_2 = eq(_tz_in_T_1, UInt<1>(0h0)) node _tz_in_T_3 = cat(_tz_in_T, _tz_in_T_2) node _tz_in_T_4 = shl(UInt<32>(0hffffffff), 32) node _tz_in_T_5 = xor(UInt<64>(0hffffffffffffffff), _tz_in_T_4) node _tz_in_T_6 = shr(io.in1, 32) node _tz_in_T_7 = and(_tz_in_T_6, _tz_in_T_5) node _tz_in_T_8 = bits(io.in1, 31, 0) node _tz_in_T_9 = shl(_tz_in_T_8, 32) node _tz_in_T_10 = not(_tz_in_T_5) node _tz_in_T_11 = and(_tz_in_T_9, _tz_in_T_10) node _tz_in_T_12 = or(_tz_in_T_7, _tz_in_T_11) node _tz_in_T_13 = bits(_tz_in_T_5, 47, 0) node _tz_in_T_14 = shl(_tz_in_T_13, 16) node _tz_in_T_15 = xor(_tz_in_T_5, _tz_in_T_14) node _tz_in_T_16 = shr(_tz_in_T_12, 16) node _tz_in_T_17 = and(_tz_in_T_16, _tz_in_T_15) node _tz_in_T_18 = bits(_tz_in_T_12, 47, 0) node _tz_in_T_19 = shl(_tz_in_T_18, 16) node _tz_in_T_20 = not(_tz_in_T_15) node _tz_in_T_21 = and(_tz_in_T_19, _tz_in_T_20) node _tz_in_T_22 = or(_tz_in_T_17, _tz_in_T_21) node _tz_in_T_23 = bits(_tz_in_T_15, 55, 0) node _tz_in_T_24 = shl(_tz_in_T_23, 8) node _tz_in_T_25 = xor(_tz_in_T_15, _tz_in_T_24) node _tz_in_T_26 = shr(_tz_in_T_22, 8) node _tz_in_T_27 = and(_tz_in_T_26, _tz_in_T_25) node _tz_in_T_28 = bits(_tz_in_T_22, 55, 0) node _tz_in_T_29 = shl(_tz_in_T_28, 8) node _tz_in_T_30 = not(_tz_in_T_25) node _tz_in_T_31 = and(_tz_in_T_29, _tz_in_T_30) node _tz_in_T_32 = or(_tz_in_T_27, _tz_in_T_31) node _tz_in_T_33 = bits(_tz_in_T_25, 59, 0) node _tz_in_T_34 = shl(_tz_in_T_33, 4) node _tz_in_T_35 = xor(_tz_in_T_25, _tz_in_T_34) node _tz_in_T_36 = shr(_tz_in_T_32, 4) node _tz_in_T_37 = and(_tz_in_T_36, _tz_in_T_35) node _tz_in_T_38 = bits(_tz_in_T_32, 59, 0) node _tz_in_T_39 = shl(_tz_in_T_38, 4) node _tz_in_T_40 = not(_tz_in_T_35) node _tz_in_T_41 = and(_tz_in_T_39, _tz_in_T_40) node _tz_in_T_42 = or(_tz_in_T_37, _tz_in_T_41) node _tz_in_T_43 = bits(_tz_in_T_35, 61, 0) node _tz_in_T_44 = shl(_tz_in_T_43, 2) node _tz_in_T_45 = xor(_tz_in_T_35, _tz_in_T_44) node _tz_in_T_46 = shr(_tz_in_T_42, 2) node _tz_in_T_47 = and(_tz_in_T_46, _tz_in_T_45) node _tz_in_T_48 = bits(_tz_in_T_42, 61, 0) node _tz_in_T_49 = shl(_tz_in_T_48, 2) node _tz_in_T_50 = not(_tz_in_T_45) node _tz_in_T_51 = and(_tz_in_T_49, _tz_in_T_50) node _tz_in_T_52 = or(_tz_in_T_47, _tz_in_T_51) node _tz_in_T_53 = bits(_tz_in_T_45, 62, 0) node _tz_in_T_54 = shl(_tz_in_T_53, 1) node _tz_in_T_55 = xor(_tz_in_T_45, _tz_in_T_54) node _tz_in_T_56 = shr(_tz_in_T_52, 1) node _tz_in_T_57 = and(_tz_in_T_56, _tz_in_T_55) node _tz_in_T_58 = bits(_tz_in_T_52, 62, 0) node _tz_in_T_59 = shl(_tz_in_T_58, 1) node _tz_in_T_60 = not(_tz_in_T_55) node _tz_in_T_61 = and(_tz_in_T_59, _tz_in_T_60) node _tz_in_T_62 = or(_tz_in_T_57, _tz_in_T_61) node _tz_in_T_63 = bits(io.in1, 31, 0) node _tz_in_T_64 = cat(UInt<1>(0h1), _tz_in_T_63) node _tz_in_T_65 = bits(io.in1, 31, 0) node _tz_in_T_66 = shl(UInt<16>(0hffff), 16) node _tz_in_T_67 = xor(UInt<32>(0hffffffff), _tz_in_T_66) node _tz_in_T_68 = shr(_tz_in_T_65, 16) node _tz_in_T_69 = and(_tz_in_T_68, _tz_in_T_67) node _tz_in_T_70 = bits(_tz_in_T_65, 15, 0) node _tz_in_T_71 = shl(_tz_in_T_70, 16) node _tz_in_T_72 = not(_tz_in_T_67) node _tz_in_T_73 = and(_tz_in_T_71, _tz_in_T_72) node _tz_in_T_74 = or(_tz_in_T_69, _tz_in_T_73) node _tz_in_T_75 = bits(_tz_in_T_67, 23, 0) node _tz_in_T_76 = shl(_tz_in_T_75, 8) node _tz_in_T_77 = xor(_tz_in_T_67, _tz_in_T_76) node _tz_in_T_78 = shr(_tz_in_T_74, 8) node _tz_in_T_79 = and(_tz_in_T_78, _tz_in_T_77) node _tz_in_T_80 = bits(_tz_in_T_74, 23, 0) node _tz_in_T_81 = shl(_tz_in_T_80, 8) node _tz_in_T_82 = not(_tz_in_T_77) node _tz_in_T_83 = and(_tz_in_T_81, _tz_in_T_82) node _tz_in_T_84 = or(_tz_in_T_79, _tz_in_T_83) node _tz_in_T_85 = bits(_tz_in_T_77, 27, 0) node _tz_in_T_86 = shl(_tz_in_T_85, 4) node _tz_in_T_87 = xor(_tz_in_T_77, _tz_in_T_86) node _tz_in_T_88 = shr(_tz_in_T_84, 4) node _tz_in_T_89 = and(_tz_in_T_88, _tz_in_T_87) node _tz_in_T_90 = bits(_tz_in_T_84, 27, 0) node _tz_in_T_91 = shl(_tz_in_T_90, 4) node _tz_in_T_92 = not(_tz_in_T_87) node _tz_in_T_93 = and(_tz_in_T_91, _tz_in_T_92) node _tz_in_T_94 = or(_tz_in_T_89, _tz_in_T_93) node _tz_in_T_95 = bits(_tz_in_T_87, 29, 0) node _tz_in_T_96 = shl(_tz_in_T_95, 2) node _tz_in_T_97 = xor(_tz_in_T_87, _tz_in_T_96) node _tz_in_T_98 = shr(_tz_in_T_94, 2) node _tz_in_T_99 = and(_tz_in_T_98, _tz_in_T_97) node _tz_in_T_100 = bits(_tz_in_T_94, 29, 0) node _tz_in_T_101 = shl(_tz_in_T_100, 2) node _tz_in_T_102 = not(_tz_in_T_97) node _tz_in_T_103 = and(_tz_in_T_101, _tz_in_T_102) node _tz_in_T_104 = or(_tz_in_T_99, _tz_in_T_103) node _tz_in_T_105 = bits(_tz_in_T_97, 30, 0) node _tz_in_T_106 = shl(_tz_in_T_105, 1) node _tz_in_T_107 = xor(_tz_in_T_97, _tz_in_T_106) node _tz_in_T_108 = shr(_tz_in_T_104, 1) node _tz_in_T_109 = and(_tz_in_T_108, _tz_in_T_107) node _tz_in_T_110 = bits(_tz_in_T_104, 30, 0) node _tz_in_T_111 = shl(_tz_in_T_110, 1) node _tz_in_T_112 = not(_tz_in_T_107) node _tz_in_T_113 = and(_tz_in_T_111, _tz_in_T_112) node _tz_in_T_114 = or(_tz_in_T_109, _tz_in_T_113) node _tz_in_T_115 = cat(UInt<1>(0h1), _tz_in_T_114) node _tz_in_T_116 = eq(UInt<1>(0h1), _tz_in_T_3) node _tz_in_T_117 = mux(_tz_in_T_116, _tz_in_T_62, io.in1) node _tz_in_T_118 = eq(UInt<2>(0h2), _tz_in_T_3) node _tz_in_T_119 = mux(_tz_in_T_118, _tz_in_T_64, _tz_in_T_117) node _tz_in_T_120 = eq(UInt<2>(0h3), _tz_in_T_3) node tz_in = mux(_tz_in_T_120, _tz_in_T_115, _tz_in_T_119) node _popc_in_T = bits(io.in2, 1, 1) node _popc_in_T_1 = eq(io.dw, UInt<1>(0h0)) node _popc_in_T_2 = bits(io.in1, 31, 0) node _popc_in_T_3 = mux(_popc_in_T_1, _popc_in_T_2, io.in1) node _popc_in_T_4 = cat(UInt<1>(0h1), tz_in) node _popc_in_T_5 = bits(_popc_in_T_4, 0, 0) node _popc_in_T_6 = bits(_popc_in_T_4, 1, 1) node _popc_in_T_7 = bits(_popc_in_T_4, 2, 2) node _popc_in_T_8 = bits(_popc_in_T_4, 3, 3) node _popc_in_T_9 = bits(_popc_in_T_4, 4, 4) node _popc_in_T_10 = bits(_popc_in_T_4, 5, 5) node _popc_in_T_11 = bits(_popc_in_T_4, 6, 6) node _popc_in_T_12 = bits(_popc_in_T_4, 7, 7) node _popc_in_T_13 = bits(_popc_in_T_4, 8, 8) node _popc_in_T_14 = bits(_popc_in_T_4, 9, 9) node _popc_in_T_15 = bits(_popc_in_T_4, 10, 10) node _popc_in_T_16 = bits(_popc_in_T_4, 11, 11) node _popc_in_T_17 = bits(_popc_in_T_4, 12, 12) node _popc_in_T_18 = bits(_popc_in_T_4, 13, 13) node _popc_in_T_19 = bits(_popc_in_T_4, 14, 14) node _popc_in_T_20 = bits(_popc_in_T_4, 15, 15) node _popc_in_T_21 = bits(_popc_in_T_4, 16, 16) node _popc_in_T_22 = bits(_popc_in_T_4, 17, 17) node _popc_in_T_23 = bits(_popc_in_T_4, 18, 18) node _popc_in_T_24 = bits(_popc_in_T_4, 19, 19) node _popc_in_T_25 = bits(_popc_in_T_4, 20, 20) node _popc_in_T_26 = bits(_popc_in_T_4, 21, 21) node _popc_in_T_27 = bits(_popc_in_T_4, 22, 22) node _popc_in_T_28 = bits(_popc_in_T_4, 23, 23) node _popc_in_T_29 = bits(_popc_in_T_4, 24, 24) node _popc_in_T_30 = bits(_popc_in_T_4, 25, 25) node _popc_in_T_31 = bits(_popc_in_T_4, 26, 26) node _popc_in_T_32 = bits(_popc_in_T_4, 27, 27) node _popc_in_T_33 = bits(_popc_in_T_4, 28, 28) node _popc_in_T_34 = bits(_popc_in_T_4, 29, 29) node _popc_in_T_35 = bits(_popc_in_T_4, 30, 30) node _popc_in_T_36 = bits(_popc_in_T_4, 31, 31) node _popc_in_T_37 = bits(_popc_in_T_4, 32, 32) node _popc_in_T_38 = bits(_popc_in_T_4, 33, 33) node _popc_in_T_39 = bits(_popc_in_T_4, 34, 34) node _popc_in_T_40 = bits(_popc_in_T_4, 35, 35) node _popc_in_T_41 = bits(_popc_in_T_4, 36, 36) node _popc_in_T_42 = bits(_popc_in_T_4, 37, 37) node _popc_in_T_43 = bits(_popc_in_T_4, 38, 38) node _popc_in_T_44 = bits(_popc_in_T_4, 39, 39) node _popc_in_T_45 = bits(_popc_in_T_4, 40, 40) node _popc_in_T_46 = bits(_popc_in_T_4, 41, 41) node _popc_in_T_47 = bits(_popc_in_T_4, 42, 42) node _popc_in_T_48 = bits(_popc_in_T_4, 43, 43) node _popc_in_T_49 = bits(_popc_in_T_4, 44, 44) node _popc_in_T_50 = bits(_popc_in_T_4, 45, 45) node _popc_in_T_51 = bits(_popc_in_T_4, 46, 46) node _popc_in_T_52 = bits(_popc_in_T_4, 47, 47) node _popc_in_T_53 = bits(_popc_in_T_4, 48, 48) node _popc_in_T_54 = bits(_popc_in_T_4, 49, 49) node _popc_in_T_55 = bits(_popc_in_T_4, 50, 50) node _popc_in_T_56 = bits(_popc_in_T_4, 51, 51) node _popc_in_T_57 = bits(_popc_in_T_4, 52, 52) node _popc_in_T_58 = bits(_popc_in_T_4, 53, 53) node _popc_in_T_59 = bits(_popc_in_T_4, 54, 54) node _popc_in_T_60 = bits(_popc_in_T_4, 55, 55) node _popc_in_T_61 = bits(_popc_in_T_4, 56, 56) node _popc_in_T_62 = bits(_popc_in_T_4, 57, 57) node _popc_in_T_63 = bits(_popc_in_T_4, 58, 58) node _popc_in_T_64 = bits(_popc_in_T_4, 59, 59) node _popc_in_T_65 = bits(_popc_in_T_4, 60, 60) node _popc_in_T_66 = bits(_popc_in_T_4, 61, 61) node _popc_in_T_67 = bits(_popc_in_T_4, 62, 62) node _popc_in_T_68 = bits(_popc_in_T_4, 63, 63) node _popc_in_T_69 = bits(_popc_in_T_4, 64, 64) node _popc_in_T_70 = mux(_popc_in_T_69, UInt<65>(0h10000000000000000), UInt<65>(0h0)) node _popc_in_T_71 = mux(_popc_in_T_68, UInt<65>(0h8000000000000000), _popc_in_T_70) node _popc_in_T_72 = mux(_popc_in_T_67, UInt<65>(0h4000000000000000), _popc_in_T_71) node _popc_in_T_73 = mux(_popc_in_T_66, UInt<65>(0h2000000000000000), _popc_in_T_72) node _popc_in_T_74 = mux(_popc_in_T_65, UInt<65>(0h1000000000000000), _popc_in_T_73) node _popc_in_T_75 = mux(_popc_in_T_64, UInt<65>(0h800000000000000), _popc_in_T_74) node _popc_in_T_76 = mux(_popc_in_T_63, UInt<65>(0h400000000000000), _popc_in_T_75) node _popc_in_T_77 = mux(_popc_in_T_62, UInt<65>(0h200000000000000), _popc_in_T_76) node _popc_in_T_78 = mux(_popc_in_T_61, UInt<65>(0h100000000000000), _popc_in_T_77) node _popc_in_T_79 = mux(_popc_in_T_60, UInt<65>(0h80000000000000), _popc_in_T_78) node _popc_in_T_80 = mux(_popc_in_T_59, UInt<65>(0h40000000000000), _popc_in_T_79) node _popc_in_T_81 = mux(_popc_in_T_58, UInt<65>(0h20000000000000), _popc_in_T_80) node _popc_in_T_82 = mux(_popc_in_T_57, UInt<65>(0h10000000000000), _popc_in_T_81) node _popc_in_T_83 = mux(_popc_in_T_56, UInt<65>(0h8000000000000), _popc_in_T_82) node _popc_in_T_84 = mux(_popc_in_T_55, UInt<65>(0h4000000000000), _popc_in_T_83) node _popc_in_T_85 = mux(_popc_in_T_54, UInt<65>(0h2000000000000), _popc_in_T_84) node _popc_in_T_86 = mux(_popc_in_T_53, UInt<65>(0h1000000000000), _popc_in_T_85) node _popc_in_T_87 = mux(_popc_in_T_52, UInt<65>(0h800000000000), _popc_in_T_86) node _popc_in_T_88 = mux(_popc_in_T_51, UInt<65>(0h400000000000), _popc_in_T_87) node _popc_in_T_89 = mux(_popc_in_T_50, UInt<65>(0h200000000000), _popc_in_T_88) node _popc_in_T_90 = mux(_popc_in_T_49, UInt<65>(0h100000000000), _popc_in_T_89) node _popc_in_T_91 = mux(_popc_in_T_48, UInt<65>(0h80000000000), _popc_in_T_90) node _popc_in_T_92 = mux(_popc_in_T_47, UInt<65>(0h40000000000), _popc_in_T_91) node _popc_in_T_93 = mux(_popc_in_T_46, UInt<65>(0h20000000000), _popc_in_T_92) node _popc_in_T_94 = mux(_popc_in_T_45, UInt<65>(0h10000000000), _popc_in_T_93) node _popc_in_T_95 = mux(_popc_in_T_44, UInt<65>(0h8000000000), _popc_in_T_94) node _popc_in_T_96 = mux(_popc_in_T_43, UInt<65>(0h4000000000), _popc_in_T_95) node _popc_in_T_97 = mux(_popc_in_T_42, UInt<65>(0h2000000000), _popc_in_T_96) node _popc_in_T_98 = mux(_popc_in_T_41, UInt<65>(0h1000000000), _popc_in_T_97) node _popc_in_T_99 = mux(_popc_in_T_40, UInt<65>(0h800000000), _popc_in_T_98) node _popc_in_T_100 = mux(_popc_in_T_39, UInt<65>(0h400000000), _popc_in_T_99) node _popc_in_T_101 = mux(_popc_in_T_38, UInt<65>(0h200000000), _popc_in_T_100) node _popc_in_T_102 = mux(_popc_in_T_37, UInt<65>(0h100000000), _popc_in_T_101) node _popc_in_T_103 = mux(_popc_in_T_36, UInt<65>(0h80000000), _popc_in_T_102) node _popc_in_T_104 = mux(_popc_in_T_35, UInt<65>(0h40000000), _popc_in_T_103) node _popc_in_T_105 = mux(_popc_in_T_34, UInt<65>(0h20000000), _popc_in_T_104) node _popc_in_T_106 = mux(_popc_in_T_33, UInt<65>(0h10000000), _popc_in_T_105) node _popc_in_T_107 = mux(_popc_in_T_32, UInt<65>(0h8000000), _popc_in_T_106) node _popc_in_T_108 = mux(_popc_in_T_31, UInt<65>(0h4000000), _popc_in_T_107) node _popc_in_T_109 = mux(_popc_in_T_30, UInt<65>(0h2000000), _popc_in_T_108) node _popc_in_T_110 = mux(_popc_in_T_29, UInt<65>(0h1000000), _popc_in_T_109) node _popc_in_T_111 = mux(_popc_in_T_28, UInt<65>(0h800000), _popc_in_T_110) node _popc_in_T_112 = mux(_popc_in_T_27, UInt<65>(0h400000), _popc_in_T_111) node _popc_in_T_113 = mux(_popc_in_T_26, UInt<65>(0h200000), _popc_in_T_112) node _popc_in_T_114 = mux(_popc_in_T_25, UInt<65>(0h100000), _popc_in_T_113) node _popc_in_T_115 = mux(_popc_in_T_24, UInt<65>(0h80000), _popc_in_T_114) node _popc_in_T_116 = mux(_popc_in_T_23, UInt<65>(0h40000), _popc_in_T_115) node _popc_in_T_117 = mux(_popc_in_T_22, UInt<65>(0h20000), _popc_in_T_116) node _popc_in_T_118 = mux(_popc_in_T_21, UInt<65>(0h10000), _popc_in_T_117) node _popc_in_T_119 = mux(_popc_in_T_20, UInt<65>(0h8000), _popc_in_T_118) node _popc_in_T_120 = mux(_popc_in_T_19, UInt<65>(0h4000), _popc_in_T_119) node _popc_in_T_121 = mux(_popc_in_T_18, UInt<65>(0h2000), _popc_in_T_120) node _popc_in_T_122 = mux(_popc_in_T_17, UInt<65>(0h1000), _popc_in_T_121) node _popc_in_T_123 = mux(_popc_in_T_16, UInt<65>(0h800), _popc_in_T_122) node _popc_in_T_124 = mux(_popc_in_T_15, UInt<65>(0h400), _popc_in_T_123) node _popc_in_T_125 = mux(_popc_in_T_14, UInt<65>(0h200), _popc_in_T_124) node _popc_in_T_126 = mux(_popc_in_T_13, UInt<65>(0h100), _popc_in_T_125) node _popc_in_T_127 = mux(_popc_in_T_12, UInt<65>(0h80), _popc_in_T_126) node _popc_in_T_128 = mux(_popc_in_T_11, UInt<65>(0h40), _popc_in_T_127) node _popc_in_T_129 = mux(_popc_in_T_10, UInt<65>(0h20), _popc_in_T_128) node _popc_in_T_130 = mux(_popc_in_T_9, UInt<65>(0h10), _popc_in_T_129) node _popc_in_T_131 = mux(_popc_in_T_8, UInt<65>(0h8), _popc_in_T_130) node _popc_in_T_132 = mux(_popc_in_T_7, UInt<65>(0h4), _popc_in_T_131) node _popc_in_T_133 = mux(_popc_in_T_6, UInt<65>(0h2), _popc_in_T_132) node _popc_in_T_134 = mux(_popc_in_T_5, UInt<65>(0h1), _popc_in_T_133) node _popc_in_T_135 = sub(_popc_in_T_134, UInt<1>(0h1)) node _popc_in_T_136 = tail(_popc_in_T_135, 1) node _popc_in_T_137 = mux(_popc_in_T, _popc_in_T_3, _popc_in_T_136) node popc_in = bits(_popc_in_T_137, 63, 0) node _count_T = bits(popc_in, 0, 0) node _count_T_1 = bits(popc_in, 1, 1) node _count_T_2 = bits(popc_in, 2, 2) node _count_T_3 = bits(popc_in, 3, 3) node _count_T_4 = bits(popc_in, 4, 4) node _count_T_5 = bits(popc_in, 5, 5) node _count_T_6 = bits(popc_in, 6, 6) node _count_T_7 = bits(popc_in, 7, 7) node _count_T_8 = bits(popc_in, 8, 8) node _count_T_9 = bits(popc_in, 9, 9) node _count_T_10 = bits(popc_in, 10, 10) node _count_T_11 = bits(popc_in, 11, 11) node _count_T_12 = bits(popc_in, 12, 12) node _count_T_13 = bits(popc_in, 13, 13) node _count_T_14 = bits(popc_in, 14, 14) node _count_T_15 = bits(popc_in, 15, 15) node _count_T_16 = bits(popc_in, 16, 16) node _count_T_17 = bits(popc_in, 17, 17) node _count_T_18 = bits(popc_in, 18, 18) node _count_T_19 = bits(popc_in, 19, 19) node _count_T_20 = bits(popc_in, 20, 20) node _count_T_21 = bits(popc_in, 21, 21) node _count_T_22 = bits(popc_in, 22, 22) node _count_T_23 = bits(popc_in, 23, 23) node _count_T_24 = bits(popc_in, 24, 24) node _count_T_25 = bits(popc_in, 25, 25) node _count_T_26 = bits(popc_in, 26, 26) node _count_T_27 = bits(popc_in, 27, 27) node _count_T_28 = bits(popc_in, 28, 28) node _count_T_29 = bits(popc_in, 29, 29) node _count_T_30 = bits(popc_in, 30, 30) node _count_T_31 = bits(popc_in, 31, 31) node _count_T_32 = bits(popc_in, 32, 32) node _count_T_33 = bits(popc_in, 33, 33) node _count_T_34 = bits(popc_in, 34, 34) node _count_T_35 = bits(popc_in, 35, 35) node _count_T_36 = bits(popc_in, 36, 36) node _count_T_37 = bits(popc_in, 37, 37) node _count_T_38 = bits(popc_in, 38, 38) node _count_T_39 = bits(popc_in, 39, 39) node _count_T_40 = bits(popc_in, 40, 40) node _count_T_41 = bits(popc_in, 41, 41) node _count_T_42 = bits(popc_in, 42, 42) node _count_T_43 = bits(popc_in, 43, 43) node _count_T_44 = bits(popc_in, 44, 44) node _count_T_45 = bits(popc_in, 45, 45) node _count_T_46 = bits(popc_in, 46, 46) node _count_T_47 = bits(popc_in, 47, 47) node _count_T_48 = bits(popc_in, 48, 48) node _count_T_49 = bits(popc_in, 49, 49) node _count_T_50 = bits(popc_in, 50, 50) node _count_T_51 = bits(popc_in, 51, 51) node _count_T_52 = bits(popc_in, 52, 52) node _count_T_53 = bits(popc_in, 53, 53) node _count_T_54 = bits(popc_in, 54, 54) node _count_T_55 = bits(popc_in, 55, 55) node _count_T_56 = bits(popc_in, 56, 56) node _count_T_57 = bits(popc_in, 57, 57) node _count_T_58 = bits(popc_in, 58, 58) node _count_T_59 = bits(popc_in, 59, 59) node _count_T_60 = bits(popc_in, 60, 60) node _count_T_61 = bits(popc_in, 61, 61) node _count_T_62 = bits(popc_in, 62, 62) node _count_T_63 = bits(popc_in, 63, 63) node _count_T_64 = add(_count_T, _count_T_1) node _count_T_65 = bits(_count_T_64, 1, 0) node _count_T_66 = add(_count_T_2, _count_T_3) node _count_T_67 = bits(_count_T_66, 1, 0) node _count_T_68 = add(_count_T_65, _count_T_67) node _count_T_69 = bits(_count_T_68, 2, 0) node _count_T_70 = add(_count_T_4, _count_T_5) node _count_T_71 = bits(_count_T_70, 1, 0) node _count_T_72 = add(_count_T_6, _count_T_7) node _count_T_73 = bits(_count_T_72, 1, 0) node _count_T_74 = add(_count_T_71, _count_T_73) node _count_T_75 = bits(_count_T_74, 2, 0) node _count_T_76 = add(_count_T_69, _count_T_75) node _count_T_77 = bits(_count_T_76, 3, 0) node _count_T_78 = add(_count_T_8, _count_T_9) node _count_T_79 = bits(_count_T_78, 1, 0) node _count_T_80 = add(_count_T_10, _count_T_11) node _count_T_81 = bits(_count_T_80, 1, 0) node _count_T_82 = add(_count_T_79, _count_T_81) node _count_T_83 = bits(_count_T_82, 2, 0) node _count_T_84 = add(_count_T_12, _count_T_13) node _count_T_85 = bits(_count_T_84, 1, 0) node _count_T_86 = add(_count_T_14, _count_T_15) node _count_T_87 = bits(_count_T_86, 1, 0) node _count_T_88 = add(_count_T_85, _count_T_87) node _count_T_89 = bits(_count_T_88, 2, 0) node _count_T_90 = add(_count_T_83, _count_T_89) node _count_T_91 = bits(_count_T_90, 3, 0) node _count_T_92 = add(_count_T_77, _count_T_91) node _count_T_93 = bits(_count_T_92, 4, 0) node _count_T_94 = add(_count_T_16, _count_T_17) node _count_T_95 = bits(_count_T_94, 1, 0) node _count_T_96 = add(_count_T_18, _count_T_19) node _count_T_97 = bits(_count_T_96, 1, 0) node _count_T_98 = add(_count_T_95, _count_T_97) node _count_T_99 = bits(_count_T_98, 2, 0) node _count_T_100 = add(_count_T_20, _count_T_21) node _count_T_101 = bits(_count_T_100, 1, 0) node _count_T_102 = add(_count_T_22, _count_T_23) node _count_T_103 = bits(_count_T_102, 1, 0) node _count_T_104 = add(_count_T_101, _count_T_103) node _count_T_105 = bits(_count_T_104, 2, 0) node _count_T_106 = add(_count_T_99, _count_T_105) node _count_T_107 = bits(_count_T_106, 3, 0) node _count_T_108 = add(_count_T_24, _count_T_25) node _count_T_109 = bits(_count_T_108, 1, 0) node _count_T_110 = add(_count_T_26, _count_T_27) node _count_T_111 = bits(_count_T_110, 1, 0) node _count_T_112 = add(_count_T_109, _count_T_111) node _count_T_113 = bits(_count_T_112, 2, 0) node _count_T_114 = add(_count_T_28, _count_T_29) node _count_T_115 = bits(_count_T_114, 1, 0) node _count_T_116 = add(_count_T_30, _count_T_31) node _count_T_117 = bits(_count_T_116, 1, 0) node _count_T_118 = add(_count_T_115, _count_T_117) node _count_T_119 = bits(_count_T_118, 2, 0) node _count_T_120 = add(_count_T_113, _count_T_119) node _count_T_121 = bits(_count_T_120, 3, 0) node _count_T_122 = add(_count_T_107, _count_T_121) node _count_T_123 = bits(_count_T_122, 4, 0) node _count_T_124 = add(_count_T_93, _count_T_123) node _count_T_125 = bits(_count_T_124, 5, 0) node _count_T_126 = add(_count_T_32, _count_T_33) node _count_T_127 = bits(_count_T_126, 1, 0) node _count_T_128 = add(_count_T_34, _count_T_35) node _count_T_129 = bits(_count_T_128, 1, 0) node _count_T_130 = add(_count_T_127, _count_T_129) node _count_T_131 = bits(_count_T_130, 2, 0) node _count_T_132 = add(_count_T_36, _count_T_37) node _count_T_133 = bits(_count_T_132, 1, 0) node _count_T_134 = add(_count_T_38, _count_T_39) node _count_T_135 = bits(_count_T_134, 1, 0) node _count_T_136 = add(_count_T_133, _count_T_135) node _count_T_137 = bits(_count_T_136, 2, 0) node _count_T_138 = add(_count_T_131, _count_T_137) node _count_T_139 = bits(_count_T_138, 3, 0) node _count_T_140 = add(_count_T_40, _count_T_41) node _count_T_141 = bits(_count_T_140, 1, 0) node _count_T_142 = add(_count_T_42, _count_T_43) node _count_T_143 = bits(_count_T_142, 1, 0) node _count_T_144 = add(_count_T_141, _count_T_143) node _count_T_145 = bits(_count_T_144, 2, 0) node _count_T_146 = add(_count_T_44, _count_T_45) node _count_T_147 = bits(_count_T_146, 1, 0) node _count_T_148 = add(_count_T_46, _count_T_47) node _count_T_149 = bits(_count_T_148, 1, 0) node _count_T_150 = add(_count_T_147, _count_T_149) node _count_T_151 = bits(_count_T_150, 2, 0) node _count_T_152 = add(_count_T_145, _count_T_151) node _count_T_153 = bits(_count_T_152, 3, 0) node _count_T_154 = add(_count_T_139, _count_T_153) node _count_T_155 = bits(_count_T_154, 4, 0) node _count_T_156 = add(_count_T_48, _count_T_49) node _count_T_157 = bits(_count_T_156, 1, 0) node _count_T_158 = add(_count_T_50, _count_T_51) node _count_T_159 = bits(_count_T_158, 1, 0) node _count_T_160 = add(_count_T_157, _count_T_159) node _count_T_161 = bits(_count_T_160, 2, 0) node _count_T_162 = add(_count_T_52, _count_T_53) node _count_T_163 = bits(_count_T_162, 1, 0) node _count_T_164 = add(_count_T_54, _count_T_55) node _count_T_165 = bits(_count_T_164, 1, 0) node _count_T_166 = add(_count_T_163, _count_T_165) node _count_T_167 = bits(_count_T_166, 2, 0) node _count_T_168 = add(_count_T_161, _count_T_167) node _count_T_169 = bits(_count_T_168, 3, 0) node _count_T_170 = add(_count_T_56, _count_T_57) node _count_T_171 = bits(_count_T_170, 1, 0) node _count_T_172 = add(_count_T_58, _count_T_59) node _count_T_173 = bits(_count_T_172, 1, 0) node _count_T_174 = add(_count_T_171, _count_T_173) node _count_T_175 = bits(_count_T_174, 2, 0) node _count_T_176 = add(_count_T_60, _count_T_61) node _count_T_177 = bits(_count_T_176, 1, 0) node _count_T_178 = add(_count_T_62, _count_T_63) node _count_T_179 = bits(_count_T_178, 1, 0) node _count_T_180 = add(_count_T_177, _count_T_179) node _count_T_181 = bits(_count_T_180, 2, 0) node _count_T_182 = add(_count_T_175, _count_T_181) node _count_T_183 = bits(_count_T_182, 3, 0) node _count_T_184 = add(_count_T_169, _count_T_183) node _count_T_185 = bits(_count_T_184, 4, 0) node _count_T_186 = add(_count_T_155, _count_T_185) node _count_T_187 = bits(_count_T_186, 5, 0) node _count_T_188 = add(_count_T_125, _count_T_187) node count = bits(_count_T_188, 6, 0) wire in1_bytes : UInt<8>[8] wire _in1_bytes_WIRE : UInt<64> connect _in1_bytes_WIRE, io.in1 node _in1_bytes_T = bits(_in1_bytes_WIRE, 7, 0) connect in1_bytes[0], _in1_bytes_T node _in1_bytes_T_1 = bits(_in1_bytes_WIRE, 15, 8) connect in1_bytes[1], _in1_bytes_T_1 node _in1_bytes_T_2 = bits(_in1_bytes_WIRE, 23, 16) connect in1_bytes[2], _in1_bytes_T_2 node _in1_bytes_T_3 = bits(_in1_bytes_WIRE, 31, 24) connect in1_bytes[3], _in1_bytes_T_3 node _in1_bytes_T_4 = bits(_in1_bytes_WIRE, 39, 32) connect in1_bytes[4], _in1_bytes_T_4 node _in1_bytes_T_5 = bits(_in1_bytes_WIRE, 47, 40) connect in1_bytes[5], _in1_bytes_T_5 node _in1_bytes_T_6 = bits(_in1_bytes_WIRE, 55, 48) connect in1_bytes[6], _in1_bytes_T_6 node _in1_bytes_T_7 = bits(_in1_bytes_WIRE, 63, 56) connect in1_bytes[7], _in1_bytes_T_7 node _orcb_T = neq(in1_bytes[0], UInt<1>(0h0)) node _orcb_T_1 = mux(_orcb_T, UInt<8>(0hff), UInt<8>(0h0)) node _orcb_T_2 = neq(in1_bytes[1], UInt<1>(0h0)) node _orcb_T_3 = mux(_orcb_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _orcb_T_4 = neq(in1_bytes[2], UInt<1>(0h0)) node _orcb_T_5 = mux(_orcb_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _orcb_T_6 = neq(in1_bytes[3], UInt<1>(0h0)) node _orcb_T_7 = mux(_orcb_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _orcb_T_8 = neq(in1_bytes[4], UInt<1>(0h0)) node _orcb_T_9 = mux(_orcb_T_8, UInt<8>(0hff), UInt<8>(0h0)) node _orcb_T_10 = neq(in1_bytes[5], UInt<1>(0h0)) node _orcb_T_11 = mux(_orcb_T_10, UInt<8>(0hff), UInt<8>(0h0)) node _orcb_T_12 = neq(in1_bytes[6], UInt<1>(0h0)) node _orcb_T_13 = mux(_orcb_T_12, UInt<8>(0hff), UInt<8>(0h0)) node _orcb_T_14 = neq(in1_bytes[7], UInt<1>(0h0)) node _orcb_T_15 = mux(_orcb_T_14, UInt<8>(0hff), UInt<8>(0h0)) wire _orcb_WIRE : UInt<8>[8] connect _orcb_WIRE[0], _orcb_T_1 connect _orcb_WIRE[1], _orcb_T_3 connect _orcb_WIRE[2], _orcb_T_5 connect _orcb_WIRE[3], _orcb_T_7 connect _orcb_WIRE[4], _orcb_T_9 connect _orcb_WIRE[5], _orcb_T_11 connect _orcb_WIRE[6], _orcb_T_13 connect _orcb_WIRE[7], _orcb_T_15 node orcb_lo_lo = cat(_orcb_WIRE[1], _orcb_WIRE[0]) node orcb_lo_hi = cat(_orcb_WIRE[3], _orcb_WIRE[2]) node orcb_lo = cat(orcb_lo_hi, orcb_lo_lo) node orcb_hi_lo = cat(_orcb_WIRE[5], _orcb_WIRE[4]) node orcb_hi_hi = cat(_orcb_WIRE[7], _orcb_WIRE[6]) node orcb_hi = cat(orcb_hi_hi, orcb_hi_lo) node orcb = cat(orcb_hi, orcb_lo) wire _rev8_WIRE : UInt<8>[8] connect _rev8_WIRE[0], in1_bytes[7] connect _rev8_WIRE[1], in1_bytes[6] connect _rev8_WIRE[2], in1_bytes[5] connect _rev8_WIRE[3], in1_bytes[4] connect _rev8_WIRE[4], in1_bytes[3] connect _rev8_WIRE[5], in1_bytes[2] connect _rev8_WIRE[6], in1_bytes[1] connect _rev8_WIRE[7], in1_bytes[0] node rev8_lo_lo = cat(_rev8_WIRE[1], _rev8_WIRE[0]) node rev8_lo_hi = cat(_rev8_WIRE[3], _rev8_WIRE[2]) node rev8_lo = cat(rev8_lo_hi, rev8_lo_lo) node rev8_hi_lo = cat(_rev8_WIRE[5], _rev8_WIRE[4]) node rev8_hi_hi = cat(_rev8_WIRE[7], _rev8_WIRE[6]) node rev8_hi = cat(rev8_hi_hi, rev8_hi_lo) node rev8 = cat(rev8_hi, rev8_lo) node _unary_T = bits(io.in2, 11, 0) node _unary_T_1 = bits(io.in1, 15, 0) node _unary_T_2 = bits(io.in1, 7, 7) node _unary_T_3 = mux(_unary_T_2, UInt<56>(0hffffffffffffff), UInt<56>(0h0)) node _unary_T_4 = bits(io.in1, 7, 0) node _unary_T_5 = cat(_unary_T_3, _unary_T_4) node _unary_T_6 = bits(io.in1, 15, 15) node _unary_T_7 = mux(_unary_T_6, UInt<48>(0hffffffffffff), UInt<48>(0h0)) node _unary_T_8 = bits(io.in1, 15, 0) node _unary_T_9 = cat(_unary_T_7, _unary_T_8) node _unary_T_10 = eq(UInt<10>(0h287), _unary_T) node _unary_T_11 = mux(_unary_T_10, orcb, count) node _unary_T_12 = eq(UInt<11>(0h6b8), _unary_T) node _unary_T_13 = mux(_unary_T_12, rev8, _unary_T_11) node _unary_T_14 = eq(UInt<8>(0h80), _unary_T) node _unary_T_15 = mux(_unary_T_14, _unary_T_1, _unary_T_13) node _unary_T_16 = eq(UInt<11>(0h604), _unary_T) node _unary_T_17 = mux(_unary_T_16, _unary_T_5, _unary_T_15) node _unary_T_18 = eq(UInt<11>(0h605), _unary_T) node unary = mux(_unary_T_18, _unary_T_9, _unary_T_17) node maxmin_out = mux(io.cmp_out, io.in2, io.in1) node _rot_shamt_T = eq(io.dw, UInt<1>(0h0)) node _rot_shamt_T_1 = mux(_rot_shamt_T, UInt<6>(0h20), UInt<7>(0h40)) node _rot_shamt_T_2 = sub(_rot_shamt_T_1, shamt) node rot_shamt = tail(_rot_shamt_T_2, 1) node _rotin_T = bits(io.fn, 0, 0) node _rotin_T_1 = shl(UInt<32>(0hffffffff), 32) node _rotin_T_2 = xor(UInt<64>(0hffffffffffffffff), _rotin_T_1) node _rotin_T_3 = shr(shin_r, 32) node _rotin_T_4 = and(_rotin_T_3, _rotin_T_2) node _rotin_T_5 = bits(shin_r, 31, 0) node _rotin_T_6 = shl(_rotin_T_5, 32) node _rotin_T_7 = not(_rotin_T_2) node _rotin_T_8 = and(_rotin_T_6, _rotin_T_7) node _rotin_T_9 = or(_rotin_T_4, _rotin_T_8) node _rotin_T_10 = bits(_rotin_T_2, 47, 0) node _rotin_T_11 = shl(_rotin_T_10, 16) node _rotin_T_12 = xor(_rotin_T_2, _rotin_T_11) node _rotin_T_13 = shr(_rotin_T_9, 16) node _rotin_T_14 = and(_rotin_T_13, _rotin_T_12) node _rotin_T_15 = bits(_rotin_T_9, 47, 0) node _rotin_T_16 = shl(_rotin_T_15, 16) node _rotin_T_17 = not(_rotin_T_12) node _rotin_T_18 = and(_rotin_T_16, _rotin_T_17) node _rotin_T_19 = or(_rotin_T_14, _rotin_T_18) node _rotin_T_20 = bits(_rotin_T_12, 55, 0) node _rotin_T_21 = shl(_rotin_T_20, 8) node _rotin_T_22 = xor(_rotin_T_12, _rotin_T_21) node _rotin_T_23 = shr(_rotin_T_19, 8) node _rotin_T_24 = and(_rotin_T_23, _rotin_T_22) node _rotin_T_25 = bits(_rotin_T_19, 55, 0) node _rotin_T_26 = shl(_rotin_T_25, 8) node _rotin_T_27 = not(_rotin_T_22) node _rotin_T_28 = and(_rotin_T_26, _rotin_T_27) node _rotin_T_29 = or(_rotin_T_24, _rotin_T_28) node _rotin_T_30 = bits(_rotin_T_22, 59, 0) node _rotin_T_31 = shl(_rotin_T_30, 4) node _rotin_T_32 = xor(_rotin_T_22, _rotin_T_31) node _rotin_T_33 = shr(_rotin_T_29, 4) node _rotin_T_34 = and(_rotin_T_33, _rotin_T_32) node _rotin_T_35 = bits(_rotin_T_29, 59, 0) node _rotin_T_36 = shl(_rotin_T_35, 4) node _rotin_T_37 = not(_rotin_T_32) node _rotin_T_38 = and(_rotin_T_36, _rotin_T_37) node _rotin_T_39 = or(_rotin_T_34, _rotin_T_38) node _rotin_T_40 = bits(_rotin_T_32, 61, 0) node _rotin_T_41 = shl(_rotin_T_40, 2) node _rotin_T_42 = xor(_rotin_T_32, _rotin_T_41) node _rotin_T_43 = shr(_rotin_T_39, 2) node _rotin_T_44 = and(_rotin_T_43, _rotin_T_42) node _rotin_T_45 = bits(_rotin_T_39, 61, 0) node _rotin_T_46 = shl(_rotin_T_45, 2) node _rotin_T_47 = not(_rotin_T_42) node _rotin_T_48 = and(_rotin_T_46, _rotin_T_47) node _rotin_T_49 = or(_rotin_T_44, _rotin_T_48) node _rotin_T_50 = bits(_rotin_T_42, 62, 0) node _rotin_T_51 = shl(_rotin_T_50, 1) node _rotin_T_52 = xor(_rotin_T_42, _rotin_T_51) node _rotin_T_53 = shr(_rotin_T_49, 1) node _rotin_T_54 = and(_rotin_T_53, _rotin_T_52) node _rotin_T_55 = bits(_rotin_T_49, 62, 0) node _rotin_T_56 = shl(_rotin_T_55, 1) node _rotin_T_57 = not(_rotin_T_52) node _rotin_T_58 = and(_rotin_T_56, _rotin_T_57) node _rotin_T_59 = or(_rotin_T_54, _rotin_T_58) node rotin = mux(_rotin_T, shin_r, _rotin_T_59) node _rotout_r_T = dshr(rotin, rot_shamt) node rotout_r = bits(_rotout_r_T, 63, 0) node _rotout_l_T = shl(UInt<32>(0hffffffff), 32) node _rotout_l_T_1 = xor(UInt<64>(0hffffffffffffffff), _rotout_l_T) node _rotout_l_T_2 = shr(rotout_r, 32) node _rotout_l_T_3 = and(_rotout_l_T_2, _rotout_l_T_1) node _rotout_l_T_4 = bits(rotout_r, 31, 0) node _rotout_l_T_5 = shl(_rotout_l_T_4, 32) node _rotout_l_T_6 = not(_rotout_l_T_1) node _rotout_l_T_7 = and(_rotout_l_T_5, _rotout_l_T_6) node _rotout_l_T_8 = or(_rotout_l_T_3, _rotout_l_T_7) node _rotout_l_T_9 = bits(_rotout_l_T_1, 47, 0) node _rotout_l_T_10 = shl(_rotout_l_T_9, 16) node _rotout_l_T_11 = xor(_rotout_l_T_1, _rotout_l_T_10) node _rotout_l_T_12 = shr(_rotout_l_T_8, 16) node _rotout_l_T_13 = and(_rotout_l_T_12, _rotout_l_T_11) node _rotout_l_T_14 = bits(_rotout_l_T_8, 47, 0) node _rotout_l_T_15 = shl(_rotout_l_T_14, 16) node _rotout_l_T_16 = not(_rotout_l_T_11) node _rotout_l_T_17 = and(_rotout_l_T_15, _rotout_l_T_16) node _rotout_l_T_18 = or(_rotout_l_T_13, _rotout_l_T_17) node _rotout_l_T_19 = bits(_rotout_l_T_11, 55, 0) node _rotout_l_T_20 = shl(_rotout_l_T_19, 8) node _rotout_l_T_21 = xor(_rotout_l_T_11, _rotout_l_T_20) node _rotout_l_T_22 = shr(_rotout_l_T_18, 8) node _rotout_l_T_23 = and(_rotout_l_T_22, _rotout_l_T_21) node _rotout_l_T_24 = bits(_rotout_l_T_18, 55, 0) node _rotout_l_T_25 = shl(_rotout_l_T_24, 8) node _rotout_l_T_26 = not(_rotout_l_T_21) node _rotout_l_T_27 = and(_rotout_l_T_25, _rotout_l_T_26) node _rotout_l_T_28 = or(_rotout_l_T_23, _rotout_l_T_27) node _rotout_l_T_29 = bits(_rotout_l_T_21, 59, 0) node _rotout_l_T_30 = shl(_rotout_l_T_29, 4) node _rotout_l_T_31 = xor(_rotout_l_T_21, _rotout_l_T_30) node _rotout_l_T_32 = shr(_rotout_l_T_28, 4) node _rotout_l_T_33 = and(_rotout_l_T_32, _rotout_l_T_31) node _rotout_l_T_34 = bits(_rotout_l_T_28, 59, 0) node _rotout_l_T_35 = shl(_rotout_l_T_34, 4) node _rotout_l_T_36 = not(_rotout_l_T_31) node _rotout_l_T_37 = and(_rotout_l_T_35, _rotout_l_T_36) node _rotout_l_T_38 = or(_rotout_l_T_33, _rotout_l_T_37) node _rotout_l_T_39 = bits(_rotout_l_T_31, 61, 0) node _rotout_l_T_40 = shl(_rotout_l_T_39, 2) node _rotout_l_T_41 = xor(_rotout_l_T_31, _rotout_l_T_40) node _rotout_l_T_42 = shr(_rotout_l_T_38, 2) node _rotout_l_T_43 = and(_rotout_l_T_42, _rotout_l_T_41) node _rotout_l_T_44 = bits(_rotout_l_T_38, 61, 0) node _rotout_l_T_45 = shl(_rotout_l_T_44, 2) node _rotout_l_T_46 = not(_rotout_l_T_41) node _rotout_l_T_47 = and(_rotout_l_T_45, _rotout_l_T_46) node _rotout_l_T_48 = or(_rotout_l_T_43, _rotout_l_T_47) node _rotout_l_T_49 = bits(_rotout_l_T_41, 62, 0) node _rotout_l_T_50 = shl(_rotout_l_T_49, 1) node _rotout_l_T_51 = xor(_rotout_l_T_41, _rotout_l_T_50) node _rotout_l_T_52 = shr(_rotout_l_T_48, 1) node _rotout_l_T_53 = and(_rotout_l_T_52, _rotout_l_T_51) node _rotout_l_T_54 = bits(_rotout_l_T_48, 62, 0) node _rotout_l_T_55 = shl(_rotout_l_T_54, 1) node _rotout_l_T_56 = not(_rotout_l_T_51) node _rotout_l_T_57 = and(_rotout_l_T_55, _rotout_l_T_56) node rotout_l = or(_rotout_l_T_53, _rotout_l_T_57) node _rotout_T = bits(io.fn, 0, 0) node _rotout_T_1 = mux(_rotout_T, rotout_r, rotout_l) node _rotout_T_2 = bits(io.fn, 0, 0) node _rotout_T_3 = mux(_rotout_T_2, shout_l, shout_r) node rotout = or(_rotout_T_1, _rotout_T_3) node _out_T = eq(UInt<1>(0h0), io.fn) node _out_T_1 = mux(_out_T, io.adder_out, shift_logic) node _out_T_2 = eq(UInt<4>(0ha), io.fn) node _out_T_3 = mux(_out_T_2, io.adder_out, _out_T_1) node _out_T_4 = eq(UInt<5>(0h10), io.fn) node _out_T_5 = mux(_out_T_4, unary, _out_T_3) node _out_T_6 = eq(UInt<5>(0h1c), io.fn) node _out_T_7 = mux(_out_T_6, maxmin_out, _out_T_5) node _out_T_8 = eq(UInt<5>(0h1d), io.fn) node _out_T_9 = mux(_out_T_8, maxmin_out, _out_T_7) node _out_T_10 = eq(UInt<5>(0h1e), io.fn) node _out_T_11 = mux(_out_T_10, maxmin_out, _out_T_9) node _out_T_12 = eq(UInt<5>(0h1f), io.fn) node _out_T_13 = mux(_out_T_12, maxmin_out, _out_T_11) node _out_T_14 = eq(UInt<5>(0h11), io.fn) node _out_T_15 = mux(_out_T_14, rotout, _out_T_13) node _out_T_16 = eq(UInt<5>(0h12), io.fn) node out = mux(_out_T_16, rotout, _out_T_15) connect io.out, out node _T_1 = eq(io.dw, UInt<1>(0h0)) when _T_1 : node _io_out_T = bits(out, 31, 31) node _io_out_T_1 = mux(_io_out_T, UInt<32>(0hffffffff), UInt<32>(0h0)) node _io_out_T_2 = bits(out, 31, 0) node _io_out_T_3 = cat(_io_out_T_1, _io_out_T_2) connect io.out, _io_out_T_3	module ALU_5( // @[ALU.scala:83:7] input clock, // @[ALU.scala:83:7] input reset, // @[ALU.scala:83:7] input io_dw, // @[ALU.scala:72:14] input [4:0] io_fn, // @[ALU.scala:72:14] input [63:0] io_in2, // @[ALU.scala:72:14] input [63:0] io_in1, // @[ALU.scala:72:14] output [63:0] io_out, // @[ALU.scala:72:14] output [63:0] io_adder_out, // @[ALU.scala:72:14] output io_cmp_out // @[ALU.scala:72:14] ); wire [7:0] in1_bytes_6; // @[ALU.scala:140:34] wire [7:0] in1_bytes_5; // @[ALU.scala:140:34] wire [7:0] in1_bytes_4; // @[ALU.scala:140:34] wire [7:0] in1_bytes_3; // @[ALU.scala:140:34] wire [7:0] in1_bytes_2; // @[ALU.scala:140:34] wire [7:0] in1_bytes_1; // @[ALU.scala:140:34] wire [7:0] in1_bytes_0; // @[ALU.scala:140:34] wire io_dw_0 = io_dw; // @[ALU.scala:83:7] wire [4:0] io_fn_0 = io_fn; // @[ALU.scala:83:7] wire [63:0] io_in2_0 = io_in2; // @[ALU.scala:83:7] wire [63:0] io_in1_0 = io_in1; // @[ALU.scala:83:7] wire [63:0] _bext_mask_T_2 = 64'hFFFFFFFFFFFFFFFF; // @[ALU.scala:122:70] wire [31:0] _tz_in_T_67 = 32'hFFFF; // @[ALU.scala:134:26] wire [31:0] _tz_in_T_66 = 32'hFFFF0000; // @[ALU.scala:134:26] wire [31:0] _tz_in_T_72 = 32'hFFFF0000; // @[ALU.scala:134:26] wire [23:0] _tz_in_T_75 = 24'hFFFF; // @[ALU.scala:134:26] wire [31:0] _tz_in_T_76 = 32'hFFFF00; // @[ALU.scala:134:26] wire [31:0] _tz_in_T_77 = 32'hFF00FF; // @[ALU.scala:134:26] wire [31:0] _tz_in_T_82 = 32'hFF00FF00; // @[ALU.scala:134:26] wire [27:0] _tz_in_T_85 = 28'hFF00FF; // @[ALU.scala:134:26] wire [31:0] _tz_in_T_86 = 32'hFF00FF0; // @[ALU.scala:134:26] wire [31:0] _tz_in_T_87 = 32'hF0F0F0F; // @[ALU.scala:134:26] wire [31:0] _tz_in_T_92 = 32'hF0F0F0F0; // @[ALU.scala:134:26] wire [29:0] _tz_in_T_95 = 30'hF0F0F0F; // @[ALU.scala:134:26] wire [31:0] _tz_in_T_96 = 32'h3C3C3C3C; // @[ALU.scala:134:26] wire [31:0] _tz_in_T_97 = 32'h33333333; // @[ALU.scala:134:26] wire [31:0] _tz_in_T_102 = 32'hCCCCCCCC; // @[ALU.scala:134:26] wire [30:0] _tz_in_T_105 = 31'h33333333; // @[ALU.scala:134:26] wire [31:0] _tz_in_T_106 = 32'h66666666; // @[ALU.scala:134:26] wire [31:0] _tz_in_T_107 = 32'h55555555; // @[ALU.scala:134:26] wire [31:0] _tz_in_T_112 = 32'hAAAAAAAA; // @[ALU.scala:134:26] wire [63:0] _shin_T_9 = 64'hFFFFFFFF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _shout_l_T_1 = 64'hFFFFFFFF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _tz_in_T_5 = 64'hFFFFFFFF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _rotin_T_2 = 64'hFFFFFFFF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _rotout_l_T_1 = 64'hFFFFFFFF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _shin_T_8 = 64'hFFFFFFFF00000000; // @[ALU.scala:106:46] wire [63:0] _shin_T_14 = 64'hFFFFFFFF00000000; // @[ALU.scala:106:46] wire [63:0] _shout_l_T = 64'hFFFFFFFF00000000; // @[ALU.scala:108:24] wire [63:0] _shout_l_T_6 = 64'hFFFFFFFF00000000; // @[ALU.scala:108:24] wire [63:0] _tz_in_T_4 = 64'hFFFFFFFF00000000; // @[ALU.scala:132:19] wire [63:0] _tz_in_T_10 = 64'hFFFFFFFF00000000; // @[ALU.scala:132:19] wire [63:0] _rotin_T_1 = 64'hFFFFFFFF00000000; // @[ALU.scala:156:44] wire [63:0] _rotin_T_7 = 64'hFFFFFFFF00000000; // @[ALU.scala:156:44] wire [63:0] _rotout_l_T = 64'hFFFFFFFF00000000; // @[ALU.scala:158:25] wire [63:0] _rotout_l_T_6 = 64'hFFFFFFFF00000000; // @[ALU.scala:158:25] wire [47:0] _shin_T_17 = 48'hFFFFFFFF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [47:0] _shout_l_T_9 = 48'hFFFFFFFF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [47:0] _tz_in_T_13 = 48'hFFFFFFFF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [47:0] _rotin_T_10 = 48'hFFFFFFFF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [47:0] _rotout_l_T_9 = 48'hFFFFFFFF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _shin_T_18 = 64'hFFFFFFFF0000; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _shout_l_T_10 = 64'hFFFFFFFF0000; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _tz_in_T_14 = 64'hFFFFFFFF0000; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _rotin_T_11 = 64'hFFFFFFFF0000; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _rotout_l_T_10 = 64'hFFFFFFFF0000; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _shin_T_19 = 64'hFFFF0000FFFF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _shout_l_T_11 = 64'hFFFF0000FFFF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _tz_in_T_15 = 64'hFFFF0000FFFF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _rotin_T_12 = 64'hFFFF0000FFFF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _rotout_l_T_11 = 64'hFFFF0000FFFF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _shin_T_24 = 64'hFFFF0000FFFF0000; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _shout_l_T_16 = 64'hFFFF0000FFFF0000; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _tz_in_T_20 = 64'hFFFF0000FFFF0000; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _rotin_T_17 = 64'hFFFF0000FFFF0000; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _rotout_l_T_16 = 64'hFFFF0000FFFF0000; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [55:0] _shin_T_27 = 56'hFFFF0000FFFF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [55:0] _shout_l_T_19 = 56'hFFFF0000FFFF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [55:0] _tz_in_T_23 = 56'hFFFF0000FFFF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [55:0] _rotin_T_20 = 56'hFFFF0000FFFF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [55:0] _rotout_l_T_19 = 56'hFFFF0000FFFF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _shin_T_28 = 64'hFFFF0000FFFF00; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _shout_l_T_20 = 64'hFFFF0000FFFF00; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _tz_in_T_24 = 64'hFFFF0000FFFF00; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _rotin_T_21 = 64'hFFFF0000FFFF00; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _rotout_l_T_20 = 64'hFFFF0000FFFF00; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _shin_T_29 = 64'hFF00FF00FF00FF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _shout_l_T_21 = 64'hFF00FF00FF00FF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _tz_in_T_25 = 64'hFF00FF00FF00FF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _rotin_T_22 = 64'hFF00FF00FF00FF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _rotout_l_T_21 = 64'hFF00FF00FF00FF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _shin_T_34 = 64'hFF00FF00FF00FF00; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _shout_l_T_26 = 64'hFF00FF00FF00FF00; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _tz_in_T_30 = 64'hFF00FF00FF00FF00; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _rotin_T_27 = 64'hFF00FF00FF00FF00; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _rotout_l_T_26 = 64'hFF00FF00FF00FF00; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [59:0] _shin_T_37 = 60'hFF00FF00FF00FF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [59:0] _shout_l_T_29 = 60'hFF00FF00FF00FF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [59:0] _tz_in_T_33 = 60'hFF00FF00FF00FF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [59:0] _rotin_T_30 = 60'hFF00FF00FF00FF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [59:0] _rotout_l_T_29 = 60'hFF00FF00FF00FF; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _shin_T_38 = 64'hFF00FF00FF00FF0; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _shout_l_T_30 = 64'hFF00FF00FF00FF0; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _tz_in_T_34 = 64'hFF00FF00FF00FF0; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _rotin_T_31 = 64'hFF00FF00FF00FF0; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _rotout_l_T_30 = 64'hFF00FF00FF00FF0; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _shin_T_39 = 64'hF0F0F0F0F0F0F0F; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _shout_l_T_31 = 64'hF0F0F0F0F0F0F0F; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _tz_in_T_35 = 64'hF0F0F0F0F0F0F0F; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _rotin_T_32 = 64'hF0F0F0F0F0F0F0F; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _rotout_l_T_31 = 64'hF0F0F0F0F0F0F0F; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _shin_T_44 = 64'hF0F0F0F0F0F0F0F0; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _shout_l_T_36 = 64'hF0F0F0F0F0F0F0F0; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _tz_in_T_40 = 64'hF0F0F0F0F0F0F0F0; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _rotin_T_37 = 64'hF0F0F0F0F0F0F0F0; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _rotout_l_T_36 = 64'hF0F0F0F0F0F0F0F0; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [61:0] _shin_T_47 = 62'hF0F0F0F0F0F0F0F; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [61:0] _shout_l_T_39 = 62'hF0F0F0F0F0F0F0F; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [61:0] _tz_in_T_43 = 62'hF0F0F0F0F0F0F0F; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [61:0] _rotin_T_40 = 62'hF0F0F0F0F0F0F0F; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [61:0] _rotout_l_T_39 = 62'hF0F0F0F0F0F0F0F; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _shin_T_48 = 64'h3C3C3C3C3C3C3C3C; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _shout_l_T_40 = 64'h3C3C3C3C3C3C3C3C; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _tz_in_T_44 = 64'h3C3C3C3C3C3C3C3C; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _rotin_T_41 = 64'h3C3C3C3C3C3C3C3C; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _rotout_l_T_40 = 64'h3C3C3C3C3C3C3C3C; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _shin_T_49 = 64'h3333333333333333; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _shout_l_T_41 = 64'h3333333333333333; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _tz_in_T_45 = 64'h3333333333333333; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _rotin_T_42 = 64'h3333333333333333; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _rotout_l_T_41 = 64'h3333333333333333; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _shin_T_54 = 64'hCCCCCCCCCCCCCCCC; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _shout_l_T_46 = 64'hCCCCCCCCCCCCCCCC; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _tz_in_T_50 = 64'hCCCCCCCCCCCCCCCC; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _rotin_T_47 = 64'hCCCCCCCCCCCCCCCC; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _rotout_l_T_46 = 64'hCCCCCCCCCCCCCCCC; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [62:0] _shin_T_57 = 63'h3333333333333333; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [62:0] _shout_l_T_49 = 63'h3333333333333333; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [62:0] _tz_in_T_53 = 63'h3333333333333333; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [62:0] _rotin_T_50 = 63'h3333333333333333; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [62:0] _rotout_l_T_49 = 63'h3333333333333333; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _shin_T_58 = 64'h6666666666666666; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _shout_l_T_50 = 64'h6666666666666666; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _tz_in_T_54 = 64'h6666666666666666; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _rotin_T_51 = 64'h6666666666666666; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _rotout_l_T_50 = 64'h6666666666666666; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _shin_T_59 = 64'h5555555555555555; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _shout_l_T_51 = 64'h5555555555555555; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _tz_in_T_55 = 64'h5555555555555555; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _rotin_T_52 = 64'h5555555555555555; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _rotout_l_T_51 = 64'h5555555555555555; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _shin_T_64 = 64'hAAAAAAAAAAAAAAAA; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _shout_l_T_56 = 64'hAAAAAAAAAAAAAAAA; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _tz_in_T_60 = 64'hAAAAAAAAAAAAAAAA; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _rotin_T_57 = 64'hAAAAAAAAAAAAAAAA; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _rotout_l_T_56 = 64'hAAAAAAAAAAAAAAAA; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire _shin_hi_T = io_dw_0; // @[ALU.scala:83:7, :102:31] wire _shamt_T_1 = io_dw_0; // @[ALU.scala:83:7, :103:42] wire [63:0] _in1_bytes_WIRE = io_in1_0; // @[ALU.scala:83:7, :140:34] wire [63:0] _io_adder_out_T_4; // @[ALU.scala:88:36] wire _io_cmp_out_T_5; // @[ALU.scala:94:36] wire [63:0] io_out_0; // @[ALU.scala:83:7] wire [63:0] io_adder_out_0; // @[ALU.scala:83:7] wire io_cmp_out_0; // @[ALU.scala:83:7] wire _in2_inv_T = io_fn_0[3]; // @[ALU.scala:58:29, :83:7] wire _io_adder_out_T_2 = io_fn_0[3]; // @[ALU.scala:58:29, :83:7] wire _io_cmp_out_T_1 = io_fn_0[3]; // @[ALU.scala:58:29, :63:30, :83:7] wire _shin_hi_32_T = io_fn_0[3]; // @[ALU.scala:58:29, :83:7] wire _shout_r_T = io_fn_0[3]; // @[ALU.scala:58:29, :83:7] wire [63:0] _in2_inv_T_1 = ~io_in2_0; // @[ALU.scala:83:7, :85:35] wire [63:0] in2_inv = _in2_inv_T ? _in2_inv_T_1 : io_in2_0; // @[ALU.scala:58:29, :83:7, :85:{20,35}] wire [63:0] in1_xor_in2 = io_in1_0 ^ in2_inv; // @[ALU.scala:83:7, :85:20, :86:28] wire [63:0] in1_and_in2 = io_in1_0 & in2_inv; // @[ALU.scala:83:7, :85:20, :87:28] wire [64:0] _io_adder_out_T = {1'h0, io_in1_0} + {1'h0, in2_inv}; // @[ALU.scala:83:7, :85:20, :88:26] wire [63:0] _io_adder_out_T_1 = _io_adder_out_T[63:0]; // @[ALU.scala:88:26] wire [64:0] _io_adder_out_T_3 = {1'h0, _io_adder_out_T_1} + {64'h0, _io_adder_out_T_2}; // @[ALU.scala:58:29, :88:{26,36}] assign _io_adder_out_T_4 = _io_adder_out_T_3[63:0]; // @[ALU.scala:88:36] assign io_adder_out_0 = _io_adder_out_T_4; // @[ALU.scala:83:7, :88:36] wire _slt_T = io_in1_0[63]; // @[ALU.scala:83:7, :92:15] wire _slt_T_6 = io_in1_0[63]; // @[ALU.scala:83:7, :92:15, :93:51] wire _slt_T_1 = io_in2_0[63]; // @[ALU.scala:83:7, :92:34] wire _slt_T_5 = io_in2_0[63]; // @[ALU.scala:83:7, :92:34, :93:35] wire _slt_T_2 = _slt_T == _slt_T_1; // @[ALU.scala:92:{15,24,34}] wire _slt_T_3 = io_adder_out_0[63]; // @[ALU.scala:83:7, :92:56] wire _slt_T_4 = io_fn_0[1]; // @[ALU.scala:61:35, :83:7] wire _slt_T_7 = _slt_T_4 ? _slt_T_5 : _slt_T_6; // @[ALU.scala:61:35, :93:{8,35,51}] wire slt = _slt_T_2 ? _slt_T_3 : _slt_T_7; // @[ALU.scala:92:{8,24,56}, :93:8] wire _io_cmp_out_T = io_fn_0[0]; // @[ALU.scala:62:35, :83:7] wire _rotin_T = io_fn_0[0]; // @[ALU.scala:62:35, :83:7, :156:24] wire _rotout_T = io_fn_0[0]; // @[ALU.scala:62:35, :83:7, :159:25] wire _rotout_T_2 = io_fn_0[0]; // @[ALU.scala:62:35, :83:7, :159:61] wire _io_cmp_out_T_2 = ~_io_cmp_out_T_1; // @[ALU.scala:63:{26,30}] wire _io_cmp_out_T_3 = in1_xor_in2 == 64'h0; // @[ALU.scala:86:28, :94:68] wire _io_cmp_out_T_4 = _io_cmp_out_T_2 ? _io_cmp_out_T_3 : slt; // @[ALU.scala:63:26, :92:8, :94:{41,68}] assign _io_cmp_out_T_5 = _io_cmp_out_T ^ _io_cmp_out_T_4; // @[ALU.scala:62:35, :94:{36,41}] assign io_cmp_out_0 = _io_cmp_out_T_5; // @[ALU.scala:83:7, :94:36] wire _shin_hi_32_T_1 = io_in1_0[31]; // @[ALU.scala:83:7, :101:55] wire _shin_hi_32_T_2 = _shin_hi_32_T & _shin_hi_32_T_1; // @[ALU.scala:58:29, :101:{46,55}] wire [31:0] shin_hi_32 = {32{_shin_hi_32_T_2}}; // @[ALU.scala:101:{28,46}] wire [31:0] _shin_hi_T_1 = io_in1_0[63:32]; // @[ALU.scala:83:7, :102:48] wire [31:0] _tz_in_T_6 = io_in1_0[63:32]; // @[ALU.scala:83:7, :102:48, :132:19] wire [31:0] shin_hi = _shin_hi_T ? _shin_hi_T_1 : shin_hi_32; // @[ALU.scala:101:28, :102:{24,31,48}] wire _shamt_T = io_in2_0[5]; // @[ALU.scala:83:7, :103:29] wire _shamt_T_2 = _shamt_T & _shamt_T_1; // @[ALU.scala:103:{29,33,42}] wire [4:0] _shamt_T_3 = io_in2_0[4:0]; // @[ALU.scala:83:7, :103:60] wire [5:0] shamt = {_shamt_T_2, _shamt_T_3}; // @[ALU.scala:103:{22,33,60}] wire [31:0] _tz_in_T_8 = io_in1_0[31:0]; // @[ALU.scala:83:7, :104:34, :132:19] wire [31:0] _tz_in_T_63 = io_in1_0[31:0]; // @[ALU.scala:83:7, :104:34, :133:25] wire [31:0] _tz_in_T_65 = io_in1_0[31:0]; // @[ALU.scala:83:7, :104:34, :134:33] wire [31:0] _popc_in_T_2 = io_in1_0[31:0]; // @[ALU.scala:83:7, :104:34, :137:32] wire [63:0] shin_r = {shin_hi, io_in1_0[31:0]}; // @[ALU.scala:83:7, :102:24, :104:{18,34}] wire _GEN = io_fn_0 == 5'h5; // @[package.scala:16:47] wire _shin_T; // @[package.scala:16:47] assign _shin_T = _GEN; // @[package.scala:16:47] wire _shout_T; // @[ALU.scala:109:25] assign _shout_T = _GEN; // @[package.scala:16:47] wire _GEN_0 = io_fn_0 == 5'hB; // @[package.scala:16:47] wire _shin_T_1; // @[package.scala:16:47] assign _shin_T_1 = _GEN_0; // @[package.scala:16:47] wire _shout_T_1; // @[ALU.scala:109:44] assign _shout_T_1 = _GEN_0; // @[package.scala:16:47] wire _GEN_1 = io_fn_0 == 5'h12; // @[package.scala:16:47] wire _shin_T_2; // @[package.scala:16:47] assign _shin_T_2 = _GEN_1; // @[package.scala:16:47] wire _out_T_16; // @[ALU.scala:161:47] assign _out_T_16 = _GEN_1; // @[package.scala:16:47] wire _GEN_2 = io_fn_0 == 5'h13; // @[package.scala:16:47] wire _shin_T_3; // @[package.scala:16:47] assign _shin_T_3 = _GEN_2; // @[package.scala:16:47] wire _shout_T_3; // @[ALU.scala:109:64] assign _shout_T_3 = _GEN_2; // @[package.scala:16:47] wire _bext_mask_T; // @[ALU.scala:122:52] assign _bext_mask_T = _GEN_2; // @[package.scala:16:47] wire _shin_T_4 = _shin_T \| _shin_T_1; // @[package.scala:16:47, :81:59] wire _shin_T_5 = _shin_T_4 \| _shin_T_2; // @[package.scala:16:47, :81:59] wire _shin_T_6 = _shin_T_5 \| _shin_T_3; // @[package.scala:16:47, :81:59] wire _shin_T_7 = ~_shin_T_6; // @[package.scala:81:59] wire [31:0] _shin_T_10 = shin_r[63:32]; // @[ALU.scala:104:18, :106:46] wire [31:0] _rotin_T_3 = shin_r[63:32]; // @[ALU.scala:104:18, :106:46, :156:44] wire [63:0] _shin_T_11 = {32'h0, _shin_T_10}; // @[ALU.scala:106:46] wire [31:0] _shin_T_12 = shin_r[31:0]; // @[ALU.scala:104:18, :106:46] wire [31:0] _rotin_T_5 = shin_r[31:0]; // @[ALU.scala:104:18, :106:46, :156:44] wire [63:0] _shin_T_13 = {_shin_T_12, 32'h0}; // @[ALU.scala:106:46] wire [63:0] _shin_T_15 = _shin_T_13 & 64'hFFFFFFFF00000000; // @[ALU.scala:106:46] wire [63:0] _shin_T_16 = _shin_T_11 \| _shin_T_15; // @[ALU.scala:106:46] wire [47:0] _shin_T_20 = _shin_T_16[63:16]; // @[ALU.scala:106:46] wire [63:0] _shin_T_21 = {16'h0, _shin_T_20 & 48'hFFFF0000FFFF}; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [47:0] _shin_T_22 = _shin_T_16[47:0]; // @[ALU.scala:106:46] wire [63:0] _shin_T_23 = {_shin_T_22, 16'h0}; // @[ALU.scala:106:46] wire [63:0] _shin_T_25 = _shin_T_23 & 64'hFFFF0000FFFF0000; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _shin_T_26 = _shin_T_21 \| _shin_T_25; // @[ALU.scala:106:46] wire [55:0] _shin_T_30 = _shin_T_26[63:8]; // @[ALU.scala:106:46] wire [63:0] _shin_T_31 = {8'h0, _shin_T_30 & 56'hFF00FF00FF00FF}; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [55:0] _shin_T_32 = _shin_T_26[55:0]; // @[ALU.scala:106:46] wire [63:0] _shin_T_33 = {_shin_T_32, 8'h0}; // @[ALU.scala:106:46] wire [63:0] _shin_T_35 = _shin_T_33 & 64'hFF00FF00FF00FF00; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _shin_T_36 = _shin_T_31 \| _shin_T_35; // @[ALU.scala:106:46] wire [59:0] _shin_T_40 = _shin_T_36[63:4]; // @[ALU.scala:106:46] wire [63:0] _shin_T_41 = {4'h0, _shin_T_40 & 60'hF0F0F0F0F0F0F0F}; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [59:0] _shin_T_42 = _shin_T_36[59:0]; // @[ALU.scala:106:46] wire [63:0] _shin_T_43 = {_shin_T_42, 4'h0}; // @[ALU.scala:106:46] wire [63:0] _shin_T_45 = _shin_T_43 & 64'hF0F0F0F0F0F0F0F0; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _shin_T_46 = _shin_T_41 \| _shin_T_45; // @[ALU.scala:106:46] wire [61:0] _shin_T_50 = _shin_T_46[63:2]; // @[ALU.scala:106:46] wire [63:0] _shin_T_51 = {2'h0, _shin_T_50 & 62'h3333333333333333}; // @[package.scala:16:47] wire [61:0] _shin_T_52 = _shin_T_46[61:0]; // @[ALU.scala:106:46] wire [63:0] _shin_T_53 = {_shin_T_52, 2'h0}; // @[package.scala:16:47] wire [63:0] _shin_T_55 = _shin_T_53 & 64'hCCCCCCCCCCCCCCCC; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _shin_T_56 = _shin_T_51 \| _shin_T_55; // @[ALU.scala:106:46] wire [62:0] _shin_T_60 = _shin_T_56[63:1]; // @[ALU.scala:106:46] wire [63:0] _shin_T_61 = {1'h0, _shin_T_60 & 63'h5555555555555555}; // @[ALU.scala:88:26, :106:46, :108:24, :132:19, :156:44, :158:25] wire [62:0] _shin_T_62 = _shin_T_56[62:0]; // @[ALU.scala:106:46] wire [63:0] _shin_T_63 = {_shin_T_62, 1'h0}; // @[ALU.scala:88:26, :106:46] wire [63:0] _shin_T_65 = _shin_T_63 & 64'hAAAAAAAAAAAAAAAA; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _shin_T_66 = _shin_T_61 \| _shin_T_65; // @[ALU.scala:106:46] wire [63:0] shin = _shin_T_7 ? _shin_T_66 : shin_r; // @[ALU.scala:64:33, :104:18, :106:{17,46}] wire _shout_r_T_1 = shin[63]; // @[ALU.scala:106:17, :107:41] wire _shout_r_T_2 = _shout_r_T & _shout_r_T_1; // @[ALU.scala:58:29, :107:{35,41}] wire [64:0] _shout_r_T_3 = {_shout_r_T_2, shin}; // @[ALU.scala:106:17, :107:{21,35}] wire [64:0] _shout_r_T_4 = _shout_r_T_3; // @[ALU.scala:107:{21,57}] wire [64:0] _shout_r_T_5 = $signed($signed(_shout_r_T_4) >>> shamt); // @[ALU.scala:103:22, :107:{57,64}] wire [63:0] shout_r = _shout_r_T_5[63:0]; // @[ALU.scala:107:{64,73}] wire [31:0] _shout_l_T_2 = shout_r[63:32]; // @[ALU.scala:107:73, :108:24] wire [63:0] _shout_l_T_3 = {32'h0, _shout_l_T_2}; // @[ALU.scala:108:24] wire [31:0] _shout_l_T_4 = shout_r[31:0]; // @[ALU.scala:107:73, :108:24] wire [63:0] _shout_l_T_5 = {_shout_l_T_4, 32'h0}; // @[ALU.scala:108:24] wire [63:0] _shout_l_T_7 = _shout_l_T_5 & 64'hFFFFFFFF00000000; // @[ALU.scala:108:24] wire [63:0] _shout_l_T_8 = _shout_l_T_3 \| _shout_l_T_7; // @[ALU.scala:108:24] wire [47:0] _shout_l_T_12 = _shout_l_T_8[63:16]; // @[ALU.scala:108:24] wire [63:0] _shout_l_T_13 = {16'h0, _shout_l_T_12 & 48'hFFFF0000FFFF}; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [47:0] _shout_l_T_14 = _shout_l_T_8[47:0]; // @[ALU.scala:108:24] wire [63:0] _shout_l_T_15 = {_shout_l_T_14, 16'h0}; // @[ALU.scala:106:46, :108:24] wire [63:0] _shout_l_T_17 = _shout_l_T_15 & 64'hFFFF0000FFFF0000; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _shout_l_T_18 = _shout_l_T_13 \| _shout_l_T_17; // @[ALU.scala:108:24] wire [55:0] _shout_l_T_22 = _shout_l_T_18[63:8]; // @[ALU.scala:108:24] wire [63:0] _shout_l_T_23 = {8'h0, _shout_l_T_22 & 56'hFF00FF00FF00FF}; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [55:0] _shout_l_T_24 = _shout_l_T_18[55:0]; // @[ALU.scala:108:24] wire [63:0] _shout_l_T_25 = {_shout_l_T_24, 8'h0}; // @[ALU.scala:108:24] wire [63:0] _shout_l_T_27 = _shout_l_T_25 & 64'hFF00FF00FF00FF00; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _shout_l_T_28 = _shout_l_T_23 \| _shout_l_T_27; // @[ALU.scala:108:24] wire [59:0] _shout_l_T_32 = _shout_l_T_28[63:4]; // @[ALU.scala:108:24] wire [63:0] _shout_l_T_33 = {4'h0, _shout_l_T_32 & 60'hF0F0F0F0F0F0F0F}; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [59:0] _shout_l_T_34 = _shout_l_T_28[59:0]; // @[ALU.scala:108:24] wire [63:0] _shout_l_T_35 = {_shout_l_T_34, 4'h0}; // @[ALU.scala:106:46, :108:24] wire [63:0] _shout_l_T_37 = _shout_l_T_35 & 64'hF0F0F0F0F0F0F0F0; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _shout_l_T_38 = _shout_l_T_33 \| _shout_l_T_37; // @[ALU.scala:108:24] wire [61:0] _shout_l_T_42 = _shout_l_T_38[63:2]; // @[ALU.scala:108:24] wire [63:0] _shout_l_T_43 = {2'h0, _shout_l_T_42 & 62'h3333333333333333}; // @[package.scala:16:47] wire [61:0] _shout_l_T_44 = _shout_l_T_38[61:0]; // @[ALU.scala:108:24] wire [63:0] _shout_l_T_45 = {_shout_l_T_44, 2'h0}; // @[package.scala:16:47] wire [63:0] _shout_l_T_47 = _shout_l_T_45 & 64'hCCCCCCCCCCCCCCCC; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _shout_l_T_48 = _shout_l_T_43 \| _shout_l_T_47; // @[ALU.scala:108:24] wire [62:0] _shout_l_T_52 = _shout_l_T_48[63:1]; // @[ALU.scala:108:24] wire [63:0] _shout_l_T_53 = {1'h0, _shout_l_T_52 & 63'h5555555555555555}; // @[ALU.scala:88:26, :106:46, :108:24, :132:19, :156:44, :158:25] wire [62:0] _shout_l_T_54 = _shout_l_T_48[62:0]; // @[ALU.scala:108:24] wire [63:0] _shout_l_T_55 = {_shout_l_T_54, 1'h0}; // @[ALU.scala:88:26, :108:24] wire [63:0] _shout_l_T_57 = _shout_l_T_55 & 64'hAAAAAAAAAAAAAAAA; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] shout_l = _shout_l_T_53 \| _shout_l_T_57; // @[ALU.scala:108:24] wire _shout_T_2 = _shout_T \| _shout_T_1; // @[ALU.scala:109:{25,35,44}] wire _shout_T_4 = _shout_T_2 \| _shout_T_3; // @[ALU.scala:109:{35,55,64}] wire [63:0] _shout_T_5 = _shout_T_4 ? shout_r : 64'h0; // @[ALU.scala:107:73, :109:{18,55}] wire _shout_T_6 = io_fn_0 == 5'h1; // @[ALU.scala:83:7, :110:25] wire [63:0] _shout_T_7 = _shout_T_6 ? shout_l : 64'h0; // @[ALU.scala:108:24, :110:{18,25}] wire [63:0] shout = _shout_T_5 \| _shout_T_7; // @[ALU.scala:109:{18,91}, :110:18] wire in2_not_zero = \|io_in2_0; // @[ALU.scala:83:7, :113:29] wire _logic_T = io_fn_0 == 5'h4; // @[ALU.scala:83:7, :119:25] wire _GEN_3 = io_fn_0 == 5'h6; // @[ALU.scala:83:7, :119:45] wire _logic_T_1; // @[ALU.scala:119:45] assign _logic_T_1 = _GEN_3; // @[ALU.scala:119:45] wire _logic_T_8; // @[ALU.scala:120:25] assign _logic_T_8 = _GEN_3; // @[ALU.scala:119:45, :120:25] wire _logic_T_2 = _logic_T \| _logic_T_1; // @[ALU.scala:119:{25,36,45}] wire _GEN_4 = io_fn_0 == 5'h19; // @[ALU.scala:83:7, :119:64] wire _logic_T_3; // @[ALU.scala:119:64] assign _logic_T_3 = _GEN_4; // @[ALU.scala:119:64] wire _logic_T_11; // @[ALU.scala:120:64] assign _logic_T_11 = _GEN_4; // @[ALU.scala:119:64, :120:64] wire _logic_T_4 = _logic_T_2 \| _logic_T_3; // @[ALU.scala:119:{36,55,64}] wire _logic_T_5 = io_fn_0 == 5'h1A; // @[ALU.scala:83:7, :119:84] wire _logic_T_6 = _logic_T_4 \| _logic_T_5; // @[ALU.scala:119:{55,75,84}] wire [63:0] _logic_T_7 = _logic_T_6 ? in1_xor_in2 : 64'h0; // @[ALU.scala:86:28, :119:{18,75}] wire _logic_T_9 = io_fn_0 == 5'h7; // @[ALU.scala:83:7, :120:44] wire _logic_T_10 = _logic_T_8 \| _logic_T_9; // @[ALU.scala:120:{25,35,44}] wire _logic_T_12 = _logic_T_10 \| _logic_T_11; // @[ALU.scala:120:{35,55,64}] wire _logic_T_13 = io_fn_0 == 5'h18; // @[ALU.scala:83:7, :120:84] wire _logic_T_14 = _logic_T_12 \| _logic_T_13; // @[ALU.scala:120:{55,75,84}] wire [63:0] _logic_T_15 = _logic_T_14 ? in1_and_in2 : 64'h0; // @[ALU.scala:87:28, :120:{18,75}] wire [63:0] logic_0 = _logic_T_7 \| _logic_T_15; // @[ALU.scala:119:{18,115}, :120:18] wire _bext_mask_T_1 = _bext_mask_T; // @[ALU.scala:122:{43,52}] wire [63:0] bext_mask = _bext_mask_T_1 ? 64'h1 : 64'hFFFFFFFFFFFFFFFF; // @[ALU.scala:122:{22,43}] wire _shift_logic_T = io_fn_0 > 5'hB; // @[ALU.scala:59:31, :83:7] wire _shift_logic_T_1 = ~(io_fn_0[4]); // @[ALU.scala:59:48, :83:7] wire _shift_logic_T_2 = _shift_logic_T & _shift_logic_T_1; // @[ALU.scala:59:{31,41,48}] wire _shift_logic_T_3 = _shift_logic_T_2 & slt; // @[ALU.scala:59:41, :92:8, :123:36] wire [63:0] _shift_logic_T_4 = {63'h0, _shift_logic_T_3} \| logic_0; // @[ALU.scala:119:115, :123:{36,44}] wire [63:0] _shift_logic_T_5 = shout & bext_mask; // @[ALU.scala:109:91, :122:22, :123:61] wire [63:0] shift_logic = _shift_logic_T_4 \| _shift_logic_T_5; // @[ALU.scala:123:{44,52,61}] wire _tz_in_T = ~io_dw_0; // @[ALU.scala:83:7, :130:32] wire _tz_in_T_1 = io_in2_0[0]; // @[ALU.scala:83:7, :130:53] wire _tz_in_T_2 = ~_tz_in_T_1; // @[ALU.scala:130:{46,53}] wire [1:0] _tz_in_T_3 = {_tz_in_T, _tz_in_T_2}; // @[ALU.scala:130:{32,43,46}] wire [63:0] _tz_in_T_7 = {32'h0, _tz_in_T_6}; // @[ALU.scala:132:19] wire [63:0] _tz_in_T_9 = {_tz_in_T_8, 32'h0}; // @[ALU.scala:132:19] wire [63:0] _tz_in_T_11 = _tz_in_T_9 & 64'hFFFFFFFF00000000; // @[ALU.scala:132:19] wire [63:0] _tz_in_T_12 = _tz_in_T_7 \| _tz_in_T_11; // @[ALU.scala:132:19] wire [47:0] _tz_in_T_16 = _tz_in_T_12[63:16]; // @[ALU.scala:132:19] wire [63:0] _tz_in_T_17 = {16'h0, _tz_in_T_16 & 48'hFFFF0000FFFF}; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [47:0] _tz_in_T_18 = _tz_in_T_12[47:0]; // @[ALU.scala:132:19] wire [63:0] _tz_in_T_19 = {_tz_in_T_18, 16'h0}; // @[ALU.scala:106:46, :132:19] wire [63:0] _tz_in_T_21 = _tz_in_T_19 & 64'hFFFF0000FFFF0000; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _tz_in_T_22 = _tz_in_T_17 \| _tz_in_T_21; // @[ALU.scala:132:19] wire [55:0] _tz_in_T_26 = _tz_in_T_22[63:8]; // @[ALU.scala:132:19] wire [63:0] _tz_in_T_27 = {8'h0, _tz_in_T_26 & 56'hFF00FF00FF00FF}; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [55:0] _tz_in_T_28 = _tz_in_T_22[55:0]; // @[ALU.scala:132:19] wire [63:0] _tz_in_T_29 = {_tz_in_T_28, 8'h0}; // @[ALU.scala:132:19] wire [63:0] _tz_in_T_31 = _tz_in_T_29 & 64'hFF00FF00FF00FF00; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _tz_in_T_32 = _tz_in_T_27 \| _tz_in_T_31; // @[ALU.scala:132:19] wire [59:0] _tz_in_T_36 = _tz_in_T_32[63:4]; // @[ALU.scala:132:19] wire [63:0] _tz_in_T_37 = {4'h0, _tz_in_T_36 & 60'hF0F0F0F0F0F0F0F}; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [59:0] _tz_in_T_38 = _tz_in_T_32[59:0]; // @[ALU.scala:132:19] wire [63:0] _tz_in_T_39 = {_tz_in_T_38, 4'h0}; // @[ALU.scala:106:46, :132:19] wire [63:0] _tz_in_T_41 = _tz_in_T_39 & 64'hF0F0F0F0F0F0F0F0; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _tz_in_T_42 = _tz_in_T_37 \| _tz_in_T_41; // @[ALU.scala:132:19] wire [61:0] _tz_in_T_46 = _tz_in_T_42[63:2]; // @[ALU.scala:132:19] wire [63:0] _tz_in_T_47 = {2'h0, _tz_in_T_46 & 62'h3333333333333333}; // @[package.scala:16:47] wire [61:0] _tz_in_T_48 = _tz_in_T_42[61:0]; // @[ALU.scala:132:19] wire [63:0] _tz_in_T_49 = {_tz_in_T_48, 2'h0}; // @[package.scala:16:47] wire [63:0] _tz_in_T_51 = _tz_in_T_49 & 64'hCCCCCCCCCCCCCCCC; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _tz_in_T_52 = _tz_in_T_47 \| _tz_in_T_51; // @[ALU.scala:132:19] wire [62:0] _tz_in_T_56 = _tz_in_T_52[63:1]; // @[ALU.scala:132:19] wire [63:0] _tz_in_T_57 = {1'h0, _tz_in_T_56 & 63'h5555555555555555}; // @[ALU.scala:88:26, :106:46, :108:24, :132:19, :156:44, :158:25] wire [62:0] _tz_in_T_58 = _tz_in_T_52[62:0]; // @[ALU.scala:132:19] wire [63:0] _tz_in_T_59 = {_tz_in_T_58, 1'h0}; // @[ALU.scala:88:26, :132:19] wire [63:0] _tz_in_T_61 = _tz_in_T_59 & 64'hAAAAAAAAAAAAAAAA; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _tz_in_T_62 = _tz_in_T_57 \| _tz_in_T_61; // @[ALU.scala:132:19] wire [32:0] _tz_in_T_64 = {1'h1, _tz_in_T_63}; // @[ALU.scala:133:{16,25}] wire [15:0] _tz_in_T_68 = _tz_in_T_65[31:16]; // @[ALU.scala:134:{26,33}] wire [31:0] _tz_in_T_69 = {16'h0, _tz_in_T_68}; // @[ALU.scala:106:46, :134:26] wire [15:0] _tz_in_T_70 = _tz_in_T_65[15:0]; // @[ALU.scala:134:{26,33}] wire [31:0] _tz_in_T_71 = {_tz_in_T_70, 16'h0}; // @[ALU.scala:106:46, :134:26] wire [31:0] _tz_in_T_73 = _tz_in_T_71 & 32'hFFFF0000; // @[ALU.scala:134:26] wire [31:0] _tz_in_T_74 = _tz_in_T_69 \| _tz_in_T_73; // @[ALU.scala:134:26] wire [23:0] _tz_in_T_78 = _tz_in_T_74[31:8]; // @[ALU.scala:134:26] wire [31:0] _tz_in_T_79 = {8'h0, _tz_in_T_78 & 24'hFF00FF}; // @[ALU.scala:134:26] wire [23:0] _tz_in_T_80 = _tz_in_T_74[23:0]; // @[ALU.scala:134:26] wire [31:0] _tz_in_T_81 = {_tz_in_T_80, 8'h0}; // @[ALU.scala:134:26] wire [31:0] _tz_in_T_83 = _tz_in_T_81 & 32'hFF00FF00; // @[ALU.scala:134:26] wire [31:0] _tz_in_T_84 = _tz_in_T_79 \| _tz_in_T_83; // @[ALU.scala:134:26] wire [27:0] _tz_in_T_88 = _tz_in_T_84[31:4]; // @[ALU.scala:134:26] wire [31:0] _tz_in_T_89 = {4'h0, _tz_in_T_88 & 28'hF0F0F0F}; // @[ALU.scala:106:46, :134:26] wire [27:0] _tz_in_T_90 = _tz_in_T_84[27:0]; // @[ALU.scala:134:26] wire [31:0] _tz_in_T_91 = {_tz_in_T_90, 4'h0}; // @[ALU.scala:106:46, :134:26] wire [31:0] _tz_in_T_93 = _tz_in_T_91 & 32'hF0F0F0F0; // @[ALU.scala:134:26] wire [31:0] _tz_in_T_94 = _tz_in_T_89 \| _tz_in_T_93; // @[ALU.scala:134:26] wire [29:0] _tz_in_T_98 = _tz_in_T_94[31:2]; // @[ALU.scala:134:26] wire [31:0] _tz_in_T_99 = {2'h0, _tz_in_T_98 & 30'h33333333}; // @[package.scala:16:47] wire [29:0] _tz_in_T_100 = _tz_in_T_94[29:0]; // @[ALU.scala:134:26] wire [31:0] _tz_in_T_101 = {_tz_in_T_100, 2'h0}; // @[package.scala:16:47] wire [31:0] _tz_in_T_103 = _tz_in_T_101 & 32'hCCCCCCCC; // @[ALU.scala:134:26] wire [31:0] _tz_in_T_104 = _tz_in_T_99 \| _tz_in_T_103; // @[ALU.scala:134:26] wire [30:0] _tz_in_T_108 = _tz_in_T_104[31:1]; // @[ALU.scala:134:26] wire [31:0] _tz_in_T_109 = {1'h0, _tz_in_T_108 & 31'h55555555}; // @[ALU.scala:88:26, :134:26] wire [30:0] _tz_in_T_110 = _tz_in_T_104[30:0]; // @[ALU.scala:134:26] wire [31:0] _tz_in_T_111 = {_tz_in_T_110, 1'h0}; // @[ALU.scala:88:26, :134:26] wire [31:0] _tz_in_T_113 = _tz_in_T_111 & 32'hAAAAAAAA; // @[ALU.scala:134:26] wire [31:0] _tz_in_T_114 = _tz_in_T_109 \| _tz_in_T_113; // @[ALU.scala:134:26] wire [32:0] _tz_in_T_115 = {1'h1, _tz_in_T_114}; // @[ALU.scala:134:{16,26}] wire _tz_in_T_116 = _tz_in_T_3 == 2'h1; // @[ALU.scala:130:{43,62}] wire [63:0] _tz_in_T_117 = _tz_in_T_116 ? _tz_in_T_62 : io_in1_0; // @[ALU.scala:83:7, :130:62, :132:19] wire _tz_in_T_118 = _tz_in_T_3 == 2'h2; // @[ALU.scala:130:{43,62}] wire [63:0] _tz_in_T_119 = _tz_in_T_118 ? {31'h0, _tz_in_T_64} : _tz_in_T_117; // @[ALU.scala:130:62, :133:16] wire _tz_in_T_120 = &_tz_in_T_3; // @[ALU.scala:130:{43,62}] wire [63:0] tz_in = _tz_in_T_120 ? {31'h0, _tz_in_T_115} : _tz_in_T_119; // @[ALU.scala:130:62, :134:16] wire _popc_in_T = io_in2_0[1]; // @[ALU.scala:83:7, :136:27] wire _popc_in_T_1 = ~io_dw_0; // @[ALU.scala:83:7, :130:32, :137:15] wire [63:0] _popc_in_T_3 = _popc_in_T_1 ? {32'h0, _popc_in_T_2} : io_in1_0; // @[ALU.scala:83:7, :137:{8,15,32}] wire [64:0] _popc_in_T_4 = {1'h1, tz_in}; // @[ALU.scala:130:62, :138:27] wire _popc_in_T_5 = _popc_in_T_4[0]; // @[OneHot.scala:85:71] wire _popc_in_T_6 = _popc_in_T_4[1]; // @[OneHot.scala:85:71] wire _popc_in_T_7 = _popc_in_T_4[2]; // @[OneHot.scala:85:71] wire _popc_in_T_8 = _popc_in_T_4[3]; // @[OneHot.scala:85:71] wire _popc_in_T_9 = _popc_in_T_4[4]; // @[OneHot.scala:85:71] wire _popc_in_T_10 = _popc_in_T_4[5]; // @[OneHot.scala:85:71] wire _popc_in_T_11 = _popc_in_T_4[6]; // @[OneHot.scala:85:71] wire _popc_in_T_12 = _popc_in_T_4[7]; // @[OneHot.scala:85:71] wire _popc_in_T_13 = _popc_in_T_4[8]; // @[OneHot.scala:85:71] wire _popc_in_T_14 = _popc_in_T_4[9]; // @[OneHot.scala:85:71] wire _popc_in_T_15 = _popc_in_T_4[10]; // @[OneHot.scala:85:71] wire _popc_in_T_16 = _popc_in_T_4[11]; // @[OneHot.scala:85:71] wire _popc_in_T_17 = _popc_in_T_4[12]; // @[OneHot.scala:85:71] wire _popc_in_T_18 = _popc_in_T_4[13]; // @[OneHot.scala:85:71] wire _popc_in_T_19 = _popc_in_T_4[14]; // @[OneHot.scala:85:71] wire _popc_in_T_20 = _popc_in_T_4[15]; // @[OneHot.scala:85:71] wire _popc_in_T_21 = _popc_in_T_4[16]; // @[OneHot.scala:85:71] wire _popc_in_T_22 = _popc_in_T_4[17]; // @[OneHot.scala:85:71] wire _popc_in_T_23 = _popc_in_T_4[18]; // @[OneHot.scala:85:71] wire _popc_in_T_24 = _popc_in_T_4[19]; // @[OneHot.scala:85:71] wire _popc_in_T_25 = _popc_in_T_4[20]; // @[OneHot.scala:85:71] wire _popc_in_T_26 = _popc_in_T_4[21]; // @[OneHot.scala:85:71] wire _popc_in_T_27 = _popc_in_T_4[22]; // @[OneHot.scala:85:71] wire _popc_in_T_28 = _popc_in_T_4[23]; // @[OneHot.scala:85:71] wire _popc_in_T_29 = _popc_in_T_4[24]; // @[OneHot.scala:85:71] wire _popc_in_T_30 = _popc_in_T_4[25]; // @[OneHot.scala:85:71] wire _popc_in_T_31 = _popc_in_T_4[26]; // @[OneHot.scala:85:71] wire _popc_in_T_32 = _popc_in_T_4[27]; // @[OneHot.scala:85:71] wire _popc_in_T_33 = _popc_in_T_4[28]; // @[OneHot.scala:85:71] wire _popc_in_T_34 = _popc_in_T_4[29]; // @[OneHot.scala:85:71] wire _popc_in_T_35 = _popc_in_T_4[30]; // @[OneHot.scala:85:71] wire _popc_in_T_36 = _popc_in_T_4[31]; // @[OneHot.scala:85:71] wire _popc_in_T_37 = _popc_in_T_4[32]; // @[OneHot.scala:85:71] wire _popc_in_T_38 = _popc_in_T_4[33]; // @[OneHot.scala:85:71] wire _popc_in_T_39 = _popc_in_T_4[34]; // @[OneHot.scala:85:71] wire _popc_in_T_40 = _popc_in_T_4[35]; // @[OneHot.scala:85:71] wire _popc_in_T_41 = _popc_in_T_4[36]; // @[OneHot.scala:85:71] wire _popc_in_T_42 = _popc_in_T_4[37]; // @[OneHot.scala:85:71] wire _popc_in_T_43 = _popc_in_T_4[38]; // @[OneHot.scala:85:71] wire _popc_in_T_44 = _popc_in_T_4[39]; // @[OneHot.scala:85:71] wire _popc_in_T_45 = _popc_in_T_4[40]; // @[OneHot.scala:85:71] wire _popc_in_T_46 = _popc_in_T_4[41]; // @[OneHot.scala:85:71] wire _popc_in_T_47 = _popc_in_T_4[42]; // @[OneHot.scala:85:71] wire _popc_in_T_48 = _popc_in_T_4[43]; // @[OneHot.scala:85:71] wire _popc_in_T_49 = _popc_in_T_4[44]; // @[OneHot.scala:85:71] wire _popc_in_T_50 = _popc_in_T_4[45]; // @[OneHot.scala:85:71] wire _popc_in_T_51 = _popc_in_T_4[46]; // @[OneHot.scala:85:71] wire _popc_in_T_52 = _popc_in_T_4[47]; // @[OneHot.scala:85:71] wire _popc_in_T_53 = _popc_in_T_4[48]; // @[OneHot.scala:85:71] wire _popc_in_T_54 = _popc_in_T_4[49]; // @[OneHot.scala:85:71] wire _popc_in_T_55 = _popc_in_T_4[50]; // @[OneHot.scala:85:71] wire _popc_in_T_56 = _popc_in_T_4[51]; // @[OneHot.scala:85:71] wire _popc_in_T_57 = _popc_in_T_4[52]; // @[OneHot.scala:85:71] wire _popc_in_T_58 = _popc_in_T_4[53]; // @[OneHot.scala:85:71] wire _popc_in_T_59 = _popc_in_T_4[54]; // @[OneHot.scala:85:71] wire _popc_in_T_60 = _popc_in_T_4[55]; // @[OneHot.scala:85:71] wire _popc_in_T_61 = _popc_in_T_4[56]; // @[OneHot.scala:85:71] wire _popc_in_T_62 = _popc_in_T_4[57]; // @[OneHot.scala:85:71] wire _popc_in_T_63 = _popc_in_T_4[58]; // @[OneHot.scala:85:71] wire _popc_in_T_64 = _popc_in_T_4[59]; // @[OneHot.scala:85:71] wire _popc_in_T_65 = _popc_in_T_4[60]; // @[OneHot.scala:85:71] wire _popc_in_T_66 = _popc_in_T_4[61]; // @[OneHot.scala:85:71] wire _popc_in_T_67 = _popc_in_T_4[62]; // @[OneHot.scala:85:71] wire _popc_in_T_68 = _popc_in_T_4[63]; // @[OneHot.scala:85:71] wire _popc_in_T_69 = _popc_in_T_4[64]; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_70 = {_popc_in_T_69, 64'h0}; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_71 = _popc_in_T_68 ? 65'h8000000000000000 : _popc_in_T_70; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_72 = _popc_in_T_67 ? 65'h4000000000000000 : _popc_in_T_71; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_73 = _popc_in_T_66 ? 65'h2000000000000000 : _popc_in_T_72; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_74 = _popc_in_T_65 ? 65'h1000000000000000 : _popc_in_T_73; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_75 = _popc_in_T_64 ? 65'h800000000000000 : _popc_in_T_74; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_76 = _popc_in_T_63 ? 65'h400000000000000 : _popc_in_T_75; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_77 = _popc_in_T_62 ? 65'h200000000000000 : _popc_in_T_76; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_78 = _popc_in_T_61 ? 65'h100000000000000 : _popc_in_T_77; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_79 = _popc_in_T_60 ? 65'h80000000000000 : _popc_in_T_78; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_80 = _popc_in_T_59 ? 65'h40000000000000 : _popc_in_T_79; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_81 = _popc_in_T_58 ? 65'h20000000000000 : _popc_in_T_80; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_82 = _popc_in_T_57 ? 65'h10000000000000 : _popc_in_T_81; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_83 = _popc_in_T_56 ? 65'h8000000000000 : _popc_in_T_82; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_84 = _popc_in_T_55 ? 65'h4000000000000 : _popc_in_T_83; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_85 = _popc_in_T_54 ? 65'h2000000000000 : _popc_in_T_84; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_86 = _popc_in_T_53 ? 65'h1000000000000 : _popc_in_T_85; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_87 = _popc_in_T_52 ? 65'h800000000000 : _popc_in_T_86; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_88 = _popc_in_T_51 ? 65'h400000000000 : _popc_in_T_87; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_89 = _popc_in_T_50 ? 65'h200000000000 : _popc_in_T_88; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_90 = _popc_in_T_49 ? 65'h100000000000 : _popc_in_T_89; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_91 = _popc_in_T_48 ? 65'h80000000000 : _popc_in_T_90; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_92 = _popc_in_T_47 ? 65'h40000000000 : _popc_in_T_91; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_93 = _popc_in_T_46 ? 65'h20000000000 : _popc_in_T_92; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_94 = _popc_in_T_45 ? 65'h10000000000 : _popc_in_T_93; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_95 = _popc_in_T_44 ? 65'h8000000000 : _popc_in_T_94; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_96 = _popc_in_T_43 ? 65'h4000000000 : _popc_in_T_95; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_97 = _popc_in_T_42 ? 65'h2000000000 : _popc_in_T_96; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_98 = _popc_in_T_41 ? 65'h1000000000 : _popc_in_T_97; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_99 = _popc_in_T_40 ? 65'h800000000 : _popc_in_T_98; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_100 = _popc_in_T_39 ? 65'h400000000 : _popc_in_T_99; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_101 = _popc_in_T_38 ? 65'h200000000 : _popc_in_T_100; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_102 = _popc_in_T_37 ? 65'h100000000 : _popc_in_T_101; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_103 = _popc_in_T_36 ? 65'h80000000 : _popc_in_T_102; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_104 = _popc_in_T_35 ? 65'h40000000 : _popc_in_T_103; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_105 = _popc_in_T_34 ? 65'h20000000 : _popc_in_T_104; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_106 = _popc_in_T_33 ? 65'h10000000 : _popc_in_T_105; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_107 = _popc_in_T_32 ? 65'h8000000 : _popc_in_T_106; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_108 = _popc_in_T_31 ? 65'h4000000 : _popc_in_T_107; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_109 = _popc_in_T_30 ? 65'h2000000 : _popc_in_T_108; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_110 = _popc_in_T_29 ? 65'h1000000 : _popc_in_T_109; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_111 = _popc_in_T_28 ? 65'h800000 : _popc_in_T_110; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_112 = _popc_in_T_27 ? 65'h400000 : _popc_in_T_111; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_113 = _popc_in_T_26 ? 65'h200000 : _popc_in_T_112; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_114 = _popc_in_T_25 ? 65'h100000 : _popc_in_T_113; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_115 = _popc_in_T_24 ? 65'h80000 : _popc_in_T_114; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_116 = _popc_in_T_23 ? 65'h40000 : _popc_in_T_115; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_117 = _popc_in_T_22 ? 65'h20000 : _popc_in_T_116; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_118 = _popc_in_T_21 ? 65'h10000 : _popc_in_T_117; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_119 = _popc_in_T_20 ? 65'h8000 : _popc_in_T_118; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_120 = _popc_in_T_19 ? 65'h4000 : _popc_in_T_119; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_121 = _popc_in_T_18 ? 65'h2000 : _popc_in_T_120; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_122 = _popc_in_T_17 ? 65'h1000 : _popc_in_T_121; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_123 = _popc_in_T_16 ? 65'h800 : _popc_in_T_122; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_124 = _popc_in_T_15 ? 65'h400 : _popc_in_T_123; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_125 = _popc_in_T_14 ? 65'h200 : _popc_in_T_124; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_126 = _popc_in_T_13 ? 65'h100 : _popc_in_T_125; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_127 = _popc_in_T_12 ? 65'h80 : _popc_in_T_126; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_128 = _popc_in_T_11 ? 65'h40 : _popc_in_T_127; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_129 = _popc_in_T_10 ? 65'h20 : _popc_in_T_128; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_130 = _popc_in_T_9 ? 65'h10 : _popc_in_T_129; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_131 = _popc_in_T_8 ? 65'h8 : _popc_in_T_130; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_132 = _popc_in_T_7 ? 65'h4 : _popc_in_T_131; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_133 = _popc_in_T_6 ? 65'h2 : _popc_in_T_132; // @[OneHot.scala:85:71] wire [64:0] _popc_in_T_134 = _popc_in_T_5 ? 65'h1 : _popc_in_T_133; // @[OneHot.scala:85:71] wire [65:0] _popc_in_T_135 = {1'h0, _popc_in_T_134} - 66'h1; // @[Mux.scala:50:70] wire [64:0] _popc_in_T_136 = _popc_in_T_135[64:0]; // @[ALU.scala:138:37] wire [64:0] _popc_in_T_137 = _popc_in_T ? {1'h0, _popc_in_T_3} : _popc_in_T_136; // @[ALU.scala:88:26, :136:{20,27}, :137:8, :138:37] wire [63:0] popc_in = _popc_in_T_137[63:0]; // @[ALU.scala:136:20, :138:43] wire _count_T = popc_in[0]; // @[ALU.scala:138:43, :139:23] wire _count_T_1 = popc_in[1]; // @[ALU.scala:138:43, :139:23] wire _count_T_2 = popc_in[2]; // @[ALU.scala:138:43, :139:23] wire _count_T_3 = popc_in[3]; // @[ALU.scala:138:43, :139:23] wire _count_T_4 = popc_in[4]; // @[ALU.scala:138:43, :139:23] wire _count_T_5 = popc_in[5]; // @[ALU.scala:138:43, :139:23] wire _count_T_6 = popc_in[6]; // @[ALU.scala:138:43, :139:23] wire _count_T_7 = popc_in[7]; // @[ALU.scala:138:43, :139:23] wire _count_T_8 = popc_in[8]; // @[ALU.scala:138:43, :139:23] wire _count_T_9 = popc_in[9]; // @[ALU.scala:138:43, :139:23] wire _count_T_10 = popc_in[10]; // @[ALU.scala:138:43, :139:23] wire _count_T_11 = popc_in[11]; // @[ALU.scala:138:43, :139:23] wire _count_T_12 = popc_in[12]; // @[ALU.scala:138:43, :139:23] wire _count_T_13 = popc_in[13]; // @[ALU.scala:138:43, :139:23] wire _count_T_14 = popc_in[14]; // @[ALU.scala:138:43, :139:23] wire _count_T_15 = popc_in[15]; // @[ALU.scala:138:43, :139:23] wire _count_T_16 = popc_in[16]; // @[ALU.scala:138:43, :139:23] wire _count_T_17 = popc_in[17]; // @[ALU.scala:138:43, :139:23] wire _count_T_18 = popc_in[18]; // @[ALU.scala:138:43, :139:23] wire _count_T_19 = popc_in[19]; // @[ALU.scala:138:43, :139:23] wire _count_T_20 = popc_in[20]; // @[ALU.scala:138:43, :139:23] wire _count_T_21 = popc_in[21]; // @[ALU.scala:138:43, :139:23] wire _count_T_22 = popc_in[22]; // @[ALU.scala:138:43, :139:23] wire _count_T_23 = popc_in[23]; // @[ALU.scala:138:43, :139:23] wire _count_T_24 = popc_in[24]; // @[ALU.scala:138:43, :139:23] wire _count_T_25 = popc_in[25]; // @[ALU.scala:138:43, :139:23] wire _count_T_26 = popc_in[26]; // @[ALU.scala:138:43, :139:23] wire _count_T_27 = popc_in[27]; // @[ALU.scala:138:43, :139:23] wire _count_T_28 = popc_in[28]; // @[ALU.scala:138:43, :139:23] wire _count_T_29 = popc_in[29]; // @[ALU.scala:138:43, :139:23] wire _count_T_30 = popc_in[30]; // @[ALU.scala:138:43, :139:23] wire _count_T_31 = popc_in[31]; // @[ALU.scala:138:43, :139:23] wire _count_T_32 = popc_in[32]; // @[ALU.scala:138:43, :139:23] wire _count_T_33 = popc_in[33]; // @[ALU.scala:138:43, :139:23] wire _count_T_34 = popc_in[34]; // @[ALU.scala:138:43, :139:23] wire _count_T_35 = popc_in[35]; // @[ALU.scala:138:43, :139:23] wire _count_T_36 = popc_in[36]; // @[ALU.scala:138:43, :139:23] wire _count_T_37 = popc_in[37]; // @[ALU.scala:138:43, :139:23] wire _count_T_38 = popc_in[38]; // @[ALU.scala:138:43, :139:23] wire _count_T_39 = popc_in[39]; // @[ALU.scala:138:43, :139:23] wire _count_T_40 = popc_in[40]; // @[ALU.scala:138:43, :139:23] wire _count_T_41 = popc_in[41]; // @[ALU.scala:138:43, :139:23] wire _count_T_42 = popc_in[42]; // @[ALU.scala:138:43, :139:23] wire _count_T_43 = popc_in[43]; // @[ALU.scala:138:43, :139:23] wire _count_T_44 = popc_in[44]; // @[ALU.scala:138:43, :139:23] wire _count_T_45 = popc_in[45]; // @[ALU.scala:138:43, :139:23] wire _count_T_46 = popc_in[46]; // @[ALU.scala:138:43, :139:23] wire _count_T_47 = popc_in[47]; // @[ALU.scala:138:43, :139:23] wire _count_T_48 = popc_in[48]; // @[ALU.scala:138:43, :139:23] wire _count_T_49 = popc_in[49]; // @[ALU.scala:138:43, :139:23] wire _count_T_50 = popc_in[50]; // @[ALU.scala:138:43, :139:23] wire _count_T_51 = popc_in[51]; // @[ALU.scala:138:43, :139:23] wire _count_T_52 = popc_in[52]; // @[ALU.scala:138:43, :139:23] wire _count_T_53 = popc_in[53]; // @[ALU.scala:138:43, :139:23] wire _count_T_54 = popc_in[54]; // @[ALU.scala:138:43, :139:23] wire _count_T_55 = popc_in[55]; // @[ALU.scala:138:43, :139:23] wire _count_T_56 = popc_in[56]; // @[ALU.scala:138:43, :139:23] wire _count_T_57 = popc_in[57]; // @[ALU.scala:138:43, :139:23] wire _count_T_58 = popc_in[58]; // @[ALU.scala:138:43, :139:23] wire _count_T_59 = popc_in[59]; // @[ALU.scala:138:43, :139:23] wire _count_T_60 = popc_in[60]; // @[ALU.scala:138:43, :139:23] wire _count_T_61 = popc_in[61]; // @[ALU.scala:138:43, :139:23] wire _count_T_62 = popc_in[62]; // @[ALU.scala:138:43, :139:23] wire _count_T_63 = popc_in[63]; // @[ALU.scala:138:43, :139:23] wire [1:0] _count_T_64 = {1'h0, _count_T} + {1'h0, _count_T_1}; // @[ALU.scala:88:26, :139:23] wire [1:0] _count_T_65 = _count_T_64; // @[ALU.scala:139:23] wire [1:0] _count_T_66 = {1'h0, _count_T_2} + {1'h0, _count_T_3}; // @[ALU.scala:88:26, :139:23] wire [1:0] _count_T_67 = _count_T_66; // @[ALU.scala:139:23] wire [2:0] _count_T_68 = {1'h0, _count_T_65} + {1'h0, _count_T_67}; // @[ALU.scala:88:26, :139:23] wire [2:0] _count_T_69 = _count_T_68; // @[ALU.scala:139:23] wire [1:0] _count_T_70 = {1'h0, _count_T_4} + {1'h0, _count_T_5}; // @[ALU.scala:88:26, :139:23] wire [1:0] _count_T_71 = _count_T_70; // @[ALU.scala:139:23] wire [1:0] _count_T_72 = {1'h0, _count_T_6} + {1'h0, _count_T_7}; // @[ALU.scala:88:26, :139:23] wire [1:0] _count_T_73 = _count_T_72; // @[ALU.scala:139:23] wire [2:0] _count_T_74 = {1'h0, _count_T_71} + {1'h0, _count_T_73}; // @[ALU.scala:88:26, :139:23] wire [2:0] _count_T_75 = _count_T_74; // @[ALU.scala:139:23] wire [3:0] _count_T_76 = {1'h0, _count_T_69} + {1'h0, _count_T_75}; // @[ALU.scala:88:26, :139:23] wire [3:0] _count_T_77 = _count_T_76; // @[ALU.scala:139:23] wire [1:0] _count_T_78 = {1'h0, _count_T_8} + {1'h0, _count_T_9}; // @[ALU.scala:88:26, :139:23] wire [1:0] _count_T_79 = _count_T_78; // @[ALU.scala:139:23] wire [1:0] _count_T_80 = {1'h0, _count_T_10} + {1'h0, _count_T_11}; // @[ALU.scala:88:26, :139:23] wire [1:0] _count_T_81 = _count_T_80; // @[ALU.scala:139:23] wire [2:0] _count_T_82 = {1'h0, _count_T_79} + {1'h0, _count_T_81}; // @[ALU.scala:88:26, :139:23] wire [2:0] _count_T_83 = _count_T_82; // @[ALU.scala:139:23] wire [1:0] _count_T_84 = {1'h0, _count_T_12} + {1'h0, _count_T_13}; // @[ALU.scala:88:26, :139:23] wire [1:0] _count_T_85 = _count_T_84; // @[ALU.scala:139:23] wire [1:0] _count_T_86 = {1'h0, _count_T_14} + {1'h0, _count_T_15}; // @[ALU.scala:88:26, :139:23] wire [1:0] _count_T_87 = _count_T_86; // @[ALU.scala:139:23] wire [2:0] _count_T_88 = {1'h0, _count_T_85} + {1'h0, _count_T_87}; // @[ALU.scala:88:26, :139:23] wire [2:0] _count_T_89 = _count_T_88; // @[ALU.scala:139:23] wire [3:0] _count_T_90 = {1'h0, _count_T_83} + {1'h0, _count_T_89}; // @[ALU.scala:88:26, :139:23] wire [3:0] _count_T_91 = _count_T_90; // @[ALU.scala:139:23] wire [4:0] _count_T_92 = {1'h0, _count_T_77} + {1'h0, _count_T_91}; // @[ALU.scala:88:26, :139:23] wire [4:0] _count_T_93 = _count_T_92; // @[ALU.scala:139:23] wire [1:0] _count_T_94 = {1'h0, _count_T_16} + {1'h0, _count_T_17}; // @[ALU.scala:88:26, :139:23] wire [1:0] _count_T_95 = _count_T_94; // @[ALU.scala:139:23] wire [1:0] _count_T_96 = {1'h0, _count_T_18} + {1'h0, _count_T_19}; // @[ALU.scala:88:26, :139:23] wire [1:0] _count_T_97 = _count_T_96; // @[ALU.scala:139:23] wire [2:0] _count_T_98 = {1'h0, _count_T_95} + {1'h0, _count_T_97}; // @[ALU.scala:88:26, :139:23] wire [2:0] _count_T_99 = _count_T_98; // @[ALU.scala:139:23] wire [1:0] _count_T_100 = {1'h0, _count_T_20} + {1'h0, _count_T_21}; // @[ALU.scala:88:26, :139:23] wire [1:0] _count_T_101 = _count_T_100; // @[ALU.scala:139:23] wire [1:0] _count_T_102 = {1'h0, _count_T_22} + {1'h0, _count_T_23}; // @[ALU.scala:88:26, :139:23] wire [1:0] _count_T_103 = _count_T_102; // @[ALU.scala:139:23] wire [2:0] _count_T_104 = {1'h0, _count_T_101} + {1'h0, _count_T_103}; // @[ALU.scala:88:26, :139:23] wire [2:0] _count_T_105 = _count_T_104; // @[ALU.scala:139:23] wire [3:0] _count_T_106 = {1'h0, _count_T_99} + {1'h0, _count_T_105}; // @[ALU.scala:88:26, :139:23] wire [3:0] _count_T_107 = _count_T_106; // @[ALU.scala:139:23] wire [1:0] _count_T_108 = {1'h0, _count_T_24} + {1'h0, _count_T_25}; // @[ALU.scala:88:26, :139:23] wire [1:0] _count_T_109 = _count_T_108; // @[ALU.scala:139:23] wire [1:0] _count_T_110 = {1'h0, _count_T_26} + {1'h0, _count_T_27}; // @[ALU.scala:88:26, :139:23] wire [1:0] _count_T_111 = _count_T_110; // @[ALU.scala:139:23] wire [2:0] _count_T_112 = {1'h0, _count_T_109} + {1'h0, _count_T_111}; // @[ALU.scala:88:26, :139:23] wire [2:0] _count_T_113 = _count_T_112; // @[ALU.scala:139:23] wire [1:0] _count_T_114 = {1'h0, _count_T_28} + {1'h0, _count_T_29}; // @[ALU.scala:88:26, :139:23] wire [1:0] _count_T_115 = _count_T_114; // @[ALU.scala:139:23] wire [1:0] _count_T_116 = {1'h0, _count_T_30} + {1'h0, _count_T_31}; // @[ALU.scala:88:26, :139:23] wire [1:0] _count_T_117 = _count_T_116; // @[ALU.scala:139:23] wire [2:0] _count_T_118 = {1'h0, _count_T_115} + {1'h0, _count_T_117}; // @[ALU.scala:88:26, :139:23] wire [2:0] _count_T_119 = _count_T_118; // @[ALU.scala:139:23] wire [3:0] _count_T_120 = {1'h0, _count_T_113} + {1'h0, _count_T_119}; // @[ALU.scala:88:26, :139:23] wire [3:0] _count_T_121 = _count_T_120; // @[ALU.scala:139:23] wire [4:0] _count_T_122 = {1'h0, _count_T_107} + {1'h0, _count_T_121}; // @[ALU.scala:88:26, :139:23] wire [4:0] _count_T_123 = _count_T_122; // @[ALU.scala:139:23] wire [5:0] _count_T_124 = {1'h0, _count_T_93} + {1'h0, _count_T_123}; // @[ALU.scala:88:26, :139:23] wire [5:0] _count_T_125 = _count_T_124; // @[ALU.scala:139:23] wire [1:0] _count_T_126 = {1'h0, _count_T_32} + {1'h0, _count_T_33}; // @[ALU.scala:88:26, :139:23] wire [1:0] _count_T_127 = _count_T_126; // @[ALU.scala:139:23] wire [1:0] _count_T_128 = {1'h0, _count_T_34} + {1'h0, _count_T_35}; // @[ALU.scala:88:26, :139:23] wire [1:0] _count_T_129 = _count_T_128; // @[ALU.scala:139:23] wire [2:0] _count_T_130 = {1'h0, _count_T_127} + {1'h0, _count_T_129}; // @[ALU.scala:88:26, :139:23] wire [2:0] _count_T_131 = _count_T_130; // @[ALU.scala:139:23] wire [1:0] _count_T_132 = {1'h0, _count_T_36} + {1'h0, _count_T_37}; // @[ALU.scala:88:26, :139:23] wire [1:0] _count_T_133 = _count_T_132; // @[ALU.scala:139:23] wire [1:0] _count_T_134 = {1'h0, _count_T_38} + {1'h0, _count_T_39}; // @[ALU.scala:88:26, :139:23] wire [1:0] _count_T_135 = _count_T_134; // @[ALU.scala:139:23] wire [2:0] _count_T_136 = {1'h0, _count_T_133} + {1'h0, _count_T_135}; // @[ALU.scala:88:26, :139:23] wire [2:0] _count_T_137 = _count_T_136; // @[ALU.scala:139:23] wire [3:0] _count_T_138 = {1'h0, _count_T_131} + {1'h0, _count_T_137}; // @[ALU.scala:88:26, :139:23] wire [3:0] _count_T_139 = _count_T_138; // @[ALU.scala:139:23] wire [1:0] _count_T_140 = {1'h0, _count_T_40} + {1'h0, _count_T_41}; // @[ALU.scala:88:26, :139:23] wire [1:0] _count_T_141 = _count_T_140; // @[ALU.scala:139:23] wire [1:0] _count_T_142 = {1'h0, _count_T_42} + {1'h0, _count_T_43}; // @[ALU.scala:88:26, :139:23] wire [1:0] _count_T_143 = _count_T_142; // @[ALU.scala:139:23] wire [2:0] _count_T_144 = {1'h0, _count_T_141} + {1'h0, _count_T_143}; // @[ALU.scala:88:26, :139:23] wire [2:0] _count_T_145 = _count_T_144; // @[ALU.scala:139:23] wire [1:0] _count_T_146 = {1'h0, _count_T_44} + {1'h0, _count_T_45}; // @[ALU.scala:88:26, :139:23] wire [1:0] _count_T_147 = _count_T_146; // @[ALU.scala:139:23] wire [1:0] _count_T_148 = {1'h0, _count_T_46} + {1'h0, _count_T_47}; // @[ALU.scala:88:26, :139:23] wire [1:0] _count_T_149 = _count_T_148; // @[ALU.scala:139:23] wire [2:0] _count_T_150 = {1'h0, _count_T_147} + {1'h0, _count_T_149}; // @[ALU.scala:88:26, :139:23] wire [2:0] _count_T_151 = _count_T_150; // @[ALU.scala:139:23] wire [3:0] _count_T_152 = {1'h0, _count_T_145} + {1'h0, _count_T_151}; // @[ALU.scala:88:26, :139:23] wire [3:0] _count_T_153 = _count_T_152; // @[ALU.scala:139:23] wire [4:0] _count_T_154 = {1'h0, _count_T_139} + {1'h0, _count_T_153}; // @[ALU.scala:88:26, :139:23] wire [4:0] _count_T_155 = _count_T_154; // @[ALU.scala:139:23] wire [1:0] _count_T_156 = {1'h0, _count_T_48} + {1'h0, _count_T_49}; // @[ALU.scala:88:26, :139:23] wire [1:0] _count_T_157 = _count_T_156; // @[ALU.scala:139:23] wire [1:0] _count_T_158 = {1'h0, _count_T_50} + {1'h0, _count_T_51}; // @[ALU.scala:88:26, :139:23] wire [1:0] _count_T_159 = _count_T_158; // @[ALU.scala:139:23] wire [2:0] _count_T_160 = {1'h0, _count_T_157} + {1'h0, _count_T_159}; // @[ALU.scala:88:26, :139:23] wire [2:0] _count_T_161 = _count_T_160; // @[ALU.scala:139:23] wire [1:0] _count_T_162 = {1'h0, _count_T_52} + {1'h0, _count_T_53}; // @[ALU.scala:88:26, :139:23] wire [1:0] _count_T_163 = _count_T_162; // @[ALU.scala:139:23] wire [1:0] _count_T_164 = {1'h0, _count_T_54} + {1'h0, _count_T_55}; // @[ALU.scala:88:26, :139:23] wire [1:0] _count_T_165 = _count_T_164; // @[ALU.scala:139:23] wire [2:0] _count_T_166 = {1'h0, _count_T_163} + {1'h0, _count_T_165}; // @[ALU.scala:88:26, :139:23] wire [2:0] _count_T_167 = _count_T_166; // @[ALU.scala:139:23] wire [3:0] _count_T_168 = {1'h0, _count_T_161} + {1'h0, _count_T_167}; // @[ALU.scala:88:26, :139:23] wire [3:0] _count_T_169 = _count_T_168; // @[ALU.scala:139:23] wire [1:0] _count_T_170 = {1'h0, _count_T_56} + {1'h0, _count_T_57}; // @[ALU.scala:88:26, :139:23] wire [1:0] _count_T_171 = _count_T_170; // @[ALU.scala:139:23] wire [1:0] _count_T_172 = {1'h0, _count_T_58} + {1'h0, _count_T_59}; // @[ALU.scala:88:26, :139:23] wire [1:0] _count_T_173 = _count_T_172; // @[ALU.scala:139:23] wire [2:0] _count_T_174 = {1'h0, _count_T_171} + {1'h0, _count_T_173}; // @[ALU.scala:88:26, :139:23] wire [2:0] _count_T_175 = _count_T_174; // @[ALU.scala:139:23] wire [1:0] _count_T_176 = {1'h0, _count_T_60} + {1'h0, _count_T_61}; // @[ALU.scala:88:26, :139:23] wire [1:0] _count_T_177 = _count_T_176; // @[ALU.scala:139:23] wire [1:0] _count_T_178 = {1'h0, _count_T_62} + {1'h0, _count_T_63}; // @[ALU.scala:88:26, :139:23] wire [1:0] _count_T_179 = _count_T_178; // @[ALU.scala:139:23] wire [2:0] _count_T_180 = {1'h0, _count_T_177} + {1'h0, _count_T_179}; // @[ALU.scala:88:26, :139:23] wire [2:0] _count_T_181 = _count_T_180; // @[ALU.scala:139:23] wire [3:0] _count_T_182 = {1'h0, _count_T_175} + {1'h0, _count_T_181}; // @[ALU.scala:88:26, :139:23] wire [3:0] _count_T_183 = _count_T_182; // @[ALU.scala:139:23] wire [4:0] _count_T_184 = {1'h0, _count_T_169} + {1'h0, _count_T_183}; // @[ALU.scala:88:26, :139:23] wire [4:0] _count_T_185 = _count_T_184; // @[ALU.scala:139:23] wire [5:0] _count_T_186 = {1'h0, _count_T_155} + {1'h0, _count_T_185}; // @[ALU.scala:88:26, :139:23] wire [5:0] _count_T_187 = _count_T_186; // @[ALU.scala:139:23] wire [6:0] _count_T_188 = {1'h0, _count_T_125} + {1'h0, _count_T_187}; // @[ALU.scala:88:26, :139:23] wire [6:0] count = _count_T_188; // @[ALU.scala:139:23] wire [7:0] _in1_bytes_T; // @[ALU.scala:140:34] wire [7:0] _in1_bytes_T_1; // @[ALU.scala:140:34] wire [7:0] _rev8_WIRE_7 = in1_bytes_0; // @[ALU.scala:140:34, :142:21] wire [7:0] _in1_bytes_T_2; // @[ALU.scala:140:34] wire [7:0] _rev8_WIRE_6 = in1_bytes_1; // @[ALU.scala:140:34, :142:21] wire [7:0] _in1_bytes_T_3; // @[ALU.scala:140:34] wire [7:0] _rev8_WIRE_5 = in1_bytes_2; // @[ALU.scala:140:34, :142:21] wire [7:0] _in1_bytes_T_4; // @[ALU.scala:140:34] wire [7:0] _rev8_WIRE_4 = in1_bytes_3; // @[ALU.scala:140:34, :142:21] wire [7:0] _in1_bytes_T_5; // @[ALU.scala:140:34] wire [7:0] _rev8_WIRE_3 = in1_bytes_4; // @[ALU.scala:140:34, :142:21] wire [7:0] _in1_bytes_T_6; // @[ALU.scala:140:34] wire [7:0] _rev8_WIRE_2 = in1_bytes_5; // @[ALU.scala:140:34, :142:21] wire [7:0] _in1_bytes_T_7; // @[ALU.scala:140:34] wire [7:0] _rev8_WIRE_1 = in1_bytes_6; // @[ALU.scala:140:34, :142:21] wire [7:0] in1_bytes_7; // @[ALU.scala:140:34] wire [7:0] _rev8_WIRE_0 = in1_bytes_7; // @[ALU.scala:140:34, :142:21] assign _in1_bytes_T = _in1_bytes_WIRE[7:0]; // @[ALU.scala:140:34] assign in1_bytes_0 = _in1_bytes_T; // @[ALU.scala:140:34] assign _in1_bytes_T_1 = _in1_bytes_WIRE[15:8]; // @[ALU.scala:140:34] assign in1_bytes_1 = _in1_bytes_T_1; // @[ALU.scala:140:34] assign _in1_bytes_T_2 = _in1_bytes_WIRE[23:16]; // @[ALU.scala:140:34] assign in1_bytes_2 = _in1_bytes_T_2; // @[ALU.scala:140:34] assign _in1_bytes_T_3 = _in1_bytes_WIRE[31:24]; // @[ALU.scala:140:34] assign in1_bytes_3 = _in1_bytes_T_3; // @[ALU.scala:140:34] assign _in1_bytes_T_4 = _in1_bytes_WIRE[39:32]; // @[ALU.scala:140:34] assign in1_bytes_4 = _in1_bytes_T_4; // @[ALU.scala:140:34] assign _in1_bytes_T_5 = _in1_bytes_WIRE[47:40]; // @[ALU.scala:140:34] assign in1_bytes_5 = _in1_bytes_T_5; // @[ALU.scala:140:34] assign _in1_bytes_T_6 = _in1_bytes_WIRE[55:48]; // @[ALU.scala:140:34] assign in1_bytes_6 = _in1_bytes_T_6; // @[ALU.scala:140:34] assign _in1_bytes_T_7 = _in1_bytes_WIRE[63:56]; // @[ALU.scala:140:34] assign in1_bytes_7 = _in1_bytes_T_7; // @[ALU.scala:140:34] wire _orcb_T = \|in1_bytes_0; // @[ALU.scala:140:34, :141:51] wire [7:0] _orcb_T_1 = {8{_orcb_T}}; // @[ALU.scala:141:{45,51}] wire [7:0] _orcb_WIRE_0 = _orcb_T_1; // @[ALU.scala:141:{21,45}] wire _orcb_T_2 = \|in1_bytes_1; // @[ALU.scala:140:34, :141:51] wire [7:0] _orcb_T_3 = {8{_orcb_T_2}}; // @[ALU.scala:141:{45,51}] wire [7:0] _orcb_WIRE_1 = _orcb_T_3; // @[ALU.scala:141:{21,45}] wire _orcb_T_4 = \|in1_bytes_2; // @[ALU.scala:140:34, :141:51] wire [7:0] _orcb_T_5 = {8{_orcb_T_4}}; // @[ALU.scala:141:{45,51}] wire [7:0] _orcb_WIRE_2 = _orcb_T_5; // @[ALU.scala:141:{21,45}] wire _orcb_T_6 = \|in1_bytes_3; // @[ALU.scala:140:34, :141:51] wire [7:0] _orcb_T_7 = {8{_orcb_T_6}}; // @[ALU.scala:141:{45,51}] wire [7:0] _orcb_WIRE_3 = _orcb_T_7; // @[ALU.scala:141:{21,45}] wire _orcb_T_8 = \|in1_bytes_4; // @[ALU.scala:140:34, :141:51] wire [7:0] _orcb_T_9 = {8{_orcb_T_8}}; // @[ALU.scala:141:{45,51}] wire [7:0] _orcb_WIRE_4 = _orcb_T_9; // @[ALU.scala:141:{21,45}] wire _orcb_T_10 = \|in1_bytes_5; // @[ALU.scala:140:34, :141:51] wire [7:0] _orcb_T_11 = {8{_orcb_T_10}}; // @[ALU.scala:141:{45,51}] wire [7:0] _orcb_WIRE_5 = _orcb_T_11; // @[ALU.scala:141:{21,45}] wire _orcb_T_12 = \|in1_bytes_6; // @[ALU.scala:140:34, :141:51] wire [7:0] _orcb_T_13 = {8{_orcb_T_12}}; // @[ALU.scala:141:{45,51}] wire [7:0] _orcb_WIRE_6 = _orcb_T_13; // @[ALU.scala:141:{21,45}] wire _orcb_T_14 = \|in1_bytes_7; // @[ALU.scala:140:34, :141:51] wire [7:0] _orcb_T_15 = {8{_orcb_T_14}}; // @[ALU.scala:141:{45,51}] wire [7:0] _orcb_WIRE_7 = _orcb_T_15; // @[ALU.scala:141:{21,45}] wire [15:0] orcb_lo_lo = {_orcb_WIRE_1, _orcb_WIRE_0}; // @[ALU.scala:141:{21,62}] wire [15:0] orcb_lo_hi = {_orcb_WIRE_3, _orcb_WIRE_2}; // @[ALU.scala:141:{21,62}] wire [31:0] orcb_lo = {orcb_lo_hi, orcb_lo_lo}; // @[ALU.scala:141:62] wire [15:0] orcb_hi_lo = {_orcb_WIRE_5, _orcb_WIRE_4}; // @[ALU.scala:141:{21,62}] wire [15:0] orcb_hi_hi = {_orcb_WIRE_7, _orcb_WIRE_6}; // @[ALU.scala:141:{21,62}] wire [31:0] orcb_hi = {orcb_hi_hi, orcb_hi_lo}; // @[ALU.scala:141:62] wire [63:0] orcb = {orcb_hi, orcb_lo}; // @[ALU.scala:141:62] wire [15:0] rev8_lo_lo = {_rev8_WIRE_1, _rev8_WIRE_0}; // @[ALU.scala:142:{21,41}] wire [15:0] rev8_lo_hi = {_rev8_WIRE_3, _rev8_WIRE_2}; // @[ALU.scala:142:{21,41}] wire [31:0] rev8_lo = {rev8_lo_hi, rev8_lo_lo}; // @[ALU.scala:142:41] wire [15:0] rev8_hi_lo = {_rev8_WIRE_5, _rev8_WIRE_4}; // @[ALU.scala:142:{21,41}] wire [15:0] rev8_hi_hi = {_rev8_WIRE_7, _rev8_WIRE_6}; // @[ALU.scala:142:{21,41}] wire [31:0] rev8_hi = {rev8_hi_hi, rev8_hi_lo}; // @[ALU.scala:142:41] wire [63:0] rev8 = {rev8_hi, rev8_lo}; // @[ALU.scala:142:41] wire [11:0] _unary_T = io_in2_0[11:0]; // @[ALU.scala:83:7, :143:31] wire [15:0] _unary_T_1 = io_in1_0[15:0]; // @[ALU.scala:83:7, :146:22] wire [15:0] _unary_T_8 = io_in1_0[15:0]; // @[ALU.scala:83:7, :146:22, :148:51] wire _unary_T_2 = io_in1_0[7]; // @[ALU.scala:83:7, :147:35] wire [55:0] _unary_T_3 = {56{_unary_T_2}}; // @[ALU.scala:147:{20,35}] wire [7:0] _unary_T_4 = io_in1_0[7:0]; // @[ALU.scala:83:7, :147:49] wire [63:0] _unary_T_5 = {_unary_T_3, _unary_T_4}; // @[ALU.scala:147:{20,40,49}] wire _unary_T_6 = io_in1_0[15]; // @[ALU.scala:83:7, :148:36] wire [47:0] _unary_T_7 = {48{_unary_T_6}}; // @[ALU.scala:148:{20,36}] wire [63:0] _unary_T_9 = {_unary_T_7, _unary_T_8}; // @[ALU.scala:148:{20,42,51}] wire _unary_T_10 = _unary_T == 12'h287; // @[ALU.scala:143:{31,45}] wire [63:0] _unary_T_11 = _unary_T_10 ? orcb : {57'h0, count}; // @[ALU.scala:139:23, :141:62, :143:45] wire _unary_T_12 = _unary_T == 12'h6B8; // @[ALU.scala:143:{31,45}] wire [63:0] _unary_T_13 = _unary_T_12 ? rev8 : _unary_T_11; // @[ALU.scala:142:41, :143:45] wire _unary_T_14 = _unary_T == 12'h80; // @[ALU.scala:143:{31,45}] wire [63:0] _unary_T_15 = _unary_T_14 ? {48'h0, _unary_T_1} : _unary_T_13; // @[ALU.scala:143:45, :146:22] wire _unary_T_16 = _unary_T == 12'h604; // @[ALU.scala:143:{31,45}] wire [63:0] _unary_T_17 = _unary_T_16 ? _unary_T_5 : _unary_T_15; // @[ALU.scala:143:45, :147:40] wire _unary_T_18 = _unary_T == 12'h605; // @[ALU.scala:143:{31,45}] wire [63:0] unary = _unary_T_18 ? _unary_T_9 : _unary_T_17; // @[ALU.scala:143:45, :148:42] wire [63:0] maxmin_out = io_cmp_out_0 ? io_in2_0 : io_in1_0; // @[ALU.scala:83:7, :152:23] wire _rot_shamt_T = ~io_dw_0; // @[ALU.scala:83:7, :130:32, :155:29] wire [6:0] _rot_shamt_T_1 = _rot_shamt_T ? 7'h20 : 7'h40; // @[ALU.scala:155:{22,29}] wire [7:0] _rot_shamt_T_2 = {1'h0, _rot_shamt_T_1} - {2'h0, shamt}; // @[package.scala:16:47] wire [6:0] rot_shamt = _rot_shamt_T_2[6:0]; // @[ALU.scala:155:54] wire [63:0] _rotin_T_4 = {32'h0, _rotin_T_3}; // @[ALU.scala:156:44] wire [63:0] _rotin_T_6 = {_rotin_T_5, 32'h0}; // @[ALU.scala:156:44] wire [63:0] _rotin_T_8 = _rotin_T_6 & 64'hFFFFFFFF00000000; // @[ALU.scala:156:44] wire [63:0] _rotin_T_9 = _rotin_T_4 \| _rotin_T_8; // @[ALU.scala:156:44] wire [47:0] _rotin_T_13 = _rotin_T_9[63:16]; // @[ALU.scala:156:44] wire [63:0] _rotin_T_14 = {16'h0, _rotin_T_13 & 48'hFFFF0000FFFF}; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [47:0] _rotin_T_15 = _rotin_T_9[47:0]; // @[ALU.scala:156:44] wire [63:0] _rotin_T_16 = {_rotin_T_15, 16'h0}; // @[ALU.scala:106:46, :156:44] wire [63:0] _rotin_T_18 = _rotin_T_16 & 64'hFFFF0000FFFF0000; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _rotin_T_19 = _rotin_T_14 \| _rotin_T_18; // @[ALU.scala:156:44] wire [55:0] _rotin_T_23 = _rotin_T_19[63:8]; // @[ALU.scala:156:44] wire [63:0] _rotin_T_24 = {8'h0, _rotin_T_23 & 56'hFF00FF00FF00FF}; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [55:0] _rotin_T_25 = _rotin_T_19[55:0]; // @[ALU.scala:156:44] wire [63:0] _rotin_T_26 = {_rotin_T_25, 8'h0}; // @[ALU.scala:156:44] wire [63:0] _rotin_T_28 = _rotin_T_26 & 64'hFF00FF00FF00FF00; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _rotin_T_29 = _rotin_T_24 \| _rotin_T_28; // @[ALU.scala:156:44] wire [59:0] _rotin_T_33 = _rotin_T_29[63:4]; // @[ALU.scala:156:44] wire [63:0] _rotin_T_34 = {4'h0, _rotin_T_33 & 60'hF0F0F0F0F0F0F0F}; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [59:0] _rotin_T_35 = _rotin_T_29[59:0]; // @[ALU.scala:156:44] wire [63:0] _rotin_T_36 = {_rotin_T_35, 4'h0}; // @[ALU.scala:106:46, :156:44] wire [63:0] _rotin_T_38 = _rotin_T_36 & 64'hF0F0F0F0F0F0F0F0; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _rotin_T_39 = _rotin_T_34 \| _rotin_T_38; // @[ALU.scala:156:44] wire [61:0] _rotin_T_43 = _rotin_T_39[63:2]; // @[ALU.scala:156:44] wire [63:0] _rotin_T_44 = {2'h0, _rotin_T_43 & 62'h3333333333333333}; // @[package.scala:16:47] wire [61:0] _rotin_T_45 = _rotin_T_39[61:0]; // @[ALU.scala:156:44] wire [63:0] _rotin_T_46 = {_rotin_T_45, 2'h0}; // @[package.scala:16:47] wire [63:0] _rotin_T_48 = _rotin_T_46 & 64'hCCCCCCCCCCCCCCCC; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _rotin_T_49 = _rotin_T_44 \| _rotin_T_48; // @[ALU.scala:156:44] wire [62:0] _rotin_T_53 = _rotin_T_49[63:1]; // @[ALU.scala:156:44] wire [63:0] _rotin_T_54 = {1'h0, _rotin_T_53 & 63'h5555555555555555}; // @[ALU.scala:88:26, :106:46, :108:24, :132:19, :156:44, :158:25] wire [62:0] _rotin_T_55 = _rotin_T_49[62:0]; // @[ALU.scala:156:44] wire [63:0] _rotin_T_56 = {_rotin_T_55, 1'h0}; // @[ALU.scala:88:26, :156:44] wire [63:0] _rotin_T_58 = _rotin_T_56 & 64'hAAAAAAAAAAAAAAAA; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _rotin_T_59 = _rotin_T_54 \| _rotin_T_58; // @[ALU.scala:156:44] wire [63:0] rotin = _rotin_T ? shin_r : _rotin_T_59; // @[ALU.scala:104:18, :156:{18,24,44}] wire [63:0] _rotout_r_T = rotin >> rot_shamt; // @[ALU.scala:155:54, :156:18, :157:25] wire [63:0] rotout_r = _rotout_r_T; // @[ALU.scala:157:{25,38}] wire [31:0] _rotout_l_T_2 = rotout_r[63:32]; // @[ALU.scala:157:38, :158:25] wire [63:0] _rotout_l_T_3 = {32'h0, _rotout_l_T_2}; // @[ALU.scala:158:25] wire [31:0] _rotout_l_T_4 = rotout_r[31:0]; // @[ALU.scala:157:38, :158:25] wire [63:0] _rotout_l_T_5 = {_rotout_l_T_4, 32'h0}; // @[ALU.scala:158:25] wire [63:0] _rotout_l_T_7 = _rotout_l_T_5 & 64'hFFFFFFFF00000000; // @[ALU.scala:158:25] wire [63:0] _rotout_l_T_8 = _rotout_l_T_3 \| _rotout_l_T_7; // @[ALU.scala:158:25] wire [47:0] _rotout_l_T_12 = _rotout_l_T_8[63:16]; // @[ALU.scala:158:25] wire [63:0] _rotout_l_T_13 = {16'h0, _rotout_l_T_12 & 48'hFFFF0000FFFF}; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [47:0] _rotout_l_T_14 = _rotout_l_T_8[47:0]; // @[ALU.scala:158:25] wire [63:0] _rotout_l_T_15 = {_rotout_l_T_14, 16'h0}; // @[ALU.scala:106:46, :158:25] wire [63:0] _rotout_l_T_17 = _rotout_l_T_15 & 64'hFFFF0000FFFF0000; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _rotout_l_T_18 = _rotout_l_T_13 \| _rotout_l_T_17; // @[ALU.scala:158:25] wire [55:0] _rotout_l_T_22 = _rotout_l_T_18[63:8]; // @[ALU.scala:158:25] wire [63:0] _rotout_l_T_23 = {8'h0, _rotout_l_T_22 & 56'hFF00FF00FF00FF}; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [55:0] _rotout_l_T_24 = _rotout_l_T_18[55:0]; // @[ALU.scala:158:25] wire [63:0] _rotout_l_T_25 = {_rotout_l_T_24, 8'h0}; // @[ALU.scala:158:25] wire [63:0] _rotout_l_T_27 = _rotout_l_T_25 & 64'hFF00FF00FF00FF00; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _rotout_l_T_28 = _rotout_l_T_23 \| _rotout_l_T_27; // @[ALU.scala:158:25] wire [59:0] _rotout_l_T_32 = _rotout_l_T_28[63:4]; // @[ALU.scala:158:25] wire [63:0] _rotout_l_T_33 = {4'h0, _rotout_l_T_32 & 60'hF0F0F0F0F0F0F0F}; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [59:0] _rotout_l_T_34 = _rotout_l_T_28[59:0]; // @[ALU.scala:158:25] wire [63:0] _rotout_l_T_35 = {_rotout_l_T_34, 4'h0}; // @[ALU.scala:106:46, :158:25] wire [63:0] _rotout_l_T_37 = _rotout_l_T_35 & 64'hF0F0F0F0F0F0F0F0; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _rotout_l_T_38 = _rotout_l_T_33 \| _rotout_l_T_37; // @[ALU.scala:158:25] wire [61:0] _rotout_l_T_42 = _rotout_l_T_38[63:2]; // @[ALU.scala:158:25] wire [63:0] _rotout_l_T_43 = {2'h0, _rotout_l_T_42 & 62'h3333333333333333}; // @[package.scala:16:47] wire [61:0] _rotout_l_T_44 = _rotout_l_T_38[61:0]; // @[ALU.scala:158:25] wire [63:0] _rotout_l_T_45 = {_rotout_l_T_44, 2'h0}; // @[package.scala:16:47] wire [63:0] _rotout_l_T_47 = _rotout_l_T_45 & 64'hCCCCCCCCCCCCCCCC; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] _rotout_l_T_48 = _rotout_l_T_43 \| _rotout_l_T_47; // @[ALU.scala:158:25] wire [62:0] _rotout_l_T_52 = _rotout_l_T_48[63:1]; // @[ALU.scala:158:25] wire [63:0] _rotout_l_T_53 = {1'h0, _rotout_l_T_52 & 63'h5555555555555555}; // @[ALU.scala:88:26, :106:46, :108:24, :132:19, :156:44, :158:25] wire [62:0] _rotout_l_T_54 = _rotout_l_T_48[62:0]; // @[ALU.scala:158:25] wire [63:0] _rotout_l_T_55 = {_rotout_l_T_54, 1'h0}; // @[ALU.scala:88:26, :158:25] wire [63:0] _rotout_l_T_57 = _rotout_l_T_55 & 64'hAAAAAAAAAAAAAAAA; // @[ALU.scala:106:46, :108:24, :132:19, :156:44, :158:25] wire [63:0] rotout_l = _rotout_l_T_53 \| _rotout_l_T_57; // @[ALU.scala:158:25] wire [63:0] _rotout_T_1 = _rotout_T ? rotout_r : rotout_l; // @[ALU.scala:157:38, :158:25, :159:{19,25}] wire [63:0] _rotout_T_3 = _rotout_T_2 ? shout_l : shout_r; // @[ALU.scala:107:73, :108:24, :159:{55,61}] wire [63:0] rotout = _rotout_T_1 \| _rotout_T_3; // @[ALU.scala:159:{19,50,55}] wire _out_T = io_fn_0 == 5'h0; // @[ALU.scala:83:7, :161:47] wire [63:0] _out_T_1 = _out_T ? io_adder_out_0 : shift_logic; // @[ALU.scala:83:7, :123:52, :161:47] wire _out_T_2 = io_fn_0 == 5'hA; // @[ALU.scala:83:7, :161:47] wire [63:0] _out_T_3 = _out_T_2 ? io_adder_out_0 : _out_T_1; // @[ALU.scala:83:7, :161:47] wire _out_T_4 = io_fn_0 == 5'h10; // @[ALU.scala:83:7, :161:47] wire [63:0] _out_T_5 = _out_T_4 ? unary : _out_T_3; // @[ALU.scala:143:45, :161:47] wire _out_T_6 = io_fn_0 == 5'h1C; // @[ALU.scala:83:7, :161:47] wire [63:0] _out_T_7 = _out_T_6 ? maxmin_out : _out_T_5; // @[ALU.scala:152:23, :161:47] wire _out_T_8 = io_fn_0 == 5'h1D; // @[ALU.scala:83:7, :161:47] wire [63:0] _out_T_9 = _out_T_8 ? maxmin_out : _out_T_7; // @[ALU.scala:152:23, :161:47] wire _out_T_10 = io_fn_0 == 5'h1E; // @[ALU.scala:83:7, :161:47] wire [63:0] _out_T_11 = _out_T_10 ? maxmin_out : _out_T_9; // @[ALU.scala:152:23, :161:47] wire _out_T_12 = &io_fn_0; // @[ALU.scala:83:7, :161:47] wire [63:0] _out_T_13 = _out_T_12 ? maxmin_out : _out_T_11; // @[ALU.scala:152:23, :161:47] wire _out_T_14 = io_fn_0 == 5'h11; // @[ALU.scala:83:7, :161:47] wire [63:0] _out_T_15 = _out_T_14 ? rotout : _out_T_13; // @[ALU.scala:159:50, :161:47] wire [63:0] out = _out_T_16 ? rotout : _out_T_15; // @[ALU.scala:159:50, :161:47] wire _io_out_T = out[31]; // @[ALU.scala:161:47, :178:56] wire [31:0] _io_out_T_1 = {32{_io_out_T}}; // @[ALU.scala:178:{48,56}] wire [31:0] _io_out_T_2 = out[31:0]; // @[ALU.scala:161:47, :178:66] wire [63:0] _io_out_T_3 = {_io_out_T_1, _io_out_T_2}; // @[ALU.scala:178:{43,48,66}] assign io_out_0 = io_dw_0 ? out : _io_out_T_3; // @[ALU.scala:83:7, :161:47, :175:10, :178:{28,37,43}] assign io_out = io_out_0; // @[ALU.scala:83:7] assign io_adder_out = io_adder_out_0; // @[ALU.scala:83:7] assign io_cmp_out = io_cmp_out_0; // @[ALU.scala:83:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module ShiftQueue_5 : input clock : Clock input reset : Reset output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { btb : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<5>, bht : { history : UInt<8>, value : UInt<1>}}, pc : UInt<40>, data : UInt<32>, mask : UInt<2>, xcpt : { pf : { inst : UInt<1>}, gf : { inst : UInt<1>}, ae : { inst : UInt<1>}}, replay : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { btb : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<5>, bht : { history : UInt<8>, value : UInt<1>}}, pc : UInt<40>, data : UInt<32>, mask : UInt<2>, xcpt : { pf : { inst : UInt<1>}, gf : { inst : UInt<1>}, ae : { inst : UInt<1>}}, replay : UInt<1>}}, count : UInt<3>, mask : UInt<5>} wire _valid_WIRE : UInt<1>[5] connect _valid_WIRE[0], UInt<1>(0h0) connect _valid_WIRE[1], UInt<1>(0h0) connect _valid_WIRE[2], UInt<1>(0h0) connect _valid_WIRE[3], UInt<1>(0h0) connect _valid_WIRE[4], UInt<1>(0h0) regreset valid : UInt<1>[5], clock, reset, _valid_WIRE reg elts : { btb : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<5>, bht : { history : UInt<8>, value : UInt<1>}}, pc : UInt<40>, data : UInt<32>, mask : UInt<2>, xcpt : { pf : { inst : UInt<1>}, gf : { inst : UInt<1>}, ae : { inst : UInt<1>}}, replay : UInt<1>}[5], clock node wdata = mux(valid[1], elts[1], io.enq.bits) node _wen_T = and(io.enq.ready, io.enq.valid) node _wen_T_1 = or(UInt<1>(0h0), valid[0]) node _wen_T_2 = and(_wen_T, _wen_T_1) node _wen_T_3 = or(valid[1], _wen_T_2) node _wen_T_4 = and(io.enq.ready, io.enq.valid) node _wen_T_5 = and(_wen_T_4, UInt<1>(0h1)) node _wen_T_6 = eq(valid[0], UInt<1>(0h0)) node _wen_T_7 = and(_wen_T_5, _wen_T_6) node wen = mux(io.deq.ready, _wen_T_3, _wen_T_7) when wen : connect elts[0], wdata node _valid_0_T = and(io.enq.ready, io.enq.valid) node _valid_0_T_1 = or(UInt<1>(0h0), valid[0]) node _valid_0_T_2 = and(_valid_0_T, _valid_0_T_1) node _valid_0_T_3 = or(valid[1], _valid_0_T_2) node _valid_0_T_4 = and(io.enq.ready, io.enq.valid) node _valid_0_T_5 = and(_valid_0_T_4, UInt<1>(0h1)) node _valid_0_T_6 = or(_valid_0_T_5, valid[0]) node _valid_0_T_7 = mux(io.deq.ready, _valid_0_T_3, _valid_0_T_6) connect valid[0], _valid_0_T_7 node wdata_1 = mux(valid[2], elts[2], io.enq.bits) node _wen_T_8 = and(io.enq.ready, io.enq.valid) node _wen_T_9 = or(UInt<1>(0h0), valid[1]) node _wen_T_10 = and(_wen_T_8, _wen_T_9) node _wen_T_11 = or(valid[2], _wen_T_10) node _wen_T_12 = and(io.enq.ready, io.enq.valid) node _wen_T_13 = and(_wen_T_12, valid[0]) node _wen_T_14 = eq(valid[1], UInt<1>(0h0)) node _wen_T_15 = and(_wen_T_13, _wen_T_14) node wen_1 = mux(io.deq.ready, _wen_T_11, _wen_T_15) when wen_1 : connect elts[1], wdata_1 node _valid_1_T = and(io.enq.ready, io.enq.valid) node _valid_1_T_1 = or(UInt<1>(0h0), valid[1]) node _valid_1_T_2 = and(_valid_1_T, _valid_1_T_1) node _valid_1_T_3 = or(valid[2], _valid_1_T_2) node _valid_1_T_4 = and(io.enq.ready, io.enq.valid) node _valid_1_T_5 = and(_valid_1_T_4, valid[0]) node _valid_1_T_6 = or(_valid_1_T_5, valid[1]) node _valid_1_T_7 = mux(io.deq.ready, _valid_1_T_3, _valid_1_T_6) connect valid[1], _valid_1_T_7 node wdata_2 = mux(valid[3], elts[3], io.enq.bits) node _wen_T_16 = and(io.enq.ready, io.enq.valid) node _wen_T_17 = or(UInt<1>(0h0), valid[2]) node _wen_T_18 = and(_wen_T_16, _wen_T_17) node _wen_T_19 = or(valid[3], _wen_T_18) node _wen_T_20 = and(io.enq.ready, io.enq.valid) node _wen_T_21 = and(_wen_T_20, valid[1]) node _wen_T_22 = eq(valid[2], UInt<1>(0h0)) node _wen_T_23 = and(_wen_T_21, _wen_T_22) node wen_2 = mux(io.deq.ready, _wen_T_19, _wen_T_23) when wen_2 : connect elts[2], wdata_2 node _valid_2_T = and(io.enq.ready, io.enq.valid) node _valid_2_T_1 = or(UInt<1>(0h0), valid[2]) node _valid_2_T_2 = and(_valid_2_T, _valid_2_T_1) node _valid_2_T_3 = or(valid[3], _valid_2_T_2) node _valid_2_T_4 = and(io.enq.ready, io.enq.valid) node _valid_2_T_5 = and(_valid_2_T_4, valid[1]) node _valid_2_T_6 = or(_valid_2_T_5, valid[2]) node _valid_2_T_7 = mux(io.deq.ready, _valid_2_T_3, _valid_2_T_6) connect valid[2], _valid_2_T_7 node wdata_3 = mux(valid[4], elts[4], io.enq.bits) node _wen_T_24 = and(io.enq.ready, io.enq.valid) node _wen_T_25 = or(UInt<1>(0h0), valid[3]) node _wen_T_26 = and(_wen_T_24, _wen_T_25) node _wen_T_27 = or(valid[4], _wen_T_26) node _wen_T_28 = and(io.enq.ready, io.enq.valid) node _wen_T_29 = and(_wen_T_28, valid[2]) node _wen_T_30 = eq(valid[3], UInt<1>(0h0)) node _wen_T_31 = and(_wen_T_29, _wen_T_30) node wen_3 = mux(io.deq.ready, _wen_T_27, _wen_T_31) when wen_3 : connect elts[3], wdata_3 node _valid_3_T = and(io.enq.ready, io.enq.valid) node _valid_3_T_1 = or(UInt<1>(0h0), valid[3]) node _valid_3_T_2 = and(_valid_3_T, _valid_3_T_1) node _valid_3_T_3 = or(valid[4], _valid_3_T_2) node _valid_3_T_4 = and(io.enq.ready, io.enq.valid) node _valid_3_T_5 = and(_valid_3_T_4, valid[2]) node _valid_3_T_6 = or(_valid_3_T_5, valid[3]) node _valid_3_T_7 = mux(io.deq.ready, _valid_3_T_3, _valid_3_T_6) connect valid[3], _valid_3_T_7 node _wen_T_32 = and(io.enq.ready, io.enq.valid) node _wen_T_33 = or(UInt<1>(0h0), valid[4]) node _wen_T_34 = and(_wen_T_32, _wen_T_33) node _wen_T_35 = or(UInt<1>(0h0), _wen_T_34) node _wen_T_36 = and(io.enq.ready, io.enq.valid) node _wen_T_37 = and(_wen_T_36, valid[3]) node _wen_T_38 = eq(valid[4], UInt<1>(0h0)) node _wen_T_39 = and(_wen_T_37, _wen_T_38) node wen_4 = mux(io.deq.ready, _wen_T_35, _wen_T_39) when wen_4 : connect elts[4], io.enq.bits node _valid_4_T = and(io.enq.ready, io.enq.valid) node _valid_4_T_1 = or(UInt<1>(0h0), valid[4]) node _valid_4_T_2 = and(_valid_4_T, _valid_4_T_1) node _valid_4_T_3 = or(UInt<1>(0h0), _valid_4_T_2) node _valid_4_T_4 = and(io.enq.ready, io.enq.valid) node _valid_4_T_5 = and(_valid_4_T_4, valid[3]) node _valid_4_T_6 = or(_valid_4_T_5, valid[4]) node _valid_4_T_7 = mux(io.deq.ready, _valid_4_T_3, _valid_4_T_6) connect valid[4], _valid_4_T_7 node _io_enq_ready_T = eq(valid[4], UInt<1>(0h0)) connect io.enq.ready, _io_enq_ready_T connect io.deq.valid, valid[0] connect io.deq.bits, elts[0] when io.enq.valid : connect io.deq.valid, UInt<1>(0h1) node _T = eq(valid[0], UInt<1>(0h0)) when _T : connect io.deq.bits, io.enq.bits node io_mask_lo = cat(valid[1], valid[0]) node io_mask_hi_hi = cat(valid[4], valid[3]) node io_mask_hi = cat(io_mask_hi_hi, valid[2]) node _io_mask_T = cat(io_mask_hi, io_mask_lo) connect io.mask, _io_mask_T node _io_count_T = bits(io.mask, 0, 0) node _io_count_T_1 = bits(io.mask, 1, 1) node _io_count_T_2 = bits(io.mask, 2, 2) node _io_count_T_3 = bits(io.mask, 3, 3) node _io_count_T_4 = bits(io.mask, 4, 4) node _io_count_T_5 = add(_io_count_T, _io_count_T_1) node _io_count_T_6 = bits(_io_count_T_5, 1, 0) node _io_count_T_7 = add(_io_count_T_3, _io_count_T_4) node _io_count_T_8 = bits(_io_count_T_7, 1, 0) node _io_count_T_9 = add(_io_count_T_2, _io_count_T_8) node _io_count_T_10 = bits(_io_count_T_9, 1, 0) node _io_count_T_11 = add(_io_count_T_6, _io_count_T_10) node _io_count_T_12 = bits(_io_count_T_11, 2, 0) connect io.count, _io_count_T_12	module ShiftQueue_5( // @[ShiftQueue.scala:12:7] input clock, // @[ShiftQueue.scala:12:7] input reset, // @[ShiftQueue.scala:12:7] output io_enq_ready, // @[ShiftQueue.scala:17:14] input io_enq_valid, // @[ShiftQueue.scala:17:14] input [1:0] io_enq_bits_btb_cfiType, // @[ShiftQueue.scala:17:14] input io_enq_bits_btb_taken, // @[ShiftQueue.scala:17:14] input [1:0] io_enq_bits_btb_mask, // @[ShiftQueue.scala:17:14] input io_enq_bits_btb_bridx, // @[ShiftQueue.scala:17:14] input [38:0] io_enq_bits_btb_target, // @[ShiftQueue.scala:17:14] input [4:0] io_enq_bits_btb_entry, // @[ShiftQueue.scala:17:14] input [7:0] io_enq_bits_btb_bht_history, // @[ShiftQueue.scala:17:14] input io_enq_bits_btb_bht_value, // @[ShiftQueue.scala:17:14] input [39:0] io_enq_bits_pc, // @[ShiftQueue.scala:17:14] input [31:0] io_enq_bits_data, // @[ShiftQueue.scala:17:14] input [1:0] io_enq_bits_mask, // @[ShiftQueue.scala:17:14] input io_enq_bits_xcpt_pf_inst, // @[ShiftQueue.scala:17:14] input io_enq_bits_xcpt_ae_inst, // @[ShiftQueue.scala:17:14] input io_enq_bits_replay, // @[ShiftQueue.scala:17:14] input io_deq_ready, // @[ShiftQueue.scala:17:14] output io_deq_valid, // @[ShiftQueue.scala:17:14] output [1:0] io_deq_bits_btb_cfiType, // @[ShiftQueue.scala:17:14] output io_deq_bits_btb_taken, // @[ShiftQueue.scala:17:14] output [1:0] io_deq_bits_btb_mask, // @[ShiftQueue.scala:17:14] output io_deq_bits_btb_bridx, // @[ShiftQueue.scala:17:14] output [38:0] io_deq_bits_btb_target, // @[ShiftQueue.scala:17:14] output [4:0] io_deq_bits_btb_entry, // @[ShiftQueue.scala:17:14] output [7:0] io_deq_bits_btb_bht_history, // @[ShiftQueue.scala:17:14] output io_deq_bits_btb_bht_value, // @[ShiftQueue.scala:17:14] output [39:0] io_deq_bits_pc, // @[ShiftQueue.scala:17:14] output [31:0] io_deq_bits_data, // @[ShiftQueue.scala:17:14] output [1:0] io_deq_bits_mask, // @[ShiftQueue.scala:17:14] output io_deq_bits_xcpt_pf_inst, // @[ShiftQueue.scala:17:14] output io_deq_bits_xcpt_gf_inst, // @[ShiftQueue.scala:17:14] output io_deq_bits_xcpt_ae_inst, // @[ShiftQueue.scala:17:14] output io_deq_bits_replay, // @[ShiftQueue.scala:17:14] output [4:0] io_mask // @[ShiftQueue.scala:17:14] ); wire io_enq_valid_0 = io_enq_valid; // @[ShiftQueue.scala:12:7] wire [1:0] io_enq_bits_btb_cfiType_0 = io_enq_bits_btb_cfiType; // @[ShiftQueue.scala:12:7] wire io_enq_bits_btb_taken_0 = io_enq_bits_btb_taken; // @[ShiftQueue.scala:12:7] wire [1:0] io_enq_bits_btb_mask_0 = io_enq_bits_btb_mask; // @[ShiftQueue.scala:12:7] wire io_enq_bits_btb_bridx_0 = io_enq_bits_btb_bridx; // @[ShiftQueue.scala:12:7] wire [38:0] io_enq_bits_btb_target_0 = io_enq_bits_btb_target; // @[ShiftQueue.scala:12:7] wire [4:0] io_enq_bits_btb_entry_0 = io_enq_bits_btb_entry; // @[ShiftQueue.scala:12:7] wire [7:0] io_enq_bits_btb_bht_history_0 = io_enq_bits_btb_bht_history; // @[ShiftQueue.scala:12:7] wire io_enq_bits_btb_bht_value_0 = io_enq_bits_btb_bht_value; // @[ShiftQueue.scala:12:7] wire [39:0] io_enq_bits_pc_0 = io_enq_bits_pc; // @[ShiftQueue.scala:12:7] wire [31:0] io_enq_bits_data_0 = io_enq_bits_data; // @[ShiftQueue.scala:12:7] wire [1:0] io_enq_bits_mask_0 = io_enq_bits_mask; // @[ShiftQueue.scala:12:7] wire io_enq_bits_xcpt_pf_inst_0 = io_enq_bits_xcpt_pf_inst; // @[ShiftQueue.scala:12:7] wire io_enq_bits_xcpt_ae_inst_0 = io_enq_bits_xcpt_ae_inst; // @[ShiftQueue.scala:12:7] wire io_enq_bits_replay_0 = io_enq_bits_replay; // @[ShiftQueue.scala:12:7] wire io_deq_ready_0 = io_deq_ready; // @[ShiftQueue.scala:12:7] wire io_enq_bits_xcpt_gf_inst = 1'h0; // @[ShiftQueue.scala:12:7] wire _valid_WIRE_0 = 1'h0; // @[ShiftQueue.scala:21:38] wire _valid_WIRE_1 = 1'h0; // @[ShiftQueue.scala:21:38] wire _valid_WIRE_2 = 1'h0; // @[ShiftQueue.scala:21:38] wire _valid_WIRE_3 = 1'h0; // @[ShiftQueue.scala:21:38] wire _valid_WIRE_4 = 1'h0; // @[ShiftQueue.scala:21:38] wire _io_enq_ready_T; // @[ShiftQueue.scala:40:19] wire [2:0] _io_count_T_12; // @[ShiftQueue.scala:54:23] wire [4:0] _io_mask_T; // @[ShiftQueue.scala:53:20] wire io_enq_ready_0; // @[ShiftQueue.scala:12:7] wire [7:0] io_deq_bits_btb_bht_history_0; // @[ShiftQueue.scala:12:7] wire io_deq_bits_btb_bht_value_0; // @[ShiftQueue.scala:12:7] wire [1:0] io_deq_bits_btb_cfiType_0; // @[ShiftQueue.scala:12:7] wire io_deq_bits_btb_taken_0; // @[ShiftQueue.scala:12:7] wire [1:0] io_deq_bits_btb_mask_0; // @[ShiftQueue.scala:12:7] wire io_deq_bits_btb_bridx_0; // @[ShiftQueue.scala:12:7] wire [38:0] io_deq_bits_btb_target_0; // @[ShiftQueue.scala:12:7] wire [4:0] io_deq_bits_btb_entry_0; // @[ShiftQueue.scala:12:7] wire io_deq_bits_xcpt_pf_inst_0; // @[ShiftQueue.scala:12:7] wire io_deq_bits_xcpt_gf_inst_0; // @[ShiftQueue.scala:12:7] wire io_deq_bits_xcpt_ae_inst_0; // @[ShiftQueue.scala:12:7] wire [39:0] io_deq_bits_pc_0; // @[ShiftQueue.scala:12:7] wire [31:0] io_deq_bits_data_0; // @[ShiftQueue.scala:12:7] wire [1:0] io_deq_bits_mask_0; // @[ShiftQueue.scala:12:7] wire io_deq_bits_replay_0; // @[ShiftQueue.scala:12:7] wire io_deq_valid_0; // @[ShiftQueue.scala:12:7] wire [2:0] io_count; // @[ShiftQueue.scala:12:7] wire [4:0] io_mask_0; // @[ShiftQueue.scala:12:7] reg valid_0; // @[ShiftQueue.scala:21:30] wire _wen_T_1 = valid_0; // @[ShiftQueue.scala:21:30, :30:67] wire _valid_0_T_1 = valid_0; // @[ShiftQueue.scala:21:30, :36:67] reg valid_1; // @[ShiftQueue.scala:21:30] wire _wen_T_9 = valid_1; // @[ShiftQueue.scala:21:30, :30:67] wire _valid_1_T_1 = valid_1; // @[ShiftQueue.scala:21:30, :36:67] reg valid_2; // @[ShiftQueue.scala:21:30] wire _wen_T_17 = valid_2; // @[ShiftQueue.scala:21:30, :30:67] wire _valid_2_T_1 = valid_2; // @[ShiftQueue.scala:21:30, :36:67] reg valid_3; // @[ShiftQueue.scala:21:30] wire _wen_T_25 = valid_3; // @[ShiftQueue.scala:21:30, :30:67] wire _valid_3_T_1 = valid_3; // @[ShiftQueue.scala:21:30, :36:67] reg valid_4; // @[ShiftQueue.scala:21:30] wire _wen_T_33 = valid_4; // @[ShiftQueue.scala:21:30, :30:67] wire _valid_4_T_1 = valid_4; // @[ShiftQueue.scala:21:30, :36:67] reg [1:0] elts_0_btb_cfiType; // @[ShiftQueue.scala:22:25] reg elts_0_btb_taken; // @[ShiftQueue.scala:22:25] reg [1:0] elts_0_btb_mask; // @[ShiftQueue.scala:22:25] reg elts_0_btb_bridx; // @[ShiftQueue.scala:22:25] reg [38:0] elts_0_btb_target; // @[ShiftQueue.scala:22:25] reg [4:0] elts_0_btb_entry; // @[ShiftQueue.scala:22:25] reg [7:0] elts_0_btb_bht_history; // @[ShiftQueue.scala:22:25] reg elts_0_btb_bht_value; // @[ShiftQueue.scala:22:25] reg [39:0] elts_0_pc; // @[ShiftQueue.scala:22:25] reg [31:0] elts_0_data; // @[ShiftQueue.scala:22:25] reg [1:0] elts_0_mask; // @[ShiftQueue.scala:22:25] reg elts_0_xcpt_pf_inst; // @[ShiftQueue.scala:22:25] reg elts_0_xcpt_gf_inst; // @[ShiftQueue.scala:22:25] reg elts_0_xcpt_ae_inst; // @[ShiftQueue.scala:22:25] reg elts_0_replay; // @[ShiftQueue.scala:22:25] reg [1:0] elts_1_btb_cfiType; // @[ShiftQueue.scala:22:25] reg elts_1_btb_taken; // @[ShiftQueue.scala:22:25] reg [1:0] elts_1_btb_mask; // @[ShiftQueue.scala:22:25] reg elts_1_btb_bridx; // @[ShiftQueue.scala:22:25] reg [38:0] elts_1_btb_target; // @[ShiftQueue.scala:22:25] reg [4:0] elts_1_btb_entry; // @[ShiftQueue.scala:22:25] reg [7:0] elts_1_btb_bht_history; // @[ShiftQueue.scala:22:25] reg elts_1_btb_bht_value; // @[ShiftQueue.scala:22:25] reg [39:0] elts_1_pc; // @[ShiftQueue.scala:22:25] reg [31:0] elts_1_data; // @[ShiftQueue.scala:22:25] reg [1:0] elts_1_mask; // @[ShiftQueue.scala:22:25] reg elts_1_xcpt_pf_inst; // @[ShiftQueue.scala:22:25] reg elts_1_xcpt_gf_inst; // @[ShiftQueue.scala:22:25] reg elts_1_xcpt_ae_inst; // @[ShiftQueue.scala:22:25] reg elts_1_replay; // @[ShiftQueue.scala:22:25] reg [1:0] elts_2_btb_cfiType; // @[ShiftQueue.scala:22:25] reg elts_2_btb_taken; // @[ShiftQueue.scala:22:25] reg [1:0] elts_2_btb_mask; // @[ShiftQueue.scala:22:25] reg elts_2_btb_bridx; // @[ShiftQueue.scala:22:25] reg [38:0] elts_2_btb_target; // @[ShiftQueue.scala:22:25] reg [4:0] elts_2_btb_entry; // @[ShiftQueue.scala:22:25] reg [7:0] elts_2_btb_bht_history; // @[ShiftQueue.scala:22:25] reg elts_2_btb_bht_value; // @[ShiftQueue.scala:22:25] reg [39:0] elts_2_pc; // @[ShiftQueue.scala:22:25] reg [31:0] elts_2_data; // @[ShiftQueue.scala:22:25] reg [1:0] elts_2_mask; // @[ShiftQueue.scala:22:25] reg elts_2_xcpt_pf_inst; // @[ShiftQueue.scala:22:25] reg elts_2_xcpt_gf_inst; // @[ShiftQueue.scala:22:25] reg elts_2_xcpt_ae_inst; // @[ShiftQueue.scala:22:25] reg elts_2_replay; // @[ShiftQueue.scala:22:25] reg [1:0] elts_3_btb_cfiType; // @[ShiftQueue.scala:22:25] reg elts_3_btb_taken; // @[ShiftQueue.scala:22:25] reg [1:0] elts_3_btb_mask; // @[ShiftQueue.scala:22:25] reg elts_3_btb_bridx; // @[ShiftQueue.scala:22:25] reg [38:0] elts_3_btb_target; // @[ShiftQueue.scala:22:25] reg [4:0] elts_3_btb_entry; // @[ShiftQueue.scala:22:25] reg [7:0] elts_3_btb_bht_history; // @[ShiftQueue.scala:22:25] reg elts_3_btb_bht_value; // @[ShiftQueue.scala:22:25] reg [39:0] elts_3_pc; // @[ShiftQueue.scala:22:25] reg [31:0] elts_3_data; // @[ShiftQueue.scala:22:25] reg [1:0] elts_3_mask; // @[ShiftQueue.scala:22:25] reg elts_3_xcpt_pf_inst; // @[ShiftQueue.scala:22:25] reg elts_3_xcpt_gf_inst; // @[ShiftQueue.scala:22:25] reg elts_3_xcpt_ae_inst; // @[ShiftQueue.scala:22:25] reg elts_3_replay; // @[ShiftQueue.scala:22:25] reg [1:0] elts_4_btb_cfiType; // @[ShiftQueue.scala:22:25] reg elts_4_btb_taken; // @[ShiftQueue.scala:22:25] reg [1:0] elts_4_btb_mask; // @[ShiftQueue.scala:22:25] reg elts_4_btb_bridx; // @[ShiftQueue.scala:22:25] reg [38:0] elts_4_btb_target; // @[ShiftQueue.scala:22:25] reg [4:0] elts_4_btb_entry; // @[ShiftQueue.scala:22:25] reg [7:0] elts_4_btb_bht_history; // @[ShiftQueue.scala:22:25] reg elts_4_btb_bht_value; // @[ShiftQueue.scala:22:25] reg [39:0] elts_4_pc; // @[ShiftQueue.scala:22:25] reg [31:0] elts_4_data; // @[ShiftQueue.scala:22:25] reg [1:0] elts_4_mask; // @[ShiftQueue.scala:22:25] reg elts_4_xcpt_pf_inst; // @[ShiftQueue.scala:22:25] reg elts_4_xcpt_gf_inst; // @[ShiftQueue.scala:22:25] reg elts_4_xcpt_ae_inst; // @[ShiftQueue.scala:22:25] reg elts_4_replay; // @[ShiftQueue.scala:22:25] wire [1:0] wdata_btb_cfiType = valid_1 ? elts_1_btb_cfiType : io_enq_bits_btb_cfiType_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_btb_taken = valid_1 ? elts_1_btb_taken : io_enq_bits_btb_taken_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [1:0] wdata_btb_mask = valid_1 ? elts_1_btb_mask : io_enq_bits_btb_mask_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_btb_bridx = valid_1 ? elts_1_btb_bridx : io_enq_bits_btb_bridx_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [38:0] wdata_btb_target = valid_1 ? elts_1_btb_target : io_enq_bits_btb_target_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [4:0] wdata_btb_entry = valid_1 ? elts_1_btb_entry : io_enq_bits_btb_entry_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [7:0] wdata_btb_bht_history = valid_1 ? elts_1_btb_bht_history : io_enq_bits_btb_bht_history_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_btb_bht_value = valid_1 ? elts_1_btb_bht_value : io_enq_bits_btb_bht_value_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [39:0] wdata_pc = valid_1 ? elts_1_pc : io_enq_bits_pc_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [31:0] wdata_data = valid_1 ? elts_1_data : io_enq_bits_data_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [1:0] wdata_mask = valid_1 ? elts_1_mask : io_enq_bits_mask_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_xcpt_pf_inst = valid_1 ? elts_1_xcpt_pf_inst : io_enq_bits_xcpt_pf_inst_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_xcpt_gf_inst = valid_1 & elts_1_xcpt_gf_inst; // @[ShiftQueue.scala:21:30, :22:25, :27:57] wire wdata_xcpt_ae_inst = valid_1 ? elts_1_xcpt_ae_inst : io_enq_bits_xcpt_ae_inst_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_replay = valid_1 ? elts_1_replay : io_enq_bits_replay_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire _GEN = io_enq_ready_0 & io_enq_valid_0; // @[Decoupled.scala:51:35] wire _wen_T; // @[Decoupled.scala:51:35] assign _wen_T = _GEN; // @[Decoupled.scala:51:35] wire _wen_T_4; // @[Decoupled.scala:51:35] assign _wen_T_4 = _GEN; // @[Decoupled.scala:51:35] wire _valid_0_T; // @[Decoupled.scala:51:35] assign _valid_0_T = _GEN; // @[Decoupled.scala:51:35] wire _valid_0_T_4; // @[Decoupled.scala:51:35] assign _valid_0_T_4 = _GEN; // @[Decoupled.scala:51:35] wire _wen_T_8; // @[Decoupled.scala:51:35] assign _wen_T_8 = _GEN; // @[Decoupled.scala:51:35] wire _wen_T_12; // @[Decoupled.scala:51:35] assign _wen_T_12 = _GEN; // @[Decoupled.scala:51:35] wire _valid_1_T; // @[Decoupled.scala:51:35] assign _valid_1_T = _GEN; // @[Decoupled.scala:51:35] wire _valid_1_T_4; // @[Decoupled.scala:51:35] assign _valid_1_T_4 = _GEN; // @[Decoupled.scala:51:35] wire _wen_T_16; // @[Decoupled.scala:51:35] assign _wen_T_16 = _GEN; // @[Decoupled.scala:51:35] wire _wen_T_20; // @[Decoupled.scala:51:35] assign _wen_T_20 = _GEN; // @[Decoupled.scala:51:35] wire _valid_2_T; // @[Decoupled.scala:51:35] assign _valid_2_T = _GEN; // @[Decoupled.scala:51:35] wire _valid_2_T_4; // @[Decoupled.scala:51:35] assign _valid_2_T_4 = _GEN; // @[Decoupled.scala:51:35] wire _wen_T_24; // @[Decoupled.scala:51:35] assign _wen_T_24 = _GEN; // @[Decoupled.scala:51:35] wire _wen_T_28; // @[Decoupled.scala:51:35] assign _wen_T_28 = _GEN; // @[Decoupled.scala:51:35] wire _valid_3_T; // @[Decoupled.scala:51:35] assign _valid_3_T = _GEN; // @[Decoupled.scala:51:35] wire _valid_3_T_4; // @[Decoupled.scala:51:35] assign _valid_3_T_4 = _GEN; // @[Decoupled.scala:51:35] wire _wen_T_32; // @[Decoupled.scala:51:35] assign _wen_T_32 = _GEN; // @[Decoupled.scala:51:35] wire _wen_T_36; // @[Decoupled.scala:51:35] assign _wen_T_36 = _GEN; // @[Decoupled.scala:51:35] wire _valid_4_T; // @[Decoupled.scala:51:35] assign _valid_4_T = _GEN; // @[Decoupled.scala:51:35] wire _valid_4_T_4; // @[Decoupled.scala:51:35] assign _valid_4_T_4 = _GEN; // @[Decoupled.scala:51:35] wire _wen_T_2 = _wen_T & _wen_T_1; // @[Decoupled.scala:51:35] wire _wen_T_3 = valid_1 \| _wen_T_2; // @[ShiftQueue.scala:21:30, :30:{28,43}] wire _wen_T_5 = _wen_T_4; // @[Decoupled.scala:51:35] wire _wen_T_6 = ~valid_0; // @[ShiftQueue.scala:21:30, :31:46] wire _wen_T_7 = _wen_T_5 & _wen_T_6; // @[ShiftQueue.scala:31:{23,43,46}] wire wen = io_deq_ready_0 ? _wen_T_3 : _wen_T_7; // @[ShiftQueue.scala:12:7, :29:10, :30:28, :31:43] wire _valid_0_T_2 = _valid_0_T & _valid_0_T_1; // @[Decoupled.scala:51:35] wire _valid_0_T_3 = valid_1 \| _valid_0_T_2; // @[ShiftQueue.scala:21:30, :36:{28,43}] wire _valid_0_T_5 = _valid_0_T_4; // @[Decoupled.scala:51:35] wire _valid_0_T_6 = _valid_0_T_5 \| valid_0; // @[ShiftQueue.scala:21:30, :37:{23,43}] wire _valid_0_T_7 = io_deq_ready_0 ? _valid_0_T_3 : _valid_0_T_6; // @[ShiftQueue.scala:12:7, :35:10, :36:28, :37:43] wire [1:0] wdata_1_btb_cfiType = valid_2 ? elts_2_btb_cfiType : io_enq_bits_btb_cfiType_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_1_btb_taken = valid_2 ? elts_2_btb_taken : io_enq_bits_btb_taken_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [1:0] wdata_1_btb_mask = valid_2 ? elts_2_btb_mask : io_enq_bits_btb_mask_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_1_btb_bridx = valid_2 ? elts_2_btb_bridx : io_enq_bits_btb_bridx_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [38:0] wdata_1_btb_target = valid_2 ? elts_2_btb_target : io_enq_bits_btb_target_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [4:0] wdata_1_btb_entry = valid_2 ? elts_2_btb_entry : io_enq_bits_btb_entry_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [7:0] wdata_1_btb_bht_history = valid_2 ? elts_2_btb_bht_history : io_enq_bits_btb_bht_history_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_1_btb_bht_value = valid_2 ? elts_2_btb_bht_value : io_enq_bits_btb_bht_value_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [39:0] wdata_1_pc = valid_2 ? elts_2_pc : io_enq_bits_pc_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [31:0] wdata_1_data = valid_2 ? elts_2_data : io_enq_bits_data_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [1:0] wdata_1_mask = valid_2 ? elts_2_mask : io_enq_bits_mask_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_1_xcpt_pf_inst = valid_2 ? elts_2_xcpt_pf_inst : io_enq_bits_xcpt_pf_inst_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_1_xcpt_gf_inst = valid_2 & elts_2_xcpt_gf_inst; // @[ShiftQueue.scala:21:30, :22:25, :27:57] wire wdata_1_xcpt_ae_inst = valid_2 ? elts_2_xcpt_ae_inst : io_enq_bits_xcpt_ae_inst_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_1_replay = valid_2 ? elts_2_replay : io_enq_bits_replay_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire _wen_T_10 = _wen_T_8 & _wen_T_9; // @[Decoupled.scala:51:35] wire _wen_T_11 = valid_2 \| _wen_T_10; // @[ShiftQueue.scala:21:30, :30:{28,43}] wire _wen_T_13 = _wen_T_12 & valid_0; // @[Decoupled.scala:51:35] wire _wen_T_14 = ~valid_1; // @[ShiftQueue.scala:21:30, :31:46] wire _wen_T_15 = _wen_T_13 & _wen_T_14; // @[ShiftQueue.scala:31:{23,43,46}] wire wen_1 = io_deq_ready_0 ? _wen_T_11 : _wen_T_15; // @[ShiftQueue.scala:12:7, :29:10, :30:28, :31:43] wire _valid_1_T_2 = _valid_1_T & _valid_1_T_1; // @[Decoupled.scala:51:35] wire _valid_1_T_3 = valid_2 \| _valid_1_T_2; // @[ShiftQueue.scala:21:30, :36:{28,43}] wire _valid_1_T_5 = _valid_1_T_4 & valid_0; // @[Decoupled.scala:51:35] wire _valid_1_T_6 = _valid_1_T_5 \| valid_1; // @[ShiftQueue.scala:21:30, :37:{23,43}] wire _valid_1_T_7 = io_deq_ready_0 ? _valid_1_T_3 : _valid_1_T_6; // @[ShiftQueue.scala:12:7, :35:10, :36:28, :37:43] wire [1:0] wdata_2_btb_cfiType = valid_3 ? elts_3_btb_cfiType : io_enq_bits_btb_cfiType_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_2_btb_taken = valid_3 ? elts_3_btb_taken : io_enq_bits_btb_taken_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [1:0] wdata_2_btb_mask = valid_3 ? elts_3_btb_mask : io_enq_bits_btb_mask_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_2_btb_bridx = valid_3 ? elts_3_btb_bridx : io_enq_bits_btb_bridx_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [38:0] wdata_2_btb_target = valid_3 ? elts_3_btb_target : io_enq_bits_btb_target_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [4:0] wdata_2_btb_entry = valid_3 ? elts_3_btb_entry : io_enq_bits_btb_entry_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [7:0] wdata_2_btb_bht_history = valid_3 ? elts_3_btb_bht_history : io_enq_bits_btb_bht_history_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_2_btb_bht_value = valid_3 ? elts_3_btb_bht_value : io_enq_bits_btb_bht_value_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [39:0] wdata_2_pc = valid_3 ? elts_3_pc : io_enq_bits_pc_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [31:0] wdata_2_data = valid_3 ? elts_3_data : io_enq_bits_data_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [1:0] wdata_2_mask = valid_3 ? elts_3_mask : io_enq_bits_mask_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_2_xcpt_pf_inst = valid_3 ? elts_3_xcpt_pf_inst : io_enq_bits_xcpt_pf_inst_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_2_xcpt_gf_inst = valid_3 & elts_3_xcpt_gf_inst; // @[ShiftQueue.scala:21:30, :22:25, :27:57] wire wdata_2_xcpt_ae_inst = valid_3 ? elts_3_xcpt_ae_inst : io_enq_bits_xcpt_ae_inst_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_2_replay = valid_3 ? elts_3_replay : io_enq_bits_replay_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire _wen_T_18 = _wen_T_16 & _wen_T_17; // @[Decoupled.scala:51:35] wire _wen_T_19 = valid_3 \| _wen_T_18; // @[ShiftQueue.scala:21:30, :30:{28,43}] wire _wen_T_21 = _wen_T_20 & valid_1; // @[Decoupled.scala:51:35] wire _wen_T_22 = ~valid_2; // @[ShiftQueue.scala:21:30, :31:46] wire _wen_T_23 = _wen_T_21 & _wen_T_22; // @[ShiftQueue.scala:31:{23,43,46}] wire wen_2 = io_deq_ready_0 ? _wen_T_19 : _wen_T_23; // @[ShiftQueue.scala:12:7, :29:10, :30:28, :31:43] wire _valid_2_T_2 = _valid_2_T & _valid_2_T_1; // @[Decoupled.scala:51:35] wire _valid_2_T_3 = valid_3 \| _valid_2_T_2; // @[ShiftQueue.scala:21:30, :36:{28,43}] wire _valid_2_T_5 = _valid_2_T_4 & valid_1; // @[Decoupled.scala:51:35] wire _valid_2_T_6 = _valid_2_T_5 \| valid_2; // @[ShiftQueue.scala:21:30, :37:{23,43}] wire _valid_2_T_7 = io_deq_ready_0 ? _valid_2_T_3 : _valid_2_T_6; // @[ShiftQueue.scala:12:7, :35:10, :36:28, :37:43] wire [1:0] wdata_3_btb_cfiType = valid_4 ? elts_4_btb_cfiType : io_enq_bits_btb_cfiType_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_3_btb_taken = valid_4 ? elts_4_btb_taken : io_enq_bits_btb_taken_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [1:0] wdata_3_btb_mask = valid_4 ? elts_4_btb_mask : io_enq_bits_btb_mask_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_3_btb_bridx = valid_4 ? elts_4_btb_bridx : io_enq_bits_btb_bridx_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [38:0] wdata_3_btb_target = valid_4 ? elts_4_btb_target : io_enq_bits_btb_target_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [4:0] wdata_3_btb_entry = valid_4 ? elts_4_btb_entry : io_enq_bits_btb_entry_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [7:0] wdata_3_btb_bht_history = valid_4 ? elts_4_btb_bht_history : io_enq_bits_btb_bht_history_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_3_btb_bht_value = valid_4 ? elts_4_btb_bht_value : io_enq_bits_btb_bht_value_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [39:0] wdata_3_pc = valid_4 ? elts_4_pc : io_enq_bits_pc_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [31:0] wdata_3_data = valid_4 ? elts_4_data : io_enq_bits_data_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [1:0] wdata_3_mask = valid_4 ? elts_4_mask : io_enq_bits_mask_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_3_xcpt_pf_inst = valid_4 ? elts_4_xcpt_pf_inst : io_enq_bits_xcpt_pf_inst_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_3_xcpt_gf_inst = valid_4 & elts_4_xcpt_gf_inst; // @[ShiftQueue.scala:21:30, :22:25, :27:57] wire wdata_3_xcpt_ae_inst = valid_4 ? elts_4_xcpt_ae_inst : io_enq_bits_xcpt_ae_inst_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_3_replay = valid_4 ? elts_4_replay : io_enq_bits_replay_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire _wen_T_26 = _wen_T_24 & _wen_T_25; // @[Decoupled.scala:51:35] wire _wen_T_27 = valid_4 \| _wen_T_26; // @[ShiftQueue.scala:21:30, :30:{28,43}] wire _wen_T_29 = _wen_T_28 & valid_2; // @[Decoupled.scala:51:35] wire _wen_T_30 = ~valid_3; // @[ShiftQueue.scala:21:30, :31:46] wire _wen_T_31 = _wen_T_29 & _wen_T_30; // @[ShiftQueue.scala:31:{23,43,46}] wire wen_3 = io_deq_ready_0 ? _wen_T_27 : _wen_T_31; // @[ShiftQueue.scala:12:7, :29:10, :30:28, :31:43] wire _valid_3_T_2 = _valid_3_T & _valid_3_T_1; // @[Decoupled.scala:51:35] wire _valid_3_T_3 = valid_4 \| _valid_3_T_2; // @[ShiftQueue.scala:21:30, :36:{28,43}] wire _valid_3_T_5 = _valid_3_T_4 & valid_2; // @[Decoupled.scala:51:35] wire _valid_3_T_6 = _valid_3_T_5 \| valid_3; // @[ShiftQueue.scala:21:30, :37:{23,43}] wire _valid_3_T_7 = io_deq_ready_0 ? _valid_3_T_3 : _valid_3_T_6; // @[ShiftQueue.scala:12:7, :35:10, :36:28, :37:43] wire _wen_T_34 = _wen_T_32 & _wen_T_33; // @[Decoupled.scala:51:35] wire _wen_T_35 = _wen_T_34; // @[ShiftQueue.scala:30:{28,43}] wire _wen_T_37 = _wen_T_36 & valid_3; // @[Decoupled.scala:51:35] wire _wen_T_38 = ~valid_4; // @[ShiftQueue.scala:21:30, :31:46] wire _wen_T_39 = _wen_T_37 & _wen_T_38; // @[ShiftQueue.scala:31:{23,43,46}] wire wen_4 = io_deq_ready_0 ? _wen_T_35 : _wen_T_39; // @[ShiftQueue.scala:12:7, :29:10, :30:28, :31:43] wire _valid_4_T_2 = _valid_4_T & _valid_4_T_1; // @[Decoupled.scala:51:35] wire _valid_4_T_3 = _valid_4_T_2; // @[ShiftQueue.scala:36:{28,43}] wire _valid_4_T_5 = _valid_4_T_4 & valid_3; // @[Decoupled.scala:51:35] wire _valid_4_T_6 = _valid_4_T_5 \| valid_4; // @[ShiftQueue.scala:21:30, :37:{23,43}] wire _valid_4_T_7 = io_deq_ready_0 ? _valid_4_T_3 : _valid_4_T_6; // @[ShiftQueue.scala:12:7, :35:10, :36:28, :37:43] assign _io_enq_ready_T = ~valid_4; // @[ShiftQueue.scala:21:30, :31:46, :40:19] assign io_enq_ready_0 = _io_enq_ready_T; // @[ShiftQueue.scala:12:7, :40:19] assign io_deq_valid_0 = io_enq_valid_0 \| valid_0; // @[ShiftQueue.scala:12:7, :21:30, :41:16, :45:{25,40}] assign io_deq_bits_btb_cfiType_0 = valid_0 ? elts_0_btb_cfiType : io_enq_bits_btb_cfiType_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_btb_taken_0 = valid_0 ? elts_0_btb_taken : io_enq_bits_btb_taken_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_btb_mask_0 = valid_0 ? elts_0_btb_mask : io_enq_bits_btb_mask_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_btb_bridx_0 = valid_0 ? elts_0_btb_bridx : io_enq_bits_btb_bridx_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_btb_target_0 = valid_0 ? elts_0_btb_target : io_enq_bits_btb_target_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_btb_entry_0 = valid_0 ? elts_0_btb_entry : io_enq_bits_btb_entry_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_btb_bht_history_0 = valid_0 ? elts_0_btb_bht_history : io_enq_bits_btb_bht_history_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_btb_bht_value_0 = valid_0 ? elts_0_btb_bht_value : io_enq_bits_btb_bht_value_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_pc_0 = valid_0 ? elts_0_pc : io_enq_bits_pc_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_data_0 = valid_0 ? elts_0_data : io_enq_bits_data_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_mask_0 = valid_0 ? elts_0_mask : io_enq_bits_mask_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_xcpt_pf_inst_0 = valid_0 ? elts_0_xcpt_pf_inst : io_enq_bits_xcpt_pf_inst_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_xcpt_gf_inst_0 = valid_0 & elts_0_xcpt_gf_inst; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_xcpt_ae_inst_0 = valid_0 ? elts_0_xcpt_ae_inst : io_enq_bits_xcpt_ae_inst_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_replay_0 = valid_0 ? elts_0_replay : io_enq_bits_replay_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] wire [1:0] io_mask_lo = {valid_1, valid_0}; // @[ShiftQueue.scala:21:30, :53:20] wire [1:0] io_mask_hi_hi = {valid_4, valid_3}; // @[ShiftQueue.scala:21:30, :53:20] wire [2:0] io_mask_hi = {io_mask_hi_hi, valid_2}; // @[ShiftQueue.scala:21:30, :53:20] assign _io_mask_T = {io_mask_hi, io_mask_lo}; // @[ShiftQueue.scala:53:20] assign io_mask_0 = _io_mask_T; // @[ShiftQueue.scala:12:7, :53:20] wire _io_count_T = io_mask_0[0]; // @[ShiftQueue.scala:12:7, :54:23] wire _io_count_T_1 = io_mask_0[1]; // @[ShiftQueue.scala:12:7, :54:23] wire _io_count_T_2 = io_mask_0[2]; // @[ShiftQueue.scala:12:7, :54:23] wire _io_count_T_3 = io_mask_0[3]; // @[ShiftQueue.scala:12:7, :54:23] wire _io_count_T_4 = io_mask_0[4]; // @[ShiftQueue.scala:12:7, :54:23] wire [1:0] _io_count_T_5 = {1'h0, _io_count_T} + {1'h0, _io_count_T_1}; // @[ShiftQueue.scala:54:23] wire [1:0] _io_count_T_6 = _io_count_T_5; // @[ShiftQueue.scala:54:23] wire [1:0] _io_count_T_7 = {1'h0, _io_count_T_3} + {1'h0, _io_count_T_4}; // @[ShiftQueue.scala:54:23] wire [1:0] _io_count_T_8 = _io_count_T_7; // @[ShiftQueue.scala:54:23] wire [2:0] _io_count_T_9 = {2'h0, _io_count_T_2} + {1'h0, _io_count_T_8}; // @[ShiftQueue.scala:54:23] wire [1:0] _io_count_T_10 = _io_count_T_9[1:0]; // @[ShiftQueue.scala:54:23] wire [2:0] _io_count_T_11 = {1'h0, _io_count_T_6} + {1'h0, _io_count_T_10}; // @[ShiftQueue.scala:54:23] assign _io_count_T_12 = _io_count_T_11; // @[ShiftQueue.scala:54:23] assign io_count = _io_count_T_12; // @[ShiftQueue.scala:12:7, :54:23] always @(posedge clock) begin // @[ShiftQueue.scala:12:7] if (reset) begin // @[ShiftQueue.scala:12:7] valid_0 <= 1'h0; // @[ShiftQueue.scala:21:30] valid_1 <= 1'h0; // @[ShiftQueue.scala:21:30] valid_2 <= 1'h0; // @[ShiftQueue.scala:21:30] valid_3 <= 1'h0; // @[ShiftQueue.scala:21:30] valid_4 <= 1'h0; // @[ShiftQueue.scala:21:30] end else begin // @[ShiftQueue.scala:12:7] valid_0 <= _valid_0_T_7; // @[ShiftQueue.scala:21:30, :35:10] valid_1 <= _valid_1_T_7; // @[ShiftQueue.scala:21:30, :35:10] valid_2 <= _valid_2_T_7; // @[ShiftQueue.scala:21:30, :35:10] valid_3 <= _valid_3_T_7; // @[ShiftQueue.scala:21:30, :35:10] valid_4 <= _valid_4_T_7; // @[ShiftQueue.scala:21:30, :35:10] end if (wen) begin // @[ShiftQueue.scala:29:10] elts_0_btb_cfiType <= wdata_btb_cfiType; // @[ShiftQueue.scala:22:25, :27:57] elts_0_btb_taken <= wdata_btb_taken; // @[ShiftQueue.scala:22:25, :27:57] elts_0_btb_mask <= wdata_btb_mask; // @[ShiftQueue.scala:22:25, :27:57] elts_0_btb_bridx <= wdata_btb_bridx; // @[ShiftQueue.scala:22:25, :27:57] elts_0_btb_target <= wdata_btb_target; // @[ShiftQueue.scala:22:25, :27:57] elts_0_btb_entry <= wdata_btb_entry; // @[ShiftQueue.scala:22:25, :27:57] elts_0_btb_bht_history <= wdata_btb_bht_history; // @[ShiftQueue.scala:22:25, :27:57] elts_0_btb_bht_value <= wdata_btb_bht_value; // @[ShiftQueue.scala:22:25, :27:57] elts_0_pc <= wdata_pc; // @[ShiftQueue.scala:22:25, :27:57] elts_0_data <= wdata_data; // @[ShiftQueue.scala:22:25, :27:57] elts_0_mask <= wdata_mask; // @[ShiftQueue.scala:22:25, :27:57] elts_0_xcpt_pf_inst <= wdata_xcpt_pf_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_0_xcpt_gf_inst <= wdata_xcpt_gf_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_0_xcpt_ae_inst <= wdata_xcpt_ae_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_0_replay <= wdata_replay; // @[ShiftQueue.scala:22:25, :27:57] end if (wen_1) begin // @[ShiftQueue.scala:29:10] elts_1_btb_cfiType <= wdata_1_btb_cfiType; // @[ShiftQueue.scala:22:25, :27:57] elts_1_btb_taken <= wdata_1_btb_taken; // @[ShiftQueue.scala:22:25, :27:57] elts_1_btb_mask <= wdata_1_btb_mask; // @[ShiftQueue.scala:22:25, :27:57] elts_1_btb_bridx <= wdata_1_btb_bridx; // @[ShiftQueue.scala:22:25, :27:57] elts_1_btb_target <= wdata_1_btb_target; // @[ShiftQueue.scala:22:25, :27:57] elts_1_btb_entry <= wdata_1_btb_entry; // @[ShiftQueue.scala:22:25, :27:57] elts_1_btb_bht_history <= wdata_1_btb_bht_history; // @[ShiftQueue.scala:22:25, :27:57] elts_1_btb_bht_value <= wdata_1_btb_bht_value; // @[ShiftQueue.scala:22:25, :27:57] elts_1_pc <= wdata_1_pc; // @[ShiftQueue.scala:22:25, :27:57] elts_1_data <= wdata_1_data; // @[ShiftQueue.scala:22:25, :27:57] elts_1_mask <= wdata_1_mask; // @[ShiftQueue.scala:22:25, :27:57] elts_1_xcpt_pf_inst <= wdata_1_xcpt_pf_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_1_xcpt_gf_inst <= wdata_1_xcpt_gf_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_1_xcpt_ae_inst <= wdata_1_xcpt_ae_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_1_replay <= wdata_1_replay; // @[ShiftQueue.scala:22:25, :27:57] end if (wen_2) begin // @[ShiftQueue.scala:29:10] elts_2_btb_cfiType <= wdata_2_btb_cfiType; // @[ShiftQueue.scala:22:25, :27:57] elts_2_btb_taken <= wdata_2_btb_taken; // @[ShiftQueue.scala:22:25, :27:57] elts_2_btb_mask <= wdata_2_btb_mask; // @[ShiftQueue.scala:22:25, :27:57] elts_2_btb_bridx <= wdata_2_btb_bridx; // @[ShiftQueue.scala:22:25, :27:57] elts_2_btb_target <= wdata_2_btb_target; // @[ShiftQueue.scala:22:25, :27:57] elts_2_btb_entry <= wdata_2_btb_entry; // @[ShiftQueue.scala:22:25, :27:57] elts_2_btb_bht_history <= wdata_2_btb_bht_history; // @[ShiftQueue.scala:22:25, :27:57] elts_2_btb_bht_value <= wdata_2_btb_bht_value; // @[ShiftQueue.scala:22:25, :27:57] elts_2_pc <= wdata_2_pc; // @[ShiftQueue.scala:22:25, :27:57] elts_2_data <= wdata_2_data; // @[ShiftQueue.scala:22:25, :27:57] elts_2_mask <= wdata_2_mask; // @[ShiftQueue.scala:22:25, :27:57] elts_2_xcpt_pf_inst <= wdata_2_xcpt_pf_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_2_xcpt_gf_inst <= wdata_2_xcpt_gf_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_2_xcpt_ae_inst <= wdata_2_xcpt_ae_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_2_replay <= wdata_2_replay; // @[ShiftQueue.scala:22:25, :27:57] end if (wen_3) begin // @[ShiftQueue.scala:29:10] elts_3_btb_cfiType <= wdata_3_btb_cfiType; // @[ShiftQueue.scala:22:25, :27:57] elts_3_btb_taken <= wdata_3_btb_taken; // @[ShiftQueue.scala:22:25, :27:57] elts_3_btb_mask <= wdata_3_btb_mask; // @[ShiftQueue.scala:22:25, :27:57] elts_3_btb_bridx <= wdata_3_btb_bridx; // @[ShiftQueue.scala:22:25, :27:57] elts_3_btb_target <= wdata_3_btb_target; // @[ShiftQueue.scala:22:25, :27:57] elts_3_btb_entry <= wdata_3_btb_entry; // @[ShiftQueue.scala:22:25, :27:57] elts_3_btb_bht_history <= wdata_3_btb_bht_history; // @[ShiftQueue.scala:22:25, :27:57] elts_3_btb_bht_value <= wdata_3_btb_bht_value; // @[ShiftQueue.scala:22:25, :27:57] elts_3_pc <= wdata_3_pc; // @[ShiftQueue.scala:22:25, :27:57] elts_3_data <= wdata_3_data; // @[ShiftQueue.scala:22:25, :27:57] elts_3_mask <= wdata_3_mask; // @[ShiftQueue.scala:22:25, :27:57] elts_3_xcpt_pf_inst <= wdata_3_xcpt_pf_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_3_xcpt_gf_inst <= wdata_3_xcpt_gf_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_3_xcpt_ae_inst <= wdata_3_xcpt_ae_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_3_replay <= wdata_3_replay; // @[ShiftQueue.scala:22:25, :27:57] end if (wen_4) begin // @[ShiftQueue.scala:29:10] elts_4_btb_cfiType <= io_enq_bits_btb_cfiType_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_btb_taken <= io_enq_bits_btb_taken_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_btb_mask <= io_enq_bits_btb_mask_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_btb_bridx <= io_enq_bits_btb_bridx_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_btb_target <= io_enq_bits_btb_target_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_btb_entry <= io_enq_bits_btb_entry_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_btb_bht_history <= io_enq_bits_btb_bht_history_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_btb_bht_value <= io_enq_bits_btb_bht_value_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_pc <= io_enq_bits_pc_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_data <= io_enq_bits_data_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_mask <= io_enq_bits_mask_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_xcpt_pf_inst <= io_enq_bits_xcpt_pf_inst_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_xcpt_ae_inst <= io_enq_bits_xcpt_ae_inst_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_replay <= io_enq_bits_replay_0; // @[ShiftQueue.scala:12:7, :22:25] end elts_4_xcpt_gf_inst <= ~wen_4 & elts_4_xcpt_gf_inst; // @[ShiftQueue.scala:22:25, :29:10, :32:{16,26}] always @(posedge) assign io_enq_ready = io_enq_ready_0; // @[ShiftQueue.scala:12:7] assign io_deq_valid = io_deq_valid_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_btb_cfiType = io_deq_bits_btb_cfiType_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_btb_taken = io_deq_bits_btb_taken_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_btb_mask = io_deq_bits_btb_mask_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_btb_bridx = io_deq_bits_btb_bridx_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_btb_target = io_deq_bits_btb_target_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_btb_entry = io_deq_bits_btb_entry_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_btb_bht_history = io_deq_bits_btb_bht_history_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_btb_bht_value = io_deq_bits_btb_bht_value_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_pc = io_deq_bits_pc_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_data = io_deq_bits_data_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_mask = io_deq_bits_mask_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_xcpt_pf_inst = io_deq_bits_xcpt_pf_inst_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_xcpt_gf_inst = io_deq_bits_xcpt_gf_inst_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_xcpt_ae_inst = io_deq_bits_xcpt_ae_inst_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_replay = io_deq_bits_replay_0; // @[ShiftQueue.scala:12:7] assign io_mask = io_mask_0; // @[ShiftQueue.scala:12:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLROM : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_95 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready connect nodeIn, auto.in wire rom : UInt<64>[512] connect rom[0], UInt<64>(0h405051300000517) connect rom[1], UInt<64>(0h301022f330551073) connect rom[2], UInt<64>(0h12f2934122d293) connect rom[3], UInt<64>(0h3030107300028863) connect rom[4], UInt<64>(0h3445307322200513) connect rom[5], UInt<64>(0h3045107300800513) connect rom[6], UInt<64>(0h1050007330052073) connect rom[7], UInt<64>(0hffdff06f) connect rom[8], UInt<64>(0hf1402573020005b7) connect rom[9], UInt<64>(0h380006f00050463) connect rom[10], UInt<64>(0h10069300458613) connect rom[11], UInt<64>(0h46061300d62023) connect rom[12], UInt<64>(0hfe069ae3ffc62683) connect rom[13], UInt<64>(0h2c0006f) connect rom[14], UInt<64>(0h0) connect rom[15], UInt<64>(0h0) connect rom[16], UInt<64>(0h5a283f81ff06f) connect rom[17], UInt<64>(0h251513fe029ee3) connect rom[18], UInt<64>(0h5a02300b505b3) connect rom[19], UInt<64>(0h5350300001537) connect rom[20], UInt<64>(0hf140257334151073) connect rom[21], UInt<64>(0h185859300000597) connect rom[22], UInt<64>(0h3006307308000613) connect rom[23], UInt<64>(0h1330200073) connect rom[24], UInt<64>(0h100e0000edfe0dd0) connect rom[25], UInt<64>(0hb00b000038000000) connect rom[26], UInt<64>(0h1100000028000000) connect rom[27], UInt<64>(0h10000000) connect rom[28], UInt<64>(0h780b000060020000) connect rom[29], UInt<64>(0h0) connect rom[30], UInt<64>(0h0) connect rom[31], UInt<64>(0h1000000) connect rom[32], UInt<64>(0h400000003000000) connect rom[33], UInt<64>(0h100000000000000) connect rom[34], UInt<64>(0h400000003000000) connect rom[35], UInt<64>(0h10000000f000000) connect rom[36], UInt<64>(0h1500000003000000) connect rom[37], UInt<64>(0h2d6263751b000000) connect rom[38], UInt<64>(0h706968632c726162) connect rom[39], UInt<64>(0h7665642d64726179) connect rom[40], UInt<64>(0h300000000000000) connect rom[41], UInt<64>(0h2600000011000000) connect rom[42], UInt<64>(0h2c7261622d626375) connect rom[43], UInt<64>(0h6472617970696863) connect rom[44], UInt<64>(0h100000000000000) connect rom[45], UInt<64>(0h73657361696c61) connect rom[46], UInt<64>(0h1500000003000000) connect rom[47], UInt<64>(0h636f732f2c000000) connect rom[48], UInt<64>(0h406c61697265732f) connect rom[49], UInt<64>(0h3030303032303031) connect rom[50], UInt<64>(0h200000000000000) connect rom[51], UInt<64>(0h736f686301000000) connect rom[52], UInt<64>(0h300000000006e65) connect rom[53], UInt<64>(0h3400000015000000) connect rom[54], UInt<64>(0h7265732f636f732f) connect rom[55], UInt<64>(0h32303031406c6169) connect rom[56], UInt<64>(0h30303030) connect rom[57], UInt<64>(0h100000002000000) connect rom[58], UInt<64>(0h73757063) connect rom[59], UInt<64>(0h400000003000000) connect rom[60], UInt<64>(0h100000000000000) connect rom[61], UInt<64>(0h400000003000000) connect rom[62], UInt<64>(0hf000000) connect rom[63], UInt<64>(0h400000003000000) connect rom[64], UInt<64>(0h20a1070040000000) connect rom[65], UInt<64>(0h4075706301000000) connect rom[66], UInt<64>(0h300000000000030) connect rom[67], UInt<64>(0h5300000004000000) connect rom[68], UInt<64>(0h300000000000000) connect rom[69], UInt<64>(0h1b00000015000000) connect rom[70], UInt<64>(0h722c657669666973) connect rom[71], UInt<64>(0h72003074656b636f) connect rom[72], UInt<64>(0h76637369) connect rom[73], UInt<64>(0h400000003000000) connect rom[74], UInt<64>(0h4000000063000000) connect rom[75], UInt<64>(0h400000003000000) connect rom[76], UInt<64>(0h4000000076000000) connect rom[77], UInt<64>(0h400000003000000) connect rom[78], UInt<64>(0h80000083000000) connect rom[79], UInt<64>(0h400000003000000) connect rom[80], UInt<64>(0h100000090000000) connect rom[81], UInt<64>(0h400000003000000) connect rom[82], UInt<64>(0h200000009b000000) connect rom[83], UInt<64>(0h400000003000000) connect rom[84], UInt<64>(0h757063a6000000) connect rom[85], UInt<64>(0h400000003000000) connect rom[86], UInt<64>(0h1000000b2000000) connect rom[87], UInt<64>(0h400000003000000) connect rom[88], UInt<64>(0h40000000d1000000) connect rom[89], UInt<64>(0h400000003000000) connect rom[90], UInt<64>(0h40000000e4000000) connect rom[91], UInt<64>(0h400000003000000) connect rom[92], UInt<64>(0h800000f1000000) connect rom[93], UInt<64>(0h400000003000000) connect rom[94], UInt<64>(0h1000000fe000000) connect rom[95], UInt<64>(0h400000003000000) connect rom[96], UInt<64>(0h2000000009010000) connect rom[97], UInt<64>(0hb00000003000000) connect rom[98], UInt<64>(0h6373697214010000) connect rom[99], UInt<64>(0h393376732c76) connect rom[100], UInt<64>(0h400000003000000) connect rom[101], UInt<64>(0h10000001d010000) connect rom[102], UInt<64>(0h400000003000000) connect rom[103], UInt<64>(0h2e010000) connect rom[104], UInt<64>(0h3800000003000000) connect rom[105], UInt<64>(0h3436767232010000) connect rom[106], UInt<64>(0h7a62636466616d69) connect rom[107], UInt<64>(0h66697a5f72736369) connect rom[108], UInt<64>(0h697a5f6965636e65) connect rom[109], UInt<64>(0h5f68667a5f6d7068) connect rom[110], UInt<64>(0h5f62627a5f61627a) connect rom[111], UInt<64>(0h636f72785f73627a) connect rom[112], UInt<64>(0h30000000074656b) connect rom[113], UInt<64>(0h3c01000004000000) connect rom[114], UInt<64>(0h300000004000000) connect rom[115], UInt<64>(0h5101000004000000) connect rom[116], UInt<64>(0h300000008000000) connect rom[117], UInt<64>(0h6201000005000000) connect rom[118], UInt<64>(0h79616b6f) connect rom[119], UInt<64>(0h400000003000000) connect rom[120], UInt<64>(0h20a1070040000000) connect rom[121], UInt<64>(0h3000000) connect rom[122], UInt<64>(0h100000069010000) connect rom[123], UInt<64>(0h7075727265746e69) connect rom[124], UInt<64>(0h6f72746e6f632d74) connect rom[125], UInt<64>(0h72656c6c) connect rom[126], UInt<64>(0h400000003000000) connect rom[127], UInt<64>(0h100000073010000) connect rom[128], UInt<64>(0hf00000003000000) connect rom[129], UInt<64>(0h637369721b000000) connect rom[130], UInt<64>(0h6e692d7570632c76) connect rom[131], UInt<64>(0h300000000006374) connect rom[132], UInt<64>(0h8401000000000000) connect rom[133], UInt<64>(0h400000003000000) connect rom[134], UInt<64>(0h400000099010000) connect rom[135], UInt<64>(0h200000002000000) connect rom[136], UInt<64>(0h100000002000000) connect rom[137], UInt<64>(0h66697468) connect rom[138], UInt<64>(0ha00000003000000) connect rom[139], UInt<64>(0h2c6263751b000000) connect rom[140], UInt<64>(0h3066697468) connect rom[141], UInt<64>(0h100000002000000) connect rom[142], UInt<64>(0h384079726f6d656d) connect rom[143], UInt<64>(0h303030303030) connect rom[144], UInt<64>(0h700000003000000) connect rom[145], UInt<64>(0h6f6d656da6000000) connect rom[146], UInt<64>(0h300000000007972) connect rom[147], UInt<64>(0h2e01000008000000) connect rom[148], UInt<64>(0h10000000008) connect rom[149], UInt<64>(0h900000003000000) connect rom[150], UInt<64>(0h6173696462010000) connect rom[151], UInt<64>(0h64656c62) connect rom[152], UInt<64>(0h400000003000000) connect rom[153], UInt<64>(0h300000099010000) connect rom[154], UInt<64>(0h100000002000000) connect rom[155], UInt<64>(0h384079726f6d656d) connect rom[156], UInt<64>(0h30303030303030) connect rom[157], UInt<64>(0h700000003000000) connect rom[158], UInt<64>(0h6f6d656da6000000) connect rom[159], UInt<64>(0h300000000007972) connect rom[160], UInt<64>(0h2e01000008000000) connect rom[161], UInt<64>(0h1000000080) connect rom[162], UInt<64>(0h400000003000000) connect rom[163], UInt<64>(0h200000099010000) connect rom[164], UInt<64>(0h100000002000000) connect rom[165], UInt<64>(0h300000000636f73) connect rom[166], UInt<64>(0h4000000) connect rom[167], UInt<64>(0h300000001000000) connect rom[168], UInt<64>(0hf00000004000000) connect rom[169], UInt<64>(0h300000001000000) connect rom[170], UInt<64>(0h1b00000020000000) connect rom[171], UInt<64>(0h2c7261622d626375) connect rom[172], UInt<64>(0h6472617970696863) connect rom[173], UInt<64>(0h6d697300636f732d) connect rom[174], UInt<64>(0h7375622d656c70) connect rom[175], UInt<64>(0h3000000) connect rom[176], UInt<64>(0h1000000a1010000) connect rom[177], UInt<64>(0h6464612d746f6f62) connect rom[178], UInt<64>(0h6765722d73736572) connect rom[179], UInt<64>(0h3030303140) connect rom[180], UInt<64>(0h800000003000000) connect rom[181], UInt<64>(0h1000002e010000) connect rom[182], UInt<64>(0h300000000100000) connect rom[183], UInt<64>(0ha801000008000000) connect rom[184], UInt<64>(0h6c6f72746e6f63) connect rom[185], UInt<64>(0h100000002000000) connect rom[186], UInt<64>(0h6f632d6568636163) connect rom[187], UInt<64>(0h72656c6c6f72746e) connect rom[188], UInt<64>(0h3030303031303240) connect rom[189], UInt<64>(0h300000000000000) connect rom[190], UInt<64>(0h6500000004000000) connect rom[191], UInt<64>(0h300000040000000) connect rom[192], UInt<64>(0hb201000004000000) connect rom[193], UInt<64>(0h300000002000000) connect rom[194], UInt<64>(0h7800000004000000) connect rom[195], UInt<64>(0h300000000400000) connect rom[196], UInt<64>(0h8500000004000000) connect rom[197], UInt<64>(0h300000000000001) connect rom[198], UInt<64>(0hbe01000000000000) connect rom[199], UInt<64>(0h1d00000003000000) connect rom[200], UInt<64>(0h696669731b000000) connect rom[201], UInt<64>(0h756c636e692c6576) connect rom[202], UInt<64>(0h6863616365766973) connect rom[203], UInt<64>(0h6568636163003065) connect rom[204], UInt<64>(0h300000000000000) connect rom[205], UInt<64>(0h1d01000008000000) connect rom[206], UInt<64>(0h300000002000000) connect rom[207], UInt<64>(0h800000003000000) connect rom[208], UInt<64>(0h1022e010000) connect rom[209], UInt<64>(0h300000000100000) connect rom[210], UInt<64>(0ha801000008000000) connect rom[211], UInt<64>(0h6c6f72746e6f63) connect rom[212], UInt<64>(0h400000003000000) connect rom[213], UInt<64>(0hc000000cc010000) connect rom[214], UInt<64>(0h400000003000000) connect rom[215], UInt<64>(0h100000099010000) connect rom[216], UInt<64>(0h100000002000000) connect rom[217], UInt<64>(0h6f6c635f73756263) connect rom[218], UInt<64>(0h300000000006b63) connect rom[219], UInt<64>(0hde01000004000000) connect rom[220], UInt<64>(0h300000000000000) connect rom[221], UInt<64>(0h5300000004000000) connect rom[222], UInt<64>(0h30000000065cd1d) connect rom[223], UInt<64>(0heb0100000b000000) connect rom[224], UInt<64>(0h6f6c635f73756263) connect rom[225], UInt<64>(0h300000000006b63) connect rom[226], UInt<64>(0h1b0000000c000000) connect rom[227], UInt<64>(0h6c632d6465786966) connect rom[228], UInt<64>(0h2000000006b636f) connect rom[229], UInt<64>(0h6e696c6301000000) connect rom[230], UInt<64>(0h3030303030324074) connect rom[231], UInt<64>(0h300000000000030) connect rom[232], UInt<64>(0h1b0000000d000000) connect rom[233], UInt<64>(0h6c632c7663736972) connect rom[234], UInt<64>(0h30746e69) connect rom[235], UInt<64>(0h1000000003000000) connect rom[236], UInt<64>(0h4000000fe010000) connect rom[237], UInt<64>(0h400000003000000) connect rom[238], UInt<64>(0h300000007000000) connect rom[239], UInt<64>(0h2e01000008000000) connect rom[240], UInt<64>(0h10000000002) connect rom[241], UInt<64>(0h800000003000000) connect rom[242], UInt<64>(0h746e6f63a8010000) connect rom[243], UInt<64>(0h2000000006c6f72) connect rom[244], UInt<64>(0h636f6c6301000000) connect rom[245], UInt<64>(0h4072657461672d6b) connect rom[246], UInt<64>(0h303030303031) connect rom[247], UInt<64>(0h800000003000000) connect rom[248], UInt<64>(0h10002e010000) connect rom[249], UInt<64>(0h300000000100000) connect rom[250], UInt<64>(0ha801000008000000) connect rom[251], UInt<64>(0h6c6f72746e6f63) connect rom[252], UInt<64>(0h100000002000000) connect rom[253], UInt<64>(0h6f632d6775626564) connect rom[254], UInt<64>(0h72656c6c6f72746e) connect rom[255], UInt<64>(0h300000000003040) connect rom[256], UInt<64>(0h1b00000021000000) connect rom[257], UInt<64>(0h642c657669666973) connect rom[258], UInt<64>(0h3331302d67756265) connect rom[259], UInt<64>(0h642c766373697200) connect rom[260], UInt<64>(0h3331302d67756265) connect rom[261], UInt<64>(0h300000000000000) connect rom[262], UInt<64>(0h1202000005000000) connect rom[263], UInt<64>(0h6761746a) connect rom[264], UInt<64>(0h800000003000000) connect rom[265], UInt<64>(0h4000000fe010000) connect rom[266], UInt<64>(0h3000000ffff0000) connect rom[267], UInt<64>(0h2e01000008000000) connect rom[268], UInt<64>(0h10000000000000) connect rom[269], UInt<64>(0h800000003000000) connect rom[270], UInt<64>(0h746e6f63a8010000) connect rom[271], UInt<64>(0h2000000006c6f72) connect rom[272], UInt<64>(0h6f72726501000000) connect rom[273], UInt<64>(0h6563697665642d72) connect rom[274], UInt<64>(0h3030303340) connect rom[275], UInt<64>(0he00000003000000) connect rom[276], UInt<64>(0h696669731b000000) connect rom[277], UInt<64>(0h726f7272652c6576) connect rom[278], UInt<64>(0h300000000000030) connect rom[279], UInt<64>(0h2e01000008000000) connect rom[280], UInt<64>(0h10000000300000) connect rom[281], UInt<64>(0h100000002000000) connect rom[282], UInt<64>(0h6f6c635f73756266) connect rom[283], UInt<64>(0h300000000006b63) connect rom[284], UInt<64>(0hde01000004000000) connect rom[285], UInt<64>(0h300000000000000) connect rom[286], UInt<64>(0h5300000004000000) connect rom[287], UInt<64>(0h30000000065cd1d) connect rom[288], UInt<64>(0heb0100000b000000) connect rom[289], UInt<64>(0h6f6c635f73756266) connect rom[290], UInt<64>(0h300000000006b63) connect rom[291], UInt<64>(0h1b0000000c000000) connect rom[292], UInt<64>(0h6c632d6465786966) connect rom[293], UInt<64>(0h2000000006b636f) connect rom[294], UInt<64>(0h65746e6901000000) connect rom[295], UInt<64>(0h6f632d7470757272) connect rom[296], UInt<64>(0h72656c6c6f72746e) connect rom[297], UInt<64>(0h3030303030306340) connect rom[298], UInt<64>(0h300000000000000) connect rom[299], UInt<64>(0h7301000004000000) connect rom[300], UInt<64>(0h300000001000000) connect rom[301], UInt<64>(0h1b0000000c000000) connect rom[302], UInt<64>(0h6c702c7663736972) connect rom[303], UInt<64>(0h300000000306369) connect rom[304], UInt<64>(0h8401000000000000) connect rom[305], UInt<64>(0h1000000003000000) connect rom[306], UInt<64>(0h4000000fe010000) connect rom[307], UInt<64>(0h40000000b000000) connect rom[308], UInt<64>(0h300000009000000) connect rom[309], UInt<64>(0h2e01000008000000) connect rom[310], UInt<64>(0h40000000c) connect rom[311], UInt<64>(0h800000003000000) connect rom[312], UInt<64>(0h746e6f63a8010000) connect rom[313], UInt<64>(0h3000000006c6f72) connect rom[314], UInt<64>(0h1f02000004000000) connect rom[315], UInt<64>(0h300000001000000) connect rom[316], UInt<64>(0h3202000004000000) connect rom[317], UInt<64>(0h300000001000000) connect rom[318], UInt<64>(0h9901000004000000) connect rom[319], UInt<64>(0h200000006000000) connect rom[320], UInt<64>(0h7375626d01000000) connect rom[321], UInt<64>(0h6b636f6c635f) connect rom[322], UInt<64>(0h400000003000000) connect rom[323], UInt<64>(0hde010000) connect rom[324], UInt<64>(0h400000003000000) connect rom[325], UInt<64>(0h65cd1d53000000) connect rom[326], UInt<64>(0hb00000003000000) connect rom[327], UInt<64>(0h7375626deb010000) connect rom[328], UInt<64>(0h6b636f6c635f) connect rom[329], UInt<64>(0hc00000003000000) connect rom[330], UInt<64>(0h657869661b000000) connect rom[331], UInt<64>(0h6b636f6c632d64) connect rom[332], UInt<64>(0h100000002000000) connect rom[333], UInt<64>(0h6f6c635f73756270) connect rom[334], UInt<64>(0h300000000006b63) connect rom[335], UInt<64>(0hde01000004000000) connect rom[336], UInt<64>(0h300000000000000) connect rom[337], UInt<64>(0h5300000004000000) connect rom[338], UInt<64>(0h30000000065cd1d) connect rom[339], UInt<64>(0heb0100000b000000) connect rom[340], UInt<64>(0h6f6c635f73756270) connect rom[341], UInt<64>(0h300000000006b63) connect rom[342], UInt<64>(0h1b0000000c000000) connect rom[343], UInt<64>(0h6c632d6465786966) connect rom[344], UInt<64>(0h3000000006b636f) connect rom[345], UInt<64>(0h9901000004000000) connect rom[346], UInt<64>(0h200000005000000) connect rom[347], UInt<64>(0h406d6f7201000000) connect rom[348], UInt<64>(0h3030303031) connect rom[349], UInt<64>(0hc00000003000000) connect rom[350], UInt<64>(0h696669731b000000) connect rom[351], UInt<64>(0h306d6f722c6576) connect rom[352], UInt<64>(0h800000003000000) connect rom[353], UInt<64>(0h1002e010000) connect rom[354], UInt<64>(0h300000000000100) connect rom[355], UInt<64>(0ha801000004000000) connect rom[356], UInt<64>(0h2000000006d656d) connect rom[357], UInt<64>(0h7375627301000000) connect rom[358], UInt<64>(0h6b636f6c635f) connect rom[359], UInt<64>(0h400000003000000) connect rom[360], UInt<64>(0hde010000) connect rom[361], UInt<64>(0h400000003000000) connect rom[362], UInt<64>(0h65cd1d53000000) connect rom[363], UInt<64>(0hb00000003000000) connect rom[364], UInt<64>(0h73756273eb010000) connect rom[365], UInt<64>(0h6b636f6c635f) connect rom[366], UInt<64>(0hc00000003000000) connect rom[367], UInt<64>(0h657869661b000000) connect rom[368], UInt<64>(0h6b636f6c632d64) connect rom[369], UInt<64>(0h100000002000000) connect rom[370], UInt<64>(0h31406c6169726573) connect rom[371], UInt<64>(0h30303030323030) connect rom[372], UInt<64>(0h400000003000000) connect rom[373], UInt<64>(0h50000003d020000) connect rom[374], UInt<64>(0hd00000003000000) connect rom[375], UInt<64>(0h696669731b000000) connect rom[376], UInt<64>(0h30747261752c6576) connect rom[377], UInt<64>(0h300000000000000) connect rom[378], UInt<64>(0h4402000004000000) connect rom[379], UInt<64>(0h300000006000000) connect rom[380], UInt<64>(0h5502000004000000) connect rom[381], UInt<64>(0h300000001000000) connect rom[382], UInt<64>(0h2e01000008000000) connect rom[383], UInt<64>(0h10000000000210) connect rom[384], UInt<64>(0h800000003000000) connect rom[385], UInt<64>(0h746e6f63a8010000) connect rom[386], UInt<64>(0h2000000006c6f72) connect rom[387], UInt<64>(0h656c697401000000) connect rom[388], UInt<64>(0h732d74657365722d) connect rom[389], UInt<64>(0h3131407265747465) connect rom[390], UInt<64>(0h30303030) connect rom[391], UInt<64>(0h800000003000000) connect rom[392], UInt<64>(0h11002e010000) connect rom[393], UInt<64>(0h300000000100000) connect rom[394], UInt<64>(0ha801000008000000) connect rom[395], UInt<64>(0h6c6f72746e6f63) connect rom[396], UInt<64>(0h200000002000000) connect rom[397], UInt<64>(0h900000002000000) connect rom[398], UInt<64>(0h7373657264646123) connect rom[399], UInt<64>(0h2300736c6c65632d) connect rom[400], UInt<64>(0h6c65632d657a6973) connect rom[401], UInt<64>(0h61706d6f6300736c) connect rom[402], UInt<64>(0h6f6d00656c626974) connect rom[403], UInt<64>(0h69726573006c6564) connect rom[404], UInt<64>(0h6f64747300306c61) connect rom[405], UInt<64>(0h687461702d7475) connect rom[406], UInt<64>(0h65736162656d6974) connect rom[407], UInt<64>(0h6e6575716572662d) connect rom[408], UInt<64>(0h6b636f6c63007963) connect rom[409], UInt<64>(0h6e6575716572662d) connect rom[410], UInt<64>(0h6361632d64007963) connect rom[411], UInt<64>(0h6b636f6c622d6568) connect rom[412], UInt<64>(0h2d6400657a69732d) connect rom[413], UInt<64>(0h65732d6568636163) connect rom[414], UInt<64>(0h6361632d64007374) connect rom[415], UInt<64>(0h657a69732d6568) connect rom[416], UInt<64>(0h65732d626c742d64) connect rom[417], UInt<64>(0h626c742d64007374) connect rom[418], UInt<64>(0h656400657a69732d) connect rom[419], UInt<64>(0h7079745f65636976) connect rom[420], UInt<64>(0h6177647261680065) connect rom[421], UInt<64>(0h2d636578652d6572) connect rom[422], UInt<64>(0h696f706b61657262) connect rom[423], UInt<64>(0h746e756f632d746e) connect rom[424], UInt<64>(0h65686361632d6900) connect rom[425], UInt<64>(0h732d6b636f6c622d) connect rom[426], UInt<64>(0h61632d6900657a69) connect rom[427], UInt<64>(0h737465732d656863) connect rom[428], UInt<64>(0h65686361632d6900) connect rom[429], UInt<64>(0h2d6900657a69732d) connect rom[430], UInt<64>(0h737465732d626c74) connect rom[431], UInt<64>(0h732d626c742d6900) connect rom[432], UInt<64>(0h2d756d6d00657a69) connect rom[433], UInt<64>(0h78656e0065707974) connect rom[434], UInt<64>(0h2d6c6576656c2d74) connect rom[435], UInt<64>(0h6572006568636163) connect rom[436], UInt<64>(0h2c76637369720067) connect rom[437], UInt<64>(0h6373697200617369) connect rom[438], UInt<64>(0h617267706d702c76) connect rom[439], UInt<64>(0h79746972616c756e) connect rom[440], UInt<64>(0h702c766373697200) connect rom[441], UInt<64>(0h6e6f69676572706d) connect rom[442], UInt<64>(0h7375746174730073) connect rom[443], UInt<64>(0h6c70732d626c7400) connect rom[444], UInt<64>(0h65746e6923007469) connect rom[445], UInt<64>(0h65632d7470757272) connect rom[446], UInt<64>(0h65746e6900736c6c) connect rom[447], UInt<64>(0h6f632d7470757272) connect rom[448], UInt<64>(0h72656c6c6f72746e) connect rom[449], UInt<64>(0h656c646e61687000) connect rom[450], UInt<64>(0h7365676e617200) connect rom[451], UInt<64>(0h656d616e2d676572) connect rom[452], UInt<64>(0h2d65686361630073) connect rom[453], UInt<64>(0h6163006c6576656c) connect rom[454], UInt<64>(0h66696e752d656863) connect rom[455], UInt<64>(0h6966697300646569) connect rom[456], UInt<64>(0h2d7268736d2c6576) connect rom[457], UInt<64>(0h632300746e756f63) connect rom[458], UInt<64>(0h6c65632d6b636f6c) connect rom[459], UInt<64>(0h6b636f6c6300736c) connect rom[460], UInt<64>(0h2d74757074756f2d) connect rom[461], UInt<64>(0h6e690073656d616e) connect rom[462], UInt<64>(0h7374707572726574) connect rom[463], UInt<64>(0h65646e657478652d) connect rom[464], UInt<64>(0h2d67756265640064) connect rom[465], UInt<64>(0h7200686361747461) connect rom[466], UInt<64>(0h78616d2c76637369) connect rom[467], UInt<64>(0h7469726f6972702d) connect rom[468], UInt<64>(0h2c76637369720079) connect rom[469], UInt<64>(0h6f6c63007665646e) connect rom[470], UInt<64>(0h65746e6900736b63) connect rom[471], UInt<64>(0h61702d7470757272) connect rom[472], UInt<64>(0h746e6900746e6572) connect rom[473], UInt<64>(0h73747075727265) connect rom[474], UInt<64>(0h0) connect rom[475], UInt<64>(0h0) connect rom[476], UInt<64>(0h0) connect rom[477], UInt<64>(0h0) connect rom[478], UInt<64>(0h0) connect rom[479], UInt<64>(0h0) connect rom[480], UInt<64>(0h0) connect rom[481], UInt<64>(0h0) connect rom[482], UInt<64>(0h0) connect rom[483], UInt<64>(0h0) connect rom[484], UInt<64>(0h0) connect rom[485], UInt<64>(0h0) connect rom[486], UInt<64>(0h0) connect rom[487], UInt<64>(0h0) connect rom[488], UInt<64>(0h0) connect rom[489], UInt<64>(0h0) connect rom[490], UInt<64>(0h0) connect rom[491], UInt<64>(0h0) connect rom[492], UInt<64>(0h0) connect rom[493], UInt<64>(0h0) connect rom[494], UInt<64>(0h0) connect rom[495], UInt<64>(0h0) connect rom[496], UInt<64>(0h0) connect rom[497], UInt<64>(0h0) connect rom[498], UInt<64>(0h0) connect rom[499], UInt<64>(0h0) connect rom[500], UInt<64>(0h0) connect rom[501], UInt<64>(0h0) connect rom[502], UInt<64>(0h0) connect rom[503], UInt<64>(0h0) connect rom[504], UInt<64>(0h0) connect rom[505], UInt<64>(0h0) connect rom[506], UInt<64>(0h0) connect rom[507], UInt<64>(0h0) connect rom[508], UInt<64>(0h0) connect rom[509], UInt<64>(0h0) connect rom[510], UInt<64>(0h0) connect rom[511], UInt<64>(0h0) connect nodeIn.d.valid, nodeIn.a.valid connect nodeIn.a.ready, nodeIn.d.ready node index = bits(nodeIn.a.bits.address, 11, 3) node high = bits(nodeIn.a.bits.address, 15, 12) node _nodeIn_d_bits_T = orr(high) node _nodeIn_d_bits_T_1 = mux(_nodeIn_d_bits_T, UInt<1>(0h0), rom[index]) wire nodeIn_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} connect nodeIn_d_bits_d.opcode, UInt<1>(0h1) connect nodeIn_d_bits_d.param, UInt<1>(0h0) connect nodeIn_d_bits_d.size, nodeIn.a.bits.size connect nodeIn_d_bits_d.source, nodeIn.a.bits.source connect nodeIn_d_bits_d.sink, UInt<1>(0h0) connect nodeIn_d_bits_d.denied, UInt<1>(0h0) connect nodeIn_d_bits_d.data, _nodeIn_d_bits_T_1 connect nodeIn_d_bits_d.corrupt, UInt<1>(0h0) connect nodeIn.d.bits.corrupt, nodeIn_d_bits_d.corrupt connect nodeIn.d.bits.data, nodeIn_d_bits_d.data connect nodeIn.d.bits.denied, nodeIn_d_bits_d.denied connect nodeIn.d.bits.sink, nodeIn_d_bits_d.sink connect nodeIn.d.bits.source, nodeIn_d_bits_d.source connect nodeIn.d.bits.size, nodeIn_d_bits_d.size connect nodeIn.d.bits.param, nodeIn_d_bits_d.param connect nodeIn.d.bits.opcode, nodeIn_d_bits_d.opcode wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<17>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<17>(0h0) connect _WIRE.bits.source, UInt<11>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<17>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<17>(0h0) connect _WIRE_2.bits.source, UInt<11>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1)	module TLROM( // @[BootROM.scala:41:9] input clock, // @[BootROM.scala:41:9] input reset, // @[BootROM.scala:41:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [16:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[BootROM.scala:41:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[BootROM.scala:41:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[BootROM.scala:41:9] wire [1:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[BootROM.scala:41:9] wire [10:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[BootROM.scala:41:9] wire [16:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[BootROM.scala:41:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[BootROM.scala:41:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[BootROM.scala:41:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[BootROM.scala:41:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[BootROM.scala:41:9] wire [511:0][63:0] _GEN = '{64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h73747075727265, 64'h746E6900746E6572, 64'h61702D7470757272, 64'h65746E6900736B63, 64'h6F6C63007665646E, 64'h2C76637369720079, 64'h7469726F6972702D, 64'h78616D2C76637369, 64'h7200686361747461, 64'h2D67756265640064, 64'h65646E657478652D, 64'h7374707572726574, 64'h6E690073656D616E, 64'h2D74757074756F2D, 64'h6B636F6C6300736C, 64'h6C65632D6B636F6C, 64'h632300746E756F63, 64'h2D7268736D2C6576, 64'h6966697300646569, 64'h66696E752D656863, 64'h6163006C6576656C, 64'h2D65686361630073, 64'h656D616E2D676572, 64'h7365676E617200, 64'h656C646E61687000, 64'h72656C6C6F72746E, 64'h6F632D7470757272, 64'h65746E6900736C6C, 64'h65632D7470757272, 64'h65746E6923007469, 64'h6C70732D626C7400, 64'h7375746174730073, 64'h6E6F69676572706D, 64'h702C766373697200, 64'h79746972616C756E, 64'h617267706D702C76, 64'h6373697200617369, 64'h2C76637369720067, 64'h6572006568636163, 64'h2D6C6576656C2D74, 64'h78656E0065707974, 64'h2D756D6D00657A69, 64'h732D626C742D6900, 64'h737465732D626C74, 64'h2D6900657A69732D, 64'h65686361632D6900, 64'h737465732D656863, 64'h61632D6900657A69, 64'h732D6B636F6C622D, 64'h65686361632D6900, 64'h746E756F632D746E, 64'h696F706B61657262, 64'h2D636578652D6572, 64'h6177647261680065, 64'h7079745F65636976, 64'h656400657A69732D, 64'h626C742D64007374, 64'h65732D626C742D64, 64'h657A69732D6568, 64'h6361632D64007374, 64'h65732D6568636163, 64'h2D6400657A69732D, 64'h6B636F6C622D6568, 64'h6361632D64007963, 64'h6E6575716572662D, 64'h6B636F6C63007963, 64'h6E6575716572662D, 64'h65736162656D6974, 64'h687461702D7475, 64'h6F64747300306C61, 64'h69726573006C6564, 64'h6F6D00656C626974, 64'h61706D6F6300736C, 64'h6C65632D657A6973, 64'h2300736C6C65632D, 64'h7373657264646123, 64'h900000002000000, 64'h200000002000000, 64'h6C6F72746E6F63, 64'hA801000008000000, 64'h300000000100000, 64'h11002E010000, 64'h800000003000000, 64'h30303030, 64'h3131407265747465, 64'h732D74657365722D, 64'h656C697401000000, 64'h2000000006C6F72, 64'h746E6F63A8010000, 64'h800000003000000, 64'h10000000000210, 64'h2E01000008000000, 64'h300000001000000, 64'h5502000004000000, 64'h300000006000000, 64'h4402000004000000, 64'h300000000000000, 64'h30747261752C6576, 64'h696669731B000000, 64'hD00000003000000, 64'h50000003D020000, 64'h400000003000000, 64'h30303030323030, 64'h31406C6169726573, 64'h100000002000000, 64'h6B636F6C632D64, 64'h657869661B000000, 64'hC00000003000000, 64'h6B636F6C635F, 64'h73756273EB010000, 64'hB00000003000000, 64'h65CD1D53000000, 64'h400000003000000, 64'hDE010000, 64'h400000003000000, 64'h6B636F6C635F, 64'h7375627301000000, 64'h2000000006D656D, 64'hA801000004000000, 64'h300000000000100, 64'h1002E010000, 64'h800000003000000, 64'h306D6F722C6576, 64'h696669731B000000, 64'hC00000003000000, 64'h3030303031, 64'h406D6F7201000000, 64'h200000005000000, 64'h9901000004000000, 64'h3000000006B636F, 64'h6C632D6465786966, 64'h1B0000000C000000, 64'h300000000006B63, 64'h6F6C635F73756270, 64'hEB0100000B000000, 64'h30000000065CD1D, 64'h5300000004000000, 64'h300000000000000, 64'hDE01000004000000, 64'h300000000006B63, 64'h6F6C635F73756270, 64'h100000002000000, 64'h6B636F6C632D64, 64'h657869661B000000, 64'hC00000003000000, 64'h6B636F6C635F, 64'h7375626DEB010000, 64'hB00000003000000, 64'h65CD1D53000000, 64'h400000003000000, 64'hDE010000, 64'h400000003000000, 64'h6B636F6C635F, 64'h7375626D01000000, 64'h200000006000000, 64'h9901000004000000, 64'h300000001000000, 64'h3202000004000000, 64'h300000001000000, 64'h1F02000004000000, 64'h3000000006C6F72, 64'h746E6F63A8010000, 64'h800000003000000, 64'h40000000C, 64'h2E01000008000000, 64'h300000009000000, 64'h40000000B000000, 64'h4000000FE010000, 64'h1000000003000000, 64'h8401000000000000, 64'h300000000306369, 64'h6C702C7663736972, 64'h1B0000000C000000, 64'h300000001000000, 64'h7301000004000000, 64'h300000000000000, 64'h3030303030306340, 64'h72656C6C6F72746E, 64'h6F632D7470757272, 64'h65746E6901000000, 64'h2000000006B636F, 64'h6C632D6465786966, 64'h1B0000000C000000, 64'h300000000006B63, 64'h6F6C635F73756266, 64'hEB0100000B000000, 64'h30000000065CD1D, 64'h5300000004000000, 64'h300000000000000, 64'hDE01000004000000, 64'h300000000006B63, 64'h6F6C635F73756266, 64'h100000002000000, 64'h10000000300000, 64'h2E01000008000000, 64'h300000000000030, 64'h726F7272652C6576, 64'h696669731B000000, 64'hE00000003000000, 64'h3030303340, 64'h6563697665642D72, 64'h6F72726501000000, 64'h2000000006C6F72, 64'h746E6F63A8010000, 64'h800000003000000, 64'h10000000000000, 64'h2E01000008000000, 64'h3000000FFFF0000, 64'h4000000FE010000, 64'h800000003000000, 64'h6761746A, 64'h1202000005000000, 64'h300000000000000, 64'h3331302D67756265, 64'h642C766373697200, 64'h3331302D67756265, 64'h642C657669666973, 64'h1B00000021000000, 64'h300000000003040, 64'h72656C6C6F72746E, 64'h6F632D6775626564, 64'h100000002000000, 64'h6C6F72746E6F63, 64'hA801000008000000, 64'h300000000100000, 64'h10002E010000, 64'h800000003000000, 64'h303030303031, 64'h4072657461672D6B, 64'h636F6C6301000000, 64'h2000000006C6F72, 64'h746E6F63A8010000, 64'h800000003000000, 64'h10000000002, 64'h2E01000008000000, 64'h300000007000000, 64'h400000003000000, 64'h4000000FE010000, 64'h1000000003000000, 64'h30746E69, 64'h6C632C7663736972, 64'h1B0000000D000000, 64'h300000000000030, 64'h3030303030324074, 64'h6E696C6301000000, 64'h2000000006B636F, 64'h6C632D6465786966, 64'h1B0000000C000000, 64'h300000000006B63, 64'h6F6C635F73756263, 64'hEB0100000B000000, 64'h30000000065CD1D, 64'h5300000004000000, 64'h300000000000000, 64'hDE01000004000000, 64'h300000000006B63, 64'h6F6C635F73756263, 64'h100000002000000, 64'h100000099010000, 64'h400000003000000, 64'hC000000CC010000, 64'h400000003000000, 64'h6C6F72746E6F63, 64'hA801000008000000, 64'h300000000100000, 64'h1022E010000, 64'h800000003000000, 64'h300000002000000, 64'h1D01000008000000, 64'h300000000000000, 64'h6568636163003065, 64'h6863616365766973, 64'h756C636E692C6576, 64'h696669731B000000, 64'h1D00000003000000, 64'hBE01000000000000, 64'h300000000000001, 64'h8500000004000000, 64'h300000000400000, 64'h7800000004000000, 64'h300000002000000, 64'hB201000004000000, 64'h300000040000000, 64'h6500000004000000, 64'h300000000000000, 64'h3030303031303240, 64'h72656C6C6F72746E, 64'h6F632D6568636163, 64'h100000002000000, 64'h6C6F72746E6F63, 64'hA801000008000000, 64'h300000000100000, 64'h1000002E010000, 64'h800000003000000, 64'h3030303140, 64'h6765722D73736572, 64'h6464612D746F6F62, 64'h1000000A1010000, 64'h3000000, 64'h7375622D656C70, 64'h6D697300636F732D, 64'h6472617970696863, 64'h2C7261622D626375, 64'h1B00000020000000, 64'h300000001000000, 64'hF00000004000000, 64'h300000001000000, 64'h4000000, 64'h300000000636F73, 64'h100000002000000, 64'h200000099010000, 64'h400000003000000, 64'h1000000080, 64'h2E01000008000000, 64'h300000000007972, 64'h6F6D656DA6000000, 64'h700000003000000, 64'h30303030303030, 64'h384079726F6D656D, 64'h100000002000000, 64'h300000099010000, 64'h400000003000000, 64'h64656C62, 64'h6173696462010000, 64'h900000003000000, 64'h10000000008, 64'h2E01000008000000, 64'h300000000007972, 64'h6F6D656DA6000000, 64'h700000003000000, 64'h303030303030, 64'h384079726F6D656D, 64'h100000002000000, 64'h3066697468, 64'h2C6263751B000000, 64'hA00000003000000, 64'h66697468, 64'h100000002000000, 64'h200000002000000, 64'h400000099010000, 64'h400000003000000, 64'h8401000000000000, 64'h300000000006374, 64'h6E692D7570632C76, 64'h637369721B000000, 64'hF00000003000000, 64'h100000073010000, 64'h400000003000000, 64'h72656C6C, 64'h6F72746E6F632D74, 64'h7075727265746E69, 64'h100000069010000, 64'h3000000, 64'h20A1070040000000, 64'h400000003000000, 64'h79616B6F, 64'h6201000005000000, 64'h300000008000000, 64'h5101000004000000, 64'h300000004000000, 64'h3C01000004000000, 64'h30000000074656B, 64'h636F72785F73627A, 64'h5F62627A5F61627A, 64'h5F68667A5F6D7068, 64'h697A5F6965636E65, 64'h66697A5F72736369, 64'h7A62636466616D69, 64'h3436767232010000, 64'h3800000003000000, 64'h2E010000, 64'h400000003000000, 64'h10000001D010000, 64'h400000003000000, 64'h393376732C76, 64'h6373697214010000, 64'hB00000003000000, 64'h2000000009010000, 64'h400000003000000, 64'h1000000FE000000, 64'h400000003000000, 64'h800000F1000000, 64'h400000003000000, 64'h40000000E4000000, 64'h400000003000000, 64'h40000000D1000000, 64'h400000003000000, 64'h1000000B2000000, 64'h400000003000000, 64'h757063A6000000, 64'h400000003000000, 64'h200000009B000000, 64'h400000003000000, 64'h100000090000000, 64'h400000003000000, 64'h80000083000000, 64'h400000003000000, 64'h4000000076000000, 64'h400000003000000, 64'h4000000063000000, 64'h400000003000000, 64'h76637369, 64'h72003074656B636F, 64'h722C657669666973, 64'h1B00000015000000, 64'h300000000000000, 64'h5300000004000000, 64'h300000000000030, 64'h4075706301000000, 64'h20A1070040000000, 64'h400000003000000, 64'hF000000, 64'h400000003000000, 64'h100000000000000, 64'h400000003000000, 64'h73757063, 64'h100000002000000, 64'h30303030, 64'h32303031406C6169, 64'h7265732F636F732F, 64'h3400000015000000, 64'h300000000006E65, 64'h736F686301000000, 64'h200000000000000, 64'h3030303032303031, 64'h406C61697265732F, 64'h636F732F2C000000, 64'h1500000003000000, 64'h73657361696C61, 64'h100000000000000, 64'h6472617970696863, 64'h2C7261622D626375, 64'h2600000011000000, 64'h300000000000000, 64'h7665642D64726179, 64'h706968632C726162, 64'h2D6263751B000000, 64'h1500000003000000, 64'h10000000F000000, 64'h400000003000000, 64'h100000000000000, 64'h400000003000000, 64'h1000000, 64'h0, 64'h0, 64'h780B000060020000, 64'h10000000, 64'h1100000028000000, 64'hB00B000038000000, 64'h100E0000EDFE0DD0, 64'h1330200073, 64'h3006307308000613, 64'h185859300000597, 64'hF140257334151073, 64'h5350300001537, 64'h5A02300B505B3, 64'h251513FE029EE3, 64'h5A283F81FF06F, 64'h0, 64'h0, 64'h2C0006F, 64'hFE069AE3FFC62683, 64'h46061300D62023, 64'h10069300458613, 64'h380006F00050463, 64'hF1402573020005B7, 64'hFFDFF06F, 64'h1050007330052073, 64'h3045107300800513, 64'h3445307322200513, 64'h3030107300028863, 64'h12F2934122D293, 64'h301022F330551073, 64'h405051300000517}; wire [63:0] rom_0 = 64'h405051300000517; // @[BootROM.scala:50:22] wire [63:0] rom_1 = 64'h301022F330551073; // @[BootROM.scala:50:22] wire [63:0] rom_2 = 64'h12F2934122D293; // @[BootROM.scala:50:22] wire [63:0] rom_3 = 64'h3030107300028863; // @[BootROM.scala:50:22] wire [63:0] rom_4 = 64'h3445307322200513; // @[BootROM.scala:50:22] wire [63:0] rom_5 = 64'h3045107300800513; // @[BootROM.scala:50:22] wire [63:0] rom_6 = 64'h1050007330052073; // @[BootROM.scala:50:22] wire [63:0] rom_7 = 64'hFFDFF06F; // @[BootROM.scala:50:22] wire [63:0] rom_8 = 64'hF1402573020005B7; // @[BootROM.scala:50:22] wire [63:0] rom_9 = 64'h380006F00050463; // @[BootROM.scala:50:22] wire [63:0] rom_10 = 64'h10069300458613; // @[BootROM.scala:50:22] wire [63:0] rom_11 = 64'h46061300D62023; // @[BootROM.scala:50:22] wire [63:0] rom_12 = 64'hFE069AE3FFC62683; // @[BootROM.scala:50:22] wire [63:0] rom_13 = 64'h2C0006F; // @[BootROM.scala:50:22] wire [63:0] rom_16 = 64'h5A283F81FF06F; // @[BootROM.scala:50:22] wire [63:0] rom_17 = 64'h251513FE029EE3; // @[BootROM.scala:50:22] wire [63:0] rom_18 = 64'h5A02300B505B3; // @[BootROM.scala:50:22] wire [63:0] rom_19 = 64'h5350300001537; // @[BootROM.scala:50:22] wire [63:0] rom_20 = 64'hF140257334151073; // @[BootROM.scala:50:22] wire [63:0] rom_21 = 64'h185859300000597; // @[BootROM.scala:50:22] wire [63:0] rom_22 = 64'h3006307308000613; // @[BootROM.scala:50:22] wire [63:0] rom_23 = 64'h1330200073; // @[BootROM.scala:50:22] wire [63:0] rom_24 = 64'h100E0000EDFE0DD0; // @[BootROM.scala:50:22] wire [63:0] rom_25 = 64'hB00B000038000000; // @[BootROM.scala:50:22] wire [63:0] rom_26 = 64'h1100000028000000; // @[BootROM.scala:50:22] wire [63:0] rom_27 = 64'h10000000; // @[BootROM.scala:50:22] wire [63:0] rom_28 = 64'h780B000060020000; // @[BootROM.scala:50:22] wire [63:0] rom_31 = 64'h1000000; // @[BootROM.scala:50:22] wire [63:0] rom_35 = 64'h10000000F000000; // @[BootROM.scala:50:22] wire [63:0] rom_37 = 64'h2D6263751B000000; // @[BootROM.scala:50:22] wire [63:0] rom_38 = 64'h706968632C726162; // @[BootROM.scala:50:22] wire [63:0] rom_39 = 64'h7665642D64726179; // @[BootROM.scala:50:22] wire [63:0] rom_41 = 64'h2600000011000000; // @[BootROM.scala:50:22] wire [63:0] rom_45 = 64'h73657361696C61; // @[BootROM.scala:50:22] wire [63:0] rom_36 = 64'h1500000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_46 = 64'h1500000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_47 = 64'h636F732F2C000000; // @[BootROM.scala:50:22] wire [63:0] rom_48 = 64'h406C61697265732F; // @[BootROM.scala:50:22] wire [63:0] rom_49 = 64'h3030303032303031; // @[BootROM.scala:50:22] wire [63:0] rom_50 = 64'h200000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_51 = 64'h736F686301000000; // @[BootROM.scala:50:22] wire [63:0] rom_52 = 64'h300000000006E65; // @[BootROM.scala:50:22] wire [63:0] rom_53 = 64'h3400000015000000; // @[BootROM.scala:50:22] wire [63:0] rom_54 = 64'h7265732F636F732F; // @[BootROM.scala:50:22] wire [63:0] rom_55 = 64'h32303031406C6169; // @[BootROM.scala:50:22] wire [63:0] rom_58 = 64'h73757063; // @[BootROM.scala:50:22] wire [63:0] rom_33 = 64'h100000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_44 = 64'h100000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_60 = 64'h100000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_62 = 64'hF000000; // @[BootROM.scala:50:22] wire [63:0] rom_65 = 64'h4075706301000000; // @[BootROM.scala:50:22] wire [63:0] rom_69 = 64'h1B00000015000000; // @[BootROM.scala:50:22] wire [63:0] rom_70 = 64'h722C657669666973; // @[BootROM.scala:50:22] wire [63:0] rom_71 = 64'h72003074656B636F; // @[BootROM.scala:50:22] wire [63:0] rom_72 = 64'h76637369; // @[BootROM.scala:50:22] wire [63:0] rom_74 = 64'h4000000063000000; // @[BootROM.scala:50:22] wire [63:0] rom_76 = 64'h4000000076000000; // @[BootROM.scala:50:22] wire [63:0] rom_78 = 64'h80000083000000; // @[BootROM.scala:50:22] wire [63:0] rom_80 = 64'h100000090000000; // @[BootROM.scala:50:22] wire [63:0] rom_82 = 64'h200000009B000000; // @[BootROM.scala:50:22] wire [63:0] rom_84 = 64'h757063A6000000; // @[BootROM.scala:50:22] wire [63:0] rom_86 = 64'h1000000B2000000; // @[BootROM.scala:50:22] wire [63:0] rom_88 = 64'h40000000D1000000; // @[BootROM.scala:50:22] wire [63:0] rom_90 = 64'h40000000E4000000; // @[BootROM.scala:50:22] wire [63:0] rom_92 = 64'h800000F1000000; // @[BootROM.scala:50:22] wire [63:0] rom_94 = 64'h1000000FE000000; // @[BootROM.scala:50:22] wire [63:0] rom_96 = 64'h2000000009010000; // @[BootROM.scala:50:22] wire [63:0] rom_98 = 64'h6373697214010000; // @[BootROM.scala:50:22] wire [63:0] rom_99 = 64'h393376732C76; // @[BootROM.scala:50:22] wire [63:0] rom_101 = 64'h10000001D010000; // @[BootROM.scala:50:22] wire [63:0] rom_103 = 64'h2E010000; // @[BootROM.scala:50:22] wire [63:0] rom_104 = 64'h3800000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_105 = 64'h3436767232010000; // @[BootROM.scala:50:22] wire [63:0] rom_106 = 64'h7A62636466616D69; // @[BootROM.scala:50:22] wire [63:0] rom_107 = 64'h66697A5F72736369; // @[BootROM.scala:50:22] wire [63:0] rom_108 = 64'h697A5F6965636E65; // @[BootROM.scala:50:22] wire [63:0] rom_109 = 64'h5F68667A5F6D7068; // @[BootROM.scala:50:22] wire [63:0] rom_110 = 64'h5F62627A5F61627A; // @[BootROM.scala:50:22] wire [63:0] rom_111 = 64'h636F72785F73627A; // @[BootROM.scala:50:22] wire [63:0] rom_112 = 64'h30000000074656B; // @[BootROM.scala:50:22] wire [63:0] rom_113 = 64'h3C01000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_114 = 64'h300000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_115 = 64'h5101000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_116 = 64'h300000008000000; // @[BootROM.scala:50:22] wire [63:0] rom_117 = 64'h6201000005000000; // @[BootROM.scala:50:22] wire [63:0] rom_118 = 64'h79616B6F; // @[BootROM.scala:50:22] wire [63:0] rom_64 = 64'h20A1070040000000; // @[BootROM.scala:50:22] wire [63:0] rom_120 = 64'h20A1070040000000; // @[BootROM.scala:50:22] wire [63:0] rom_122 = 64'h100000069010000; // @[BootROM.scala:50:22] wire [63:0] rom_123 = 64'h7075727265746E69; // @[BootROM.scala:50:22] wire [63:0] rom_124 = 64'h6F72746E6F632D74; // @[BootROM.scala:50:22] wire [63:0] rom_125 = 64'h72656C6C; // @[BootROM.scala:50:22] wire [63:0] rom_127 = 64'h100000073010000; // @[BootROM.scala:50:22] wire [63:0] rom_128 = 64'hF00000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_129 = 64'h637369721B000000; // @[BootROM.scala:50:22] wire [63:0] rom_130 = 64'h6E692D7570632C76; // @[BootROM.scala:50:22] wire [63:0] rom_131 = 64'h300000000006374; // @[BootROM.scala:50:22] wire [63:0] rom_134 = 64'h400000099010000; // @[BootROM.scala:50:22] wire [63:0] rom_137 = 64'h66697468; // @[BootROM.scala:50:22] wire [63:0] rom_138 = 64'hA00000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_139 = 64'h2C6263751B000000; // @[BootROM.scala:50:22] wire [63:0] rom_140 = 64'h3066697468; // @[BootROM.scala:50:22] wire [63:0] rom_143 = 64'h303030303030; // @[BootROM.scala:50:22] wire [63:0] rom_148 = 64'h10000000008; // @[BootROM.scala:50:22] wire [63:0] rom_149 = 64'h900000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_150 = 64'h6173696462010000; // @[BootROM.scala:50:22] wire [63:0] rom_151 = 64'h64656C62; // @[BootROM.scala:50:22] wire [63:0] rom_153 = 64'h300000099010000; // @[BootROM.scala:50:22] wire [63:0] rom_142 = 64'h384079726F6D656D; // @[BootROM.scala:50:22] wire [63:0] rom_155 = 64'h384079726F6D656D; // @[BootROM.scala:50:22] wire [63:0] rom_156 = 64'h30303030303030; // @[BootROM.scala:50:22] wire [63:0] rom_144 = 64'h700000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_157 = 64'h700000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_145 = 64'h6F6D656DA6000000; // @[BootROM.scala:50:22] wire [63:0] rom_158 = 64'h6F6D656DA6000000; // @[BootROM.scala:50:22] wire [63:0] rom_146 = 64'h300000000007972; // @[BootROM.scala:50:22] wire [63:0] rom_159 = 64'h300000000007972; // @[BootROM.scala:50:22] wire [63:0] rom_161 = 64'h1000000080; // @[BootROM.scala:50:22] wire [63:0] rom_163 = 64'h200000099010000; // @[BootROM.scala:50:22] wire [63:0] rom_165 = 64'h300000000636F73; // @[BootROM.scala:50:22] wire [63:0] rom_166 = 64'h4000000; // @[BootROM.scala:50:22] wire [63:0] rom_168 = 64'hF00000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_170 = 64'h1B00000020000000; // @[BootROM.scala:50:22] wire [63:0] rom_42 = 64'h2C7261622D626375; // @[BootROM.scala:50:22] wire [63:0] rom_171 = 64'h2C7261622D626375; // @[BootROM.scala:50:22] wire [63:0] rom_43 = 64'h6472617970696863; // @[BootROM.scala:50:22] wire [63:0] rom_172 = 64'h6472617970696863; // @[BootROM.scala:50:22] wire [63:0] rom_173 = 64'h6D697300636F732D; // @[BootROM.scala:50:22] wire [63:0] rom_174 = 64'h7375622D656C70; // @[BootROM.scala:50:22] wire [63:0] rom_121 = 64'h3000000; // @[BootROM.scala:50:22] wire [63:0] rom_175 = 64'h3000000; // @[BootROM.scala:50:22] wire [63:0] rom_176 = 64'h1000000A1010000; // @[BootROM.scala:50:22] wire [63:0] rom_177 = 64'h6464612D746F6F62; // @[BootROM.scala:50:22] wire [63:0] rom_178 = 64'h6765722D73736572; // @[BootROM.scala:50:22] wire [63:0] rom_179 = 64'h3030303140; // @[BootROM.scala:50:22] wire [63:0] rom_181 = 64'h1000002E010000; // @[BootROM.scala:50:22] wire [63:0] rom_186 = 64'h6F632D6568636163; // @[BootROM.scala:50:22] wire [63:0] rom_188 = 64'h3030303031303240; // @[BootROM.scala:50:22] wire [63:0] rom_190 = 64'h6500000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_191 = 64'h300000040000000; // @[BootROM.scala:50:22] wire [63:0] rom_192 = 64'hB201000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_194 = 64'h7800000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_195 = 64'h300000000400000; // @[BootROM.scala:50:22] wire [63:0] rom_196 = 64'h8500000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_197 = 64'h300000000000001; // @[BootROM.scala:50:22] wire [63:0] rom_198 = 64'hBE01000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_199 = 64'h1D00000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_201 = 64'h756C636E692C6576; // @[BootROM.scala:50:22] wire [63:0] rom_202 = 64'h6863616365766973; // @[BootROM.scala:50:22] wire [63:0] rom_203 = 64'h6568636163003065; // @[BootROM.scala:50:22] wire [63:0] rom_205 = 64'h1D01000008000000; // @[BootROM.scala:50:22] wire [63:0] rom_193 = 64'h300000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_206 = 64'h300000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_208 = 64'h1022E010000; // @[BootROM.scala:50:22] wire [63:0] rom_213 = 64'hC000000CC010000; // @[BootROM.scala:50:22] wire [63:0] rom_215 = 64'h100000099010000; // @[BootROM.scala:50:22] wire [63:0] rom_217 = 64'h6F6C635F73756263; // @[BootROM.scala:50:22] wire [63:0] rom_224 = 64'h6F6C635F73756263; // @[BootROM.scala:50:22] wire [63:0] rom_229 = 64'h6E696C6301000000; // @[BootROM.scala:50:22] wire [63:0] rom_230 = 64'h3030303030324074; // @[BootROM.scala:50:22] wire [63:0] rom_232 = 64'h1B0000000D000000; // @[BootROM.scala:50:22] wire [63:0] rom_233 = 64'h6C632C7663736972; // @[BootROM.scala:50:22] wire [63:0] rom_234 = 64'h30746E69; // @[BootROM.scala:50:22] wire [63:0] rom_238 = 64'h300000007000000; // @[BootROM.scala:50:22] wire [63:0] rom_240 = 64'h10000000002; // @[BootROM.scala:50:22] wire [63:0] rom_244 = 64'h636F6C6301000000; // @[BootROM.scala:50:22] wire [63:0] rom_245 = 64'h4072657461672D6B; // @[BootROM.scala:50:22] wire [63:0] rom_246 = 64'h303030303031; // @[BootROM.scala:50:22] wire [63:0] rom_248 = 64'h10002E010000; // @[BootROM.scala:50:22] wire [63:0] rom_253 = 64'h6F632D6775626564; // @[BootROM.scala:50:22] wire [63:0] rom_255 = 64'h300000000003040; // @[BootROM.scala:50:22] wire [63:0] rom_256 = 64'h1B00000021000000; // @[BootROM.scala:50:22] wire [63:0] rom_257 = 64'h642C657669666973; // @[BootROM.scala:50:22] wire [63:0] rom_259 = 64'h642C766373697200; // @[BootROM.scala:50:22] wire [63:0] rom_258 = 64'h3331302D67756265; // @[BootROM.scala:50:22] wire [63:0] rom_260 = 64'h3331302D67756265; // @[BootROM.scala:50:22] wire [63:0] rom_262 = 64'h1202000005000000; // @[BootROM.scala:50:22] wire [63:0] rom_263 = 64'h6761746A; // @[BootROM.scala:50:22] wire [63:0] rom_266 = 64'h3000000FFFF0000; // @[BootROM.scala:50:22] wire [63:0] rom_268 = 64'h10000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_272 = 64'h6F72726501000000; // @[BootROM.scala:50:22] wire [63:0] rom_273 = 64'h6563697665642D72; // @[BootROM.scala:50:22] wire [63:0] rom_274 = 64'h3030303340; // @[BootROM.scala:50:22] wire [63:0] rom_275 = 64'hE00000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_277 = 64'h726F7272652C6576; // @[BootROM.scala:50:22] wire [63:0] rom_66 = 64'h300000000000030; // @[BootROM.scala:50:22] wire [63:0] rom_231 = 64'h300000000000030; // @[BootROM.scala:50:22] wire [63:0] rom_278 = 64'h300000000000030; // @[BootROM.scala:50:22] wire [63:0] rom_280 = 64'h10000000300000; // @[BootROM.scala:50:22] wire [63:0] rom_282 = 64'h6F6C635F73756266; // @[BootROM.scala:50:22] wire [63:0] rom_289 = 64'h6F6C635F73756266; // @[BootROM.scala:50:22] wire [63:0] rom_228 = 64'h2000000006B636F; // @[BootROM.scala:50:22] wire [63:0] rom_293 = 64'h2000000006B636F; // @[BootROM.scala:50:22] wire [63:0] rom_294 = 64'h65746E6901000000; // @[BootROM.scala:50:22] wire [63:0] rom_297 = 64'h3030303030306340; // @[BootROM.scala:50:22] wire [63:0] rom_299 = 64'h7301000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_302 = 64'h6C702C7663736972; // @[BootROM.scala:50:22] wire [63:0] rom_303 = 64'h300000000306369; // @[BootROM.scala:50:22] wire [63:0] rom_132 = 64'h8401000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_304 = 64'h8401000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_235 = 64'h1000000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_305 = 64'h1000000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_236 = 64'h4000000FE010000; // @[BootROM.scala:50:22] wire [63:0] rom_265 = 64'h4000000FE010000; // @[BootROM.scala:50:22] wire [63:0] rom_306 = 64'h4000000FE010000; // @[BootROM.scala:50:22] wire [63:0] rom_307 = 64'h40000000B000000; // @[BootROM.scala:50:22] wire [63:0] rom_308 = 64'h300000009000000; // @[BootROM.scala:50:22] wire [63:0] rom_310 = 64'h40000000C; // @[BootROM.scala:50:22] wire [63:0] rom_313 = 64'h3000000006C6F72; // @[BootROM.scala:50:22] wire [63:0] rom_314 = 64'h1F02000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_316 = 64'h3202000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_319 = 64'h200000006000000; // @[BootROM.scala:50:22] wire [63:0] rom_320 = 64'h7375626D01000000; // @[BootROM.scala:50:22] wire [63:0] rom_327 = 64'h7375626DEB010000; // @[BootROM.scala:50:22] wire [63:0] rom_219 = 64'hDE01000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_284 = 64'hDE01000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_335 = 64'hDE01000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_67 = 64'h5300000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_221 = 64'h5300000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_286 = 64'h5300000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_337 = 64'h5300000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_222 = 64'h30000000065CD1D; // @[BootROM.scala:50:22] wire [63:0] rom_287 = 64'h30000000065CD1D; // @[BootROM.scala:50:22] wire [63:0] rom_338 = 64'h30000000065CD1D; // @[BootROM.scala:50:22] wire [63:0] rom_223 = 64'hEB0100000B000000; // @[BootROM.scala:50:22] wire [63:0] rom_288 = 64'hEB0100000B000000; // @[BootROM.scala:50:22] wire [63:0] rom_339 = 64'hEB0100000B000000; // @[BootROM.scala:50:22] wire [63:0] rom_333 = 64'h6F6C635F73756270; // @[BootROM.scala:50:22] wire [63:0] rom_340 = 64'h6F6C635F73756270; // @[BootROM.scala:50:22] wire [63:0] rom_218 = 64'h300000000006B63; // @[BootROM.scala:50:22] wire [63:0] rom_225 = 64'h300000000006B63; // @[BootROM.scala:50:22] wire [63:0] rom_283 = 64'h300000000006B63; // @[BootROM.scala:50:22] wire [63:0] rom_290 = 64'h300000000006B63; // @[BootROM.scala:50:22] wire [63:0] rom_334 = 64'h300000000006B63; // @[BootROM.scala:50:22] wire [63:0] rom_341 = 64'h300000000006B63; // @[BootROM.scala:50:22] wire [63:0] rom_226 = 64'h1B0000000C000000; // @[BootROM.scala:50:22] wire [63:0] rom_291 = 64'h1B0000000C000000; // @[BootROM.scala:50:22] wire [63:0] rom_301 = 64'h1B0000000C000000; // @[BootROM.scala:50:22] wire [63:0] rom_342 = 64'h1B0000000C000000; // @[BootROM.scala:50:22] wire [63:0] rom_227 = 64'h6C632D6465786966; // @[BootROM.scala:50:22] wire [63:0] rom_292 = 64'h6C632D6465786966; // @[BootROM.scala:50:22] wire [63:0] rom_343 = 64'h6C632D6465786966; // @[BootROM.scala:50:22] wire [63:0] rom_344 = 64'h3000000006B636F; // @[BootROM.scala:50:22] wire [63:0] rom_318 = 64'h9901000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_345 = 64'h9901000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_346 = 64'h200000005000000; // @[BootROM.scala:50:22] wire [63:0] rom_347 = 64'h406D6F7201000000; // @[BootROM.scala:50:22] wire [63:0] rom_348 = 64'h3030303031; // @[BootROM.scala:50:22] wire [63:0] rom_351 = 64'h306D6F722C6576; // @[BootROM.scala:50:22] wire [63:0] rom_353 = 64'h1002E010000; // @[BootROM.scala:50:22] wire [63:0] rom_354 = 64'h300000000000100; // @[BootROM.scala:50:22] wire [63:0] rom_355 = 64'hA801000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_356 = 64'h2000000006D656D; // @[BootROM.scala:50:22] wire [63:0] rom_357 = 64'h7375627301000000; // @[BootROM.scala:50:22] wire [63:0] rom_323 = 64'hDE010000; // @[BootROM.scala:50:22] wire [63:0] rom_360 = 64'hDE010000; // @[BootROM.scala:50:22] wire [63:0] rom_325 = 64'h65CD1D53000000; // @[BootROM.scala:50:22] wire [63:0] rom_362 = 64'h65CD1D53000000; // @[BootROM.scala:50:22] wire [63:0] rom_97 = 64'hB00000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_326 = 64'hB00000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_363 = 64'hB00000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_364 = 64'h73756273EB010000; // @[BootROM.scala:50:22] wire [63:0] rom_321 = 64'h6B636F6C635F; // @[BootROM.scala:50:22] wire [63:0] rom_328 = 64'h6B636F6C635F; // @[BootROM.scala:50:22] wire [63:0] rom_358 = 64'h6B636F6C635F; // @[BootROM.scala:50:22] wire [63:0] rom_365 = 64'h6B636F6C635F; // @[BootROM.scala:50:22] wire [63:0] rom_329 = 64'hC00000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_349 = 64'hC00000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_366 = 64'hC00000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_330 = 64'h657869661B000000; // @[BootROM.scala:50:22] wire [63:0] rom_367 = 64'h657869661B000000; // @[BootROM.scala:50:22] wire [63:0] rom_331 = 64'h6B636F6C632D64; // @[BootROM.scala:50:22] wire [63:0] rom_368 = 64'h6B636F6C632D64; // @[BootROM.scala:50:22] wire [63:0] rom_57 = 64'h100000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_136 = 64'h100000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_141 = 64'h100000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_154 = 64'h100000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_164 = 64'h100000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_185 = 64'h100000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_216 = 64'h100000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_252 = 64'h100000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_281 = 64'h100000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_332 = 64'h100000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_369 = 64'h100000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_370 = 64'h31406C6169726573; // @[BootROM.scala:50:22] wire [63:0] rom_371 = 64'h30303030323030; // @[BootROM.scala:50:22] wire [63:0] rom_32 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_34 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_59 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_61 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_63 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_73 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_75 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_77 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_79 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_81 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_83 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_85 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_87 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_89 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_91 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_93 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_95 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_100 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_102 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_119 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_126 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_133 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_152 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_162 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_212 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_214 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_237 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_322 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_324 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_359 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_361 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_372 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_373 = 64'h50000003D020000; // @[BootROM.scala:50:22] wire [63:0] rom_374 = 64'hD00000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_200 = 64'h696669731B000000; // @[BootROM.scala:50:22] wire [63:0] rom_276 = 64'h696669731B000000; // @[BootROM.scala:50:22] wire [63:0] rom_350 = 64'h696669731B000000; // @[BootROM.scala:50:22] wire [63:0] rom_375 = 64'h696669731B000000; // @[BootROM.scala:50:22] wire [63:0] rom_376 = 64'h30747261752C6576; // @[BootROM.scala:50:22] wire [63:0] rom_40 = 64'h300000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_68 = 64'h300000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_189 = 64'h300000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_204 = 64'h300000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_220 = 64'h300000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_261 = 64'h300000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_285 = 64'h300000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_298 = 64'h300000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_336 = 64'h300000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_377 = 64'h300000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_378 = 64'h4402000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_379 = 64'h300000006000000; // @[BootROM.scala:50:22] wire [63:0] rom_380 = 64'h5502000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_167 = 64'h300000001000000; // @[BootROM.scala:50:22] wire [63:0] rom_169 = 64'h300000001000000; // @[BootROM.scala:50:22] wire [63:0] rom_300 = 64'h300000001000000; // @[BootROM.scala:50:22] wire [63:0] rom_315 = 64'h300000001000000; // @[BootROM.scala:50:22] wire [63:0] rom_317 = 64'h300000001000000; // @[BootROM.scala:50:22] wire [63:0] rom_381 = 64'h300000001000000; // @[BootROM.scala:50:22] wire [63:0] rom_147 = 64'h2E01000008000000; // @[BootROM.scala:50:22] wire [63:0] rom_160 = 64'h2E01000008000000; // @[BootROM.scala:50:22] wire [63:0] rom_239 = 64'h2E01000008000000; // @[BootROM.scala:50:22] wire [63:0] rom_267 = 64'h2E01000008000000; // @[BootROM.scala:50:22] wire [63:0] rom_279 = 64'h2E01000008000000; // @[BootROM.scala:50:22] wire [63:0] rom_309 = 64'h2E01000008000000; // @[BootROM.scala:50:22] wire [63:0] rom_382 = 64'h2E01000008000000; // @[BootROM.scala:50:22] wire [63:0] rom_383 = 64'h10000000000210; // @[BootROM.scala:50:22] wire [63:0] rom_242 = 64'h746E6F63A8010000; // @[BootROM.scala:50:22] wire [63:0] rom_270 = 64'h746E6F63A8010000; // @[BootROM.scala:50:22] wire [63:0] rom_312 = 64'h746E6F63A8010000; // @[BootROM.scala:50:22] wire [63:0] rom_385 = 64'h746E6F63A8010000; // @[BootROM.scala:50:22] wire [63:0] rom_243 = 64'h2000000006C6F72; // @[BootROM.scala:50:22] wire [63:0] rom_271 = 64'h2000000006C6F72; // @[BootROM.scala:50:22] wire [63:0] rom_386 = 64'h2000000006C6F72; // @[BootROM.scala:50:22] wire [63:0] rom_387 = 64'h656C697401000000; // @[BootROM.scala:50:22] wire [63:0] rom_388 = 64'h732D74657365722D; // @[BootROM.scala:50:22] wire [63:0] rom_389 = 64'h3131407265747465; // @[BootROM.scala:50:22] wire [63:0] rom_56 = 64'h30303030; // @[BootROM.scala:50:22] wire [63:0] rom_390 = 64'h30303030; // @[BootROM.scala:50:22] wire [63:0] rom_180 = 64'h800000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_207 = 64'h800000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_241 = 64'h800000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_247 = 64'h800000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_264 = 64'h800000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_269 = 64'h800000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_311 = 64'h800000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_352 = 64'h800000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_384 = 64'h800000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_391 = 64'h800000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_392 = 64'h11002E010000; // @[BootROM.scala:50:22] wire [63:0] rom_182 = 64'h300000000100000; // @[BootROM.scala:50:22] wire [63:0] rom_209 = 64'h300000000100000; // @[BootROM.scala:50:22] wire [63:0] rom_249 = 64'h300000000100000; // @[BootROM.scala:50:22] wire [63:0] rom_393 = 64'h300000000100000; // @[BootROM.scala:50:22] wire [63:0] rom_183 = 64'hA801000008000000; // @[BootROM.scala:50:22] wire [63:0] rom_210 = 64'hA801000008000000; // @[BootROM.scala:50:22] wire [63:0] rom_250 = 64'hA801000008000000; // @[BootROM.scala:50:22] wire [63:0] rom_394 = 64'hA801000008000000; // @[BootROM.scala:50:22] wire [63:0] rom_184 = 64'h6C6F72746E6F63; // @[BootROM.scala:50:22] wire [63:0] rom_211 = 64'h6C6F72746E6F63; // @[BootROM.scala:50:22] wire [63:0] rom_251 = 64'h6C6F72746E6F63; // @[BootROM.scala:50:22] wire [63:0] rom_395 = 64'h6C6F72746E6F63; // @[BootROM.scala:50:22] wire [63:0] rom_135 = 64'h200000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_396 = 64'h200000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_397 = 64'h900000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_398 = 64'h7373657264646123; // @[BootROM.scala:50:22] wire [63:0] rom_399 = 64'h2300736C6C65632D; // @[BootROM.scala:50:22] wire [63:0] rom_400 = 64'h6C65632D657A6973; // @[BootROM.scala:50:22] wire [63:0] rom_401 = 64'h61706D6F6300736C; // @[BootROM.scala:50:22] wire [63:0] rom_402 = 64'h6F6D00656C626974; // @[BootROM.scala:50:22] wire [63:0] rom_403 = 64'h69726573006C6564; // @[BootROM.scala:50:22] wire [63:0] rom_404 = 64'h6F64747300306C61; // @[BootROM.scala:50:22] wire [63:0] rom_405 = 64'h687461702D7475; // @[BootROM.scala:50:22] wire [63:0] rom_406 = 64'h65736162656D6974; // @[BootROM.scala:50:22] wire [63:0] rom_408 = 64'h6B636F6C63007963; // @[BootROM.scala:50:22] wire [63:0] rom_407 = 64'h6E6575716572662D; // @[BootROM.scala:50:22] wire [63:0] rom_409 = 64'h6E6575716572662D; // @[BootROM.scala:50:22] wire [63:0] rom_410 = 64'h6361632D64007963; // @[BootROM.scala:50:22] wire [63:0] rom_411 = 64'h6B636F6C622D6568; // @[BootROM.scala:50:22] wire [63:0] rom_412 = 64'h2D6400657A69732D; // @[BootROM.scala:50:22] wire [63:0] rom_413 = 64'h65732D6568636163; // @[BootROM.scala:50:22] wire [63:0] rom_414 = 64'h6361632D64007374; // @[BootROM.scala:50:22] wire [63:0] rom_415 = 64'h657A69732D6568; // @[BootROM.scala:50:22] wire [63:0] rom_416 = 64'h65732D626C742D64; // @[BootROM.scala:50:22] wire [63:0] rom_417 = 64'h626C742D64007374; // @[BootROM.scala:50:22] wire [63:0] rom_418 = 64'h656400657A69732D; // @[BootROM.scala:50:22] wire [63:0] rom_419 = 64'h7079745F65636976; // @[BootROM.scala:50:22] wire [63:0] rom_420 = 64'h6177647261680065; // @[BootROM.scala:50:22] wire [63:0] rom_421 = 64'h2D636578652D6572; // @[BootROM.scala:50:22] wire [63:0] rom_422 = 64'h696F706B61657262; // @[BootROM.scala:50:22] wire [63:0] rom_423 = 64'h746E756F632D746E; // @[BootROM.scala:50:22] wire [63:0] rom_425 = 64'h732D6B636F6C622D; // @[BootROM.scala:50:22] wire [63:0] rom_426 = 64'h61632D6900657A69; // @[BootROM.scala:50:22] wire [63:0] rom_427 = 64'h737465732D656863; // @[BootROM.scala:50:22] wire [63:0] rom_424 = 64'h65686361632D6900; // @[BootROM.scala:50:22] wire [63:0] rom_428 = 64'h65686361632D6900; // @[BootROM.scala:50:22] wire [63:0] rom_429 = 64'h2D6900657A69732D; // @[BootROM.scala:50:22] wire [63:0] rom_430 = 64'h737465732D626C74; // @[BootROM.scala:50:22] wire [63:0] rom_431 = 64'h732D626C742D6900; // @[BootROM.scala:50:22] wire [63:0] rom_432 = 64'h2D756D6D00657A69; // @[BootROM.scala:50:22] wire [63:0] rom_433 = 64'h78656E0065707974; // @[BootROM.scala:50:22] wire [63:0] rom_434 = 64'h2D6C6576656C2D74; // @[BootROM.scala:50:22] wire [63:0] rom_435 = 64'h6572006568636163; // @[BootROM.scala:50:22] wire [63:0] rom_436 = 64'h2C76637369720067; // @[BootROM.scala:50:22] wire [63:0] rom_437 = 64'h6373697200617369; // @[BootROM.scala:50:22] wire [63:0] rom_438 = 64'h617267706D702C76; // @[BootROM.scala:50:22] wire [63:0] rom_439 = 64'h79746972616C756E; // @[BootROM.scala:50:22] wire [63:0] rom_440 = 64'h702C766373697200; // @[BootROM.scala:50:22] wire [63:0] rom_441 = 64'h6E6F69676572706D; // @[BootROM.scala:50:22] wire [63:0] rom_442 = 64'h7375746174730073; // @[BootROM.scala:50:22] wire [63:0] rom_443 = 64'h6C70732D626C7400; // @[BootROM.scala:50:22] wire [63:0] rom_444 = 64'h65746E6923007469; // @[BootROM.scala:50:22] wire [63:0] rom_445 = 64'h65632D7470757272; // @[BootROM.scala:50:22] wire [63:0] rom_446 = 64'h65746E6900736C6C; // @[BootROM.scala:50:22] wire [63:0] rom_295 = 64'h6F632D7470757272; // @[BootROM.scala:50:22] wire [63:0] rom_447 = 64'h6F632D7470757272; // @[BootROM.scala:50:22] wire [63:0] rom_187 = 64'h72656C6C6F72746E; // @[BootROM.scala:50:22] wire [63:0] rom_254 = 64'h72656C6C6F72746E; // @[BootROM.scala:50:22] wire [63:0] rom_296 = 64'h72656C6C6F72746E; // @[BootROM.scala:50:22] wire [63:0] rom_448 = 64'h72656C6C6F72746E; // @[BootROM.scala:50:22] wire [63:0] rom_449 = 64'h656C646E61687000; // @[BootROM.scala:50:22] wire [63:0] rom_450 = 64'h7365676E617200; // @[BootROM.scala:50:22] wire [63:0] rom_451 = 64'h656D616E2D676572; // @[BootROM.scala:50:22] wire [63:0] rom_452 = 64'h2D65686361630073; // @[BootROM.scala:50:22] wire [63:0] rom_453 = 64'h6163006C6576656C; // @[BootROM.scala:50:22] wire [63:0] rom_454 = 64'h66696E752D656863; // @[BootROM.scala:50:22] wire [63:0] rom_455 = 64'h6966697300646569; // @[BootROM.scala:50:22] wire [63:0] rom_456 = 64'h2D7268736D2C6576; // @[BootROM.scala:50:22] wire [63:0] rom_457 = 64'h632300746E756F63; // @[BootROM.scala:50:22] wire [63:0] rom_458 = 64'h6C65632D6B636F6C; // @[BootROM.scala:50:22] wire [63:0] rom_459 = 64'h6B636F6C6300736C; // @[BootROM.scala:50:22] wire [63:0] rom_460 = 64'h2D74757074756F2D; // @[BootROM.scala:50:22] wire [63:0] rom_461 = 64'h6E690073656D616E; // @[BootROM.scala:50:22] wire [63:0] rom_462 = 64'h7374707572726574; // @[BootROM.scala:50:22] wire [63:0] rom_463 = 64'h65646E657478652D; // @[BootROM.scala:50:22] wire [63:0] rom_464 = 64'h2D67756265640064; // @[BootROM.scala:50:22] wire [63:0] rom_465 = 64'h7200686361747461; // @[BootROM.scala:50:22] wire [63:0] rom_466 = 64'h78616D2C76637369; // @[BootROM.scala:50:22] wire [63:0] rom_467 = 64'h7469726F6972702D; // @[BootROM.scala:50:22] wire [63:0] rom_468 = 64'h2C76637369720079; // @[BootROM.scala:50:22] wire [63:0] rom_469 = 64'h6F6C63007665646E; // @[BootROM.scala:50:22] wire [63:0] rom_470 = 64'h65746E6900736B63; // @[BootROM.scala:50:22] wire [63:0] rom_471 = 64'h61702D7470757272; // @[BootROM.scala:50:22] wire [63:0] rom_472 = 64'h746E6900746E6572; // @[BootROM.scala:50:22] wire [63:0] rom_473 = 64'h73747075727265; // @[BootROM.scala:50:22] wire [63:0] rom_14 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_15 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_29 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_30 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_474 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_475 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_476 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_477 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_478 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_479 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_480 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_481 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_482 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_483 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_484 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_485 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_486 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_487 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_488 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_489 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_490 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_491 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_492 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_493 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_494 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_495 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_496 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_497 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_498 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_499 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_500 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_501 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_502 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_503 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_504 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_505 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_506 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_507 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_508 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_509 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_510 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_511 = 64'h0; // @[BootROM.scala:50:22] wire auto_in_d_bits_sink = 1'h0; // @[BootROM.scala:41:9] wire auto_in_d_bits_denied = 1'h0; // @[BootROM.scala:41:9] wire auto_in_d_bits_corrupt = 1'h0; // @[BootROM.scala:41:9] wire nodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:810:17] wire nodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:810:17] wire nodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:810:17] wire [1:0] auto_in_d_bits_param = 2'h0; // @[BootROM.scala:41:9] wire [1:0] nodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:810:17] wire [2:0] auto_in_d_bits_opcode = 3'h1; // @[BootROM.scala:41:9] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode = 3'h1; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_d_opcode = 3'h1; // @[Edges.scala:810:17] wire nodeIn_a_valid = auto_in_a_valid_0; // @[BootROM.scala:41:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[BootROM.scala:41:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[BootROM.scala:41:9] wire [1:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[BootROM.scala:41:9] wire [10:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[BootROM.scala:41:9] wire [16:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[BootROM.scala:41:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[BootROM.scala:41:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[BootROM.scala:41:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[BootROM.scala:41:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[BootROM.scala:41:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [10:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire auto_in_a_ready_0; // @[BootROM.scala:41:9] wire [1:0] auto_in_d_bits_size_0; // @[BootROM.scala:41:9] wire [10:0] auto_in_d_bits_source_0; // @[BootROM.scala:41:9] wire [63:0] auto_in_d_bits_data_0; // @[BootROM.scala:41:9] wire auto_in_d_valid_0; // @[BootROM.scala:41:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[BootROM.scala:41:9] assign nodeIn_d_valid = nodeIn_a_valid; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_d_size = nodeIn_a_bits_size; // @[Edges.scala:810:17] wire [10:0] nodeIn_d_bits_d_source = nodeIn_a_bits_source; // @[Edges.scala:810:17] assign nodeIn_a_ready = nodeIn_d_ready; // @[MixedNode.scala:551:17] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[BootROM.scala:41:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[BootROM.scala:41:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[BootROM.scala:41:9] wire [63:0] nodeIn_d_bits_d_data; // @[Edges.scala:810:17] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[BootROM.scala:41:9] wire [8:0] index = nodeIn_a_bits_address[11:3]; // @[BootROM.scala:55:34] wire [3:0] high = nodeIn_a_bits_address[15:12]; // @[BootROM.scala:56:64] wire _nodeIn_d_bits_T = \|high; // @[BootROM.scala:56:64, :57:53] wire [63:0] _nodeIn_d_bits_T_1 = _nodeIn_d_bits_T ? 64'h0 : _GEN[index]; // @[BootROM.scala:55:34, :57:{47,53}] assign nodeIn_d_bits_d_data = _nodeIn_d_bits_T_1; // @[Edges.scala:810:17] assign nodeIn_d_bits_size = nodeIn_d_bits_d_size; // @[Edges.scala:810:17] assign nodeIn_d_bits_source = nodeIn_d_bits_d_source; // @[Edges.scala:810:17] assign nodeIn_d_bits_data = nodeIn_d_bits_d_data; // @[Edges.scala:810:17] TLMonitor_95 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] assign auto_in_a_ready = auto_in_a_ready_0; // @[BootROM.scala:41:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[BootROM.scala:41:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[BootROM.scala:41:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[BootROM.scala:41:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[BootROM.scala:41:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module Tile_213 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_469 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a	module Tile_213( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0 // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] PE_469 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module CLINTClockSinkDomain : output auto : { flip clint_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, int_in_clock_xing_out_1 : { sync : UInt<1>[2]}, int_in_clock_xing_out_0 : { sync : UInt<1>[2]}, flip clock_in : { clock : Clock, reset : Reset}} input tick : UInt<1> output clock : Clock output reset : Reset wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset inst clint of CLINT connect clint.clock, childClock connect clint.reset, childReset inst intsource of IntSyncCrossingSource_n1x2 connect intsource.clock, childClock connect intsource.reset, childReset inst intsource_1 of IntSyncCrossingSource_n1x2_1 connect intsource_1.clock, childClock connect intsource_1.reset, childReset wire clockNodeIn : { clock : Clock, reset : Reset} invalidate clockNodeIn.reset invalidate clockNodeIn.clock wire intInClockXingOut : { sync : UInt<1>[2]} invalidate intInClockXingOut.sync[0] invalidate intInClockXingOut.sync[1] wire intInClockXingIn : { sync : UInt<1>[2]} invalidate intInClockXingIn.sync[0] invalidate intInClockXingIn.sync[1] connect intInClockXingOut, intInClockXingIn wire intInClockXingOut_1 : { sync : UInt<1>[2]} invalidate intInClockXingOut_1.sync[0] invalidate intInClockXingOut_1.sync[1] wire intInClockXingIn_1 : { sync : UInt<1>[2]} invalidate intInClockXingIn_1.sync[0] invalidate intInClockXingIn_1.sync[1] connect intInClockXingOut_1, intInClockXingIn_1 connect intsource.auto.in[0], clint.auto.int_out_0[0] connect intsource.auto.in[1], clint.auto.int_out_0[1] connect intsource_1.auto.in[0], clint.auto.int_out_1[0] connect intsource_1.auto.in[1], clint.auto.int_out_1[1] connect intInClockXingIn, intsource.auto.out connect intInClockXingIn_1, intsource_1.auto.out connect clockNodeIn, auto.clock_in connect auto.int_in_clock_xing_out_0, intInClockXingOut connect auto.int_in_clock_xing_out_1, intInClockXingOut_1 connect clint.auto.in, auto.clint_in connect clint.io.rtcTick, tick connect childClock, clockNodeIn.clock connect childReset, clockNodeIn.reset connect clock, clockNodeIn.clock connect reset, clockNodeIn.reset extmodule plusarg_reader_92 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_93 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32	module CLINTClockSinkDomain( // @[ClockDomain.scala:14:9] output auto_clint_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_clint_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_clint_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_clint_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_clint_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_clint_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [25:0] auto_clint_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_clint_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_clint_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_clint_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_clint_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_clint_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_clint_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_clint_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_clint_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_clint_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_int_in_clock_xing_out_1_sync_0, // @[LazyModuleImp.scala:107:25] output auto_int_in_clock_xing_out_1_sync_1, // @[LazyModuleImp.scala:107:25] output auto_int_in_clock_xing_out_0_sync_0, // @[LazyModuleImp.scala:107:25] output auto_int_in_clock_xing_out_0_sync_1, // @[LazyModuleImp.scala:107:25] input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25] input auto_clock_in_reset, // @[LazyModuleImp.scala:107:25] input tick, // @[CLINT.scala:115:20] output clock, // @[ClockDomain.scala:21:19] output reset // @[ClockDomain.scala:22:19] ); wire _clint_auto_int_out_1_0; // @[CLINT.scala:112:48] wire _clint_auto_int_out_1_1; // @[CLINT.scala:112:48] wire _clint_auto_int_out_0_0; // @[CLINT.scala:112:48] wire _clint_auto_int_out_0_1; // @[CLINT.scala:112:48] wire auto_clint_in_a_valid_0 = auto_clint_in_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_clint_in_a_bits_opcode_0 = auto_clint_in_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] auto_clint_in_a_bits_param_0 = auto_clint_in_a_bits_param; // @[ClockDomain.scala:14:9] wire [1:0] auto_clint_in_a_bits_size_0 = auto_clint_in_a_bits_size; // @[ClockDomain.scala:14:9] wire [10:0] auto_clint_in_a_bits_source_0 = auto_clint_in_a_bits_source; // @[ClockDomain.scala:14:9] wire [25:0] auto_clint_in_a_bits_address_0 = auto_clint_in_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] auto_clint_in_a_bits_mask_0 = auto_clint_in_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] auto_clint_in_a_bits_data_0 = auto_clint_in_a_bits_data; // @[ClockDomain.scala:14:9] wire auto_clint_in_a_bits_corrupt_0 = auto_clint_in_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_clint_in_d_ready_0 = auto_clint_in_d_ready; // @[ClockDomain.scala:14:9] wire auto_clock_in_clock_0 = auto_clock_in_clock; // @[ClockDomain.scala:14:9] wire auto_clock_in_reset_0 = auto_clock_in_reset; // @[ClockDomain.scala:14:9] wire auto_clint_in_d_bits_sink = 1'h0; // @[ClockDomain.scala:14:9] wire auto_clint_in_d_bits_denied = 1'h0; // @[ClockDomain.scala:14:9] wire auto_clint_in_d_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9] wire _childClock_T = 1'h0; // @[ClockDomain.scala:14:9] wire [1:0] auto_clint_in_d_bits_param = 2'h0; // @[ClockDomain.scala:14:9] wire intInClockXingOut_1_sync_0; // @[MixedNode.scala:542:17] wire intInClockXingOut_1_sync_1; // @[MixedNode.scala:542:17] wire intInClockXingOut_sync_0; // @[MixedNode.scala:542:17] wire intInClockXingOut_sync_1; // @[MixedNode.scala:542:17] wire clockNodeIn_clock = auto_clock_in_clock_0; // @[ClockDomain.scala:14:9] wire clockNodeIn_reset = auto_clock_in_reset_0; // @[ClockDomain.scala:14:9] wire auto_clint_in_a_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_clint_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_clint_in_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [10:0] auto_clint_in_d_bits_source_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_clint_in_d_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_clint_in_d_valid_0; // @[ClockDomain.scala:14:9] wire auto_int_in_clock_xing_out_1_sync_0_0; // @[ClockDomain.scala:14:9] wire auto_int_in_clock_xing_out_1_sync_1_0; // @[ClockDomain.scala:14:9] wire auto_int_in_clock_xing_out_0_sync_0_0; // @[ClockDomain.scala:14:9] wire auto_int_in_clock_xing_out_0_sync_1_0; // @[ClockDomain.scala:14:9] wire childClock; // @[LazyModuleImp.scala:155:31] wire childReset; // @[LazyModuleImp.scala:158:31] assign childClock = clockNodeIn_clock; // @[MixedNode.scala:551:17] assign childReset = clockNodeIn_reset; // @[MixedNode.scala:551:17] wire intInClockXingIn_sync_0; // @[MixedNode.scala:551:17] assign auto_int_in_clock_xing_out_0_sync_0_0 = intInClockXingOut_sync_0; // @[ClockDomain.scala:14:9] wire intInClockXingIn_sync_1; // @[MixedNode.scala:551:17] assign auto_int_in_clock_xing_out_0_sync_1_0 = intInClockXingOut_sync_1; // @[ClockDomain.scala:14:9] assign intInClockXingOut_sync_0 = intInClockXingIn_sync_0; // @[MixedNode.scala:542:17, :551:17] assign intInClockXingOut_sync_1 = intInClockXingIn_sync_1; // @[MixedNode.scala:542:17, :551:17] wire intInClockXingIn_1_sync_0; // @[MixedNode.scala:551:17] assign auto_int_in_clock_xing_out_1_sync_0_0 = intInClockXingOut_1_sync_0; // @[ClockDomain.scala:14:9] wire intInClockXingIn_1_sync_1; // @[MixedNode.scala:551:17] assign auto_int_in_clock_xing_out_1_sync_1_0 = intInClockXingOut_1_sync_1; // @[ClockDomain.scala:14:9] assign intInClockXingOut_1_sync_0 = intInClockXingIn_1_sync_0; // @[MixedNode.scala:542:17, :551:17] assign intInClockXingOut_1_sync_1 = intInClockXingIn_1_sync_1; // @[MixedNode.scala:542:17, :551:17] CLINT clint ( // @[CLINT.scala:112:48] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_int_out_1_0 (_clint_auto_int_out_1_0), .auto_int_out_1_1 (_clint_auto_int_out_1_1), .auto_int_out_0_0 (_clint_auto_int_out_0_0), .auto_int_out_0_1 (_clint_auto_int_out_0_1), .auto_in_a_ready (auto_clint_in_a_ready_0), .auto_in_a_valid (auto_clint_in_a_valid_0), // @[ClockDomain.scala:14:9] .auto_in_a_bits_opcode (auto_clint_in_a_bits_opcode_0), // @[ClockDomain.scala:14:9] .auto_in_a_bits_param (auto_clint_in_a_bits_param_0), // @[ClockDomain.scala:14:9] .auto_in_a_bits_size (auto_clint_in_a_bits_size_0), // @[ClockDomain.scala:14:9] .auto_in_a_bits_source (auto_clint_in_a_bits_source_0), // @[ClockDomain.scala:14:9] .auto_in_a_bits_address (auto_clint_in_a_bits_address_0), // @[ClockDomain.scala:14:9] .auto_in_a_bits_mask (auto_clint_in_a_bits_mask_0), // @[ClockDomain.scala:14:9] .auto_in_a_bits_data (auto_clint_in_a_bits_data_0), // @[ClockDomain.scala:14:9] .auto_in_a_bits_corrupt (auto_clint_in_a_bits_corrupt_0), // @[ClockDomain.scala:14:9] .auto_in_d_ready (auto_clint_in_d_ready_0), // @[ClockDomain.scala:14:9] .auto_in_d_valid (auto_clint_in_d_valid_0), .auto_in_d_bits_opcode (auto_clint_in_d_bits_opcode_0), .auto_in_d_bits_size (auto_clint_in_d_bits_size_0), .auto_in_d_bits_source (auto_clint_in_d_bits_source_0), .auto_in_d_bits_data (auto_clint_in_d_bits_data_0), .io_rtcTick (tick) ); // @[CLINT.scala:112:48] IntSyncCrossingSource_n1x2 intsource ( // @[Crossing.scala:29:31] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_0 (_clint_auto_int_out_0_0), // @[CLINT.scala:112:48] .auto_in_1 (_clint_auto_int_out_0_1), // @[CLINT.scala:112:48] .auto_out_sync_0 (intInClockXingIn_sync_0), .auto_out_sync_1 (intInClockXingIn_sync_1) ); // @[Crossing.scala:29:31] IntSyncCrossingSource_n1x2_1 intsource_1 ( // @[Crossing.scala:29:31] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_0 (_clint_auto_int_out_1_0), // @[CLINT.scala:112:48] .auto_in_1 (_clint_auto_int_out_1_1), // @[CLINT.scala:112:48] .auto_out_sync_0 (intInClockXingIn_1_sync_0), .auto_out_sync_1 (intInClockXingIn_1_sync_1) ); // @[Crossing.scala:29:31] assign auto_clint_in_a_ready = auto_clint_in_a_ready_0; // @[ClockDomain.scala:14:9] assign auto_clint_in_d_valid = auto_clint_in_d_valid_0; // @[ClockDomain.scala:14:9] assign auto_clint_in_d_bits_opcode = auto_clint_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_clint_in_d_bits_size = auto_clint_in_d_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_clint_in_d_bits_source = auto_clint_in_d_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_clint_in_d_bits_data = auto_clint_in_d_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_int_in_clock_xing_out_1_sync_0 = auto_int_in_clock_xing_out_1_sync_0_0; // @[ClockDomain.scala:14:9] assign auto_int_in_clock_xing_out_1_sync_1 = auto_int_in_clock_xing_out_1_sync_1_0; // @[ClockDomain.scala:14:9] assign auto_int_in_clock_xing_out_0_sync_0 = auto_int_in_clock_xing_out_0_sync_0_0; // @[ClockDomain.scala:14:9] assign auto_int_in_clock_xing_out_0_sync_1 = auto_int_in_clock_xing_out_0_sync_1_0; // @[ClockDomain.scala:14:9] assign clock = clockNodeIn_clock; // @[ClockDomain.scala:14:9] assign reset = clockNodeIn_reset; // @[ClockDomain.scala:14:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module IssueSlot_8 : input clock : Clock input reset : Reset output io : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, request_hp : UInt<1>, flip grant : UInt<1>, flip brupdate : { b1 : { resolve_mask : UInt<8>, mispredict_mask : UInt<8>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, flip kill : UInt<1>, flip clear : UInt<1>, flip ldspec_miss : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { pdst : UInt<6>, poisoned : UInt<1>}}[3], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<4>}, flip spec_ld_wakeup : { valid : UInt<1>, bits : UInt<6>}[1], flip in_uop : { valid : UInt<1>, bits : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}}, out_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, debug : { p1 : UInt<1>, p2 : UInt<1>, p3 : UInt<1>, ppred : UInt<1>, state : UInt<2>}} wire next_state : UInt wire next_uopc : UInt wire next_lrs1_rtype : UInt wire next_lrs2_rtype : UInt regreset state : UInt<2>, clock, reset, UInt<2>(0h0) regreset p1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset p2 : UInt<1>, clock, reset, UInt<1>(0h0) regreset p3 : UInt<1>, clock, reset, UInt<1>(0h0) regreset ppred : UInt<1>, clock, reset, UInt<1>(0h0) regreset p1_poisoned : UInt<1>, clock, reset, UInt<1>(0h0) regreset p2_poisoned : UInt<1>, clock, reset, UInt<1>(0h0) connect p1_poisoned, UInt<1>(0h0) connect p2_poisoned, UInt<1>(0h0) node next_p1_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned) node next_p2_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned) wire slot_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>} invalidate slot_uop_uop.debug_tsrc invalidate slot_uop_uop.debug_fsrc invalidate slot_uop_uop.bp_xcpt_if invalidate slot_uop_uop.bp_debug_if invalidate slot_uop_uop.xcpt_ma_if invalidate slot_uop_uop.xcpt_ae_if invalidate slot_uop_uop.xcpt_pf_if invalidate slot_uop_uop.fp_single invalidate slot_uop_uop.fp_val invalidate slot_uop_uop.frs3_en invalidate slot_uop_uop.lrs2_rtype invalidate slot_uop_uop.lrs1_rtype invalidate slot_uop_uop.dst_rtype invalidate slot_uop_uop.ldst_val invalidate slot_uop_uop.lrs3 invalidate slot_uop_uop.lrs2 invalidate slot_uop_uop.lrs1 invalidate slot_uop_uop.ldst invalidate slot_uop_uop.ldst_is_rs1 invalidate slot_uop_uop.flush_on_commit invalidate slot_uop_uop.is_unique invalidate slot_uop_uop.is_sys_pc2epc invalidate slot_uop_uop.uses_stq invalidate slot_uop_uop.uses_ldq invalidate slot_uop_uop.is_amo invalidate slot_uop_uop.is_fencei invalidate slot_uop_uop.is_fence invalidate slot_uop_uop.mem_signed invalidate slot_uop_uop.mem_size invalidate slot_uop_uop.mem_cmd invalidate slot_uop_uop.bypassable invalidate slot_uop_uop.exc_cause invalidate slot_uop_uop.exception invalidate slot_uop_uop.stale_pdst invalidate slot_uop_uop.ppred_busy invalidate slot_uop_uop.prs3_busy invalidate slot_uop_uop.prs2_busy invalidate slot_uop_uop.prs1_busy invalidate slot_uop_uop.ppred invalidate slot_uop_uop.prs3 invalidate slot_uop_uop.prs2 invalidate slot_uop_uop.prs1 invalidate slot_uop_uop.pdst invalidate slot_uop_uop.rxq_idx invalidate slot_uop_uop.stq_idx invalidate slot_uop_uop.ldq_idx invalidate slot_uop_uop.rob_idx invalidate slot_uop_uop.csr_addr invalidate slot_uop_uop.imm_packed invalidate slot_uop_uop.taken invalidate slot_uop_uop.pc_lob invalidate slot_uop_uop.edge_inst invalidate slot_uop_uop.ftq_idx invalidate slot_uop_uop.br_tag invalidate slot_uop_uop.br_mask invalidate slot_uop_uop.is_sfb invalidate slot_uop_uop.is_jal invalidate slot_uop_uop.is_jalr invalidate slot_uop_uop.is_br invalidate slot_uop_uop.iw_p2_poisoned invalidate slot_uop_uop.iw_p1_poisoned invalidate slot_uop_uop.iw_state invalidate slot_uop_uop.ctrl.is_std invalidate slot_uop_uop.ctrl.is_sta invalidate slot_uop_uop.ctrl.is_load invalidate slot_uop_uop.ctrl.csr_cmd invalidate slot_uop_uop.ctrl.fcn_dw invalidate slot_uop_uop.ctrl.op_fcn invalidate slot_uop_uop.ctrl.imm_sel invalidate slot_uop_uop.ctrl.op2_sel invalidate slot_uop_uop.ctrl.op1_sel invalidate slot_uop_uop.ctrl.br_type invalidate slot_uop_uop.fu_code invalidate slot_uop_uop.iq_type invalidate slot_uop_uop.debug_pc invalidate slot_uop_uop.is_rvc invalidate slot_uop_uop.debug_inst invalidate slot_uop_uop.inst invalidate slot_uop_uop.uopc connect slot_uop_uop.uopc, UInt<7>(0h0) connect slot_uop_uop.bypassable, UInt<1>(0h0) connect slot_uop_uop.fp_val, UInt<1>(0h0) connect slot_uop_uop.uses_stq, UInt<1>(0h0) connect slot_uop_uop.uses_ldq, UInt<1>(0h0) connect slot_uop_uop.pdst, UInt<1>(0h0) connect slot_uop_uop.dst_rtype, UInt<2>(0h2) wire slot_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>} invalidate slot_uop_cs.is_std invalidate slot_uop_cs.is_sta invalidate slot_uop_cs.is_load invalidate slot_uop_cs.csr_cmd invalidate slot_uop_cs.fcn_dw invalidate slot_uop_cs.op_fcn invalidate slot_uop_cs.imm_sel invalidate slot_uop_cs.op2_sel invalidate slot_uop_cs.op1_sel invalidate slot_uop_cs.br_type connect slot_uop_cs.br_type, UInt<4>(0h0) connect slot_uop_cs.csr_cmd, UInt<3>(0h0) connect slot_uop_cs.is_load, UInt<1>(0h0) connect slot_uop_cs.is_sta, UInt<1>(0h0) connect slot_uop_cs.is_std, UInt<1>(0h0) connect slot_uop_uop.ctrl, slot_uop_cs regreset slot_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, clock, reset, slot_uop_uop node next_uop = mux(io.in_uop.valid, io.in_uop.bits, slot_uop) when io.kill : connect state, UInt<2>(0h0) else : when io.in_uop.valid : connect state, io.in_uop.bits.iw_state else : when io.clear : connect state, UInt<2>(0h0) else : connect state, next_state connect next_state, state connect next_uopc, slot_uop.uopc connect next_lrs1_rtype, slot_uop.lrs1_rtype connect next_lrs2_rtype, slot_uop.lrs2_rtype when io.kill : connect next_state, UInt<2>(0h0) else : node _T = eq(state, UInt<2>(0h1)) node _T_1 = and(io.grant, _T) node _T_2 = eq(state, UInt<2>(0h2)) node _T_3 = and(io.grant, _T_2) node _T_4 = and(_T_3, p1) node _T_5 = and(_T_4, p2) node _T_6 = and(_T_5, ppred) node _T_7 = or(_T_1, _T_6) when _T_7 : node _T_8 = or(p1_poisoned, p2_poisoned) node _T_9 = and(io.ldspec_miss, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) when _T_10 : connect next_state, UInt<2>(0h0) else : node _T_11 = eq(state, UInt<2>(0h2)) node _T_12 = and(io.grant, _T_11) when _T_12 : node _T_13 = or(p1_poisoned, p2_poisoned) node _T_14 = and(io.ldspec_miss, _T_13) node _T_15 = eq(_T_14, UInt<1>(0h0)) when _T_15 : connect next_state, UInt<2>(0h1) when p1 : connect slot_uop.uopc, UInt<7>(0h3) connect next_uopc, UInt<7>(0h3) connect slot_uop.lrs1_rtype, UInt<2>(0h2) connect next_lrs1_rtype, UInt<2>(0h2) else : connect slot_uop.lrs2_rtype, UInt<2>(0h2) connect next_lrs2_rtype, UInt<2>(0h2) when io.in_uop.valid : connect slot_uop, io.in_uop.bits node _T_16 = eq(state, UInt<2>(0h0)) node _T_17 = or(_T_16, io.clear) node _T_18 = or(_T_17, io.kill) node _T_19 = asUInt(reset) node _T_20 = eq(_T_19, UInt<1>(0h0)) when _T_20 : node _T_21 = eq(_T_18, UInt<1>(0h0)) when _T_21 : printf(clock, UInt<1>(0h1), "Assertion failed: trying to overwrite a valid issue slot.\n at issue-slot.scala:156 assert (is_invalid \|\| io.clear \|\| io.kill, \"trying to overwrite a valid issue slot.\")\n") : printf assert(clock, _T_18, UInt<1>(0h1), "") : assert wire next_p1 : UInt<1> connect next_p1, p1 wire next_p2 : UInt<1> connect next_p2, p2 wire next_p3 : UInt<1> connect next_p3, p3 wire next_ppred : UInt<1> connect next_ppred, ppred when io.in_uop.valid : node _p1_T = eq(io.in_uop.bits.prs1_busy, UInt<1>(0h0)) connect p1, _p1_T node _p2_T = eq(io.in_uop.bits.prs2_busy, UInt<1>(0h0)) connect p2, _p2_T node _p3_T = eq(io.in_uop.bits.prs3_busy, UInt<1>(0h0)) connect p3, _p3_T node _ppred_T = eq(io.in_uop.bits.ppred_busy, UInt<1>(0h0)) connect ppred, _ppred_T node _T_22 = and(io.ldspec_miss, next_p1_poisoned) when _T_22 : node _T_23 = neq(next_uop.prs1, UInt<1>(0h0)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs1=x0!\n at issue-slot.scala:176 assert(next_uop.prs1 =/= 0.U, \"Poison bit can't be set for prs1=x0!\")\n") : printf_1 assert(clock, _T_23, UInt<1>(0h1), "") : assert_1 connect p1, UInt<1>(0h0) node _T_27 = and(io.ldspec_miss, next_p2_poisoned) when _T_27 : node _T_28 = neq(next_uop.prs2, UInt<1>(0h0)) node _T_29 = asUInt(reset) node _T_30 = eq(_T_29, UInt<1>(0h0)) when _T_30 : node _T_31 = eq(_T_28, UInt<1>(0h0)) when _T_31 : printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs2=x0!\n at issue-slot.scala:180 assert(next_uop.prs2 =/= 0.U, \"Poison bit can't be set for prs2=x0!\")\n") : printf_2 assert(clock, _T_28, UInt<1>(0h1), "") : assert_2 connect p2, UInt<1>(0h0) node _T_32 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs1) node _T_33 = and(io.wakeup_ports[0].valid, _T_32) when _T_33 : connect p1, UInt<1>(0h1) node _T_34 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs2) node _T_35 = and(io.wakeup_ports[0].valid, _T_34) when _T_35 : connect p2, UInt<1>(0h1) node _T_36 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs3) node _T_37 = and(io.wakeup_ports[0].valid, _T_36) when _T_37 : connect p3, UInt<1>(0h1) node _T_38 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs1) node _T_39 = and(io.wakeup_ports[1].valid, _T_38) when _T_39 : connect p1, UInt<1>(0h1) node _T_40 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs2) node _T_41 = and(io.wakeup_ports[1].valid, _T_40) when _T_41 : connect p2, UInt<1>(0h1) node _T_42 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs3) node _T_43 = and(io.wakeup_ports[1].valid, _T_42) when _T_43 : connect p3, UInt<1>(0h1) node _T_44 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs1) node _T_45 = and(io.wakeup_ports[2].valid, _T_44) when _T_45 : connect p1, UInt<1>(0h1) node _T_46 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs2) node _T_47 = and(io.wakeup_ports[2].valid, _T_46) when _T_47 : connect p2, UInt<1>(0h1) node _T_48 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs3) node _T_49 = and(io.wakeup_ports[2].valid, _T_48) when _T_49 : connect p3, UInt<1>(0h1) node _T_50 = eq(io.pred_wakeup_port.bits, next_uop.ppred) node _T_51 = and(io.pred_wakeup_port.valid, _T_50) when _T_51 : connect ppred, UInt<1>(0h1) node _T_52 = eq(io.spec_ld_wakeup[0].bits, UInt<1>(0h0)) node _T_53 = and(io.spec_ld_wakeup[0].valid, _T_52) node _T_54 = eq(_T_53, UInt<1>(0h0)) node _T_55 = asUInt(reset) node _T_56 = eq(_T_55, UInt<1>(0h0)) when _T_56 : node _T_57 = eq(_T_54, UInt<1>(0h0)) when _T_57 : printf(clock, UInt<1>(0h1), "Assertion failed: Loads to x0 should never speculatively wakeup other instructions\n at issue-slot.scala:203 assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U),\n") : printf_3 assert(clock, _T_54, UInt<1>(0h1), "") : assert_3 node _T_58 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs1) node _T_59 = and(io.spec_ld_wakeup[0].valid, _T_58) node _T_60 = eq(next_uop.lrs1_rtype, UInt<2>(0h0)) node _T_61 = and(_T_59, _T_60) when _T_61 : connect p1, UInt<1>(0h1) connect p1_poisoned, UInt<1>(0h1) node _T_62 = eq(next_p1_poisoned, UInt<1>(0h0)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:214 assert (!next_p1_poisoned)\n") : printf_4 assert(clock, _T_62, UInt<1>(0h1), "") : assert_4 node _T_66 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs2) node _T_67 = and(io.spec_ld_wakeup[0].valid, _T_66) node _T_68 = eq(next_uop.lrs2_rtype, UInt<2>(0h0)) node _T_69 = and(_T_67, _T_68) when _T_69 : connect p2, UInt<1>(0h1) connect p2_poisoned, UInt<1>(0h1) node _T_70 = eq(next_p2_poisoned, UInt<1>(0h0)) node _T_71 = asUInt(reset) node _T_72 = eq(_T_71, UInt<1>(0h0)) when _T_72 : node _T_73 = eq(_T_70, UInt<1>(0h0)) when _T_73 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:221 assert (!next_p2_poisoned)\n") : printf_5 assert(clock, _T_70, UInt<1>(0h1), "") : assert_5 node _next_br_mask_T = not(io.brupdate.b1.resolve_mask) node next_br_mask = and(slot_uop.br_mask, _next_br_mask_T) node _T_74 = and(io.brupdate.b1.mispredict_mask, slot_uop.br_mask) node _T_75 = neq(_T_74, UInt<1>(0h0)) when _T_75 : connect next_state, UInt<2>(0h0) node _T_76 = eq(io.in_uop.valid, UInt<1>(0h0)) when _T_76 : connect slot_uop.br_mask, next_br_mask node _io_request_T = neq(state, UInt<2>(0h0)) node _io_request_T_1 = and(_io_request_T, p1) node _io_request_T_2 = and(_io_request_T_1, p2) node _io_request_T_3 = and(_io_request_T_2, p3) node _io_request_T_4 = and(_io_request_T_3, ppred) node _io_request_T_5 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_6 = and(_io_request_T_4, _io_request_T_5) connect io.request, _io_request_T_6 node _high_priority_T = or(slot_uop.is_br, slot_uop.is_jal) node high_priority = or(_high_priority_T, slot_uop.is_jalr) node _io_request_hp_T = and(io.request, high_priority) connect io.request_hp, _io_request_hp_T node _T_77 = eq(state, UInt<2>(0h1)) when _T_77 : node _io_request_T_7 = and(p1, p2) node _io_request_T_8 = and(_io_request_T_7, p3) node _io_request_T_9 = and(_io_request_T_8, ppred) node _io_request_T_10 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_11 = and(_io_request_T_9, _io_request_T_10) connect io.request, _io_request_T_11 else : node _T_78 = eq(state, UInt<2>(0h2)) when _T_78 : node _io_request_T_12 = or(p1, p2) node _io_request_T_13 = and(_io_request_T_12, ppred) node _io_request_T_14 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_15 = and(_io_request_T_13, _io_request_T_14) connect io.request, _io_request_T_15 else : connect io.request, UInt<1>(0h0) node _io_valid_T = neq(state, UInt<2>(0h0)) connect io.valid, _io_valid_T connect io.uop, slot_uop connect io.uop.iw_p1_poisoned, p1_poisoned connect io.uop.iw_p2_poisoned, p2_poisoned node _may_vacate_T = eq(state, UInt<2>(0h1)) node _may_vacate_T_1 = eq(state, UInt<2>(0h2)) node _may_vacate_T_2 = and(_may_vacate_T_1, p1) node _may_vacate_T_3 = and(_may_vacate_T_2, p2) node _may_vacate_T_4 = and(_may_vacate_T_3, ppred) node _may_vacate_T_5 = or(_may_vacate_T, _may_vacate_T_4) node may_vacate = and(io.grant, _may_vacate_T_5) node _squash_grant_T = or(p1_poisoned, p2_poisoned) node squash_grant = and(io.ldspec_miss, _squash_grant_T) node _io_will_be_valid_T = neq(state, UInt<2>(0h0)) node _io_will_be_valid_T_1 = eq(squash_grant, UInt<1>(0h0)) node _io_will_be_valid_T_2 = and(may_vacate, _io_will_be_valid_T_1) node _io_will_be_valid_T_3 = eq(_io_will_be_valid_T_2, UInt<1>(0h0)) node _io_will_be_valid_T_4 = and(_io_will_be_valid_T, _io_will_be_valid_T_3) connect io.will_be_valid, _io_will_be_valid_T_4 connect io.out_uop, slot_uop connect io.out_uop.iw_state, next_state connect io.out_uop.uopc, next_uopc connect io.out_uop.lrs1_rtype, next_lrs1_rtype connect io.out_uop.lrs2_rtype, next_lrs2_rtype connect io.out_uop.br_mask, next_br_mask node _io_out_uop_prs1_busy_T = eq(p1, UInt<1>(0h0)) connect io.out_uop.prs1_busy, _io_out_uop_prs1_busy_T node _io_out_uop_prs2_busy_T = eq(p2, UInt<1>(0h0)) connect io.out_uop.prs2_busy, _io_out_uop_prs2_busy_T node _io_out_uop_prs3_busy_T = eq(p3, UInt<1>(0h0)) connect io.out_uop.prs3_busy, _io_out_uop_prs3_busy_T node _io_out_uop_ppred_busy_T = eq(ppred, UInt<1>(0h0)) connect io.out_uop.ppred_busy, _io_out_uop_ppred_busy_T connect io.out_uop.iw_p1_poisoned, p1_poisoned connect io.out_uop.iw_p2_poisoned, p2_poisoned node _T_79 = eq(state, UInt<2>(0h2)) when _T_79 : node _T_80 = and(p1, p2) node _T_81 = and(_T_80, ppred) when _T_81 : skip else : node _T_82 = and(p1, ppred) when _T_82 : connect io.uop.uopc, slot_uop.uopc connect io.uop.lrs2_rtype, UInt<2>(0h2) else : node _T_83 = and(p2, ppred) when _T_83 : connect io.uop.uopc, UInt<7>(0h3) connect io.uop.lrs1_rtype, UInt<2>(0h2) connect io.debug.p1, p1 connect io.debug.p2, p2 connect io.debug.p3, p3 connect io.debug.ppred, ppred connect io.debug.state, state	module IssueSlot_8( // @[issue-slot.scala:69:7] input clock, // @[issue-slot.scala:69:7] input reset, // @[issue-slot.scala:69:7] output io_valid, // @[issue-slot.scala:73:14] output io_will_be_valid, // @[issue-slot.scala:73:14] output io_request, // @[issue-slot.scala:73:14] output io_request_hp, // @[issue-slot.scala:73:14] input io_grant, // @[issue-slot.scala:73:14] input [7:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14] input [7:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14] input [7:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14] input io_brupdate_b2_valid, // @[issue-slot.scala:73:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14] input io_brupdate_b2_taken, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14] input io_kill, // @[issue-slot.scala:73:14] input io_ldspec_miss, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14] input [5:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14] input [5:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_2_valid, // @[issue-slot.scala:73:14] input [5:0] io_wakeup_ports_2_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_2_bits_poisoned, // @[issue-slot.scala:73:14] input io_spec_ld_wakeup_0_valid, // @[issue-slot.scala:73:14] input [5:0] io_spec_ld_wakeup_0_bits, // @[issue-slot.scala:73:14] input io_in_uop_valid, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14] input io_in_uop_bits_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_in_uop_bits_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14] input [7:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14] input io_in_uop_bits_taken, // @[issue-slot.scala:73:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ppred, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14] input io_in_uop_bits_exception, // @[issue-slot.scala:73:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14] input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14] output io_out_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14] output io_out_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] output io_out_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] output io_out_uop_is_br, // @[issue-slot.scala:73:14] output io_out_uop_is_jalr, // @[issue-slot.scala:73:14] output io_out_uop_is_jal, // @[issue-slot.scala:73:14] output io_out_uop_is_sfb, // @[issue-slot.scala:73:14] output [7:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_out_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14] output io_out_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_pdst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_prs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_prs2, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_prs3, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ppred, // @[issue-slot.scala:73:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_out_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14] output io_out_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14] output io_out_uop_mem_signed, // @[issue-slot.scala:73:14] output io_out_uop_is_fence, // @[issue-slot.scala:73:14] output io_out_uop_is_fencei, // @[issue-slot.scala:73:14] output io_out_uop_is_amo, // @[issue-slot.scala:73:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_out_uop_uses_stq, // @[issue-slot.scala:73:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_out_uop_is_unique, // @[issue-slot.scala:73:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14] output io_out_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_out_uop_frs3_en, // @[issue-slot.scala:73:14] output io_out_uop_fp_val, // @[issue-slot.scala:73:14] output io_out_uop_fp_single, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14] output io_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14] output io_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] output io_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] output io_uop_is_br, // @[issue-slot.scala:73:14] output io_uop_is_jalr, // @[issue-slot.scala:73:14] output io_uop_is_jal, // @[issue-slot.scala:73:14] output io_uop_is_sfb, // @[issue-slot.scala:73:14] output [7:0] io_uop_br_mask, // @[issue-slot.scala:73:14] output [2:0] io_uop_br_tag, // @[issue-slot.scala:73:14] output [3:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14] output io_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14] output [4:0] io_uop_rob_idx, // @[issue-slot.scala:73:14] output [2:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14] output [2:0] io_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14] output [5:0] io_uop_pdst, // @[issue-slot.scala:73:14] output [5:0] io_uop_prs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_prs2, // @[issue-slot.scala:73:14] output [5:0] io_uop_prs3, // @[issue-slot.scala:73:14] output [3:0] io_uop_ppred, // @[issue-slot.scala:73:14] output io_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_uop_ppred_busy, // @[issue-slot.scala:73:14] output [5:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14] output io_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14] output io_uop_mem_signed, // @[issue-slot.scala:73:14] output io_uop_is_fence, // @[issue-slot.scala:73:14] output io_uop_is_fencei, // @[issue-slot.scala:73:14] output io_uop_is_amo, // @[issue-slot.scala:73:14] output io_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_uop_uses_stq, // @[issue-slot.scala:73:14] output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_uop_is_unique, // @[issue-slot.scala:73:14] output io_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14] output io_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_uop_frs3_en, // @[issue-slot.scala:73:14] output io_uop_fp_val, // @[issue-slot.scala:73:14] output io_uop_fp_single, // @[issue-slot.scala:73:14] output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14] output io_debug_p1, // @[issue-slot.scala:73:14] output io_debug_p2, // @[issue-slot.scala:73:14] output io_debug_p3, // @[issue-slot.scala:73:14] output io_debug_ppred, // @[issue-slot.scala:73:14] output [1:0] io_debug_state // @[issue-slot.scala:73:14] ); wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7] wire [7:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7] wire [7:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7] wire [7:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7] wire io_ldspec_miss_0 = io_ldspec_miss; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7] wire [5:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_bits_poisoned_0 = io_wakeup_ports_0_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7] wire [5:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_bits_poisoned_0 = io_wakeup_ports_1_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:69:7] wire [5:0] io_wakeup_ports_2_bits_pdst_0 = io_wakeup_ports_2_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_2_bits_poisoned_0 = io_wakeup_ports_2_bits_poisoned; // @[issue-slot.scala:69:7] wire io_spec_ld_wakeup_0_valid_0 = io_spec_ld_wakeup_0_valid; // @[issue-slot.scala:69:7] wire [5:0] io_spec_ld_wakeup_0_bits_0 = io_spec_ld_wakeup_0_bits; // @[issue-slot.scala:69:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p1_poisoned_0 = io_in_uop_bits_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p2_poisoned_0 = io_in_uop_bits_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7] wire [7:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7] wire io_clear = 1'h0; // @[issue-slot.scala:69:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7] wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire [3:0] io_pred_wakeup_port_bits = 4'h0; // @[issue-slot.scala:69:7] wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_uop_ftq_idx = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_uop_ppred = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_br_tag = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ldq_idx = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_stq_idx = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_rob_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_pdst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_prs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_prs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_prs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_stale_pdst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [7:0] slot_uop_uop_br_mask = 8'h0; // @[consts.scala:269:19] wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire _io_valid_T; // @[issue-slot.scala:79:24] wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32] wire _io_request_hp_T; // @[issue-slot.scala:243:31] wire [6:0] next_uopc; // @[issue-slot.scala:82:29] wire [1:0] next_state; // @[issue-slot.scala:81:29] wire [7:0] next_br_mask; // @[util.scala:85:25] wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28] wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28] wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28] wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28] wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29] wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29] wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [7:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [3:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_out_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7] wire [3:0] io_out_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_out_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7] wire io_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7] wire io_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [7:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_pdst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_prs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_prs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_prs3_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire io_debug_p1_0; // @[issue-slot.scala:69:7] wire io_debug_p2_0; // @[issue-slot.scala:69:7] wire io_debug_p3_0; // @[issue-slot.scala:69:7] wire io_debug_ppred_0; // @[issue-slot.scala:69:7] wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7] wire io_valid_0; // @[issue-slot.scala:69:7] wire io_will_be_valid_0; // @[issue-slot.scala:69:7] wire io_request_0; // @[issue-slot.scala:69:7] wire io_request_hp_0; // @[issue-slot.scala:69:7] assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29] assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29] assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29] assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29] reg [1:0] state; // @[issue-slot.scala:86:22] assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22] reg p1; // @[issue-slot.scala:87:22] assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22] wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25] reg p2; // @[issue-slot.scala:88:22] assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22] wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25] reg p3; // @[issue-slot.scala:89:22] assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22] wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25] reg ppred; // @[issue-slot.scala:90:22] assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22] wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28] reg p1_poisoned; // @[issue-slot.scala:95:28] assign io_out_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28] assign io_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28] reg p2_poisoned; // @[issue-slot.scala:96:28] assign io_out_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28] assign io_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28] wire next_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : p1_poisoned; // @[issue-slot.scala:69:7, :95:28, :99:29] wire next_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : p2_poisoned; // @[issue-slot.scala:69:7, :96:28, :100:29] reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25] reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25] assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25] assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_rvc; // @[issue-slot.scala:102:25] assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25] assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25] assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25] assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_iw_p1_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_iw_p2_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_is_br; // @[issue-slot.scala:102:25] assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jalr; // @[issue-slot.scala:102:25] assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jal; // @[issue-slot.scala:102:25] assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sfb; // @[issue-slot.scala:102:25] assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] reg [7:0] slot_uop_br_mask; // @[issue-slot.scala:102:25] assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_br_tag; // @[issue-slot.scala:102:25] assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_edge_inst; // @[issue-slot.scala:102:25] assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25] assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_taken; // @[issue-slot.scala:102:25] assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25] assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25] assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_prs1; // @[issue-slot.scala:102:25] assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_prs2; // @[issue-slot.scala:102:25] assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_prs3; // @[issue-slot.scala:102:25] assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ppred; // @[issue-slot.scala:102:25] assign io_out_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25] assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25] assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs3_busy; // @[issue-slot.scala:102:25] assign io_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ppred_busy; // @[issue-slot.scala:102:25] assign io_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_exception; // @[issue-slot.scala:102:25] assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25] assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bypassable; // @[issue-slot.scala:102:25] assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25] assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_mem_signed; // @[issue-slot.scala:102:25] assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fence; // @[issue-slot.scala:102:25] assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fencei; // @[issue-slot.scala:102:25] assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_amo; // @[issue-slot.scala:102:25] assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_stq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25] assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_unique; // @[issue-slot.scala:102:25] assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25] assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25] assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25] assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25] assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_val; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25] assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25] reg slot_uop_frs3_en; // @[issue-slot.scala:102:25] assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_val; // @[issue-slot.scala:102:25] assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_single; // @[issue-slot.scala:102:25] assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : slot_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : slot_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [7:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ppred = io_in_uop_valid_0 ? io_in_uop_bits_ppred_0 : slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs3_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs3_busy_0 : slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ppred_busy = io_in_uop_valid_0 ? io_in_uop_bits_ppred_busy_0 : slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25] wire _T_7 = io_grant_0 & state == 2'h1 \| io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}] wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25] wire _T_14 = io_ldspec_miss_0 & (p1_poisoned \| p2_poisoned); // @[issue-slot.scala:69:7, :95:28, :96:28, :140:{28,44}] wire _GEN = _T_12 & ~_T_14; // @[issue-slot.scala:126:14, :139:{25,51}, :140:{11,28,62}, :141:18] wire _GEN_0 = io_kill_0 \| _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51] wire _GEN_1 = _GEN_0 \| ~(_T_12 & ~_T_14 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:{11,28,62}, :142:17, :143:23] assign next_uopc = _GEN_1 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51] assign next_lrs1_rtype = _GEN_1 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51] wire _GEN_2 = _GEN_0 \| ~_GEN \| p1; // @[issue-slot.scala:87:22, :102:25, :126:14, :131:18, :134:63, :139:51, :140:62, :141:18, :142:17] assign next_lrs2_rtype = _GEN_2 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17] wire _p1_T = ~io_in_uop_bits_prs1_busy_0; // @[issue-slot.scala:69:7, :169:11] wire _p2_T = ~io_in_uop_bits_prs2_busy_0; // @[issue-slot.scala:69:7, :170:11] wire _p3_T = ~io_in_uop_bits_prs3_busy_0; // @[issue-slot.scala:69:7, :171:11] wire _ppred_T = ~io_in_uop_bits_ppred_busy_0; // @[issue-slot.scala:69:7, :172:14] wire _T_22 = io_ldspec_miss_0 & next_p1_poisoned; // @[issue-slot.scala:69:7, :99:29, :175:24] wire _T_27 = io_ldspec_miss_0 & next_p2_poisoned; // @[issue-slot.scala:69:7, :100:29, :179:24] wire _T_61 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs1 & next_uop_lrs1_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :209:38, :210:{33,51}, :211:27] wire _T_69 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs2 & next_uop_lrs2_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :216:38, :217:{33,51}, :218:27]
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_48 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<8>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 7, 0) node _source_ok_T = shr(io.in.a.bits.source, 8) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<8>(0hf3)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<8>(0h0)) node uncommonBits = bits(_uncommonBits_T, 7, 0) node _T_4 = shr(io.in.a.bits.source, 8) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<8>(0hf3)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<8>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 7, 0) node _T_24 = shr(io.in.a.bits.source, 8) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<8>(0hf3)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<17>(0h10000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<8>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 7, 0) node _T_86 = shr(io.in.a.bits.source, 8) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<8>(0hf3)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<17>(0h10000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<17>(0h10000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<8>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 7, 0) node _T_152 = shr(io.in.a.bits.source, 8) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<8>(0hf3)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<17>(0h10000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<8>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 7, 0) node _T_199 = shr(io.in.a.bits.source, 8) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<8>(0hf3)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_208 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_209 = and(_T_207, _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<17>(0h10000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = and(_T_210, _T_215) node _T_217 = or(UInt<1>(0h0), _T_216) node _T_218 = and(_T_206, _T_217) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_218, UInt<1>(0h1), "") : assert_26 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(is_aligned, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_228, UInt<1>(0h1), "") : assert_29 node _T_232 = eq(io.in.a.bits.mask, mask) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_236 : node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_239 = and(_T_237, _T_238) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<8>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 7, 0) node _T_240 = shr(io.in.a.bits.source, 8) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = leq(UInt<1>(0h0), uncommonBits_5) node _T_243 = and(_T_241, _T_242) node _T_244 = leq(uncommonBits_5, UInt<8>(0hf3)) node _T_245 = and(_T_243, _T_244) node _T_246 = and(_T_239, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_253 = cvt(_T_252) node _T_254 = and(_T_253, asSInt(UInt<17>(0h10000))) node _T_255 = asSInt(_T_254) node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) node _T_257 = and(_T_251, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = and(_T_247, _T_258) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_259, UInt<1>(0h1), "") : assert_31 node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(is_aligned, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_269, UInt<1>(0h1), "") : assert_34 node _T_273 = not(mask) node _T_274 = and(io.in.a.bits.mask, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_275, UInt<1>(0h1), "") : assert_35 node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_279 : node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_282 = and(_T_280, _T_281) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<8>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 7, 0) node _T_283 = shr(io.in.a.bits.source, 8) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = leq(UInt<1>(0h0), uncommonBits_6) node _T_286 = and(_T_284, _T_285) node _T_287 = leq(uncommonBits_6, UInt<8>(0hf3)) node _T_288 = and(_T_286, _T_287) node _T_289 = and(_T_282, _T_288) node _T_290 = or(UInt<1>(0h0), _T_289) node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_292 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<17>(0h10000))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = and(_T_291, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = and(_T_290, _T_298) node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_T_299, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_299, UInt<1>(0h1), "") : assert_36 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(is_aligned, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_309, UInt<1>(0h1), "") : assert_39 node _T_313 = eq(io.in.a.bits.mask, mask) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_313, UInt<1>(0h1), "") : assert_40 node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_317 : node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<8>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 7, 0) node _T_321 = shr(io.in.a.bits.source, 8) node _T_322 = eq(_T_321, UInt<1>(0h0)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_7) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_7, UInt<8>(0hf3)) node _T_326 = and(_T_324, _T_325) node _T_327 = and(_T_320, _T_326) node _T_328 = or(UInt<1>(0h0), _T_327) node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<17>(0h10000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = and(_T_329, _T_334) node _T_336 = or(UInt<1>(0h0), _T_335) node _T_337 = and(_T_328, _T_336) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_337, UInt<1>(0h1), "") : assert_41 node _T_341 = asUInt(reset) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(is_aligned, UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_347, UInt<1>(0h1), "") : assert_44 node _T_351 = eq(io.in.a.bits.mask, mask) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_351, UInt<1>(0h1), "") : assert_45 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<8>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 7, 0) node _T_359 = shr(io.in.a.bits.source, 8) node _T_360 = eq(_T_359, UInt<1>(0h0)) node _T_361 = leq(UInt<1>(0h0), uncommonBits_8) node _T_362 = and(_T_360, _T_361) node _T_363 = leq(uncommonBits_8, UInt<8>(0hf3)) node _T_364 = and(_T_362, _T_363) node _T_365 = and(_T_358, _T_364) node _T_366 = or(UInt<1>(0h0), _T_365) node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_369 = cvt(_T_368) node _T_370 = and(_T_369, asSInt(UInt<17>(0h10000))) node _T_371 = asSInt(_T_370) node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0))) node _T_373 = and(_T_367, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = and(_T_366, _T_374) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_375, UInt<1>(0h1), "") : assert_46 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(is_aligned, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_385, UInt<1>(0h1), "") : assert_49 node _T_389 = eq(io.in.a.bits.mask, mask) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_389, UInt<1>(0h1), "") : assert_50 node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_393, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_397, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<8>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 7, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 8) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<8>(0hf3)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_401 : node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_405, UInt<1>(0h1), "") : assert_54 node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_409, UInt<1>(0h1), "") : assert_55 node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_413, UInt<1>(0h1), "") : assert_56 node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(_T_417, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_417, UInt<1>(0h1), "") : assert_57 node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_421 : node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(sink_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_428, UInt<1>(0h1), "") : assert_60 node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_432, UInt<1>(0h1), "") : assert_61 node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_436, UInt<1>(0h1), "") : assert_62 node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(_T_440, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_440, UInt<1>(0h1), "") : assert_63 node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_445 = or(UInt<1>(0h0), _T_444) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_445, UInt<1>(0h1), "") : assert_64 node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_449 : node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(sink_ok, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_457 = asUInt(reset) node _T_458 = eq(_T_457, UInt<1>(0h0)) when _T_458 : node _T_459 = eq(_T_456, UInt<1>(0h0)) when _T_459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_456, UInt<1>(0h1), "") : assert_67 node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_T_460, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_460, UInt<1>(0h1), "") : assert_68 node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_464, UInt<1>(0h1), "") : assert_69 node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_469 = or(_T_468, io.in.d.bits.corrupt) node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_T_469, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_469, UInt<1>(0h1), "") : assert_70 node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_474 = or(UInt<1>(0h0), _T_473) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_474, UInt<1>(0h1), "") : assert_71 node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_478 : node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_482, UInt<1>(0h1), "") : assert_73 node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_486, UInt<1>(0h1), "") : assert_74 node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_491, UInt<1>(0h1), "") : assert_75 node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_495 : node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_499, UInt<1>(0h1), "") : assert_77 node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_504 = or(_T_503, io.in.d.bits.corrupt) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_504, UInt<1>(0h1), "") : assert_78 node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_509, UInt<1>(0h1), "") : assert_79 node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_513 : node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_517, UInt<1>(0h1), "") : assert_81 node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_521, UInt<1>(0h1), "") : assert_82 node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_526 = or(UInt<1>(0h0), _T_525) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_526, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<28>(0h0) connect _WIRE.bits.source, UInt<8>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_530, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<28>(0h0) connect _WIRE_2.bits.source, UInt<8>(0h0) connect _WIRE_2.bits.size, UInt<3>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_534, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_538, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_542 = eq(a_first, UInt<1>(0h0)) node _T_543 = and(io.in.a.valid, _T_542) when _T_543 : node _T_544 = eq(io.in.a.bits.opcode, opcode) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_544, UInt<1>(0h1), "") : assert_87 node _T_548 = eq(io.in.a.bits.param, param) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_548, UInt<1>(0h1), "") : assert_88 node _T_552 = eq(io.in.a.bits.size, size) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_552, UInt<1>(0h1), "") : assert_89 node _T_556 = eq(io.in.a.bits.source, source) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_556, UInt<1>(0h1), "") : assert_90 node _T_560 = eq(io.in.a.bits.address, address) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_560, UInt<1>(0h1), "") : assert_91 node _T_564 = and(io.in.a.ready, io.in.a.valid) node _T_565 = and(_T_564, a_first) when _T_565 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_566 = eq(d_first, UInt<1>(0h0)) node _T_567 = and(io.in.d.valid, _T_566) when _T_567 : node _T_568 = eq(io.in.d.bits.opcode, opcode_1) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_568, UInt<1>(0h1), "") : assert_92 node _T_572 = eq(io.in.d.bits.param, param_1) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_572, UInt<1>(0h1), "") : assert_93 node _T_576 = eq(io.in.d.bits.size, size_1) node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(_T_576, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_576, UInt<1>(0h1), "") : assert_94 node _T_580 = eq(io.in.d.bits.source, source_1) node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(_T_580, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_580, UInt<1>(0h1), "") : assert_95 node _T_584 = eq(io.in.d.bits.sink, sink) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_584, UInt<1>(0h1), "") : assert_96 node _T_588 = eq(io.in.d.bits.denied, denied) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_588, UInt<1>(0h1), "") : assert_97 node _T_592 = and(io.in.d.ready, io.in.d.valid) node _T_593 = and(_T_592, d_first) when _T_593 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<244>, clock, reset, UInt<244>(0h0) regreset inflight_opcodes : UInt<976>, clock, reset, UInt<976>(0h0) regreset inflight_sizes : UInt<976>, clock, reset, UInt<976>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<244> connect a_set, UInt<244>(0h0) wire a_set_wo_ready : UInt<244> connect a_set_wo_ready, UInt<244>(0h0) wire a_opcodes_set : UInt<976> connect a_opcodes_set, UInt<976>(0h0) wire a_sizes_set : UInt<976> connect a_sizes_set, UInt<976>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_594 = and(io.in.a.valid, a_first_1) node _T_595 = and(_T_594, UInt<1>(0h1)) when _T_595 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_596 = and(io.in.a.ready, io.in.a.valid) node _T_597 = and(_T_596, a_first_1) node _T_598 = and(_T_597, UInt<1>(0h1)) when _T_598 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_599 = dshr(inflight, io.in.a.bits.source) node _T_600 = bits(_T_599, 0, 0) node _T_601 = eq(_T_600, UInt<1>(0h0)) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_601, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<244> connect d_clr, UInt<244>(0h0) wire d_clr_wo_ready : UInt<244> connect d_clr_wo_ready, UInt<244>(0h0) wire d_opcodes_clr : UInt<976> connect d_opcodes_clr, UInt<976>(0h0) wire d_sizes_clr : UInt<976> connect d_sizes_clr, UInt<976>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_605 = and(io.in.d.valid, d_first_1) node _T_606 = and(_T_605, UInt<1>(0h1)) node _T_607 = eq(d_release_ack, UInt<1>(0h0)) node _T_608 = and(_T_606, _T_607) when _T_608 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_609 = and(io.in.d.ready, io.in.d.valid) node _T_610 = and(_T_609, d_first_1) node _T_611 = and(_T_610, UInt<1>(0h1)) node _T_612 = eq(d_release_ack, UInt<1>(0h0)) node _T_613 = and(_T_611, _T_612) when _T_613 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_614 = and(io.in.d.valid, d_first_1) node _T_615 = and(_T_614, UInt<1>(0h1)) node _T_616 = eq(d_release_ack, UInt<1>(0h0)) node _T_617 = and(_T_615, _T_616) when _T_617 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_618 = dshr(inflight, io.in.d.bits.source) node _T_619 = bits(_T_618, 0, 0) node _T_620 = or(_T_619, same_cycle_resp) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_620, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_626 = or(_T_624, _T_625) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_626, UInt<1>(0h1), "") : assert_100 node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_630, UInt<1>(0h1), "") : assert_101 else : node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_636 = or(_T_634, _T_635) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_636, UInt<1>(0h1), "") : assert_102 node _T_640 = eq(io.in.d.bits.size, a_size_lookup) node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(_T_640, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_640, UInt<1>(0h1), "") : assert_103 node _T_644 = and(io.in.d.valid, d_first_1) node _T_645 = and(_T_644, a_first_1) node _T_646 = and(_T_645, io.in.a.valid) node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_648 = and(_T_646, _T_647) node _T_649 = eq(d_release_ack, UInt<1>(0h0)) node _T_650 = and(_T_648, _T_649) when _T_650 : node _T_651 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_652 = or(_T_651, io.in.a.ready) node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(_T_652, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_652, UInt<1>(0h1), "") : assert_104 node _T_656 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_657 = orr(a_set_wo_ready) node _T_658 = eq(_T_657, UInt<1>(0h0)) node _T_659 = or(_T_656, _T_658) node _T_660 = asUInt(reset) node _T_661 = eq(_T_660, UInt<1>(0h0)) when _T_661 : node _T_662 = eq(_T_659, UInt<1>(0h0)) when _T_662 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_659, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_96 node _T_663 = orr(inflight) node _T_664 = eq(_T_663, UInt<1>(0h0)) node _T_665 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_666 = or(_T_664, _T_665) node _T_667 = lt(watchdog, plusarg_reader.out) node _T_668 = or(_T_666, _T_667) node _T_669 = asUInt(reset) node _T_670 = eq(_T_669, UInt<1>(0h0)) when _T_670 : node _T_671 = eq(_T_668, UInt<1>(0h0)) when _T_671 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_668, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_672 = and(io.in.a.ready, io.in.a.valid) node _T_673 = and(io.in.d.ready, io.in.d.valid) node _T_674 = or(_T_672, _T_673) when _T_674 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<244>, clock, reset, UInt<244>(0h0) regreset inflight_opcodes_1 : UInt<976>, clock, reset, UInt<976>(0h0) regreset inflight_sizes_1 : UInt<976>, clock, reset, UInt<976>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<28>(0h0) connect _c_first_WIRE.bits.source, UInt<8>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<28>(0h0) connect _c_first_WIRE_2.bits.source, UInt<8>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<244> connect c_set, UInt<244>(0h0) wire c_set_wo_ready : UInt<244> connect c_set_wo_ready, UInt<244>(0h0) wire c_opcodes_set : UInt<976> connect c_opcodes_set, UInt<976>(0h0) wire c_sizes_set : UInt<976> connect c_sizes_set, UInt<976>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<28>(0h0) connect _WIRE_6.bits.source, UInt<8>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_675 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<28>(0h0) connect _WIRE_8.bits.source, UInt<8>(0h0) connect _WIRE_8.bits.size, UInt<3>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_676 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_677 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_678 = and(_T_676, _T_677) node _T_679 = and(_T_675, _T_678) when _T_679 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<28>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<8>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<28>(0h0) connect _WIRE_10.bits.source, UInt<8>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_680 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_681 = and(_T_680, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<28>(0h0) connect _WIRE_12.bits.source, UInt<8>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_682 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_683 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_684 = and(_T_682, _T_683) node _T_685 = and(_T_681, _T_684) when _T_685 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<28>(0h0) connect _c_set_WIRE.bits.source, UInt<8>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<28>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<8>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<28>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<8>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<28>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<8>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<28>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<8>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<28>(0h0) connect _WIRE_14.bits.source, UInt<8>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_686 = dshr(inflight_1, _WIRE_15.bits.source) node _T_687 = bits(_T_686, 0, 0) node _T_688 = eq(_T_687, UInt<1>(0h0)) node _T_689 = asUInt(reset) node _T_690 = eq(_T_689, UInt<1>(0h0)) when _T_690 : node _T_691 = eq(_T_688, UInt<1>(0h0)) when _T_691 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_688, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<28>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<8>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<28>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<8>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<244> connect d_clr_1, UInt<244>(0h0) wire d_clr_wo_ready_1 : UInt<244> connect d_clr_wo_ready_1, UInt<244>(0h0) wire d_opcodes_clr_1 : UInt<976> connect d_opcodes_clr_1, UInt<976>(0h0) wire d_sizes_clr_1 : UInt<976> connect d_sizes_clr_1, UInt<976>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_692 = and(io.in.d.valid, d_first_2) node _T_693 = and(_T_692, UInt<1>(0h1)) node _T_694 = and(_T_693, d_release_ack_1) when _T_694 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_695 = and(io.in.d.ready, io.in.d.valid) node _T_696 = and(_T_695, d_first_2) node _T_697 = and(_T_696, UInt<1>(0h1)) node _T_698 = and(_T_697, d_release_ack_1) when _T_698 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_699 = and(io.in.d.valid, d_first_2) node _T_700 = and(_T_699, UInt<1>(0h1)) node _T_701 = and(_T_700, d_release_ack_1) when _T_701 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_702 = dshr(inflight_1, io.in.d.bits.source) node _T_703 = bits(_T_702, 0, 0) node _T_704 = or(_T_703, same_cycle_resp_1) node _T_705 = asUInt(reset) node _T_706 = eq(_T_705, UInt<1>(0h0)) when _T_706 : node _T_707 = eq(_T_704, UInt<1>(0h0)) when _T_707 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_704, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<28>(0h0) connect _WIRE_16.bits.source, UInt<8>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_708 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_709 = asUInt(reset) node _T_710 = eq(_T_709, UInt<1>(0h0)) when _T_710 : node _T_711 = eq(_T_708, UInt<1>(0h0)) when _T_711 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_708, UInt<1>(0h1), "") : assert_109 else : node _T_712 = eq(io.in.d.bits.size, c_size_lookup) node _T_713 = asUInt(reset) node _T_714 = eq(_T_713, UInt<1>(0h0)) when _T_714 : node _T_715 = eq(_T_712, UInt<1>(0h0)) when _T_715 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_712, UInt<1>(0h1), "") : assert_110 node _T_716 = and(io.in.d.valid, d_first_2) node _T_717 = and(_T_716, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<28>(0h0) connect _WIRE_18.bits.source, UInt<8>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_718 = and(_T_717, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<28>(0h0) connect _WIRE_20.bits.source, UInt<8>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_719 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_720 = and(_T_718, _T_719) node _T_721 = and(_T_720, d_release_ack_1) node _T_722 = eq(c_probe_ack, UInt<1>(0h0)) node _T_723 = and(_T_721, _T_722) when _T_723 : node _T_724 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<28>(0h0) connect _WIRE_22.bits.source, UInt<8>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_725 = or(_T_724, _WIRE_23.ready) node _T_726 = asUInt(reset) node _T_727 = eq(_T_726, UInt<1>(0h0)) when _T_727 : node _T_728 = eq(_T_725, UInt<1>(0h0)) when _T_728 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_725, UInt<1>(0h1), "") : assert_111 node _T_729 = orr(c_set_wo_ready) when _T_729 : node _T_730 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_731 = asUInt(reset) node _T_732 = eq(_T_731, UInt<1>(0h0)) when _T_732 : node _T_733 = eq(_T_730, UInt<1>(0h0)) when _T_733 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_730, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_97 node _T_734 = orr(inflight_1) node _T_735 = eq(_T_734, UInt<1>(0h0)) node _T_736 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_737 = or(_T_735, _T_736) node _T_738 = lt(watchdog_1, plusarg_reader_1.out) node _T_739 = or(_T_737, _T_738) node _T_740 = asUInt(reset) node _T_741 = eq(_T_740, UInt<1>(0h0)) when _T_741 : node _T_742 = eq(_T_739, UInt<1>(0h0)) when _T_742 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_739, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<28>(0h0) connect _WIRE_24.bits.source, UInt<8>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_743 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_744 = and(io.in.d.ready, io.in.d.valid) node _T_745 = or(_T_743, _T_744) when _T_745 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_48( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [27:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [27:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [7:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [27:0] _c_first_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_first_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_first_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_first_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_set_wo_ready_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_set_wo_ready_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_opcodes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_opcodes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_sizes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_sizes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_opcodes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_opcodes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_sizes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_sizes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_probe_ack_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_probe_ack_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_probe_ack_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_probe_ack_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_4_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_5_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [7:0] _c_first_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_first_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_first_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_first_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_set_wo_ready_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_set_wo_ready_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_opcodes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_opcodes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_sizes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_sizes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_opcodes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_opcodes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_sizes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_sizes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_probe_ack_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_probe_ack_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_probe_ack_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_probe_ack_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_4_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_5_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [2050:0] _c_opcodes_set_T_1 = 2051'h0; // @[Monitor.scala:767:54] wire [2050:0] _c_sizes_set_T_1 = 2051'h0; // @[Monitor.scala:768:52] wire [10:0] _c_opcodes_set_T = 11'h0; // @[Monitor.scala:767:79] wire [10:0] _c_sizes_set_T = 11'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [255:0] _c_set_wo_ready_T = 256'h1; // @[OneHot.scala:58:35] wire [255:0] _c_set_T = 256'h1; // @[OneHot.scala:58:35] wire [975:0] c_opcodes_set = 976'h0; // @[Monitor.scala:740:34] wire [975:0] c_sizes_set = 976'h0; // @[Monitor.scala:741:34] wire [243:0] c_set = 244'h0; // @[Monitor.scala:738:34] wire [243:0] c_set_wo_ready = 244'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [7:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 8'hF4; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [27:0] _is_aligned_T = {22'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 28'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [7:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [7:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [7:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [7:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [7:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [7:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [7:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [7:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [7:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [7:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 8'hF4; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_672 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_672; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_672; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [7:0] source; // @[Monitor.scala:390:22] reg [27:0] address; // @[Monitor.scala:391:22] wire _T_745 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_745; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [7:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [243:0] inflight; // @[Monitor.scala:614:27] reg [975:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [975:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [243:0] a_set; // @[Monitor.scala:626:34] wire [243:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [975:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [975:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [10:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [10:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [10:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [10:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [10:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [10:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [10:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [10:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [10:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [975:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [975:0] _a_opcode_lookup_T_6 = {972'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [975:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[975:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [975:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [975:0] _a_size_lookup_T_6 = {972'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [975:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[975:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [255:0] _GEN_2 = 256'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [255:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [255:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[243:0] : 244'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_672 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[243:0] : 244'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [10:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [10:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [10:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [2050:0] _a_opcodes_set_T_1 = {2047'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[975:0] : 976'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [2050:0] _a_sizes_set_T_1 = {2047'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[975:0] : 976'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [243:0] d_clr; // @[Monitor.scala:664:34] wire [243:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [975:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [975:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [255:0] _GEN_5 = 256'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [255:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[243:0] : 244'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_745 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[243:0] : 244'h0; // @[OneHot.scala:58:35] wire [2062:0] _d_opcodes_clr_T_5 = 2063'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[975:0] : 976'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [2062:0] _d_sizes_clr_T_5 = 2063'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[975:0] : 976'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [243:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [243:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [243:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [975:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [975:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [975:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [975:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [975:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [975:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [243:0] inflight_1; // @[Monitor.scala:726:35] wire [243:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [975:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [975:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [975:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [975:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [975:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [975:0] _c_opcode_lookup_T_6 = {972'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [975:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[975:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [975:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [975:0] _c_size_lookup_T_6 = {972'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [975:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[975:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [243:0] d_clr_1; // @[Monitor.scala:774:34] wire [243:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [975:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [975:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_716 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_716 & d_release_ack_1 ? _d_clr_wo_ready_T_1[243:0] : 244'h0; // @[OneHot.scala:58:35] wire _T_698 = _T_745 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_698 ? _d_clr_T_1[243:0] : 244'h0; // @[OneHot.scala:58:35] wire [2062:0] _d_opcodes_clr_T_11 = 2063'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_698 ? _d_opcodes_clr_T_11[975:0] : 976'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [2062:0] _d_sizes_clr_T_11 = 2063'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_698 ? _d_sizes_clr_T_11[975:0] : 976'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 8'h0; // @[Monitor.scala:36:7, :795:113] wire [243:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [243:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [975:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [975:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [975:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [975:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_184 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<20>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3	module MacUnit_184( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [19:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54] assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module ClockSinkDomain_1 : output auto : { flip clock_in : { clock : Clock, reset : Reset}} output clock : Clock output reset : Reset wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset wire clockNodeIn : { clock : Clock, reset : Reset} invalidate clockNodeIn.reset invalidate clockNodeIn.clock connect clockNodeIn, auto.clock_in connect childClock, clockNodeIn.clock connect childReset, clockNodeIn.reset connect clock, clockNodeIn.clock connect reset, clockNodeIn.reset	module ClockSinkDomain_1( // @[ClockDomain.scala:14:9] input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25] input auto_clock_in_reset // @[LazyModuleImp.scala:107:25] ); wire auto_clock_in_clock_0 = auto_clock_in_clock; // @[ClockDomain.scala:14:9] wire auto_clock_in_reset_0 = auto_clock_in_reset; // @[ClockDomain.scala:14:9] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire clockNodeIn_clock = auto_clock_in_clock_0; // @[ClockDomain.scala:14:9] wire clockNodeIn_reset = auto_clock_in_reset_0; // @[ClockDomain.scala:14:9] wire childClock; // @[LazyModuleImp.scala:155:31] wire childReset; // @[LazyModuleImp.scala:158:31] assign childClock = clockNodeIn_clock; // @[MixedNode.scala:551:17] assign childReset = clockNodeIn_reset; // @[MixedNode.scala:551:17] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFN_e8_s24_30 : output io : { flip op : UInt<2>, flip a : UInt<33>, flip b : UInt<33>, flip c : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} inst mulAddRecFNToRaw_preMul of MulAddRecFNToRaw_preMul_e8_s24_30 inst mulAddRecFNToRaw_postMul of MulAddRecFNToRaw_postMul_e8_s24_30 connect mulAddRecFNToRaw_preMul.io.op, io.op connect mulAddRecFNToRaw_preMul.io.a, io.a connect mulAddRecFNToRaw_preMul.io.b, io.b connect mulAddRecFNToRaw_preMul.io.c, io.c node _mulAddResult_T = mul(mulAddRecFNToRaw_preMul.io.mulAddA, mulAddRecFNToRaw_preMul.io.mulAddB) node mulAddResult = add(_mulAddResult_T, mulAddRecFNToRaw_preMul.io.mulAddC) connect mulAddRecFNToRaw_postMul.io.fromPreMul.bit0AlignedSigC, mulAddRecFNToRaw_preMul.io.toPostMul.bit0AlignedSigC connect mulAddRecFNToRaw_postMul.io.fromPreMul.highAlignedSigC, mulAddRecFNToRaw_preMul.io.toPostMul.highAlignedSigC connect mulAddRecFNToRaw_postMul.io.fromPreMul.CDom_CAlignDist, mulAddRecFNToRaw_preMul.io.toPostMul.CDom_CAlignDist connect mulAddRecFNToRaw_postMul.io.fromPreMul.CIsDominant, mulAddRecFNToRaw_preMul.io.toPostMul.CIsDominant connect mulAddRecFNToRaw_postMul.io.fromPreMul.doSubMags, mulAddRecFNToRaw_preMul.io.toPostMul.doSubMags connect mulAddRecFNToRaw_postMul.io.fromPreMul.sExpSum, mulAddRecFNToRaw_preMul.io.toPostMul.sExpSum connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroC, mulAddRecFNToRaw_preMul.io.toPostMul.isZeroC connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfC, mulAddRecFNToRaw_preMul.io.toPostMul.isInfC connect mulAddRecFNToRaw_postMul.io.fromPreMul.isNaNC, mulAddRecFNToRaw_preMul.io.toPostMul.isNaNC connect mulAddRecFNToRaw_postMul.io.fromPreMul.signProd, mulAddRecFNToRaw_preMul.io.toPostMul.signProd connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroB, mulAddRecFNToRaw_preMul.io.toPostMul.isZeroB connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfB, mulAddRecFNToRaw_preMul.io.toPostMul.isInfB connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroA, mulAddRecFNToRaw_preMul.io.toPostMul.isZeroA connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfA, mulAddRecFNToRaw_preMul.io.toPostMul.isInfA connect mulAddRecFNToRaw_postMul.io.fromPreMul.isNaNAOrB, mulAddRecFNToRaw_preMul.io.toPostMul.isNaNAOrB connect mulAddRecFNToRaw_postMul.io.fromPreMul.isSigNaNAny, mulAddRecFNToRaw_preMul.io.toPostMul.isSigNaNAny connect mulAddRecFNToRaw_postMul.io.mulAddResult, mulAddResult connect mulAddRecFNToRaw_postMul.io.roundingMode, io.roundingMode inst roundRawFNToRecFN of RoundRawFNToRecFN_e8_s24_46 connect roundRawFNToRecFN.io.invalidExc, mulAddRecFNToRaw_postMul.io.invalidExc connect roundRawFNToRecFN.io.infiniteExc, UInt<1>(0h0) connect roundRawFNToRecFN.io.in.sig, mulAddRecFNToRaw_postMul.io.rawOut.sig connect roundRawFNToRecFN.io.in.sExp, mulAddRecFNToRaw_postMul.io.rawOut.sExp connect roundRawFNToRecFN.io.in.sign, mulAddRecFNToRaw_postMul.io.rawOut.sign connect roundRawFNToRecFN.io.in.isZero, mulAddRecFNToRaw_postMul.io.rawOut.isZero connect roundRawFNToRecFN.io.in.isInf, mulAddRecFNToRaw_postMul.io.rawOut.isInf connect roundRawFNToRecFN.io.in.isNaN, mulAddRecFNToRaw_postMul.io.rawOut.isNaN connect roundRawFNToRecFN.io.roundingMode, io.roundingMode connect roundRawFNToRecFN.io.detectTininess, io.detectTininess connect io.out, roundRawFNToRecFN.io.out connect io.exceptionFlags, roundRawFNToRecFN.io.exceptionFlags	module MulAddRecFN_e8_s24_30( // @[MulAddRecFN.scala:300:7] input [32:0] io_c, // @[MulAddRecFN.scala:303:16] output [32:0] io_out // @[MulAddRecFN.scala:303:16] ); wire _mulAddRecFNToRaw_postMul_io_invalidExc; // @[MulAddRecFN.scala:319:15] wire _mulAddRecFNToRaw_postMul_io_rawOut_isNaN; // @[MulAddRecFN.scala:319:15] wire _mulAddRecFNToRaw_postMul_io_rawOut_isInf; // @[MulAddRecFN.scala:319:15] wire _mulAddRecFNToRaw_postMul_io_rawOut_isZero; // @[MulAddRecFN.scala:319:15] wire _mulAddRecFNToRaw_postMul_io_rawOut_sign; // @[MulAddRecFN.scala:319:15] wire [9:0] _mulAddRecFNToRaw_postMul_io_rawOut_sExp; // @[MulAddRecFN.scala:319:15] wire [26:0] _mulAddRecFNToRaw_postMul_io_rawOut_sig; // @[MulAddRecFN.scala:319:15] wire [47:0] _mulAddRecFNToRaw_preMul_io_mulAddC; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfC; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC; // @[MulAddRecFN.scala:317:15] wire [9:0] _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant; // @[MulAddRecFN.scala:317:15] wire [25:0] _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC; // @[MulAddRecFN.scala:317:15] wire [32:0] io_c_0 = io_c; // @[MulAddRecFN.scala:300:7] wire [47:0] _mulAddResult_T = 48'h0; // @[MulAddRecFN.scala:327:45] wire io_detectTininess = 1'h1; // @[MulAddRecFN.scala:300:7, :303:16, :317:15, :319:15, :339:15] wire [2:0] io_roundingMode = 3'h0; // @[MulAddRecFN.scala:300:7, :303:16, :319:15, :339:15] wire [32:0] io_b = 33'h80000000; // @[MulAddRecFN.scala:300:7, :303:16, :317:15] wire [32:0] io_a = 33'h115800000; // @[MulAddRecFN.scala:300:7, :303:16, :317:15] wire [1:0] io_op = 2'h0; // @[MulAddRecFN.scala:300:7, :303:16, :317:15] wire [32:0] io_out_0; // @[MulAddRecFN.scala:300:7] wire [4:0] io_exceptionFlags; // @[MulAddRecFN.scala:300:7] wire [48:0] mulAddResult = {1'h0, _mulAddRecFNToRaw_preMul_io_mulAddC}; // @[MulAddRecFN.scala:317:15, :327:45, :328:50] MulAddRecFNToRaw_preMul_e8_s24_30 mulAddRecFNToRaw_preMul ( // @[MulAddRecFN.scala:317:15] .io_c (io_c_0), // @[MulAddRecFN.scala:300:7] .io_mulAddC (_mulAddRecFNToRaw_preMul_io_mulAddC), .io_toPostMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny), .io_toPostMul_isNaNC (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC), .io_toPostMul_isInfC (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfC), .io_toPostMul_isZeroC (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC), .io_toPostMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum), .io_toPostMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags), .io_toPostMul_CIsDominant (_mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant), .io_toPostMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC), .io_toPostMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC) ); // @[MulAddRecFN.scala:317:15] MulAddRecFNToRaw_postMul_e8_s24_30 mulAddRecFNToRaw_postMul ( // @[MulAddRecFN.scala:319:15] .io_fromPreMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isNaNC (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isInfC (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfC), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isZeroC (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_CIsDominant (_mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC), // @[MulAddRecFN.scala:317:15] .io_mulAddResult (mulAddResult), // @[MulAddRecFN.scala:328:50] .io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc), .io_rawOut_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN), .io_rawOut_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf), .io_rawOut_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero), .io_rawOut_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign), .io_rawOut_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp), .io_rawOut_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig) ); // @[MulAddRecFN.scala:319:15] RoundRawFNToRecFN_e8_s24_46 roundRawFNToRecFN ( // @[MulAddRecFN.scala:339:15] .io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc), // @[MulAddRecFN.scala:319:15] .io_in_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN), // @[MulAddRecFN.scala:319:15] .io_in_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf), // @[MulAddRecFN.scala:319:15] .io_in_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero), // @[MulAddRecFN.scala:319:15] .io_in_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign), // @[MulAddRecFN.scala:319:15] .io_in_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp), // @[MulAddRecFN.scala:319:15] .io_in_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig), // @[MulAddRecFN.scala:319:15] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags) ); // @[MulAddRecFN.scala:339:15] assign io_out = io_out_0; // @[MulAddRecFN.scala:300:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module Repeater_TLBundleD_a32d128s5k4z4u : input clock : Clock input reset : Reset output io : { flip repeat : UInt<1>, full : UInt<1>, flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}} regreset full : UInt<1>, clock, reset, UInt<1>(0h0) reg saved : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}, clock node _io_deq_valid_T = or(io.enq.valid, full) connect io.deq.valid, _io_deq_valid_T node _io_enq_ready_T = eq(full, UInt<1>(0h0)) node _io_enq_ready_T_1 = and(io.deq.ready, _io_enq_ready_T) connect io.enq.ready, _io_enq_ready_T_1 node _io_deq_bits_T = mux(full, saved, io.enq.bits) connect io.deq.bits, _io_deq_bits_T connect io.full, full node _T = and(io.enq.ready, io.enq.valid) node _T_1 = and(_T, io.repeat) when _T_1 : connect full, UInt<1>(0h1) connect saved, io.enq.bits node _T_2 = and(io.deq.ready, io.deq.valid) node _T_3 = eq(io.repeat, UInt<1>(0h0)) node _T_4 = and(_T_2, _T_3) when _T_4 : connect full, UInt<1>(0h0)	module Repeater_TLBundleD_a32d128s5k4z4u( // @[Repeater.scala:10:7] input clock, // @[Repeater.scala:10:7] input reset, // @[Repeater.scala:10:7] input io_repeat, // @[Repeater.scala:13:14] output io_enq_ready, // @[Repeater.scala:13:14] input io_enq_valid, // @[Repeater.scala:13:14] input [2:0] io_enq_bits_opcode, // @[Repeater.scala:13:14] input [1:0] io_enq_bits_param, // @[Repeater.scala:13:14] input [3:0] io_enq_bits_size, // @[Repeater.scala:13:14] input [4:0] io_enq_bits_source, // @[Repeater.scala:13:14] input [3:0] io_enq_bits_sink, // @[Repeater.scala:13:14] input io_enq_bits_denied, // @[Repeater.scala:13:14] input [127:0] io_enq_bits_data, // @[Repeater.scala:13:14] input io_enq_bits_corrupt, // @[Repeater.scala:13:14] input io_deq_ready, // @[Repeater.scala:13:14] output io_deq_valid, // @[Repeater.scala:13:14] output [2:0] io_deq_bits_opcode, // @[Repeater.scala:13:14] output [1:0] io_deq_bits_param, // @[Repeater.scala:13:14] output [3:0] io_deq_bits_size, // @[Repeater.scala:13:14] output [4:0] io_deq_bits_source, // @[Repeater.scala:13:14] output [3:0] io_deq_bits_sink, // @[Repeater.scala:13:14] output io_deq_bits_denied, // @[Repeater.scala:13:14] output [127:0] io_deq_bits_data, // @[Repeater.scala:13:14] output io_deq_bits_corrupt // @[Repeater.scala:13:14] ); wire io_repeat_0 = io_repeat; // @[Repeater.scala:10:7] wire io_enq_valid_0 = io_enq_valid; // @[Repeater.scala:10:7] wire [2:0] io_enq_bits_opcode_0 = io_enq_bits_opcode; // @[Repeater.scala:10:7] wire [1:0] io_enq_bits_param_0 = io_enq_bits_param; // @[Repeater.scala:10:7] wire [3:0] io_enq_bits_size_0 = io_enq_bits_size; // @[Repeater.scala:10:7] wire [4:0] io_enq_bits_source_0 = io_enq_bits_source; // @[Repeater.scala:10:7] wire [3:0] io_enq_bits_sink_0 = io_enq_bits_sink; // @[Repeater.scala:10:7] wire io_enq_bits_denied_0 = io_enq_bits_denied; // @[Repeater.scala:10:7] wire [127:0] io_enq_bits_data_0 = io_enq_bits_data; // @[Repeater.scala:10:7] wire io_enq_bits_corrupt_0 = io_enq_bits_corrupt; // @[Repeater.scala:10:7] wire io_deq_ready_0 = io_deq_ready; // @[Repeater.scala:10:7] wire _io_enq_ready_T_1; // @[Repeater.scala:25:32] wire _io_deq_valid_T; // @[Repeater.scala:24:32] wire [2:0] _io_deq_bits_T_opcode; // @[Repeater.scala:26:21] wire [1:0] _io_deq_bits_T_param; // @[Repeater.scala:26:21] wire [3:0] _io_deq_bits_T_size; // @[Repeater.scala:26:21] wire [4:0] _io_deq_bits_T_source; // @[Repeater.scala:26:21] wire [3:0] _io_deq_bits_T_sink; // @[Repeater.scala:26:21] wire _io_deq_bits_T_denied; // @[Repeater.scala:26:21] wire [127:0] _io_deq_bits_T_data; // @[Repeater.scala:26:21] wire _io_deq_bits_T_corrupt; // @[Repeater.scala:26:21] wire io_enq_ready_0; // @[Repeater.scala:10:7] wire [2:0] io_deq_bits_opcode_0; // @[Repeater.scala:10:7] wire [1:0] io_deq_bits_param_0; // @[Repeater.scala:10:7] wire [3:0] io_deq_bits_size_0; // @[Repeater.scala:10:7] wire [4:0] io_deq_bits_source_0; // @[Repeater.scala:10:7] wire [3:0] io_deq_bits_sink_0; // @[Repeater.scala:10:7] wire io_deq_bits_denied_0; // @[Repeater.scala:10:7] wire [127:0] io_deq_bits_data_0; // @[Repeater.scala:10:7] wire io_deq_bits_corrupt_0; // @[Repeater.scala:10:7] wire io_deq_valid_0; // @[Repeater.scala:10:7] wire io_full; // @[Repeater.scala:10:7] reg full; // @[Repeater.scala:20:21] assign io_full = full; // @[Repeater.scala:10:7, :20:21] reg [2:0] saved_opcode; // @[Repeater.scala:21:18] reg [1:0] saved_param; // @[Repeater.scala:21:18] reg [3:0] saved_size; // @[Repeater.scala:21:18] reg [4:0] saved_source; // @[Repeater.scala:21:18] reg [3:0] saved_sink; // @[Repeater.scala:21:18] reg saved_denied; // @[Repeater.scala:21:18] reg [127:0] saved_data; // @[Repeater.scala:21:18] reg saved_corrupt; // @[Repeater.scala:21:18] assign _io_deq_valid_T = io_enq_valid_0 \| full; // @[Repeater.scala:10:7, :20:21, :24:32] assign io_deq_valid_0 = _io_deq_valid_T; // @[Repeater.scala:10:7, :24:32] wire _io_enq_ready_T = ~full; // @[Repeater.scala:20:21, :25:35] assign _io_enq_ready_T_1 = io_deq_ready_0 & _io_enq_ready_T; // @[Repeater.scala:10:7, :25:{32,35}] assign io_enq_ready_0 = _io_enq_ready_T_1; // @[Repeater.scala:10:7, :25:32] assign _io_deq_bits_T_opcode = full ? saved_opcode : io_enq_bits_opcode_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_param = full ? saved_param : io_enq_bits_param_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_size = full ? saved_size : io_enq_bits_size_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_source = full ? saved_source : io_enq_bits_source_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_sink = full ? saved_sink : io_enq_bits_sink_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_denied = full ? saved_denied : io_enq_bits_denied_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_data = full ? saved_data : io_enq_bits_data_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_corrupt = full ? saved_corrupt : io_enq_bits_corrupt_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign io_deq_bits_opcode_0 = _io_deq_bits_T_opcode; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_param_0 = _io_deq_bits_T_param; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_size_0 = _io_deq_bits_T_size; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_source_0 = _io_deq_bits_T_source; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_sink_0 = _io_deq_bits_T_sink; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_denied_0 = _io_deq_bits_T_denied; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_data_0 = _io_deq_bits_T_data; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_corrupt_0 = _io_deq_bits_T_corrupt; // @[Repeater.scala:10:7, :26:21] wire _T_1 = io_enq_ready_0 & io_enq_valid_0 & io_repeat_0; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[Repeater.scala:10:7] if (reset) // @[Repeater.scala:10:7] full <= 1'h0; // @[Repeater.scala:20:21] else // @[Repeater.scala:10:7] full <= ~(io_deq_ready_0 & io_deq_valid_0 & ~io_repeat_0) & (_T_1 \| full); // @[Decoupled.scala:51:35] if (_T_1) begin // @[Decoupled.scala:51:35] saved_opcode <= io_enq_bits_opcode_0; // @[Repeater.scala:10:7, :21:18] saved_param <= io_enq_bits_param_0; // @[Repeater.scala:10:7, :21:18] saved_size <= io_enq_bits_size_0; // @[Repeater.scala:10:7, :21:18] saved_source <= io_enq_bits_source_0; // @[Repeater.scala:10:7, :21:18] saved_sink <= io_enq_bits_sink_0; // @[Repeater.scala:10:7, :21:18] saved_denied <= io_enq_bits_denied_0; // @[Repeater.scala:10:7, :21:18] saved_data <= io_enq_bits_data_0; // @[Repeater.scala:10:7, :21:18] saved_corrupt <= io_enq_bits_corrupt_0; // @[Repeater.scala:10:7, :21:18] end always @(posedge) assign io_enq_ready = io_enq_ready_0; // @[Repeater.scala:10:7] assign io_deq_valid = io_deq_valid_0; // @[Repeater.scala:10:7] assign io_deq_bits_opcode = io_deq_bits_opcode_0; // @[Repeater.scala:10:7] assign io_deq_bits_param = io_deq_bits_param_0; // @[Repeater.scala:10:7] assign io_deq_bits_size = io_deq_bits_size_0; // @[Repeater.scala:10:7] assign io_deq_bits_source = io_deq_bits_source_0; // @[Repeater.scala:10:7] assign io_deq_bits_sink = io_deq_bits_sink_0; // @[Repeater.scala:10:7] assign io_deq_bits_denied = io_deq_bits_denied_0; // @[Repeater.scala:10:7] assign io_deq_bits_data = io_deq_bits_data_0; // @[Repeater.scala:10:7] assign io_deq_bits_corrupt = io_deq_bits_corrupt_0; // @[Repeater.scala:10:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module Tile_14 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_270 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a	module Tile_14( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0, // @[Tile.scala:17:14] output io_bad_dataflow // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] wire io_bad_dataflow_0; // @[Tile.scala:16:7] PE_270 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0), .io_bad_dataflow (io_bad_dataflow_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module IssueSlot_102 : input clock : Clock input reset : Reset output io : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, flip grant : UInt<1>, iss_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, flip in_uop : { valid : UInt<1>, bits : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}}, out_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt<21>}}, flip kill : UInt<1>, flip clear : UInt<1>, flip squash_grant : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<3>, rebusy : UInt<1>}}[5], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip child_rebusys : UInt<3>} regreset slot_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg slot_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, clock wire next_valid : UInt<1> connect next_valid, slot_valid wire next_uop_out : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect next_uop_out, slot_uop node _next_uop_out_br_mask_T = not(io.brupdate.b1.resolve_mask) node _next_uop_out_br_mask_T_1 = and(slot_uop.br_mask, _next_uop_out_br_mask_T) connect next_uop_out.br_mask, _next_uop_out_br_mask_T_1 wire next_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect next_uop, next_uop_out node _killed_T = and(io.brupdate.b1.mispredict_mask, slot_uop.br_mask) node _killed_T_1 = neq(_killed_T, UInt<1>(0h0)) node killed = or(_killed_T_1, io.kill) connect io.valid, slot_valid connect io.out_uop, next_uop node _io_will_be_valid_T = eq(killed, UInt<1>(0h0)) node _io_will_be_valid_T_1 = and(next_valid, _io_will_be_valid_T) connect io.will_be_valid, _io_will_be_valid_T_1 when io.kill : connect slot_valid, UInt<1>(0h0) else : when io.in_uop.valid : connect slot_valid, UInt<1>(0h1) else : when io.clear : connect slot_valid, UInt<1>(0h0) else : node _slot_valid_T = eq(killed, UInt<1>(0h0)) node _slot_valid_T_1 = and(next_valid, _slot_valid_T) connect slot_valid, _slot_valid_T_1 when io.in_uop.valid : connect slot_uop, io.in_uop.bits node _T = eq(slot_valid, UInt<1>(0h0)) node _T_1 = or(_T, io.clear) node _T_2 = or(_T_1, io.kill) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:79 assert (!slot_valid \|\| io.clear \|\| io.kill)\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert else : connect slot_uop, next_uop connect next_uop.iw_p1_bypass_hint, UInt<1>(0h0) connect next_uop.iw_p2_bypass_hint, UInt<1>(0h0) connect next_uop.iw_p3_bypass_hint, UInt<1>(0h0) connect next_uop.iw_p1_speculative_child, UInt<1>(0h0) connect next_uop.iw_p2_speculative_child, UInt<1>(0h0) wire rebusied_prs1 : UInt<1> connect rebusied_prs1, UInt<1>(0h0) wire rebusied_prs2 : UInt<1> connect rebusied_prs2, UInt<1>(0h0) node rebusied = or(rebusied_prs1, rebusied_prs2) node prs1_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs1) node prs1_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs1) node prs1_matches_2 = eq(io.wakeup_ports[2].bits.uop.pdst, slot_uop.prs1) node prs1_matches_3 = eq(io.wakeup_ports[3].bits.uop.pdst, slot_uop.prs1) node prs1_matches_4 = eq(io.wakeup_ports[4].bits.uop.pdst, slot_uop.prs1) node prs2_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs2) node prs2_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs2) node prs2_matches_2 = eq(io.wakeup_ports[2].bits.uop.pdst, slot_uop.prs2) node prs2_matches_3 = eq(io.wakeup_ports[3].bits.uop.pdst, slot_uop.prs2) node prs2_matches_4 = eq(io.wakeup_ports[4].bits.uop.pdst, slot_uop.prs2) node prs3_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs3) node prs3_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs3) node prs3_matches_2 = eq(io.wakeup_ports[2].bits.uop.pdst, slot_uop.prs3) node prs3_matches_3 = eq(io.wakeup_ports[3].bits.uop.pdst, slot_uop.prs3) node prs3_matches_4 = eq(io.wakeup_ports[4].bits.uop.pdst, slot_uop.prs3) node prs1_wakeups_0 = and(io.wakeup_ports[0].valid, prs1_matches_0) node prs1_wakeups_1 = and(io.wakeup_ports[1].valid, prs1_matches_1) node prs1_wakeups_2 = and(io.wakeup_ports[2].valid, prs1_matches_2) node prs1_wakeups_3 = and(io.wakeup_ports[3].valid, prs1_matches_3) node prs1_wakeups_4 = and(io.wakeup_ports[4].valid, prs1_matches_4) node prs2_wakeups_0 = and(io.wakeup_ports[0].valid, prs2_matches_0) node prs2_wakeups_1 = and(io.wakeup_ports[1].valid, prs2_matches_1) node prs2_wakeups_2 = and(io.wakeup_ports[2].valid, prs2_matches_2) node prs2_wakeups_3 = and(io.wakeup_ports[3].valid, prs2_matches_3) node prs2_wakeups_4 = and(io.wakeup_ports[4].valid, prs2_matches_4) node prs3_wakeups_0 = and(io.wakeup_ports[0].valid, prs3_matches_0) node prs3_wakeups_1 = and(io.wakeup_ports[1].valid, prs3_matches_1) node prs3_wakeups_2 = and(io.wakeup_ports[2].valid, prs3_matches_2) node prs3_wakeups_3 = and(io.wakeup_ports[3].valid, prs3_matches_3) node prs3_wakeups_4 = and(io.wakeup_ports[4].valid, prs3_matches_4) node prs1_rebusys_0 = and(io.wakeup_ports[0].bits.rebusy, prs1_matches_0) node prs1_rebusys_1 = and(io.wakeup_ports[1].bits.rebusy, prs1_matches_1) node prs1_rebusys_2 = and(io.wakeup_ports[2].bits.rebusy, prs1_matches_2) node prs1_rebusys_3 = and(io.wakeup_ports[3].bits.rebusy, prs1_matches_3) node prs1_rebusys_4 = and(io.wakeup_ports[4].bits.rebusy, prs1_matches_4) node prs2_rebusys_0 = and(io.wakeup_ports[0].bits.rebusy, prs2_matches_0) node prs2_rebusys_1 = and(io.wakeup_ports[1].bits.rebusy, prs2_matches_1) node prs2_rebusys_2 = and(io.wakeup_ports[2].bits.rebusy, prs2_matches_2) node prs2_rebusys_3 = and(io.wakeup_ports[3].bits.rebusy, prs2_matches_3) node prs2_rebusys_4 = and(io.wakeup_ports[4].bits.rebusy, prs2_matches_4) node _T_6 = or(prs1_wakeups_0, prs1_wakeups_1) node _T_7 = or(_T_6, prs1_wakeups_2) node _T_8 = or(_T_7, prs1_wakeups_3) node _T_9 = or(_T_8, prs1_wakeups_4) when _T_9 : connect next_uop.prs1_busy, UInt<1>(0h0) node _next_uop_iw_p1_speculative_child_T = mux(prs1_wakeups_0, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p1_speculative_child_T_1 = mux(prs1_wakeups_1, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p1_speculative_child_T_2 = mux(prs1_wakeups_2, io.wakeup_ports[2].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p1_speculative_child_T_3 = mux(prs1_wakeups_3, io.wakeup_ports[3].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p1_speculative_child_T_4 = mux(prs1_wakeups_4, io.wakeup_ports[4].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p1_speculative_child_T_5 = or(_next_uop_iw_p1_speculative_child_T, _next_uop_iw_p1_speculative_child_T_1) node _next_uop_iw_p1_speculative_child_T_6 = or(_next_uop_iw_p1_speculative_child_T_5, _next_uop_iw_p1_speculative_child_T_2) node _next_uop_iw_p1_speculative_child_T_7 = or(_next_uop_iw_p1_speculative_child_T_6, _next_uop_iw_p1_speculative_child_T_3) node _next_uop_iw_p1_speculative_child_T_8 = or(_next_uop_iw_p1_speculative_child_T_7, _next_uop_iw_p1_speculative_child_T_4) wire _next_uop_iw_p1_speculative_child_WIRE : UInt<3> connect _next_uop_iw_p1_speculative_child_WIRE, _next_uop_iw_p1_speculative_child_T_8 connect next_uop.iw_p1_speculative_child, _next_uop_iw_p1_speculative_child_WIRE node _next_uop_iw_p1_bypass_hint_T = mux(prs1_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p1_bypass_hint_T_1 = mux(prs1_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p1_bypass_hint_T_2 = mux(prs1_wakeups_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p1_bypass_hint_T_3 = mux(prs1_wakeups_3, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p1_bypass_hint_T_4 = mux(prs1_wakeups_4, io.wakeup_ports[4].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p1_bypass_hint_T_5 = or(_next_uop_iw_p1_bypass_hint_T, _next_uop_iw_p1_bypass_hint_T_1) node _next_uop_iw_p1_bypass_hint_T_6 = or(_next_uop_iw_p1_bypass_hint_T_5, _next_uop_iw_p1_bypass_hint_T_2) node _next_uop_iw_p1_bypass_hint_T_7 = or(_next_uop_iw_p1_bypass_hint_T_6, _next_uop_iw_p1_bypass_hint_T_3) node _next_uop_iw_p1_bypass_hint_T_8 = or(_next_uop_iw_p1_bypass_hint_T_7, _next_uop_iw_p1_bypass_hint_T_4) wire _next_uop_iw_p1_bypass_hint_WIRE : UInt<1> connect _next_uop_iw_p1_bypass_hint_WIRE, _next_uop_iw_p1_bypass_hint_T_8 connect next_uop.iw_p1_bypass_hint, _next_uop_iw_p1_bypass_hint_WIRE node _T_10 = or(prs1_rebusys_0, prs1_rebusys_1) node _T_11 = or(_T_10, prs1_rebusys_2) node _T_12 = or(_T_11, prs1_rebusys_3) node _T_13 = or(_T_12, prs1_rebusys_4) node _T_14 = and(io.child_rebusys, slot_uop.iw_p1_speculative_child) node _T_15 = neq(_T_14, UInt<1>(0h0)) node _T_16 = or(_T_13, _T_15) node _T_17 = eq(slot_uop.lrs1_rtype, UInt<2>(0h0)) node _T_18 = and(_T_16, _T_17) when _T_18 : connect next_uop.prs1_busy, UInt<1>(0h1) connect rebusied_prs1, UInt<1>(0h1) node _T_19 = or(prs2_wakeups_0, prs2_wakeups_1) node _T_20 = or(_T_19, prs2_wakeups_2) node _T_21 = or(_T_20, prs2_wakeups_3) node _T_22 = or(_T_21, prs2_wakeups_4) when _T_22 : connect next_uop.prs2_busy, UInt<1>(0h0) node _next_uop_iw_p2_speculative_child_T = mux(prs2_wakeups_0, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p2_speculative_child_T_1 = mux(prs2_wakeups_1, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p2_speculative_child_T_2 = mux(prs2_wakeups_2, io.wakeup_ports[2].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p2_speculative_child_T_3 = mux(prs2_wakeups_3, io.wakeup_ports[3].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p2_speculative_child_T_4 = mux(prs2_wakeups_4, io.wakeup_ports[4].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p2_speculative_child_T_5 = or(_next_uop_iw_p2_speculative_child_T, _next_uop_iw_p2_speculative_child_T_1) node _next_uop_iw_p2_speculative_child_T_6 = or(_next_uop_iw_p2_speculative_child_T_5, _next_uop_iw_p2_speculative_child_T_2) node _next_uop_iw_p2_speculative_child_T_7 = or(_next_uop_iw_p2_speculative_child_T_6, _next_uop_iw_p2_speculative_child_T_3) node _next_uop_iw_p2_speculative_child_T_8 = or(_next_uop_iw_p2_speculative_child_T_7, _next_uop_iw_p2_speculative_child_T_4) wire _next_uop_iw_p2_speculative_child_WIRE : UInt<3> connect _next_uop_iw_p2_speculative_child_WIRE, _next_uop_iw_p2_speculative_child_T_8 connect next_uop.iw_p2_speculative_child, _next_uop_iw_p2_speculative_child_WIRE node _next_uop_iw_p2_bypass_hint_T = mux(prs2_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p2_bypass_hint_T_1 = mux(prs2_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p2_bypass_hint_T_2 = mux(prs2_wakeups_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p2_bypass_hint_T_3 = mux(prs2_wakeups_3, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p2_bypass_hint_T_4 = mux(prs2_wakeups_4, io.wakeup_ports[4].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p2_bypass_hint_T_5 = or(_next_uop_iw_p2_bypass_hint_T, _next_uop_iw_p2_bypass_hint_T_1) node _next_uop_iw_p2_bypass_hint_T_6 = or(_next_uop_iw_p2_bypass_hint_T_5, _next_uop_iw_p2_bypass_hint_T_2) node _next_uop_iw_p2_bypass_hint_T_7 = or(_next_uop_iw_p2_bypass_hint_T_6, _next_uop_iw_p2_bypass_hint_T_3) node _next_uop_iw_p2_bypass_hint_T_8 = or(_next_uop_iw_p2_bypass_hint_T_7, _next_uop_iw_p2_bypass_hint_T_4) wire _next_uop_iw_p2_bypass_hint_WIRE : UInt<1> connect _next_uop_iw_p2_bypass_hint_WIRE, _next_uop_iw_p2_bypass_hint_T_8 connect next_uop.iw_p2_bypass_hint, _next_uop_iw_p2_bypass_hint_WIRE node _T_23 = or(prs2_rebusys_0, prs2_rebusys_1) node _T_24 = or(_T_23, prs2_rebusys_2) node _T_25 = or(_T_24, prs2_rebusys_3) node _T_26 = or(_T_25, prs2_rebusys_4) node _T_27 = and(io.child_rebusys, slot_uop.iw_p2_speculative_child) node _T_28 = neq(_T_27, UInt<1>(0h0)) node _T_29 = or(_T_26, _T_28) node _T_30 = eq(slot_uop.lrs2_rtype, UInt<2>(0h0)) node _T_31 = and(_T_29, _T_30) when _T_31 : connect next_uop.prs2_busy, UInt<1>(0h1) connect rebusied_prs2, UInt<1>(0h1) node _T_32 = or(prs3_wakeups_0, prs3_wakeups_1) node _T_33 = or(_T_32, prs3_wakeups_2) node _T_34 = or(_T_33, prs3_wakeups_3) node _T_35 = or(_T_34, prs3_wakeups_4) when _T_35 : connect next_uop.prs3_busy, UInt<1>(0h0) node _next_uop_iw_p3_bypass_hint_T = mux(prs3_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p3_bypass_hint_T_1 = mux(prs3_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p3_bypass_hint_T_2 = mux(prs3_wakeups_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p3_bypass_hint_T_3 = mux(prs3_wakeups_3, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p3_bypass_hint_T_4 = mux(prs3_wakeups_4, io.wakeup_ports[4].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p3_bypass_hint_T_5 = or(_next_uop_iw_p3_bypass_hint_T, _next_uop_iw_p3_bypass_hint_T_1) node _next_uop_iw_p3_bypass_hint_T_6 = or(_next_uop_iw_p3_bypass_hint_T_5, _next_uop_iw_p3_bypass_hint_T_2) node _next_uop_iw_p3_bypass_hint_T_7 = or(_next_uop_iw_p3_bypass_hint_T_6, _next_uop_iw_p3_bypass_hint_T_3) node _next_uop_iw_p3_bypass_hint_T_8 = or(_next_uop_iw_p3_bypass_hint_T_7, _next_uop_iw_p3_bypass_hint_T_4) wire _next_uop_iw_p3_bypass_hint_WIRE : UInt<1> connect _next_uop_iw_p3_bypass_hint_WIRE, _next_uop_iw_p3_bypass_hint_T_8 connect next_uop.iw_p3_bypass_hint, _next_uop_iw_p3_bypass_hint_WIRE node _T_36 = eq(io.pred_wakeup_port.bits, slot_uop.ppred) node _T_37 = and(io.pred_wakeup_port.valid, _T_36) when _T_37 : connect next_uop.ppred_busy, UInt<1>(0h0) node _iss_ready_T = eq(slot_uop.prs1_busy, UInt<1>(0h0)) node _iss_ready_T_1 = eq(slot_uop.prs2_busy, UInt<1>(0h0)) node _iss_ready_T_2 = and(_iss_ready_T, _iss_ready_T_1) node _iss_ready_T_3 = and(slot_uop.ppred_busy, UInt<1>(0h1)) node _iss_ready_T_4 = eq(_iss_ready_T_3, UInt<1>(0h0)) node _iss_ready_T_5 = and(_iss_ready_T_2, _iss_ready_T_4) node _iss_ready_T_6 = and(slot_uop.prs3_busy, UInt<1>(0h0)) node _iss_ready_T_7 = eq(_iss_ready_T_6, UInt<1>(0h0)) node iss_ready = and(_iss_ready_T_5, _iss_ready_T_7) node _agen_ready_T = eq(slot_uop.prs1_busy, UInt<1>(0h0)) node _agen_ready_T_1 = and(slot_uop.fu_code[1], _agen_ready_T) node _agen_ready_T_2 = and(slot_uop.ppred_busy, UInt<1>(0h1)) node _agen_ready_T_3 = eq(_agen_ready_T_2, UInt<1>(0h0)) node _agen_ready_T_4 = and(_agen_ready_T_1, _agen_ready_T_3) node agen_ready = and(_agen_ready_T_4, UInt<1>(0h0)) node _dgen_ready_T = eq(slot_uop.prs2_busy, UInt<1>(0h0)) node _dgen_ready_T_1 = and(slot_uop.fu_code[2], _dgen_ready_T) node _dgen_ready_T_2 = and(slot_uop.ppred_busy, UInt<1>(0h1)) node _dgen_ready_T_3 = eq(_dgen_ready_T_2, UInt<1>(0h0)) node _dgen_ready_T_4 = and(_dgen_ready_T_1, _dgen_ready_T_3) node dgen_ready = and(_dgen_ready_T_4, UInt<1>(0h0)) node _io_request_T = eq(slot_uop.iw_issued, UInt<1>(0h0)) node _io_request_T_1 = and(slot_valid, _io_request_T) node _io_request_T_2 = or(iss_ready, agen_ready) node _io_request_T_3 = or(_io_request_T_2, dgen_ready) node _io_request_T_4 = and(_io_request_T_1, _io_request_T_3) connect io.request, _io_request_T_4 connect io.iss_uop, slot_uop connect next_uop.iw_issued, UInt<1>(0h0) connect next_uop.iw_issued_partial_agen, UInt<1>(0h0) connect next_uop.iw_issued_partial_dgen, UInt<1>(0h0) node _T_38 = eq(io.squash_grant, UInt<1>(0h0)) node _T_39 = and(io.grant, _T_38) when _T_39 : connect next_uop.iw_issued, UInt<1>(0h1) node _T_40 = and(slot_valid, slot_uop.iw_issued) when _T_40 : connect next_valid, rebusied	module IssueSlot_102( // @[issue-slot.scala:49:7] input clock, // @[issue-slot.scala:49:7] input reset, // @[issue-slot.scala:49:7] output io_valid, // @[issue-slot.scala:52:14] output io_will_be_valid, // @[issue-slot.scala:52:14] output io_request, // @[issue-slot.scala:52:14] input io_grant, // @[issue-slot.scala:52:14] output [31:0] io_iss_uop_inst, // @[issue-slot.scala:52:14] output [31:0] io_iss_uop_debug_inst, // @[issue-slot.scala:52:14] output io_iss_uop_is_rvc, // @[issue-slot.scala:52:14] output [39:0] io_iss_uop_debug_pc, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_0, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_1, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_2, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_3, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_0, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_1, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_2, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_3, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_4, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_5, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_6, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_7, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_8, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_9, // @[issue-slot.scala:52:14] output io_iss_uop_iw_issued, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_dis_col_sel, // @[issue-slot.scala:52:14] output [15:0] io_iss_uop_br_mask, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_br_tag, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_br_type, // @[issue-slot.scala:52:14] output io_iss_uop_is_sfb, // @[issue-slot.scala:52:14] output io_iss_uop_is_fence, // @[issue-slot.scala:52:14] output io_iss_uop_is_fencei, // @[issue-slot.scala:52:14] output io_iss_uop_is_sfence, // @[issue-slot.scala:52:14] output io_iss_uop_is_amo, // @[issue-slot.scala:52:14] output io_iss_uop_is_eret, // @[issue-slot.scala:52:14] output io_iss_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] output io_iss_uop_is_rocc, // @[issue-slot.scala:52:14] output io_iss_uop_is_mov, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ftq_idx, // @[issue-slot.scala:52:14] output io_iss_uop_edge_inst, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_pc_lob, // @[issue-slot.scala:52:14] output io_iss_uop_taken, // @[issue-slot.scala:52:14] output io_iss_uop_imm_rename, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_imm_sel, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_pimm, // @[issue-slot.scala:52:14] output [19:0] io_iss_uop_imm_packed, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_op1_sel, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_op2_sel, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_rob_idx, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ldq_idx, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_stq_idx, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_rxq_idx, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_pdst, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs1, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs2, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs3, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ppred, // @[issue-slot.scala:52:14] output io_iss_uop_prs1_busy, // @[issue-slot.scala:52:14] output io_iss_uop_prs2_busy, // @[issue-slot.scala:52:14] output io_iss_uop_prs3_busy, // @[issue-slot.scala:52:14] output io_iss_uop_ppred_busy, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_stale_pdst, // @[issue-slot.scala:52:14] output io_iss_uop_exception, // @[issue-slot.scala:52:14] output [63:0] io_iss_uop_exc_cause, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_mem_cmd, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_mem_size, // @[issue-slot.scala:52:14] output io_iss_uop_mem_signed, // @[issue-slot.scala:52:14] output io_iss_uop_uses_ldq, // @[issue-slot.scala:52:14] output io_iss_uop_uses_stq, // @[issue-slot.scala:52:14] output io_iss_uop_is_unique, // @[issue-slot.scala:52:14] output io_iss_uop_flush_on_commit, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_csr_cmd, // @[issue-slot.scala:52:14] output io_iss_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_ldst, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs1, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs2, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs3, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_dst_rtype, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_lrs1_rtype, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_lrs2_rtype, // @[issue-slot.scala:52:14] output io_iss_uop_frs3_en, // @[issue-slot.scala:52:14] output io_iss_uop_fcn_dw, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_fcn_op, // @[issue-slot.scala:52:14] output io_iss_uop_fp_val, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_fp_rm, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_typ, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] output io_iss_uop_bp_debug_if, // @[issue-slot.scala:52:14] output io_iss_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_debug_fsrc, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_in_uop_valid, // @[issue-slot.scala:52:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:52:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_0, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_1, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_2, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_0, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_1, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_2, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_4, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_5, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_6, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_7, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_8, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_9, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_issued, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_br_type, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sfence, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_eret, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_rocc, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:52:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:52:14] input io_in_uop_bits_taken, // @[issue-slot.scala:52:14] input io_in_uop_bits_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_pimm, // @[issue-slot.scala:52:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_op2_sel, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:52:14] input io_in_uop_bits_exception, // @[issue-slot.scala:52:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:52:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:52:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:52:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:52:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_csr_cmd, // @[issue-slot.scala:52:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:52:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:52:14] input io_in_uop_bits_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_fcn_op, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_typ, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:52:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:52:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:52:14] output io_out_uop_is_rvc, // @[issue-slot.scala:52:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_0, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_1, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_2, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_3, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_0, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_1, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_2, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_3, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_4, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_5, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_6, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_7, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_8, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_9, // @[issue-slot.scala:52:14] output io_out_uop_iw_issued, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] output io_out_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] output io_out_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] output io_out_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_dis_col_sel, // @[issue-slot.scala:52:14] output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_br_type, // @[issue-slot.scala:52:14] output io_out_uop_is_sfb, // @[issue-slot.scala:52:14] output io_out_uop_is_fence, // @[issue-slot.scala:52:14] output io_out_uop_is_fencei, // @[issue-slot.scala:52:14] output io_out_uop_is_sfence, // @[issue-slot.scala:52:14] output io_out_uop_is_amo, // @[issue-slot.scala:52:14] output io_out_uop_is_eret, // @[issue-slot.scala:52:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] output io_out_uop_is_rocc, // @[issue-slot.scala:52:14] output io_out_uop_is_mov, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:52:14] output io_out_uop_edge_inst, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:52:14] output io_out_uop_taken, // @[issue-slot.scala:52:14] output io_out_uop_imm_rename, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_imm_sel, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_pimm, // @[issue-slot.scala:52:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_op1_sel, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_op2_sel, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_pdst, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs1, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs2, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs3, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ppred, // @[issue-slot.scala:52:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:52:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:52:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:52:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:52:14] output io_out_uop_exception, // @[issue-slot.scala:52:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:52:14] output io_out_uop_mem_signed, // @[issue-slot.scala:52:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:52:14] output io_out_uop_uses_stq, // @[issue-slot.scala:52:14] output io_out_uop_is_unique, // @[issue-slot.scala:52:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_csr_cmd, // @[issue-slot.scala:52:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:52:14] output io_out_uop_frs3_en, // @[issue-slot.scala:52:14] output io_out_uop_fcn_dw, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_fcn_op, // @[issue-slot.scala:52:14] output io_out_uop_fp_val, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_fp_rm, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_typ, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:52:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:52:14] input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:52:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:52:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_br_type, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sfence, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_eret, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_rocc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_op2_sel, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_fcn_op, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_typ, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:52:14] input io_brupdate_b2_taken, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:52:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:52:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:52:14] input io_kill, // @[issue-slot.scala:52:14] input io_clear, // @[issue-slot.scala:52:14] input io_squash_grant, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_0_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_0_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_0_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_0_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_0_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_0_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_bypassable, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_speculative_mask, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_rebusy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_1_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_1_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_1_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_1_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_1_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_1_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_2_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_2_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_2_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_2_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_2_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_2_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_3_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_3_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_3_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_3_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_3_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_3_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_4_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_4_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_4_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_4_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_4_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_4_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_4_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_4_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_pred_wakeup_port_valid, // @[issue-slot.scala:52:14] input [4:0] io_pred_wakeup_port_bits, // @[issue-slot.scala:52:14] input [2:0] io_child_rebusys // @[issue-slot.scala:52:14] ); wire [15:0] next_uop_out_br_mask; // @[util.scala:104:23] wire io_grant_0 = io_grant; // @[issue-slot.scala:49:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:49:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:49:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_0_0 = io_in_uop_bits_iq_type_0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_1_0 = io_in_uop_bits_iq_type_1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_2_0 = io_in_uop_bits_iq_type_2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_3_0 = io_in_uop_bits_iq_type_3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_0_0 = io_in_uop_bits_fu_code_0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_1_0 = io_in_uop_bits_fu_code_1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_2_0 = io_in_uop_bits_fu_code_2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_3_0 = io_in_uop_bits_fu_code_3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_4_0 = io_in_uop_bits_fu_code_4; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_5_0 = io_in_uop_bits_fu_code_5; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_6_0 = io_in_uop_bits_fu_code_6; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_7_0 = io_in_uop_bits_fu_code_7; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_8_0 = io_in_uop_bits_fu_code_8; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_9_0 = io_in_uop_bits_fu_code_9; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_0 = io_in_uop_bits_iw_issued; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_iw_p1_speculative_child_0 = io_in_uop_bits_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_iw_p2_speculative_child_0 = io_in_uop_bits_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p1_bypass_hint_0 = io_in_uop_bits_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p2_bypass_hint_0 = io_in_uop_bits_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p3_bypass_hint_0 = io_in_uop_bits_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_dis_col_sel_0 = io_in_uop_bits_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_br_type_0 = io_in_uop_bits_br_type; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sfence_0 = io_in_uop_bits_is_sfence; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_eret_0 = io_in_uop_bits_is_eret; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_rocc_0 = io_in_uop_bits_is_rocc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_mov_0 = io_in_uop_bits_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:49:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:49:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:49:7] wire io_in_uop_bits_imm_rename_0 = io_in_uop_bits_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_imm_sel_0 = io_in_uop_bits_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_pimm_0 = io_in_uop_bits_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_op1_sel_0 = io_in_uop_bits_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_op2_sel_0 = io_in_uop_bits_op2_sel; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ldst_0 = io_in_uop_bits_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_wen_0 = io_in_uop_bits_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren1_0 = io_in_uop_bits_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren2_0 = io_in_uop_bits_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren3_0 = io_in_uop_bits_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_swap12_0 = io_in_uop_bits_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_swap23_0 = io_in_uop_bits_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_ctrl_typeTagIn_0 = io_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_ctrl_typeTagOut_0 = io_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fromint_0 = io_in_uop_bits_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_toint_0 = io_in_uop_bits_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fastpipe_0 = io_in_uop_bits_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fma_0 = io_in_uop_bits_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_div_0 = io_in_uop_bits_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_sqrt_0 = io_in_uop_bits_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_wflags_0 = io_in_uop_bits_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_vec_0 = io_in_uop_bits_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:49:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:49:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:49:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:49:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:49:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_csr_cmd_0 = io_in_uop_bits_csr_cmd; // @[issue-slot.scala:49:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fcn_dw_0 = io_in_uop_bits_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_fcn_op_0 = io_in_uop_bits_fcn_op; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_fp_rm_0 = io_in_uop_bits_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_typ_0 = io_in_uop_bits_fp_typ; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:49:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:49:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:49:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:49:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:49:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:49:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:49:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:49:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:49:7] wire io_squash_grant_0 = io_squash_grant; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_0_bits_uop_inst_0 = io_wakeup_ports_0_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_0_bits_uop_debug_inst_0 = io_wakeup_ports_0_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_rvc_0 = io_wakeup_ports_0_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_0_bits_uop_debug_pc_0 = io_wakeup_ports_0_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_0_0 = io_wakeup_ports_0_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_1_0 = io_wakeup_ports_0_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_2_0 = io_wakeup_ports_0_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_3_0 = io_wakeup_ports_0_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_0_0 = io_wakeup_ports_0_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_1_0 = io_wakeup_ports_0_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_2_0 = io_wakeup_ports_0_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_3_0 = io_wakeup_ports_0_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_4_0 = io_wakeup_ports_0_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_5_0 = io_wakeup_ports_0_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_6_0 = io_wakeup_ports_0_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_7_0 = io_wakeup_ports_0_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_8_0 = io_wakeup_ports_0_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_9_0 = io_wakeup_ports_0_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_0 = io_wakeup_ports_0_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel_0 = io_wakeup_ports_0_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_0_bits_uop_br_mask_0 = io_wakeup_ports_0_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_tag_0 = io_wakeup_ports_0_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_type_0 = io_wakeup_ports_0_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sfb_0 = io_wakeup_ports_0_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_fence_0 = io_wakeup_ports_0_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_fencei_0 = io_wakeup_ports_0_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sfence_0 = io_wakeup_ports_0_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_amo_0 = io_wakeup_ports_0_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_eret_0 = io_wakeup_ports_0_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_0_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_rocc_0 = io_wakeup_ports_0_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_mov_0 = io_wakeup_ports_0_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ftq_idx_0 = io_wakeup_ports_0_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_edge_inst_0 = io_wakeup_ports_0_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_pc_lob_0 = io_wakeup_ports_0_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_taken_0 = io_wakeup_ports_0_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_imm_rename_0 = io_wakeup_ports_0_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_imm_sel_0 = io_wakeup_ports_0_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_pimm_0 = io_wakeup_ports_0_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_0_bits_uop_imm_packed_0 = io_wakeup_ports_0_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_op1_sel_0 = io_wakeup_ports_0_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_op2_sel_0 = io_wakeup_ports_0_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_rob_idx_0 = io_wakeup_ports_0_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ldq_idx_0 = io_wakeup_ports_0_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_stq_idx_0 = io_wakeup_ports_0_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_rxq_idx_0 = io_wakeup_ports_0_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_pdst_0 = io_wakeup_ports_0_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs1_0 = io_wakeup_ports_0_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs2_0 = io_wakeup_ports_0_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs3_0 = io_wakeup_ports_0_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ppred_0 = io_wakeup_ports_0_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs1_busy_0 = io_wakeup_ports_0_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs2_busy_0 = io_wakeup_ports_0_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs3_busy_0 = io_wakeup_ports_0_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_ppred_busy_0 = io_wakeup_ports_0_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_stale_pdst_0 = io_wakeup_ports_0_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_exception_0 = io_wakeup_ports_0_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_0_bits_uop_exc_cause_0 = io_wakeup_ports_0_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_mem_cmd_0 = io_wakeup_ports_0_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_mem_size_0 = io_wakeup_ports_0_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_mem_signed_0 = io_wakeup_ports_0_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_uses_ldq_0 = io_wakeup_ports_0_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_uses_stq_0 = io_wakeup_ports_0_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_unique_0 = io_wakeup_ports_0_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_flush_on_commit_0 = io_wakeup_ports_0_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_csr_cmd_0 = io_wakeup_ports_0_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_0_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_ldst_0 = io_wakeup_ports_0_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs1_0 = io_wakeup_ports_0_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs2_0 = io_wakeup_ports_0_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs3_0 = io_wakeup_ports_0_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_dst_rtype_0 = io_wakeup_ports_0_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype_0 = io_wakeup_ports_0_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype_0 = io_wakeup_ports_0_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_frs3_en_0 = io_wakeup_ports_0_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fcn_dw_0 = io_wakeup_ports_0_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_fcn_op_0 = io_wakeup_ports_0_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_val_0 = io_wakeup_ports_0_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_fp_rm_0 = io_wakeup_ports_0_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_typ_0 = io_wakeup_ports_0_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_0_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_bp_debug_if_0 = io_wakeup_ports_0_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_0_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc_0 = io_wakeup_ports_0_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc_0 = io_wakeup_ports_0_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_bypassable_0 = io_wakeup_ports_0_bits_bypassable; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_speculative_mask_0 = io_wakeup_ports_0_bits_speculative_mask; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_rebusy_0 = io_wakeup_ports_0_bits_rebusy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_1_bits_uop_inst_0 = io_wakeup_ports_1_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_1_bits_uop_debug_inst_0 = io_wakeup_ports_1_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_rvc_0 = io_wakeup_ports_1_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_1_bits_uop_debug_pc_0 = io_wakeup_ports_1_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_0_0 = io_wakeup_ports_1_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_1_0 = io_wakeup_ports_1_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_2_0 = io_wakeup_ports_1_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_3_0 = io_wakeup_ports_1_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_0_0 = io_wakeup_ports_1_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_1_0 = io_wakeup_ports_1_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_2_0 = io_wakeup_ports_1_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_3_0 = io_wakeup_ports_1_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_4_0 = io_wakeup_ports_1_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_5_0 = io_wakeup_ports_1_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_6_0 = io_wakeup_ports_1_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_7_0 = io_wakeup_ports_1_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_8_0 = io_wakeup_ports_1_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_9_0 = io_wakeup_ports_1_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_0 = io_wakeup_ports_1_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel_0 = io_wakeup_ports_1_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_1_bits_uop_br_mask_0 = io_wakeup_ports_1_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_tag_0 = io_wakeup_ports_1_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_type_0 = io_wakeup_ports_1_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sfb_0 = io_wakeup_ports_1_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_fence_0 = io_wakeup_ports_1_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_fencei_0 = io_wakeup_ports_1_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sfence_0 = io_wakeup_ports_1_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_amo_0 = io_wakeup_ports_1_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_eret_0 = io_wakeup_ports_1_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_1_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_rocc_0 = io_wakeup_ports_1_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_mov_0 = io_wakeup_ports_1_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ftq_idx_0 = io_wakeup_ports_1_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_edge_inst_0 = io_wakeup_ports_1_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_pc_lob_0 = io_wakeup_ports_1_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_taken_0 = io_wakeup_ports_1_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_imm_rename_0 = io_wakeup_ports_1_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_imm_sel_0 = io_wakeup_ports_1_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_pimm_0 = io_wakeup_ports_1_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_1_bits_uop_imm_packed_0 = io_wakeup_ports_1_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_op1_sel_0 = io_wakeup_ports_1_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_op2_sel_0 = io_wakeup_ports_1_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_rob_idx_0 = io_wakeup_ports_1_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ldq_idx_0 = io_wakeup_ports_1_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_stq_idx_0 = io_wakeup_ports_1_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_rxq_idx_0 = io_wakeup_ports_1_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_pdst_0 = io_wakeup_ports_1_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs1_0 = io_wakeup_ports_1_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs2_0 = io_wakeup_ports_1_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs3_0 = io_wakeup_ports_1_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ppred_0 = io_wakeup_ports_1_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs1_busy_0 = io_wakeup_ports_1_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs2_busy_0 = io_wakeup_ports_1_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs3_busy_0 = io_wakeup_ports_1_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_ppred_busy_0 = io_wakeup_ports_1_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_stale_pdst_0 = io_wakeup_ports_1_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_exception_0 = io_wakeup_ports_1_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_1_bits_uop_exc_cause_0 = io_wakeup_ports_1_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_mem_cmd_0 = io_wakeup_ports_1_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_mem_size_0 = io_wakeup_ports_1_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_mem_signed_0 = io_wakeup_ports_1_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_uses_ldq_0 = io_wakeup_ports_1_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_uses_stq_0 = io_wakeup_ports_1_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_unique_0 = io_wakeup_ports_1_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_flush_on_commit_0 = io_wakeup_ports_1_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_csr_cmd_0 = io_wakeup_ports_1_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_1_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_ldst_0 = io_wakeup_ports_1_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs1_0 = io_wakeup_ports_1_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs2_0 = io_wakeup_ports_1_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs3_0 = io_wakeup_ports_1_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_dst_rtype_0 = io_wakeup_ports_1_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype_0 = io_wakeup_ports_1_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype_0 = io_wakeup_ports_1_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_frs3_en_0 = io_wakeup_ports_1_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fcn_dw_0 = io_wakeup_ports_1_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_fcn_op_0 = io_wakeup_ports_1_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_val_0 = io_wakeup_ports_1_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_fp_rm_0 = io_wakeup_ports_1_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_typ_0 = io_wakeup_ports_1_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_1_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_bp_debug_if_0 = io_wakeup_ports_1_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_1_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc_0 = io_wakeup_ports_1_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc_0 = io_wakeup_ports_1_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_2_bits_uop_inst_0 = io_wakeup_ports_2_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_2_bits_uop_debug_inst_0 = io_wakeup_ports_2_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_rvc_0 = io_wakeup_ports_2_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_2_bits_uop_debug_pc_0 = io_wakeup_ports_2_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_0_0 = io_wakeup_ports_2_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_1_0 = io_wakeup_ports_2_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_2_0 = io_wakeup_ports_2_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_3_0 = io_wakeup_ports_2_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_0_0 = io_wakeup_ports_2_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_1_0 = io_wakeup_ports_2_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_2_0 = io_wakeup_ports_2_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_3_0 = io_wakeup_ports_2_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_4_0 = io_wakeup_ports_2_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_5_0 = io_wakeup_ports_2_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_6_0 = io_wakeup_ports_2_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_7_0 = io_wakeup_ports_2_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_8_0 = io_wakeup_ports_2_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_9_0 = io_wakeup_ports_2_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_0 = io_wakeup_ports_2_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_dis_col_sel_0 = io_wakeup_ports_2_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_2_bits_uop_br_mask_0 = io_wakeup_ports_2_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_br_tag_0 = io_wakeup_ports_2_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_br_type_0 = io_wakeup_ports_2_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sfb_0 = io_wakeup_ports_2_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_fence_0 = io_wakeup_ports_2_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_fencei_0 = io_wakeup_ports_2_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sfence_0 = io_wakeup_ports_2_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_amo_0 = io_wakeup_ports_2_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_eret_0 = io_wakeup_ports_2_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_2_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_rocc_0 = io_wakeup_ports_2_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_mov_0 = io_wakeup_ports_2_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_ftq_idx_0 = io_wakeup_ports_2_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_edge_inst_0 = io_wakeup_ports_2_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_pc_lob_0 = io_wakeup_ports_2_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_taken_0 = io_wakeup_ports_2_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_imm_rename_0 = io_wakeup_ports_2_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_imm_sel_0 = io_wakeup_ports_2_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_pimm_0 = io_wakeup_ports_2_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_2_bits_uop_imm_packed_0 = io_wakeup_ports_2_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_op1_sel_0 = io_wakeup_ports_2_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_op2_sel_0 = io_wakeup_ports_2_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_rob_idx_0 = io_wakeup_ports_2_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_ldq_idx_0 = io_wakeup_ports_2_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_stq_idx_0 = io_wakeup_ports_2_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_rxq_idx_0 = io_wakeup_ports_2_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_pdst_0 = io_wakeup_ports_2_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs1_0 = io_wakeup_ports_2_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs2_0 = io_wakeup_ports_2_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs3_0 = io_wakeup_ports_2_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_ppred_0 = io_wakeup_ports_2_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs1_busy_0 = io_wakeup_ports_2_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs2_busy_0 = io_wakeup_ports_2_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs3_busy_0 = io_wakeup_ports_2_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_ppred_busy_0 = io_wakeup_ports_2_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_stale_pdst_0 = io_wakeup_ports_2_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_exception_0 = io_wakeup_ports_2_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_2_bits_uop_exc_cause_0 = io_wakeup_ports_2_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_mem_cmd_0 = io_wakeup_ports_2_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_mem_size_0 = io_wakeup_ports_2_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_mem_signed_0 = io_wakeup_ports_2_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_uses_ldq_0 = io_wakeup_ports_2_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_uses_stq_0 = io_wakeup_ports_2_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_unique_0 = io_wakeup_ports_2_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_flush_on_commit_0 = io_wakeup_ports_2_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_csr_cmd_0 = io_wakeup_ports_2_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_2_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_ldst_0 = io_wakeup_ports_2_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs1_0 = io_wakeup_ports_2_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs2_0 = io_wakeup_ports_2_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs3_0 = io_wakeup_ports_2_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_dst_rtype_0 = io_wakeup_ports_2_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype_0 = io_wakeup_ports_2_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype_0 = io_wakeup_ports_2_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_frs3_en_0 = io_wakeup_ports_2_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fcn_dw_0 = io_wakeup_ports_2_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_fcn_op_0 = io_wakeup_ports_2_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_val_0 = io_wakeup_ports_2_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_fp_rm_0 = io_wakeup_ports_2_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_typ_0 = io_wakeup_ports_2_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_2_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_bp_debug_if_0 = io_wakeup_ports_2_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_2_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc_0 = io_wakeup_ports_2_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc_0 = io_wakeup_ports_2_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_3_bits_uop_inst_0 = io_wakeup_ports_3_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_3_bits_uop_debug_inst_0 = io_wakeup_ports_3_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_rvc_0 = io_wakeup_ports_3_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_3_bits_uop_debug_pc_0 = io_wakeup_ports_3_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_0_0 = io_wakeup_ports_3_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_1_0 = io_wakeup_ports_3_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_2_0 = io_wakeup_ports_3_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_3_0 = io_wakeup_ports_3_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_0_0 = io_wakeup_ports_3_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_1_0 = io_wakeup_ports_3_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_2_0 = io_wakeup_ports_3_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_3_0 = io_wakeup_ports_3_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_4_0 = io_wakeup_ports_3_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_5_0 = io_wakeup_ports_3_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_6_0 = io_wakeup_ports_3_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_7_0 = io_wakeup_ports_3_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_8_0 = io_wakeup_ports_3_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_9_0 = io_wakeup_ports_3_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_0 = io_wakeup_ports_3_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_dis_col_sel_0 = io_wakeup_ports_3_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_3_bits_uop_br_mask_0 = io_wakeup_ports_3_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_br_tag_0 = io_wakeup_ports_3_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_br_type_0 = io_wakeup_ports_3_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sfb_0 = io_wakeup_ports_3_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_fence_0 = io_wakeup_ports_3_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_fencei_0 = io_wakeup_ports_3_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sfence_0 = io_wakeup_ports_3_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_amo_0 = io_wakeup_ports_3_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_eret_0 = io_wakeup_ports_3_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_3_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_rocc_0 = io_wakeup_ports_3_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_mov_0 = io_wakeup_ports_3_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_ftq_idx_0 = io_wakeup_ports_3_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_edge_inst_0 = io_wakeup_ports_3_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_pc_lob_0 = io_wakeup_ports_3_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_taken_0 = io_wakeup_ports_3_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_imm_rename_0 = io_wakeup_ports_3_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_imm_sel_0 = io_wakeup_ports_3_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_pimm_0 = io_wakeup_ports_3_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_3_bits_uop_imm_packed_0 = io_wakeup_ports_3_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_op1_sel_0 = io_wakeup_ports_3_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_op2_sel_0 = io_wakeup_ports_3_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_rob_idx_0 = io_wakeup_ports_3_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_ldq_idx_0 = io_wakeup_ports_3_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_stq_idx_0 = io_wakeup_ports_3_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_rxq_idx_0 = io_wakeup_ports_3_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_pdst_0 = io_wakeup_ports_3_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs1_0 = io_wakeup_ports_3_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs2_0 = io_wakeup_ports_3_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs3_0 = io_wakeup_ports_3_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_ppred_0 = io_wakeup_ports_3_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs1_busy_0 = io_wakeup_ports_3_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs2_busy_0 = io_wakeup_ports_3_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs3_busy_0 = io_wakeup_ports_3_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_ppred_busy_0 = io_wakeup_ports_3_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_stale_pdst_0 = io_wakeup_ports_3_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_exception_0 = io_wakeup_ports_3_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_3_bits_uop_exc_cause_0 = io_wakeup_ports_3_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_mem_cmd_0 = io_wakeup_ports_3_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_mem_size_0 = io_wakeup_ports_3_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_mem_signed_0 = io_wakeup_ports_3_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_uses_ldq_0 = io_wakeup_ports_3_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_uses_stq_0 = io_wakeup_ports_3_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_unique_0 = io_wakeup_ports_3_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_flush_on_commit_0 = io_wakeup_ports_3_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_csr_cmd_0 = io_wakeup_ports_3_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_3_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_ldst_0 = io_wakeup_ports_3_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs1_0 = io_wakeup_ports_3_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs2_0 = io_wakeup_ports_3_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs3_0 = io_wakeup_ports_3_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_dst_rtype_0 = io_wakeup_ports_3_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype_0 = io_wakeup_ports_3_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype_0 = io_wakeup_ports_3_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_frs3_en_0 = io_wakeup_ports_3_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fcn_dw_0 = io_wakeup_ports_3_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_fcn_op_0 = io_wakeup_ports_3_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_val_0 = io_wakeup_ports_3_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_fp_rm_0 = io_wakeup_ports_3_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_typ_0 = io_wakeup_ports_3_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_3_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_bp_debug_if_0 = io_wakeup_ports_3_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_3_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc_0 = io_wakeup_ports_3_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc_0 = io_wakeup_ports_3_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_valid_0 = io_wakeup_ports_4_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_4_bits_uop_inst_0 = io_wakeup_ports_4_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_4_bits_uop_debug_inst_0 = io_wakeup_ports_4_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_rvc_0 = io_wakeup_ports_4_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_4_bits_uop_debug_pc_0 = io_wakeup_ports_4_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iq_type_0_0 = io_wakeup_ports_4_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iq_type_1_0 = io_wakeup_ports_4_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iq_type_2_0 = io_wakeup_ports_4_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iq_type_3_0 = io_wakeup_ports_4_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_0_0 = io_wakeup_ports_4_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_1_0 = io_wakeup_ports_4_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_2_0 = io_wakeup_ports_4_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_3_0 = io_wakeup_ports_4_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_4_0 = io_wakeup_ports_4_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_5_0 = io_wakeup_ports_4_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_6_0 = io_wakeup_ports_4_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_7_0 = io_wakeup_ports_4_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_8_0 = io_wakeup_ports_4_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_9_0 = io_wakeup_ports_4_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_issued_0 = io_wakeup_ports_4_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_4_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_4_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_dis_col_sel_0 = io_wakeup_ports_4_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_4_bits_uop_br_mask_0 = io_wakeup_ports_4_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_4_bits_uop_br_tag_0 = io_wakeup_ports_4_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_4_bits_uop_br_type_0 = io_wakeup_ports_4_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_sfb_0 = io_wakeup_ports_4_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_fence_0 = io_wakeup_ports_4_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_fencei_0 = io_wakeup_ports_4_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_sfence_0 = io_wakeup_ports_4_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_amo_0 = io_wakeup_ports_4_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_eret_0 = io_wakeup_ports_4_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_4_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_rocc_0 = io_wakeup_ports_4_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_mov_0 = io_wakeup_ports_4_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_ftq_idx_0 = io_wakeup_ports_4_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_edge_inst_0 = io_wakeup_ports_4_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_pc_lob_0 = io_wakeup_ports_4_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_taken_0 = io_wakeup_ports_4_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_imm_rename_0 = io_wakeup_ports_4_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_imm_sel_0 = io_wakeup_ports_4_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_pimm_0 = io_wakeup_ports_4_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_4_bits_uop_imm_packed_0 = io_wakeup_ports_4_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_op1_sel_0 = io_wakeup_ports_4_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_op2_sel_0 = io_wakeup_ports_4_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_rob_idx_0 = io_wakeup_ports_4_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_ldq_idx_0 = io_wakeup_ports_4_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_stq_idx_0 = io_wakeup_ports_4_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_rxq_idx_0 = io_wakeup_ports_4_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_pdst_0 = io_wakeup_ports_4_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_prs1_0 = io_wakeup_ports_4_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_prs2_0 = io_wakeup_ports_4_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_prs3_0 = io_wakeup_ports_4_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_ppred_0 = io_wakeup_ports_4_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_prs1_busy_0 = io_wakeup_ports_4_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_prs2_busy_0 = io_wakeup_ports_4_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_prs3_busy_0 = io_wakeup_ports_4_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_ppred_busy_0 = io_wakeup_ports_4_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_stale_pdst_0 = io_wakeup_ports_4_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_exception_0 = io_wakeup_ports_4_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_4_bits_uop_exc_cause_0 = io_wakeup_ports_4_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_mem_cmd_0 = io_wakeup_ports_4_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_mem_size_0 = io_wakeup_ports_4_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_mem_signed_0 = io_wakeup_ports_4_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_uses_ldq_0 = io_wakeup_ports_4_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_uses_stq_0 = io_wakeup_ports_4_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_unique_0 = io_wakeup_ports_4_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_flush_on_commit_0 = io_wakeup_ports_4_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_csr_cmd_0 = io_wakeup_ports_4_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_4_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_ldst_0 = io_wakeup_ports_4_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_lrs1_0 = io_wakeup_ports_4_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_lrs2_0 = io_wakeup_ports_4_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_lrs3_0 = io_wakeup_ports_4_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_dst_rtype_0 = io_wakeup_ports_4_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_lrs1_rtype_0 = io_wakeup_ports_4_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_lrs2_rtype_0 = io_wakeup_ports_4_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_frs3_en_0 = io_wakeup_ports_4_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fcn_dw_0 = io_wakeup_ports_4_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_fcn_op_0 = io_wakeup_ports_4_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_val_0 = io_wakeup_ports_4_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_fp_rm_0 = io_wakeup_ports_4_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_fp_typ_0 = io_wakeup_ports_4_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_4_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_4_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_4_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_bp_debug_if_0 = io_wakeup_ports_4_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_4_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_debug_fsrc_0 = io_wakeup_ports_4_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_debug_tsrc_0 = io_wakeup_ports_4_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_pred_wakeup_port_valid_0 = io_pred_wakeup_port_valid; // @[issue-slot.scala:49:7] wire [4:0] io_pred_wakeup_port_bits_0 = io_pred_wakeup_port_bits; // @[issue-slot.scala:49:7] wire [2:0] io_child_rebusys_0 = io_child_rebusys; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire next_uop_out_iw_issued_partial_agen = 1'h0; // @[util.scala:104:23] wire next_uop_out_iw_issued_partial_dgen = 1'h0; // @[util.scala:104:23] wire next_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:59:28] wire next_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:59:28] wire prs1_rebusys_1 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_2 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_3 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_4 = 1'h0; // @[issue-slot.scala:102:91] wire prs2_rebusys_1 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_2 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_3 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_4 = 1'h0; // @[issue-slot.scala:103:91] wire _next_uop_iw_p1_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _next_uop_iw_p2_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _next_uop_iw_p3_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _iss_ready_T_6 = 1'h0; // @[issue-slot.scala:136:131] wire agen_ready = 1'h0; // @[issue-slot.scala:137:114] wire dgen_ready = 1'h0; // @[issue-slot.scala:138:114] wire [2:0] io_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-slot.scala:49:7] wire [2:0] _next_uop_iw_p1_speculative_child_T_1 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _next_uop_iw_p2_speculative_child_T_1 = 3'h0; // @[Mux.scala:30:73] wire io_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire _iss_ready_T_7 = 1'h1; // @[issue-slot.scala:136:110] wire [2:0] io_wakeup_ports_2_bits_speculative_mask = 3'h1; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_speculative_mask = 3'h2; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_speculative_mask = 3'h4; // @[issue-slot.scala:49:7] wire _io_will_be_valid_T_1; // @[issue-slot.scala:65:34] wire _io_request_T_4; // @[issue-slot.scala:140:51] wire [31:0] next_uop_inst; // @[issue-slot.scala:59:28] wire [31:0] next_uop_debug_inst; // @[issue-slot.scala:59:28] wire next_uop_is_rvc; // @[issue-slot.scala:59:28] wire [39:0] next_uop_debug_pc; // @[issue-slot.scala:59:28] wire next_uop_iq_type_0; // @[issue-slot.scala:59:28] wire next_uop_iq_type_1; // @[issue-slot.scala:59:28] wire next_uop_iq_type_2; // @[issue-slot.scala:59:28] wire next_uop_iq_type_3; // @[issue-slot.scala:59:28] wire next_uop_fu_code_0; // @[issue-slot.scala:59:28] wire next_uop_fu_code_1; // @[issue-slot.scala:59:28] wire next_uop_fu_code_2; // @[issue-slot.scala:59:28] wire next_uop_fu_code_3; // @[issue-slot.scala:59:28] wire next_uop_fu_code_4; // @[issue-slot.scala:59:28] wire next_uop_fu_code_5; // @[issue-slot.scala:59:28] wire next_uop_fu_code_6; // @[issue-slot.scala:59:28] wire next_uop_fu_code_7; // @[issue-slot.scala:59:28] wire next_uop_fu_code_8; // @[issue-slot.scala:59:28] wire next_uop_fu_code_9; // @[issue-slot.scala:59:28] wire next_uop_iw_issued; // @[issue-slot.scala:59:28] wire [2:0] next_uop_iw_p1_speculative_child; // @[issue-slot.scala:59:28] wire [2:0] next_uop_iw_p2_speculative_child; // @[issue-slot.scala:59:28] wire next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:59:28] wire next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:59:28] wire next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:59:28] wire [2:0] next_uop_dis_col_sel; // @[issue-slot.scala:59:28] wire [15:0] next_uop_br_mask; // @[issue-slot.scala:59:28] wire [3:0] next_uop_br_tag; // @[issue-slot.scala:59:28] wire [3:0] next_uop_br_type; // @[issue-slot.scala:59:28] wire next_uop_is_sfb; // @[issue-slot.scala:59:28] wire next_uop_is_fence; // @[issue-slot.scala:59:28] wire next_uop_is_fencei; // @[issue-slot.scala:59:28] wire next_uop_is_sfence; // @[issue-slot.scala:59:28] wire next_uop_is_amo; // @[issue-slot.scala:59:28] wire next_uop_is_eret; // @[issue-slot.scala:59:28] wire next_uop_is_sys_pc2epc; // @[issue-slot.scala:59:28] wire next_uop_is_rocc; // @[issue-slot.scala:59:28] wire next_uop_is_mov; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ftq_idx; // @[issue-slot.scala:59:28] wire next_uop_edge_inst; // @[issue-slot.scala:59:28] wire [5:0] next_uop_pc_lob; // @[issue-slot.scala:59:28] wire next_uop_taken; // @[issue-slot.scala:59:28] wire next_uop_imm_rename; // @[issue-slot.scala:59:28] wire [2:0] next_uop_imm_sel; // @[issue-slot.scala:59:28] wire [4:0] next_uop_pimm; // @[issue-slot.scala:59:28] wire [19:0] next_uop_imm_packed; // @[issue-slot.scala:59:28] wire [1:0] next_uop_op1_sel; // @[issue-slot.scala:59:28] wire [2:0] next_uop_op2_sel; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ldst; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_wen; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren1; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren2; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren3; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_swap12; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_swap23; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fromint; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_toint; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fma; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_div; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_wflags; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_vec; // @[issue-slot.scala:59:28] wire [6:0] next_uop_rob_idx; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ldq_idx; // @[issue-slot.scala:59:28] wire [4:0] next_uop_stq_idx; // @[issue-slot.scala:59:28] wire [1:0] next_uop_rxq_idx; // @[issue-slot.scala:59:28] wire [6:0] next_uop_pdst; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs1; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs2; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs3; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ppred; // @[issue-slot.scala:59:28] wire next_uop_prs1_busy; // @[issue-slot.scala:59:28] wire next_uop_prs2_busy; // @[issue-slot.scala:59:28] wire next_uop_prs3_busy; // @[issue-slot.scala:59:28] wire next_uop_ppred_busy; // @[issue-slot.scala:59:28] wire [6:0] next_uop_stale_pdst; // @[issue-slot.scala:59:28] wire next_uop_exception; // @[issue-slot.scala:59:28] wire [63:0] next_uop_exc_cause; // @[issue-slot.scala:59:28] wire [4:0] next_uop_mem_cmd; // @[issue-slot.scala:59:28] wire [1:0] next_uop_mem_size; // @[issue-slot.scala:59:28] wire next_uop_mem_signed; // @[issue-slot.scala:59:28] wire next_uop_uses_ldq; // @[issue-slot.scala:59:28] wire next_uop_uses_stq; // @[issue-slot.scala:59:28] wire next_uop_is_unique; // @[issue-slot.scala:59:28] wire next_uop_flush_on_commit; // @[issue-slot.scala:59:28] wire [2:0] next_uop_csr_cmd; // @[issue-slot.scala:59:28] wire next_uop_ldst_is_rs1; // @[issue-slot.scala:59:28] wire [5:0] next_uop_ldst; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs1; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs2; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs3; // @[issue-slot.scala:59:28] wire [1:0] next_uop_dst_rtype; // @[issue-slot.scala:59:28] wire [1:0] next_uop_lrs1_rtype; // @[issue-slot.scala:59:28] wire [1:0] next_uop_lrs2_rtype; // @[issue-slot.scala:59:28] wire next_uop_frs3_en; // @[issue-slot.scala:59:28] wire next_uop_fcn_dw; // @[issue-slot.scala:59:28] wire [4:0] next_uop_fcn_op; // @[issue-slot.scala:59:28] wire next_uop_fp_val; // @[issue-slot.scala:59:28] wire [2:0] next_uop_fp_rm; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_typ; // @[issue-slot.scala:59:28] wire next_uop_xcpt_pf_if; // @[issue-slot.scala:59:28] wire next_uop_xcpt_ae_if; // @[issue-slot.scala:59:28] wire next_uop_xcpt_ma_if; // @[issue-slot.scala:59:28] wire next_uop_bp_debug_if; // @[issue-slot.scala:59:28] wire next_uop_bp_xcpt_if; // @[issue-slot.scala:59:28] wire [2:0] next_uop_debug_fsrc; // @[issue-slot.scala:59:28] wire [2:0] next_uop_debug_tsrc; // @[issue-slot.scala:59:28] wire io_iss_uop_iq_type_0_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_0_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_4_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_5_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_6_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_7_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_8_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_9_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7] wire [31:0] io_iss_uop_inst_0; // @[issue-slot.scala:49:7] wire [31:0] io_iss_uop_debug_inst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_rvc_0; // @[issue-slot.scala:49:7] wire [39:0] io_iss_uop_debug_pc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_dis_col_sel_0; // @[issue-slot.scala:49:7] wire [15:0] io_iss_uop_br_mask_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_br_tag_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_br_type_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sfb_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_fence_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_fencei_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sfence_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_amo_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_eret_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_rocc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_mov_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ftq_idx_0; // @[issue-slot.scala:49:7] wire io_iss_uop_edge_inst_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_pc_lob_0; // @[issue-slot.scala:49:7] wire io_iss_uop_taken_0; // @[issue-slot.scala:49:7] wire io_iss_uop_imm_rename_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_imm_sel_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_pimm_0; // @[issue-slot.scala:49:7] wire [19:0] io_iss_uop_imm_packed_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_op1_sel_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_op2_sel_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_rob_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ldq_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_stq_idx_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_rxq_idx_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_pdst_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs1_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs2_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs3_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ppred_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs1_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs2_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs3_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_ppred_busy_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_stale_pdst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_exception_0; // @[issue-slot.scala:49:7] wire [63:0] io_iss_uop_exc_cause_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_mem_cmd_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_mem_size_0; // @[issue-slot.scala:49:7] wire io_iss_uop_mem_signed_0; // @[issue-slot.scala:49:7] wire io_iss_uop_uses_ldq_0; // @[issue-slot.scala:49:7] wire io_iss_uop_uses_stq_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_unique_0; // @[issue-slot.scala:49:7] wire io_iss_uop_flush_on_commit_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_csr_cmd_0; // @[issue-slot.scala:49:7] wire io_iss_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_ldst_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs2_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs3_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_dst_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7] wire io_iss_uop_frs3_en_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fcn_dw_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_fcn_op_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_val_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_fp_rm_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_typ_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_bp_debug_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_debug_fsrc_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_debug_tsrc_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_0_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_1_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_2_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_0_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_1_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_2_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_4_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_5_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_6_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_7_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_8_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_9_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:49:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:49:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_dis_col_sel_0; // @[issue-slot.scala:49:7] wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_br_type_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sfence_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_eret_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_rocc_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_mov_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:49:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:49:7] wire io_out_uop_taken_0; // @[issue-slot.scala:49:7] wire io_out_uop_imm_rename_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_imm_sel_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_pimm_0; // @[issue-slot.scala:49:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_op1_sel_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_op2_sel_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:49:7] wire io_out_uop_exception_0; // @[issue-slot.scala:49:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:49:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:49:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:49:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:49:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_csr_cmd_0; // @[issue-slot.scala:49:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:49:7] wire io_out_uop_fcn_dw_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_fcn_op_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_fp_rm_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_typ_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:49:7] wire io_valid_0; // @[issue-slot.scala:49:7] wire io_will_be_valid_0; // @[issue-slot.scala:49:7] wire io_request_0; // @[issue-slot.scala:49:7] reg slot_valid; // @[issue-slot.scala:55:27] assign io_valid_0 = slot_valid; // @[issue-slot.scala:49:7, :55:27] reg [31:0] slot_uop_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:49:7, :56:21] wire [31:0] next_uop_out_inst = slot_uop_inst; // @[util.scala:104:23] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:49:7, :56:21] wire [31:0] next_uop_out_debug_inst = slot_uop_debug_inst; // @[util.scala:104:23] reg slot_uop_is_rvc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_rvc = slot_uop_is_rvc; // @[util.scala:104:23] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:49:7, :56:21] wire [39:0] next_uop_out_debug_pc = slot_uop_debug_pc; // @[util.scala:104:23] reg slot_uop_iq_type_0; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_0_0 = slot_uop_iq_type_0; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_0 = slot_uop_iq_type_0; // @[util.scala:104:23] reg slot_uop_iq_type_1; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_1_0 = slot_uop_iq_type_1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_1 = slot_uop_iq_type_1; // @[util.scala:104:23] reg slot_uop_iq_type_2; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_2_0 = slot_uop_iq_type_2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_2 = slot_uop_iq_type_2; // @[util.scala:104:23] reg slot_uop_iq_type_3; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_3_0 = slot_uop_iq_type_3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_3 = slot_uop_iq_type_3; // @[util.scala:104:23] reg slot_uop_fu_code_0; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_0_0 = slot_uop_fu_code_0; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_0 = slot_uop_fu_code_0; // @[util.scala:104:23] reg slot_uop_fu_code_1; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_1_0 = slot_uop_fu_code_1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_1 = slot_uop_fu_code_1; // @[util.scala:104:23] reg slot_uop_fu_code_2; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_2_0 = slot_uop_fu_code_2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_2 = slot_uop_fu_code_2; // @[util.scala:104:23] reg slot_uop_fu_code_3; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_3_0 = slot_uop_fu_code_3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_3 = slot_uop_fu_code_3; // @[util.scala:104:23] reg slot_uop_fu_code_4; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_4_0 = slot_uop_fu_code_4; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_4 = slot_uop_fu_code_4; // @[util.scala:104:23] reg slot_uop_fu_code_5; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_5_0 = slot_uop_fu_code_5; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_5 = slot_uop_fu_code_5; // @[util.scala:104:23] reg slot_uop_fu_code_6; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_6_0 = slot_uop_fu_code_6; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_6 = slot_uop_fu_code_6; // @[util.scala:104:23] reg slot_uop_fu_code_7; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_7_0 = slot_uop_fu_code_7; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_7 = slot_uop_fu_code_7; // @[util.scala:104:23] reg slot_uop_fu_code_8; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_8_0 = slot_uop_fu_code_8; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_8 = slot_uop_fu_code_8; // @[util.scala:104:23] reg slot_uop_fu_code_9; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_9_0 = slot_uop_fu_code_9; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_9 = slot_uop_fu_code_9; // @[util.scala:104:23] reg slot_uop_iw_issued; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_issued_0 = slot_uop_iw_issued; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_issued = slot_uop_iw_issued; // @[util.scala:104:23] reg [2:0] slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p1_speculative_child_0 = slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_iw_p1_speculative_child = slot_uop_iw_p1_speculative_child; // @[util.scala:104:23] reg [2:0] slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p2_speculative_child_0 = slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_iw_p2_speculative_child = slot_uop_iw_p2_speculative_child; // @[util.scala:104:23] reg slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p1_bypass_hint_0 = slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p1_bypass_hint = slot_uop_iw_p1_bypass_hint; // @[util.scala:104:23] reg slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p2_bypass_hint_0 = slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p2_bypass_hint = slot_uop_iw_p2_bypass_hint; // @[util.scala:104:23] reg slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p3_bypass_hint_0 = slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p3_bypass_hint = slot_uop_iw_p3_bypass_hint; // @[util.scala:104:23] reg [2:0] slot_uop_dis_col_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_dis_col_sel_0 = slot_uop_dis_col_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_dis_col_sel = slot_uop_dis_col_sel; // @[util.scala:104:23] reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:56:21] assign io_iss_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:49:7, :56:21] reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:56:21] assign io_iss_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_br_tag = slot_uop_br_tag; // @[util.scala:104:23] reg [3:0] slot_uop_br_type; // @[issue-slot.scala:56:21] assign io_iss_uop_br_type_0 = slot_uop_br_type; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_br_type = slot_uop_br_type; // @[util.scala:104:23] reg slot_uop_is_sfb; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sfb = slot_uop_is_sfb; // @[util.scala:104:23] reg slot_uop_is_fence; // @[issue-slot.scala:56:21] assign io_iss_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_fence = slot_uop_is_fence; // @[util.scala:104:23] reg slot_uop_is_fencei; // @[issue-slot.scala:56:21] assign io_iss_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_fencei = slot_uop_is_fencei; // @[util.scala:104:23] reg slot_uop_is_sfence; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sfence_0 = slot_uop_is_sfence; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sfence = slot_uop_is_sfence; // @[util.scala:104:23] reg slot_uop_is_amo; // @[issue-slot.scala:56:21] assign io_iss_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_amo = slot_uop_is_amo; // @[util.scala:104:23] reg slot_uop_is_eret; // @[issue-slot.scala:56:21] assign io_iss_uop_is_eret_0 = slot_uop_is_eret; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_eret = slot_uop_is_eret; // @[util.scala:104:23] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sys_pc2epc = slot_uop_is_sys_pc2epc; // @[util.scala:104:23] reg slot_uop_is_rocc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_rocc_0 = slot_uop_is_rocc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_rocc = slot_uop_is_rocc; // @[util.scala:104:23] reg slot_uop_is_mov; // @[issue-slot.scala:56:21] assign io_iss_uop_is_mov_0 = slot_uop_is_mov; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_mov = slot_uop_is_mov; // @[util.scala:104:23] reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ftq_idx = slot_uop_ftq_idx; // @[util.scala:104:23] reg slot_uop_edge_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_edge_inst = slot_uop_edge_inst; // @[util.scala:104:23] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:56:21] assign io_iss_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_pc_lob = slot_uop_pc_lob; // @[util.scala:104:23] reg slot_uop_taken; // @[issue-slot.scala:56:21] assign io_iss_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_taken = slot_uop_taken; // @[util.scala:104:23] reg slot_uop_imm_rename; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_rename_0 = slot_uop_imm_rename; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_imm_rename = slot_uop_imm_rename; // @[util.scala:104:23] reg [2:0] slot_uop_imm_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_sel_0 = slot_uop_imm_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_imm_sel = slot_uop_imm_sel; // @[util.scala:104:23] reg [4:0] slot_uop_pimm; // @[issue-slot.scala:56:21] assign io_iss_uop_pimm_0 = slot_uop_pimm; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_pimm = slot_uop_pimm; // @[util.scala:104:23] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:49:7, :56:21] wire [19:0] next_uop_out_imm_packed = slot_uop_imm_packed; // @[util.scala:104:23] reg [1:0] slot_uop_op1_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_op1_sel_0 = slot_uop_op1_sel; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_op1_sel = slot_uop_op1_sel; // @[util.scala:104:23] reg [2:0] slot_uop_op2_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_op2_sel_0 = slot_uop_op2_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_op2_sel = slot_uop_op2_sel; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ldst_0 = slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ldst = slot_uop_fp_ctrl_ldst; // @[util.scala:104:23] reg slot_uop_fp_ctrl_wen; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_wen_0 = slot_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_wen = slot_uop_fp_ctrl_wen; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren1_0 = slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren1 = slot_uop_fp_ctrl_ren1; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren2_0 = slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren2 = slot_uop_fp_ctrl_ren2; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren3_0 = slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren3 = slot_uop_fp_ctrl_ren3; // @[util.scala:104:23] reg slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_swap12_0 = slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_swap12 = slot_uop_fp_ctrl_swap12; // @[util.scala:104:23] reg slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_swap23_0 = slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_swap23 = slot_uop_fp_ctrl_swap23; // @[util.scala:104:23] reg [1:0] slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_typeTagIn_0 = slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_ctrl_typeTagIn = slot_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23] reg [1:0] slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_typeTagOut_0 = slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_ctrl_typeTagOut = slot_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fromint_0 = slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fromint = slot_uop_fp_ctrl_fromint; // @[util.scala:104:23] reg slot_uop_fp_ctrl_toint; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_toint_0 = slot_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_toint = slot_uop_fp_ctrl_toint; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fastpipe_0 = slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fastpipe = slot_uop_fp_ctrl_fastpipe; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fma; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fma_0 = slot_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fma = slot_uop_fp_ctrl_fma; // @[util.scala:104:23] reg slot_uop_fp_ctrl_div; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_div_0 = slot_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_div = slot_uop_fp_ctrl_div; // @[util.scala:104:23] reg slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_sqrt_0 = slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_sqrt = slot_uop_fp_ctrl_sqrt; // @[util.scala:104:23] reg slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_wflags_0 = slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_wflags = slot_uop_fp_ctrl_wflags; // @[util.scala:104:23] reg slot_uop_fp_ctrl_vec; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_vec_0 = slot_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_vec = slot_uop_fp_ctrl_vec; // @[util.scala:104:23] reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_rob_idx = slot_uop_rob_idx; // @[util.scala:104:23] reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ldq_idx = slot_uop_ldq_idx; // @[util.scala:104:23] reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_stq_idx = slot_uop_stq_idx; // @[util.scala:104:23] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_rxq_idx = slot_uop_rxq_idx; // @[util.scala:104:23] reg [6:0] slot_uop_pdst; // @[issue-slot.scala:56:21] assign io_iss_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_pdst = slot_uop_pdst; // @[util.scala:104:23] reg [6:0] slot_uop_prs1; // @[issue-slot.scala:56:21] assign io_iss_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs1 = slot_uop_prs1; // @[util.scala:104:23] reg [6:0] slot_uop_prs2; // @[issue-slot.scala:56:21] assign io_iss_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs2 = slot_uop_prs2; // @[util.scala:104:23] reg [6:0] slot_uop_prs3; // @[issue-slot.scala:56:21] assign io_iss_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs3 = slot_uop_prs3; // @[util.scala:104:23] reg [4:0] slot_uop_ppred; // @[issue-slot.scala:56:21] assign io_iss_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ppred = slot_uop_ppred; // @[util.scala:104:23] reg slot_uop_prs1_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs1_busy = slot_uop_prs1_busy; // @[util.scala:104:23] reg slot_uop_prs2_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs2_busy = slot_uop_prs2_busy; // @[util.scala:104:23] reg slot_uop_prs3_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs3_busy = slot_uop_prs3_busy; // @[util.scala:104:23] reg slot_uop_ppred_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_ppred_busy = slot_uop_ppred_busy; // @[util.scala:104:23] wire _iss_ready_T_3 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :136:88] wire _agen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :137:95] wire _dgen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :138:95] reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:56:21] assign io_iss_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_stale_pdst = slot_uop_stale_pdst; // @[util.scala:104:23] reg slot_uop_exception; // @[issue-slot.scala:56:21] assign io_iss_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_exception = slot_uop_exception; // @[util.scala:104:23] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:56:21] assign io_iss_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:49:7, :56:21] wire [63:0] next_uop_out_exc_cause = slot_uop_exc_cause; // @[util.scala:104:23] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_mem_cmd = slot_uop_mem_cmd; // @[util.scala:104:23] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_mem_size = slot_uop_mem_size; // @[util.scala:104:23] reg slot_uop_mem_signed; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_mem_signed = slot_uop_mem_signed; // @[util.scala:104:23] reg slot_uop_uses_ldq; // @[issue-slot.scala:56:21] assign io_iss_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_uses_ldq = slot_uop_uses_ldq; // @[util.scala:104:23] reg slot_uop_uses_stq; // @[issue-slot.scala:56:21] assign io_iss_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_uses_stq = slot_uop_uses_stq; // @[util.scala:104:23] reg slot_uop_is_unique; // @[issue-slot.scala:56:21] assign io_iss_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_unique = slot_uop_is_unique; // @[util.scala:104:23] reg slot_uop_flush_on_commit; // @[issue-slot.scala:56:21] assign io_iss_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_flush_on_commit = slot_uop_flush_on_commit; // @[util.scala:104:23] reg [2:0] slot_uop_csr_cmd; // @[issue-slot.scala:56:21] assign io_iss_uop_csr_cmd_0 = slot_uop_csr_cmd; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_csr_cmd = slot_uop_csr_cmd; // @[util.scala:104:23] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:56:21] assign io_iss_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_ldst_is_rs1 = slot_uop_ldst_is_rs1; // @[util.scala:104:23] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:56:21] assign io_iss_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_ldst = slot_uop_ldst; // @[util.scala:104:23] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs1 = slot_uop_lrs1; // @[util.scala:104:23] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs2 = slot_uop_lrs2; // @[util.scala:104:23] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs3 = slot_uop_lrs3; // @[util.scala:104:23] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_dst_rtype = slot_uop_dst_rtype; // @[util.scala:104:23] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs1_rtype_0 = slot_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_lrs1_rtype = slot_uop_lrs1_rtype; // @[util.scala:104:23] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs2_rtype_0 = slot_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_lrs2_rtype = slot_uop_lrs2_rtype; // @[util.scala:104:23] reg slot_uop_frs3_en; // @[issue-slot.scala:56:21] assign io_iss_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_frs3_en = slot_uop_frs3_en; // @[util.scala:104:23] reg slot_uop_fcn_dw; // @[issue-slot.scala:56:21] assign io_iss_uop_fcn_dw_0 = slot_uop_fcn_dw; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fcn_dw = slot_uop_fcn_dw; // @[util.scala:104:23] reg [4:0] slot_uop_fcn_op; // @[issue-slot.scala:56:21] assign io_iss_uop_fcn_op_0 = slot_uop_fcn_op; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_fcn_op = slot_uop_fcn_op; // @[util.scala:104:23] reg slot_uop_fp_val; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_val = slot_uop_fp_val; // @[util.scala:104:23] reg [2:0] slot_uop_fp_rm; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_rm_0 = slot_uop_fp_rm; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_fp_rm = slot_uop_fp_rm; // @[util.scala:104:23] reg [1:0] slot_uop_fp_typ; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_typ_0 = slot_uop_fp_typ; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_typ = slot_uop_fp_typ; // @[util.scala:104:23] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_pf_if = slot_uop_xcpt_pf_if; // @[util.scala:104:23] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_ae_if = slot_uop_xcpt_ae_if; // @[util.scala:104:23] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_ma_if = slot_uop_xcpt_ma_if; // @[util.scala:104:23] reg slot_uop_bp_debug_if; // @[issue-slot.scala:56:21] assign io_iss_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_bp_debug_if = slot_uop_bp_debug_if; // @[util.scala:104:23] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:56:21] assign io_iss_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_bp_xcpt_if = slot_uop_bp_xcpt_if; // @[util.scala:104:23] reg [2:0] slot_uop_debug_fsrc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_debug_fsrc = slot_uop_debug_fsrc; // @[util.scala:104:23] reg [2:0] slot_uop_debug_tsrc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_debug_tsrc = slot_uop_debug_tsrc; // @[util.scala:104:23] wire next_valid; // @[issue-slot.scala:58:28] assign next_uop_inst = next_uop_out_inst; // @[util.scala:104:23] assign next_uop_debug_inst = next_uop_out_debug_inst; // @[util.scala:104:23] assign next_uop_is_rvc = next_uop_out_is_rvc; // @[util.scala:104:23] assign next_uop_debug_pc = next_uop_out_debug_pc; // @[util.scala:104:23] assign next_uop_iq_type_0 = next_uop_out_iq_type_0; // @[util.scala:104:23] assign next_uop_iq_type_1 = next_uop_out_iq_type_1; // @[util.scala:104:23] assign next_uop_iq_type_2 = next_uop_out_iq_type_2; // @[util.scala:104:23] assign next_uop_iq_type_3 = next_uop_out_iq_type_3; // @[util.scala:104:23] assign next_uop_fu_code_0 = next_uop_out_fu_code_0; // @[util.scala:104:23] assign next_uop_fu_code_1 = next_uop_out_fu_code_1; // @[util.scala:104:23] assign next_uop_fu_code_2 = next_uop_out_fu_code_2; // @[util.scala:104:23] assign next_uop_fu_code_3 = next_uop_out_fu_code_3; // @[util.scala:104:23] assign next_uop_fu_code_4 = next_uop_out_fu_code_4; // @[util.scala:104:23] assign next_uop_fu_code_5 = next_uop_out_fu_code_5; // @[util.scala:104:23] assign next_uop_fu_code_6 = next_uop_out_fu_code_6; // @[util.scala:104:23] assign next_uop_fu_code_7 = next_uop_out_fu_code_7; // @[util.scala:104:23] assign next_uop_fu_code_8 = next_uop_out_fu_code_8; // @[util.scala:104:23] assign next_uop_fu_code_9 = next_uop_out_fu_code_9; // @[util.scala:104:23] wire [15:0] _next_uop_out_br_mask_T_1; // @[util.scala:93:25] assign next_uop_dis_col_sel = next_uop_out_dis_col_sel; // @[util.scala:104:23] assign next_uop_br_mask = next_uop_out_br_mask; // @[util.scala:104:23] assign next_uop_br_tag = next_uop_out_br_tag; // @[util.scala:104:23] assign next_uop_br_type = next_uop_out_br_type; // @[util.scala:104:23] assign next_uop_is_sfb = next_uop_out_is_sfb; // @[util.scala:104:23] assign next_uop_is_fence = next_uop_out_is_fence; // @[util.scala:104:23] assign next_uop_is_fencei = next_uop_out_is_fencei; // @[util.scala:104:23] assign next_uop_is_sfence = next_uop_out_is_sfence; // @[util.scala:104:23] assign next_uop_is_amo = next_uop_out_is_amo; // @[util.scala:104:23] assign next_uop_is_eret = next_uop_out_is_eret; // @[util.scala:104:23] assign next_uop_is_sys_pc2epc = next_uop_out_is_sys_pc2epc; // @[util.scala:104:23] assign next_uop_is_rocc = next_uop_out_is_rocc; // @[util.scala:104:23] assign next_uop_is_mov = next_uop_out_is_mov; // @[util.scala:104:23] assign next_uop_ftq_idx = next_uop_out_ftq_idx; // @[util.scala:104:23] assign next_uop_edge_inst = next_uop_out_edge_inst; // @[util.scala:104:23] assign next_uop_pc_lob = next_uop_out_pc_lob; // @[util.scala:104:23] assign next_uop_taken = next_uop_out_taken; // @[util.scala:104:23] assign next_uop_imm_rename = next_uop_out_imm_rename; // @[util.scala:104:23] assign next_uop_imm_sel = next_uop_out_imm_sel; // @[util.scala:104:23] assign next_uop_pimm = next_uop_out_pimm; // @[util.scala:104:23] assign next_uop_imm_packed = next_uop_out_imm_packed; // @[util.scala:104:23] assign next_uop_op1_sel = next_uop_out_op1_sel; // @[util.scala:104:23] assign next_uop_op2_sel = next_uop_out_op2_sel; // @[util.scala:104:23] assign next_uop_fp_ctrl_ldst = next_uop_out_fp_ctrl_ldst; // @[util.scala:104:23] assign next_uop_fp_ctrl_wen = next_uop_out_fp_ctrl_wen; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren1 = next_uop_out_fp_ctrl_ren1; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren2 = next_uop_out_fp_ctrl_ren2; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren3 = next_uop_out_fp_ctrl_ren3; // @[util.scala:104:23] assign next_uop_fp_ctrl_swap12 = next_uop_out_fp_ctrl_swap12; // @[util.scala:104:23] assign next_uop_fp_ctrl_swap23 = next_uop_out_fp_ctrl_swap23; // @[util.scala:104:23] assign next_uop_fp_ctrl_typeTagIn = next_uop_out_fp_ctrl_typeTagIn; // @[util.scala:104:23] assign next_uop_fp_ctrl_typeTagOut = next_uop_out_fp_ctrl_typeTagOut; // @[util.scala:104:23] assign next_uop_fp_ctrl_fromint = next_uop_out_fp_ctrl_fromint; // @[util.scala:104:23] assign next_uop_fp_ctrl_toint = next_uop_out_fp_ctrl_toint; // @[util.scala:104:23] assign next_uop_fp_ctrl_fastpipe = next_uop_out_fp_ctrl_fastpipe; // @[util.scala:104:23] assign next_uop_fp_ctrl_fma = next_uop_out_fp_ctrl_fma; // @[util.scala:104:23] assign next_uop_fp_ctrl_div = next_uop_out_fp_ctrl_div; // @[util.scala:104:23] assign next_uop_fp_ctrl_sqrt = next_uop_out_fp_ctrl_sqrt; // @[util.scala:104:23] assign next_uop_fp_ctrl_wflags = next_uop_out_fp_ctrl_wflags; // @[util.scala:104:23] assign next_uop_fp_ctrl_vec = next_uop_out_fp_ctrl_vec; // @[util.scala:104:23] assign next_uop_rob_idx = next_uop_out_rob_idx; // @[util.scala:104:23] assign next_uop_ldq_idx = next_uop_out_ldq_idx; // @[util.scala:104:23] assign next_uop_stq_idx = next_uop_out_stq_idx; // @[util.scala:104:23] assign next_uop_rxq_idx = next_uop_out_rxq_idx; // @[util.scala:104:23] assign next_uop_pdst = next_uop_out_pdst; // @[util.scala:104:23] assign next_uop_prs1 = next_uop_out_prs1; // @[util.scala:104:23] assign next_uop_prs2 = next_uop_out_prs2; // @[util.scala:104:23] assign next_uop_prs3 = next_uop_out_prs3; // @[util.scala:104:23] assign next_uop_ppred = next_uop_out_ppred; // @[util.scala:104:23] assign next_uop_stale_pdst = next_uop_out_stale_pdst; // @[util.scala:104:23] assign next_uop_exception = next_uop_out_exception; // @[util.scala:104:23] assign next_uop_exc_cause = next_uop_out_exc_cause; // @[util.scala:104:23] assign next_uop_mem_cmd = next_uop_out_mem_cmd; // @[util.scala:104:23] assign next_uop_mem_size = next_uop_out_mem_size; // @[util.scala:104:23] assign next_uop_mem_signed = next_uop_out_mem_signed; // @[util.scala:104:23] assign next_uop_uses_ldq = next_uop_out_uses_ldq; // @[util.scala:104:23] assign next_uop_uses_stq = next_uop_out_uses_stq; // @[util.scala:104:23] assign next_uop_is_unique = next_uop_out_is_unique; // @[util.scala:104:23] assign next_uop_flush_on_commit = next_uop_out_flush_on_commit; // @[util.scala:104:23] assign next_uop_csr_cmd = next_uop_out_csr_cmd; // @[util.scala:104:23] assign next_uop_ldst_is_rs1 = next_uop_out_ldst_is_rs1; // @[util.scala:104:23] assign next_uop_ldst = next_uop_out_ldst; // @[util.scala:104:23] assign next_uop_lrs1 = next_uop_out_lrs1; // @[util.scala:104:23] assign next_uop_lrs2 = next_uop_out_lrs2; // @[util.scala:104:23] assign next_uop_lrs3 = next_uop_out_lrs3; // @[util.scala:104:23] assign next_uop_dst_rtype = next_uop_out_dst_rtype; // @[util.scala:104:23] assign next_uop_lrs1_rtype = next_uop_out_lrs1_rtype; // @[util.scala:104:23] assign next_uop_lrs2_rtype = next_uop_out_lrs2_rtype; // @[util.scala:104:23] assign next_uop_frs3_en = next_uop_out_frs3_en; // @[util.scala:104:23] assign next_uop_fcn_dw = next_uop_out_fcn_dw; // @[util.scala:104:23] assign next_uop_fcn_op = next_uop_out_fcn_op; // @[util.scala:104:23] assign next_uop_fp_val = next_uop_out_fp_val; // @[util.scala:104:23] assign next_uop_fp_rm = next_uop_out_fp_rm; // @[util.scala:104:23] assign next_uop_fp_typ = next_uop_out_fp_typ; // @[util.scala:104:23] assign next_uop_xcpt_pf_if = next_uop_out_xcpt_pf_if; // @[util.scala:104:23] assign next_uop_xcpt_ae_if = next_uop_out_xcpt_ae_if; // @[util.scala:104:23] assign next_uop_xcpt_ma_if = next_uop_out_xcpt_ma_if; // @[util.scala:104:23] assign next_uop_bp_debug_if = next_uop_out_bp_debug_if; // @[util.scala:104:23] assign next_uop_bp_xcpt_if = next_uop_out_bp_xcpt_if; // @[util.scala:104:23] assign next_uop_debug_fsrc = next_uop_out_debug_fsrc; // @[util.scala:104:23] assign next_uop_debug_tsrc = next_uop_out_debug_tsrc; // @[util.scala:104:23] wire [15:0] _next_uop_out_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _next_uop_out_br_mask_T_1 = slot_uop_br_mask & _next_uop_out_br_mask_T; // @[util.scala:93:{25,27}] assign next_uop_out_br_mask = _next_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23] assign io_out_uop_inst_0 = next_uop_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_inst_0 = next_uop_debug_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_rvc_0 = next_uop_is_rvc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_pc_0 = next_uop_debug_pc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_0_0 = next_uop_iq_type_0; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_1_0 = next_uop_iq_type_1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_2_0 = next_uop_iq_type_2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_3_0 = next_uop_iq_type_3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_0_0 = next_uop_fu_code_0; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_1_0 = next_uop_fu_code_1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_2_0 = next_uop_fu_code_2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_3_0 = next_uop_fu_code_3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_4_0 = next_uop_fu_code_4; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_5_0 = next_uop_fu_code_5; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_6_0 = next_uop_fu_code_6; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_7_0 = next_uop_fu_code_7; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_8_0 = next_uop_fu_code_8; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_9_0 = next_uop_fu_code_9; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_issued_0 = next_uop_iw_issued; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p1_speculative_child_0 = next_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p2_speculative_child_0 = next_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p1_bypass_hint_0 = next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p2_bypass_hint_0 = next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p3_bypass_hint_0 = next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_dis_col_sel_0 = next_uop_dis_col_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_mask_0 = next_uop_br_mask; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_tag_0 = next_uop_br_tag; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_type_0 = next_uop_br_type; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sfb_0 = next_uop_is_sfb; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_fence_0 = next_uop_is_fence; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_fencei_0 = next_uop_is_fencei; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sfence_0 = next_uop_is_sfence; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_amo_0 = next_uop_is_amo; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_eret_0 = next_uop_is_eret; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sys_pc2epc_0 = next_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_rocc_0 = next_uop_is_rocc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_mov_0 = next_uop_is_mov; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ftq_idx_0 = next_uop_ftq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_edge_inst_0 = next_uop_edge_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pc_lob_0 = next_uop_pc_lob; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_taken_0 = next_uop_taken; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_rename_0 = next_uop_imm_rename; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_sel_0 = next_uop_imm_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pimm_0 = next_uop_pimm; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_packed_0 = next_uop_imm_packed; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_op1_sel_0 = next_uop_op1_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_op2_sel_0 = next_uop_op2_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ldst_0 = next_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_wen_0 = next_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren1_0 = next_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren2_0 = next_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren3_0 = next_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_swap12_0 = next_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_swap23_0 = next_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_typeTagIn_0 = next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_typeTagOut_0 = next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fromint_0 = next_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_toint_0 = next_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fastpipe_0 = next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fma_0 = next_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_div_0 = next_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_sqrt_0 = next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_wflags_0 = next_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_vec_0 = next_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_rob_idx_0 = next_uop_rob_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldq_idx_0 = next_uop_ldq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_stq_idx_0 = next_uop_stq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_rxq_idx_0 = next_uop_rxq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pdst_0 = next_uop_pdst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs1_0 = next_uop_prs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs2_0 = next_uop_prs2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs3_0 = next_uop_prs3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ppred_0 = next_uop_ppred; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs1_busy_0 = next_uop_prs1_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs2_busy_0 = next_uop_prs2_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs3_busy_0 = next_uop_prs3_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ppred_busy_0 = next_uop_ppred_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_stale_pdst_0 = next_uop_stale_pdst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_exception_0 = next_uop_exception; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_exc_cause_0 = next_uop_exc_cause; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_cmd_0 = next_uop_mem_cmd; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_size_0 = next_uop_mem_size; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_signed_0 = next_uop_mem_signed; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_uses_ldq_0 = next_uop_uses_ldq; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_uses_stq_0 = next_uop_uses_stq; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_unique_0 = next_uop_is_unique; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_flush_on_commit_0 = next_uop_flush_on_commit; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_csr_cmd_0 = next_uop_csr_cmd; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldst_is_rs1_0 = next_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldst_0 = next_uop_ldst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs1_0 = next_uop_lrs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs2_0 = next_uop_lrs2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs3_0 = next_uop_lrs3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_dst_rtype_0 = next_uop_dst_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs1_rtype_0 = next_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs2_rtype_0 = next_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_frs3_en_0 = next_uop_frs3_en; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fcn_dw_0 = next_uop_fcn_dw; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fcn_op_0 = next_uop_fcn_op; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_val_0 = next_uop_fp_val; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_rm_0 = next_uop_fp_rm; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_typ_0 = next_uop_fp_typ; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_pf_if_0 = next_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_ae_if_0 = next_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_ma_if_0 = next_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_bp_debug_if_0 = next_uop_bp_debug_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_bp_xcpt_if_0 = next_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_fsrc_0 = next_uop_debug_fsrc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_tsrc_0 = next_uop_debug_tsrc; // @[issue-slot.scala:49:7, :59:28] wire [15:0] _killed_T = io_brupdate_b1_mispredict_mask_0 & slot_uop_br_mask; // @[util.scala:126:51] wire _killed_T_1 = \|_killed_T; // @[util.scala:126:{51,59}] wire killed = _killed_T_1 \| io_kill_0; // @[util.scala:61:61, :126:59] wire _io_will_be_valid_T = ~killed; // @[util.scala:61:61] assign _io_will_be_valid_T_1 = next_valid & _io_will_be_valid_T; // @[issue-slot.scala:58:28, :65:{34,37}] assign io_will_be_valid_0 = _io_will_be_valid_T_1; // @[issue-slot.scala:49:7, :65:34] wire _slot_valid_T = ~killed; // @[util.scala:61:61] wire _slot_valid_T_1 = next_valid & _slot_valid_T; // @[issue-slot.scala:58:28, :74:{30,33}]
Generate the Verilog code corresponding to this FIRRTL code module IssueSlot_101 : input clock : Clock input reset : Reset output io : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, flip grant : UInt<1>, iss_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, flip in_uop : { valid : UInt<1>, bits : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}}, out_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt<21>}}, flip kill : UInt<1>, flip clear : UInt<1>, flip squash_grant : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<3>, rebusy : UInt<1>}}[5], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip child_rebusys : UInt<3>} regreset slot_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg slot_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, clock wire next_valid : UInt<1> connect next_valid, slot_valid wire next_uop_out : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect next_uop_out, slot_uop node _next_uop_out_br_mask_T = not(io.brupdate.b1.resolve_mask) node _next_uop_out_br_mask_T_1 = and(slot_uop.br_mask, _next_uop_out_br_mask_T) connect next_uop_out.br_mask, _next_uop_out_br_mask_T_1 wire next_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect next_uop, next_uop_out node _killed_T = and(io.brupdate.b1.mispredict_mask, slot_uop.br_mask) node _killed_T_1 = neq(_killed_T, UInt<1>(0h0)) node killed = or(_killed_T_1, io.kill) connect io.valid, slot_valid connect io.out_uop, next_uop node _io_will_be_valid_T = eq(killed, UInt<1>(0h0)) node _io_will_be_valid_T_1 = and(next_valid, _io_will_be_valid_T) connect io.will_be_valid, _io_will_be_valid_T_1 when io.kill : connect slot_valid, UInt<1>(0h0) else : when io.in_uop.valid : connect slot_valid, UInt<1>(0h1) else : when io.clear : connect slot_valid, UInt<1>(0h0) else : node _slot_valid_T = eq(killed, UInt<1>(0h0)) node _slot_valid_T_1 = and(next_valid, _slot_valid_T) connect slot_valid, _slot_valid_T_1 when io.in_uop.valid : connect slot_uop, io.in_uop.bits node _T = eq(slot_valid, UInt<1>(0h0)) node _T_1 = or(_T, io.clear) node _T_2 = or(_T_1, io.kill) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:79 assert (!slot_valid \|\| io.clear \|\| io.kill)\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert else : connect slot_uop, next_uop connect next_uop.iw_p1_bypass_hint, UInt<1>(0h0) connect next_uop.iw_p2_bypass_hint, UInt<1>(0h0) connect next_uop.iw_p3_bypass_hint, UInt<1>(0h0) connect next_uop.iw_p1_speculative_child, UInt<1>(0h0) connect next_uop.iw_p2_speculative_child, UInt<1>(0h0) wire rebusied_prs1 : UInt<1> connect rebusied_prs1, UInt<1>(0h0) wire rebusied_prs2 : UInt<1> connect rebusied_prs2, UInt<1>(0h0) node rebusied = or(rebusied_prs1, rebusied_prs2) node prs1_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs1) node prs1_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs1) node prs1_matches_2 = eq(io.wakeup_ports[2].bits.uop.pdst, slot_uop.prs1) node prs1_matches_3 = eq(io.wakeup_ports[3].bits.uop.pdst, slot_uop.prs1) node prs1_matches_4 = eq(io.wakeup_ports[4].bits.uop.pdst, slot_uop.prs1) node prs2_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs2) node prs2_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs2) node prs2_matches_2 = eq(io.wakeup_ports[2].bits.uop.pdst, slot_uop.prs2) node prs2_matches_3 = eq(io.wakeup_ports[3].bits.uop.pdst, slot_uop.prs2) node prs2_matches_4 = eq(io.wakeup_ports[4].bits.uop.pdst, slot_uop.prs2) node prs3_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs3) node prs3_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs3) node prs3_matches_2 = eq(io.wakeup_ports[2].bits.uop.pdst, slot_uop.prs3) node prs3_matches_3 = eq(io.wakeup_ports[3].bits.uop.pdst, slot_uop.prs3) node prs3_matches_4 = eq(io.wakeup_ports[4].bits.uop.pdst, slot_uop.prs3) node prs1_wakeups_0 = and(io.wakeup_ports[0].valid, prs1_matches_0) node prs1_wakeups_1 = and(io.wakeup_ports[1].valid, prs1_matches_1) node prs1_wakeups_2 = and(io.wakeup_ports[2].valid, prs1_matches_2) node prs1_wakeups_3 = and(io.wakeup_ports[3].valid, prs1_matches_3) node prs1_wakeups_4 = and(io.wakeup_ports[4].valid, prs1_matches_4) node prs2_wakeups_0 = and(io.wakeup_ports[0].valid, prs2_matches_0) node prs2_wakeups_1 = and(io.wakeup_ports[1].valid, prs2_matches_1) node prs2_wakeups_2 = and(io.wakeup_ports[2].valid, prs2_matches_2) node prs2_wakeups_3 = and(io.wakeup_ports[3].valid, prs2_matches_3) node prs2_wakeups_4 = and(io.wakeup_ports[4].valid, prs2_matches_4) node prs3_wakeups_0 = and(io.wakeup_ports[0].valid, prs3_matches_0) node prs3_wakeups_1 = and(io.wakeup_ports[1].valid, prs3_matches_1) node prs3_wakeups_2 = and(io.wakeup_ports[2].valid, prs3_matches_2) node prs3_wakeups_3 = and(io.wakeup_ports[3].valid, prs3_matches_3) node prs3_wakeups_4 = and(io.wakeup_ports[4].valid, prs3_matches_4) node prs1_rebusys_0 = and(io.wakeup_ports[0].bits.rebusy, prs1_matches_0) node prs1_rebusys_1 = and(io.wakeup_ports[1].bits.rebusy, prs1_matches_1) node prs1_rebusys_2 = and(io.wakeup_ports[2].bits.rebusy, prs1_matches_2) node prs1_rebusys_3 = and(io.wakeup_ports[3].bits.rebusy, prs1_matches_3) node prs1_rebusys_4 = and(io.wakeup_ports[4].bits.rebusy, prs1_matches_4) node prs2_rebusys_0 = and(io.wakeup_ports[0].bits.rebusy, prs2_matches_0) node prs2_rebusys_1 = and(io.wakeup_ports[1].bits.rebusy, prs2_matches_1) node prs2_rebusys_2 = and(io.wakeup_ports[2].bits.rebusy, prs2_matches_2) node prs2_rebusys_3 = and(io.wakeup_ports[3].bits.rebusy, prs2_matches_3) node prs2_rebusys_4 = and(io.wakeup_ports[4].bits.rebusy, prs2_matches_4) node _T_6 = or(prs1_wakeups_0, prs1_wakeups_1) node _T_7 = or(_T_6, prs1_wakeups_2) node _T_8 = or(_T_7, prs1_wakeups_3) node _T_9 = or(_T_8, prs1_wakeups_4) when _T_9 : connect next_uop.prs1_busy, UInt<1>(0h0) node _next_uop_iw_p1_speculative_child_T = mux(prs1_wakeups_0, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p1_speculative_child_T_1 = mux(prs1_wakeups_1, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p1_speculative_child_T_2 = mux(prs1_wakeups_2, io.wakeup_ports[2].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p1_speculative_child_T_3 = mux(prs1_wakeups_3, io.wakeup_ports[3].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p1_speculative_child_T_4 = mux(prs1_wakeups_4, io.wakeup_ports[4].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p1_speculative_child_T_5 = or(_next_uop_iw_p1_speculative_child_T, _next_uop_iw_p1_speculative_child_T_1) node _next_uop_iw_p1_speculative_child_T_6 = or(_next_uop_iw_p1_speculative_child_T_5, _next_uop_iw_p1_speculative_child_T_2) node _next_uop_iw_p1_speculative_child_T_7 = or(_next_uop_iw_p1_speculative_child_T_6, _next_uop_iw_p1_speculative_child_T_3) node _next_uop_iw_p1_speculative_child_T_8 = or(_next_uop_iw_p1_speculative_child_T_7, _next_uop_iw_p1_speculative_child_T_4) wire _next_uop_iw_p1_speculative_child_WIRE : UInt<3> connect _next_uop_iw_p1_speculative_child_WIRE, _next_uop_iw_p1_speculative_child_T_8 connect next_uop.iw_p1_speculative_child, _next_uop_iw_p1_speculative_child_WIRE node _next_uop_iw_p1_bypass_hint_T = mux(prs1_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p1_bypass_hint_T_1 = mux(prs1_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p1_bypass_hint_T_2 = mux(prs1_wakeups_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p1_bypass_hint_T_3 = mux(prs1_wakeups_3, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p1_bypass_hint_T_4 = mux(prs1_wakeups_4, io.wakeup_ports[4].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p1_bypass_hint_T_5 = or(_next_uop_iw_p1_bypass_hint_T, _next_uop_iw_p1_bypass_hint_T_1) node _next_uop_iw_p1_bypass_hint_T_6 = or(_next_uop_iw_p1_bypass_hint_T_5, _next_uop_iw_p1_bypass_hint_T_2) node _next_uop_iw_p1_bypass_hint_T_7 = or(_next_uop_iw_p1_bypass_hint_T_6, _next_uop_iw_p1_bypass_hint_T_3) node _next_uop_iw_p1_bypass_hint_T_8 = or(_next_uop_iw_p1_bypass_hint_T_7, _next_uop_iw_p1_bypass_hint_T_4) wire _next_uop_iw_p1_bypass_hint_WIRE : UInt<1> connect _next_uop_iw_p1_bypass_hint_WIRE, _next_uop_iw_p1_bypass_hint_T_8 connect next_uop.iw_p1_bypass_hint, _next_uop_iw_p1_bypass_hint_WIRE node _T_10 = or(prs1_rebusys_0, prs1_rebusys_1) node _T_11 = or(_T_10, prs1_rebusys_2) node _T_12 = or(_T_11, prs1_rebusys_3) node _T_13 = or(_T_12, prs1_rebusys_4) node _T_14 = and(io.child_rebusys, slot_uop.iw_p1_speculative_child) node _T_15 = neq(_T_14, UInt<1>(0h0)) node _T_16 = or(_T_13, _T_15) node _T_17 = eq(slot_uop.lrs1_rtype, UInt<2>(0h0)) node _T_18 = and(_T_16, _T_17) when _T_18 : connect next_uop.prs1_busy, UInt<1>(0h1) connect rebusied_prs1, UInt<1>(0h1) node _T_19 = or(prs2_wakeups_0, prs2_wakeups_1) node _T_20 = or(_T_19, prs2_wakeups_2) node _T_21 = or(_T_20, prs2_wakeups_3) node _T_22 = or(_T_21, prs2_wakeups_4) when _T_22 : connect next_uop.prs2_busy, UInt<1>(0h0) node _next_uop_iw_p2_speculative_child_T = mux(prs2_wakeups_0, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p2_speculative_child_T_1 = mux(prs2_wakeups_1, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p2_speculative_child_T_2 = mux(prs2_wakeups_2, io.wakeup_ports[2].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p2_speculative_child_T_3 = mux(prs2_wakeups_3, io.wakeup_ports[3].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p2_speculative_child_T_4 = mux(prs2_wakeups_4, io.wakeup_ports[4].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p2_speculative_child_T_5 = or(_next_uop_iw_p2_speculative_child_T, _next_uop_iw_p2_speculative_child_T_1) node _next_uop_iw_p2_speculative_child_T_6 = or(_next_uop_iw_p2_speculative_child_T_5, _next_uop_iw_p2_speculative_child_T_2) node _next_uop_iw_p2_speculative_child_T_7 = or(_next_uop_iw_p2_speculative_child_T_6, _next_uop_iw_p2_speculative_child_T_3) node _next_uop_iw_p2_speculative_child_T_8 = or(_next_uop_iw_p2_speculative_child_T_7, _next_uop_iw_p2_speculative_child_T_4) wire _next_uop_iw_p2_speculative_child_WIRE : UInt<3> connect _next_uop_iw_p2_speculative_child_WIRE, _next_uop_iw_p2_speculative_child_T_8 connect next_uop.iw_p2_speculative_child, _next_uop_iw_p2_speculative_child_WIRE node _next_uop_iw_p2_bypass_hint_T = mux(prs2_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p2_bypass_hint_T_1 = mux(prs2_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p2_bypass_hint_T_2 = mux(prs2_wakeups_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p2_bypass_hint_T_3 = mux(prs2_wakeups_3, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p2_bypass_hint_T_4 = mux(prs2_wakeups_4, io.wakeup_ports[4].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p2_bypass_hint_T_5 = or(_next_uop_iw_p2_bypass_hint_T, _next_uop_iw_p2_bypass_hint_T_1) node _next_uop_iw_p2_bypass_hint_T_6 = or(_next_uop_iw_p2_bypass_hint_T_5, _next_uop_iw_p2_bypass_hint_T_2) node _next_uop_iw_p2_bypass_hint_T_7 = or(_next_uop_iw_p2_bypass_hint_T_6, _next_uop_iw_p2_bypass_hint_T_3) node _next_uop_iw_p2_bypass_hint_T_8 = or(_next_uop_iw_p2_bypass_hint_T_7, _next_uop_iw_p2_bypass_hint_T_4) wire _next_uop_iw_p2_bypass_hint_WIRE : UInt<1> connect _next_uop_iw_p2_bypass_hint_WIRE, _next_uop_iw_p2_bypass_hint_T_8 connect next_uop.iw_p2_bypass_hint, _next_uop_iw_p2_bypass_hint_WIRE node _T_23 = or(prs2_rebusys_0, prs2_rebusys_1) node _T_24 = or(_T_23, prs2_rebusys_2) node _T_25 = or(_T_24, prs2_rebusys_3) node _T_26 = or(_T_25, prs2_rebusys_4) node _T_27 = and(io.child_rebusys, slot_uop.iw_p2_speculative_child) node _T_28 = neq(_T_27, UInt<1>(0h0)) node _T_29 = or(_T_26, _T_28) node _T_30 = eq(slot_uop.lrs2_rtype, UInt<2>(0h0)) node _T_31 = and(_T_29, _T_30) when _T_31 : connect next_uop.prs2_busy, UInt<1>(0h1) connect rebusied_prs2, UInt<1>(0h1) node _T_32 = or(prs3_wakeups_0, prs3_wakeups_1) node _T_33 = or(_T_32, prs3_wakeups_2) node _T_34 = or(_T_33, prs3_wakeups_3) node _T_35 = or(_T_34, prs3_wakeups_4) when _T_35 : connect next_uop.prs3_busy, UInt<1>(0h0) node _next_uop_iw_p3_bypass_hint_T = mux(prs3_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p3_bypass_hint_T_1 = mux(prs3_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p3_bypass_hint_T_2 = mux(prs3_wakeups_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p3_bypass_hint_T_3 = mux(prs3_wakeups_3, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p3_bypass_hint_T_4 = mux(prs3_wakeups_4, io.wakeup_ports[4].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p3_bypass_hint_T_5 = or(_next_uop_iw_p3_bypass_hint_T, _next_uop_iw_p3_bypass_hint_T_1) node _next_uop_iw_p3_bypass_hint_T_6 = or(_next_uop_iw_p3_bypass_hint_T_5, _next_uop_iw_p3_bypass_hint_T_2) node _next_uop_iw_p3_bypass_hint_T_7 = or(_next_uop_iw_p3_bypass_hint_T_6, _next_uop_iw_p3_bypass_hint_T_3) node _next_uop_iw_p3_bypass_hint_T_8 = or(_next_uop_iw_p3_bypass_hint_T_7, _next_uop_iw_p3_bypass_hint_T_4) wire _next_uop_iw_p3_bypass_hint_WIRE : UInt<1> connect _next_uop_iw_p3_bypass_hint_WIRE, _next_uop_iw_p3_bypass_hint_T_8 connect next_uop.iw_p3_bypass_hint, _next_uop_iw_p3_bypass_hint_WIRE node _T_36 = eq(io.pred_wakeup_port.bits, slot_uop.ppred) node _T_37 = and(io.pred_wakeup_port.valid, _T_36) when _T_37 : connect next_uop.ppred_busy, UInt<1>(0h0) node _iss_ready_T = eq(slot_uop.prs1_busy, UInt<1>(0h0)) node _iss_ready_T_1 = eq(slot_uop.prs2_busy, UInt<1>(0h0)) node _iss_ready_T_2 = and(_iss_ready_T, _iss_ready_T_1) node _iss_ready_T_3 = and(slot_uop.ppred_busy, UInt<1>(0h1)) node _iss_ready_T_4 = eq(_iss_ready_T_3, UInt<1>(0h0)) node _iss_ready_T_5 = and(_iss_ready_T_2, _iss_ready_T_4) node _iss_ready_T_6 = and(slot_uop.prs3_busy, UInt<1>(0h0)) node _iss_ready_T_7 = eq(_iss_ready_T_6, UInt<1>(0h0)) node iss_ready = and(_iss_ready_T_5, _iss_ready_T_7) node _agen_ready_T = eq(slot_uop.prs1_busy, UInt<1>(0h0)) node _agen_ready_T_1 = and(slot_uop.fu_code[1], _agen_ready_T) node _agen_ready_T_2 = and(slot_uop.ppred_busy, UInt<1>(0h1)) node _agen_ready_T_3 = eq(_agen_ready_T_2, UInt<1>(0h0)) node _agen_ready_T_4 = and(_agen_ready_T_1, _agen_ready_T_3) node agen_ready = and(_agen_ready_T_4, UInt<1>(0h0)) node _dgen_ready_T = eq(slot_uop.prs2_busy, UInt<1>(0h0)) node _dgen_ready_T_1 = and(slot_uop.fu_code[2], _dgen_ready_T) node _dgen_ready_T_2 = and(slot_uop.ppred_busy, UInt<1>(0h1)) node _dgen_ready_T_3 = eq(_dgen_ready_T_2, UInt<1>(0h0)) node _dgen_ready_T_4 = and(_dgen_ready_T_1, _dgen_ready_T_3) node dgen_ready = and(_dgen_ready_T_4, UInt<1>(0h0)) node _io_request_T = eq(slot_uop.iw_issued, UInt<1>(0h0)) node _io_request_T_1 = and(slot_valid, _io_request_T) node _io_request_T_2 = or(iss_ready, agen_ready) node _io_request_T_3 = or(_io_request_T_2, dgen_ready) node _io_request_T_4 = and(_io_request_T_1, _io_request_T_3) connect io.request, _io_request_T_4 connect io.iss_uop, slot_uop connect next_uop.iw_issued, UInt<1>(0h0) connect next_uop.iw_issued_partial_agen, UInt<1>(0h0) connect next_uop.iw_issued_partial_dgen, UInt<1>(0h0) node _T_38 = eq(io.squash_grant, UInt<1>(0h0)) node _T_39 = and(io.grant, _T_38) when _T_39 : connect next_uop.iw_issued, UInt<1>(0h1) node _T_40 = and(slot_valid, slot_uop.iw_issued) when _T_40 : connect next_valid, rebusied	module IssueSlot_101( // @[issue-slot.scala:49:7] input clock, // @[issue-slot.scala:49:7] input reset, // @[issue-slot.scala:49:7] output io_valid, // @[issue-slot.scala:52:14] output io_will_be_valid, // @[issue-slot.scala:52:14] output io_request, // @[issue-slot.scala:52:14] input io_grant, // @[issue-slot.scala:52:14] output [31:0] io_iss_uop_inst, // @[issue-slot.scala:52:14] output [31:0] io_iss_uop_debug_inst, // @[issue-slot.scala:52:14] output io_iss_uop_is_rvc, // @[issue-slot.scala:52:14] output [39:0] io_iss_uop_debug_pc, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_0, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_1, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_2, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_3, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_0, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_1, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_2, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_3, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_4, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_5, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_6, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_7, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_8, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_9, // @[issue-slot.scala:52:14] output io_iss_uop_iw_issued, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_dis_col_sel, // @[issue-slot.scala:52:14] output [15:0] io_iss_uop_br_mask, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_br_tag, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_br_type, // @[issue-slot.scala:52:14] output io_iss_uop_is_sfb, // @[issue-slot.scala:52:14] output io_iss_uop_is_fence, // @[issue-slot.scala:52:14] output io_iss_uop_is_fencei, // @[issue-slot.scala:52:14] output io_iss_uop_is_sfence, // @[issue-slot.scala:52:14] output io_iss_uop_is_amo, // @[issue-slot.scala:52:14] output io_iss_uop_is_eret, // @[issue-slot.scala:52:14] output io_iss_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] output io_iss_uop_is_rocc, // @[issue-slot.scala:52:14] output io_iss_uop_is_mov, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ftq_idx, // @[issue-slot.scala:52:14] output io_iss_uop_edge_inst, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_pc_lob, // @[issue-slot.scala:52:14] output io_iss_uop_taken, // @[issue-slot.scala:52:14] output io_iss_uop_imm_rename, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_imm_sel, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_pimm, // @[issue-slot.scala:52:14] output [19:0] io_iss_uop_imm_packed, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_op1_sel, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_op2_sel, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_rob_idx, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ldq_idx, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_stq_idx, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_rxq_idx, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_pdst, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs1, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs2, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs3, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ppred, // @[issue-slot.scala:52:14] output io_iss_uop_prs1_busy, // @[issue-slot.scala:52:14] output io_iss_uop_prs2_busy, // @[issue-slot.scala:52:14] output io_iss_uop_prs3_busy, // @[issue-slot.scala:52:14] output io_iss_uop_ppred_busy, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_stale_pdst, // @[issue-slot.scala:52:14] output io_iss_uop_exception, // @[issue-slot.scala:52:14] output [63:0] io_iss_uop_exc_cause, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_mem_cmd, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_mem_size, // @[issue-slot.scala:52:14] output io_iss_uop_mem_signed, // @[issue-slot.scala:52:14] output io_iss_uop_uses_ldq, // @[issue-slot.scala:52:14] output io_iss_uop_uses_stq, // @[issue-slot.scala:52:14] output io_iss_uop_is_unique, // @[issue-slot.scala:52:14] output io_iss_uop_flush_on_commit, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_csr_cmd, // @[issue-slot.scala:52:14] output io_iss_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_ldst, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs1, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs2, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs3, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_dst_rtype, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_lrs1_rtype, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_lrs2_rtype, // @[issue-slot.scala:52:14] output io_iss_uop_frs3_en, // @[issue-slot.scala:52:14] output io_iss_uop_fcn_dw, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_fcn_op, // @[issue-slot.scala:52:14] output io_iss_uop_fp_val, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_fp_rm, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_typ, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] output io_iss_uop_bp_debug_if, // @[issue-slot.scala:52:14] output io_iss_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_debug_fsrc, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_in_uop_valid, // @[issue-slot.scala:52:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:52:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_0, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_1, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_2, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_0, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_1, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_2, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_4, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_5, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_6, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_7, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_8, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_9, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_issued, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_br_type, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sfence, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_eret, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_rocc, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:52:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:52:14] input io_in_uop_bits_taken, // @[issue-slot.scala:52:14] input io_in_uop_bits_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_pimm, // @[issue-slot.scala:52:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_op2_sel, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:52:14] input io_in_uop_bits_exception, // @[issue-slot.scala:52:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:52:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:52:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:52:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:52:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_csr_cmd, // @[issue-slot.scala:52:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:52:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:52:14] input io_in_uop_bits_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_fcn_op, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_typ, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:52:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:52:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:52:14] output io_out_uop_is_rvc, // @[issue-slot.scala:52:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_0, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_1, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_2, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_3, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_0, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_1, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_2, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_3, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_4, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_5, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_6, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_7, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_8, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_9, // @[issue-slot.scala:52:14] output io_out_uop_iw_issued, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] output io_out_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] output io_out_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] output io_out_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_dis_col_sel, // @[issue-slot.scala:52:14] output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_br_type, // @[issue-slot.scala:52:14] output io_out_uop_is_sfb, // @[issue-slot.scala:52:14] output io_out_uop_is_fence, // @[issue-slot.scala:52:14] output io_out_uop_is_fencei, // @[issue-slot.scala:52:14] output io_out_uop_is_sfence, // @[issue-slot.scala:52:14] output io_out_uop_is_amo, // @[issue-slot.scala:52:14] output io_out_uop_is_eret, // @[issue-slot.scala:52:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] output io_out_uop_is_rocc, // @[issue-slot.scala:52:14] output io_out_uop_is_mov, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:52:14] output io_out_uop_edge_inst, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:52:14] output io_out_uop_taken, // @[issue-slot.scala:52:14] output io_out_uop_imm_rename, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_imm_sel, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_pimm, // @[issue-slot.scala:52:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_op1_sel, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_op2_sel, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_pdst, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs1, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs2, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs3, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ppred, // @[issue-slot.scala:52:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:52:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:52:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:52:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:52:14] output io_out_uop_exception, // @[issue-slot.scala:52:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:52:14] output io_out_uop_mem_signed, // @[issue-slot.scala:52:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:52:14] output io_out_uop_uses_stq, // @[issue-slot.scala:52:14] output io_out_uop_is_unique, // @[issue-slot.scala:52:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_csr_cmd, // @[issue-slot.scala:52:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:52:14] output io_out_uop_frs3_en, // @[issue-slot.scala:52:14] output io_out_uop_fcn_dw, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_fcn_op, // @[issue-slot.scala:52:14] output io_out_uop_fp_val, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_fp_rm, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_typ, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:52:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:52:14] input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:52:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:52:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_br_type, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sfence, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_eret, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_rocc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_op2_sel, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_fcn_op, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_typ, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:52:14] input io_brupdate_b2_taken, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:52:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:52:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:52:14] input io_kill, // @[issue-slot.scala:52:14] input io_clear, // @[issue-slot.scala:52:14] input io_squash_grant, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_0_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_0_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_0_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_0_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_0_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_0_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_bypassable, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_speculative_mask, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_rebusy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_1_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_1_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_1_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_1_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_1_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_1_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_2_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_2_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_2_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_2_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_2_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_2_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_3_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_3_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_3_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_3_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_3_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_3_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_4_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_4_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_4_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_4_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_4_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_4_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_4_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_4_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_pred_wakeup_port_valid, // @[issue-slot.scala:52:14] input [4:0] io_pred_wakeup_port_bits, // @[issue-slot.scala:52:14] input [2:0] io_child_rebusys // @[issue-slot.scala:52:14] ); wire [15:0] next_uop_out_br_mask; // @[util.scala:104:23] wire io_grant_0 = io_grant; // @[issue-slot.scala:49:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:49:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:49:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_0_0 = io_in_uop_bits_iq_type_0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_1_0 = io_in_uop_bits_iq_type_1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_2_0 = io_in_uop_bits_iq_type_2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_3_0 = io_in_uop_bits_iq_type_3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_0_0 = io_in_uop_bits_fu_code_0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_1_0 = io_in_uop_bits_fu_code_1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_2_0 = io_in_uop_bits_fu_code_2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_3_0 = io_in_uop_bits_fu_code_3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_4_0 = io_in_uop_bits_fu_code_4; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_5_0 = io_in_uop_bits_fu_code_5; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_6_0 = io_in_uop_bits_fu_code_6; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_7_0 = io_in_uop_bits_fu_code_7; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_8_0 = io_in_uop_bits_fu_code_8; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_9_0 = io_in_uop_bits_fu_code_9; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_0 = io_in_uop_bits_iw_issued; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_iw_p1_speculative_child_0 = io_in_uop_bits_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_iw_p2_speculative_child_0 = io_in_uop_bits_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p1_bypass_hint_0 = io_in_uop_bits_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p2_bypass_hint_0 = io_in_uop_bits_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p3_bypass_hint_0 = io_in_uop_bits_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_dis_col_sel_0 = io_in_uop_bits_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_br_type_0 = io_in_uop_bits_br_type; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sfence_0 = io_in_uop_bits_is_sfence; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_eret_0 = io_in_uop_bits_is_eret; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_rocc_0 = io_in_uop_bits_is_rocc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_mov_0 = io_in_uop_bits_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:49:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:49:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:49:7] wire io_in_uop_bits_imm_rename_0 = io_in_uop_bits_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_imm_sel_0 = io_in_uop_bits_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_pimm_0 = io_in_uop_bits_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_op1_sel_0 = io_in_uop_bits_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_op2_sel_0 = io_in_uop_bits_op2_sel; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ldst_0 = io_in_uop_bits_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_wen_0 = io_in_uop_bits_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren1_0 = io_in_uop_bits_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren2_0 = io_in_uop_bits_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren3_0 = io_in_uop_bits_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_swap12_0 = io_in_uop_bits_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_swap23_0 = io_in_uop_bits_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_ctrl_typeTagIn_0 = io_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_ctrl_typeTagOut_0 = io_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fromint_0 = io_in_uop_bits_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_toint_0 = io_in_uop_bits_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fastpipe_0 = io_in_uop_bits_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fma_0 = io_in_uop_bits_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_div_0 = io_in_uop_bits_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_sqrt_0 = io_in_uop_bits_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_wflags_0 = io_in_uop_bits_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_vec_0 = io_in_uop_bits_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:49:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:49:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:49:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:49:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:49:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_csr_cmd_0 = io_in_uop_bits_csr_cmd; // @[issue-slot.scala:49:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fcn_dw_0 = io_in_uop_bits_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_fcn_op_0 = io_in_uop_bits_fcn_op; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_fp_rm_0 = io_in_uop_bits_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_typ_0 = io_in_uop_bits_fp_typ; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:49:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:49:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:49:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:49:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:49:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:49:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:49:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:49:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:49:7] wire io_squash_grant_0 = io_squash_grant; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_0_bits_uop_inst_0 = io_wakeup_ports_0_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_0_bits_uop_debug_inst_0 = io_wakeup_ports_0_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_rvc_0 = io_wakeup_ports_0_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_0_bits_uop_debug_pc_0 = io_wakeup_ports_0_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_0_0 = io_wakeup_ports_0_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_1_0 = io_wakeup_ports_0_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_2_0 = io_wakeup_ports_0_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_3_0 = io_wakeup_ports_0_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_0_0 = io_wakeup_ports_0_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_1_0 = io_wakeup_ports_0_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_2_0 = io_wakeup_ports_0_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_3_0 = io_wakeup_ports_0_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_4_0 = io_wakeup_ports_0_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_5_0 = io_wakeup_ports_0_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_6_0 = io_wakeup_ports_0_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_7_0 = io_wakeup_ports_0_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_8_0 = io_wakeup_ports_0_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_9_0 = io_wakeup_ports_0_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_0 = io_wakeup_ports_0_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel_0 = io_wakeup_ports_0_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_0_bits_uop_br_mask_0 = io_wakeup_ports_0_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_tag_0 = io_wakeup_ports_0_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_type_0 = io_wakeup_ports_0_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sfb_0 = io_wakeup_ports_0_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_fence_0 = io_wakeup_ports_0_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_fencei_0 = io_wakeup_ports_0_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sfence_0 = io_wakeup_ports_0_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_amo_0 = io_wakeup_ports_0_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_eret_0 = io_wakeup_ports_0_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_0_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_rocc_0 = io_wakeup_ports_0_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_mov_0 = io_wakeup_ports_0_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ftq_idx_0 = io_wakeup_ports_0_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_edge_inst_0 = io_wakeup_ports_0_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_pc_lob_0 = io_wakeup_ports_0_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_taken_0 = io_wakeup_ports_0_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_imm_rename_0 = io_wakeup_ports_0_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_imm_sel_0 = io_wakeup_ports_0_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_pimm_0 = io_wakeup_ports_0_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_0_bits_uop_imm_packed_0 = io_wakeup_ports_0_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_op1_sel_0 = io_wakeup_ports_0_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_op2_sel_0 = io_wakeup_ports_0_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_rob_idx_0 = io_wakeup_ports_0_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ldq_idx_0 = io_wakeup_ports_0_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_stq_idx_0 = io_wakeup_ports_0_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_rxq_idx_0 = io_wakeup_ports_0_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_pdst_0 = io_wakeup_ports_0_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs1_0 = io_wakeup_ports_0_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs2_0 = io_wakeup_ports_0_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs3_0 = io_wakeup_ports_0_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ppred_0 = io_wakeup_ports_0_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs1_busy_0 = io_wakeup_ports_0_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs2_busy_0 = io_wakeup_ports_0_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs3_busy_0 = io_wakeup_ports_0_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_ppred_busy_0 = io_wakeup_ports_0_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_stale_pdst_0 = io_wakeup_ports_0_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_exception_0 = io_wakeup_ports_0_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_0_bits_uop_exc_cause_0 = io_wakeup_ports_0_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_mem_cmd_0 = io_wakeup_ports_0_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_mem_size_0 = io_wakeup_ports_0_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_mem_signed_0 = io_wakeup_ports_0_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_uses_ldq_0 = io_wakeup_ports_0_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_uses_stq_0 = io_wakeup_ports_0_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_unique_0 = io_wakeup_ports_0_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_flush_on_commit_0 = io_wakeup_ports_0_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_csr_cmd_0 = io_wakeup_ports_0_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_0_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_ldst_0 = io_wakeup_ports_0_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs1_0 = io_wakeup_ports_0_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs2_0 = io_wakeup_ports_0_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs3_0 = io_wakeup_ports_0_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_dst_rtype_0 = io_wakeup_ports_0_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype_0 = io_wakeup_ports_0_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype_0 = io_wakeup_ports_0_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_frs3_en_0 = io_wakeup_ports_0_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fcn_dw_0 = io_wakeup_ports_0_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_fcn_op_0 = io_wakeup_ports_0_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_val_0 = io_wakeup_ports_0_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_fp_rm_0 = io_wakeup_ports_0_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_typ_0 = io_wakeup_ports_0_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_0_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_bp_debug_if_0 = io_wakeup_ports_0_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_0_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc_0 = io_wakeup_ports_0_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc_0 = io_wakeup_ports_0_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_bypassable_0 = io_wakeup_ports_0_bits_bypassable; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_speculative_mask_0 = io_wakeup_ports_0_bits_speculative_mask; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_rebusy_0 = io_wakeup_ports_0_bits_rebusy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_1_bits_uop_inst_0 = io_wakeup_ports_1_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_1_bits_uop_debug_inst_0 = io_wakeup_ports_1_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_rvc_0 = io_wakeup_ports_1_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_1_bits_uop_debug_pc_0 = io_wakeup_ports_1_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_0_0 = io_wakeup_ports_1_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_1_0 = io_wakeup_ports_1_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_2_0 = io_wakeup_ports_1_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_3_0 = io_wakeup_ports_1_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_0_0 = io_wakeup_ports_1_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_1_0 = io_wakeup_ports_1_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_2_0 = io_wakeup_ports_1_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_3_0 = io_wakeup_ports_1_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_4_0 = io_wakeup_ports_1_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_5_0 = io_wakeup_ports_1_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_6_0 = io_wakeup_ports_1_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_7_0 = io_wakeup_ports_1_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_8_0 = io_wakeup_ports_1_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_9_0 = io_wakeup_ports_1_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_0 = io_wakeup_ports_1_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel_0 = io_wakeup_ports_1_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_1_bits_uop_br_mask_0 = io_wakeup_ports_1_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_tag_0 = io_wakeup_ports_1_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_type_0 = io_wakeup_ports_1_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sfb_0 = io_wakeup_ports_1_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_fence_0 = io_wakeup_ports_1_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_fencei_0 = io_wakeup_ports_1_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sfence_0 = io_wakeup_ports_1_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_amo_0 = io_wakeup_ports_1_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_eret_0 = io_wakeup_ports_1_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_1_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_rocc_0 = io_wakeup_ports_1_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_mov_0 = io_wakeup_ports_1_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ftq_idx_0 = io_wakeup_ports_1_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_edge_inst_0 = io_wakeup_ports_1_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_pc_lob_0 = io_wakeup_ports_1_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_taken_0 = io_wakeup_ports_1_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_imm_rename_0 = io_wakeup_ports_1_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_imm_sel_0 = io_wakeup_ports_1_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_pimm_0 = io_wakeup_ports_1_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_1_bits_uop_imm_packed_0 = io_wakeup_ports_1_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_op1_sel_0 = io_wakeup_ports_1_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_op2_sel_0 = io_wakeup_ports_1_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_rob_idx_0 = io_wakeup_ports_1_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ldq_idx_0 = io_wakeup_ports_1_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_stq_idx_0 = io_wakeup_ports_1_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_rxq_idx_0 = io_wakeup_ports_1_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_pdst_0 = io_wakeup_ports_1_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs1_0 = io_wakeup_ports_1_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs2_0 = io_wakeup_ports_1_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs3_0 = io_wakeup_ports_1_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ppred_0 = io_wakeup_ports_1_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs1_busy_0 = io_wakeup_ports_1_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs2_busy_0 = io_wakeup_ports_1_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs3_busy_0 = io_wakeup_ports_1_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_ppred_busy_0 = io_wakeup_ports_1_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_stale_pdst_0 = io_wakeup_ports_1_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_exception_0 = io_wakeup_ports_1_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_1_bits_uop_exc_cause_0 = io_wakeup_ports_1_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_mem_cmd_0 = io_wakeup_ports_1_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_mem_size_0 = io_wakeup_ports_1_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_mem_signed_0 = io_wakeup_ports_1_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_uses_ldq_0 = io_wakeup_ports_1_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_uses_stq_0 = io_wakeup_ports_1_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_unique_0 = io_wakeup_ports_1_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_flush_on_commit_0 = io_wakeup_ports_1_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_csr_cmd_0 = io_wakeup_ports_1_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_1_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_ldst_0 = io_wakeup_ports_1_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs1_0 = io_wakeup_ports_1_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs2_0 = io_wakeup_ports_1_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs3_0 = io_wakeup_ports_1_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_dst_rtype_0 = io_wakeup_ports_1_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype_0 = io_wakeup_ports_1_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype_0 = io_wakeup_ports_1_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_frs3_en_0 = io_wakeup_ports_1_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fcn_dw_0 = io_wakeup_ports_1_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_fcn_op_0 = io_wakeup_ports_1_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_val_0 = io_wakeup_ports_1_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_fp_rm_0 = io_wakeup_ports_1_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_typ_0 = io_wakeup_ports_1_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_1_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_bp_debug_if_0 = io_wakeup_ports_1_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_1_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc_0 = io_wakeup_ports_1_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc_0 = io_wakeup_ports_1_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_2_bits_uop_inst_0 = io_wakeup_ports_2_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_2_bits_uop_debug_inst_0 = io_wakeup_ports_2_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_rvc_0 = io_wakeup_ports_2_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_2_bits_uop_debug_pc_0 = io_wakeup_ports_2_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_0_0 = io_wakeup_ports_2_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_1_0 = io_wakeup_ports_2_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_2_0 = io_wakeup_ports_2_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_3_0 = io_wakeup_ports_2_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_0_0 = io_wakeup_ports_2_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_1_0 = io_wakeup_ports_2_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_2_0 = io_wakeup_ports_2_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_3_0 = io_wakeup_ports_2_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_4_0 = io_wakeup_ports_2_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_5_0 = io_wakeup_ports_2_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_6_0 = io_wakeup_ports_2_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_7_0 = io_wakeup_ports_2_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_8_0 = io_wakeup_ports_2_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_9_0 = io_wakeup_ports_2_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_0 = io_wakeup_ports_2_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_dis_col_sel_0 = io_wakeup_ports_2_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_2_bits_uop_br_mask_0 = io_wakeup_ports_2_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_br_tag_0 = io_wakeup_ports_2_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_br_type_0 = io_wakeup_ports_2_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sfb_0 = io_wakeup_ports_2_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_fence_0 = io_wakeup_ports_2_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_fencei_0 = io_wakeup_ports_2_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sfence_0 = io_wakeup_ports_2_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_amo_0 = io_wakeup_ports_2_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_eret_0 = io_wakeup_ports_2_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_2_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_rocc_0 = io_wakeup_ports_2_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_mov_0 = io_wakeup_ports_2_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_ftq_idx_0 = io_wakeup_ports_2_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_edge_inst_0 = io_wakeup_ports_2_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_pc_lob_0 = io_wakeup_ports_2_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_taken_0 = io_wakeup_ports_2_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_imm_rename_0 = io_wakeup_ports_2_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_imm_sel_0 = io_wakeup_ports_2_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_pimm_0 = io_wakeup_ports_2_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_2_bits_uop_imm_packed_0 = io_wakeup_ports_2_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_op1_sel_0 = io_wakeup_ports_2_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_op2_sel_0 = io_wakeup_ports_2_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_rob_idx_0 = io_wakeup_ports_2_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_ldq_idx_0 = io_wakeup_ports_2_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_stq_idx_0 = io_wakeup_ports_2_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_rxq_idx_0 = io_wakeup_ports_2_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_pdst_0 = io_wakeup_ports_2_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs1_0 = io_wakeup_ports_2_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs2_0 = io_wakeup_ports_2_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs3_0 = io_wakeup_ports_2_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_ppred_0 = io_wakeup_ports_2_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs1_busy_0 = io_wakeup_ports_2_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs2_busy_0 = io_wakeup_ports_2_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs3_busy_0 = io_wakeup_ports_2_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_ppred_busy_0 = io_wakeup_ports_2_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_stale_pdst_0 = io_wakeup_ports_2_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_exception_0 = io_wakeup_ports_2_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_2_bits_uop_exc_cause_0 = io_wakeup_ports_2_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_mem_cmd_0 = io_wakeup_ports_2_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_mem_size_0 = io_wakeup_ports_2_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_mem_signed_0 = io_wakeup_ports_2_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_uses_ldq_0 = io_wakeup_ports_2_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_uses_stq_0 = io_wakeup_ports_2_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_unique_0 = io_wakeup_ports_2_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_flush_on_commit_0 = io_wakeup_ports_2_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_csr_cmd_0 = io_wakeup_ports_2_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_2_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_ldst_0 = io_wakeup_ports_2_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs1_0 = io_wakeup_ports_2_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs2_0 = io_wakeup_ports_2_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs3_0 = io_wakeup_ports_2_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_dst_rtype_0 = io_wakeup_ports_2_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype_0 = io_wakeup_ports_2_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype_0 = io_wakeup_ports_2_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_frs3_en_0 = io_wakeup_ports_2_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fcn_dw_0 = io_wakeup_ports_2_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_fcn_op_0 = io_wakeup_ports_2_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_val_0 = io_wakeup_ports_2_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_fp_rm_0 = io_wakeup_ports_2_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_typ_0 = io_wakeup_ports_2_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_2_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_bp_debug_if_0 = io_wakeup_ports_2_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_2_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc_0 = io_wakeup_ports_2_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc_0 = io_wakeup_ports_2_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_3_bits_uop_inst_0 = io_wakeup_ports_3_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_3_bits_uop_debug_inst_0 = io_wakeup_ports_3_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_rvc_0 = io_wakeup_ports_3_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_3_bits_uop_debug_pc_0 = io_wakeup_ports_3_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_0_0 = io_wakeup_ports_3_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_1_0 = io_wakeup_ports_3_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_2_0 = io_wakeup_ports_3_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_3_0 = io_wakeup_ports_3_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_0_0 = io_wakeup_ports_3_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_1_0 = io_wakeup_ports_3_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_2_0 = io_wakeup_ports_3_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_3_0 = io_wakeup_ports_3_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_4_0 = io_wakeup_ports_3_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_5_0 = io_wakeup_ports_3_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_6_0 = io_wakeup_ports_3_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_7_0 = io_wakeup_ports_3_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_8_0 = io_wakeup_ports_3_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_9_0 = io_wakeup_ports_3_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_0 = io_wakeup_ports_3_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_dis_col_sel_0 = io_wakeup_ports_3_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_3_bits_uop_br_mask_0 = io_wakeup_ports_3_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_br_tag_0 = io_wakeup_ports_3_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_br_type_0 = io_wakeup_ports_3_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sfb_0 = io_wakeup_ports_3_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_fence_0 = io_wakeup_ports_3_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_fencei_0 = io_wakeup_ports_3_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sfence_0 = io_wakeup_ports_3_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_amo_0 = io_wakeup_ports_3_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_eret_0 = io_wakeup_ports_3_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_3_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_rocc_0 = io_wakeup_ports_3_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_mov_0 = io_wakeup_ports_3_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_ftq_idx_0 = io_wakeup_ports_3_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_edge_inst_0 = io_wakeup_ports_3_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_pc_lob_0 = io_wakeup_ports_3_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_taken_0 = io_wakeup_ports_3_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_imm_rename_0 = io_wakeup_ports_3_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_imm_sel_0 = io_wakeup_ports_3_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_pimm_0 = io_wakeup_ports_3_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_3_bits_uop_imm_packed_0 = io_wakeup_ports_3_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_op1_sel_0 = io_wakeup_ports_3_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_op2_sel_0 = io_wakeup_ports_3_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_rob_idx_0 = io_wakeup_ports_3_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_ldq_idx_0 = io_wakeup_ports_3_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_stq_idx_0 = io_wakeup_ports_3_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_rxq_idx_0 = io_wakeup_ports_3_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_pdst_0 = io_wakeup_ports_3_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs1_0 = io_wakeup_ports_3_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs2_0 = io_wakeup_ports_3_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs3_0 = io_wakeup_ports_3_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_ppred_0 = io_wakeup_ports_3_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs1_busy_0 = io_wakeup_ports_3_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs2_busy_0 = io_wakeup_ports_3_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs3_busy_0 = io_wakeup_ports_3_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_ppred_busy_0 = io_wakeup_ports_3_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_stale_pdst_0 = io_wakeup_ports_3_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_exception_0 = io_wakeup_ports_3_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_3_bits_uop_exc_cause_0 = io_wakeup_ports_3_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_mem_cmd_0 = io_wakeup_ports_3_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_mem_size_0 = io_wakeup_ports_3_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_mem_signed_0 = io_wakeup_ports_3_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_uses_ldq_0 = io_wakeup_ports_3_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_uses_stq_0 = io_wakeup_ports_3_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_unique_0 = io_wakeup_ports_3_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_flush_on_commit_0 = io_wakeup_ports_3_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_csr_cmd_0 = io_wakeup_ports_3_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_3_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_ldst_0 = io_wakeup_ports_3_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs1_0 = io_wakeup_ports_3_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs2_0 = io_wakeup_ports_3_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs3_0 = io_wakeup_ports_3_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_dst_rtype_0 = io_wakeup_ports_3_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype_0 = io_wakeup_ports_3_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype_0 = io_wakeup_ports_3_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_frs3_en_0 = io_wakeup_ports_3_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fcn_dw_0 = io_wakeup_ports_3_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_fcn_op_0 = io_wakeup_ports_3_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_val_0 = io_wakeup_ports_3_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_fp_rm_0 = io_wakeup_ports_3_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_typ_0 = io_wakeup_ports_3_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_3_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_bp_debug_if_0 = io_wakeup_ports_3_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_3_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc_0 = io_wakeup_ports_3_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc_0 = io_wakeup_ports_3_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_valid_0 = io_wakeup_ports_4_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_4_bits_uop_inst_0 = io_wakeup_ports_4_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_4_bits_uop_debug_inst_0 = io_wakeup_ports_4_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_rvc_0 = io_wakeup_ports_4_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_4_bits_uop_debug_pc_0 = io_wakeup_ports_4_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iq_type_0_0 = io_wakeup_ports_4_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iq_type_1_0 = io_wakeup_ports_4_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iq_type_2_0 = io_wakeup_ports_4_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iq_type_3_0 = io_wakeup_ports_4_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_0_0 = io_wakeup_ports_4_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_1_0 = io_wakeup_ports_4_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_2_0 = io_wakeup_ports_4_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_3_0 = io_wakeup_ports_4_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_4_0 = io_wakeup_ports_4_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_5_0 = io_wakeup_ports_4_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_6_0 = io_wakeup_ports_4_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_7_0 = io_wakeup_ports_4_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_8_0 = io_wakeup_ports_4_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_9_0 = io_wakeup_ports_4_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_issued_0 = io_wakeup_ports_4_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_4_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_4_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_dis_col_sel_0 = io_wakeup_ports_4_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_4_bits_uop_br_mask_0 = io_wakeup_ports_4_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_4_bits_uop_br_tag_0 = io_wakeup_ports_4_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_4_bits_uop_br_type_0 = io_wakeup_ports_4_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_sfb_0 = io_wakeup_ports_4_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_fence_0 = io_wakeup_ports_4_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_fencei_0 = io_wakeup_ports_4_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_sfence_0 = io_wakeup_ports_4_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_amo_0 = io_wakeup_ports_4_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_eret_0 = io_wakeup_ports_4_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_4_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_rocc_0 = io_wakeup_ports_4_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_mov_0 = io_wakeup_ports_4_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_ftq_idx_0 = io_wakeup_ports_4_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_edge_inst_0 = io_wakeup_ports_4_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_pc_lob_0 = io_wakeup_ports_4_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_taken_0 = io_wakeup_ports_4_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_imm_rename_0 = io_wakeup_ports_4_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_imm_sel_0 = io_wakeup_ports_4_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_pimm_0 = io_wakeup_ports_4_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_4_bits_uop_imm_packed_0 = io_wakeup_ports_4_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_op1_sel_0 = io_wakeup_ports_4_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_op2_sel_0 = io_wakeup_ports_4_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_rob_idx_0 = io_wakeup_ports_4_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_ldq_idx_0 = io_wakeup_ports_4_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_stq_idx_0 = io_wakeup_ports_4_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_rxq_idx_0 = io_wakeup_ports_4_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_pdst_0 = io_wakeup_ports_4_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_prs1_0 = io_wakeup_ports_4_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_prs2_0 = io_wakeup_ports_4_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_prs3_0 = io_wakeup_ports_4_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_ppred_0 = io_wakeup_ports_4_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_prs1_busy_0 = io_wakeup_ports_4_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_prs2_busy_0 = io_wakeup_ports_4_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_prs3_busy_0 = io_wakeup_ports_4_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_ppred_busy_0 = io_wakeup_ports_4_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_stale_pdst_0 = io_wakeup_ports_4_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_exception_0 = io_wakeup_ports_4_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_4_bits_uop_exc_cause_0 = io_wakeup_ports_4_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_mem_cmd_0 = io_wakeup_ports_4_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_mem_size_0 = io_wakeup_ports_4_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_mem_signed_0 = io_wakeup_ports_4_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_uses_ldq_0 = io_wakeup_ports_4_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_uses_stq_0 = io_wakeup_ports_4_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_unique_0 = io_wakeup_ports_4_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_flush_on_commit_0 = io_wakeup_ports_4_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_csr_cmd_0 = io_wakeup_ports_4_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_4_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_ldst_0 = io_wakeup_ports_4_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_lrs1_0 = io_wakeup_ports_4_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_lrs2_0 = io_wakeup_ports_4_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_lrs3_0 = io_wakeup_ports_4_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_dst_rtype_0 = io_wakeup_ports_4_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_lrs1_rtype_0 = io_wakeup_ports_4_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_lrs2_rtype_0 = io_wakeup_ports_4_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_frs3_en_0 = io_wakeup_ports_4_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fcn_dw_0 = io_wakeup_ports_4_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_fcn_op_0 = io_wakeup_ports_4_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_val_0 = io_wakeup_ports_4_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_fp_rm_0 = io_wakeup_ports_4_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_fp_typ_0 = io_wakeup_ports_4_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_4_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_4_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_4_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_bp_debug_if_0 = io_wakeup_ports_4_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_4_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_debug_fsrc_0 = io_wakeup_ports_4_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_debug_tsrc_0 = io_wakeup_ports_4_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_pred_wakeup_port_valid_0 = io_pred_wakeup_port_valid; // @[issue-slot.scala:49:7] wire [4:0] io_pred_wakeup_port_bits_0 = io_pred_wakeup_port_bits; // @[issue-slot.scala:49:7] wire [2:0] io_child_rebusys_0 = io_child_rebusys; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire next_uop_out_iw_issued_partial_agen = 1'h0; // @[util.scala:104:23] wire next_uop_out_iw_issued_partial_dgen = 1'h0; // @[util.scala:104:23] wire next_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:59:28] wire next_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:59:28] wire prs1_rebusys_1 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_2 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_3 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_4 = 1'h0; // @[issue-slot.scala:102:91] wire prs2_rebusys_1 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_2 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_3 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_4 = 1'h0; // @[issue-slot.scala:103:91] wire _next_uop_iw_p1_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _next_uop_iw_p2_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _next_uop_iw_p3_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _iss_ready_T_6 = 1'h0; // @[issue-slot.scala:136:131] wire agen_ready = 1'h0; // @[issue-slot.scala:137:114] wire dgen_ready = 1'h0; // @[issue-slot.scala:138:114] wire [2:0] io_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-slot.scala:49:7] wire [2:0] _next_uop_iw_p1_speculative_child_T_1 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _next_uop_iw_p2_speculative_child_T_1 = 3'h0; // @[Mux.scala:30:73] wire io_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire _iss_ready_T_7 = 1'h1; // @[issue-slot.scala:136:110] wire [2:0] io_wakeup_ports_2_bits_speculative_mask = 3'h1; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_speculative_mask = 3'h2; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_speculative_mask = 3'h4; // @[issue-slot.scala:49:7] wire _io_will_be_valid_T_1; // @[issue-slot.scala:65:34] wire _io_request_T_4; // @[issue-slot.scala:140:51] wire [31:0] next_uop_inst; // @[issue-slot.scala:59:28] wire [31:0] next_uop_debug_inst; // @[issue-slot.scala:59:28] wire next_uop_is_rvc; // @[issue-slot.scala:59:28] wire [39:0] next_uop_debug_pc; // @[issue-slot.scala:59:28] wire next_uop_iq_type_0; // @[issue-slot.scala:59:28] wire next_uop_iq_type_1; // @[issue-slot.scala:59:28] wire next_uop_iq_type_2; // @[issue-slot.scala:59:28] wire next_uop_iq_type_3; // @[issue-slot.scala:59:28] wire next_uop_fu_code_0; // @[issue-slot.scala:59:28] wire next_uop_fu_code_1; // @[issue-slot.scala:59:28] wire next_uop_fu_code_2; // @[issue-slot.scala:59:28] wire next_uop_fu_code_3; // @[issue-slot.scala:59:28] wire next_uop_fu_code_4; // @[issue-slot.scala:59:28] wire next_uop_fu_code_5; // @[issue-slot.scala:59:28] wire next_uop_fu_code_6; // @[issue-slot.scala:59:28] wire next_uop_fu_code_7; // @[issue-slot.scala:59:28] wire next_uop_fu_code_8; // @[issue-slot.scala:59:28] wire next_uop_fu_code_9; // @[issue-slot.scala:59:28] wire next_uop_iw_issued; // @[issue-slot.scala:59:28] wire [2:0] next_uop_iw_p1_speculative_child; // @[issue-slot.scala:59:28] wire [2:0] next_uop_iw_p2_speculative_child; // @[issue-slot.scala:59:28] wire next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:59:28] wire next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:59:28] wire next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:59:28] wire [2:0] next_uop_dis_col_sel; // @[issue-slot.scala:59:28] wire [15:0] next_uop_br_mask; // @[issue-slot.scala:59:28] wire [3:0] next_uop_br_tag; // @[issue-slot.scala:59:28] wire [3:0] next_uop_br_type; // @[issue-slot.scala:59:28] wire next_uop_is_sfb; // @[issue-slot.scala:59:28] wire next_uop_is_fence; // @[issue-slot.scala:59:28] wire next_uop_is_fencei; // @[issue-slot.scala:59:28] wire next_uop_is_sfence; // @[issue-slot.scala:59:28] wire next_uop_is_amo; // @[issue-slot.scala:59:28] wire next_uop_is_eret; // @[issue-slot.scala:59:28] wire next_uop_is_sys_pc2epc; // @[issue-slot.scala:59:28] wire next_uop_is_rocc; // @[issue-slot.scala:59:28] wire next_uop_is_mov; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ftq_idx; // @[issue-slot.scala:59:28] wire next_uop_edge_inst; // @[issue-slot.scala:59:28] wire [5:0] next_uop_pc_lob; // @[issue-slot.scala:59:28] wire next_uop_taken; // @[issue-slot.scala:59:28] wire next_uop_imm_rename; // @[issue-slot.scala:59:28] wire [2:0] next_uop_imm_sel; // @[issue-slot.scala:59:28] wire [4:0] next_uop_pimm; // @[issue-slot.scala:59:28] wire [19:0] next_uop_imm_packed; // @[issue-slot.scala:59:28] wire [1:0] next_uop_op1_sel; // @[issue-slot.scala:59:28] wire [2:0] next_uop_op2_sel; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ldst; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_wen; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren1; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren2; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren3; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_swap12; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_swap23; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fromint; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_toint; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fma; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_div; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_wflags; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_vec; // @[issue-slot.scala:59:28] wire [6:0] next_uop_rob_idx; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ldq_idx; // @[issue-slot.scala:59:28] wire [4:0] next_uop_stq_idx; // @[issue-slot.scala:59:28] wire [1:0] next_uop_rxq_idx; // @[issue-slot.scala:59:28] wire [6:0] next_uop_pdst; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs1; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs2; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs3; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ppred; // @[issue-slot.scala:59:28] wire next_uop_prs1_busy; // @[issue-slot.scala:59:28] wire next_uop_prs2_busy; // @[issue-slot.scala:59:28] wire next_uop_prs3_busy; // @[issue-slot.scala:59:28] wire next_uop_ppred_busy; // @[issue-slot.scala:59:28] wire [6:0] next_uop_stale_pdst; // @[issue-slot.scala:59:28] wire next_uop_exception; // @[issue-slot.scala:59:28] wire [63:0] next_uop_exc_cause; // @[issue-slot.scala:59:28] wire [4:0] next_uop_mem_cmd; // @[issue-slot.scala:59:28] wire [1:0] next_uop_mem_size; // @[issue-slot.scala:59:28] wire next_uop_mem_signed; // @[issue-slot.scala:59:28] wire next_uop_uses_ldq; // @[issue-slot.scala:59:28] wire next_uop_uses_stq; // @[issue-slot.scala:59:28] wire next_uop_is_unique; // @[issue-slot.scala:59:28] wire next_uop_flush_on_commit; // @[issue-slot.scala:59:28] wire [2:0] next_uop_csr_cmd; // @[issue-slot.scala:59:28] wire next_uop_ldst_is_rs1; // @[issue-slot.scala:59:28] wire [5:0] next_uop_ldst; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs1; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs2; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs3; // @[issue-slot.scala:59:28] wire [1:0] next_uop_dst_rtype; // @[issue-slot.scala:59:28] wire [1:0] next_uop_lrs1_rtype; // @[issue-slot.scala:59:28] wire [1:0] next_uop_lrs2_rtype; // @[issue-slot.scala:59:28] wire next_uop_frs3_en; // @[issue-slot.scala:59:28] wire next_uop_fcn_dw; // @[issue-slot.scala:59:28] wire [4:0] next_uop_fcn_op; // @[issue-slot.scala:59:28] wire next_uop_fp_val; // @[issue-slot.scala:59:28] wire [2:0] next_uop_fp_rm; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_typ; // @[issue-slot.scala:59:28] wire next_uop_xcpt_pf_if; // @[issue-slot.scala:59:28] wire next_uop_xcpt_ae_if; // @[issue-slot.scala:59:28] wire next_uop_xcpt_ma_if; // @[issue-slot.scala:59:28] wire next_uop_bp_debug_if; // @[issue-slot.scala:59:28] wire next_uop_bp_xcpt_if; // @[issue-slot.scala:59:28] wire [2:0] next_uop_debug_fsrc; // @[issue-slot.scala:59:28] wire [2:0] next_uop_debug_tsrc; // @[issue-slot.scala:59:28] wire io_iss_uop_iq_type_0_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_0_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_4_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_5_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_6_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_7_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_8_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_9_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7] wire [31:0] io_iss_uop_inst_0; // @[issue-slot.scala:49:7] wire [31:0] io_iss_uop_debug_inst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_rvc_0; // @[issue-slot.scala:49:7] wire [39:0] io_iss_uop_debug_pc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_dis_col_sel_0; // @[issue-slot.scala:49:7] wire [15:0] io_iss_uop_br_mask_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_br_tag_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_br_type_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sfb_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_fence_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_fencei_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sfence_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_amo_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_eret_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_rocc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_mov_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ftq_idx_0; // @[issue-slot.scala:49:7] wire io_iss_uop_edge_inst_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_pc_lob_0; // @[issue-slot.scala:49:7] wire io_iss_uop_taken_0; // @[issue-slot.scala:49:7] wire io_iss_uop_imm_rename_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_imm_sel_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_pimm_0; // @[issue-slot.scala:49:7] wire [19:0] io_iss_uop_imm_packed_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_op1_sel_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_op2_sel_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_rob_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ldq_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_stq_idx_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_rxq_idx_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_pdst_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs1_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs2_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs3_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ppred_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs1_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs2_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs3_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_ppred_busy_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_stale_pdst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_exception_0; // @[issue-slot.scala:49:7] wire [63:0] io_iss_uop_exc_cause_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_mem_cmd_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_mem_size_0; // @[issue-slot.scala:49:7] wire io_iss_uop_mem_signed_0; // @[issue-slot.scala:49:7] wire io_iss_uop_uses_ldq_0; // @[issue-slot.scala:49:7] wire io_iss_uop_uses_stq_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_unique_0; // @[issue-slot.scala:49:7] wire io_iss_uop_flush_on_commit_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_csr_cmd_0; // @[issue-slot.scala:49:7] wire io_iss_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_ldst_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs2_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs3_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_dst_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7] wire io_iss_uop_frs3_en_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fcn_dw_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_fcn_op_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_val_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_fp_rm_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_typ_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_bp_debug_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_debug_fsrc_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_debug_tsrc_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_0_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_1_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_2_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_0_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_1_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_2_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_4_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_5_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_6_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_7_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_8_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_9_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:49:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:49:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_dis_col_sel_0; // @[issue-slot.scala:49:7] wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_br_type_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sfence_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_eret_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_rocc_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_mov_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:49:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:49:7] wire io_out_uop_taken_0; // @[issue-slot.scala:49:7] wire io_out_uop_imm_rename_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_imm_sel_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_pimm_0; // @[issue-slot.scala:49:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_op1_sel_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_op2_sel_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:49:7] wire io_out_uop_exception_0; // @[issue-slot.scala:49:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:49:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:49:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:49:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:49:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_csr_cmd_0; // @[issue-slot.scala:49:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:49:7] wire io_out_uop_fcn_dw_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_fcn_op_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_fp_rm_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_typ_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:49:7] wire io_valid_0; // @[issue-slot.scala:49:7] wire io_will_be_valid_0; // @[issue-slot.scala:49:7] wire io_request_0; // @[issue-slot.scala:49:7] reg slot_valid; // @[issue-slot.scala:55:27] assign io_valid_0 = slot_valid; // @[issue-slot.scala:49:7, :55:27] reg [31:0] slot_uop_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:49:7, :56:21] wire [31:0] next_uop_out_inst = slot_uop_inst; // @[util.scala:104:23] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:49:7, :56:21] wire [31:0] next_uop_out_debug_inst = slot_uop_debug_inst; // @[util.scala:104:23] reg slot_uop_is_rvc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_rvc = slot_uop_is_rvc; // @[util.scala:104:23] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:49:7, :56:21] wire [39:0] next_uop_out_debug_pc = slot_uop_debug_pc; // @[util.scala:104:23] reg slot_uop_iq_type_0; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_0_0 = slot_uop_iq_type_0; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_0 = slot_uop_iq_type_0; // @[util.scala:104:23] reg slot_uop_iq_type_1; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_1_0 = slot_uop_iq_type_1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_1 = slot_uop_iq_type_1; // @[util.scala:104:23] reg slot_uop_iq_type_2; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_2_0 = slot_uop_iq_type_2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_2 = slot_uop_iq_type_2; // @[util.scala:104:23] reg slot_uop_iq_type_3; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_3_0 = slot_uop_iq_type_3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_3 = slot_uop_iq_type_3; // @[util.scala:104:23] reg slot_uop_fu_code_0; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_0_0 = slot_uop_fu_code_0; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_0 = slot_uop_fu_code_0; // @[util.scala:104:23] reg slot_uop_fu_code_1; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_1_0 = slot_uop_fu_code_1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_1 = slot_uop_fu_code_1; // @[util.scala:104:23] reg slot_uop_fu_code_2; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_2_0 = slot_uop_fu_code_2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_2 = slot_uop_fu_code_2; // @[util.scala:104:23] reg slot_uop_fu_code_3; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_3_0 = slot_uop_fu_code_3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_3 = slot_uop_fu_code_3; // @[util.scala:104:23] reg slot_uop_fu_code_4; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_4_0 = slot_uop_fu_code_4; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_4 = slot_uop_fu_code_4; // @[util.scala:104:23] reg slot_uop_fu_code_5; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_5_0 = slot_uop_fu_code_5; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_5 = slot_uop_fu_code_5; // @[util.scala:104:23] reg slot_uop_fu_code_6; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_6_0 = slot_uop_fu_code_6; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_6 = slot_uop_fu_code_6; // @[util.scala:104:23] reg slot_uop_fu_code_7; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_7_0 = slot_uop_fu_code_7; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_7 = slot_uop_fu_code_7; // @[util.scala:104:23] reg slot_uop_fu_code_8; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_8_0 = slot_uop_fu_code_8; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_8 = slot_uop_fu_code_8; // @[util.scala:104:23] reg slot_uop_fu_code_9; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_9_0 = slot_uop_fu_code_9; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_9 = slot_uop_fu_code_9; // @[util.scala:104:23] reg slot_uop_iw_issued; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_issued_0 = slot_uop_iw_issued; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_issued = slot_uop_iw_issued; // @[util.scala:104:23] reg [2:0] slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p1_speculative_child_0 = slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_iw_p1_speculative_child = slot_uop_iw_p1_speculative_child; // @[util.scala:104:23] reg [2:0] slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p2_speculative_child_0 = slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_iw_p2_speculative_child = slot_uop_iw_p2_speculative_child; // @[util.scala:104:23] reg slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p1_bypass_hint_0 = slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p1_bypass_hint = slot_uop_iw_p1_bypass_hint; // @[util.scala:104:23] reg slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p2_bypass_hint_0 = slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p2_bypass_hint = slot_uop_iw_p2_bypass_hint; // @[util.scala:104:23] reg slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p3_bypass_hint_0 = slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p3_bypass_hint = slot_uop_iw_p3_bypass_hint; // @[util.scala:104:23] reg [2:0] slot_uop_dis_col_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_dis_col_sel_0 = slot_uop_dis_col_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_dis_col_sel = slot_uop_dis_col_sel; // @[util.scala:104:23] reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:56:21] assign io_iss_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:49:7, :56:21] reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:56:21] assign io_iss_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_br_tag = slot_uop_br_tag; // @[util.scala:104:23] reg [3:0] slot_uop_br_type; // @[issue-slot.scala:56:21] assign io_iss_uop_br_type_0 = slot_uop_br_type; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_br_type = slot_uop_br_type; // @[util.scala:104:23] reg slot_uop_is_sfb; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sfb = slot_uop_is_sfb; // @[util.scala:104:23] reg slot_uop_is_fence; // @[issue-slot.scala:56:21] assign io_iss_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_fence = slot_uop_is_fence; // @[util.scala:104:23] reg slot_uop_is_fencei; // @[issue-slot.scala:56:21] assign io_iss_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_fencei = slot_uop_is_fencei; // @[util.scala:104:23] reg slot_uop_is_sfence; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sfence_0 = slot_uop_is_sfence; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sfence = slot_uop_is_sfence; // @[util.scala:104:23] reg slot_uop_is_amo; // @[issue-slot.scala:56:21] assign io_iss_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_amo = slot_uop_is_amo; // @[util.scala:104:23] reg slot_uop_is_eret; // @[issue-slot.scala:56:21] assign io_iss_uop_is_eret_0 = slot_uop_is_eret; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_eret = slot_uop_is_eret; // @[util.scala:104:23] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sys_pc2epc = slot_uop_is_sys_pc2epc; // @[util.scala:104:23] reg slot_uop_is_rocc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_rocc_0 = slot_uop_is_rocc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_rocc = slot_uop_is_rocc; // @[util.scala:104:23] reg slot_uop_is_mov; // @[issue-slot.scala:56:21] assign io_iss_uop_is_mov_0 = slot_uop_is_mov; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_mov = slot_uop_is_mov; // @[util.scala:104:23] reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ftq_idx = slot_uop_ftq_idx; // @[util.scala:104:23] reg slot_uop_edge_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_edge_inst = slot_uop_edge_inst; // @[util.scala:104:23] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:56:21] assign io_iss_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_pc_lob = slot_uop_pc_lob; // @[util.scala:104:23] reg slot_uop_taken; // @[issue-slot.scala:56:21] assign io_iss_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_taken = slot_uop_taken; // @[util.scala:104:23] reg slot_uop_imm_rename; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_rename_0 = slot_uop_imm_rename; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_imm_rename = slot_uop_imm_rename; // @[util.scala:104:23] reg [2:0] slot_uop_imm_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_sel_0 = slot_uop_imm_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_imm_sel = slot_uop_imm_sel; // @[util.scala:104:23] reg [4:0] slot_uop_pimm; // @[issue-slot.scala:56:21] assign io_iss_uop_pimm_0 = slot_uop_pimm; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_pimm = slot_uop_pimm; // @[util.scala:104:23] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:49:7, :56:21] wire [19:0] next_uop_out_imm_packed = slot_uop_imm_packed; // @[util.scala:104:23] reg [1:0] slot_uop_op1_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_op1_sel_0 = slot_uop_op1_sel; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_op1_sel = slot_uop_op1_sel; // @[util.scala:104:23] reg [2:0] slot_uop_op2_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_op2_sel_0 = slot_uop_op2_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_op2_sel = slot_uop_op2_sel; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ldst_0 = slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ldst = slot_uop_fp_ctrl_ldst; // @[util.scala:104:23] reg slot_uop_fp_ctrl_wen; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_wen_0 = slot_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_wen = slot_uop_fp_ctrl_wen; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren1_0 = slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren1 = slot_uop_fp_ctrl_ren1; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren2_0 = slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren2 = slot_uop_fp_ctrl_ren2; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren3_0 = slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren3 = slot_uop_fp_ctrl_ren3; // @[util.scala:104:23] reg slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_swap12_0 = slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_swap12 = slot_uop_fp_ctrl_swap12; // @[util.scala:104:23] reg slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_swap23_0 = slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_swap23 = slot_uop_fp_ctrl_swap23; // @[util.scala:104:23] reg [1:0] slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_typeTagIn_0 = slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_ctrl_typeTagIn = slot_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23] reg [1:0] slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_typeTagOut_0 = slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_ctrl_typeTagOut = slot_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fromint_0 = slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fromint = slot_uop_fp_ctrl_fromint; // @[util.scala:104:23] reg slot_uop_fp_ctrl_toint; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_toint_0 = slot_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_toint = slot_uop_fp_ctrl_toint; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fastpipe_0 = slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fastpipe = slot_uop_fp_ctrl_fastpipe; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fma; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fma_0 = slot_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fma = slot_uop_fp_ctrl_fma; // @[util.scala:104:23] reg slot_uop_fp_ctrl_div; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_div_0 = slot_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_div = slot_uop_fp_ctrl_div; // @[util.scala:104:23] reg slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_sqrt_0 = slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_sqrt = slot_uop_fp_ctrl_sqrt; // @[util.scala:104:23] reg slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_wflags_0 = slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_wflags = slot_uop_fp_ctrl_wflags; // @[util.scala:104:23] reg slot_uop_fp_ctrl_vec; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_vec_0 = slot_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_vec = slot_uop_fp_ctrl_vec; // @[util.scala:104:23] reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_rob_idx = slot_uop_rob_idx; // @[util.scala:104:23] reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ldq_idx = slot_uop_ldq_idx; // @[util.scala:104:23] reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_stq_idx = slot_uop_stq_idx; // @[util.scala:104:23] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_rxq_idx = slot_uop_rxq_idx; // @[util.scala:104:23] reg [6:0] slot_uop_pdst; // @[issue-slot.scala:56:21] assign io_iss_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_pdst = slot_uop_pdst; // @[util.scala:104:23] reg [6:0] slot_uop_prs1; // @[issue-slot.scala:56:21] assign io_iss_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs1 = slot_uop_prs1; // @[util.scala:104:23] reg [6:0] slot_uop_prs2; // @[issue-slot.scala:56:21] assign io_iss_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs2 = slot_uop_prs2; // @[util.scala:104:23] reg [6:0] slot_uop_prs3; // @[issue-slot.scala:56:21] assign io_iss_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs3 = slot_uop_prs3; // @[util.scala:104:23] reg [4:0] slot_uop_ppred; // @[issue-slot.scala:56:21] assign io_iss_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ppred = slot_uop_ppred; // @[util.scala:104:23] reg slot_uop_prs1_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs1_busy = slot_uop_prs1_busy; // @[util.scala:104:23] reg slot_uop_prs2_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs2_busy = slot_uop_prs2_busy; // @[util.scala:104:23] reg slot_uop_prs3_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs3_busy = slot_uop_prs3_busy; // @[util.scala:104:23] reg slot_uop_ppred_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_ppred_busy = slot_uop_ppred_busy; // @[util.scala:104:23] wire _iss_ready_T_3 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :136:88] wire _agen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :137:95] wire _dgen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :138:95] reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:56:21] assign io_iss_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_stale_pdst = slot_uop_stale_pdst; // @[util.scala:104:23] reg slot_uop_exception; // @[issue-slot.scala:56:21] assign io_iss_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_exception = slot_uop_exception; // @[util.scala:104:23] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:56:21] assign io_iss_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:49:7, :56:21] wire [63:0] next_uop_out_exc_cause = slot_uop_exc_cause; // @[util.scala:104:23] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_mem_cmd = slot_uop_mem_cmd; // @[util.scala:104:23] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_mem_size = slot_uop_mem_size; // @[util.scala:104:23] reg slot_uop_mem_signed; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_mem_signed = slot_uop_mem_signed; // @[util.scala:104:23] reg slot_uop_uses_ldq; // @[issue-slot.scala:56:21] assign io_iss_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_uses_ldq = slot_uop_uses_ldq; // @[util.scala:104:23] reg slot_uop_uses_stq; // @[issue-slot.scala:56:21] assign io_iss_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_uses_stq = slot_uop_uses_stq; // @[util.scala:104:23] reg slot_uop_is_unique; // @[issue-slot.scala:56:21] assign io_iss_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_unique = slot_uop_is_unique; // @[util.scala:104:23] reg slot_uop_flush_on_commit; // @[issue-slot.scala:56:21] assign io_iss_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_flush_on_commit = slot_uop_flush_on_commit; // @[util.scala:104:23] reg [2:0] slot_uop_csr_cmd; // @[issue-slot.scala:56:21] assign io_iss_uop_csr_cmd_0 = slot_uop_csr_cmd; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_csr_cmd = slot_uop_csr_cmd; // @[util.scala:104:23] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:56:21] assign io_iss_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_ldst_is_rs1 = slot_uop_ldst_is_rs1; // @[util.scala:104:23] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:56:21] assign io_iss_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_ldst = slot_uop_ldst; // @[util.scala:104:23] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs1 = slot_uop_lrs1; // @[util.scala:104:23] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs2 = slot_uop_lrs2; // @[util.scala:104:23] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs3 = slot_uop_lrs3; // @[util.scala:104:23] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_dst_rtype = slot_uop_dst_rtype; // @[util.scala:104:23] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs1_rtype_0 = slot_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_lrs1_rtype = slot_uop_lrs1_rtype; // @[util.scala:104:23] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs2_rtype_0 = slot_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_lrs2_rtype = slot_uop_lrs2_rtype; // @[util.scala:104:23] reg slot_uop_frs3_en; // @[issue-slot.scala:56:21] assign io_iss_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_frs3_en = slot_uop_frs3_en; // @[util.scala:104:23] reg slot_uop_fcn_dw; // @[issue-slot.scala:56:21] assign io_iss_uop_fcn_dw_0 = slot_uop_fcn_dw; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fcn_dw = slot_uop_fcn_dw; // @[util.scala:104:23] reg [4:0] slot_uop_fcn_op; // @[issue-slot.scala:56:21] assign io_iss_uop_fcn_op_0 = slot_uop_fcn_op; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_fcn_op = slot_uop_fcn_op; // @[util.scala:104:23] reg slot_uop_fp_val; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_val = slot_uop_fp_val; // @[util.scala:104:23] reg [2:0] slot_uop_fp_rm; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_rm_0 = slot_uop_fp_rm; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_fp_rm = slot_uop_fp_rm; // @[util.scala:104:23] reg [1:0] slot_uop_fp_typ; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_typ_0 = slot_uop_fp_typ; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_typ = slot_uop_fp_typ; // @[util.scala:104:23] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_pf_if = slot_uop_xcpt_pf_if; // @[util.scala:104:23] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_ae_if = slot_uop_xcpt_ae_if; // @[util.scala:104:23] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_ma_if = slot_uop_xcpt_ma_if; // @[util.scala:104:23] reg slot_uop_bp_debug_if; // @[issue-slot.scala:56:21] assign io_iss_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_bp_debug_if = slot_uop_bp_debug_if; // @[util.scala:104:23] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:56:21] assign io_iss_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_bp_xcpt_if = slot_uop_bp_xcpt_if; // @[util.scala:104:23] reg [2:0] slot_uop_debug_fsrc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_debug_fsrc = slot_uop_debug_fsrc; // @[util.scala:104:23] reg [2:0] slot_uop_debug_tsrc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_debug_tsrc = slot_uop_debug_tsrc; // @[util.scala:104:23] wire next_valid; // @[issue-slot.scala:58:28] assign next_uop_inst = next_uop_out_inst; // @[util.scala:104:23] assign next_uop_debug_inst = next_uop_out_debug_inst; // @[util.scala:104:23] assign next_uop_is_rvc = next_uop_out_is_rvc; // @[util.scala:104:23] assign next_uop_debug_pc = next_uop_out_debug_pc; // @[util.scala:104:23] assign next_uop_iq_type_0 = next_uop_out_iq_type_0; // @[util.scala:104:23] assign next_uop_iq_type_1 = next_uop_out_iq_type_1; // @[util.scala:104:23] assign next_uop_iq_type_2 = next_uop_out_iq_type_2; // @[util.scala:104:23] assign next_uop_iq_type_3 = next_uop_out_iq_type_3; // @[util.scala:104:23] assign next_uop_fu_code_0 = next_uop_out_fu_code_0; // @[util.scala:104:23] assign next_uop_fu_code_1 = next_uop_out_fu_code_1; // @[util.scala:104:23] assign next_uop_fu_code_2 = next_uop_out_fu_code_2; // @[util.scala:104:23] assign next_uop_fu_code_3 = next_uop_out_fu_code_3; // @[util.scala:104:23] assign next_uop_fu_code_4 = next_uop_out_fu_code_4; // @[util.scala:104:23] assign next_uop_fu_code_5 = next_uop_out_fu_code_5; // @[util.scala:104:23] assign next_uop_fu_code_6 = next_uop_out_fu_code_6; // @[util.scala:104:23] assign next_uop_fu_code_7 = next_uop_out_fu_code_7; // @[util.scala:104:23] assign next_uop_fu_code_8 = next_uop_out_fu_code_8; // @[util.scala:104:23] assign next_uop_fu_code_9 = next_uop_out_fu_code_9; // @[util.scala:104:23] wire [15:0] _next_uop_out_br_mask_T_1; // @[util.scala:93:25] assign next_uop_dis_col_sel = next_uop_out_dis_col_sel; // @[util.scala:104:23] assign next_uop_br_mask = next_uop_out_br_mask; // @[util.scala:104:23] assign next_uop_br_tag = next_uop_out_br_tag; // @[util.scala:104:23] assign next_uop_br_type = next_uop_out_br_type; // @[util.scala:104:23] assign next_uop_is_sfb = next_uop_out_is_sfb; // @[util.scala:104:23] assign next_uop_is_fence = next_uop_out_is_fence; // @[util.scala:104:23] assign next_uop_is_fencei = next_uop_out_is_fencei; // @[util.scala:104:23] assign next_uop_is_sfence = next_uop_out_is_sfence; // @[util.scala:104:23] assign next_uop_is_amo = next_uop_out_is_amo; // @[util.scala:104:23] assign next_uop_is_eret = next_uop_out_is_eret; // @[util.scala:104:23] assign next_uop_is_sys_pc2epc = next_uop_out_is_sys_pc2epc; // @[util.scala:104:23] assign next_uop_is_rocc = next_uop_out_is_rocc; // @[util.scala:104:23] assign next_uop_is_mov = next_uop_out_is_mov; // @[util.scala:104:23] assign next_uop_ftq_idx = next_uop_out_ftq_idx; // @[util.scala:104:23] assign next_uop_edge_inst = next_uop_out_edge_inst; // @[util.scala:104:23] assign next_uop_pc_lob = next_uop_out_pc_lob; // @[util.scala:104:23] assign next_uop_taken = next_uop_out_taken; // @[util.scala:104:23] assign next_uop_imm_rename = next_uop_out_imm_rename; // @[util.scala:104:23] assign next_uop_imm_sel = next_uop_out_imm_sel; // @[util.scala:104:23] assign next_uop_pimm = next_uop_out_pimm; // @[util.scala:104:23] assign next_uop_imm_packed = next_uop_out_imm_packed; // @[util.scala:104:23] assign next_uop_op1_sel = next_uop_out_op1_sel; // @[util.scala:104:23] assign next_uop_op2_sel = next_uop_out_op2_sel; // @[util.scala:104:23] assign next_uop_fp_ctrl_ldst = next_uop_out_fp_ctrl_ldst; // @[util.scala:104:23] assign next_uop_fp_ctrl_wen = next_uop_out_fp_ctrl_wen; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren1 = next_uop_out_fp_ctrl_ren1; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren2 = next_uop_out_fp_ctrl_ren2; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren3 = next_uop_out_fp_ctrl_ren3; // @[util.scala:104:23] assign next_uop_fp_ctrl_swap12 = next_uop_out_fp_ctrl_swap12; // @[util.scala:104:23] assign next_uop_fp_ctrl_swap23 = next_uop_out_fp_ctrl_swap23; // @[util.scala:104:23] assign next_uop_fp_ctrl_typeTagIn = next_uop_out_fp_ctrl_typeTagIn; // @[util.scala:104:23] assign next_uop_fp_ctrl_typeTagOut = next_uop_out_fp_ctrl_typeTagOut; // @[util.scala:104:23] assign next_uop_fp_ctrl_fromint = next_uop_out_fp_ctrl_fromint; // @[util.scala:104:23] assign next_uop_fp_ctrl_toint = next_uop_out_fp_ctrl_toint; // @[util.scala:104:23] assign next_uop_fp_ctrl_fastpipe = next_uop_out_fp_ctrl_fastpipe; // @[util.scala:104:23] assign next_uop_fp_ctrl_fma = next_uop_out_fp_ctrl_fma; // @[util.scala:104:23] assign next_uop_fp_ctrl_div = next_uop_out_fp_ctrl_div; // @[util.scala:104:23] assign next_uop_fp_ctrl_sqrt = next_uop_out_fp_ctrl_sqrt; // @[util.scala:104:23] assign next_uop_fp_ctrl_wflags = next_uop_out_fp_ctrl_wflags; // @[util.scala:104:23] assign next_uop_fp_ctrl_vec = next_uop_out_fp_ctrl_vec; // @[util.scala:104:23] assign next_uop_rob_idx = next_uop_out_rob_idx; // @[util.scala:104:23] assign next_uop_ldq_idx = next_uop_out_ldq_idx; // @[util.scala:104:23] assign next_uop_stq_idx = next_uop_out_stq_idx; // @[util.scala:104:23] assign next_uop_rxq_idx = next_uop_out_rxq_idx; // @[util.scala:104:23] assign next_uop_pdst = next_uop_out_pdst; // @[util.scala:104:23] assign next_uop_prs1 = next_uop_out_prs1; // @[util.scala:104:23] assign next_uop_prs2 = next_uop_out_prs2; // @[util.scala:104:23] assign next_uop_prs3 = next_uop_out_prs3; // @[util.scala:104:23] assign next_uop_ppred = next_uop_out_ppred; // @[util.scala:104:23] assign next_uop_stale_pdst = next_uop_out_stale_pdst; // @[util.scala:104:23] assign next_uop_exception = next_uop_out_exception; // @[util.scala:104:23] assign next_uop_exc_cause = next_uop_out_exc_cause; // @[util.scala:104:23] assign next_uop_mem_cmd = next_uop_out_mem_cmd; // @[util.scala:104:23] assign next_uop_mem_size = next_uop_out_mem_size; // @[util.scala:104:23] assign next_uop_mem_signed = next_uop_out_mem_signed; // @[util.scala:104:23] assign next_uop_uses_ldq = next_uop_out_uses_ldq; // @[util.scala:104:23] assign next_uop_uses_stq = next_uop_out_uses_stq; // @[util.scala:104:23] assign next_uop_is_unique = next_uop_out_is_unique; // @[util.scala:104:23] assign next_uop_flush_on_commit = next_uop_out_flush_on_commit; // @[util.scala:104:23] assign next_uop_csr_cmd = next_uop_out_csr_cmd; // @[util.scala:104:23] assign next_uop_ldst_is_rs1 = next_uop_out_ldst_is_rs1; // @[util.scala:104:23] assign next_uop_ldst = next_uop_out_ldst; // @[util.scala:104:23] assign next_uop_lrs1 = next_uop_out_lrs1; // @[util.scala:104:23] assign next_uop_lrs2 = next_uop_out_lrs2; // @[util.scala:104:23] assign next_uop_lrs3 = next_uop_out_lrs3; // @[util.scala:104:23] assign next_uop_dst_rtype = next_uop_out_dst_rtype; // @[util.scala:104:23] assign next_uop_lrs1_rtype = next_uop_out_lrs1_rtype; // @[util.scala:104:23] assign next_uop_lrs2_rtype = next_uop_out_lrs2_rtype; // @[util.scala:104:23] assign next_uop_frs3_en = next_uop_out_frs3_en; // @[util.scala:104:23] assign next_uop_fcn_dw = next_uop_out_fcn_dw; // @[util.scala:104:23] assign next_uop_fcn_op = next_uop_out_fcn_op; // @[util.scala:104:23] assign next_uop_fp_val = next_uop_out_fp_val; // @[util.scala:104:23] assign next_uop_fp_rm = next_uop_out_fp_rm; // @[util.scala:104:23] assign next_uop_fp_typ = next_uop_out_fp_typ; // @[util.scala:104:23] assign next_uop_xcpt_pf_if = next_uop_out_xcpt_pf_if; // @[util.scala:104:23] assign next_uop_xcpt_ae_if = next_uop_out_xcpt_ae_if; // @[util.scala:104:23] assign next_uop_xcpt_ma_if = next_uop_out_xcpt_ma_if; // @[util.scala:104:23] assign next_uop_bp_debug_if = next_uop_out_bp_debug_if; // @[util.scala:104:23] assign next_uop_bp_xcpt_if = next_uop_out_bp_xcpt_if; // @[util.scala:104:23] assign next_uop_debug_fsrc = next_uop_out_debug_fsrc; // @[util.scala:104:23] assign next_uop_debug_tsrc = next_uop_out_debug_tsrc; // @[util.scala:104:23] wire [15:0] _next_uop_out_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _next_uop_out_br_mask_T_1 = slot_uop_br_mask & _next_uop_out_br_mask_T; // @[util.scala:93:{25,27}] assign next_uop_out_br_mask = _next_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23] assign io_out_uop_inst_0 = next_uop_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_inst_0 = next_uop_debug_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_rvc_0 = next_uop_is_rvc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_pc_0 = next_uop_debug_pc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_0_0 = next_uop_iq_type_0; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_1_0 = next_uop_iq_type_1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_2_0 = next_uop_iq_type_2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_3_0 = next_uop_iq_type_3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_0_0 = next_uop_fu_code_0; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_1_0 = next_uop_fu_code_1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_2_0 = next_uop_fu_code_2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_3_0 = next_uop_fu_code_3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_4_0 = next_uop_fu_code_4; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_5_0 = next_uop_fu_code_5; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_6_0 = next_uop_fu_code_6; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_7_0 = next_uop_fu_code_7; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_8_0 = next_uop_fu_code_8; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_9_0 = next_uop_fu_code_9; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_issued_0 = next_uop_iw_issued; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p1_speculative_child_0 = next_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p2_speculative_child_0 = next_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p1_bypass_hint_0 = next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p2_bypass_hint_0 = next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p3_bypass_hint_0 = next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_dis_col_sel_0 = next_uop_dis_col_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_mask_0 = next_uop_br_mask; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_tag_0 = next_uop_br_tag; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_type_0 = next_uop_br_type; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sfb_0 = next_uop_is_sfb; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_fence_0 = next_uop_is_fence; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_fencei_0 = next_uop_is_fencei; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sfence_0 = next_uop_is_sfence; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_amo_0 = next_uop_is_amo; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_eret_0 = next_uop_is_eret; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sys_pc2epc_0 = next_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_rocc_0 = next_uop_is_rocc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_mov_0 = next_uop_is_mov; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ftq_idx_0 = next_uop_ftq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_edge_inst_0 = next_uop_edge_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pc_lob_0 = next_uop_pc_lob; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_taken_0 = next_uop_taken; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_rename_0 = next_uop_imm_rename; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_sel_0 = next_uop_imm_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pimm_0 = next_uop_pimm; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_packed_0 = next_uop_imm_packed; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_op1_sel_0 = next_uop_op1_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_op2_sel_0 = next_uop_op2_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ldst_0 = next_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_wen_0 = next_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren1_0 = next_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren2_0 = next_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren3_0 = next_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_swap12_0 = next_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_swap23_0 = next_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_typeTagIn_0 = next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_typeTagOut_0 = next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fromint_0 = next_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_toint_0 = next_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fastpipe_0 = next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fma_0 = next_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_div_0 = next_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_sqrt_0 = next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_wflags_0 = next_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_vec_0 = next_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_rob_idx_0 = next_uop_rob_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldq_idx_0 = next_uop_ldq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_stq_idx_0 = next_uop_stq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_rxq_idx_0 = next_uop_rxq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pdst_0 = next_uop_pdst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs1_0 = next_uop_prs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs2_0 = next_uop_prs2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs3_0 = next_uop_prs3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ppred_0 = next_uop_ppred; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs1_busy_0 = next_uop_prs1_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs2_busy_0 = next_uop_prs2_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs3_busy_0 = next_uop_prs3_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ppred_busy_0 = next_uop_ppred_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_stale_pdst_0 = next_uop_stale_pdst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_exception_0 = next_uop_exception; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_exc_cause_0 = next_uop_exc_cause; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_cmd_0 = next_uop_mem_cmd; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_size_0 = next_uop_mem_size; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_signed_0 = next_uop_mem_signed; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_uses_ldq_0 = next_uop_uses_ldq; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_uses_stq_0 = next_uop_uses_stq; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_unique_0 = next_uop_is_unique; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_flush_on_commit_0 = next_uop_flush_on_commit; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_csr_cmd_0 = next_uop_csr_cmd; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldst_is_rs1_0 = next_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldst_0 = next_uop_ldst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs1_0 = next_uop_lrs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs2_0 = next_uop_lrs2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs3_0 = next_uop_lrs3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_dst_rtype_0 = next_uop_dst_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs1_rtype_0 = next_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs2_rtype_0 = next_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_frs3_en_0 = next_uop_frs3_en; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fcn_dw_0 = next_uop_fcn_dw; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fcn_op_0 = next_uop_fcn_op; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_val_0 = next_uop_fp_val; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_rm_0 = next_uop_fp_rm; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_typ_0 = next_uop_fp_typ; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_pf_if_0 = next_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_ae_if_0 = next_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_ma_if_0 = next_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_bp_debug_if_0 = next_uop_bp_debug_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_bp_xcpt_if_0 = next_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_fsrc_0 = next_uop_debug_fsrc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_tsrc_0 = next_uop_debug_tsrc; // @[issue-slot.scala:49:7, :59:28] wire [15:0] _killed_T = io_brupdate_b1_mispredict_mask_0 & slot_uop_br_mask; // @[util.scala:126:51] wire _killed_T_1 = \|_killed_T; // @[util.scala:126:{51,59}] wire killed = _killed_T_1 \| io_kill_0; // @[util.scala:61:61, :126:59] wire _io_will_be_valid_T = ~killed; // @[util.scala:61:61] assign _io_will_be_valid_T_1 = next_valid & _io_will_be_valid_T; // @[issue-slot.scala:58:28, :65:{34,37}] assign io_will_be_valid_0 = _io_will_be_valid_T_1; // @[issue-slot.scala:49:7, :65:34] wire _slot_valid_T = ~killed; // @[util.scala:61:61] wire _slot_valid_T_1 = next_valid & _slot_valid_T; // @[issue-slot.scala:58:28, :74:{30,33}]
Generate the Verilog code corresponding to this FIRRTL code module TLUART : input clock : Clock input reset : Reset output auto : { int_xing_out : { sync : UInt<1>[1]}, flip control_xing_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, io_out : { txd : UInt<1>, flip rxd : UInt<1>}} inst buffer of TLBuffer_a29d64s12k1z2u connect buffer.clock, clock connect buffer.reset, reset inst intsource of IntSyncCrossingSource_n1x1_5 connect intsource.clock, clock connect intsource.reset, reset wire ioNodeOut : { txd : UInt<1>, flip rxd : UInt<1>} invalidate ioNodeOut.rxd invalidate ioNodeOut.txd wire intnodeOut : UInt<1>[1] invalidate intnodeOut[0] wire controlNodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate controlNodeIn.d.bits.corrupt invalidate controlNodeIn.d.bits.data invalidate controlNodeIn.d.bits.denied invalidate controlNodeIn.d.bits.sink invalidate controlNodeIn.d.bits.source invalidate controlNodeIn.d.bits.size invalidate controlNodeIn.d.bits.param invalidate controlNodeIn.d.bits.opcode invalidate controlNodeIn.d.valid invalidate controlNodeIn.d.ready invalidate controlNodeIn.a.bits.corrupt invalidate controlNodeIn.a.bits.data invalidate controlNodeIn.a.bits.mask invalidate controlNodeIn.a.bits.address invalidate controlNodeIn.a.bits.source invalidate controlNodeIn.a.bits.size invalidate controlNodeIn.a.bits.param invalidate controlNodeIn.a.bits.opcode invalidate controlNodeIn.a.valid invalidate controlNodeIn.a.ready inst monitor of TLMonitor_62 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, controlNodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, controlNodeIn.d.bits.data connect monitor.io.in.d.bits.denied, controlNodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, controlNodeIn.d.bits.sink connect monitor.io.in.d.bits.source, controlNodeIn.d.bits.source connect monitor.io.in.d.bits.size, controlNodeIn.d.bits.size connect monitor.io.in.d.bits.param, controlNodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, controlNodeIn.d.bits.opcode connect monitor.io.in.d.valid, controlNodeIn.d.valid connect monitor.io.in.d.ready, controlNodeIn.d.ready connect monitor.io.in.a.bits.corrupt, controlNodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, controlNodeIn.a.bits.data connect monitor.io.in.a.bits.mask, controlNodeIn.a.bits.mask connect monitor.io.in.a.bits.address, controlNodeIn.a.bits.address connect monitor.io.in.a.bits.source, controlNodeIn.a.bits.source connect monitor.io.in.a.bits.size, controlNodeIn.a.bits.size connect monitor.io.in.a.bits.param, controlNodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, controlNodeIn.a.bits.opcode connect monitor.io.in.a.valid, controlNodeIn.a.valid connect monitor.io.in.a.ready, controlNodeIn.a.ready wire controlXingOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate controlXingOut.d.bits.corrupt invalidate controlXingOut.d.bits.data invalidate controlXingOut.d.bits.denied invalidate controlXingOut.d.bits.sink invalidate controlXingOut.d.bits.source invalidate controlXingOut.d.bits.size invalidate controlXingOut.d.bits.param invalidate controlXingOut.d.bits.opcode invalidate controlXingOut.d.valid invalidate controlXingOut.d.ready invalidate controlXingOut.a.bits.corrupt invalidate controlXingOut.a.bits.data invalidate controlXingOut.a.bits.mask invalidate controlXingOut.a.bits.address invalidate controlXingOut.a.bits.source invalidate controlXingOut.a.bits.size invalidate controlXingOut.a.bits.param invalidate controlXingOut.a.bits.opcode invalidate controlXingOut.a.valid invalidate controlXingOut.a.ready wire controlXingIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate controlXingIn.d.bits.corrupt invalidate controlXingIn.d.bits.data invalidate controlXingIn.d.bits.denied invalidate controlXingIn.d.bits.sink invalidate controlXingIn.d.bits.source invalidate controlXingIn.d.bits.size invalidate controlXingIn.d.bits.param invalidate controlXingIn.d.bits.opcode invalidate controlXingIn.d.valid invalidate controlXingIn.d.ready invalidate controlXingIn.a.bits.corrupt invalidate controlXingIn.a.bits.data invalidate controlXingIn.a.bits.mask invalidate controlXingIn.a.bits.address invalidate controlXingIn.a.bits.source invalidate controlXingIn.a.bits.size invalidate controlXingIn.a.bits.param invalidate controlXingIn.a.bits.opcode invalidate controlXingIn.a.valid invalidate controlXingIn.a.ready connect controlXingOut, controlXingIn wire intXingOut : { sync : UInt<1>[1]} invalidate intXingOut.sync[0] wire intXingIn : { sync : UInt<1>[1]} invalidate intXingIn.sync[0] connect intXingOut, intXingIn connect intsource.auto.in[0], intnodeOut[0] connect buffer.auto.out.d, controlNodeIn.d connect controlNodeIn.a.bits, buffer.auto.out.a.bits connect controlNodeIn.a.valid, buffer.auto.out.a.valid connect buffer.auto.out.a.ready, controlNodeIn.a.ready connect buffer.auto.in, controlXingOut connect intXingIn, intsource.auto.out connect auto.io_out, ioNodeOut connect controlXingIn, auto.control_xing_in connect auto.int_xing_out, intXingOut inst txm of UARTTx connect txm.clock, clock connect txm.reset, reset inst txq of Queue8_UInt8 connect txq.clock, clock connect txq.reset, reset inst rxm of UARTRx connect rxm.clock, clock connect rxm.reset, reset inst rxq of Queue8_UInt8_1 connect rxq.clock, clock connect rxq.reset, reset regreset div : UInt<16>, clock, reset, UInt<16>(0h10f4) regreset txen : UInt<1>, clock, reset, UInt<1>(0h0) regreset rxen : UInt<1>, clock, reset, UInt<1>(0h0) regreset enwire4 : UInt<1>, clock, reset, UInt<1>(0h0) regreset invpol : UInt<1>, clock, reset, UInt<1>(0h0) regreset enparity : UInt<1>, clock, reset, UInt<1>(0h0) regreset parity : UInt<1>, clock, reset, UInt<1>(0h0) regreset errorparity : UInt<1>, clock, reset, UInt<1>(0h0) regreset errie : UInt<1>, clock, reset, UInt<1>(0h0) regreset txwm : UInt<4>, clock, reset, UInt<4>(0h0) regreset rxwm : UInt<4>, clock, reset, UInt<4>(0h0) regreset nstop : UInt<1>, clock, reset, UInt<1>(0h0) regreset data8or9 : UInt<1>, clock, reset, UInt<1>(0h1) connect txm.io.en, txen connect txm.io.in, txq.io.deq connect txm.io.div, div connect txm.io.nstop, nstop connect ioNodeOut.txd, txm.io.out connect rxm.io.en, rxen connect rxm.io.in, ioNodeOut.rxd connect rxq.io.enq.valid, rxm.io.out.valid connect rxq.io.enq.bits, rxm.io.out.bits connect rxm.io.div, div node _tx_busy_T = orr(txq.io.count) node _tx_busy_T_1 = or(txm.io.tx_busy, _tx_busy_T) node tx_busy = and(_tx_busy_T_1, txen) wire _ie_WIRE : { rxwm : UInt<1>, txwm : UInt<1>} connect _ie_WIRE.txwm, UInt<1>(0h0) connect _ie_WIRE.rxwm, UInt<1>(0h0) regreset ie : { rxwm : UInt<1>, txwm : UInt<1>}, clock, reset, _ie_WIRE wire ip : { rxwm : UInt<1>, txwm : UInt<1>} node _ip_txwm_T = lt(txq.io.count, txwm) connect ip.txwm, _ip_txwm_T node _ip_rxwm_T = gt(rxq.io.count, rxwm) connect ip.rxwm, _ip_rxwm_T node _intnodeOut_0_T = and(ip.txwm, ie.txwm) node _intnodeOut_0_T_1 = and(ip.rxwm, ie.rxwm) node _intnodeOut_0_T_2 = or(_intnodeOut_0_T, _intnodeOut_0_T_1) connect intnodeOut[0], _intnodeOut_0_T_2 wire quash : UInt<1> node _T = eq(txq.io.enq.ready, UInt<1>(0h0)) node _T_1 = eq(rxq.io.deq.valid, UInt<1>(0h0)) wire in : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<12>, size : UInt<2>}}}} node _in_bits_read_T = eq(controlNodeIn.a.bits.opcode, UInt<3>(0h4)) connect in.bits.read, _in_bits_read_T node _in_bits_index_T = shr(controlNodeIn.a.bits.address, 3) connect in.bits.index, _in_bits_index_T connect in.bits.data, controlNodeIn.a.bits.data connect in.bits.mask, controlNodeIn.a.bits.mask connect in.bits.extra.tlrr_extra.source, controlNodeIn.a.bits.source connect in.bits.extra.tlrr_extra.size, controlNodeIn.a.bits.size wire out : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, data : UInt<64>, extra : { tlrr_extra : { source : UInt<12>, size : UInt<2>}}}} wire out_front : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<12>, size : UInt<2>}}}} connect out_front.bits, in.bits node out_maskMatch = not(UInt<9>(0h3)) node out_findex = and(out_front.bits.index, out_maskMatch) node out_bindex = and(out_front.bits.index, out_maskMatch) node _out_T = eq(out_findex, UInt<9>(0h0)) node _out_T_1 = eq(out_bindex, UInt<9>(0h0)) node _out_T_2 = eq(out_findex, UInt<9>(0h0)) node _out_T_3 = eq(out_bindex, UInt<9>(0h0)) node _out_T_4 = eq(out_findex, UInt<9>(0h0)) node _out_T_5 = eq(out_bindex, UInt<9>(0h0)) node _out_T_6 = eq(out_findex, UInt<9>(0h0)) node _out_T_7 = eq(out_bindex, UInt<9>(0h0)) wire out_rivalid : UInt<1>[16] wire out_wivalid : UInt<1>[16] wire out_roready : UInt<1>[16] wire out_woready : UInt<1>[16] node _out_frontMask_T = bits(out_front.bits.mask, 0, 0) node _out_frontMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_frontMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_frontMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_frontMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_frontMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_frontMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_frontMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_frontMask_T_8 = mux(_out_frontMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_9 = mux(_out_frontMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_10 = mux(_out_frontMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_11 = mux(_out_frontMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_12 = mux(_out_frontMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_13 = mux(_out_frontMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_14 = mux(_out_frontMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_15 = mux(_out_frontMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_frontMask_lo_lo = cat(_out_frontMask_T_9, _out_frontMask_T_8) node out_frontMask_lo_hi = cat(_out_frontMask_T_11, _out_frontMask_T_10) node out_frontMask_lo = cat(out_frontMask_lo_hi, out_frontMask_lo_lo) node out_frontMask_hi_lo = cat(_out_frontMask_T_13, _out_frontMask_T_12) node out_frontMask_hi_hi = cat(_out_frontMask_T_15, _out_frontMask_T_14) node out_frontMask_hi = cat(out_frontMask_hi_hi, out_frontMask_hi_lo) node out_frontMask = cat(out_frontMask_hi, out_frontMask_lo) node _out_backMask_T = bits(out_front.bits.mask, 0, 0) node _out_backMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_backMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_backMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_backMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_backMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_backMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_backMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_backMask_T_8 = mux(_out_backMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_9 = mux(_out_backMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_10 = mux(_out_backMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_11 = mux(_out_backMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_12 = mux(_out_backMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_13 = mux(_out_backMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_14 = mux(_out_backMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_15 = mux(_out_backMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_backMask_lo_lo = cat(_out_backMask_T_9, _out_backMask_T_8) node out_backMask_lo_hi = cat(_out_backMask_T_11, _out_backMask_T_10) node out_backMask_lo = cat(out_backMask_lo_hi, out_backMask_lo_lo) node out_backMask_hi_lo = cat(_out_backMask_T_13, _out_backMask_T_12) node out_backMask_hi_hi = cat(_out_backMask_T_15, _out_backMask_T_14) node out_backMask_hi = cat(out_backMask_hi_hi, out_backMask_hi_lo) node out_backMask = cat(out_backMask_hi, out_backMask_lo) node _out_rimask_T = bits(out_frontMask, 7, 0) node out_rimask = orr(_out_rimask_T) node _out_wimask_T = bits(out_frontMask, 7, 0) node out_wimask = andr(_out_wimask_T) node _out_romask_T = bits(out_backMask, 7, 0) node out_romask = orr(_out_romask_T) node _out_womask_T = bits(out_backMask, 7, 0) node out_womask = andr(_out_womask_T) node out_f_rivalid = and(out_rivalid[0], out_rimask) node out_f_roready = and(out_roready[0], out_romask) node out_f_wivalid = and(out_wivalid[0], out_wimask) node out_f_woready = and(out_woready[0], out_womask) node _out_T_8 = bits(out_front.bits.data, 7, 0) node _out_txq_io_enq_valid_T = eq(quash, UInt<1>(0h0)) node _out_txq_io_enq_valid_T_1 = and(out_f_woready, _out_txq_io_enq_valid_T) connect txq.io.enq.valid, _out_txq_io_enq_valid_T_1 connect txq.io.enq.bits, _out_T_8 node _out_T_9 = and(out_f_wivalid, UInt<1>(0h1)) node _out_T_10 = and(UInt<1>(0h1), out_f_woready) node _out_T_11 = eq(out_rimask, UInt<1>(0h0)) node _out_T_12 = eq(out_wimask, UInt<1>(0h0)) node _out_T_13 = eq(out_romask, UInt<1>(0h0)) node _out_T_14 = eq(out_womask, UInt<1>(0h0)) node _out_T_15 = or(UInt<1>(0h0), UInt<8>(0h0)) node _out_T_16 = bits(_out_T_15, 7, 0) node _out_rimask_T_1 = bits(out_frontMask, 30, 8) node out_rimask_1 = orr(_out_rimask_T_1) node _out_wimask_T_1 = bits(out_frontMask, 30, 8) node out_wimask_1 = andr(_out_wimask_T_1) node _out_romask_T_1 = bits(out_backMask, 30, 8) node out_romask_1 = orr(_out_romask_T_1) node _out_womask_T_1 = bits(out_backMask, 30, 8) node out_womask_1 = andr(_out_womask_T_1) node out_f_rivalid_1 = and(out_rivalid[1], out_rimask_1) node out_f_roready_1 = and(out_roready[1], out_romask_1) node out_f_wivalid_1 = and(out_wivalid[1], out_wimask_1) node out_f_woready_1 = and(out_woready[1], out_womask_1) node _out_T_17 = bits(out_front.bits.data, 30, 8) node _out_T_18 = and(out_f_rivalid_1, UInt<1>(0h1)) node _out_T_19 = and(UInt<1>(0h1), out_f_roready_1) node _out_T_20 = eq(out_rimask_1, UInt<1>(0h0)) node _out_T_21 = eq(out_wimask_1, UInt<1>(0h0)) node _out_T_22 = eq(out_romask_1, UInt<1>(0h0)) node _out_T_23 = eq(out_womask_1, UInt<1>(0h0)) node _out_prepend_T = or(_out_T_16, UInt<8>(0h0)) node out_prepend = cat(UInt<1>(0h0), _out_prepend_T) node _out_T_24 = or(out_prepend, UInt<31>(0h0)) node _out_T_25 = bits(_out_T_24, 30, 0) node _out_rimask_T_2 = bits(out_frontMask, 31, 31) node out_rimask_2 = orr(_out_rimask_T_2) node _out_wimask_T_2 = bits(out_frontMask, 31, 31) node out_wimask_2 = andr(_out_wimask_T_2) node _out_romask_T_2 = bits(out_backMask, 31, 31) node out_romask_2 = orr(_out_romask_T_2) node _out_womask_T_2 = bits(out_backMask, 31, 31) node out_womask_2 = andr(_out_womask_T_2) node out_f_rivalid_2 = and(out_rivalid[2], out_rimask_2) node out_f_roready_2 = and(out_roready[2], out_romask_2) node out_f_wivalid_2 = and(out_wivalid[2], out_wimask_2) node out_f_woready_2 = and(out_woready[2], out_womask_2) node _out_T_26 = bits(out_front.bits.data, 31, 31) node _out_quash_T = bits(_out_T_26, 0, 0) node _out_quash_T_1 = and(out_f_woready_2, _out_quash_T) connect quash, _out_quash_T_1 node _out_T_27 = and(out_f_rivalid_2, UInt<1>(0h1)) node _out_T_28 = and(UInt<1>(0h1), out_f_roready_2) node _out_T_29 = eq(out_rimask_2, UInt<1>(0h0)) node _out_T_30 = eq(out_wimask_2, UInt<1>(0h0)) node _out_T_31 = eq(out_romask_2, UInt<1>(0h0)) node _out_T_32 = eq(out_womask_2, UInt<1>(0h0)) node _out_prepend_T_1 = or(_out_T_25, UInt<31>(0h0)) node out_prepend_1 = cat(_T, _out_prepend_T_1) node _out_T_33 = or(out_prepend_1, UInt<32>(0h0)) node _out_T_34 = bits(_out_T_33, 31, 0) node _out_rimask_T_3 = bits(out_frontMask, 39, 32) node out_rimask_3 = orr(_out_rimask_T_3) node _out_wimask_T_3 = bits(out_frontMask, 39, 32) node out_wimask_3 = andr(_out_wimask_T_3) node _out_romask_T_3 = bits(out_backMask, 39, 32) node out_romask_3 = orr(_out_romask_T_3) node _out_womask_T_3 = bits(out_backMask, 39, 32) node out_womask_3 = andr(_out_womask_T_3) node out_f_rivalid_3 = and(out_rivalid[3], out_rimask_3) node out_f_roready_3 = and(out_roready[3], out_romask_3) node out_f_wivalid_3 = and(out_wivalid[3], out_wimask_3) node out_f_woready_3 = and(out_woready[3], out_womask_3) connect rxq.io.deq.ready, out_f_roready_3 node _out_T_35 = bits(out_front.bits.data, 39, 32) node _out_T_36 = and(out_f_rivalid_3, UInt<1>(0h1)) node _out_T_37 = and(UInt<1>(0h1), out_f_roready_3) node _out_T_38 = eq(out_rimask_3, UInt<1>(0h0)) node _out_T_39 = eq(out_wimask_3, UInt<1>(0h0)) node _out_T_40 = eq(out_romask_3, UInt<1>(0h0)) node _out_T_41 = eq(out_womask_3, UInt<1>(0h0)) node _out_prepend_T_2 = or(_out_T_34, UInt<32>(0h0)) node out_prepend_2 = cat(rxq.io.deq.bits, _out_prepend_T_2) node _out_T_42 = or(out_prepend_2, UInt<40>(0h0)) node _out_T_43 = bits(_out_T_42, 39, 0) node _out_rimask_T_4 = bits(out_frontMask, 62, 40) node out_rimask_4 = orr(_out_rimask_T_4) node _out_wimask_T_4 = bits(out_frontMask, 62, 40) node out_wimask_4 = andr(_out_wimask_T_4) node _out_romask_T_4 = bits(out_backMask, 62, 40) node out_romask_4 = orr(_out_romask_T_4) node _out_womask_T_4 = bits(out_backMask, 62, 40) node out_womask_4 = andr(_out_womask_T_4) node out_f_rivalid_4 = and(out_rivalid[4], out_rimask_4) node out_f_roready_4 = and(out_roready[4], out_romask_4) node out_f_wivalid_4 = and(out_wivalid[4], out_wimask_4) node out_f_woready_4 = and(out_woready[4], out_womask_4) node _out_T_44 = bits(out_front.bits.data, 62, 40) node _out_T_45 = and(out_f_rivalid_4, UInt<1>(0h1)) node _out_T_46 = and(UInt<1>(0h1), out_f_roready_4) node _out_T_47 = eq(out_rimask_4, UInt<1>(0h0)) node _out_T_48 = eq(out_wimask_4, UInt<1>(0h0)) node _out_T_49 = eq(out_romask_4, UInt<1>(0h0)) node _out_T_50 = eq(out_womask_4, UInt<1>(0h0)) node _out_prepend_T_3 = or(_out_T_43, UInt<40>(0h0)) node out_prepend_3 = cat(UInt<1>(0h0), _out_prepend_T_3) node _out_T_51 = or(out_prepend_3, UInt<63>(0h0)) node _out_T_52 = bits(_out_T_51, 62, 0) node _out_rimask_T_5 = bits(out_frontMask, 63, 63) node out_rimask_5 = orr(_out_rimask_T_5) node _out_wimask_T_5 = bits(out_frontMask, 63, 63) node out_wimask_5 = andr(_out_wimask_T_5) node _out_romask_T_5 = bits(out_backMask, 63, 63) node out_romask_5 = orr(_out_romask_T_5) node _out_womask_T_5 = bits(out_backMask, 63, 63) node out_womask_5 = andr(_out_womask_T_5) node out_f_rivalid_5 = and(out_rivalid[5], out_rimask_5) node out_f_roready_5 = and(out_roready[5], out_romask_5) node out_f_wivalid_5 = and(out_wivalid[5], out_wimask_5) node out_f_woready_5 = and(out_woready[5], out_womask_5) node _out_T_53 = bits(out_front.bits.data, 63, 63) node _out_T_54 = and(out_f_rivalid_5, UInt<1>(0h1)) node _out_T_55 = and(UInt<1>(0h1), out_f_roready_5) node _out_T_56 = eq(out_rimask_5, UInt<1>(0h0)) node _out_T_57 = eq(out_wimask_5, UInt<1>(0h0)) node _out_T_58 = eq(out_romask_5, UInt<1>(0h0)) node _out_T_59 = eq(out_womask_5, UInt<1>(0h0)) node _out_prepend_T_4 = or(_out_T_52, UInt<63>(0h0)) node out_prepend_4 = cat(_T_1, _out_prepend_T_4) node _out_T_60 = or(out_prepend_4, UInt<64>(0h0)) node _out_T_61 = bits(_out_T_60, 63, 0) node _out_rimask_T_6 = bits(out_frontMask, 0, 0) node out_rimask_6 = orr(_out_rimask_T_6) node _out_wimask_T_6 = bits(out_frontMask, 0, 0) node out_wimask_6 = andr(_out_wimask_T_6) node _out_romask_T_6 = bits(out_backMask, 0, 0) node out_romask_6 = orr(_out_romask_T_6) node _out_womask_T_6 = bits(out_backMask, 0, 0) node out_womask_6 = andr(_out_womask_T_6) node out_f_rivalid_6 = and(out_rivalid[6], out_rimask_6) node out_f_roready_6 = and(out_roready[6], out_romask_6) node out_f_wivalid_6 = and(out_wivalid[6], out_wimask_6) node out_f_woready_6 = and(out_woready[6], out_womask_6) node _out_T_62 = bits(out_front.bits.data, 0, 0) when out_f_woready_6 : connect txen, _out_T_62 node _out_T_63 = and(out_f_rivalid_6, UInt<1>(0h1)) node _out_T_64 = and(UInt<1>(0h1), out_f_roready_6) node _out_T_65 = and(out_f_wivalid_6, UInt<1>(0h1)) node _out_T_66 = and(UInt<1>(0h1), out_f_woready_6) node _out_T_67 = eq(out_rimask_6, UInt<1>(0h0)) node _out_T_68 = eq(out_wimask_6, UInt<1>(0h0)) node _out_T_69 = eq(out_romask_6, UInt<1>(0h0)) node _out_T_70 = eq(out_womask_6, UInt<1>(0h0)) node _out_T_71 = or(txen, UInt<1>(0h0)) node _out_T_72 = bits(_out_T_71, 0, 0) node _out_rimask_T_7 = bits(out_frontMask, 1, 1) node out_rimask_7 = orr(_out_rimask_T_7) node _out_wimask_T_7 = bits(out_frontMask, 1, 1) node out_wimask_7 = andr(_out_wimask_T_7) node _out_romask_T_7 = bits(out_backMask, 1, 1) node out_romask_7 = orr(_out_romask_T_7) node _out_womask_T_7 = bits(out_backMask, 1, 1) node out_womask_7 = andr(_out_womask_T_7) node out_f_rivalid_7 = and(out_rivalid[7], out_rimask_7) node out_f_roready_7 = and(out_roready[7], out_romask_7) node out_f_wivalid_7 = and(out_wivalid[7], out_wimask_7) node out_f_woready_7 = and(out_woready[7], out_womask_7) node _out_T_73 = bits(out_front.bits.data, 1, 1) when out_f_woready_7 : connect nstop, _out_T_73 node _out_T_74 = and(out_f_rivalid_7, UInt<1>(0h1)) node _out_T_75 = and(UInt<1>(0h1), out_f_roready_7) node _out_T_76 = and(out_f_wivalid_7, UInt<1>(0h1)) node _out_T_77 = and(UInt<1>(0h1), out_f_woready_7) node _out_T_78 = eq(out_rimask_7, UInt<1>(0h0)) node _out_T_79 = eq(out_wimask_7, UInt<1>(0h0)) node _out_T_80 = eq(out_romask_7, UInt<1>(0h0)) node _out_T_81 = eq(out_womask_7, UInt<1>(0h0)) node _out_prepend_T_5 = or(_out_T_72, UInt<1>(0h0)) node out_prepend_5 = cat(nstop, _out_prepend_T_5) node _out_T_82 = or(out_prepend_5, UInt<2>(0h0)) node _out_T_83 = bits(_out_T_82, 1, 0) node _out_rimask_T_8 = bits(out_frontMask, 19, 16) node out_rimask_8 = orr(_out_rimask_T_8) node _out_wimask_T_8 = bits(out_frontMask, 19, 16) node out_wimask_8 = andr(_out_wimask_T_8) node _out_romask_T_8 = bits(out_backMask, 19, 16) node out_romask_8 = orr(_out_romask_T_8) node _out_womask_T_8 = bits(out_backMask, 19, 16) node out_womask_8 = andr(_out_womask_T_8) node out_f_rivalid_8 = and(out_rivalid[8], out_rimask_8) node out_f_roready_8 = and(out_roready[8], out_romask_8) node out_f_wivalid_8 = and(out_wivalid[8], out_wimask_8) node out_f_woready_8 = and(out_woready[8], out_womask_8) node _out_T_84 = bits(out_front.bits.data, 19, 16) when out_f_woready_8 : connect txwm, _out_T_84 node _out_T_85 = and(out_f_rivalid_8, UInt<1>(0h1)) node _out_T_86 = and(UInt<1>(0h1), out_f_roready_8) node _out_T_87 = and(out_f_wivalid_8, UInt<1>(0h1)) node _out_T_88 = and(UInt<1>(0h1), out_f_woready_8) node _out_T_89 = eq(out_rimask_8, UInt<1>(0h0)) node _out_T_90 = eq(out_wimask_8, UInt<1>(0h0)) node _out_T_91 = eq(out_romask_8, UInt<1>(0h0)) node _out_T_92 = eq(out_womask_8, UInt<1>(0h0)) node _out_prepend_T_6 = or(_out_T_83, UInt<16>(0h0)) node out_prepend_6 = cat(txwm, _out_prepend_T_6) node _out_T_93 = or(out_prepend_6, UInt<20>(0h0)) node _out_T_94 = bits(_out_T_93, 19, 0) node _out_rimask_T_9 = bits(out_frontMask, 32, 32) node out_rimask_9 = orr(_out_rimask_T_9) node _out_wimask_T_9 = bits(out_frontMask, 32, 32) node out_wimask_9 = andr(_out_wimask_T_9) node _out_romask_T_9 = bits(out_backMask, 32, 32) node out_romask_9 = orr(_out_romask_T_9) node _out_womask_T_9 = bits(out_backMask, 32, 32) node out_womask_9 = andr(_out_womask_T_9) node out_f_rivalid_9 = and(out_rivalid[9], out_rimask_9) node out_f_roready_9 = and(out_roready[9], out_romask_9) node out_f_wivalid_9 = and(out_wivalid[9], out_wimask_9) node out_f_woready_9 = and(out_woready[9], out_womask_9) node _out_T_95 = bits(out_front.bits.data, 32, 32) when out_f_woready_9 : connect rxen, _out_T_95 node _out_T_96 = and(out_f_rivalid_9, UInt<1>(0h1)) node _out_T_97 = and(UInt<1>(0h1), out_f_roready_9) node _out_T_98 = and(out_f_wivalid_9, UInt<1>(0h1)) node _out_T_99 = and(UInt<1>(0h1), out_f_woready_9) node _out_T_100 = eq(out_rimask_9, UInt<1>(0h0)) node _out_T_101 = eq(out_wimask_9, UInt<1>(0h0)) node _out_T_102 = eq(out_romask_9, UInt<1>(0h0)) node _out_T_103 = eq(out_womask_9, UInt<1>(0h0)) node _out_prepend_T_7 = or(_out_T_94, UInt<32>(0h0)) node out_prepend_7 = cat(rxen, _out_prepend_T_7) node _out_T_104 = or(out_prepend_7, UInt<33>(0h0)) node _out_T_105 = bits(_out_T_104, 32, 0) node _out_rimask_T_10 = bits(out_frontMask, 51, 48) node out_rimask_10 = orr(_out_rimask_T_10) node _out_wimask_T_10 = bits(out_frontMask, 51, 48) node out_wimask_10 = andr(_out_wimask_T_10) node _out_romask_T_10 = bits(out_backMask, 51, 48) node out_romask_10 = orr(_out_romask_T_10) node _out_womask_T_10 = bits(out_backMask, 51, 48) node out_womask_10 = andr(_out_womask_T_10) node out_f_rivalid_10 = and(out_rivalid[10], out_rimask_10) node out_f_roready_10 = and(out_roready[10], out_romask_10) node out_f_wivalid_10 = and(out_wivalid[10], out_wimask_10) node out_f_woready_10 = and(out_woready[10], out_womask_10) node _out_T_106 = bits(out_front.bits.data, 51, 48) when out_f_woready_10 : connect rxwm, _out_T_106 node _out_T_107 = and(out_f_rivalid_10, UInt<1>(0h1)) node _out_T_108 = and(UInt<1>(0h1), out_f_roready_10) node _out_T_109 = and(out_f_wivalid_10, UInt<1>(0h1)) node _out_T_110 = and(UInt<1>(0h1), out_f_woready_10) node _out_T_111 = eq(out_rimask_10, UInt<1>(0h0)) node _out_T_112 = eq(out_wimask_10, UInt<1>(0h0)) node _out_T_113 = eq(out_romask_10, UInt<1>(0h0)) node _out_T_114 = eq(out_womask_10, UInt<1>(0h0)) node _out_prepend_T_8 = or(_out_T_105, UInt<48>(0h0)) node out_prepend_8 = cat(rxwm, _out_prepend_T_8) node _out_T_115 = or(out_prepend_8, UInt<52>(0h0)) node _out_T_116 = bits(_out_T_115, 51, 0) node _out_rimask_T_11 = bits(out_frontMask, 0, 0) node out_rimask_11 = orr(_out_rimask_T_11) node _out_wimask_T_11 = bits(out_frontMask, 0, 0) node out_wimask_11 = andr(_out_wimask_T_11) node _out_romask_T_11 = bits(out_backMask, 0, 0) node out_romask_11 = orr(_out_romask_T_11) node _out_womask_T_11 = bits(out_backMask, 0, 0) node out_womask_11 = andr(_out_womask_T_11) node out_f_rivalid_11 = and(out_rivalid[11], out_rimask_11) node out_f_roready_11 = and(out_roready[11], out_romask_11) node out_f_wivalid_11 = and(out_wivalid[11], out_wimask_11) node out_f_woready_11 = and(out_woready[11], out_womask_11) node _out_T_117 = bits(out_front.bits.data, 0, 0) when out_f_woready_11 : connect ie.txwm, _out_T_117 node _out_T_118 = and(out_f_rivalid_11, UInt<1>(0h1)) node _out_T_119 = and(UInt<1>(0h1), out_f_roready_11) node _out_T_120 = and(out_f_wivalid_11, UInt<1>(0h1)) node _out_T_121 = and(UInt<1>(0h1), out_f_woready_11) node _out_T_122 = eq(out_rimask_11, UInt<1>(0h0)) node _out_T_123 = eq(out_wimask_11, UInt<1>(0h0)) node _out_T_124 = eq(out_romask_11, UInt<1>(0h0)) node _out_T_125 = eq(out_womask_11, UInt<1>(0h0)) node _out_T_126 = or(ie.txwm, UInt<1>(0h0)) node _out_T_127 = bits(_out_T_126, 0, 0) node _out_rimask_T_12 = bits(out_frontMask, 1, 1) node out_rimask_12 = orr(_out_rimask_T_12) node _out_wimask_T_12 = bits(out_frontMask, 1, 1) node out_wimask_12 = andr(_out_wimask_T_12) node _out_romask_T_12 = bits(out_backMask, 1, 1) node out_romask_12 = orr(_out_romask_T_12) node _out_womask_T_12 = bits(out_backMask, 1, 1) node out_womask_12 = andr(_out_womask_T_12) node out_f_rivalid_12 = and(out_rivalid[12], out_rimask_12) node out_f_roready_12 = and(out_roready[12], out_romask_12) node out_f_wivalid_12 = and(out_wivalid[12], out_wimask_12) node out_f_woready_12 = and(out_woready[12], out_womask_12) node _out_T_128 = bits(out_front.bits.data, 1, 1) when out_f_woready_12 : connect ie.rxwm, _out_T_128 node _out_T_129 = and(out_f_rivalid_12, UInt<1>(0h1)) node _out_T_130 = and(UInt<1>(0h1), out_f_roready_12) node _out_T_131 = and(out_f_wivalid_12, UInt<1>(0h1)) node _out_T_132 = and(UInt<1>(0h1), out_f_woready_12) node _out_T_133 = eq(out_rimask_12, UInt<1>(0h0)) node _out_T_134 = eq(out_wimask_12, UInt<1>(0h0)) node _out_T_135 = eq(out_romask_12, UInt<1>(0h0)) node _out_T_136 = eq(out_womask_12, UInt<1>(0h0)) node _out_prepend_T_9 = or(_out_T_127, UInt<1>(0h0)) node out_prepend_9 = cat(ie.rxwm, _out_prepend_T_9) node _out_T_137 = or(out_prepend_9, UInt<2>(0h0)) node _out_T_138 = bits(_out_T_137, 1, 0) node _out_rimask_T_13 = bits(out_frontMask, 32, 32) node out_rimask_13 = orr(_out_rimask_T_13) node _out_wimask_T_13 = bits(out_frontMask, 32, 32) node out_wimask_13 = andr(_out_wimask_T_13) node _out_romask_T_13 = bits(out_backMask, 32, 32) node out_romask_13 = orr(_out_romask_T_13) node _out_womask_T_13 = bits(out_backMask, 32, 32) node out_womask_13 = andr(_out_womask_T_13) node out_f_rivalid_13 = and(out_rivalid[13], out_rimask_13) node out_f_roready_13 = and(out_roready[13], out_romask_13) node out_f_wivalid_13 = and(out_wivalid[13], out_wimask_13) node out_f_woready_13 = and(out_woready[13], out_womask_13) node _out_T_139 = bits(out_front.bits.data, 32, 32) node _out_T_140 = and(out_f_rivalid_13, UInt<1>(0h1)) node _out_T_141 = and(UInt<1>(0h1), out_f_roready_13) node _out_T_142 = eq(out_rimask_13, UInt<1>(0h0)) node _out_T_143 = eq(out_wimask_13, UInt<1>(0h0)) node _out_T_144 = eq(out_romask_13, UInt<1>(0h0)) node _out_T_145 = eq(out_womask_13, UInt<1>(0h0)) node _out_prepend_T_10 = or(_out_T_138, UInt<32>(0h0)) node out_prepend_10 = cat(ip.txwm, _out_prepend_T_10) node _out_T_146 = or(out_prepend_10, UInt<33>(0h0)) node _out_T_147 = bits(_out_T_146, 32, 0) node _out_rimask_T_14 = bits(out_frontMask, 33, 33) node out_rimask_14 = orr(_out_rimask_T_14) node _out_wimask_T_14 = bits(out_frontMask, 33, 33) node out_wimask_14 = andr(_out_wimask_T_14) node _out_romask_T_14 = bits(out_backMask, 33, 33) node out_romask_14 = orr(_out_romask_T_14) node _out_womask_T_14 = bits(out_backMask, 33, 33) node out_womask_14 = andr(_out_womask_T_14) node out_f_rivalid_14 = and(out_rivalid[14], out_rimask_14) node out_f_roready_14 = and(out_roready[14], out_romask_14) node out_f_wivalid_14 = and(out_wivalid[14], out_wimask_14) node out_f_woready_14 = and(out_woready[14], out_womask_14) node _out_T_148 = bits(out_front.bits.data, 33, 33) node _out_T_149 = and(out_f_rivalid_14, UInt<1>(0h1)) node _out_T_150 = and(UInt<1>(0h1), out_f_roready_14) node _out_T_151 = eq(out_rimask_14, UInt<1>(0h0)) node _out_T_152 = eq(out_wimask_14, UInt<1>(0h0)) node _out_T_153 = eq(out_romask_14, UInt<1>(0h0)) node _out_T_154 = eq(out_womask_14, UInt<1>(0h0)) node _out_prepend_T_11 = or(_out_T_147, UInt<33>(0h0)) node out_prepend_11 = cat(ip.rxwm, _out_prepend_T_11) node _out_T_155 = or(out_prepend_11, UInt<34>(0h0)) node _out_T_156 = bits(_out_T_155, 33, 0) node _out_rimask_T_15 = bits(out_frontMask, 15, 0) node out_rimask_15 = orr(_out_rimask_T_15) node _out_wimask_T_15 = bits(out_frontMask, 15, 0) node out_wimask_15 = andr(_out_wimask_T_15) node _out_romask_T_15 = bits(out_backMask, 15, 0) node out_romask_15 = orr(_out_romask_T_15) node _out_womask_T_15 = bits(out_backMask, 15, 0) node out_womask_15 = andr(_out_womask_T_15) node out_f_rivalid_15 = and(out_rivalid[15], out_rimask_15) node out_f_roready_15 = and(out_roready[15], out_romask_15) node out_f_wivalid_15 = and(out_wivalid[15], out_wimask_15) node out_f_woready_15 = and(out_woready[15], out_womask_15) node _out_T_157 = bits(out_front.bits.data, 15, 0) when out_f_woready_15 : connect div, _out_T_157 node _out_T_158 = and(out_f_rivalid_15, UInt<1>(0h1)) node _out_T_159 = and(UInt<1>(0h1), out_f_roready_15) node _out_T_160 = and(out_f_wivalid_15, UInt<1>(0h1)) node _out_T_161 = and(UInt<1>(0h1), out_f_woready_15) node _out_T_162 = eq(out_rimask_15, UInt<1>(0h0)) node _out_T_163 = eq(out_wimask_15, UInt<1>(0h0)) node _out_T_164 = eq(out_romask_15, UInt<1>(0h0)) node _out_T_165 = eq(out_womask_15, UInt<1>(0h0)) node _out_T_166 = or(div, UInt<16>(0h0)) node _out_T_167 = bits(_out_T_166, 15, 0) node _out_iindex_T = bits(out_front.bits.index, 0, 0) node _out_iindex_T_1 = bits(out_front.bits.index, 1, 1) node _out_iindex_T_2 = bits(out_front.bits.index, 2, 2) node _out_iindex_T_3 = bits(out_front.bits.index, 3, 3) node _out_iindex_T_4 = bits(out_front.bits.index, 4, 4) node _out_iindex_T_5 = bits(out_front.bits.index, 5, 5) node _out_iindex_T_6 = bits(out_front.bits.index, 6, 6) node _out_iindex_T_7 = bits(out_front.bits.index, 7, 7) node _out_iindex_T_8 = bits(out_front.bits.index, 8, 8) node out_iindex = cat(_out_iindex_T_1, _out_iindex_T) node _out_oindex_T = bits(out_front.bits.index, 0, 0) node _out_oindex_T_1 = bits(out_front.bits.index, 1, 1) node _out_oindex_T_2 = bits(out_front.bits.index, 2, 2) node _out_oindex_T_3 = bits(out_front.bits.index, 3, 3) node _out_oindex_T_4 = bits(out_front.bits.index, 4, 4) node _out_oindex_T_5 = bits(out_front.bits.index, 5, 5) node _out_oindex_T_6 = bits(out_front.bits.index, 6, 6) node _out_oindex_T_7 = bits(out_front.bits.index, 7, 7) node _out_oindex_T_8 = bits(out_front.bits.index, 8, 8) node out_oindex = cat(_out_oindex_T_1, _out_oindex_T) node _out_frontSel_T = dshl(UInt<1>(0h1), out_iindex) node out_frontSel_0 = bits(_out_frontSel_T, 0, 0) node out_frontSel_1 = bits(_out_frontSel_T, 1, 1) node out_frontSel_2 = bits(_out_frontSel_T, 2, 2) node out_frontSel_3 = bits(_out_frontSel_T, 3, 3) node _out_backSel_T = dshl(UInt<1>(0h1), out_oindex) node out_backSel_0 = bits(_out_backSel_T, 0, 0) node out_backSel_1 = bits(_out_backSel_T, 1, 1) node out_backSel_2 = bits(_out_backSel_T, 2, 2) node out_backSel_3 = bits(_out_backSel_T, 3, 3) node _out_rifireMux_T = and(in.valid, out_front.ready) node _out_rifireMux_T_1 = and(_out_rifireMux_T, out_front.bits.read) wire out_rifireMux_out : UInt<1> node _out_rifireMux_T_2 = and(_out_rifireMux_T_1, out_frontSel_0) node _out_rifireMux_T_3 = and(_out_rifireMux_T_2, _out_T) connect out_rifireMux_out, UInt<1>(0h1) connect out_rivalid[5], _out_rifireMux_T_3 connect out_rivalid[4], _out_rifireMux_T_3 connect out_rivalid[3], _out_rifireMux_T_3 connect out_rivalid[2], _out_rifireMux_T_3 connect out_rivalid[1], _out_rifireMux_T_3 connect out_rivalid[0], _out_rifireMux_T_3 node _out_rifireMux_T_4 = eq(_out_T, UInt<1>(0h0)) node _out_rifireMux_T_5 = or(out_rifireMux_out, _out_rifireMux_T_4) wire out_rifireMux_out_1 : UInt<1> node _out_rifireMux_T_6 = and(_out_rifireMux_T_1, out_frontSel_1) node _out_rifireMux_T_7 = and(_out_rifireMux_T_6, _out_T_2) connect out_rifireMux_out_1, UInt<1>(0h1) connect out_rivalid[10], _out_rifireMux_T_7 connect out_rivalid[9], _out_rifireMux_T_7 connect out_rivalid[8], _out_rifireMux_T_7 connect out_rivalid[7], _out_rifireMux_T_7 connect out_rivalid[6], _out_rifireMux_T_7 node _out_rifireMux_T_8 = eq(_out_T_2, UInt<1>(0h0)) node _out_rifireMux_T_9 = or(out_rifireMux_out_1, _out_rifireMux_T_8) wire out_rifireMux_out_2 : UInt<1> node _out_rifireMux_T_10 = and(_out_rifireMux_T_1, out_frontSel_2) node _out_rifireMux_T_11 = and(_out_rifireMux_T_10, _out_T_4) connect out_rifireMux_out_2, UInt<1>(0h1) connect out_rivalid[14], _out_rifireMux_T_11 connect out_rivalid[13], _out_rifireMux_T_11 connect out_rivalid[12], _out_rifireMux_T_11 connect out_rivalid[11], _out_rifireMux_T_11 node _out_rifireMux_T_12 = eq(_out_T_4, UInt<1>(0h0)) node _out_rifireMux_T_13 = or(out_rifireMux_out_2, _out_rifireMux_T_12) wire out_rifireMux_out_3 : UInt<1> node _out_rifireMux_T_14 = and(_out_rifireMux_T_1, out_frontSel_3) node _out_rifireMux_T_15 = and(_out_rifireMux_T_14, _out_T_6) connect out_rifireMux_out_3, UInt<1>(0h1) connect out_rivalid[15], _out_rifireMux_T_15 node _out_rifireMux_T_16 = eq(_out_T_6, UInt<1>(0h0)) node _out_rifireMux_T_17 = or(out_rifireMux_out_3, _out_rifireMux_T_16) node _out_rifireMux_T_18 = geq(out_iindex, UInt<3>(0h4)) wire _out_rifireMux_WIRE : UInt<1>[4] connect _out_rifireMux_WIRE[0], _out_rifireMux_T_5 connect _out_rifireMux_WIRE[1], _out_rifireMux_T_9 connect _out_rifireMux_WIRE[2], _out_rifireMux_T_13 connect _out_rifireMux_WIRE[3], _out_rifireMux_T_17 node out_rifireMux = mux(_out_rifireMux_T_18, UInt<1>(0h1), _out_rifireMux_WIRE[out_iindex]) node _out_wifireMux_T = and(in.valid, out_front.ready) node _out_wifireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wifireMux_T_2 = and(_out_wifireMux_T, _out_wifireMux_T_1) wire out_wifireMux_out : UInt<1> node _out_wifireMux_T_3 = and(_out_wifireMux_T_2, out_frontSel_0) node _out_wifireMux_T_4 = and(_out_wifireMux_T_3, _out_T) connect out_wifireMux_out, UInt<1>(0h1) connect out_wivalid[5], _out_wifireMux_T_4 connect out_wivalid[4], _out_wifireMux_T_4 connect out_wivalid[3], _out_wifireMux_T_4 connect out_wivalid[2], _out_wifireMux_T_4 connect out_wivalid[1], _out_wifireMux_T_4 connect out_wivalid[0], _out_wifireMux_T_4 node _out_wifireMux_T_5 = eq(_out_T, UInt<1>(0h0)) node _out_wifireMux_T_6 = or(out_wifireMux_out, _out_wifireMux_T_5) wire out_wifireMux_out_1 : UInt<1> node _out_wifireMux_T_7 = and(_out_wifireMux_T_2, out_frontSel_1) node _out_wifireMux_T_8 = and(_out_wifireMux_T_7, _out_T_2) connect out_wifireMux_out_1, UInt<1>(0h1) connect out_wivalid[10], _out_wifireMux_T_8 connect out_wivalid[9], _out_wifireMux_T_8 connect out_wivalid[8], _out_wifireMux_T_8 connect out_wivalid[7], _out_wifireMux_T_8 connect out_wivalid[6], _out_wifireMux_T_8 node _out_wifireMux_T_9 = eq(_out_T_2, UInt<1>(0h0)) node _out_wifireMux_T_10 = or(out_wifireMux_out_1, _out_wifireMux_T_9) wire out_wifireMux_out_2 : UInt<1> node _out_wifireMux_T_11 = and(_out_wifireMux_T_2, out_frontSel_2) node _out_wifireMux_T_12 = and(_out_wifireMux_T_11, _out_T_4) connect out_wifireMux_out_2, UInt<1>(0h1) connect out_wivalid[14], _out_wifireMux_T_12 connect out_wivalid[13], _out_wifireMux_T_12 connect out_wivalid[12], _out_wifireMux_T_12 connect out_wivalid[11], _out_wifireMux_T_12 node _out_wifireMux_T_13 = eq(_out_T_4, UInt<1>(0h0)) node _out_wifireMux_T_14 = or(out_wifireMux_out_2, _out_wifireMux_T_13) wire out_wifireMux_out_3 : UInt<1> node _out_wifireMux_T_15 = and(_out_wifireMux_T_2, out_frontSel_3) node _out_wifireMux_T_16 = and(_out_wifireMux_T_15, _out_T_6) connect out_wifireMux_out_3, UInt<1>(0h1) connect out_wivalid[15], _out_wifireMux_T_16 node _out_wifireMux_T_17 = eq(_out_T_6, UInt<1>(0h0)) node _out_wifireMux_T_18 = or(out_wifireMux_out_3, _out_wifireMux_T_17) node _out_wifireMux_T_19 = geq(out_iindex, UInt<3>(0h4)) wire _out_wifireMux_WIRE : UInt<1>[4] connect _out_wifireMux_WIRE[0], _out_wifireMux_T_6 connect _out_wifireMux_WIRE[1], _out_wifireMux_T_10 connect _out_wifireMux_WIRE[2], _out_wifireMux_T_14 connect _out_wifireMux_WIRE[3], _out_wifireMux_T_18 node out_wifireMux = mux(_out_wifireMux_T_19, UInt<1>(0h1), _out_wifireMux_WIRE[out_iindex]) node _out_rofireMux_T = and(out_front.valid, out.ready) node _out_rofireMux_T_1 = and(_out_rofireMux_T, out_front.bits.read) wire out_rofireMux_out : UInt<1> node _out_rofireMux_T_2 = and(_out_rofireMux_T_1, out_backSel_0) node _out_rofireMux_T_3 = and(_out_rofireMux_T_2, _out_T_1) connect out_rofireMux_out, UInt<1>(0h1) connect out_roready[5], _out_rofireMux_T_3 connect out_roready[4], _out_rofireMux_T_3 connect out_roready[3], _out_rofireMux_T_3 connect out_roready[2], _out_rofireMux_T_3 connect out_roready[1], _out_rofireMux_T_3 connect out_roready[0], _out_rofireMux_T_3 node _out_rofireMux_T_4 = eq(_out_T_1, UInt<1>(0h0)) node _out_rofireMux_T_5 = or(out_rofireMux_out, _out_rofireMux_T_4) wire out_rofireMux_out_1 : UInt<1> node _out_rofireMux_T_6 = and(_out_rofireMux_T_1, out_backSel_1) node _out_rofireMux_T_7 = and(_out_rofireMux_T_6, _out_T_3) connect out_rofireMux_out_1, UInt<1>(0h1) connect out_roready[10], _out_rofireMux_T_7 connect out_roready[9], _out_rofireMux_T_7 connect out_roready[8], _out_rofireMux_T_7 connect out_roready[7], _out_rofireMux_T_7 connect out_roready[6], _out_rofireMux_T_7 node _out_rofireMux_T_8 = eq(_out_T_3, UInt<1>(0h0)) node _out_rofireMux_T_9 = or(out_rofireMux_out_1, _out_rofireMux_T_8) wire out_rofireMux_out_2 : UInt<1> node _out_rofireMux_T_10 = and(_out_rofireMux_T_1, out_backSel_2) node _out_rofireMux_T_11 = and(_out_rofireMux_T_10, _out_T_5) connect out_rofireMux_out_2, UInt<1>(0h1) connect out_roready[14], _out_rofireMux_T_11 connect out_roready[13], _out_rofireMux_T_11 connect out_roready[12], _out_rofireMux_T_11 connect out_roready[11], _out_rofireMux_T_11 node _out_rofireMux_T_12 = eq(_out_T_5, UInt<1>(0h0)) node _out_rofireMux_T_13 = or(out_rofireMux_out_2, _out_rofireMux_T_12) wire out_rofireMux_out_3 : UInt<1> node _out_rofireMux_T_14 = and(_out_rofireMux_T_1, out_backSel_3) node _out_rofireMux_T_15 = and(_out_rofireMux_T_14, _out_T_7) connect out_rofireMux_out_3, UInt<1>(0h1) connect out_roready[15], _out_rofireMux_T_15 node _out_rofireMux_T_16 = eq(_out_T_7, UInt<1>(0h0)) node _out_rofireMux_T_17 = or(out_rofireMux_out_3, _out_rofireMux_T_16) node _out_rofireMux_T_18 = geq(out_oindex, UInt<3>(0h4)) wire _out_rofireMux_WIRE : UInt<1>[4] connect _out_rofireMux_WIRE[0], _out_rofireMux_T_5 connect _out_rofireMux_WIRE[1], _out_rofireMux_T_9 connect _out_rofireMux_WIRE[2], _out_rofireMux_T_13 connect _out_rofireMux_WIRE[3], _out_rofireMux_T_17 node out_rofireMux = mux(_out_rofireMux_T_18, UInt<1>(0h1), _out_rofireMux_WIRE[out_oindex]) node _out_wofireMux_T = and(out_front.valid, out.ready) node _out_wofireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wofireMux_T_2 = and(_out_wofireMux_T, _out_wofireMux_T_1) wire out_wofireMux_out : UInt<1> node _out_wofireMux_T_3 = and(_out_wofireMux_T_2, out_backSel_0) node _out_wofireMux_T_4 = and(_out_wofireMux_T_3, _out_T_1) connect out_wofireMux_out, UInt<1>(0h1) connect out_woready[5], _out_wofireMux_T_4 connect out_woready[4], _out_wofireMux_T_4 connect out_woready[3], _out_wofireMux_T_4 connect out_woready[2], _out_wofireMux_T_4 connect out_woready[1], _out_wofireMux_T_4 connect out_woready[0], _out_wofireMux_T_4 node _out_wofireMux_T_5 = eq(_out_T_1, UInt<1>(0h0)) node _out_wofireMux_T_6 = or(out_wofireMux_out, _out_wofireMux_T_5) wire out_wofireMux_out_1 : UInt<1> node _out_wofireMux_T_7 = and(_out_wofireMux_T_2, out_backSel_1) node _out_wofireMux_T_8 = and(_out_wofireMux_T_7, _out_T_3) connect out_wofireMux_out_1, UInt<1>(0h1) connect out_woready[10], _out_wofireMux_T_8 connect out_woready[9], _out_wofireMux_T_8 connect out_woready[8], _out_wofireMux_T_8 connect out_woready[7], _out_wofireMux_T_8 connect out_woready[6], _out_wofireMux_T_8 node _out_wofireMux_T_9 = eq(_out_T_3, UInt<1>(0h0)) node _out_wofireMux_T_10 = or(out_wofireMux_out_1, _out_wofireMux_T_9) wire out_wofireMux_out_2 : UInt<1> node _out_wofireMux_T_11 = and(_out_wofireMux_T_2, out_backSel_2) node _out_wofireMux_T_12 = and(_out_wofireMux_T_11, _out_T_5) connect out_wofireMux_out_2, UInt<1>(0h1) connect out_woready[14], _out_wofireMux_T_12 connect out_woready[13], _out_wofireMux_T_12 connect out_woready[12], _out_wofireMux_T_12 connect out_woready[11], _out_wofireMux_T_12 node _out_wofireMux_T_13 = eq(_out_T_5, UInt<1>(0h0)) node _out_wofireMux_T_14 = or(out_wofireMux_out_2, _out_wofireMux_T_13) wire out_wofireMux_out_3 : UInt<1> node _out_wofireMux_T_15 = and(_out_wofireMux_T_2, out_backSel_3) node _out_wofireMux_T_16 = and(_out_wofireMux_T_15, _out_T_7) connect out_wofireMux_out_3, UInt<1>(0h1) connect out_woready[15], _out_wofireMux_T_16 node _out_wofireMux_T_17 = eq(_out_T_7, UInt<1>(0h0)) node _out_wofireMux_T_18 = or(out_wofireMux_out_3, _out_wofireMux_T_17) node _out_wofireMux_T_19 = geq(out_oindex, UInt<3>(0h4)) wire _out_wofireMux_WIRE : UInt<1>[4] connect _out_wofireMux_WIRE[0], _out_wofireMux_T_6 connect _out_wofireMux_WIRE[1], _out_wofireMux_T_10 connect _out_wofireMux_WIRE[2], _out_wofireMux_T_14 connect _out_wofireMux_WIRE[3], _out_wofireMux_T_18 node out_wofireMux = mux(_out_wofireMux_T_19, UInt<1>(0h1), _out_wofireMux_WIRE[out_oindex]) node out_iready = mux(out_front.bits.read, out_rifireMux, out_wifireMux) node out_oready = mux(out_front.bits.read, out_rofireMux, out_wofireMux) node _out_in_ready_T = and(out_front.ready, out_iready) connect in.ready, _out_in_ready_T node _out_front_valid_T = and(in.valid, out_iready) connect out_front.valid, _out_front_valid_T node _out_front_ready_T = and(out.ready, out_oready) connect out_front.ready, _out_front_ready_T node _out_out_valid_T = and(out_front.valid, out_oready) connect out.valid, _out_out_valid_T connect out.bits.read, out_front.bits.read node _out_out_bits_data_T = geq(out_oindex, UInt<3>(0h4)) wire _out_out_bits_data_WIRE : UInt<1>[4] connect _out_out_bits_data_WIRE[0], _out_T_1 connect _out_out_bits_data_WIRE[1], _out_T_3 connect _out_out_bits_data_WIRE[2], _out_T_5 connect _out_out_bits_data_WIRE[3], _out_T_7 node _out_out_bits_data_T_1 = mux(_out_out_bits_data_T, UInt<1>(0h1), _out_out_bits_data_WIRE[out_oindex]) node _out_out_bits_data_T_2 = geq(out_oindex, UInt<3>(0h4)) wire _out_out_bits_data_WIRE_1 : UInt<64>[4] connect _out_out_bits_data_WIRE_1[0], _out_T_61 connect _out_out_bits_data_WIRE_1[1], _out_T_116 connect _out_out_bits_data_WIRE_1[2], _out_T_156 connect _out_out_bits_data_WIRE_1[3], _out_T_167 node _out_out_bits_data_T_3 = mux(_out_out_bits_data_T_2, UInt<1>(0h0), _out_out_bits_data_WIRE_1[out_oindex]) node _out_out_bits_data_T_4 = mux(_out_out_bits_data_T_1, _out_out_bits_data_T_3, UInt<1>(0h0)) connect out.bits.data, _out_out_bits_data_T_4 connect out.bits.extra, out_front.bits.extra connect in.valid, controlNodeIn.a.valid connect controlNodeIn.a.ready, in.ready connect controlNodeIn.d.valid, out.valid connect out.ready, controlNodeIn.d.ready wire controlNodeIn_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} connect controlNodeIn_d_bits_d.opcode, UInt<1>(0h0) connect controlNodeIn_d_bits_d.param, UInt<1>(0h0) connect controlNodeIn_d_bits_d.size, out.bits.extra.tlrr_extra.size connect controlNodeIn_d_bits_d.source, out.bits.extra.tlrr_extra.source connect controlNodeIn_d_bits_d.sink, UInt<1>(0h0) connect controlNodeIn_d_bits_d.denied, UInt<1>(0h0) invalidate controlNodeIn_d_bits_d.data connect controlNodeIn_d_bits_d.corrupt, UInt<1>(0h0) connect controlNodeIn.d.bits.corrupt, controlNodeIn_d_bits_d.corrupt connect controlNodeIn.d.bits.data, controlNodeIn_d_bits_d.data connect controlNodeIn.d.bits.denied, controlNodeIn_d_bits_d.denied connect controlNodeIn.d.bits.sink, controlNodeIn_d_bits_d.sink connect controlNodeIn.d.bits.source, controlNodeIn_d_bits_d.source connect controlNodeIn.d.bits.size, controlNodeIn_d_bits_d.size connect controlNodeIn.d.bits.param, controlNodeIn_d_bits_d.param connect controlNodeIn.d.bits.opcode, controlNodeIn_d_bits_d.opcode connect controlNodeIn.d.bits.data, out.bits.data node _controlNodeIn_d_bits_opcode_T = mux(out.bits.read, UInt<1>(0h1), UInt<1>(0h0)) connect controlNodeIn.d.bits.opcode, _controlNodeIn_d_bits_opcode_T wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<29>(0h0) connect _WIRE.bits.source, UInt<12>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<29>(0h0) connect _WIRE_2.bits.source, UInt<12>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1)	module TLUART( // @[UART.scala:127:25] input clock, // @[UART.scala:127:25] input reset, // @[UART.scala:127:25] output auto_int_xing_out_sync_0, // @[LazyModuleImp.scala:107:25] output auto_control_xing_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_control_xing_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_control_xing_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_control_xing_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_control_xing_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [11:0] auto_control_xing_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [28:0] auto_control_xing_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_control_xing_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_control_xing_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_control_xing_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_control_xing_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_control_xing_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_control_xing_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_control_xing_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [11:0] auto_control_xing_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_control_xing_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_io_out_txd, // @[LazyModuleImp.scala:107:25] input auto_io_out_rxd // @[LazyModuleImp.scala:107:25] ); wire out_front_valid; // @[RegisterRouter.scala:87:24] wire out_front_ready; // @[RegisterRouter.scala:87:24] wire out_bits_read; // @[RegisterRouter.scala:87:24] wire [11:0] out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [8:0] in_bits_index; // @[RegisterRouter.scala:73:18] wire in_bits_read; // @[RegisterRouter.scala:73:18] wire buffer_auto_out_d_valid; // @[Buffer.scala:40:9] wire buffer_auto_out_d_ready; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_d_bits_data; // @[Buffer.scala:40:9] wire [11:0] buffer_auto_out_d_bits_source; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_out_a_valid; // @[Buffer.scala:40:9] wire buffer_auto_out_a_ready; // @[Buffer.scala:40:9] wire buffer_auto_out_a_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_a_bits_data; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_out_a_bits_mask; // @[Buffer.scala:40:9] wire [28:0] buffer_auto_out_a_bits_address; // @[Buffer.scala:40:9] wire [11:0] buffer_auto_out_a_bits_source; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_a_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_d_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_d_ready; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_d_bits_data; // @[Buffer.scala:40:9] wire [11:0] buffer_auto_in_d_bits_source; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_d_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_d_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_a_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_a_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_a_bits_data; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [28:0] buffer_auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [11:0] buffer_auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire _rxq_io_deq_valid; // @[UART.scala:133:19] wire [7:0] _rxq_io_deq_bits; // @[UART.scala:133:19] wire [3:0] _rxq_io_count; // @[UART.scala:133:19] wire _rxm_io_out_valid; // @[UART.scala:132:19] wire [7:0] _rxm_io_out_bits; // @[UART.scala:132:19] wire _txq_io_enq_ready; // @[UART.scala:130:19] wire _txq_io_deq_valid; // @[UART.scala:130:19] wire [7:0] _txq_io_deq_bits; // @[UART.scala:130:19] wire [3:0] _txq_io_count; // @[UART.scala:130:19] wire _txm_io_in_ready; // @[UART.scala:129:19] wire _txm_io_tx_busy; // @[UART.scala:129:19] wire auto_control_xing_in_a_valid_0 = auto_control_xing_in_a_valid; // @[UART.scala:127:25] wire [2:0] auto_control_xing_in_a_bits_opcode_0 = auto_control_xing_in_a_bits_opcode; // @[UART.scala:127:25] wire [2:0] auto_control_xing_in_a_bits_param_0 = auto_control_xing_in_a_bits_param; // @[UART.scala:127:25] wire [1:0] auto_control_xing_in_a_bits_size_0 = auto_control_xing_in_a_bits_size; // @[UART.scala:127:25] wire [11:0] auto_control_xing_in_a_bits_source_0 = auto_control_xing_in_a_bits_source; // @[UART.scala:127:25] wire [28:0] auto_control_xing_in_a_bits_address_0 = auto_control_xing_in_a_bits_address; // @[UART.scala:127:25] wire [7:0] auto_control_xing_in_a_bits_mask_0 = auto_control_xing_in_a_bits_mask; // @[UART.scala:127:25] wire [63:0] auto_control_xing_in_a_bits_data_0 = auto_control_xing_in_a_bits_data; // @[UART.scala:127:25] wire auto_control_xing_in_a_bits_corrupt_0 = auto_control_xing_in_a_bits_corrupt; // @[UART.scala:127:25] wire auto_control_xing_in_d_ready_0 = auto_control_xing_in_d_ready; // @[UART.scala:127:25] wire auto_io_out_rxd_0 = auto_io_out_rxd; // @[UART.scala:127:25] wire [8:0] out_maskMatch = 9'h1FC; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_15 = 8'h0; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_16 = 8'h0; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T = 8'h0; // @[RegisterRouter.scala:87:24] wire [8:0] out_prepend = 9'h0; // @[RegisterRouter.scala:87:24] wire [30:0] _out_T_24 = 31'h0; // @[RegisterRouter.scala:87:24] wire [30:0] _out_T_25 = 31'h0; // @[RegisterRouter.scala:87:24] wire [30:0] _out_prepend_T_1 = 31'h0; // @[RegisterRouter.scala:87:24] wire [2:0] controlNodeIn_d_bits_d_opcode = 3'h0; // @[Edges.scala:792:17] wire [63:0] controlNodeIn_d_bits_d_data = 64'h0; // @[Edges.scala:792:17] wire auto_control_xing_in_d_bits_sink = 1'h0; // @[UART.scala:127:25] wire auto_control_xing_in_d_bits_denied = 1'h0; // @[UART.scala:127:25] wire auto_control_xing_in_d_bits_corrupt = 1'h0; // @[UART.scala:127:25] wire buffer_auto_in_d_bits_sink = 1'h0; // @[Buffer.scala:40:9] wire buffer_auto_in_d_bits_denied = 1'h0; // @[Buffer.scala:40:9] wire buffer_auto_in_d_bits_corrupt = 1'h0; // @[Buffer.scala:40:9] wire buffer_auto_out_d_bits_sink = 1'h0; // @[Buffer.scala:40:9] wire buffer_auto_out_d_bits_denied = 1'h0; // @[Buffer.scala:40:9] wire buffer_auto_out_d_bits_corrupt = 1'h0; // @[Buffer.scala:40:9] wire buffer_nodeOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17] wire buffer_nodeOut_d_bits_denied = 1'h0; // @[MixedNode.scala:542:17] wire buffer_nodeOut_d_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire buffer_nodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire buffer_nodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire buffer_nodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire controlNodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire controlNodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire controlNodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire controlXingOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17] wire controlXingOut_d_bits_denied = 1'h0; // @[MixedNode.scala:542:17] wire controlXingOut_d_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire controlXingIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire controlXingIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire controlXingIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire _ie_WIRE_rxwm = 1'h0; // @[UART.scala:186:32] wire _ie_WIRE_txwm = 1'h0; // @[UART.scala:186:32] wire _out_rifireMux_T_18 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wifireMux_T_19 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_rofireMux_T_18 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wofireMux_T_19 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T_2 = 1'h0; // @[MuxLiteral.scala:49:17] wire controlNodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:792:17] wire controlNodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:792:17] wire controlNodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:792:17] wire [1:0] auto_control_xing_in_d_bits_param = 2'h0; // @[UART.scala:127:25] wire [1:0] buffer_auto_in_d_bits_param = 2'h0; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_d_bits_param = 2'h0; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeOut_d_bits_param = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] buffer_nodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] controlNodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] controlXingOut_d_bits_param = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] controlXingIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] controlNodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:792:17] wire intXingOut_sync_0; // @[MixedNode.scala:542:17] wire out_rifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_18 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_rofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_18 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_iready = 1'h1; // @[RegisterRouter.scala:87:24] wire out_oready = 1'h1; // @[RegisterRouter.scala:87:24] wire controlXingIn_a_ready; // @[MixedNode.scala:551:17] wire controlXingIn_a_valid = auto_control_xing_in_a_valid_0; // @[UART.scala:127:25] wire [2:0] controlXingIn_a_bits_opcode = auto_control_xing_in_a_bits_opcode_0; // @[UART.scala:127:25] wire [2:0] controlXingIn_a_bits_param = auto_control_xing_in_a_bits_param_0; // @[UART.scala:127:25] wire [1:0] controlXingIn_a_bits_size = auto_control_xing_in_a_bits_size_0; // @[UART.scala:127:25] wire [11:0] controlXingIn_a_bits_source = auto_control_xing_in_a_bits_source_0; // @[UART.scala:127:25] wire [28:0] controlXingIn_a_bits_address = auto_control_xing_in_a_bits_address_0; // @[UART.scala:127:25] wire [7:0] controlXingIn_a_bits_mask = auto_control_xing_in_a_bits_mask_0; // @[UART.scala:127:25] wire [63:0] controlXingIn_a_bits_data = auto_control_xing_in_a_bits_data_0; // @[UART.scala:127:25] wire controlXingIn_a_bits_corrupt = auto_control_xing_in_a_bits_corrupt_0; // @[UART.scala:127:25] wire controlXingIn_d_ready = auto_control_xing_in_d_ready_0; // @[UART.scala:127:25] wire controlXingIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] controlXingIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] controlXingIn_d_bits_size; // @[MixedNode.scala:551:17] wire [11:0] controlXingIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] controlXingIn_d_bits_data; // @[MixedNode.scala:551:17] wire ioNodeOut_txd; // @[MixedNode.scala:542:17] wire ioNodeOut_rxd = auto_io_out_rxd_0; // @[UART.scala:127:25] wire auto_int_xing_out_sync_0_0; // @[UART.scala:127:25] wire auto_control_xing_in_a_ready_0; // @[UART.scala:127:25] wire [2:0] auto_control_xing_in_d_bits_opcode_0; // @[UART.scala:127:25] wire [1:0] auto_control_xing_in_d_bits_size_0; // @[UART.scala:127:25] wire [11:0] auto_control_xing_in_d_bits_source_0; // @[UART.scala:127:25] wire [63:0] auto_control_xing_in_d_bits_data_0; // @[UART.scala:127:25] wire auto_control_xing_in_d_valid_0; // @[UART.scala:127:25] wire auto_io_out_txd_0; // @[UART.scala:127:25] wire buffer_nodeIn_a_ready; // @[MixedNode.scala:551:17] wire controlXingOut_a_ready = buffer_auto_in_a_ready; // @[Buffer.scala:40:9] wire controlXingOut_a_valid; // @[MixedNode.scala:542:17] wire buffer_nodeIn_a_valid = buffer_auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] controlXingOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] buffer_nodeIn_a_bits_opcode = buffer_auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] controlXingOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] buffer_nodeIn_a_bits_param = buffer_auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [1:0] controlXingOut_a_bits_size; // @[MixedNode.scala:542:17] wire [1:0] buffer_nodeIn_a_bits_size = buffer_auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [11:0] controlXingOut_a_bits_source; // @[MixedNode.scala:542:17] wire [11:0] buffer_nodeIn_a_bits_source = buffer_auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [28:0] controlXingOut_a_bits_address; // @[MixedNode.scala:542:17] wire [28:0] buffer_nodeIn_a_bits_address = buffer_auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] controlXingOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [7:0] buffer_nodeIn_a_bits_mask = buffer_auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] controlXingOut_a_bits_data; // @[MixedNode.scala:542:17] wire [63:0] buffer_nodeIn_a_bits_data = buffer_auto_in_a_bits_data; // @[Buffer.scala:40:9] wire controlXingOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire buffer_nodeIn_a_bits_corrupt = buffer_auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire controlXingOut_d_ready; // @[MixedNode.scala:542:17] wire buffer_nodeIn_d_ready = buffer_auto_in_d_ready; // @[Buffer.scala:40:9] wire buffer_nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] buffer_nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire controlXingOut_d_valid = buffer_auto_in_d_valid; // @[Buffer.scala:40:9] wire [2:0] controlXingOut_d_bits_opcode = buffer_auto_in_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [11:0] buffer_nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [1:0] controlXingOut_d_bits_size = buffer_auto_in_d_bits_size; // @[Buffer.scala:40:9] wire [11:0] controlXingOut_d_bits_source = buffer_auto_in_d_bits_source; // @[Buffer.scala:40:9] wire [63:0] buffer_nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire [63:0] controlXingOut_d_bits_data = buffer_auto_in_d_bits_data; // @[Buffer.scala:40:9] wire controlNodeIn_a_ready; // @[MixedNode.scala:551:17] wire buffer_nodeOut_a_ready = buffer_auto_out_a_ready; // @[Buffer.scala:40:9] wire buffer_nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] buffer_nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire controlNodeIn_a_valid = buffer_auto_out_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] controlNodeIn_a_bits_opcode = buffer_auto_out_a_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [2:0] controlNodeIn_a_bits_param = buffer_auto_out_a_bits_param; // @[Buffer.scala:40:9] wire [11:0] buffer_nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [1:0] controlNodeIn_a_bits_size = buffer_auto_out_a_bits_size; // @[Buffer.scala:40:9] wire [28:0] buffer_nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [11:0] controlNodeIn_a_bits_source = buffer_auto_out_a_bits_source; // @[Buffer.scala:40:9] wire [7:0] buffer_nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [28:0] controlNodeIn_a_bits_address = buffer_auto_out_a_bits_address; // @[Buffer.scala:40:9] wire [63:0] buffer_nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire [7:0] controlNodeIn_a_bits_mask = buffer_auto_out_a_bits_mask; // @[Buffer.scala:40:9] wire buffer_nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire [63:0] controlNodeIn_a_bits_data = buffer_auto_out_a_bits_data; // @[Buffer.scala:40:9] wire buffer_nodeOut_d_ready; // @[MixedNode.scala:542:17] wire controlNodeIn_a_bits_corrupt = buffer_auto_out_a_bits_corrupt; // @[Buffer.scala:40:9] wire controlNodeIn_d_ready = buffer_auto_out_d_ready; // @[Buffer.scala:40:9] wire controlNodeIn_d_valid; // @[MixedNode.scala:551:17] wire buffer_nodeOut_d_valid = buffer_auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] controlNodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] buffer_nodeOut_d_bits_opcode = buffer_auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] controlNodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] buffer_nodeOut_d_bits_size = buffer_auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [11:0] controlNodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [11:0] buffer_nodeOut_d_bits_source = buffer_auto_out_d_bits_source; // @[Buffer.scala:40:9] wire [63:0] controlNodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire [63:0] buffer_nodeOut_d_bits_data = buffer_auto_out_d_bits_data; // @[Buffer.scala:40:9] assign buffer_nodeIn_a_ready = buffer_nodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_out_a_valid = buffer_nodeOut_a_valid; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_opcode = buffer_nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_param = buffer_nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_size = buffer_nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_source = buffer_nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_address = buffer_nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_mask = buffer_nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_data = buffer_nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_corrupt = buffer_nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_out_d_ready = buffer_nodeOut_d_ready; // @[Buffer.scala:40:9] assign buffer_nodeIn_d_valid = buffer_nodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_opcode = buffer_nodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_size = buffer_nodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_source = buffer_nodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_data = buffer_nodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_in_a_ready = buffer_nodeIn_a_ready; // @[Buffer.scala:40:9] assign buffer_nodeOut_a_valid = buffer_nodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_opcode = buffer_nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_param = buffer_nodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_size = buffer_nodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_source = buffer_nodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_address = buffer_nodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_mask = buffer_nodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_data = buffer_nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_corrupt = buffer_nodeIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_d_ready = buffer_nodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_in_d_valid = buffer_nodeIn_d_valid; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_opcode = buffer_nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_size = buffer_nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_source = buffer_nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_data = buffer_nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign auto_io_out_txd_0 = ioNodeOut_txd; // @[UART.scala:127:25] wire _intnodeOut_0_T_2; // @[UART.scala:191:41] wire intnodeOut_0; // @[MixedNode.scala:542:17] wire in_ready; // @[RegisterRouter.scala:73:18] assign buffer_auto_out_a_ready = controlNodeIn_a_ready; // @[Buffer.scala:40:9] wire in_valid = controlNodeIn_a_valid; // @[RegisterRouter.scala:73:18] wire [1:0] in_bits_extra_tlrr_extra_size = controlNodeIn_a_bits_size; // @[RegisterRouter.scala:73:18] wire [11:0] in_bits_extra_tlrr_extra_source = controlNodeIn_a_bits_source; // @[RegisterRouter.scala:73:18] wire [7:0] in_bits_mask = controlNodeIn_a_bits_mask; // @[RegisterRouter.scala:73:18] wire [63:0] in_bits_data = controlNodeIn_a_bits_data; // @[RegisterRouter.scala:73:18] wire out_ready = controlNodeIn_d_ready; // @[RegisterRouter.scala:87:24] wire out_valid; // @[RegisterRouter.scala:87:24] assign buffer_auto_out_d_valid = controlNodeIn_d_valid; // @[Buffer.scala:40:9] assign buffer_auto_out_d_bits_opcode = controlNodeIn_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] controlNodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign buffer_auto_out_d_bits_size = controlNodeIn_d_bits_size; // @[Buffer.scala:40:9] wire [11:0] controlNodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign buffer_auto_out_d_bits_source = controlNodeIn_d_bits_source; // @[Buffer.scala:40:9] wire [63:0] out_bits_data; // @[RegisterRouter.scala:87:24] assign buffer_auto_out_d_bits_data = controlNodeIn_d_bits_data; // @[Buffer.scala:40:9] assign controlXingIn_a_ready = controlXingOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_in_a_valid = controlXingOut_a_valid; // @[Buffer.scala:40:9] assign buffer_auto_in_a_bits_opcode = controlXingOut_a_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_in_a_bits_param = controlXingOut_a_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_in_a_bits_size = controlXingOut_a_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_in_a_bits_source = controlXingOut_a_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_in_a_bits_address = controlXingOut_a_bits_address; // @[Buffer.scala:40:9] assign buffer_auto_in_a_bits_mask = controlXingOut_a_bits_mask; // @[Buffer.scala:40:9] assign buffer_auto_in_a_bits_data = controlXingOut_a_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_in_a_bits_corrupt = controlXingOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_in_d_ready = controlXingOut_d_ready; // @[Buffer.scala:40:9] assign controlXingIn_d_valid = controlXingOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign controlXingIn_d_bits_opcode = controlXingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign controlXingIn_d_bits_size = controlXingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign controlXingIn_d_bits_source = controlXingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign controlXingIn_d_bits_data = controlXingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign auto_control_xing_in_a_ready_0 = controlXingIn_a_ready; // @[UART.scala:127:25] assign controlXingOut_a_valid = controlXingIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign controlXingOut_a_bits_opcode = controlXingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign controlXingOut_a_bits_param = controlXingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign controlXingOut_a_bits_size = controlXingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign controlXingOut_a_bits_source = controlXingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign controlXingOut_a_bits_address = controlXingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign controlXingOut_a_bits_mask = controlXingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign controlXingOut_a_bits_data = controlXingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign controlXingOut_a_bits_corrupt = controlXingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign controlXingOut_d_ready = controlXingIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_control_xing_in_d_valid_0 = controlXingIn_d_valid; // @[UART.scala:127:25] assign auto_control_xing_in_d_bits_opcode_0 = controlXingIn_d_bits_opcode; // @[UART.scala:127:25] assign auto_control_xing_in_d_bits_size_0 = controlXingIn_d_bits_size; // @[UART.scala:127:25] assign auto_control_xing_in_d_bits_source_0 = controlXingIn_d_bits_source; // @[UART.scala:127:25] assign auto_control_xing_in_d_bits_data_0 = controlXingIn_d_bits_data; // @[UART.scala:127:25] wire intXingIn_sync_0; // @[MixedNode.scala:551:17] assign auto_int_xing_out_sync_0_0 = intXingOut_sync_0; // @[UART.scala:127:25] assign intXingOut_sync_0 = intXingIn_sync_0; // @[MixedNode.scala:542:17, :551:17] reg [15:0] div; // @[UART.scala:135:20] wire [15:0] _out_T_166 = div; // @[RegisterRouter.scala:87:24] reg txen; // @[UART.scala:141:21] wire _out_T_71 = txen; // @[RegisterRouter.scala:87:24] reg rxen; // @[UART.scala:142:21] reg [3:0] txwm; // @[UART.scala:149:21] reg [3:0] rxwm; // @[UART.scala:150:21] reg nstop; // @[UART.scala:151:22] wire _tx_busy_T = \|_txq_io_count; // @[UART.scala:130:19, :175:49] wire _tx_busy_T_1 = _txm_io_tx_busy \| _tx_busy_T; // @[UART.scala:129:19, :175:{33,49}] wire tx_busy = _tx_busy_T_1 & txen; // @[UART.scala:141:21, :175:{33,54}] reg ie_rxwm; // @[UART.scala:186:19] reg ie_txwm; // @[UART.scala:186:19] wire _out_T_126 = ie_txwm; // @[RegisterRouter.scala:87:24] wire _ip_rxwm_T; // @[UART.scala:190:28] wire _ip_txwm_T; // @[UART.scala:189:28] wire ip_rxwm; // @[UART.scala:187:16] wire ip_txwm; // @[UART.scala:187:16] assign _ip_txwm_T = _txq_io_count < txwm; // @[UART.scala:130:19, :149:21, :189:28] assign ip_txwm = _ip_txwm_T; // @[UART.scala:187:16, :189:28] assign _ip_rxwm_T = _rxq_io_count > rxwm; // @[UART.scala:133:19, :150:21, :190:28] assign ip_rxwm = _ip_rxwm_T; // @[UART.scala:187:16, :190:28] wire _intnodeOut_0_T = ip_txwm & ie_txwm; // @[UART.scala:186:19, :187:16, :191:29] wire _intnodeOut_0_T_1 = ip_rxwm & ie_rxwm; // @[UART.scala:186:19, :187:16, :191:53] assign _intnodeOut_0_T_2 = _intnodeOut_0_T \| _intnodeOut_0_T_1; // @[UART.scala:191:{29,41,53}] assign intnodeOut_0 = _intnodeOut_0_T_2; // @[UART.scala:191:41] wire _out_quash_T_1; // @[RegMapFIFO.scala:26:26] wire quash; // @[RegMapFIFO.scala:11:21] wire _out_in_ready_T; // @[RegisterRouter.scala:87:24] assign controlNodeIn_a_ready = in_ready; // @[RegisterRouter.scala:73:18] wire _in_bits_read_T; // @[RegisterRouter.scala:74:36] wire _out_front_valid_T = in_valid; // @[RegisterRouter.scala:73:18, :87:24] wire out_front_bits_read = in_bits_read; // @[RegisterRouter.scala:73:18, :87:24] wire [8:0] out_front_bits_index = in_bits_index; // @[RegisterRouter.scala:73:18, :87:24] wire [63:0] out_front_bits_data = in_bits_data; // @[RegisterRouter.scala:73:18, :87:24] wire [7:0] out_front_bits_mask = in_bits_mask; // @[RegisterRouter.scala:73:18, :87:24] wire [11:0] out_front_bits_extra_tlrr_extra_source = in_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:73:18, :87:24] wire [1:0] out_front_bits_extra_tlrr_extra_size = in_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:73:18, :87:24] assign _in_bits_read_T = controlNodeIn_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36] assign in_bits_read = _in_bits_read_T; // @[RegisterRouter.scala:73:18, :74:36] wire [25:0] _in_bits_index_T = controlNodeIn_a_bits_address[28:3]; // @[Edges.scala:192:34] assign in_bits_index = _in_bits_index_T[8:0]; // @[RegisterRouter.scala:73:18, :75:19] wire _out_front_ready_T = out_ready; // @[RegisterRouter.scala:87:24] wire _out_out_valid_T; // @[RegisterRouter.scala:87:24] assign controlNodeIn_d_valid = out_valid; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24] wire _controlNodeIn_d_bits_opcode_T = out_bits_read; // @[RegisterRouter.scala:87:24, :105:25] assign controlNodeIn_d_bits_data = out_bits_data; // @[RegisterRouter.scala:87:24] assign controlNodeIn_d_bits_d_source = out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [1:0] out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign controlNodeIn_d_bits_d_size = out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign _out_in_ready_T = out_front_ready; // @[RegisterRouter.scala:87:24] assign _out_out_valid_T = out_front_valid; // @[RegisterRouter.scala:87:24] assign out_bits_read = out_front_bits_read; // @[RegisterRouter.scala:87:24] assign out_bits_extra_tlrr_extra_source = out_front_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] assign out_bits_extra_tlrr_extra_size = out_front_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] wire [8:0] _GEN = out_front_bits_index & 9'h1FC; // @[RegisterRouter.scala:87:24] wire [8:0] out_findex; // @[RegisterRouter.scala:87:24] assign out_findex = _GEN; // @[RegisterRouter.scala:87:24] wire [8:0] out_bindex; // @[RegisterRouter.scala:87:24] assign out_bindex = _GEN; // @[RegisterRouter.scala:87:24] wire _GEN_0 = out_findex == 9'h0; // @[RegisterRouter.scala:87:24] wire _out_T; // @[RegisterRouter.scala:87:24] assign _out_T = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_T_2; // @[RegisterRouter.scala:87:24] assign _out_T_2 = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_T_4; // @[RegisterRouter.scala:87:24] assign _out_T_4 = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_T_6; // @[RegisterRouter.scala:87:24] assign _out_T_6 = _GEN_0; // @[RegisterRouter.scala:87:24] wire _GEN_1 = out_bindex == 9'h0; // @[RegisterRouter.scala:87:24] wire _out_T_1; // @[RegisterRouter.scala:87:24] assign _out_T_1 = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_T_3; // @[RegisterRouter.scala:87:24] assign _out_T_3 = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_T_5; // @[RegisterRouter.scala:87:24] assign _out_T_5 = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_T_7; // @[RegisterRouter.scala:87:24] assign _out_T_7 = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_0 = _out_T_1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_1 = _out_T_3; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2 = _out_T_5; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_3 = _out_T_7; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_15; // @[RegisterRouter.scala:87:24] wire out_rivalid_0; // @[RegisterRouter.scala:87:24] wire out_rivalid_1; // @[RegisterRouter.scala:87:24] wire out_rivalid_2; // @[RegisterRouter.scala:87:24] wire out_rivalid_3; // @[RegisterRouter.scala:87:24] wire out_rivalid_4; // @[RegisterRouter.scala:87:24] wire out_rivalid_5; // @[RegisterRouter.scala:87:24] wire out_rivalid_6; // @[RegisterRouter.scala:87:24] wire out_rivalid_7; // @[RegisterRouter.scala:87:24] wire out_rivalid_8; // @[RegisterRouter.scala:87:24] wire out_rivalid_9; // @[RegisterRouter.scala:87:24] wire out_rivalid_10; // @[RegisterRouter.scala:87:24] wire out_rivalid_11; // @[RegisterRouter.scala:87:24] wire out_rivalid_12; // @[RegisterRouter.scala:87:24] wire out_rivalid_13; // @[RegisterRouter.scala:87:24] wire out_rivalid_14; // @[RegisterRouter.scala:87:24] wire out_rivalid_15; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_16; // @[RegisterRouter.scala:87:24] wire out_wivalid_0; // @[RegisterRouter.scala:87:24] wire out_wivalid_1; // @[RegisterRouter.scala:87:24] wire out_wivalid_2; // @[RegisterRouter.scala:87:24] wire out_wivalid_3; // @[RegisterRouter.scala:87:24] wire out_wivalid_4; // @[RegisterRouter.scala:87:24] wire out_wivalid_5; // @[RegisterRouter.scala:87:24] wire out_wivalid_6; // @[RegisterRouter.scala:87:24] wire out_wivalid_7; // @[RegisterRouter.scala:87:24] wire out_wivalid_8; // @[RegisterRouter.scala:87:24] wire out_wivalid_9; // @[RegisterRouter.scala:87:24] wire out_wivalid_10; // @[RegisterRouter.scala:87:24] wire out_wivalid_11; // @[RegisterRouter.scala:87:24] wire out_wivalid_12; // @[RegisterRouter.scala:87:24] wire out_wivalid_13; // @[RegisterRouter.scala:87:24] wire out_wivalid_14; // @[RegisterRouter.scala:87:24] wire out_wivalid_15; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_15; // @[RegisterRouter.scala:87:24] wire out_roready_0; // @[RegisterRouter.scala:87:24] wire out_roready_1; // @[RegisterRouter.scala:87:24] wire out_roready_2; // @[RegisterRouter.scala:87:24] wire out_roready_3; // @[RegisterRouter.scala:87:24] wire out_roready_4; // @[RegisterRouter.scala:87:24] wire out_roready_5; // @[RegisterRouter.scala:87:24] wire out_roready_6; // @[RegisterRouter.scala:87:24] wire out_roready_7; // @[RegisterRouter.scala:87:24] wire out_roready_8; // @[RegisterRouter.scala:87:24] wire out_roready_9; // @[RegisterRouter.scala:87:24] wire out_roready_10; // @[RegisterRouter.scala:87:24] wire out_roready_11; // @[RegisterRouter.scala:87:24] wire out_roready_12; // @[RegisterRouter.scala:87:24] wire out_roready_13; // @[RegisterRouter.scala:87:24] wire out_roready_14; // @[RegisterRouter.scala:87:24] wire out_roready_15; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_16; // @[RegisterRouter.scala:87:24] wire out_woready_0; // @[RegisterRouter.scala:87:24] wire out_woready_1; // @[RegisterRouter.scala:87:24] wire out_woready_2; // @[RegisterRouter.scala:87:24] wire out_woready_3; // @[RegisterRouter.scala:87:24] wire out_woready_4; // @[RegisterRouter.scala:87:24] wire out_woready_5; // @[RegisterRouter.scala:87:24] wire out_woready_6; // @[RegisterRouter.scala:87:24] wire out_woready_7; // @[RegisterRouter.scala:87:24] wire out_woready_8; // @[RegisterRouter.scala:87:24] wire out_woready_9; // @[RegisterRouter.scala:87:24] wire out_woready_10; // @[RegisterRouter.scala:87:24] wire out_woready_11; // @[RegisterRouter.scala:87:24] wire out_woready_12; // @[RegisterRouter.scala:87:24] wire out_woready_13; // @[RegisterRouter.scala:87:24] wire out_woready_14; // @[RegisterRouter.scala:87:24] wire out_woready_15; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_8 = {8{_out_frontMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_9 = {8{_out_frontMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_10 = {8{_out_frontMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_11 = {8{_out_frontMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_12 = {8{_out_frontMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_13 = {8{_out_frontMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_14 = {8{_out_frontMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_15 = {8{_out_frontMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_lo = {_out_frontMask_T_9, _out_frontMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_hi = {_out_frontMask_T_11, _out_frontMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_lo = {out_frontMask_lo_hi, out_frontMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_lo = {_out_frontMask_T_13, _out_frontMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_hi = {_out_frontMask_T_15, _out_frontMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_hi = {out_frontMask_hi_hi, out_frontMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_frontMask = {out_frontMask_hi, out_frontMask_lo}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_8 = {8{_out_backMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_9 = {8{_out_backMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_10 = {8{_out_backMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_11 = {8{_out_backMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_12 = {8{_out_backMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_13 = {8{_out_backMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_14 = {8{_out_backMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_15 = {8{_out_backMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_lo = {_out_backMask_T_9, _out_backMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_hi = {_out_backMask_T_11, _out_backMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_lo = {out_backMask_lo_hi, out_backMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_lo = {_out_backMask_T_13, _out_backMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_hi = {_out_backMask_T_15, _out_backMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_hi = {out_backMask_hi_hi, out_backMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_backMask = {out_backMask_hi, out_backMask_lo}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire out_rimask = \|_out_rimask_T; // @[RegisterRouter.scala:87:24] wire out_wimask = &_out_wimask_T; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire out_romask = \|_out_romask_T; // @[RegisterRouter.scala:87:24] wire out_womask = &_out_womask_T; // @[RegisterRouter.scala:87:24] wire out_f_rivalid = out_rivalid_0 & out_rimask; // @[RegisterRouter.scala:87:24] wire out_f_roready = out_roready_0 & out_romask; // @[RegisterRouter.scala:87:24] wire out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala:87:24] wire _out_T_9 = out_f_wivalid; // @[RegisterRouter.scala:87:24] wire out_f_woready = out_woready_0 & out_womask; // @[RegisterRouter.scala:87:24] wire _out_T_10 = out_f_woready; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire _out_txq_io_enq_valid_T = ~quash; // @[RegMapFIFO.scala:11:21, :18:33] wire _out_txq_io_enq_valid_T_1 = out_f_woready & _out_txq_io_enq_valid_T; // @[RegisterRouter.scala:87:24] wire _out_T_11 = ~out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_12 = ~out_wimask; // @[RegisterRouter.scala:87:24] wire _out_T_13 = ~out_romask; // @[RegisterRouter.scala:87:24] wire _out_T_14 = ~out_womask; // @[RegisterRouter.scala:87:24] wire [22:0] _out_rimask_T_1 = out_frontMask[30:8]; // @[RegisterRouter.scala:87:24] wire [22:0] _out_wimask_T_1 = out_frontMask[30:8]; // @[RegisterRouter.scala:87:24] wire out_rimask_1 = \|_out_rimask_T_1; // @[RegisterRouter.scala:87:24] wire out_wimask_1 = &_out_wimask_T_1; // @[RegisterRouter.scala:87:24] wire [22:0] _out_romask_T_1 = out_backMask[30:8]; // @[RegisterRouter.scala:87:24] wire [22:0] _out_womask_T_1 = out_backMask[30:8]; // @[RegisterRouter.scala:87:24] wire out_romask_1 = \|_out_romask_T_1; // @[RegisterRouter.scala:87:24] wire out_womask_1 = &_out_womask_T_1; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1 = out_rivalid_1 & out_rimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_18 = out_f_rivalid_1; // @[RegisterRouter.scala:87:24] wire out_f_roready_1 = out_roready_1 & out_romask_1; // @[RegisterRouter.scala:87:24] wire _out_T_19 = out_f_roready_1; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1 = out_wivalid_1 & out_wimask_1; // @[RegisterRouter.scala:87:24] wire out_f_woready_1 = out_woready_1 & out_womask_1; // @[RegisterRouter.scala:87:24] wire [22:0] _out_T_17 = out_front_bits_data[30:8]; // @[RegisterRouter.scala:87:24] wire _out_T_20 = ~out_rimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_21 = ~out_wimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_22 = ~out_romask_1; // @[RegisterRouter.scala:87:24] wire _out_T_23 = ~out_womask_1; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_2 = out_frontMask[31]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_2 = out_frontMask[31]; // @[RegisterRouter.scala:87:24] wire out_rimask_2 = _out_rimask_T_2; // @[RegisterRouter.scala:87:24] wire out_wimask_2 = _out_wimask_T_2; // @[RegisterRouter.scala:87:24] wire _out_romask_T_2 = out_backMask[31]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_2 = out_backMask[31]; // @[RegisterRouter.scala:87:24] wire out_romask_2 = _out_romask_T_2; // @[RegisterRouter.scala:87:24] wire out_womask_2 = _out_womask_T_2; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_2 = out_rivalid_2 & out_rimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_27 = out_f_rivalid_2; // @[RegisterRouter.scala:87:24] wire out_f_roready_2 = out_roready_2 & out_romask_2; // @[RegisterRouter.scala:87:24] wire _out_T_28 = out_f_roready_2; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_2 = out_wivalid_2 & out_wimask_2; // @[RegisterRouter.scala:87:24] wire out_f_woready_2 = out_woready_2 & out_womask_2; // @[RegisterRouter.scala:87:24] wire _out_T_26 = out_front_bits_data[31]; // @[RegisterRouter.scala:87:24] wire _out_quash_T = _out_T_26; // @[RegisterRouter.scala:87:24] assign _out_quash_T_1 = out_f_woready_2 & _out_quash_T; // @[RegisterRouter.scala:87:24] assign quash = _out_quash_T_1; // @[RegMapFIFO.scala:11:21, :26:26] wire _out_T_29 = ~out_rimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_30 = ~out_wimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_31 = ~out_romask_2; // @[RegisterRouter.scala:87:24] wire _out_T_32 = ~out_womask_2; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1 = {~_txq_io_enq_ready, 31'h0}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_33 = out_prepend_1; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_34 = _out_T_33; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_2 = _out_T_34; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_3 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_3 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24] wire out_rimask_3 = \|_out_rimask_T_3; // @[RegisterRouter.scala:87:24] wire out_wimask_3 = &_out_wimask_T_3; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_3 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_3 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24] wire out_romask_3 = \|_out_romask_T_3; // @[RegisterRouter.scala:87:24] wire out_womask_3 = &_out_womask_T_3; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_3 = out_rivalid_3 & out_rimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_36 = out_f_rivalid_3; // @[RegisterRouter.scala:87:24] wire out_f_roready_3 = out_roready_3 & out_romask_3; // @[RegisterRouter.scala:87:24] wire _out_T_37 = out_f_roready_3; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_3 = out_wivalid_3 & out_wimask_3; // @[RegisterRouter.scala:87:24] wire out_f_woready_3 = out_woready_3 & out_womask_3; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_35 = out_front_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire _out_T_38 = ~out_rimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_39 = ~out_wimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_40 = ~out_romask_3; // @[RegisterRouter.scala:87:24] wire _out_T_41 = ~out_womask_3; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_2 = {_rxq_io_deq_bits, _out_prepend_T_2}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_42 = out_prepend_2; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_43 = _out_T_42; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_3 = _out_T_43; // @[RegisterRouter.scala:87:24] wire [22:0] _out_rimask_T_4 = out_frontMask[62:40]; // @[RegisterRouter.scala:87:24] wire [22:0] _out_wimask_T_4 = out_frontMask[62:40]; // @[RegisterRouter.scala:87:24] wire out_rimask_4 = \|_out_rimask_T_4; // @[RegisterRouter.scala:87:24] wire out_wimask_4 = &_out_wimask_T_4; // @[RegisterRouter.scala:87:24] wire [22:0] _out_romask_T_4 = out_backMask[62:40]; // @[RegisterRouter.scala:87:24] wire [22:0] _out_womask_T_4 = out_backMask[62:40]; // @[RegisterRouter.scala:87:24] wire out_romask_4 = \|_out_romask_T_4; // @[RegisterRouter.scala:87:24] wire out_womask_4 = &_out_womask_T_4; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_4 = out_rivalid_4 & out_rimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_45 = out_f_rivalid_4; // @[RegisterRouter.scala:87:24] wire out_f_roready_4 = out_roready_4 & out_romask_4; // @[RegisterRouter.scala:87:24] wire _out_T_46 = out_f_roready_4; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_4 = out_wivalid_4 & out_wimask_4; // @[RegisterRouter.scala:87:24] wire out_f_woready_4 = out_woready_4 & out_womask_4; // @[RegisterRouter.scala:87:24] wire [22:0] _out_T_44 = out_front_bits_data[62:40]; // @[RegisterRouter.scala:87:24] wire _out_T_47 = ~out_rimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_48 = ~out_wimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_49 = ~out_romask_4; // @[RegisterRouter.scala:87:24] wire _out_T_50 = ~out_womask_4; // @[RegisterRouter.scala:87:24] wire [40:0] out_prepend_3 = {1'h0, _out_prepend_T_3}; // @[RegisterRouter.scala:87:24] wire [62:0] _out_T_51 = {22'h0, out_prepend_3}; // @[RegisterRouter.scala:87:24] wire [62:0] _out_T_52 = _out_T_51; // @[RegisterRouter.scala:87:24] wire [62:0] _out_prepend_T_4 = _out_T_52; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_5 = out_frontMask[63]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_5 = out_frontMask[63]; // @[RegisterRouter.scala:87:24] wire out_rimask_5 = _out_rimask_T_5; // @[RegisterRouter.scala:87:24] wire out_wimask_5 = _out_wimask_T_5; // @[RegisterRouter.scala:87:24] wire _out_romask_T_5 = out_backMask[63]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_5 = out_backMask[63]; // @[RegisterRouter.scala:87:24] wire out_romask_5 = _out_romask_T_5; // @[RegisterRouter.scala:87:24] wire out_womask_5 = _out_womask_T_5; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_5 = out_rivalid_5 & out_rimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_54 = out_f_rivalid_5; // @[RegisterRouter.scala:87:24] wire out_f_roready_5 = out_roready_5 & out_romask_5; // @[RegisterRouter.scala:87:24] wire _out_T_55 = out_f_roready_5; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_5 = out_wivalid_5 & out_wimask_5; // @[RegisterRouter.scala:87:24] wire out_f_woready_5 = out_woready_5 & out_womask_5; // @[RegisterRouter.scala:87:24] wire _out_T_53 = out_front_bits_data[63]; // @[RegisterRouter.scala:87:24] wire _out_T_56 = ~out_rimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_57 = ~out_wimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_58 = ~out_romask_5; // @[RegisterRouter.scala:87:24] wire _out_T_59 = ~out_womask_5; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_4 = {~_rxq_io_deq_valid, _out_prepend_T_4}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_60 = out_prepend_4; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_61 = _out_T_60; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_1_0 = _out_T_61; // @[MuxLiteral.scala:49:48] wire _out_rimask_T_6 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_6 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_11 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_11 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire out_rimask_6 = _out_rimask_T_6; // @[RegisterRouter.scala:87:24] wire out_wimask_6 = _out_wimask_T_6; // @[RegisterRouter.scala:87:24] wire _out_romask_T_6 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_6 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_11 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_11 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire out_romask_6 = _out_romask_T_6; // @[RegisterRouter.scala:87:24] wire out_womask_6 = _out_womask_T_6; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_6 = out_rivalid_6 & out_rimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_63 = out_f_rivalid_6; // @[RegisterRouter.scala:87:24] wire out_f_roready_6 = out_roready_6 & out_romask_6; // @[RegisterRouter.scala:87:24] wire _out_T_64 = out_f_roready_6; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_6 = out_wivalid_6 & out_wimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_65 = out_f_wivalid_6; // @[RegisterRouter.scala:87:24] wire out_f_woready_6 = out_woready_6 & out_womask_6; // @[RegisterRouter.scala:87:24] wire _out_T_66 = out_f_woready_6; // @[RegisterRouter.scala:87:24] wire _out_T_62 = out_front_bits_data[0]; // @[RegisterRouter.scala:87:24] wire _out_T_117 = out_front_bits_data[0]; // @[RegisterRouter.scala:87:24] wire _out_T_67 = ~out_rimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_68 = ~out_wimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_69 = ~out_romask_6; // @[RegisterRouter.scala:87:24] wire _out_T_70 = ~out_womask_6; // @[RegisterRouter.scala:87:24] wire _out_T_72 = _out_T_71; // @[RegisterRouter.scala:87:24] wire _out_prepend_T_5 = _out_T_72; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_7 = out_frontMask[1]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_7 = out_frontMask[1]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_12 = out_frontMask[1]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_12 = out_frontMask[1]; // @[RegisterRouter.scala:87:24] wire out_rimask_7 = _out_rimask_T_7; // @[RegisterRouter.scala:87:24] wire out_wimask_7 = _out_wimask_T_7; // @[RegisterRouter.scala:87:24] wire _out_romask_T_7 = out_backMask[1]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_7 = out_backMask[1]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_12 = out_backMask[1]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_12 = out_backMask[1]; // @[RegisterRouter.scala:87:24] wire out_romask_7 = _out_romask_T_7; // @[RegisterRouter.scala:87:24] wire out_womask_7 = _out_womask_T_7; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_7 = out_rivalid_7 & out_rimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_74 = out_f_rivalid_7; // @[RegisterRouter.scala:87:24] wire out_f_roready_7 = out_roready_7 & out_romask_7; // @[RegisterRouter.scala:87:24] wire _out_T_75 = out_f_roready_7; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_7 = out_wivalid_7 & out_wimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_76 = out_f_wivalid_7; // @[RegisterRouter.scala:87:24] wire out_f_woready_7 = out_woready_7 & out_womask_7; // @[RegisterRouter.scala:87:24] wire _out_T_77 = out_f_woready_7; // @[RegisterRouter.scala:87:24] wire _out_T_73 = out_front_bits_data[1]; // @[RegisterRouter.scala:87:24] wire _out_T_128 = out_front_bits_data[1]; // @[RegisterRouter.scala:87:24] wire _out_T_78 = ~out_rimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_79 = ~out_wimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_80 = ~out_romask_7; // @[RegisterRouter.scala:87:24] wire _out_T_81 = ~out_womask_7; // @[RegisterRouter.scala:87:24] wire [1:0] out_prepend_5 = {nstop, _out_prepend_T_5}; // @[RegisterRouter.scala:87:24] wire [1:0] _out_T_82 = out_prepend_5; // @[RegisterRouter.scala:87:24] wire [1:0] _out_T_83 = _out_T_82; // @[RegisterRouter.scala:87:24] wire [3:0] _out_rimask_T_8 = out_frontMask[19:16]; // @[RegisterRouter.scala:87:24] wire [3:0] _out_wimask_T_8 = out_frontMask[19:16]; // @[RegisterRouter.scala:87:24] wire out_rimask_8 = \|_out_rimask_T_8; // @[RegisterRouter.scala:87:24] wire out_wimask_8 = &_out_wimask_T_8; // @[RegisterRouter.scala:87:24] wire [3:0] _out_romask_T_8 = out_backMask[19:16]; // @[RegisterRouter.scala:87:24] wire [3:0] _out_womask_T_8 = out_backMask[19:16]; // @[RegisterRouter.scala:87:24] wire out_romask_8 = \|_out_romask_T_8; // @[RegisterRouter.scala:87:24] wire out_womask_8 = &_out_womask_T_8; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_8 = out_rivalid_8 & out_rimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_85 = out_f_rivalid_8; // @[RegisterRouter.scala:87:24] wire out_f_roready_8 = out_roready_8 & out_romask_8; // @[RegisterRouter.scala:87:24] wire _out_T_86 = out_f_roready_8; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_8 = out_wivalid_8 & out_wimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_87 = out_f_wivalid_8; // @[RegisterRouter.scala:87:24] wire out_f_woready_8 = out_woready_8 & out_womask_8; // @[RegisterRouter.scala:87:24] wire _out_T_88 = out_f_woready_8; // @[RegisterRouter.scala:87:24] wire [3:0] _out_T_84 = out_front_bits_data[19:16]; // @[RegisterRouter.scala:87:24] wire _out_T_89 = ~out_rimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_90 = ~out_wimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_91 = ~out_romask_8; // @[RegisterRouter.scala:87:24] wire _out_T_92 = ~out_womask_8; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_6 = {14'h0, _out_T_83}; // @[RegisterRouter.scala:87:24] wire [19:0] out_prepend_6 = {txwm, _out_prepend_T_6}; // @[RegisterRouter.scala:87:24] wire [19:0] _out_T_93 = out_prepend_6; // @[RegisterRouter.scala:87:24] wire [19:0] _out_T_94 = _out_T_93; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_9 = out_frontMask[32]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_9 = out_frontMask[32]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_13 = out_frontMask[32]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_13 = out_frontMask[32]; // @[RegisterRouter.scala:87:24] wire out_rimask_9 = _out_rimask_T_9; // @[RegisterRouter.scala:87:24] wire out_wimask_9 = _out_wimask_T_9; // @[RegisterRouter.scala:87:24] wire _out_romask_T_9 = out_backMask[32]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_9 = out_backMask[32]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_13 = out_backMask[32]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_13 = out_backMask[32]; // @[RegisterRouter.scala:87:24] wire out_romask_9 = _out_romask_T_9; // @[RegisterRouter.scala:87:24] wire out_womask_9 = _out_womask_T_9; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_9 = out_rivalid_9 & out_rimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_96 = out_f_rivalid_9; // @[RegisterRouter.scala:87:24] wire out_f_roready_9 = out_roready_9 & out_romask_9; // @[RegisterRouter.scala:87:24] wire _out_T_97 = out_f_roready_9; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_9 = out_wivalid_9 & out_wimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_98 = out_f_wivalid_9; // @[RegisterRouter.scala:87:24] wire out_f_woready_9 = out_woready_9 & out_womask_9; // @[RegisterRouter.scala:87:24] wire _out_T_99 = out_f_woready_9; // @[RegisterRouter.scala:87:24] wire _out_T_95 = out_front_bits_data[32]; // @[RegisterRouter.scala:87:24] wire _out_T_139 = out_front_bits_data[32]; // @[RegisterRouter.scala:87:24] wire _out_T_100 = ~out_rimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_101 = ~out_wimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_102 = ~out_romask_9; // @[RegisterRouter.scala:87:24] wire _out_T_103 = ~out_womask_9; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_7 = {12'h0, _out_T_94}; // @[RegisterRouter.scala:87:24] wire [32:0] out_prepend_7 = {rxen, _out_prepend_T_7}; // @[RegisterRouter.scala:87:24] wire [32:0] _out_T_104 = out_prepend_7; // @[RegisterRouter.scala:87:24] wire [32:0] _out_T_105 = _out_T_104; // @[RegisterRouter.scala:87:24] wire [3:0] _out_rimask_T_10 = out_frontMask[51:48]; // @[RegisterRouter.scala:87:24] wire [3:0] _out_wimask_T_10 = out_frontMask[51:48]; // @[RegisterRouter.scala:87:24] wire out_rimask_10 = \|_out_rimask_T_10; // @[RegisterRouter.scala:87:24] wire out_wimask_10 = &_out_wimask_T_10; // @[RegisterRouter.scala:87:24] wire [3:0] _out_romask_T_10 = out_backMask[51:48]; // @[RegisterRouter.scala:87:24] wire [3:0] _out_womask_T_10 = out_backMask[51:48]; // @[RegisterRouter.scala:87:24] wire out_romask_10 = \|_out_romask_T_10; // @[RegisterRouter.scala:87:24] wire out_womask_10 = &_out_womask_T_10; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_10 = out_rivalid_10 & out_rimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_107 = out_f_rivalid_10; // @[RegisterRouter.scala:87:24] wire out_f_roready_10 = out_roready_10 & out_romask_10; // @[RegisterRouter.scala:87:24] wire _out_T_108 = out_f_roready_10; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_10 = out_wivalid_10 & out_wimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_109 = out_f_wivalid_10; // @[RegisterRouter.scala:87:24] wire out_f_woready_10 = out_woready_10 & out_womask_10; // @[RegisterRouter.scala:87:24] wire _out_T_110 = out_f_woready_10; // @[RegisterRouter.scala:87:24] wire [3:0] _out_T_106 = out_front_bits_data[51:48]; // @[RegisterRouter.scala:87:24] wire _out_T_111 = ~out_rimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_112 = ~out_wimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_113 = ~out_romask_10; // @[RegisterRouter.scala:87:24] wire _out_T_114 = ~out_womask_10; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_8 = {15'h0, _out_T_105}; // @[RegisterRouter.scala:87:24] wire [51:0] out_prepend_8 = {rxwm, _out_prepend_T_8}; // @[RegisterRouter.scala:87:24] wire [51:0] _out_T_115 = out_prepend_8; // @[RegisterRouter.scala:87:24] wire [51:0] _out_T_116 = _out_T_115; // @[RegisterRouter.scala:87:24] wire out_rimask_11 = _out_rimask_T_11; // @[RegisterRouter.scala:87:24] wire out_wimask_11 = _out_wimask_T_11; // @[RegisterRouter.scala:87:24] wire out_romask_11 = _out_romask_T_11; // @[RegisterRouter.scala:87:24] wire out_womask_11 = _out_womask_T_11; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_11 = out_rivalid_11 & out_rimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_118 = out_f_rivalid_11; // @[RegisterRouter.scala:87:24] wire out_f_roready_11 = out_roready_11 & out_romask_11; // @[RegisterRouter.scala:87:24] wire _out_T_119 = out_f_roready_11; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_11 = out_wivalid_11 & out_wimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_120 = out_f_wivalid_11; // @[RegisterRouter.scala:87:24] wire out_f_woready_11 = out_woready_11 & out_womask_11; // @[RegisterRouter.scala:87:24] wire _out_T_121 = out_f_woready_11; // @[RegisterRouter.scala:87:24] wire _out_T_122 = ~out_rimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_123 = ~out_wimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_124 = ~out_romask_11; // @[RegisterRouter.scala:87:24] wire _out_T_125 = ~out_womask_11; // @[RegisterRouter.scala:87:24] wire _out_T_127 = _out_T_126; // @[RegisterRouter.scala:87:24] wire _out_prepend_T_9 = _out_T_127; // @[RegisterRouter.scala:87:24] wire out_rimask_12 = _out_rimask_T_12; // @[RegisterRouter.scala:87:24] wire out_wimask_12 = _out_wimask_T_12; // @[RegisterRouter.scala:87:24] wire out_romask_12 = _out_romask_T_12; // @[RegisterRouter.scala:87:24] wire out_womask_12 = _out_womask_T_12; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_12 = out_rivalid_12 & out_rimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_129 = out_f_rivalid_12; // @[RegisterRouter.scala:87:24] wire out_f_roready_12 = out_roready_12 & out_romask_12; // @[RegisterRouter.scala:87:24] wire _out_T_130 = out_f_roready_12; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_12 = out_wivalid_12 & out_wimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_131 = out_f_wivalid_12; // @[RegisterRouter.scala:87:24] wire out_f_woready_12 = out_woready_12 & out_womask_12; // @[RegisterRouter.scala:87:24] wire _out_T_132 = out_f_woready_12; // @[RegisterRouter.scala:87:24] wire _out_T_133 = ~out_rimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_134 = ~out_wimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_135 = ~out_romask_12; // @[RegisterRouter.scala:87:24] wire _out_T_136 = ~out_womask_12; // @[RegisterRouter.scala:87:24] wire [1:0] out_prepend_9 = {ie_rxwm, _out_prepend_T_9}; // @[RegisterRouter.scala:87:24] wire [1:0] _out_T_137 = out_prepend_9; // @[RegisterRouter.scala:87:24] wire [1:0] _out_T_138 = _out_T_137; // @[RegisterRouter.scala:87:24] wire out_rimask_13 = _out_rimask_T_13; // @[RegisterRouter.scala:87:24] wire out_wimask_13 = _out_wimask_T_13; // @[RegisterRouter.scala:87:24] wire out_romask_13 = _out_romask_T_13; // @[RegisterRouter.scala:87:24] wire out_womask_13 = _out_womask_T_13; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_13 = out_rivalid_13 & out_rimask_13; // @[RegisterRouter.scala:87:24] wire _out_T_140 = out_f_rivalid_13; // @[RegisterRouter.scala:87:24] wire out_f_roready_13 = out_roready_13 & out_romask_13; // @[RegisterRouter.scala:87:24] wire _out_T_141 = out_f_roready_13; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_13 = out_wivalid_13 & out_wimask_13; // @[RegisterRouter.scala:87:24] wire out_f_woready_13 = out_woready_13 & out_womask_13; // @[RegisterRouter.scala:87:24] wire _out_T_142 = ~out_rimask_13; // @[RegisterRouter.scala:87:24] wire _out_T_143 = ~out_wimask_13; // @[RegisterRouter.scala:87:24] wire _out_T_144 = ~out_romask_13; // @[RegisterRouter.scala:87:24] wire _out_T_145 = ~out_womask_13; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_10 = {30'h0, _out_T_138}; // @[RegisterRouter.scala:87:24] wire [32:0] out_prepend_10 = {ip_txwm, _out_prepend_T_10}; // @[RegisterRouter.scala:87:24] wire [32:0] _out_T_146 = out_prepend_10; // @[RegisterRouter.scala:87:24] wire [32:0] _out_T_147 = _out_T_146; // @[RegisterRouter.scala:87:24] wire [32:0] _out_prepend_T_11 = _out_T_147; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_14 = out_frontMask[33]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_14 = out_frontMask[33]; // @[RegisterRouter.scala:87:24] wire out_rimask_14 = _out_rimask_T_14; // @[RegisterRouter.scala:87:24] wire out_wimask_14 = _out_wimask_T_14; // @[RegisterRouter.scala:87:24] wire _out_romask_T_14 = out_backMask[33]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_14 = out_backMask[33]; // @[RegisterRouter.scala:87:24] wire out_romask_14 = _out_romask_T_14; // @[RegisterRouter.scala:87:24] wire out_womask_14 = _out_womask_T_14; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_14 = out_rivalid_14 & out_rimask_14; // @[RegisterRouter.scala:87:24] wire _out_T_149 = out_f_rivalid_14; // @[RegisterRouter.scala:87:24] wire out_f_roready_14 = out_roready_14 & out_romask_14; // @[RegisterRouter.scala:87:24] wire _out_T_150 = out_f_roready_14; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_14 = out_wivalid_14 & out_wimask_14; // @[RegisterRouter.scala:87:24] wire out_f_woready_14 = out_woready_14 & out_womask_14; // @[RegisterRouter.scala:87:24] wire _out_T_148 = out_front_bits_data[33]; // @[RegisterRouter.scala:87:24] wire _out_T_151 = ~out_rimask_14; // @[RegisterRouter.scala:87:24] wire _out_T_152 = ~out_wimask_14; // @[RegisterRouter.scala:87:24] wire _out_T_153 = ~out_romask_14; // @[RegisterRouter.scala:87:24] wire _out_T_154 = ~out_womask_14; // @[RegisterRouter.scala:87:24] wire [33:0] out_prepend_11 = {ip_rxwm, _out_prepend_T_11}; // @[RegisterRouter.scala:87:24] wire [33:0] _out_T_155 = out_prepend_11; // @[RegisterRouter.scala:87:24] wire [33:0] _out_T_156 = _out_T_155; // @[RegisterRouter.scala:87:24] wire [15:0] _out_rimask_T_15 = out_frontMask[15:0]; // @[RegisterRouter.scala:87:24] wire [15:0] _out_wimask_T_15 = out_frontMask[15:0]; // @[RegisterRouter.scala:87:24] wire out_rimask_15 = \|_out_rimask_T_15; // @[RegisterRouter.scala:87:24] wire out_wimask_15 = &_out_wimask_T_15; // @[RegisterRouter.scala:87:24] wire [15:0] _out_romask_T_15 = out_backMask[15:0]; // @[RegisterRouter.scala:87:24] wire [15:0] _out_womask_T_15 = out_backMask[15:0]; // @[RegisterRouter.scala:87:24] wire out_romask_15 = \|_out_romask_T_15; // @[RegisterRouter.scala:87:24] wire out_womask_15 = &_out_womask_T_15; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_15 = out_rivalid_15 & out_rimask_15; // @[RegisterRouter.scala:87:24] wire _out_T_158 = out_f_rivalid_15; // @[RegisterRouter.scala:87:24] wire out_f_roready_15 = out_roready_15 & out_romask_15; // @[RegisterRouter.scala:87:24] wire _out_T_159 = out_f_roready_15; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_15 = out_wivalid_15 & out_wimask_15; // @[RegisterRouter.scala:87:24] wire _out_T_160 = out_f_wivalid_15; // @[RegisterRouter.scala:87:24] wire out_f_woready_15 = out_woready_15 & out_womask_15; // @[RegisterRouter.scala:87:24] wire _out_T_161 = out_f_woready_15; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_157 = out_front_bits_data[15:0]; // @[RegisterRouter.scala:87:24] wire _out_T_162 = ~out_rimask_15; // @[RegisterRouter.scala:87:24] wire _out_T_163 = ~out_wimask_15; // @[RegisterRouter.scala:87:24] wire _out_T_164 = ~out_romask_15; // @[RegisterRouter.scala:87:24] wire _out_T_165 = ~out_womask_15; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_167 = _out_T_166; // @[RegisterRouter.scala:87:24] wire _out_iindex_T = out_front_bits_index[0]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T = out_front_bits_index[0]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_1 = out_front_bits_index[1]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_1 = out_front_bits_index[1]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_2 = out_front_bits_index[2]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_2 = out_front_bits_index[2]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_3 = out_front_bits_index[3]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_3 = out_front_bits_index[3]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_4 = out_front_bits_index[4]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_4 = out_front_bits_index[4]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_5 = out_front_bits_index[5]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_5 = out_front_bits_index[5]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_6 = out_front_bits_index[6]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_6 = out_front_bits_index[6]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_7 = out_front_bits_index[7]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_7 = out_front_bits_index[7]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_8 = out_front_bits_index[8]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_8 = out_front_bits_index[8]; // @[RegisterRouter.scala:87:24] wire [1:0] out_iindex = {_out_iindex_T_1, _out_iindex_T}; // @[RegisterRouter.scala:87:24] wire [1:0] out_oindex = {_out_oindex_T_1, _out_oindex_T}; // @[RegisterRouter.scala:87:24] wire [3:0] _out_frontSel_T = 4'h1 << out_iindex; // @[OneHot.scala:58:35] wire out_frontSel_0 = _out_frontSel_T[0]; // @[OneHot.scala:58:35] wire out_frontSel_1 = _out_frontSel_T[1]; // @[OneHot.scala:58:35] wire out_frontSel_2 = _out_frontSel_T[2]; // @[OneHot.scala:58:35] wire out_frontSel_3 = _out_frontSel_T[3]; // @[OneHot.scala:58:35] wire [3:0] _out_backSel_T = 4'h1 << out_oindex; // @[OneHot.scala:58:35] wire out_backSel_0 = _out_backSel_T[0]; // @[OneHot.scala:58:35] wire out_backSel_1 = _out_backSel_T[1]; // @[OneHot.scala:58:35] wire out_backSel_2 = _out_backSel_T[2]; // @[OneHot.scala:58:35] wire out_backSel_3 = _out_backSel_T[3]; // @[OneHot.scala:58:35] wire _GEN_2 = in_valid & out_front_ready; // @[RegisterRouter.scala:73:18, :87:24] wire _out_rifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T = _GEN_2; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T = _GEN_2; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1 = _out_rifireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_2 = _out_rifireMux_T_1 & out_frontSel_0; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_3 = _out_rifireMux_T_2 & _out_T; // @[RegisterRouter.scala:87:24] assign out_rivalid_0 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_1 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_2 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_3 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_4 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_5 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_4 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_6 = _out_rifireMux_T_1 & out_frontSel_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_7 = _out_rifireMux_T_6 & _out_T_2; // @[RegisterRouter.scala:87:24] assign out_rivalid_6 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_7 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_8 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_9 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_10 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_8 = ~_out_T_2; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_10 = _out_rifireMux_T_1 & out_frontSel_2; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_11 = _out_rifireMux_T_10 & _out_T_4; // @[RegisterRouter.scala:87:24] assign out_rivalid_11 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_12 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_13 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_14 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_12 = ~_out_T_4; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_14 = _out_rifireMux_T_1 & out_frontSel_3; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_15 = _out_rifireMux_T_14 & _out_T_6; // @[RegisterRouter.scala:87:24] assign out_rivalid_15 = _out_rifireMux_T_15; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_16 = ~_out_T_6; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_2 = _out_wifireMux_T & _out_wifireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_3 = _out_wifireMux_T_2 & out_frontSel_0; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_4 = _out_wifireMux_T_3 & _out_T; // @[RegisterRouter.scala:87:24] assign out_wivalid_0 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_1 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_2 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_3 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_4 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_5 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_5 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_7 = _out_wifireMux_T_2 & out_frontSel_1; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_8 = _out_wifireMux_T_7 & _out_T_2; // @[RegisterRouter.scala:87:24] assign out_wivalid_6 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_7 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_8 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_9 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_10 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_9 = ~_out_T_2; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_11 = _out_wifireMux_T_2 & out_frontSel_2; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_12 = _out_wifireMux_T_11 & _out_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_11 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_12 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_13 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_14 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_13 = ~_out_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_15 = _out_wifireMux_T_2 & out_frontSel_3; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_16 = _out_wifireMux_T_15 & _out_T_6; // @[RegisterRouter.scala:87:24] assign out_wivalid_15 = _out_wifireMux_T_16; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_17 = ~_out_T_6; // @[RegisterRouter.scala:87:24] wire _GEN_3 = out_front_valid & out_ready; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T = _GEN_3; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T = _GEN_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1 = _out_rofireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_2 = _out_rofireMux_T_1 & out_backSel_0; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_3 = _out_rofireMux_T_2 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_roready_0 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_1 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_2 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_3 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_4 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_5 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_4 = ~_out_T_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_6 = _out_rofireMux_T_1 & out_backSel_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_7 = _out_rofireMux_T_6 & _out_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_6 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_7 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_8 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_9 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_10 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_8 = ~_out_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_10 = _out_rofireMux_T_1 & out_backSel_2; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_11 = _out_rofireMux_T_10 & _out_T_5; // @[RegisterRouter.scala:87:24] assign out_roready_11 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_12 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_13 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_14 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_12 = ~_out_T_5; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_14 = _out_rofireMux_T_1 & out_backSel_3; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_15 = _out_rofireMux_T_14 & _out_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_15 = _out_rofireMux_T_15; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_16 = ~_out_T_7; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_2 = _out_wofireMux_T & _out_wofireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_3 = _out_wofireMux_T_2 & out_backSel_0; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_4 = _out_wofireMux_T_3 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_woready_0 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_1 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_2 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_3 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_4 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_5 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_5 = ~_out_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_7 = _out_wofireMux_T_2 & out_backSel_1; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_8 = _out_wofireMux_T_7 & _out_T_3; // @[RegisterRouter.scala:87:24] assign out_woready_6 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_7 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_8 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_9 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_10 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_9 = ~_out_T_3; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_11 = _out_wofireMux_T_2 & out_backSel_2; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_12 = _out_wofireMux_T_11 & _out_T_5; // @[RegisterRouter.scala:87:24] assign out_woready_11 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_12 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_13 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_14 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_13 = ~_out_T_5; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_15 = _out_wofireMux_T_2 & out_backSel_3; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_16 = _out_wofireMux_T_15 & _out_T_7; // @[RegisterRouter.scala:87:24] assign out_woready_15 = _out_wofireMux_T_16; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_17 = ~_out_T_7; // @[RegisterRouter.scala:87:24] assign in_ready = _out_in_ready_T; // @[RegisterRouter.scala:73:18, :87:24] assign out_front_valid = _out_front_valid_T; // @[RegisterRouter.scala:87:24] assign out_front_ready = _out_front_ready_T; // @[RegisterRouter.scala:87:24] assign out_valid = _out_out_valid_T; // @[RegisterRouter.scala:87:24] wire [3:0] _GEN_4 = {{_out_out_bits_data_WIRE_3}, {_out_out_bits_data_WIRE_2}, {_out_out_bits_data_WIRE_1}, {_out_out_bits_data_WIRE_0}}; // @[MuxLiteral.scala:49:{10,48}] wire _out_out_bits_data_T_1 = _GEN_4[out_oindex]; // @[MuxLiteral.scala:49:10] wire [63:0] _out_out_bits_data_WIRE_1_1 = {12'h0, _out_T_116}; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_1_2 = {30'h0, _out_T_156}; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_1_3 = {48'h0, _out_T_167}; // @[MuxLiteral.scala:49:48] wire [3:0][63:0] _GEN_5 = {{_out_out_bits_data_WIRE_1_3}, {_out_out_bits_data_WIRE_1_2}, {_out_out_bits_data_WIRE_1_1}, {_out_out_bits_data_WIRE_1_0}}; // @[MuxLiteral.scala:49:{10,48}] wire [63:0] _out_out_bits_data_T_3 = _GEN_5[out_oindex]; // @[MuxLiteral.scala:49:10] assign _out_out_bits_data_T_4 = _out_out_bits_data_T_1 ? _out_out_bits_data_T_3 : 64'h0; // @[MuxLiteral.scala:49:10] assign out_bits_data = _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24] assign controlNodeIn_d_bits_size = controlNodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign controlNodeIn_d_bits_source = controlNodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign controlNodeIn_d_bits_opcode = {2'h0, _controlNodeIn_d_bits_opcode_T}; // @[RegisterRouter.scala:105:{19,25}] always @(posedge clock) begin // @[UART.scala:127:25] if (reset) begin // @[UART.scala:127:25] div <= 16'h10F4; // @[UART.scala:135:20] txen <= 1'h0; // @[UART.scala:141:21] rxen <= 1'h0; // @[UART.scala:142:21] txwm <= 4'h0; // @[UART.scala:149:21] rxwm <= 4'h0; // @[UART.scala:150:21] nstop <= 1'h0; // @[UART.scala:151:22] ie_rxwm <= 1'h0; // @[UART.scala:186:19] ie_txwm <= 1'h0; // @[UART.scala:186:19] end else begin // @[UART.scala:127:25] if (out_f_woready_15) // @[RegisterRouter.scala:87:24] div <= _out_T_157; // @[RegisterRouter.scala:87:24] if (out_f_woready_6) // @[RegisterRouter.scala:87:24] txen <= _out_T_62; // @[RegisterRouter.scala:87:24] if (out_f_woready_9) // @[RegisterRouter.scala:87:24] rxen <= _out_T_95; // @[RegisterRouter.scala:87:24] if (out_f_woready_8) // @[RegisterRouter.scala:87:24] txwm <= _out_T_84; // @[RegisterRouter.scala:87:24] if (out_f_woready_10) // @[RegisterRouter.scala:87:24] rxwm <= _out_T_106; // @[RegisterRouter.scala:87:24] if (out_f_woready_7) // @[RegisterRouter.scala:87:24] nstop <= _out_T_73; // @[RegisterRouter.scala:87:24] if (out_f_woready_12) // @[RegisterRouter.scala:87:24] ie_rxwm <= _out_T_128; // @[RegisterRouter.scala:87:24] if (out_f_woready_11) // @[RegisterRouter.scala:87:24] ie_txwm <= _out_T_117; // @[RegisterRouter.scala:87:24] end always @(posedge) IntSyncCrossingSource_n1x1_5 intsource ( // @[Crossing.scala:29:31] .clock (clock), .reset (reset), .auto_in_0 (intnodeOut_0), // @[MixedNode.scala:542:17] .auto_out_sync_0 (intXingIn_sync_0) ); // @[Crossing.scala:29:31] TLMonitor_62 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (controlNodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (controlNodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (controlNodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (controlNodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (controlNodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (controlNodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (controlNodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (controlNodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (controlNodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (controlNodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (controlNodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (controlNodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (controlNodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_size (controlNodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (controlNodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_data (controlNodeIn_d_bits_data) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] UARTTx txm ( // @[UART.scala:129:19] .clock (clock), .reset (reset), .io_en (txen), // @[UART.scala:141:21] .io_in_ready (_txm_io_in_ready), .io_in_valid (_txq_io_deq_valid), // @[UART.scala:130:19] .io_in_bits (_txq_io_deq_bits), // @[UART.scala:130:19] .io_out (ioNodeOut_txd), .io_div (div), // @[UART.scala:135:20] .io_nstop (nstop), // @[UART.scala:151:22] .io_tx_busy (_txm_io_tx_busy) ); // @[UART.scala:129:19] Queue8_UInt8 txq ( // @[UART.scala:130:19] .clock (clock), .reset (reset), .io_enq_ready (_txq_io_enq_ready), .io_enq_valid (_out_txq_io_enq_valid_T_1), // @[RegMapFIFO.scala:18:30] .io_enq_bits (_out_T_8), // @[RegisterRouter.scala:87:24] .io_deq_ready (_txm_io_in_ready), // @[UART.scala:129:19] .io_deq_valid (_txq_io_deq_valid), .io_deq_bits (_txq_io_deq_bits), .io_count (_txq_io_count) ); // @[UART.scala:130:19] UARTRx rxm ( // @[UART.scala:132:19] .clock (clock), .reset (reset), .io_en (rxen), // @[UART.scala:142:21] .io_in (ioNodeOut_rxd), // @[MixedNode.scala:542:17] .io_out_valid (_rxm_io_out_valid), .io_out_bits (_rxm_io_out_bits), .io_div (div) // @[UART.scala:135:20] ); // @[UART.scala:132:19] Queue8_UInt8_1 rxq ( // @[UART.scala:133:19] .clock (clock), .reset (reset), .io_enq_valid (_rxm_io_out_valid), // @[UART.scala:132:19] .io_enq_bits (_rxm_io_out_bits), // @[UART.scala:132:19] .io_deq_ready (out_f_roready_3), // @[RegisterRouter.scala:87:24] .io_deq_valid (_rxq_io_deq_valid), .io_deq_bits (_rxq_io_deq_bits), .io_count (_rxq_io_count) ); // @[UART.scala:133:19] assign auto_int_xing_out_sync_0 = auto_int_xing_out_sync_0_0; // @[UART.scala:127:25] assign auto_control_xing_in_a_ready = auto_control_xing_in_a_ready_0; // @[UART.scala:127:25] assign auto_control_xing_in_d_valid = auto_control_xing_in_d_valid_0; // @[UART.scala:127:25] assign auto_control_xing_in_d_bits_opcode = auto_control_xing_in_d_bits_opcode_0; // @[UART.scala:127:25] assign auto_control_xing_in_d_bits_size = auto_control_xing_in_d_bits_size_0; // @[UART.scala:127:25] assign auto_control_xing_in_d_bits_source = auto_control_xing_in_d_bits_source_0; // @[UART.scala:127:25] assign auto_control_xing_in_d_bits_data = auto_control_xing_in_d_bits_data_0; // @[UART.scala:127:25] assign auto_io_out_txd = auto_io_out_txd_0; // @[UART.scala:127:25] endmodule
Generate the Verilog code corresponding to this FIRRTL code module IssueSlot_7 : input clock : Clock input reset : Reset output io : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, request_hp : UInt<1>, flip grant : UInt<1>, flip brupdate : { b1 : { resolve_mask : UInt<8>, mispredict_mask : UInt<8>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, flip kill : UInt<1>, flip clear : UInt<1>, flip ldspec_miss : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { pdst : UInt<6>, poisoned : UInt<1>}}[2], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<4>}, flip spec_ld_wakeup : { valid : UInt<1>, bits : UInt<6>}[1], flip in_uop : { valid : UInt<1>, bits : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}}, out_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, debug : { p1 : UInt<1>, p2 : UInt<1>, p3 : UInt<1>, ppred : UInt<1>, state : UInt<2>}} wire next_state : UInt wire next_uopc : UInt wire next_lrs1_rtype : UInt wire next_lrs2_rtype : UInt regreset state : UInt<2>, clock, reset, UInt<2>(0h0) regreset p1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset p2 : UInt<1>, clock, reset, UInt<1>(0h0) regreset p3 : UInt<1>, clock, reset, UInt<1>(0h0) regreset ppred : UInt<1>, clock, reset, UInt<1>(0h0) regreset p1_poisoned : UInt<1>, clock, reset, UInt<1>(0h0) regreset p2_poisoned : UInt<1>, clock, reset, UInt<1>(0h0) connect p1_poisoned, UInt<1>(0h0) connect p2_poisoned, UInt<1>(0h0) node next_p1_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned) node next_p2_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned) wire slot_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>} invalidate slot_uop_uop.debug_tsrc invalidate slot_uop_uop.debug_fsrc invalidate slot_uop_uop.bp_xcpt_if invalidate slot_uop_uop.bp_debug_if invalidate slot_uop_uop.xcpt_ma_if invalidate slot_uop_uop.xcpt_ae_if invalidate slot_uop_uop.xcpt_pf_if invalidate slot_uop_uop.fp_single invalidate slot_uop_uop.fp_val invalidate slot_uop_uop.frs3_en invalidate slot_uop_uop.lrs2_rtype invalidate slot_uop_uop.lrs1_rtype invalidate slot_uop_uop.dst_rtype invalidate slot_uop_uop.ldst_val invalidate slot_uop_uop.lrs3 invalidate slot_uop_uop.lrs2 invalidate slot_uop_uop.lrs1 invalidate slot_uop_uop.ldst invalidate slot_uop_uop.ldst_is_rs1 invalidate slot_uop_uop.flush_on_commit invalidate slot_uop_uop.is_unique invalidate slot_uop_uop.is_sys_pc2epc invalidate slot_uop_uop.uses_stq invalidate slot_uop_uop.uses_ldq invalidate slot_uop_uop.is_amo invalidate slot_uop_uop.is_fencei invalidate slot_uop_uop.is_fence invalidate slot_uop_uop.mem_signed invalidate slot_uop_uop.mem_size invalidate slot_uop_uop.mem_cmd invalidate slot_uop_uop.bypassable invalidate slot_uop_uop.exc_cause invalidate slot_uop_uop.exception invalidate slot_uop_uop.stale_pdst invalidate slot_uop_uop.ppred_busy invalidate slot_uop_uop.prs3_busy invalidate slot_uop_uop.prs2_busy invalidate slot_uop_uop.prs1_busy invalidate slot_uop_uop.ppred invalidate slot_uop_uop.prs3 invalidate slot_uop_uop.prs2 invalidate slot_uop_uop.prs1 invalidate slot_uop_uop.pdst invalidate slot_uop_uop.rxq_idx invalidate slot_uop_uop.stq_idx invalidate slot_uop_uop.ldq_idx invalidate slot_uop_uop.rob_idx invalidate slot_uop_uop.csr_addr invalidate slot_uop_uop.imm_packed invalidate slot_uop_uop.taken invalidate slot_uop_uop.pc_lob invalidate slot_uop_uop.edge_inst invalidate slot_uop_uop.ftq_idx invalidate slot_uop_uop.br_tag invalidate slot_uop_uop.br_mask invalidate slot_uop_uop.is_sfb invalidate slot_uop_uop.is_jal invalidate slot_uop_uop.is_jalr invalidate slot_uop_uop.is_br invalidate slot_uop_uop.iw_p2_poisoned invalidate slot_uop_uop.iw_p1_poisoned invalidate slot_uop_uop.iw_state invalidate slot_uop_uop.ctrl.is_std invalidate slot_uop_uop.ctrl.is_sta invalidate slot_uop_uop.ctrl.is_load invalidate slot_uop_uop.ctrl.csr_cmd invalidate slot_uop_uop.ctrl.fcn_dw invalidate slot_uop_uop.ctrl.op_fcn invalidate slot_uop_uop.ctrl.imm_sel invalidate slot_uop_uop.ctrl.op2_sel invalidate slot_uop_uop.ctrl.op1_sel invalidate slot_uop_uop.ctrl.br_type invalidate slot_uop_uop.fu_code invalidate slot_uop_uop.iq_type invalidate slot_uop_uop.debug_pc invalidate slot_uop_uop.is_rvc invalidate slot_uop_uop.debug_inst invalidate slot_uop_uop.inst invalidate slot_uop_uop.uopc connect slot_uop_uop.uopc, UInt<7>(0h0) connect slot_uop_uop.bypassable, UInt<1>(0h0) connect slot_uop_uop.fp_val, UInt<1>(0h0) connect slot_uop_uop.uses_stq, UInt<1>(0h0) connect slot_uop_uop.uses_ldq, UInt<1>(0h0) connect slot_uop_uop.pdst, UInt<1>(0h0) connect slot_uop_uop.dst_rtype, UInt<2>(0h2) wire slot_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>} invalidate slot_uop_cs.is_std invalidate slot_uop_cs.is_sta invalidate slot_uop_cs.is_load invalidate slot_uop_cs.csr_cmd invalidate slot_uop_cs.fcn_dw invalidate slot_uop_cs.op_fcn invalidate slot_uop_cs.imm_sel invalidate slot_uop_cs.op2_sel invalidate slot_uop_cs.op1_sel invalidate slot_uop_cs.br_type connect slot_uop_cs.br_type, UInt<4>(0h0) connect slot_uop_cs.csr_cmd, UInt<3>(0h0) connect slot_uop_cs.is_load, UInt<1>(0h0) connect slot_uop_cs.is_sta, UInt<1>(0h0) connect slot_uop_cs.is_std, UInt<1>(0h0) connect slot_uop_uop.ctrl, slot_uop_cs regreset slot_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, clock, reset, slot_uop_uop node next_uop = mux(io.in_uop.valid, io.in_uop.bits, slot_uop) when io.kill : connect state, UInt<2>(0h0) else : when io.in_uop.valid : connect state, io.in_uop.bits.iw_state else : when io.clear : connect state, UInt<2>(0h0) else : connect state, next_state connect next_state, state connect next_uopc, slot_uop.uopc connect next_lrs1_rtype, slot_uop.lrs1_rtype connect next_lrs2_rtype, slot_uop.lrs2_rtype when io.kill : connect next_state, UInt<2>(0h0) else : node _T = eq(state, UInt<2>(0h1)) node _T_1 = and(io.grant, _T) node _T_2 = eq(state, UInt<2>(0h2)) node _T_3 = and(io.grant, _T_2) node _T_4 = and(_T_3, p1) node _T_5 = and(_T_4, p2) node _T_6 = and(_T_5, ppred) node _T_7 = or(_T_1, _T_6) when _T_7 : node _T_8 = or(p1_poisoned, p2_poisoned) node _T_9 = and(io.ldspec_miss, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) when _T_10 : connect next_state, UInt<2>(0h0) else : node _T_11 = eq(state, UInt<2>(0h2)) node _T_12 = and(io.grant, _T_11) when _T_12 : node _T_13 = or(p1_poisoned, p2_poisoned) node _T_14 = and(io.ldspec_miss, _T_13) node _T_15 = eq(_T_14, UInt<1>(0h0)) when _T_15 : connect next_state, UInt<2>(0h1) when p1 : connect slot_uop.uopc, UInt<7>(0h3) connect next_uopc, UInt<7>(0h3) connect slot_uop.lrs1_rtype, UInt<2>(0h2) connect next_lrs1_rtype, UInt<2>(0h2) else : connect slot_uop.lrs2_rtype, UInt<2>(0h2) connect next_lrs2_rtype, UInt<2>(0h2) when io.in_uop.valid : connect slot_uop, io.in_uop.bits node _T_16 = eq(state, UInt<2>(0h0)) node _T_17 = or(_T_16, io.clear) node _T_18 = or(_T_17, io.kill) node _T_19 = asUInt(reset) node _T_20 = eq(_T_19, UInt<1>(0h0)) when _T_20 : node _T_21 = eq(_T_18, UInt<1>(0h0)) when _T_21 : printf(clock, UInt<1>(0h1), "Assertion failed: trying to overwrite a valid issue slot.\n at issue-slot.scala:156 assert (is_invalid \|\| io.clear \|\| io.kill, \"trying to overwrite a valid issue slot.\")\n") : printf assert(clock, _T_18, UInt<1>(0h1), "") : assert wire next_p1 : UInt<1> connect next_p1, p1 wire next_p2 : UInt<1> connect next_p2, p2 wire next_p3 : UInt<1> connect next_p3, p3 wire next_ppred : UInt<1> connect next_ppred, ppred when io.in_uop.valid : node _p1_T = eq(io.in_uop.bits.prs1_busy, UInt<1>(0h0)) connect p1, _p1_T node _p2_T = eq(io.in_uop.bits.prs2_busy, UInt<1>(0h0)) connect p2, _p2_T node _p3_T = eq(io.in_uop.bits.prs3_busy, UInt<1>(0h0)) connect p3, _p3_T node _ppred_T = eq(io.in_uop.bits.ppred_busy, UInt<1>(0h0)) connect ppred, _ppred_T node _T_22 = and(io.ldspec_miss, next_p1_poisoned) when _T_22 : node _T_23 = neq(next_uop.prs1, UInt<1>(0h0)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs1=x0!\n at issue-slot.scala:176 assert(next_uop.prs1 =/= 0.U, \"Poison bit can't be set for prs1=x0!\")\n") : printf_1 assert(clock, _T_23, UInt<1>(0h1), "") : assert_1 connect p1, UInt<1>(0h0) node _T_27 = and(io.ldspec_miss, next_p2_poisoned) when _T_27 : node _T_28 = neq(next_uop.prs2, UInt<1>(0h0)) node _T_29 = asUInt(reset) node _T_30 = eq(_T_29, UInt<1>(0h0)) when _T_30 : node _T_31 = eq(_T_28, UInt<1>(0h0)) when _T_31 : printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs2=x0!\n at issue-slot.scala:180 assert(next_uop.prs2 =/= 0.U, \"Poison bit can't be set for prs2=x0!\")\n") : printf_2 assert(clock, _T_28, UInt<1>(0h1), "") : assert_2 connect p2, UInt<1>(0h0) node _T_32 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs1) node _T_33 = and(io.wakeup_ports[0].valid, _T_32) when _T_33 : connect p1, UInt<1>(0h1) node _T_34 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs2) node _T_35 = and(io.wakeup_ports[0].valid, _T_34) when _T_35 : connect p2, UInt<1>(0h1) node _T_36 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs3) node _T_37 = and(io.wakeup_ports[0].valid, _T_36) when _T_37 : connect p3, UInt<1>(0h1) node _T_38 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs1) node _T_39 = and(io.wakeup_ports[1].valid, _T_38) when _T_39 : connect p1, UInt<1>(0h1) node _T_40 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs2) node _T_41 = and(io.wakeup_ports[1].valid, _T_40) when _T_41 : connect p2, UInt<1>(0h1) node _T_42 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs3) node _T_43 = and(io.wakeup_ports[1].valid, _T_42) when _T_43 : connect p3, UInt<1>(0h1) node _T_44 = eq(io.pred_wakeup_port.bits, next_uop.ppred) node _T_45 = and(io.pred_wakeup_port.valid, _T_44) when _T_45 : connect ppred, UInt<1>(0h1) node _T_46 = eq(io.spec_ld_wakeup[0].bits, UInt<1>(0h0)) node _T_47 = and(io.spec_ld_wakeup[0].valid, _T_46) node _T_48 = eq(_T_47, UInt<1>(0h0)) node _T_49 = asUInt(reset) node _T_50 = eq(_T_49, UInt<1>(0h0)) when _T_50 : node _T_51 = eq(_T_48, UInt<1>(0h0)) when _T_51 : printf(clock, UInt<1>(0h1), "Assertion failed: Loads to x0 should never speculatively wakeup other instructions\n at issue-slot.scala:203 assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U),\n") : printf_3 assert(clock, _T_48, UInt<1>(0h1), "") : assert_3 node _T_52 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs1) node _T_53 = and(io.spec_ld_wakeup[0].valid, _T_52) node _T_54 = eq(next_uop.lrs1_rtype, UInt<2>(0h0)) node _T_55 = and(_T_53, _T_54) when _T_55 : connect p1, UInt<1>(0h1) connect p1_poisoned, UInt<1>(0h1) node _T_56 = eq(next_p1_poisoned, UInt<1>(0h0)) node _T_57 = asUInt(reset) node _T_58 = eq(_T_57, UInt<1>(0h0)) when _T_58 : node _T_59 = eq(_T_56, UInt<1>(0h0)) when _T_59 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:214 assert (!next_p1_poisoned)\n") : printf_4 assert(clock, _T_56, UInt<1>(0h1), "") : assert_4 node _T_60 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs2) node _T_61 = and(io.spec_ld_wakeup[0].valid, _T_60) node _T_62 = eq(next_uop.lrs2_rtype, UInt<2>(0h0)) node _T_63 = and(_T_61, _T_62) when _T_63 : connect p2, UInt<1>(0h1) connect p2_poisoned, UInt<1>(0h1) node _T_64 = eq(next_p2_poisoned, UInt<1>(0h0)) node _T_65 = asUInt(reset) node _T_66 = eq(_T_65, UInt<1>(0h0)) when _T_66 : node _T_67 = eq(_T_64, UInt<1>(0h0)) when _T_67 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:221 assert (!next_p2_poisoned)\n") : printf_5 assert(clock, _T_64, UInt<1>(0h1), "") : assert_5 node _next_br_mask_T = not(io.brupdate.b1.resolve_mask) node next_br_mask = and(slot_uop.br_mask, _next_br_mask_T) node _T_68 = and(io.brupdate.b1.mispredict_mask, slot_uop.br_mask) node _T_69 = neq(_T_68, UInt<1>(0h0)) when _T_69 : connect next_state, UInt<2>(0h0) node _T_70 = eq(io.in_uop.valid, UInt<1>(0h0)) when _T_70 : connect slot_uop.br_mask, next_br_mask node _io_request_T = neq(state, UInt<2>(0h0)) node _io_request_T_1 = and(_io_request_T, p1) node _io_request_T_2 = and(_io_request_T_1, p2) node _io_request_T_3 = and(_io_request_T_2, p3) node _io_request_T_4 = and(_io_request_T_3, ppred) node _io_request_T_5 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_6 = and(_io_request_T_4, _io_request_T_5) connect io.request, _io_request_T_6 node _high_priority_T = or(slot_uop.is_br, slot_uop.is_jal) node high_priority = or(_high_priority_T, slot_uop.is_jalr) node _io_request_hp_T = and(io.request, high_priority) connect io.request_hp, _io_request_hp_T node _T_71 = eq(state, UInt<2>(0h1)) when _T_71 : node _io_request_T_7 = and(p1, p2) node _io_request_T_8 = and(_io_request_T_7, p3) node _io_request_T_9 = and(_io_request_T_8, ppred) node _io_request_T_10 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_11 = and(_io_request_T_9, _io_request_T_10) connect io.request, _io_request_T_11 else : node _T_72 = eq(state, UInt<2>(0h2)) when _T_72 : node _io_request_T_12 = or(p1, p2) node _io_request_T_13 = and(_io_request_T_12, ppred) node _io_request_T_14 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_15 = and(_io_request_T_13, _io_request_T_14) connect io.request, _io_request_T_15 else : connect io.request, UInt<1>(0h0) node _io_valid_T = neq(state, UInt<2>(0h0)) connect io.valid, _io_valid_T connect io.uop, slot_uop connect io.uop.iw_p1_poisoned, p1_poisoned connect io.uop.iw_p2_poisoned, p2_poisoned node _may_vacate_T = eq(state, UInt<2>(0h1)) node _may_vacate_T_1 = eq(state, UInt<2>(0h2)) node _may_vacate_T_2 = and(_may_vacate_T_1, p1) node _may_vacate_T_3 = and(_may_vacate_T_2, p2) node _may_vacate_T_4 = and(_may_vacate_T_3, ppred) node _may_vacate_T_5 = or(_may_vacate_T, _may_vacate_T_4) node may_vacate = and(io.grant, _may_vacate_T_5) node _squash_grant_T = or(p1_poisoned, p2_poisoned) node squash_grant = and(io.ldspec_miss, _squash_grant_T) node _io_will_be_valid_T = neq(state, UInt<2>(0h0)) node _io_will_be_valid_T_1 = eq(squash_grant, UInt<1>(0h0)) node _io_will_be_valid_T_2 = and(may_vacate, _io_will_be_valid_T_1) node _io_will_be_valid_T_3 = eq(_io_will_be_valid_T_2, UInt<1>(0h0)) node _io_will_be_valid_T_4 = and(_io_will_be_valid_T, _io_will_be_valid_T_3) connect io.will_be_valid, _io_will_be_valid_T_4 connect io.out_uop, slot_uop connect io.out_uop.iw_state, next_state connect io.out_uop.uopc, next_uopc connect io.out_uop.lrs1_rtype, next_lrs1_rtype connect io.out_uop.lrs2_rtype, next_lrs2_rtype connect io.out_uop.br_mask, next_br_mask node _io_out_uop_prs1_busy_T = eq(p1, UInt<1>(0h0)) connect io.out_uop.prs1_busy, _io_out_uop_prs1_busy_T node _io_out_uop_prs2_busy_T = eq(p2, UInt<1>(0h0)) connect io.out_uop.prs2_busy, _io_out_uop_prs2_busy_T node _io_out_uop_prs3_busy_T = eq(p3, UInt<1>(0h0)) connect io.out_uop.prs3_busy, _io_out_uop_prs3_busy_T node _io_out_uop_ppred_busy_T = eq(ppred, UInt<1>(0h0)) connect io.out_uop.ppred_busy, _io_out_uop_ppred_busy_T connect io.out_uop.iw_p1_poisoned, p1_poisoned connect io.out_uop.iw_p2_poisoned, p2_poisoned node _T_73 = eq(state, UInt<2>(0h2)) when _T_73 : node _T_74 = and(p1, p2) node _T_75 = and(_T_74, ppred) when _T_75 : skip else : node _T_76 = and(p1, ppred) when _T_76 : connect io.uop.uopc, slot_uop.uopc connect io.uop.lrs2_rtype, UInt<2>(0h2) else : node _T_77 = and(p2, ppred) when _T_77 : connect io.uop.uopc, UInt<7>(0h3) connect io.uop.lrs1_rtype, UInt<2>(0h2) connect io.debug.p1, p1 connect io.debug.p2, p2 connect io.debug.p3, p3 connect io.debug.ppred, ppred connect io.debug.state, state	module IssueSlot_7( // @[issue-slot.scala:69:7] input clock, // @[issue-slot.scala:69:7] input reset, // @[issue-slot.scala:69:7] output io_valid, // @[issue-slot.scala:73:14] output io_will_be_valid, // @[issue-slot.scala:73:14] output io_request, // @[issue-slot.scala:73:14] output io_request_hp, // @[issue-slot.scala:73:14] input io_grant, // @[issue-slot.scala:73:14] input [7:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14] input [7:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14] input [7:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14] input io_brupdate_b2_valid, // @[issue-slot.scala:73:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14] input io_brupdate_b2_taken, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14] input io_kill, // @[issue-slot.scala:73:14] input io_clear, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14] input [5:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14] input [5:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14] input io_in_uop_valid, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14] input [7:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14] input io_in_uop_bits_taken, // @[issue-slot.scala:73:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14] input io_in_uop_bits_exception, // @[issue-slot.scala:73:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14] input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14] output io_out_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14] output io_out_uop_is_br, // @[issue-slot.scala:73:14] output io_out_uop_is_jalr, // @[issue-slot.scala:73:14] output io_out_uop_is_jal, // @[issue-slot.scala:73:14] output io_out_uop_is_sfb, // @[issue-slot.scala:73:14] output [7:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_out_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14] output io_out_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_pdst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_prs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_prs2, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_prs3, // @[issue-slot.scala:73:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_out_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14] output io_out_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14] output io_out_uop_mem_signed, // @[issue-slot.scala:73:14] output io_out_uop_is_fence, // @[issue-slot.scala:73:14] output io_out_uop_is_fencei, // @[issue-slot.scala:73:14] output io_out_uop_is_amo, // @[issue-slot.scala:73:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_out_uop_uses_stq, // @[issue-slot.scala:73:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_out_uop_is_unique, // @[issue-slot.scala:73:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14] output io_out_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_out_uop_frs3_en, // @[issue-slot.scala:73:14] output io_out_uop_fp_val, // @[issue-slot.scala:73:14] output io_out_uop_fp_single, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14] output io_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output io_uop_is_br, // @[issue-slot.scala:73:14] output io_uop_is_jalr, // @[issue-slot.scala:73:14] output io_uop_is_jal, // @[issue-slot.scala:73:14] output io_uop_is_sfb, // @[issue-slot.scala:73:14] output [7:0] io_uop_br_mask, // @[issue-slot.scala:73:14] output [2:0] io_uop_br_tag, // @[issue-slot.scala:73:14] output [3:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14] output io_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14] output [4:0] io_uop_rob_idx, // @[issue-slot.scala:73:14] output [2:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14] output [2:0] io_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14] output [5:0] io_uop_pdst, // @[issue-slot.scala:73:14] output [5:0] io_uop_prs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_prs2, // @[issue-slot.scala:73:14] output [5:0] io_uop_prs3, // @[issue-slot.scala:73:14] output io_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_uop_prs3_busy, // @[issue-slot.scala:73:14] output [5:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14] output io_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14] output io_uop_mem_signed, // @[issue-slot.scala:73:14] output io_uop_is_fence, // @[issue-slot.scala:73:14] output io_uop_is_fencei, // @[issue-slot.scala:73:14] output io_uop_is_amo, // @[issue-slot.scala:73:14] output io_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_uop_uses_stq, // @[issue-slot.scala:73:14] output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_uop_is_unique, // @[issue-slot.scala:73:14] output io_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14] output io_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_uop_frs3_en, // @[issue-slot.scala:73:14] output io_uop_fp_val, // @[issue-slot.scala:73:14] output io_uop_fp_single, // @[issue-slot.scala:73:14] output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14] output io_debug_p1, // @[issue-slot.scala:73:14] output io_debug_p2, // @[issue-slot.scala:73:14] output io_debug_p3, // @[issue-slot.scala:73:14] output io_debug_ppred, // @[issue-slot.scala:73:14] output [1:0] io_debug_state // @[issue-slot.scala:73:14] ); wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7] wire [7:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7] wire [7:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7] wire [7:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7] wire [5:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7] wire [5:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7] wire [7:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7] wire io_ldspec_miss = 1'h0; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_bits_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_bits_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7] wire io_spec_ld_wakeup_0_valid = 1'h0; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ppred_busy = 1'h0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_uop_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_uop_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_uop_ppred_busy = 1'h0; // @[issue-slot.scala:69:7] wire next_p1_poisoned = 1'h0; // @[issue-slot.scala:99:29] wire next_p2_poisoned = 1'h0; // @[issue-slot.scala:100:29] wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire next_uop_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:103:21] wire next_uop_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:103:21] wire next_uop_ppred_busy = 1'h0; // @[issue-slot.scala:103:21] wire _squash_grant_T = 1'h0; // @[issue-slot.scala:261:53] wire squash_grant = 1'h0; // @[issue-slot.scala:261:37] wire [3:0] io_pred_wakeup_port_bits = 4'h0; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ppred = 4'h0; // @[issue-slot.scala:69:7] wire [3:0] io_out_uop_ppred = 4'h0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ppred = 4'h0; // @[issue-slot.scala:69:7] wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_uop_ftq_idx = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_uop_ppred = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [3:0] next_uop_ppred = 4'h0; // @[issue-slot.scala:103:21] wire [1:0] io_in_uop_bits_iw_state = 2'h1; // @[issue-slot.scala:69:7] wire [1:0] io_uop_iw_state = 2'h1; // @[issue-slot.scala:69:7] wire [1:0] next_uop_iw_state = 2'h1; // @[issue-slot.scala:103:21] wire [5:0] io_spec_ld_wakeup_0_bits = 6'h0; // @[issue-slot.scala:69:7] wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_pdst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_prs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_prs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_prs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_stale_pdst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire _ppred_T = 1'h1; // @[issue-slot.scala:172:14] wire _io_will_be_valid_T_1 = 1'h1; // @[issue-slot.scala:262:51] wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_br_tag = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ldq_idx = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_stq_idx = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_rob_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [7:0] slot_uop_uop_br_mask = 8'h0; // @[consts.scala:269:19] wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire _io_valid_T; // @[issue-slot.scala:79:24] wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32] wire _io_request_hp_T; // @[issue-slot.scala:243:31] wire [6:0] next_uopc; // @[issue-slot.scala:82:29] wire [1:0] next_state; // @[issue-slot.scala:81:29] wire [7:0] next_br_mask; // @[util.scala:85:25] wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28] wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28] wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28] wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28] wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29] wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29] wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [7:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [3:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_out_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_out_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7] wire io_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [7:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_pdst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_prs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_prs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_prs3_0; // @[issue-slot.scala:69:7] wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire io_debug_p1_0; // @[issue-slot.scala:69:7] wire io_debug_p2_0; // @[issue-slot.scala:69:7] wire io_debug_p3_0; // @[issue-slot.scala:69:7] wire io_debug_ppred_0; // @[issue-slot.scala:69:7] wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7] wire io_valid_0; // @[issue-slot.scala:69:7] wire io_will_be_valid_0; // @[issue-slot.scala:69:7] wire io_request_0; // @[issue-slot.scala:69:7] wire io_request_hp_0; // @[issue-slot.scala:69:7] assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29] assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29] assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29] assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29] reg [1:0] state; // @[issue-slot.scala:86:22] assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22] reg p1; // @[issue-slot.scala:87:22] assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22] wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25] reg p2; // @[issue-slot.scala:88:22] assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22] wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25] reg p3; // @[issue-slot.scala:89:22] assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22] wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25] reg ppred; // @[issue-slot.scala:90:22] assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22] wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28] reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25] reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25] assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25] assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_rvc; // @[issue-slot.scala:102:25] assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25] assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25] assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_br; // @[issue-slot.scala:102:25] assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jalr; // @[issue-slot.scala:102:25] assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jal; // @[issue-slot.scala:102:25] assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sfb; // @[issue-slot.scala:102:25] assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] reg [7:0] slot_uop_br_mask; // @[issue-slot.scala:102:25] assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_br_tag; // @[issue-slot.scala:102:25] assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_edge_inst; // @[issue-slot.scala:102:25] assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25] assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_taken; // @[issue-slot.scala:102:25] assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25] assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25] assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_prs1; // @[issue-slot.scala:102:25] assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_prs2; // @[issue-slot.scala:102:25] assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_prs3; // @[issue-slot.scala:102:25] assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25] assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25] assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs3_busy; // @[issue-slot.scala:102:25] assign io_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_exception; // @[issue-slot.scala:102:25] assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25] assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bypassable; // @[issue-slot.scala:102:25] assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25] assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_mem_signed; // @[issue-slot.scala:102:25] assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fence; // @[issue-slot.scala:102:25] assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fencei; // @[issue-slot.scala:102:25] assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_amo; // @[issue-slot.scala:102:25] assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_stq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25] assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_unique; // @[issue-slot.scala:102:25] assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25] assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25] assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25] assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25] assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_val; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25] assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25] reg slot_uop_frs3_en; // @[issue-slot.scala:102:25] assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_val; // @[issue-slot.scala:102:25] assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_single; // @[issue-slot.scala:102:25] assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [7:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs3_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs3_busy_0 : slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25] wire _T_7 = io_grant_0 & state == 2'h1 \| io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}] wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25] wire _GEN = io_kill_0 \| _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51] wire _GEN_0 = _GEN \| ~(_T_12 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:62, :142:17, :143:23] assign next_uopc = _GEN_0 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51] assign next_lrs1_rtype = _GEN_0 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51] wire _GEN_1 = _GEN \| ~_T_12 \| p1; // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:62, :142:17] assign next_lrs2_rtype = _GEN_1 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17]
Generate the Verilog code corresponding to this FIRRTL code module MulRawFN_7 : output io : { flip a : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}, flip b : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}, invalidExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}} inst mulFullRaw of MulFullRawFN_7 connect mulFullRaw.io.a.sig, io.a.sig connect mulFullRaw.io.a.sExp, io.a.sExp connect mulFullRaw.io.a.sign, io.a.sign connect mulFullRaw.io.a.isZero, io.a.isZero connect mulFullRaw.io.a.isInf, io.a.isInf connect mulFullRaw.io.a.isNaN, io.a.isNaN connect mulFullRaw.io.b.sig, io.b.sig connect mulFullRaw.io.b.sExp, io.b.sExp connect mulFullRaw.io.b.sign, io.b.sign connect mulFullRaw.io.b.isZero, io.b.isZero connect mulFullRaw.io.b.isInf, io.b.isInf connect mulFullRaw.io.b.isNaN, io.b.isNaN connect io.invalidExc, mulFullRaw.io.invalidExc connect io.rawOut, mulFullRaw.io.rawOut node _io_rawOut_sig_T = shr(mulFullRaw.io.rawOut.sig, 22) node _io_rawOut_sig_T_1 = bits(mulFullRaw.io.rawOut.sig, 21, 0) node _io_rawOut_sig_T_2 = orr(_io_rawOut_sig_T_1) node _io_rawOut_sig_T_3 = cat(_io_rawOut_sig_T, _io_rawOut_sig_T_2) connect io.rawOut.sig, _io_rawOut_sig_T_3	module MulRawFN_7( // @[MulRecFN.scala:75:7] input io_a_isNaN, // @[MulRecFN.scala:77:16] input io_a_isInf, // @[MulRecFN.scala:77:16] input io_a_isZero, // @[MulRecFN.scala:77:16] input io_a_sign, // @[MulRecFN.scala:77:16] input [9:0] io_a_sExp, // @[MulRecFN.scala:77:16] input [24:0] io_a_sig, // @[MulRecFN.scala:77:16] input io_b_isNaN, // @[MulRecFN.scala:77:16] input io_b_isInf, // @[MulRecFN.scala:77:16] input io_b_isZero, // @[MulRecFN.scala:77:16] input io_b_sign, // @[MulRecFN.scala:77:16] input [9:0] io_b_sExp, // @[MulRecFN.scala:77:16] input [24:0] io_b_sig, // @[MulRecFN.scala:77:16] output io_invalidExc, // @[MulRecFN.scala:77:16] output io_rawOut_isNaN, // @[MulRecFN.scala:77:16] output io_rawOut_isInf, // @[MulRecFN.scala:77:16] output io_rawOut_isZero, // @[MulRecFN.scala:77:16] output io_rawOut_sign, // @[MulRecFN.scala:77:16] output [9:0] io_rawOut_sExp, // @[MulRecFN.scala:77:16] output [26:0] io_rawOut_sig // @[MulRecFN.scala:77:16] ); wire [47:0] _mulFullRaw_io_rawOut_sig; // @[MulRecFN.scala:84:28] wire io_a_isNaN_0 = io_a_isNaN; // @[MulRecFN.scala:75:7] wire io_a_isInf_0 = io_a_isInf; // @[MulRecFN.scala:75:7] wire io_a_isZero_0 = io_a_isZero; // @[MulRecFN.scala:75:7] wire io_a_sign_0 = io_a_sign; // @[MulRecFN.scala:75:7] wire [9:0] io_a_sExp_0 = io_a_sExp; // @[MulRecFN.scala:75:7] wire [24:0] io_a_sig_0 = io_a_sig; // @[MulRecFN.scala:75:7] wire io_b_isNaN_0 = io_b_isNaN; // @[MulRecFN.scala:75:7] wire io_b_isInf_0 = io_b_isInf; // @[MulRecFN.scala:75:7] wire io_b_isZero_0 = io_b_isZero; // @[MulRecFN.scala:75:7] wire io_b_sign_0 = io_b_sign; // @[MulRecFN.scala:75:7] wire [9:0] io_b_sExp_0 = io_b_sExp; // @[MulRecFN.scala:75:7] wire [24:0] io_b_sig_0 = io_b_sig; // @[MulRecFN.scala:75:7] wire [26:0] _io_rawOut_sig_T_3; // @[MulRecFN.scala:93:10] wire io_rawOut_isNaN_0; // @[MulRecFN.scala:75:7] wire io_rawOut_isInf_0; // @[MulRecFN.scala:75:7] wire io_rawOut_isZero_0; // @[MulRecFN.scala:75:7] wire io_rawOut_sign_0; // @[MulRecFN.scala:75:7] wire [9:0] io_rawOut_sExp_0; // @[MulRecFN.scala:75:7] wire [26:0] io_rawOut_sig_0; // @[MulRecFN.scala:75:7] wire io_invalidExc_0; // @[MulRecFN.scala:75:7] wire [25:0] _io_rawOut_sig_T = _mulFullRaw_io_rawOut_sig[47:22]; // @[MulRecFN.scala:84:28, :93:15] wire [21:0] _io_rawOut_sig_T_1 = _mulFullRaw_io_rawOut_sig[21:0]; // @[MulRecFN.scala:84:28, :93:37] wire _io_rawOut_sig_T_2 = \|_io_rawOut_sig_T_1; // @[MulRecFN.scala:93:{37,55}] assign _io_rawOut_sig_T_3 = {_io_rawOut_sig_T, _io_rawOut_sig_T_2}; // @[MulRecFN.scala:93:{10,15,55}] assign io_rawOut_sig_0 = _io_rawOut_sig_T_3; // @[MulRecFN.scala:75:7, :93:10] MulFullRawFN_7 mulFullRaw ( // @[MulRecFN.scala:84:28] .io_a_isNaN (io_a_isNaN_0), // @[MulRecFN.scala:75:7] .io_a_isInf (io_a_isInf_0), // @[MulRecFN.scala:75:7] .io_a_isZero (io_a_isZero_0), // @[MulRecFN.scala:75:7] .io_a_sign (io_a_sign_0), // @[MulRecFN.scala:75:7] .io_a_sExp (io_a_sExp_0), // @[MulRecFN.scala:75:7] .io_a_sig (io_a_sig_0), // @[MulRecFN.scala:75:7] .io_b_isNaN (io_b_isNaN_0), // @[MulRecFN.scala:75:7] .io_b_isInf (io_b_isInf_0), // @[MulRecFN.scala:75:7] .io_b_isZero (io_b_isZero_0), // @[MulRecFN.scala:75:7] .io_b_sign (io_b_sign_0), // @[MulRecFN.scala:75:7] .io_b_sExp (io_b_sExp_0), // @[MulRecFN.scala:75:7] .io_b_sig (io_b_sig_0), // @[MulRecFN.scala:75:7] .io_invalidExc (io_invalidExc_0), .io_rawOut_isNaN (io_rawOut_isNaN_0), .io_rawOut_isInf (io_rawOut_isInf_0), .io_rawOut_isZero (io_rawOut_isZero_0), .io_rawOut_sign (io_rawOut_sign_0), .io_rawOut_sExp (io_rawOut_sExp_0), .io_rawOut_sig (_mulFullRaw_io_rawOut_sig) ); // @[MulRecFN.scala:84:28] assign io_invalidExc = io_invalidExc_0; // @[MulRecFN.scala:75:7] assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulRecFN.scala:75:7] assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulRecFN.scala:75:7] assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulRecFN.scala:75:7] assign io_rawOut_sign = io_rawOut_sign_0; // @[MulRecFN.scala:75:7] assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulRecFN.scala:75:7] assign io_rawOut_sig = io_rawOut_sig_0; // @[MulRecFN.scala:75:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TileResetSetter : input clock : Clock input reset : Reset output auto : { flip clock_in : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}}, clock_out : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}}, flip tl_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire tlNodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate tlNodeIn.d.bits.corrupt invalidate tlNodeIn.d.bits.data invalidate tlNodeIn.d.bits.denied invalidate tlNodeIn.d.bits.sink invalidate tlNodeIn.d.bits.source invalidate tlNodeIn.d.bits.size invalidate tlNodeIn.d.bits.param invalidate tlNodeIn.d.bits.opcode invalidate tlNodeIn.d.valid invalidate tlNodeIn.d.ready invalidate tlNodeIn.a.bits.corrupt invalidate tlNodeIn.a.bits.data invalidate tlNodeIn.a.bits.mask invalidate tlNodeIn.a.bits.address invalidate tlNodeIn.a.bits.source invalidate tlNodeIn.a.bits.size invalidate tlNodeIn.a.bits.param invalidate tlNodeIn.a.bits.opcode invalidate tlNodeIn.a.valid invalidate tlNodeIn.a.ready inst monitor of TLMonitor_101 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, tlNodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, tlNodeIn.d.bits.data connect monitor.io.in.d.bits.denied, tlNodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, tlNodeIn.d.bits.sink connect monitor.io.in.d.bits.source, tlNodeIn.d.bits.source connect monitor.io.in.d.bits.size, tlNodeIn.d.bits.size connect monitor.io.in.d.bits.param, tlNodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, tlNodeIn.d.bits.opcode connect monitor.io.in.d.valid, tlNodeIn.d.valid connect monitor.io.in.d.ready, tlNodeIn.d.ready connect monitor.io.in.a.bits.corrupt, tlNodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, tlNodeIn.a.bits.data connect monitor.io.in.a.bits.mask, tlNodeIn.a.bits.mask connect monitor.io.in.a.bits.address, tlNodeIn.a.bits.address connect monitor.io.in.a.bits.source, tlNodeIn.a.bits.source connect monitor.io.in.a.bits.size, tlNodeIn.a.bits.size connect monitor.io.in.a.bits.param, tlNodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, tlNodeIn.a.bits.opcode connect monitor.io.in.a.valid, tlNodeIn.a.valid connect monitor.io.in.a.ready, tlNodeIn.a.ready wire clockNodeOut : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}} invalidate clockNodeOut.member.allClocks_uncore.reset invalidate clockNodeOut.member.allClocks_uncore.clock wire clockNodeIn : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}} invalidate clockNodeIn.member.allClocks_uncore.reset invalidate clockNodeIn.member.allClocks_uncore.clock connect clockNodeOut, clockNodeIn connect tlNodeIn, auto.tl_in connect auto.clock_out, clockNodeOut connect clockNodeIn, auto.clock_in wire tile_async_resets : Reset[8] node _tile_async_resets_0_T = asAsyncReset(UInt<1>(0h1)) connect tile_async_resets[0], _tile_async_resets_0_T inst r_tile_resets_0 of AsyncResetRegVec_w1_i0_41 connect r_tile_resets_0.clock, clock connect r_tile_resets_0.reset, tile_async_resets[0] node _tile_async_resets_1_T = asAsyncReset(UInt<1>(0h1)) connect tile_async_resets[1], _tile_async_resets_1_T inst r_tile_resets_1 of AsyncResetRegVec_w1_i0_42 connect r_tile_resets_1.clock, clock connect r_tile_resets_1.reset, tile_async_resets[1] node _tile_async_resets_2_T = asAsyncReset(UInt<1>(0h1)) connect tile_async_resets[2], _tile_async_resets_2_T inst r_tile_resets_2 of AsyncResetRegVec_w1_i0_43 connect r_tile_resets_2.clock, clock connect r_tile_resets_2.reset, tile_async_resets[2] node _tile_async_resets_3_T = asAsyncReset(UInt<1>(0h1)) connect tile_async_resets[3], _tile_async_resets_3_T inst r_tile_resets_3 of AsyncResetRegVec_w1_i0_44 connect r_tile_resets_3.clock, clock connect r_tile_resets_3.reset, tile_async_resets[3] node _tile_async_resets_4_T = asAsyncReset(UInt<1>(0h1)) connect tile_async_resets[4], _tile_async_resets_4_T inst r_tile_resets_4 of AsyncResetRegVec_w1_i0_45 connect r_tile_resets_4.clock, clock connect r_tile_resets_4.reset, tile_async_resets[4] node _tile_async_resets_5_T = asAsyncReset(UInt<1>(0h1)) connect tile_async_resets[5], _tile_async_resets_5_T inst r_tile_resets_5 of AsyncResetRegVec_w1_i0_46 connect r_tile_resets_5.clock, clock connect r_tile_resets_5.reset, tile_async_resets[5] node _tile_async_resets_6_T = asAsyncReset(UInt<1>(0h1)) connect tile_async_resets[6], _tile_async_resets_6_T inst r_tile_resets_6 of AsyncResetRegVec_w1_i0_47 connect r_tile_resets_6.clock, clock connect r_tile_resets_6.reset, tile_async_resets[6] node _tile_async_resets_7_T = asAsyncReset(UInt<1>(0h1)) connect tile_async_resets[7], _tile_async_resets_7_T inst r_tile_resets_7 of AsyncResetRegVec_w1_i0_48 connect r_tile_resets_7.clock, clock connect r_tile_resets_7.reset, tile_async_resets[7] wire in : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}} node _in_bits_read_T = eq(tlNodeIn.a.bits.opcode, UInt<3>(0h4)) connect in.bits.read, _in_bits_read_T node _in_bits_index_T = shr(tlNodeIn.a.bits.address, 3) connect in.bits.index, _in_bits_index_T connect in.bits.data, tlNodeIn.a.bits.data connect in.bits.mask, tlNodeIn.a.bits.mask connect in.bits.extra.tlrr_extra.source, tlNodeIn.a.bits.source connect in.bits.extra.tlrr_extra.size, tlNodeIn.a.bits.size wire out : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, data : UInt<64>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}} wire out_front : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}} connect out_front.bits, in.bits node out_maskMatch = not(UInt<9>(0h3)) node out_findex = and(out_front.bits.index, out_maskMatch) node out_bindex = and(out_front.bits.index, out_maskMatch) node _out_T = eq(out_findex, UInt<9>(0h0)) node _out_T_1 = eq(out_bindex, UInt<9>(0h0)) node _out_T_2 = eq(out_findex, UInt<9>(0h0)) node _out_T_3 = eq(out_bindex, UInt<9>(0h0)) node _out_T_4 = eq(out_findex, UInt<9>(0h0)) node _out_T_5 = eq(out_bindex, UInt<9>(0h0)) node _out_T_6 = eq(out_findex, UInt<9>(0h0)) node _out_T_7 = eq(out_bindex, UInt<9>(0h0)) wire out_rivalid : UInt<1>[8] wire out_wivalid : UInt<1>[8] wire out_roready : UInt<1>[8] wire out_woready : UInt<1>[8] node _out_frontMask_T = bits(out_front.bits.mask, 0, 0) node _out_frontMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_frontMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_frontMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_frontMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_frontMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_frontMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_frontMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_frontMask_T_8 = mux(_out_frontMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_9 = mux(_out_frontMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_10 = mux(_out_frontMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_11 = mux(_out_frontMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_12 = mux(_out_frontMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_13 = mux(_out_frontMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_14 = mux(_out_frontMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_15 = mux(_out_frontMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_frontMask_lo_lo = cat(_out_frontMask_T_9, _out_frontMask_T_8) node out_frontMask_lo_hi = cat(_out_frontMask_T_11, _out_frontMask_T_10) node out_frontMask_lo = cat(out_frontMask_lo_hi, out_frontMask_lo_lo) node out_frontMask_hi_lo = cat(_out_frontMask_T_13, _out_frontMask_T_12) node out_frontMask_hi_hi = cat(_out_frontMask_T_15, _out_frontMask_T_14) node out_frontMask_hi = cat(out_frontMask_hi_hi, out_frontMask_hi_lo) node out_frontMask = cat(out_frontMask_hi, out_frontMask_lo) node _out_backMask_T = bits(out_front.bits.mask, 0, 0) node _out_backMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_backMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_backMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_backMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_backMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_backMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_backMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_backMask_T_8 = mux(_out_backMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_9 = mux(_out_backMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_10 = mux(_out_backMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_11 = mux(_out_backMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_12 = mux(_out_backMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_13 = mux(_out_backMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_14 = mux(_out_backMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_15 = mux(_out_backMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_backMask_lo_lo = cat(_out_backMask_T_9, _out_backMask_T_8) node out_backMask_lo_hi = cat(_out_backMask_T_11, _out_backMask_T_10) node out_backMask_lo = cat(out_backMask_lo_hi, out_backMask_lo_lo) node out_backMask_hi_lo = cat(_out_backMask_T_13, _out_backMask_T_12) node out_backMask_hi_hi = cat(_out_backMask_T_15, _out_backMask_T_14) node out_backMask_hi = cat(out_backMask_hi_hi, out_backMask_hi_lo) node out_backMask = cat(out_backMask_hi, out_backMask_lo) node _out_rimask_T = bits(out_frontMask, 0, 0) node out_rimask = orr(_out_rimask_T) node _out_wimask_T = bits(out_frontMask, 0, 0) node out_wimask = andr(_out_wimask_T) node _out_romask_T = bits(out_backMask, 0, 0) node out_romask = orr(_out_romask_T) node _out_womask_T = bits(out_backMask, 0, 0) node out_womask = andr(_out_womask_T) node out_f_rivalid = and(out_rivalid[0], out_rimask) node out_f_roready = and(out_roready[0], out_romask) node out_f_wivalid = and(out_wivalid[0], out_wimask) node out_f_woready = and(out_woready[0], out_womask) node _out_T_8 = bits(out_front.bits.data, 0, 0) connect r_tile_resets_0.io.en, out_f_woready connect r_tile_resets_0.io.d, _out_T_8 node _out_T_9 = eq(out_rimask, UInt<1>(0h0)) node _out_T_10 = eq(out_wimask, UInt<1>(0h0)) node _out_T_11 = eq(out_romask, UInt<1>(0h0)) node _out_T_12 = eq(out_womask, UInt<1>(0h0)) node _out_T_13 = or(r_tile_resets_0.io.q, UInt<1>(0h0)) node _out_T_14 = bits(_out_T_13, 0, 0) node _out_rimask_T_1 = bits(out_frontMask, 32, 32) node out_rimask_1 = orr(_out_rimask_T_1) node _out_wimask_T_1 = bits(out_frontMask, 32, 32) node out_wimask_1 = andr(_out_wimask_T_1) node _out_romask_T_1 = bits(out_backMask, 32, 32) node out_romask_1 = orr(_out_romask_T_1) node _out_womask_T_1 = bits(out_backMask, 32, 32) node out_womask_1 = andr(_out_womask_T_1) node out_f_rivalid_1 = and(out_rivalid[1], out_rimask_1) node out_f_roready_1 = and(out_roready[1], out_romask_1) node out_f_wivalid_1 = and(out_wivalid[1], out_wimask_1) node out_f_woready_1 = and(out_woready[1], out_womask_1) node _out_T_15 = bits(out_front.bits.data, 32, 32) connect r_tile_resets_1.io.en, out_f_woready_1 connect r_tile_resets_1.io.d, _out_T_15 node _out_T_16 = eq(out_rimask_1, UInt<1>(0h0)) node _out_T_17 = eq(out_wimask_1, UInt<1>(0h0)) node _out_T_18 = eq(out_romask_1, UInt<1>(0h0)) node _out_T_19 = eq(out_womask_1, UInt<1>(0h0)) node _out_prepend_T = or(_out_T_14, UInt<32>(0h0)) node out_prepend = cat(r_tile_resets_1.io.q, _out_prepend_T) node _out_T_20 = or(out_prepend, UInt<33>(0h0)) node _out_T_21 = bits(_out_T_20, 32, 0) node _out_rimask_T_2 = bits(out_frontMask, 0, 0) node out_rimask_2 = orr(_out_rimask_T_2) node _out_wimask_T_2 = bits(out_frontMask, 0, 0) node out_wimask_2 = andr(_out_wimask_T_2) node _out_romask_T_2 = bits(out_backMask, 0, 0) node out_romask_2 = orr(_out_romask_T_2) node _out_womask_T_2 = bits(out_backMask, 0, 0) node out_womask_2 = andr(_out_womask_T_2) node out_f_rivalid_2 = and(out_rivalid[2], out_rimask_2) node out_f_roready_2 = and(out_roready[2], out_romask_2) node out_f_wivalid_2 = and(out_wivalid[2], out_wimask_2) node out_f_woready_2 = and(out_woready[2], out_womask_2) node _out_T_22 = bits(out_front.bits.data, 0, 0) connect r_tile_resets_2.io.en, out_f_woready_2 connect r_tile_resets_2.io.d, _out_T_22 node _out_T_23 = eq(out_rimask_2, UInt<1>(0h0)) node _out_T_24 = eq(out_wimask_2, UInt<1>(0h0)) node _out_T_25 = eq(out_romask_2, UInt<1>(0h0)) node _out_T_26 = eq(out_womask_2, UInt<1>(0h0)) node _out_T_27 = or(r_tile_resets_2.io.q, UInt<1>(0h0)) node _out_T_28 = bits(_out_T_27, 0, 0) node _out_rimask_T_3 = bits(out_frontMask, 32, 32) node out_rimask_3 = orr(_out_rimask_T_3) node _out_wimask_T_3 = bits(out_frontMask, 32, 32) node out_wimask_3 = andr(_out_wimask_T_3) node _out_romask_T_3 = bits(out_backMask, 32, 32) node out_romask_3 = orr(_out_romask_T_3) node _out_womask_T_3 = bits(out_backMask, 32, 32) node out_womask_3 = andr(_out_womask_T_3) node out_f_rivalid_3 = and(out_rivalid[3], out_rimask_3) node out_f_roready_3 = and(out_roready[3], out_romask_3) node out_f_wivalid_3 = and(out_wivalid[3], out_wimask_3) node out_f_woready_3 = and(out_woready[3], out_womask_3) node _out_T_29 = bits(out_front.bits.data, 32, 32) connect r_tile_resets_3.io.en, out_f_woready_3 connect r_tile_resets_3.io.d, _out_T_29 node _out_T_30 = eq(out_rimask_3, UInt<1>(0h0)) node _out_T_31 = eq(out_wimask_3, UInt<1>(0h0)) node _out_T_32 = eq(out_romask_3, UInt<1>(0h0)) node _out_T_33 = eq(out_womask_3, UInt<1>(0h0)) node _out_prepend_T_1 = or(_out_T_28, UInt<32>(0h0)) node out_prepend_1 = cat(r_tile_resets_3.io.q, _out_prepend_T_1) node _out_T_34 = or(out_prepend_1, UInt<33>(0h0)) node _out_T_35 = bits(_out_T_34, 32, 0) node _out_rimask_T_4 = bits(out_frontMask, 0, 0) node out_rimask_4 = orr(_out_rimask_T_4) node _out_wimask_T_4 = bits(out_frontMask, 0, 0) node out_wimask_4 = andr(_out_wimask_T_4) node _out_romask_T_4 = bits(out_backMask, 0, 0) node out_romask_4 = orr(_out_romask_T_4) node _out_womask_T_4 = bits(out_backMask, 0, 0) node out_womask_4 = andr(_out_womask_T_4) node out_f_rivalid_4 = and(out_rivalid[4], out_rimask_4) node out_f_roready_4 = and(out_roready[4], out_romask_4) node out_f_wivalid_4 = and(out_wivalid[4], out_wimask_4) node out_f_woready_4 = and(out_woready[4], out_womask_4) node _out_T_36 = bits(out_front.bits.data, 0, 0) connect r_tile_resets_4.io.en, out_f_woready_4 connect r_tile_resets_4.io.d, _out_T_36 node _out_T_37 = eq(out_rimask_4, UInt<1>(0h0)) node _out_T_38 = eq(out_wimask_4, UInt<1>(0h0)) node _out_T_39 = eq(out_romask_4, UInt<1>(0h0)) node _out_T_40 = eq(out_womask_4, UInt<1>(0h0)) node _out_T_41 = or(r_tile_resets_4.io.q, UInt<1>(0h0)) node _out_T_42 = bits(_out_T_41, 0, 0) node _out_rimask_T_5 = bits(out_frontMask, 32, 32) node out_rimask_5 = orr(_out_rimask_T_5) node _out_wimask_T_5 = bits(out_frontMask, 32, 32) node out_wimask_5 = andr(_out_wimask_T_5) node _out_romask_T_5 = bits(out_backMask, 32, 32) node out_romask_5 = orr(_out_romask_T_5) node _out_womask_T_5 = bits(out_backMask, 32, 32) node out_womask_5 = andr(_out_womask_T_5) node out_f_rivalid_5 = and(out_rivalid[5], out_rimask_5) node out_f_roready_5 = and(out_roready[5], out_romask_5) node out_f_wivalid_5 = and(out_wivalid[5], out_wimask_5) node out_f_woready_5 = and(out_woready[5], out_womask_5) node _out_T_43 = bits(out_front.bits.data, 32, 32) connect r_tile_resets_5.io.en, out_f_woready_5 connect r_tile_resets_5.io.d, _out_T_43 node _out_T_44 = eq(out_rimask_5, UInt<1>(0h0)) node _out_T_45 = eq(out_wimask_5, UInt<1>(0h0)) node _out_T_46 = eq(out_romask_5, UInt<1>(0h0)) node _out_T_47 = eq(out_womask_5, UInt<1>(0h0)) node _out_prepend_T_2 = or(_out_T_42, UInt<32>(0h0)) node out_prepend_2 = cat(r_tile_resets_5.io.q, _out_prepend_T_2) node _out_T_48 = or(out_prepend_2, UInt<33>(0h0)) node _out_T_49 = bits(_out_T_48, 32, 0) node _out_rimask_T_6 = bits(out_frontMask, 0, 0) node out_rimask_6 = orr(_out_rimask_T_6) node _out_wimask_T_6 = bits(out_frontMask, 0, 0) node out_wimask_6 = andr(_out_wimask_T_6) node _out_romask_T_6 = bits(out_backMask, 0, 0) node out_romask_6 = orr(_out_romask_T_6) node _out_womask_T_6 = bits(out_backMask, 0, 0) node out_womask_6 = andr(_out_womask_T_6) node out_f_rivalid_6 = and(out_rivalid[6], out_rimask_6) node out_f_roready_6 = and(out_roready[6], out_romask_6) node out_f_wivalid_6 = and(out_wivalid[6], out_wimask_6) node out_f_woready_6 = and(out_woready[6], out_womask_6) node _out_T_50 = bits(out_front.bits.data, 0, 0) connect r_tile_resets_6.io.en, out_f_woready_6 connect r_tile_resets_6.io.d, _out_T_50 node _out_T_51 = eq(out_rimask_6, UInt<1>(0h0)) node _out_T_52 = eq(out_wimask_6, UInt<1>(0h0)) node _out_T_53 = eq(out_romask_6, UInt<1>(0h0)) node _out_T_54 = eq(out_womask_6, UInt<1>(0h0)) node _out_T_55 = or(r_tile_resets_6.io.q, UInt<1>(0h0)) node _out_T_56 = bits(_out_T_55, 0, 0) node _out_rimask_T_7 = bits(out_frontMask, 32, 32) node out_rimask_7 = orr(_out_rimask_T_7) node _out_wimask_T_7 = bits(out_frontMask, 32, 32) node out_wimask_7 = andr(_out_wimask_T_7) node _out_romask_T_7 = bits(out_backMask, 32, 32) node out_romask_7 = orr(_out_romask_T_7) node _out_womask_T_7 = bits(out_backMask, 32, 32) node out_womask_7 = andr(_out_womask_T_7) node out_f_rivalid_7 = and(out_rivalid[7], out_rimask_7) node out_f_roready_7 = and(out_roready[7], out_romask_7) node out_f_wivalid_7 = and(out_wivalid[7], out_wimask_7) node out_f_woready_7 = and(out_woready[7], out_womask_7) node _out_T_57 = bits(out_front.bits.data, 32, 32) connect r_tile_resets_7.io.en, out_f_woready_7 connect r_tile_resets_7.io.d, _out_T_57 node _out_T_58 = eq(out_rimask_7, UInt<1>(0h0)) node _out_T_59 = eq(out_wimask_7, UInt<1>(0h0)) node _out_T_60 = eq(out_romask_7, UInt<1>(0h0)) node _out_T_61 = eq(out_womask_7, UInt<1>(0h0)) node _out_prepend_T_3 = or(_out_T_56, UInt<32>(0h0)) node out_prepend_3 = cat(r_tile_resets_7.io.q, _out_prepend_T_3) node _out_T_62 = or(out_prepend_3, UInt<33>(0h0)) node _out_T_63 = bits(_out_T_62, 32, 0) node _out_iindex_T = bits(out_front.bits.index, 0, 0) node _out_iindex_T_1 = bits(out_front.bits.index, 1, 1) node _out_iindex_T_2 = bits(out_front.bits.index, 2, 2) node _out_iindex_T_3 = bits(out_front.bits.index, 3, 3) node _out_iindex_T_4 = bits(out_front.bits.index, 4, 4) node _out_iindex_T_5 = bits(out_front.bits.index, 5, 5) node _out_iindex_T_6 = bits(out_front.bits.index, 6, 6) node _out_iindex_T_7 = bits(out_front.bits.index, 7, 7) node _out_iindex_T_8 = bits(out_front.bits.index, 8, 8) node out_iindex = cat(_out_iindex_T_1, _out_iindex_T) node _out_oindex_T = bits(out_front.bits.index, 0, 0) node _out_oindex_T_1 = bits(out_front.bits.index, 1, 1) node _out_oindex_T_2 = bits(out_front.bits.index, 2, 2) node _out_oindex_T_3 = bits(out_front.bits.index, 3, 3) node _out_oindex_T_4 = bits(out_front.bits.index, 4, 4) node _out_oindex_T_5 = bits(out_front.bits.index, 5, 5) node _out_oindex_T_6 = bits(out_front.bits.index, 6, 6) node _out_oindex_T_7 = bits(out_front.bits.index, 7, 7) node _out_oindex_T_8 = bits(out_front.bits.index, 8, 8) node out_oindex = cat(_out_oindex_T_1, _out_oindex_T) node _out_frontSel_T = dshl(UInt<1>(0h1), out_iindex) node out_frontSel_0 = bits(_out_frontSel_T, 0, 0) node out_frontSel_1 = bits(_out_frontSel_T, 1, 1) node out_frontSel_2 = bits(_out_frontSel_T, 2, 2) node out_frontSel_3 = bits(_out_frontSel_T, 3, 3) node _out_backSel_T = dshl(UInt<1>(0h1), out_oindex) node out_backSel_0 = bits(_out_backSel_T, 0, 0) node out_backSel_1 = bits(_out_backSel_T, 1, 1) node out_backSel_2 = bits(_out_backSel_T, 2, 2) node out_backSel_3 = bits(_out_backSel_T, 3, 3) node _out_rifireMux_T = and(in.valid, out_front.ready) node _out_rifireMux_T_1 = and(_out_rifireMux_T, out_front.bits.read) wire out_rifireMux_out : UInt<1> node _out_rifireMux_T_2 = and(_out_rifireMux_T_1, out_frontSel_0) node _out_rifireMux_T_3 = and(_out_rifireMux_T_2, _out_T) connect out_rifireMux_out, UInt<1>(0h1) connect out_rivalid[1], _out_rifireMux_T_3 connect out_rivalid[0], _out_rifireMux_T_3 node _out_rifireMux_T_4 = eq(_out_T, UInt<1>(0h0)) node _out_rifireMux_T_5 = or(out_rifireMux_out, _out_rifireMux_T_4) wire out_rifireMux_out_1 : UInt<1> node _out_rifireMux_T_6 = and(_out_rifireMux_T_1, out_frontSel_1) node _out_rifireMux_T_7 = and(_out_rifireMux_T_6, _out_T_2) connect out_rifireMux_out_1, UInt<1>(0h1) connect out_rivalid[3], _out_rifireMux_T_7 connect out_rivalid[2], _out_rifireMux_T_7 node _out_rifireMux_T_8 = eq(_out_T_2, UInt<1>(0h0)) node _out_rifireMux_T_9 = or(out_rifireMux_out_1, _out_rifireMux_T_8) wire out_rifireMux_out_2 : UInt<1> node _out_rifireMux_T_10 = and(_out_rifireMux_T_1, out_frontSel_2) node _out_rifireMux_T_11 = and(_out_rifireMux_T_10, _out_T_4) connect out_rifireMux_out_2, UInt<1>(0h1) connect out_rivalid[5], _out_rifireMux_T_11 connect out_rivalid[4], _out_rifireMux_T_11 node _out_rifireMux_T_12 = eq(_out_T_4, UInt<1>(0h0)) node _out_rifireMux_T_13 = or(out_rifireMux_out_2, _out_rifireMux_T_12) wire out_rifireMux_out_3 : UInt<1> node _out_rifireMux_T_14 = and(_out_rifireMux_T_1, out_frontSel_3) node _out_rifireMux_T_15 = and(_out_rifireMux_T_14, _out_T_6) connect out_rifireMux_out_3, UInt<1>(0h1) connect out_rivalid[7], _out_rifireMux_T_15 connect out_rivalid[6], _out_rifireMux_T_15 node _out_rifireMux_T_16 = eq(_out_T_6, UInt<1>(0h0)) node _out_rifireMux_T_17 = or(out_rifireMux_out_3, _out_rifireMux_T_16) node _out_rifireMux_T_18 = geq(out_iindex, UInt<3>(0h4)) wire _out_rifireMux_WIRE : UInt<1>[4] connect _out_rifireMux_WIRE[0], _out_rifireMux_T_5 connect _out_rifireMux_WIRE[1], _out_rifireMux_T_9 connect _out_rifireMux_WIRE[2], _out_rifireMux_T_13 connect _out_rifireMux_WIRE[3], _out_rifireMux_T_17 node out_rifireMux = mux(_out_rifireMux_T_18, UInt<1>(0h1), _out_rifireMux_WIRE[out_iindex]) node _out_wifireMux_T = and(in.valid, out_front.ready) node _out_wifireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wifireMux_T_2 = and(_out_wifireMux_T, _out_wifireMux_T_1) wire out_wifireMux_out : UInt<1> node _out_wifireMux_T_3 = and(_out_wifireMux_T_2, out_frontSel_0) node _out_wifireMux_T_4 = and(_out_wifireMux_T_3, _out_T) connect out_wifireMux_out, UInt<1>(0h1) connect out_wivalid[1], _out_wifireMux_T_4 connect out_wivalid[0], _out_wifireMux_T_4 node _out_wifireMux_T_5 = eq(_out_T, UInt<1>(0h0)) node _out_wifireMux_T_6 = or(out_wifireMux_out, _out_wifireMux_T_5) wire out_wifireMux_out_1 : UInt<1> node _out_wifireMux_T_7 = and(_out_wifireMux_T_2, out_frontSel_1) node _out_wifireMux_T_8 = and(_out_wifireMux_T_7, _out_T_2) connect out_wifireMux_out_1, UInt<1>(0h1) connect out_wivalid[3], _out_wifireMux_T_8 connect out_wivalid[2], _out_wifireMux_T_8 node _out_wifireMux_T_9 = eq(_out_T_2, UInt<1>(0h0)) node _out_wifireMux_T_10 = or(out_wifireMux_out_1, _out_wifireMux_T_9) wire out_wifireMux_out_2 : UInt<1> node _out_wifireMux_T_11 = and(_out_wifireMux_T_2, out_frontSel_2) node _out_wifireMux_T_12 = and(_out_wifireMux_T_11, _out_T_4) connect out_wifireMux_out_2, UInt<1>(0h1) connect out_wivalid[5], _out_wifireMux_T_12 connect out_wivalid[4], _out_wifireMux_T_12 node _out_wifireMux_T_13 = eq(_out_T_4, UInt<1>(0h0)) node _out_wifireMux_T_14 = or(out_wifireMux_out_2, _out_wifireMux_T_13) wire out_wifireMux_out_3 : UInt<1> node _out_wifireMux_T_15 = and(_out_wifireMux_T_2, out_frontSel_3) node _out_wifireMux_T_16 = and(_out_wifireMux_T_15, _out_T_6) connect out_wifireMux_out_3, UInt<1>(0h1) connect out_wivalid[7], _out_wifireMux_T_16 connect out_wivalid[6], _out_wifireMux_T_16 node _out_wifireMux_T_17 = eq(_out_T_6, UInt<1>(0h0)) node _out_wifireMux_T_18 = or(out_wifireMux_out_3, _out_wifireMux_T_17) node _out_wifireMux_T_19 = geq(out_iindex, UInt<3>(0h4)) wire _out_wifireMux_WIRE : UInt<1>[4] connect _out_wifireMux_WIRE[0], _out_wifireMux_T_6 connect _out_wifireMux_WIRE[1], _out_wifireMux_T_10 connect _out_wifireMux_WIRE[2], _out_wifireMux_T_14 connect _out_wifireMux_WIRE[3], _out_wifireMux_T_18 node out_wifireMux = mux(_out_wifireMux_T_19, UInt<1>(0h1), _out_wifireMux_WIRE[out_iindex]) node _out_rofireMux_T = and(out_front.valid, out.ready) node _out_rofireMux_T_1 = and(_out_rofireMux_T, out_front.bits.read) wire out_rofireMux_out : UInt<1> node _out_rofireMux_T_2 = and(_out_rofireMux_T_1, out_backSel_0) node _out_rofireMux_T_3 = and(_out_rofireMux_T_2, _out_T_1) connect out_rofireMux_out, UInt<1>(0h1) connect out_roready[1], _out_rofireMux_T_3 connect out_roready[0], _out_rofireMux_T_3 node _out_rofireMux_T_4 = eq(_out_T_1, UInt<1>(0h0)) node _out_rofireMux_T_5 = or(out_rofireMux_out, _out_rofireMux_T_4) wire out_rofireMux_out_1 : UInt<1> node _out_rofireMux_T_6 = and(_out_rofireMux_T_1, out_backSel_1) node _out_rofireMux_T_7 = and(_out_rofireMux_T_6, _out_T_3) connect out_rofireMux_out_1, UInt<1>(0h1) connect out_roready[3], _out_rofireMux_T_7 connect out_roready[2], _out_rofireMux_T_7 node _out_rofireMux_T_8 = eq(_out_T_3, UInt<1>(0h0)) node _out_rofireMux_T_9 = or(out_rofireMux_out_1, _out_rofireMux_T_8) wire out_rofireMux_out_2 : UInt<1> node _out_rofireMux_T_10 = and(_out_rofireMux_T_1, out_backSel_2) node _out_rofireMux_T_11 = and(_out_rofireMux_T_10, _out_T_5) connect out_rofireMux_out_2, UInt<1>(0h1) connect out_roready[5], _out_rofireMux_T_11 connect out_roready[4], _out_rofireMux_T_11 node _out_rofireMux_T_12 = eq(_out_T_5, UInt<1>(0h0)) node _out_rofireMux_T_13 = or(out_rofireMux_out_2, _out_rofireMux_T_12) wire out_rofireMux_out_3 : UInt<1> node _out_rofireMux_T_14 = and(_out_rofireMux_T_1, out_backSel_3) node _out_rofireMux_T_15 = and(_out_rofireMux_T_14, _out_T_7) connect out_rofireMux_out_3, UInt<1>(0h1) connect out_roready[7], _out_rofireMux_T_15 connect out_roready[6], _out_rofireMux_T_15 node _out_rofireMux_T_16 = eq(_out_T_7, UInt<1>(0h0)) node _out_rofireMux_T_17 = or(out_rofireMux_out_3, _out_rofireMux_T_16) node _out_rofireMux_T_18 = geq(out_oindex, UInt<3>(0h4)) wire _out_rofireMux_WIRE : UInt<1>[4] connect _out_rofireMux_WIRE[0], _out_rofireMux_T_5 connect _out_rofireMux_WIRE[1], _out_rofireMux_T_9 connect _out_rofireMux_WIRE[2], _out_rofireMux_T_13 connect _out_rofireMux_WIRE[3], _out_rofireMux_T_17 node out_rofireMux = mux(_out_rofireMux_T_18, UInt<1>(0h1), _out_rofireMux_WIRE[out_oindex]) node _out_wofireMux_T = and(out_front.valid, out.ready) node _out_wofireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wofireMux_T_2 = and(_out_wofireMux_T, _out_wofireMux_T_1) wire out_wofireMux_out : UInt<1> node _out_wofireMux_T_3 = and(_out_wofireMux_T_2, out_backSel_0) node _out_wofireMux_T_4 = and(_out_wofireMux_T_3, _out_T_1) connect out_wofireMux_out, UInt<1>(0h1) connect out_woready[1], _out_wofireMux_T_4 connect out_woready[0], _out_wofireMux_T_4 node _out_wofireMux_T_5 = eq(_out_T_1, UInt<1>(0h0)) node _out_wofireMux_T_6 = or(out_wofireMux_out, _out_wofireMux_T_5) wire out_wofireMux_out_1 : UInt<1> node _out_wofireMux_T_7 = and(_out_wofireMux_T_2, out_backSel_1) node _out_wofireMux_T_8 = and(_out_wofireMux_T_7, _out_T_3) connect out_wofireMux_out_1, UInt<1>(0h1) connect out_woready[3], _out_wofireMux_T_8 connect out_woready[2], _out_wofireMux_T_8 node _out_wofireMux_T_9 = eq(_out_T_3, UInt<1>(0h0)) node _out_wofireMux_T_10 = or(out_wofireMux_out_1, _out_wofireMux_T_9) wire out_wofireMux_out_2 : UInt<1> node _out_wofireMux_T_11 = and(_out_wofireMux_T_2, out_backSel_2) node _out_wofireMux_T_12 = and(_out_wofireMux_T_11, _out_T_5) connect out_wofireMux_out_2, UInt<1>(0h1) connect out_woready[5], _out_wofireMux_T_12 connect out_woready[4], _out_wofireMux_T_12 node _out_wofireMux_T_13 = eq(_out_T_5, UInt<1>(0h0)) node _out_wofireMux_T_14 = or(out_wofireMux_out_2, _out_wofireMux_T_13) wire out_wofireMux_out_3 : UInt<1> node _out_wofireMux_T_15 = and(_out_wofireMux_T_2, out_backSel_3) node _out_wofireMux_T_16 = and(_out_wofireMux_T_15, _out_T_7) connect out_wofireMux_out_3, UInt<1>(0h1) connect out_woready[7], _out_wofireMux_T_16 connect out_woready[6], _out_wofireMux_T_16 node _out_wofireMux_T_17 = eq(_out_T_7, UInt<1>(0h0)) node _out_wofireMux_T_18 = or(out_wofireMux_out_3, _out_wofireMux_T_17) node _out_wofireMux_T_19 = geq(out_oindex, UInt<3>(0h4)) wire _out_wofireMux_WIRE : UInt<1>[4] connect _out_wofireMux_WIRE[0], _out_wofireMux_T_6 connect _out_wofireMux_WIRE[1], _out_wofireMux_T_10 connect _out_wofireMux_WIRE[2], _out_wofireMux_T_14 connect _out_wofireMux_WIRE[3], _out_wofireMux_T_18 node out_wofireMux = mux(_out_wofireMux_T_19, UInt<1>(0h1), _out_wofireMux_WIRE[out_oindex]) node out_iready = mux(out_front.bits.read, out_rifireMux, out_wifireMux) node out_oready = mux(out_front.bits.read, out_rofireMux, out_wofireMux) node _out_in_ready_T = and(out_front.ready, out_iready) connect in.ready, _out_in_ready_T node _out_front_valid_T = and(in.valid, out_iready) connect out_front.valid, _out_front_valid_T node _out_front_ready_T = and(out.ready, out_oready) connect out_front.ready, _out_front_ready_T node _out_out_valid_T = and(out_front.valid, out_oready) connect out.valid, _out_out_valid_T connect out.bits.read, out_front.bits.read node _out_out_bits_data_T = geq(out_oindex, UInt<3>(0h4)) wire _out_out_bits_data_WIRE : UInt<1>[4] connect _out_out_bits_data_WIRE[0], _out_T_1 connect _out_out_bits_data_WIRE[1], _out_T_3 connect _out_out_bits_data_WIRE[2], _out_T_5 connect _out_out_bits_data_WIRE[3], _out_T_7 node _out_out_bits_data_T_1 = mux(_out_out_bits_data_T, UInt<1>(0h1), _out_out_bits_data_WIRE[out_oindex]) node _out_out_bits_data_T_2 = geq(out_oindex, UInt<3>(0h4)) wire _out_out_bits_data_WIRE_1 : UInt<33>[4] connect _out_out_bits_data_WIRE_1[0], _out_T_21 connect _out_out_bits_data_WIRE_1[1], _out_T_35 connect _out_out_bits_data_WIRE_1[2], _out_T_49 connect _out_out_bits_data_WIRE_1[3], _out_T_63 node _out_out_bits_data_T_3 = mux(_out_out_bits_data_T_2, UInt<1>(0h0), _out_out_bits_data_WIRE_1[out_oindex]) node _out_out_bits_data_T_4 = mux(_out_out_bits_data_T_1, _out_out_bits_data_T_3, UInt<1>(0h0)) connect out.bits.data, _out_out_bits_data_T_4 connect out.bits.extra, out_front.bits.extra connect in.valid, tlNodeIn.a.valid connect tlNodeIn.a.ready, in.ready connect tlNodeIn.d.valid, out.valid connect out.ready, tlNodeIn.d.ready wire tlNodeIn_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} connect tlNodeIn_d_bits_d.opcode, UInt<1>(0h0) connect tlNodeIn_d_bits_d.param, UInt<1>(0h0) connect tlNodeIn_d_bits_d.size, out.bits.extra.tlrr_extra.size connect tlNodeIn_d_bits_d.source, out.bits.extra.tlrr_extra.source connect tlNodeIn_d_bits_d.sink, UInt<1>(0h0) connect tlNodeIn_d_bits_d.denied, UInt<1>(0h0) invalidate tlNodeIn_d_bits_d.data connect tlNodeIn_d_bits_d.corrupt, UInt<1>(0h0) connect tlNodeIn.d.bits.corrupt, tlNodeIn_d_bits_d.corrupt connect tlNodeIn.d.bits.data, tlNodeIn_d_bits_d.data connect tlNodeIn.d.bits.denied, tlNodeIn_d_bits_d.denied connect tlNodeIn.d.bits.sink, tlNodeIn_d_bits_d.sink connect tlNodeIn.d.bits.source, tlNodeIn_d_bits_d.source connect tlNodeIn.d.bits.size, tlNodeIn_d_bits_d.size connect tlNodeIn.d.bits.param, tlNodeIn_d_bits_d.param connect tlNodeIn.d.bits.opcode, tlNodeIn_d_bits_d.opcode connect tlNodeIn.d.bits.data, out.bits.data node _tlNodeIn_d_bits_opcode_T = mux(out.bits.read, UInt<1>(0h1), UInt<1>(0h0)) connect tlNodeIn.d.bits.opcode, _tlNodeIn_d_bits_opcode_T wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<21>(0h0) connect _WIRE.bits.source, UInt<11>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<21>(0h0) connect _WIRE_2.bits.source, UInt<11>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) connect clockNodeOut.member.allClocks_uncore.clock, clockNodeIn.member.allClocks_uncore.clock connect clockNodeOut.member.allClocks_uncore.reset, clockNodeIn.member.allClocks_uncore.reset extmodule plusarg_reader_240 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_241 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32	module TileResetSetter( // @[TileResetSetter.scala:26:25] input clock, // @[TileResetSetter.scala:26:25] input reset, // @[TileResetSetter.scala:26:25] input auto_clock_in_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25] input auto_clock_in_member_allClocks_uncore_reset, // @[LazyModuleImp.scala:107:25] output auto_clock_out_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25] output auto_clock_out_member_allClocks_uncore_reset, // @[LazyModuleImp.scala:107:25] output auto_tl_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_tl_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_tl_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_tl_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [20:0] auto_tl_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_tl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input auto_tl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_tl_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_tl_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_tl_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_tl_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_tl_in_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire [2:0] tlNodeIn_d_bits_opcode = {2'h0, auto_tl_in_a_bits_opcode == 3'h4}; // @[RegisterRouter.scala:74:36, :105:19] TLMonitor_101 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (auto_tl_in_d_ready), .io_in_a_valid (auto_tl_in_a_valid), .io_in_a_bits_opcode (auto_tl_in_a_bits_opcode), .io_in_a_bits_param (auto_tl_in_a_bits_param), .io_in_a_bits_size (auto_tl_in_a_bits_size), .io_in_a_bits_source (auto_tl_in_a_bits_source), .io_in_a_bits_address (auto_tl_in_a_bits_address), .io_in_a_bits_mask (auto_tl_in_a_bits_mask), .io_in_a_bits_corrupt (auto_tl_in_a_bits_corrupt), .io_in_d_ready (auto_tl_in_d_ready), .io_in_d_valid (auto_tl_in_a_valid), .io_in_d_bits_opcode (tlNodeIn_d_bits_opcode), // @[RegisterRouter.scala:105:19] .io_in_d_bits_size (auto_tl_in_a_bits_size), .io_in_d_bits_source (auto_tl_in_a_bits_source) ); // @[Nodes.scala:27:25] assign auto_clock_out_member_allClocks_uncore_clock = auto_clock_in_member_allClocks_uncore_clock; // @[TileResetSetter.scala:26:25] assign auto_clock_out_member_allClocks_uncore_reset = auto_clock_in_member_allClocks_uncore_reset; // @[TileResetSetter.scala:26:25] assign auto_tl_in_a_ready = auto_tl_in_d_ready; // @[TileResetSetter.scala:26:25] assign auto_tl_in_d_valid = auto_tl_in_a_valid; // @[TileResetSetter.scala:26:25] assign auto_tl_in_d_bits_opcode = tlNodeIn_d_bits_opcode; // @[RegisterRouter.scala:105:19] assign auto_tl_in_d_bits_size = auto_tl_in_a_bits_size; // @[TileResetSetter.scala:26:25] assign auto_tl_in_d_bits_source = auto_tl_in_a_bits_source; // @[TileResetSetter.scala:26:25] assign auto_tl_in_d_bits_data = 64'h0; // @[TileResetSetter.scala:26:25] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNPipe_l2_e5_s11 : input clock : Clock input reset : Reset output io : { flip validin : UInt<1>, flip op : UInt<2>, flip a : UInt<17>, flip b : UInt<17>, flip c : UInt<17>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<17>, exceptionFlags : UInt<5>, validout : UInt<1>} inst mulAddRecFNToRaw_preMul of MulAddRecFNToRaw_preMul_e5_s11 inst mulAddRecFNToRaw_postMul of MulAddRecFNToRaw_postMul_e5_s11 connect mulAddRecFNToRaw_preMul.io.op, io.op connect mulAddRecFNToRaw_preMul.io.a, io.a connect mulAddRecFNToRaw_preMul.io.b, io.b connect mulAddRecFNToRaw_preMul.io.c, io.c node _mulAddResult_T = mul(mulAddRecFNToRaw_preMul.io.mulAddA, mulAddRecFNToRaw_preMul.io.mulAddB) node mulAddResult = add(_mulAddResult_T, mulAddRecFNToRaw_preMul.io.mulAddC) wire valid_stage0 : UInt<1> wire roundingMode_stage0 : UInt<3> wire detectTininess_stage0 : UInt<1> regreset mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v, io.validin reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<7>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<4>, highAlignedSigC : UInt<13>, bit0AlignedSigC : UInt<1>}, clock when io.validin : connect mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b, mulAddRecFNToRaw_preMul.io.toPostMul wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out : { valid : UInt<1>, bits : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<7>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<4>, highAlignedSigC : UInt<13>, bit0AlignedSigC : UInt<1>}} connect mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.valid, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v connect mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b connect mulAddRecFNToRaw_postMul.io.fromPreMul.bit0AlignedSigC, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.bit0AlignedSigC connect mulAddRecFNToRaw_postMul.io.fromPreMul.highAlignedSigC, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.highAlignedSigC connect mulAddRecFNToRaw_postMul.io.fromPreMul.CDom_CAlignDist, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.CDom_CAlignDist connect mulAddRecFNToRaw_postMul.io.fromPreMul.CIsDominant, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.CIsDominant connect mulAddRecFNToRaw_postMul.io.fromPreMul.doSubMags, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.doSubMags connect mulAddRecFNToRaw_postMul.io.fromPreMul.sExpSum, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.sExpSum connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroC, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isZeroC connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfC, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isInfC connect mulAddRecFNToRaw_postMul.io.fromPreMul.isNaNC, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isNaNC connect mulAddRecFNToRaw_postMul.io.fromPreMul.signProd, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.signProd connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroB, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isZeroB connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfB, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isInfB connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroA, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isZeroA connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfA, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isInfA connect mulAddRecFNToRaw_postMul.io.fromPreMul.isNaNAOrB, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isNaNAOrB connect mulAddRecFNToRaw_postMul.io.fromPreMul.isSigNaNAny, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isSigNaNAny regreset mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v, io.validin reg mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b : UInt<23>, clock when io.validin : connect mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b, mulAddResult wire mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out : { valid : UInt<1>, bits : UInt<23>} connect mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out.valid, mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v connect mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out.bits, mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b connect mulAddRecFNToRaw_postMul.io.mulAddResult, mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out.bits regreset mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v, io.validin reg mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b : UInt<3>, clock when io.validin : connect mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b, io.roundingMode wire mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out : { valid : UInt<1>, bits : UInt<3>} connect mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out.valid, mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v connect mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out.bits, mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b connect mulAddRecFNToRaw_postMul.io.roundingMode, mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out.bits regreset roundingMode_stage0_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect roundingMode_stage0_pipe_v, io.validin reg roundingMode_stage0_pipe_b : UInt<3>, clock when io.validin : connect roundingMode_stage0_pipe_b, io.roundingMode wire roundingMode_stage0_pipe_out : { valid : UInt<1>, bits : UInt<3>} connect roundingMode_stage0_pipe_out.valid, roundingMode_stage0_pipe_v connect roundingMode_stage0_pipe_out.bits, roundingMode_stage0_pipe_b connect roundingMode_stage0, roundingMode_stage0_pipe_out.bits regreset detectTininess_stage0_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect detectTininess_stage0_pipe_v, io.validin reg detectTininess_stage0_pipe_b : UInt<1>, clock when io.validin : connect detectTininess_stage0_pipe_b, io.detectTininess wire detectTininess_stage0_pipe_out : { valid : UInt<1>, bits : UInt<1>} connect detectTininess_stage0_pipe_out.valid, detectTininess_stage0_pipe_v connect detectTininess_stage0_pipe_out.bits, detectTininess_stage0_pipe_b connect detectTininess_stage0, detectTininess_stage0_pipe_out.bits regreset valid_stage0_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect valid_stage0_pipe_v, io.validin reg valid_stage0_pipe_b : UInt<1>, clock when io.validin : connect valid_stage0_pipe_b, UInt<1>(0h0) wire valid_stage0_pipe_out : { valid : UInt<1>, bits : UInt<1>} connect valid_stage0_pipe_out.valid, valid_stage0_pipe_v connect valid_stage0_pipe_out.bits, valid_stage0_pipe_b connect valid_stage0, valid_stage0_pipe_out.valid inst roundRawFNToRecFN of RoundRawFNToRecFN_e5_s11 regreset roundRawFNToRecFN_io_invalidExc_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect roundRawFNToRecFN_io_invalidExc_pipe_v, valid_stage0 reg roundRawFNToRecFN_io_invalidExc_pipe_b : UInt<1>, clock when valid_stage0 : connect roundRawFNToRecFN_io_invalidExc_pipe_b, mulAddRecFNToRaw_postMul.io.invalidExc wire roundRawFNToRecFN_io_invalidExc_pipe_out : { valid : UInt<1>, bits : UInt<1>} connect roundRawFNToRecFN_io_invalidExc_pipe_out.valid, roundRawFNToRecFN_io_invalidExc_pipe_v connect roundRawFNToRecFN_io_invalidExc_pipe_out.bits, roundRawFNToRecFN_io_invalidExc_pipe_b connect roundRawFNToRecFN.io.invalidExc, roundRawFNToRecFN_io_invalidExc_pipe_out.bits regreset roundRawFNToRecFN_io_in_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect roundRawFNToRecFN_io_in_pipe_v, valid_stage0 reg roundRawFNToRecFN_io_in_pipe_b : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<14>}, clock when valid_stage0 : connect roundRawFNToRecFN_io_in_pipe_b, mulAddRecFNToRaw_postMul.io.rawOut wire roundRawFNToRecFN_io_in_pipe_out : { valid : UInt<1>, bits : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<14>}} connect roundRawFNToRecFN_io_in_pipe_out.valid, roundRawFNToRecFN_io_in_pipe_v connect roundRawFNToRecFN_io_in_pipe_out.bits, roundRawFNToRecFN_io_in_pipe_b connect roundRawFNToRecFN.io.in.sig, roundRawFNToRecFN_io_in_pipe_out.bits.sig connect roundRawFNToRecFN.io.in.sExp, roundRawFNToRecFN_io_in_pipe_out.bits.sExp connect roundRawFNToRecFN.io.in.sign, roundRawFNToRecFN_io_in_pipe_out.bits.sign connect roundRawFNToRecFN.io.in.isZero, roundRawFNToRecFN_io_in_pipe_out.bits.isZero connect roundRawFNToRecFN.io.in.isInf, roundRawFNToRecFN_io_in_pipe_out.bits.isInf connect roundRawFNToRecFN.io.in.isNaN, roundRawFNToRecFN_io_in_pipe_out.bits.isNaN regreset roundRawFNToRecFN_io_roundingMode_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect roundRawFNToRecFN_io_roundingMode_pipe_v, valid_stage0 reg roundRawFNToRecFN_io_roundingMode_pipe_b : UInt<3>, clock when valid_stage0 : connect roundRawFNToRecFN_io_roundingMode_pipe_b, roundingMode_stage0 wire roundRawFNToRecFN_io_roundingMode_pipe_out : { valid : UInt<1>, bits : UInt<3>} connect roundRawFNToRecFN_io_roundingMode_pipe_out.valid, roundRawFNToRecFN_io_roundingMode_pipe_v connect roundRawFNToRecFN_io_roundingMode_pipe_out.bits, roundRawFNToRecFN_io_roundingMode_pipe_b connect roundRawFNToRecFN.io.roundingMode, roundRawFNToRecFN_io_roundingMode_pipe_out.bits regreset roundRawFNToRecFN_io_detectTininess_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect roundRawFNToRecFN_io_detectTininess_pipe_v, valid_stage0 reg roundRawFNToRecFN_io_detectTininess_pipe_b : UInt<1>, clock when valid_stage0 : connect roundRawFNToRecFN_io_detectTininess_pipe_b, detectTininess_stage0 wire roundRawFNToRecFN_io_detectTininess_pipe_out : { valid : UInt<1>, bits : UInt<1>} connect roundRawFNToRecFN_io_detectTininess_pipe_out.valid, roundRawFNToRecFN_io_detectTininess_pipe_v connect roundRawFNToRecFN_io_detectTininess_pipe_out.bits, roundRawFNToRecFN_io_detectTininess_pipe_b connect roundRawFNToRecFN.io.detectTininess, roundRawFNToRecFN_io_detectTininess_pipe_out.bits regreset io_validout_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect io_validout_pipe_v, valid_stage0 reg io_validout_pipe_b : UInt<1>, clock when valid_stage0 : connect io_validout_pipe_b, UInt<1>(0h0) wire io_validout_pipe_out : { valid : UInt<1>, bits : UInt<1>} connect io_validout_pipe_out.valid, io_validout_pipe_v connect io_validout_pipe_out.bits, io_validout_pipe_b connect io.validout, io_validout_pipe_out.valid connect roundRawFNToRecFN.io.infiniteExc, UInt<1>(0h0) connect io.out, roundRawFNToRecFN.io.out connect io.exceptionFlags, roundRawFNToRecFN.io.exceptionFlags	module MulAddRecFNPipe_l2_e5_s11( // @[FPU.scala:633:7] input clock, // @[FPU.scala:633:7] input reset, // @[FPU.scala:633:7] input io_validin, // @[FPU.scala:638:16] input [1:0] io_op, // @[FPU.scala:638:16] input [16:0] io_a, // @[FPU.scala:638:16] input [16:0] io_b, // @[FPU.scala:638:16] input [16:0] io_c, // @[FPU.scala:638:16] input [2:0] io_roundingMode, // @[FPU.scala:638:16] output [16:0] io_out, // @[FPU.scala:638:16] output [4:0] io_exceptionFlags, // @[FPU.scala:638:16] output io_validout // @[FPU.scala:638:16] ); wire _mulAddRecFNToRaw_postMul_io_invalidExc; // @[FPU.scala:655:42] wire _mulAddRecFNToRaw_postMul_io_rawOut_isNaN; // @[FPU.scala:655:42] wire _mulAddRecFNToRaw_postMul_io_rawOut_isInf; // @[FPU.scala:655:42] wire _mulAddRecFNToRaw_postMul_io_rawOut_isZero; // @[FPU.scala:655:42] wire _mulAddRecFNToRaw_postMul_io_rawOut_sign; // @[FPU.scala:655:42] wire [6:0] _mulAddRecFNToRaw_postMul_io_rawOut_sExp; // @[FPU.scala:655:42] wire [13:0] _mulAddRecFNToRaw_postMul_io_rawOut_sig; // @[FPU.scala:655:42] wire [10:0] _mulAddRecFNToRaw_preMul_io_mulAddA; // @[FPU.scala:654:41] wire [10:0] _mulAddRecFNToRaw_preMul_io_mulAddB; // @[FPU.scala:654:41] wire [21:0] _mulAddRecFNToRaw_preMul_io_mulAddC; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfB; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_signProd; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfC; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC; // @[FPU.scala:654:41] wire [6:0] _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant; // @[FPU.scala:654:41] wire [3:0] _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist; // @[FPU.scala:654:41] wire [12:0] _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC; // @[FPU.scala:654:41] wire io_validin_0 = io_validin; // @[FPU.scala:633:7] wire [1:0] io_op_0 = io_op; // @[FPU.scala:633:7] wire [16:0] io_a_0 = io_a; // @[FPU.scala:633:7] wire [16:0] io_b_0 = io_b; // @[FPU.scala:633:7] wire [16:0] io_c_0 = io_c; // @[FPU.scala:633:7] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[FPU.scala:633:7] wire io_detectTininess = 1'h1; // @[FPU.scala:633:7] wire detectTininess_stage0 = 1'h1; // @[FPU.scala:669:37] wire detectTininess_stage0_pipe_out_bits = 1'h1; // @[Valid.scala:135:21] wire valid_stage0_pipe_out_bits = 1'h0; // @[Valid.scala:135:21] wire io_validout_pipe_out_bits = 1'h0; // @[Valid.scala:135:21] wire io_validout_pipe_out_valid; // @[Valid.scala:135:21] wire [16:0] io_out_0; // @[FPU.scala:633:7] wire [4:0] io_exceptionFlags_0; // @[FPU.scala:633:7] wire io_validout_0; // @[FPU.scala:633:7] wire [21:0] _mulAddResult_T = {11'h0, _mulAddRecFNToRaw_preMul_io_mulAddA} * {11'h0, _mulAddRecFNToRaw_preMul_io_mulAddB}; // @[FPU.scala:654:41, :663:45] wire [22:0] mulAddResult = {1'h0, _mulAddResult_T} + {1'h0, _mulAddRecFNToRaw_preMul_io_mulAddC}; // @[FPU.scala:654:41, :663:45, :664:50] wire valid_stage0_pipe_out_valid; // @[Valid.scala:135:21] wire valid_stage0; // @[FPU.scala:667:28] wire [2:0] roundingMode_stage0_pipe_out_bits; // @[Valid.scala:135:21] wire [2:0] roundingMode_stage0; // @[FPU.scala:668:35] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v; // @[Valid.scala:141:24] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_valid = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v; // @[Valid.scala:135:21, :141:24] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isSigNaNAny = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isNaNAOrB = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfA = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroA = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfB = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroB = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_signProd = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isNaNC = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfC = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroC = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC; // @[Valid.scala:135:21, :142:26] reg [6:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum; // @[Valid.scala:142:26] wire [6:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_sExpSum = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_doSubMags = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_CIsDominant = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant; // @[Valid.scala:135:21, :142:26] reg [3:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist; // @[Valid.scala:142:26] wire [3:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_CDom_CAlignDist = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist; // @[Valid.scala:135:21, :142:26] reg [12:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC; // @[Valid.scala:142:26] wire [12:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_highAlignedSigC = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_bit0AlignedSigC = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v; // @[Valid.scala:141:24] wire mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out_valid = mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v; // @[Valid.scala:135:21, :141:24] reg [22:0] mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b; // @[Valid.scala:142:26] wire [22:0] mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out_bits = mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v; // @[Valid.scala:141:24] wire mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out_valid = mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v; // @[Valid.scala:135:21, :141:24] reg [2:0] mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b; // @[Valid.scala:142:26] wire [2:0] mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out_bits = mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b; // @[Valid.scala:135:21, :142:26] reg roundingMode_stage0_pipe_v; // @[Valid.scala:141:24] wire roundingMode_stage0_pipe_out_valid = roundingMode_stage0_pipe_v; // @[Valid.scala:135:21, :141:24] reg [2:0] roundingMode_stage0_pipe_b; // @[Valid.scala:142:26] assign roundingMode_stage0_pipe_out_bits = roundingMode_stage0_pipe_b; // @[Valid.scala:135:21, :142:26] assign roundingMode_stage0 = roundingMode_stage0_pipe_out_bits; // @[Valid.scala:135:21] reg detectTininess_stage0_pipe_v; // @[Valid.scala:141:24] wire detectTininess_stage0_pipe_out_valid = detectTininess_stage0_pipe_v; // @[Valid.scala:135:21, :141:24] reg valid_stage0_pipe_v; // @[Valid.scala:141:24] assign valid_stage0_pipe_out_valid = valid_stage0_pipe_v; // @[Valid.scala:135:21, :141:24] assign valid_stage0 = valid_stage0_pipe_out_valid; // @[Valid.scala:135:21] reg roundRawFNToRecFN_io_invalidExc_pipe_v; // @[Valid.scala:141:24] wire roundRawFNToRecFN_io_invalidExc_pipe_out_valid = roundRawFNToRecFN_io_invalidExc_pipe_v; // @[Valid.scala:135:21, :141:24] reg roundRawFNToRecFN_io_invalidExc_pipe_b; // @[Valid.scala:142:26] wire roundRawFNToRecFN_io_invalidExc_pipe_out_bits = roundRawFNToRecFN_io_invalidExc_pipe_b; // @[Valid.scala:135:21, :142:26] reg roundRawFNToRecFN_io_in_pipe_v; // @[Valid.scala:141:24] wire roundRawFNToRecFN_io_in_pipe_out_valid = roundRawFNToRecFN_io_in_pipe_v; // @[Valid.scala:135:21, :141:24] reg roundRawFNToRecFN_io_in_pipe_b_isNaN; // @[Valid.scala:142:26] wire roundRawFNToRecFN_io_in_pipe_out_bits_isNaN = roundRawFNToRecFN_io_in_pipe_b_isNaN; // @[Valid.scala:135:21, :142:26] reg roundRawFNToRecFN_io_in_pipe_b_isInf; // @[Valid.scala:142:26] wire roundRawFNToRecFN_io_in_pipe_out_bits_isInf = roundRawFNToRecFN_io_in_pipe_b_isInf; // @[Valid.scala:135:21, :142:26] reg roundRawFNToRecFN_io_in_pipe_b_isZero; // @[Valid.scala:142:26] wire roundRawFNToRecFN_io_in_pipe_out_bits_isZero = roundRawFNToRecFN_io_in_pipe_b_isZero; // @[Valid.scala:135:21, :142:26] reg roundRawFNToRecFN_io_in_pipe_b_sign; // @[Valid.scala:142:26] wire roundRawFNToRecFN_io_in_pipe_out_bits_sign = roundRawFNToRecFN_io_in_pipe_b_sign; // @[Valid.scala:135:21, :142:26] reg [6:0] roundRawFNToRecFN_io_in_pipe_b_sExp; // @[Valid.scala:142:26] wire [6:0] roundRawFNToRecFN_io_in_pipe_out_bits_sExp = roundRawFNToRecFN_io_in_pipe_b_sExp; // @[Valid.scala:135:21, :142:26] reg [13:0] roundRawFNToRecFN_io_in_pipe_b_sig; // @[Valid.scala:142:26] wire [13:0] roundRawFNToRecFN_io_in_pipe_out_bits_sig = roundRawFNToRecFN_io_in_pipe_b_sig; // @[Valid.scala:135:21, :142:26] reg roundRawFNToRecFN_io_roundingMode_pipe_v; // @[Valid.scala:141:24] wire roundRawFNToRecFN_io_roundingMode_pipe_out_valid = roundRawFNToRecFN_io_roundingMode_pipe_v; // @[Valid.scala:135:21, :141:24] reg [2:0] roundRawFNToRecFN_io_roundingMode_pipe_b; // @[Valid.scala:142:26] wire [2:0] roundRawFNToRecFN_io_roundingMode_pipe_out_bits = roundRawFNToRecFN_io_roundingMode_pipe_b; // @[Valid.scala:135:21, :142:26] reg roundRawFNToRecFN_io_detectTininess_pipe_v; // @[Valid.scala:141:24] wire roundRawFNToRecFN_io_detectTininess_pipe_out_valid = roundRawFNToRecFN_io_detectTininess_pipe_v; // @[Valid.scala:135:21, :141:24] reg roundRawFNToRecFN_io_detectTininess_pipe_b; // @[Valid.scala:142:26] wire roundRawFNToRecFN_io_detectTininess_pipe_out_bits = roundRawFNToRecFN_io_detectTininess_pipe_b; // @[Valid.scala:135:21, :142:26] reg io_validout_pipe_v; // @[Valid.scala:141:24] assign io_validout_pipe_out_valid = io_validout_pipe_v; // @[Valid.scala:135:21, :141:24] assign io_validout_0 = io_validout_pipe_out_valid; // @[Valid.scala:135:21] always @(posedge clock) begin // @[FPU.scala:633:7] if (reset) begin // @[FPU.scala:633:7] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v <= 1'h0; // @[Valid.scala:141:24] mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v <= 1'h0; // @[Valid.scala:141:24] mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v <= 1'h0; // @[Valid.scala:141:24] roundingMode_stage0_pipe_v <= 1'h0; // @[Valid.scala:141:24] detectTininess_stage0_pipe_v <= 1'h0; // @[Valid.scala:141:24] valid_stage0_pipe_v <= 1'h0; // @[Valid.scala:141:24] roundRawFNToRecFN_io_invalidExc_pipe_v <= 1'h0; // @[Valid.scala:141:24] roundRawFNToRecFN_io_in_pipe_v <= 1'h0; // @[Valid.scala:141:24] roundRawFNToRecFN_io_roundingMode_pipe_v <= 1'h0; // @[Valid.scala:141:24] roundRawFNToRecFN_io_detectTininess_pipe_v <= 1'h0; // @[Valid.scala:141:24] io_validout_pipe_v <= 1'h0; // @[Valid.scala:141:24] end else begin // @[FPU.scala:633:7] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v <= io_validin_0; // @[Valid.scala:141:24] mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v <= io_validin_0; // @[Valid.scala:141:24] mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v <= io_validin_0; // @[Valid.scala:141:24] roundingMode_stage0_pipe_v <= io_validin_0; // @[Valid.scala:141:24] detectTininess_stage0_pipe_v <= io_validin_0; // @[Valid.scala:141:24] valid_stage0_pipe_v <= io_validin_0; // @[Valid.scala:141:24] roundRawFNToRecFN_io_invalidExc_pipe_v <= valid_stage0; // @[Valid.scala:141:24] roundRawFNToRecFN_io_in_pipe_v <= valid_stage0; // @[Valid.scala:141:24] roundRawFNToRecFN_io_roundingMode_pipe_v <= valid_stage0; // @[Valid.scala:141:24] roundRawFNToRecFN_io_detectTininess_pipe_v <= valid_stage0; // @[Valid.scala:141:24] io_validout_pipe_v <= valid_stage0; // @[Valid.scala:141:24] end if (io_validin_0) begin // @[FPU.scala:633:7] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny <= _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB <= _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA <= _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA <= _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB <= _mulAddRecFNToRaw_preMul_io_toPostMul_isInfB; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB <= _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd <= _mulAddRecFNToRaw_preMul_io_toPostMul_signProd; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC <= _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC <= _mulAddRecFNToRaw_preMul_io_toPostMul_isInfC; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC <= _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum <= _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags <= _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant <= _mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist <= _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC <= _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC <= _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b <= mulAddResult; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b <= io_roundingMode_0; // @[Valid.scala:142:26] roundingMode_stage0_pipe_b <= io_roundingMode_0; // @[Valid.scala:142:26] end if (valid_stage0) begin // @[FPU.scala:667:28] roundRawFNToRecFN_io_invalidExc_pipe_b <= _mulAddRecFNToRaw_postMul_io_invalidExc; // @[Valid.scala:142:26] roundRawFNToRecFN_io_in_pipe_b_isNaN <= _mulAddRecFNToRaw_postMul_io_rawOut_isNaN; // @[Valid.scala:142:26] roundRawFNToRecFN_io_in_pipe_b_isInf <= _mulAddRecFNToRaw_postMul_io_rawOut_isInf; // @[Valid.scala:142:26] roundRawFNToRecFN_io_in_pipe_b_isZero <= _mulAddRecFNToRaw_postMul_io_rawOut_isZero; // @[Valid.scala:142:26] roundRawFNToRecFN_io_in_pipe_b_sign <= _mulAddRecFNToRaw_postMul_io_rawOut_sign; // @[Valid.scala:142:26] roundRawFNToRecFN_io_in_pipe_b_sExp <= _mulAddRecFNToRaw_postMul_io_rawOut_sExp; // @[Valid.scala:142:26] roundRawFNToRecFN_io_in_pipe_b_sig <= _mulAddRecFNToRaw_postMul_io_rawOut_sig; // @[Valid.scala:142:26] roundRawFNToRecFN_io_roundingMode_pipe_b <= roundingMode_stage0; // @[Valid.scala:142:26] end roundRawFNToRecFN_io_detectTininess_pipe_b <= valid_stage0 \| roundRawFNToRecFN_io_detectTininess_pipe_b; // @[Valid.scala:142:26] always @(posedge) MulAddRecFNToRaw_preMul_e5_s11 mulAddRecFNToRaw_preMul ( // @[FPU.scala:654:41] .io_op (io_op_0), // @[FPU.scala:633:7] .io_a (io_a_0), // @[FPU.scala:633:7] .io_b (io_b_0), // @[FPU.scala:633:7] .io_c (io_c_0), // @[FPU.scala:633:7] .io_mulAddA (_mulAddRecFNToRaw_preMul_io_mulAddA), .io_mulAddB (_mulAddRecFNToRaw_preMul_io_mulAddB), .io_mulAddC (_mulAddRecFNToRaw_preMul_io_mulAddC), .io_toPostMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny), .io_toPostMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB), .io_toPostMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA), .io_toPostMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA), .io_toPostMul_isInfB (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfB), .io_toPostMul_isZeroB (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB), .io_toPostMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd), .io_toPostMul_isNaNC (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC), .io_toPostMul_isInfC (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfC), .io_toPostMul_isZeroC (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC), .io_toPostMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum), .io_toPostMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags), .io_toPostMul_CIsDominant (_mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant), .io_toPostMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist), .io_toPostMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC), .io_toPostMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC) ); // @[FPU.scala:654:41] MulAddRecFNToRaw_postMul_e5_s11 mulAddRecFNToRaw_postMul ( // @[FPU.scala:655:42] .io_fromPreMul_isSigNaNAny (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isSigNaNAny), // @[Valid.scala:135:21] .io_fromPreMul_isNaNAOrB (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isNaNAOrB), // @[Valid.scala:135:21] .io_fromPreMul_isInfA (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfA), // @[Valid.scala:135:21] .io_fromPreMul_isZeroA (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroA), // @[Valid.scala:135:21] .io_fromPreMul_isInfB (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfB), // @[Valid.scala:135:21] .io_fromPreMul_isZeroB (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroB), // @[Valid.scala:135:21] .io_fromPreMul_signProd (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_signProd), // @[Valid.scala:135:21] .io_fromPreMul_isNaNC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isNaNC), // @[Valid.scala:135:21] .io_fromPreMul_isInfC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfC), // @[Valid.scala:135:21] .io_fromPreMul_isZeroC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroC), // @[Valid.scala:135:21] .io_fromPreMul_sExpSum (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_sExpSum), // @[Valid.scala:135:21] .io_fromPreMul_doSubMags (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_doSubMags), // @[Valid.scala:135:21] .io_fromPreMul_CIsDominant (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_CIsDominant), // @[Valid.scala:135:21] .io_fromPreMul_CDom_CAlignDist (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_CDom_CAlignDist), // @[Valid.scala:135:21] .io_fromPreMul_highAlignedSigC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_highAlignedSigC), // @[Valid.scala:135:21] .io_fromPreMul_bit0AlignedSigC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_bit0AlignedSigC), // @[Valid.scala:135:21] .io_mulAddResult (mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out_bits), // @[Valid.scala:135:21] .io_roundingMode (mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out_bits), // @[Valid.scala:135:21] .io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc), .io_rawOut_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN), .io_rawOut_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf), .io_rawOut_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero), .io_rawOut_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign), .io_rawOut_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp), .io_rawOut_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig) ); // @[FPU.scala:655:42] RoundRawFNToRecFN_e5_s11 roundRawFNToRecFN ( // @[FPU.scala:682:35] .io_invalidExc (roundRawFNToRecFN_io_invalidExc_pipe_out_bits), // @[Valid.scala:135:21] .io_in_isNaN (roundRawFNToRecFN_io_in_pipe_out_bits_isNaN), // @[Valid.scala:135:21] .io_in_isInf (roundRawFNToRecFN_io_in_pipe_out_bits_isInf), // @[Valid.scala:135:21] .io_in_isZero (roundRawFNToRecFN_io_in_pipe_out_bits_isZero), // @[Valid.scala:135:21] .io_in_sign (roundRawFNToRecFN_io_in_pipe_out_bits_sign), // @[Valid.scala:135:21] .io_in_sExp (roundRawFNToRecFN_io_in_pipe_out_bits_sExp), // @[Valid.scala:135:21] .io_in_sig (roundRawFNToRecFN_io_in_pipe_out_bits_sig), // @[Valid.scala:135:21] .io_roundingMode (roundRawFNToRecFN_io_roundingMode_pipe_out_bits), // @[Valid.scala:135:21] .io_detectTininess (roundRawFNToRecFN_io_detectTininess_pipe_out_bits), // @[Valid.scala:135:21] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags_0) ); // @[FPU.scala:682:35] assign io_out = io_out_0; // @[FPU.scala:633:7] assign io_exceptionFlags = io_exceptionFlags_0; // @[FPU.scala:633:7] assign io_validout = io_validout_0; // @[FPU.scala:633:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PE_401 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_145 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<8>, clock reg c2 : SInt<8>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h0), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node _c1_T = bits(io.in_d, 7, 0) node _c1_T_1 = asSInt(_c1_T) connect c1, _c1_T_1 else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node _c2_T = bits(io.in_d, 7, 0) node _c2_T_1 = asSInt(_c2_T) connect c2, _c2_T_1 else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h0), _T_4) node _T_6 = or(UInt<1>(0h1), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c	module PE_401( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid // @[PE.scala:35:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7] wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60] wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [7:0] c1; // @[PE.scala:70:15] wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [7:0] c2; // @[PE.scala:71:15] wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = \|_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros \| io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = \|_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 \| io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}] wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16] wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8] c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15] if (~(~io_in_valid_0 \| io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8] c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15] if (io_in_valid_0) // @[PE.scala:31:7] last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] always @(posedge) MacUnit_145 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_b_0), // @[PE.scala:31:7] .io_out_d (io_out_b_0) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_43 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_43( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie7_is64_oe8_os24 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<9>, sig : UInt<65>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0)) node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1)) node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3)) node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4)) node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6)) node _roundMagUp_T = and(roundingMode_min, io.in.sign) node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0)) node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1) node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2) node _sAdjustedExp_T = add(io.in.sExp, asSInt(UInt<9>(0h80))) node _sAdjustedExp_T_1 = bits(_sAdjustedExp_T, 8, 0) node sAdjustedExp = cvt(_sAdjustedExp_T_1) node _adjustedSig_T = bits(io.in.sig, 64, 39) node _adjustedSig_T_1 = bits(io.in.sig, 38, 0) node _adjustedSig_T_2 = orr(_adjustedSig_T_1) node adjustedSig = cat(_adjustedSig_T, _adjustedSig_T_2) wire common_expOut : UInt<9> wire common_fractOut : UInt<23> wire common_overflow : UInt<1> wire common_totalUnderflow : UInt<1> wire common_underflow : UInt<1> wire common_inexact : UInt<1> node _roundMask_T = cat(UInt<24>(0h0), UInt<1>(0h0)) node roundMask = cat(_roundMask_T, UInt<2>(0h3)) node _shiftedRoundMask_T = cat(UInt<1>(0h0), roundMask) node shiftedRoundMask = shr(_shiftedRoundMask_T, 1) node _roundPosMask_T = not(shiftedRoundMask) node roundPosMask = and(_roundPosMask_T, roundMask) node _roundPosBit_T = and(adjustedSig, roundPosMask) node roundPosBit = orr(_roundPosBit_T) node _anyRoundExtra_T = and(adjustedSig, shiftedRoundMask) node anyRoundExtra = orr(_anyRoundExtra_T) node anyRound = or(roundPosBit, anyRoundExtra) node _roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _roundIncr_T_1 = and(_roundIncr_T, roundPosBit) node _roundIncr_T_2 = and(roundMagUp, anyRound) node roundIncr = or(_roundIncr_T_1, _roundIncr_T_2) node _roundedSig_T = or(adjustedSig, roundMask) node _roundedSig_T_1 = shr(_roundedSig_T, 2) node _roundedSig_T_2 = add(_roundedSig_T_1, UInt<1>(0h1)) node _roundedSig_T_3 = and(roundingMode_near_even, roundPosBit) node _roundedSig_T_4 = eq(anyRoundExtra, UInt<1>(0h0)) node _roundedSig_T_5 = and(_roundedSig_T_3, _roundedSig_T_4) node _roundedSig_T_6 = shr(roundMask, 1) node _roundedSig_T_7 = mux(_roundedSig_T_5, _roundedSig_T_6, UInt<26>(0h0)) node _roundedSig_T_8 = not(_roundedSig_T_7) node _roundedSig_T_9 = and(_roundedSig_T_2, _roundedSig_T_8) node _roundedSig_T_10 = not(roundMask) node _roundedSig_T_11 = and(adjustedSig, _roundedSig_T_10) node _roundedSig_T_12 = shr(_roundedSig_T_11, 2) node _roundedSig_T_13 = and(roundingMode_odd, anyRound) node _roundedSig_T_14 = shr(roundPosMask, 1) node _roundedSig_T_15 = mux(_roundedSig_T_13, _roundedSig_T_14, UInt<1>(0h0)) node _roundedSig_T_16 = or(_roundedSig_T_12, _roundedSig_T_15) node roundedSig = mux(roundIncr, _roundedSig_T_9, _roundedSig_T_16) node _sRoundedExp_T = shr(roundedSig, 24) node _sRoundedExp_T_1 = cvt(_sRoundedExp_T) node sRoundedExp = add(sAdjustedExp, _sRoundedExp_T_1) node _common_expOut_T = bits(sRoundedExp, 8, 0) connect common_expOut, _common_expOut_T node _common_fractOut_T = bits(roundedSig, 23, 1) node _common_fractOut_T_1 = bits(roundedSig, 22, 0) node _common_fractOut_T_2 = mux(UInt<1>(0h0), _common_fractOut_T, _common_fractOut_T_1) connect common_fractOut, _common_fractOut_T_2 connect common_overflow, UInt<1>(0h0) connect common_totalUnderflow, UInt<1>(0h0) node _unboundedRange_roundPosBit_T = bits(adjustedSig, 2, 2) node _unboundedRange_roundPosBit_T_1 = bits(adjustedSig, 1, 1) node unboundedRange_roundPosBit = mux(UInt<1>(0h0), _unboundedRange_roundPosBit_T, _unboundedRange_roundPosBit_T_1) node _unboundedRange_anyRound_T = bits(adjustedSig, 2, 2) node _unboundedRange_anyRound_T_1 = and(UInt<1>(0h0), _unboundedRange_anyRound_T) node _unboundedRange_anyRound_T_2 = bits(adjustedSig, 1, 0) node _unboundedRange_anyRound_T_3 = orr(_unboundedRange_anyRound_T_2) node unboundedRange_anyRound = or(_unboundedRange_anyRound_T_1, _unboundedRange_anyRound_T_3) node _unboundedRange_roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _unboundedRange_roundIncr_T_1 = and(_unboundedRange_roundIncr_T, unboundedRange_roundPosBit) node _unboundedRange_roundIncr_T_2 = and(roundMagUp, unboundedRange_anyRound) node unboundedRange_roundIncr = or(_unboundedRange_roundIncr_T_1, _unboundedRange_roundIncr_T_2) node _roundCarry_T = bits(roundedSig, 25, 25) node _roundCarry_T_1 = bits(roundedSig, 24, 24) node roundCarry = mux(UInt<1>(0h0), _roundCarry_T, _roundCarry_T_1) connect common_underflow, UInt<1>(0h0) node _common_inexact_T = or(common_totalUnderflow, anyRound) connect common_inexact, _common_inexact_T node isNaNOut = or(io.invalidExc, io.in.isNaN) node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf) node _commonCase_T = eq(isNaNOut, UInt<1>(0h0)) node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0)) node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1) node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0)) node commonCase = and(_commonCase_T_2, _commonCase_T_3) node overflow = and(commonCase, common_overflow) node underflow = and(commonCase, common_underflow) node _inexact_T = and(commonCase, common_inexact) node inexact = or(overflow, _inexact_T) node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag) node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp) node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow) node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd) node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1) node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0)) node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T) node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp) node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T) node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign) node _expOut_T = or(io.in.isZero, common_totalUnderflow) node _expOut_T_1 = mux(_expOut_T, UInt<9>(0h1c0), UInt<1>(0h0)) node _expOut_T_2 = not(_expOut_T_1) node _expOut_T_3 = and(common_expOut, _expOut_T_2) node _expOut_T_4 = not(UInt<9>(0h6b)) node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0)) node _expOut_T_6 = not(_expOut_T_5) node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6) node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<9>(0h80), UInt<1>(0h0)) node _expOut_T_9 = not(_expOut_T_8) node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9) node _expOut_T_11 = mux(notNaN_isInfOut, UInt<9>(0h40), UInt<1>(0h0)) node _expOut_T_12 = not(_expOut_T_11) node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12) node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<9>(0h6b), UInt<1>(0h0)) node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14) node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<9>(0h17f), UInt<1>(0h0)) node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16) node _expOut_T_18 = mux(notNaN_isInfOut, UInt<9>(0h180), UInt<1>(0h0)) node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18) node _expOut_T_20 = mux(isNaNOut, UInt<9>(0h1c0), UInt<1>(0h0)) node expOut = or(_expOut_T_19, _expOut_T_20) node _fractOut_T = or(isNaNOut, io.in.isZero) node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow) node _fractOut_T_2 = mux(isNaNOut, UInt<23>(0h400000), UInt<1>(0h0)) node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut) node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<23>(0h7fffff), UInt<23>(0h0)) node fractOut = or(_fractOut_T_3, _fractOut_T_4) node _io_out_T = cat(signOut, expOut) node _io_out_T_1 = cat(_io_out_T, fractOut) connect io.out, _io_out_T_1 node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc) node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow) node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact) connect io.exceptionFlags, _io_exceptionFlags_T_3	module RoundAnyRawFNToRecFN_ie7_is64_oe8_os24( // @[RoundAnyRawFNToRecFN.scala:48:5] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16] input [8:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16] input [64:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16] input [2:0] io_roundingMode, // @[RoundAnyRawFNToRecFN.scala:58:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16] ); wire roundingMode_near_even = io_roundingMode == 3'h0; // @[RoundAnyRawFNToRecFN.scala:90:53] wire [1:0] _GEN = {io_in_sig[39], \|(io_in_sig[38:0])}; // @[RoundAnyRawFNToRecFN.scala:116:66, :117:{26,60}, :164:56, :165:62, :166:36] wire [25:0] roundedSig = (roundingMode_near_even \| io_roundingMode == 3'h4) & io_in_sig[39] \| (io_roundingMode == 3'h2 & io_in_sign \| io_roundingMode == 3'h3 & ~io_in_sign) & (\|_GEN) ? {1'h0, io_in_sig[64:40]} + 26'h1 & {25'h1FFFFFF, ~(roundingMode_near_even & io_in_sig[39] & ~(\|(io_in_sig[38:0])))} : {1'h0, io_in_sig[64:41], io_in_sig[40] \| io_roundingMode == 3'h6 & (\|_GEN)}; // @[RoundAnyRawFNToRecFN.scala:90:53, :92:53, :93:53, :94:53, :95:53, :98:{27,42,63,66}, :106:31, :116:66, :117:{26,60}, :164:{40,56}, :165:62, :166:36, :169:{38,67}, :170:31, :171:29, :173:16, :174:{49,57}, :175:{21,25,49,64}, :176:30, :180:47, :181:42] assign io_out = {io_in_sign, io_in_sExp + {7'h0, roundedSig[25:24]} + 9'h80 & ~(io_in_isZero ? 9'h1C0 : 9'h0), io_in_isZero ? 23'h0 : roundedSig[22:0]}; // @[RoundAnyRawFNToRecFN.scala:48:5, :104:25, :173:16, :185:{40,54}, :191:27, :252:24, :253:{14,18}, :280:12, :281:16, :286:33] assign io_exceptionFlags = {4'h0, ~io_in_isZero & (\|_GEN)}; // @[RoundAnyRawFNToRecFN.scala:48:5, :164:56, :165:62, :166:36, :237:64, :240:43, :288:{53,66}] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MulRecFN_30 : output io : { flip a : UInt<33>, flip b : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} inst mulRawFN of MulRawFN_30 node mulRawFN_io_a_exp = bits(io.a, 31, 23) node _mulRawFN_io_a_isZero_T = bits(mulRawFN_io_a_exp, 8, 6) node mulRawFN_io_a_isZero = eq(_mulRawFN_io_a_isZero_T, UInt<1>(0h0)) node _mulRawFN_io_a_isSpecial_T = bits(mulRawFN_io_a_exp, 8, 7) node mulRawFN_io_a_isSpecial = eq(_mulRawFN_io_a_isSpecial_T, UInt<2>(0h3)) wire mulRawFN_io_a_out : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _mulRawFN_io_a_out_isNaN_T = bits(mulRawFN_io_a_exp, 6, 6) node _mulRawFN_io_a_out_isNaN_T_1 = and(mulRawFN_io_a_isSpecial, _mulRawFN_io_a_out_isNaN_T) connect mulRawFN_io_a_out.isNaN, _mulRawFN_io_a_out_isNaN_T_1 node _mulRawFN_io_a_out_isInf_T = bits(mulRawFN_io_a_exp, 6, 6) node _mulRawFN_io_a_out_isInf_T_1 = eq(_mulRawFN_io_a_out_isInf_T, UInt<1>(0h0)) node _mulRawFN_io_a_out_isInf_T_2 = and(mulRawFN_io_a_isSpecial, _mulRawFN_io_a_out_isInf_T_1) connect mulRawFN_io_a_out.isInf, _mulRawFN_io_a_out_isInf_T_2 connect mulRawFN_io_a_out.isZero, mulRawFN_io_a_isZero node _mulRawFN_io_a_out_sign_T = bits(io.a, 32, 32) connect mulRawFN_io_a_out.sign, _mulRawFN_io_a_out_sign_T node _mulRawFN_io_a_out_sExp_T = cvt(mulRawFN_io_a_exp) connect mulRawFN_io_a_out.sExp, _mulRawFN_io_a_out_sExp_T node _mulRawFN_io_a_out_sig_T = eq(mulRawFN_io_a_isZero, UInt<1>(0h0)) node _mulRawFN_io_a_out_sig_T_1 = cat(UInt<1>(0h0), _mulRawFN_io_a_out_sig_T) node _mulRawFN_io_a_out_sig_T_2 = bits(io.a, 22, 0) node _mulRawFN_io_a_out_sig_T_3 = cat(_mulRawFN_io_a_out_sig_T_1, _mulRawFN_io_a_out_sig_T_2) connect mulRawFN_io_a_out.sig, _mulRawFN_io_a_out_sig_T_3 connect mulRawFN.io.a.sig, mulRawFN_io_a_out.sig connect mulRawFN.io.a.sExp, mulRawFN_io_a_out.sExp connect mulRawFN.io.a.sign, mulRawFN_io_a_out.sign connect mulRawFN.io.a.isZero, mulRawFN_io_a_out.isZero connect mulRawFN.io.a.isInf, mulRawFN_io_a_out.isInf connect mulRawFN.io.a.isNaN, mulRawFN_io_a_out.isNaN node mulRawFN_io_b_exp = bits(io.b, 31, 23) node _mulRawFN_io_b_isZero_T = bits(mulRawFN_io_b_exp, 8, 6) node mulRawFN_io_b_isZero = eq(_mulRawFN_io_b_isZero_T, UInt<1>(0h0)) node _mulRawFN_io_b_isSpecial_T = bits(mulRawFN_io_b_exp, 8, 7) node mulRawFN_io_b_isSpecial = eq(_mulRawFN_io_b_isSpecial_T, UInt<2>(0h3)) wire mulRawFN_io_b_out : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _mulRawFN_io_b_out_isNaN_T = bits(mulRawFN_io_b_exp, 6, 6) node _mulRawFN_io_b_out_isNaN_T_1 = and(mulRawFN_io_b_isSpecial, _mulRawFN_io_b_out_isNaN_T) connect mulRawFN_io_b_out.isNaN, _mulRawFN_io_b_out_isNaN_T_1 node _mulRawFN_io_b_out_isInf_T = bits(mulRawFN_io_b_exp, 6, 6) node _mulRawFN_io_b_out_isInf_T_1 = eq(_mulRawFN_io_b_out_isInf_T, UInt<1>(0h0)) node _mulRawFN_io_b_out_isInf_T_2 = and(mulRawFN_io_b_isSpecial, _mulRawFN_io_b_out_isInf_T_1) connect mulRawFN_io_b_out.isInf, _mulRawFN_io_b_out_isInf_T_2 connect mulRawFN_io_b_out.isZero, mulRawFN_io_b_isZero node _mulRawFN_io_b_out_sign_T = bits(io.b, 32, 32) connect mulRawFN_io_b_out.sign, _mulRawFN_io_b_out_sign_T node _mulRawFN_io_b_out_sExp_T = cvt(mulRawFN_io_b_exp) connect mulRawFN_io_b_out.sExp, _mulRawFN_io_b_out_sExp_T node _mulRawFN_io_b_out_sig_T = eq(mulRawFN_io_b_isZero, UInt<1>(0h0)) node _mulRawFN_io_b_out_sig_T_1 = cat(UInt<1>(0h0), _mulRawFN_io_b_out_sig_T) node _mulRawFN_io_b_out_sig_T_2 = bits(io.b, 22, 0) node _mulRawFN_io_b_out_sig_T_3 = cat(_mulRawFN_io_b_out_sig_T_1, _mulRawFN_io_b_out_sig_T_2) connect mulRawFN_io_b_out.sig, _mulRawFN_io_b_out_sig_T_3 connect mulRawFN.io.b.sig, mulRawFN_io_b_out.sig connect mulRawFN.io.b.sExp, mulRawFN_io_b_out.sExp connect mulRawFN.io.b.sign, mulRawFN_io_b_out.sign connect mulRawFN.io.b.isZero, mulRawFN_io_b_out.isZero connect mulRawFN.io.b.isInf, mulRawFN_io_b_out.isInf connect mulRawFN.io.b.isNaN, mulRawFN_io_b_out.isNaN inst roundRawFNToRecFN of RoundRawFNToRecFN_e8_s24_98 connect roundRawFNToRecFN.io.invalidExc, mulRawFN.io.invalidExc connect roundRawFNToRecFN.io.infiniteExc, UInt<1>(0h0) connect roundRawFNToRecFN.io.in.sig, mulRawFN.io.rawOut.sig connect roundRawFNToRecFN.io.in.sExp, mulRawFN.io.rawOut.sExp connect roundRawFNToRecFN.io.in.sign, mulRawFN.io.rawOut.sign connect roundRawFNToRecFN.io.in.isZero, mulRawFN.io.rawOut.isZero connect roundRawFNToRecFN.io.in.isInf, mulRawFN.io.rawOut.isInf connect roundRawFNToRecFN.io.in.isNaN, mulRawFN.io.rawOut.isNaN connect roundRawFNToRecFN.io.roundingMode, io.roundingMode connect roundRawFNToRecFN.io.detectTininess, io.detectTininess connect io.out, roundRawFNToRecFN.io.out connect io.exceptionFlags, roundRawFNToRecFN.io.exceptionFlags	module MulRecFN_30( // @[MulRecFN.scala:100:7] input [32:0] io_a, // @[MulRecFN.scala:102:16] input [32:0] io_b, // @[MulRecFN.scala:102:16] output [32:0] io_out // @[MulRecFN.scala:102:16] ); wire _mulRawFN_io_invalidExc; // @[MulRecFN.scala:113:26] wire _mulRawFN_io_rawOut_isNaN; // @[MulRecFN.scala:113:26] wire _mulRawFN_io_rawOut_isInf; // @[MulRecFN.scala:113:26] wire _mulRawFN_io_rawOut_isZero; // @[MulRecFN.scala:113:26] wire _mulRawFN_io_rawOut_sign; // @[MulRecFN.scala:113:26] wire [9:0] _mulRawFN_io_rawOut_sExp; // @[MulRecFN.scala:113:26] wire [26:0] _mulRawFN_io_rawOut_sig; // @[MulRecFN.scala:113:26] wire [32:0] io_a_0 = io_a; // @[MulRecFN.scala:100:7] wire [32:0] io_b_0 = io_b; // @[MulRecFN.scala:100:7] wire io_detectTininess = 1'h1; // @[MulRecFN.scala:100:7, :102:16, :121:15] wire [2:0] io_roundingMode = 3'h0; // @[MulRecFN.scala:100:7, :102:16, :121:15] wire [32:0] io_out_0; // @[MulRecFN.scala:100:7] wire [4:0] io_exceptionFlags; // @[MulRecFN.scala:100:7] wire [8:0] mulRawFN_io_a_exp = io_a_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _mulRawFN_io_a_isZero_T = mulRawFN_io_a_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire mulRawFN_io_a_isZero = _mulRawFN_io_a_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire mulRawFN_io_a_out_isZero = mulRawFN_io_a_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _mulRawFN_io_a_isSpecial_T = mulRawFN_io_a_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire mulRawFN_io_a_isSpecial = &_mulRawFN_io_a_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _mulRawFN_io_a_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _mulRawFN_io_a_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _mulRawFN_io_a_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _mulRawFN_io_a_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _mulRawFN_io_a_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire mulRawFN_io_a_out_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire mulRawFN_io_a_out_isInf; // @[rawFloatFromRecFN.scala:55:23] wire mulRawFN_io_a_out_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] mulRawFN_io_a_out_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] mulRawFN_io_a_out_sig; // @[rawFloatFromRecFN.scala:55:23] wire _mulRawFN_io_a_out_isNaN_T = mulRawFN_io_a_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _mulRawFN_io_a_out_isInf_T = mulRawFN_io_a_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _mulRawFN_io_a_out_isNaN_T_1 = mulRawFN_io_a_isSpecial & _mulRawFN_io_a_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign mulRawFN_io_a_out_isNaN = _mulRawFN_io_a_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _mulRawFN_io_a_out_isInf_T_1 = ~_mulRawFN_io_a_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _mulRawFN_io_a_out_isInf_T_2 = mulRawFN_io_a_isSpecial & _mulRawFN_io_a_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign mulRawFN_io_a_out_isInf = _mulRawFN_io_a_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _mulRawFN_io_a_out_sign_T = io_a_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign mulRawFN_io_a_out_sign = _mulRawFN_io_a_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _mulRawFN_io_a_out_sExp_T = {1'h0, mulRawFN_io_a_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign mulRawFN_io_a_out_sExp = _mulRawFN_io_a_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _mulRawFN_io_a_out_sig_T = ~mulRawFN_io_a_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _mulRawFN_io_a_out_sig_T_1 = {1'h0, _mulRawFN_io_a_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _mulRawFN_io_a_out_sig_T_2 = io_a_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _mulRawFN_io_a_out_sig_T_3 = {_mulRawFN_io_a_out_sig_T_1, _mulRawFN_io_a_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign mulRawFN_io_a_out_sig = _mulRawFN_io_a_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [8:0] mulRawFN_io_b_exp = io_b_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _mulRawFN_io_b_isZero_T = mulRawFN_io_b_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire mulRawFN_io_b_isZero = _mulRawFN_io_b_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire mulRawFN_io_b_out_isZero = mulRawFN_io_b_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _mulRawFN_io_b_isSpecial_T = mulRawFN_io_b_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire mulRawFN_io_b_isSpecial = &_mulRawFN_io_b_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _mulRawFN_io_b_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _mulRawFN_io_b_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _mulRawFN_io_b_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _mulRawFN_io_b_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _mulRawFN_io_b_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire mulRawFN_io_b_out_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire mulRawFN_io_b_out_isInf; // @[rawFloatFromRecFN.scala:55:23] wire mulRawFN_io_b_out_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] mulRawFN_io_b_out_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] mulRawFN_io_b_out_sig; // @[rawFloatFromRecFN.scala:55:23] wire _mulRawFN_io_b_out_isNaN_T = mulRawFN_io_b_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _mulRawFN_io_b_out_isInf_T = mulRawFN_io_b_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _mulRawFN_io_b_out_isNaN_T_1 = mulRawFN_io_b_isSpecial & _mulRawFN_io_b_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign mulRawFN_io_b_out_isNaN = _mulRawFN_io_b_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _mulRawFN_io_b_out_isInf_T_1 = ~_mulRawFN_io_b_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _mulRawFN_io_b_out_isInf_T_2 = mulRawFN_io_b_isSpecial & _mulRawFN_io_b_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign mulRawFN_io_b_out_isInf = _mulRawFN_io_b_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _mulRawFN_io_b_out_sign_T = io_b_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign mulRawFN_io_b_out_sign = _mulRawFN_io_b_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _mulRawFN_io_b_out_sExp_T = {1'h0, mulRawFN_io_b_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign mulRawFN_io_b_out_sExp = _mulRawFN_io_b_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _mulRawFN_io_b_out_sig_T = ~mulRawFN_io_b_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _mulRawFN_io_b_out_sig_T_1 = {1'h0, _mulRawFN_io_b_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _mulRawFN_io_b_out_sig_T_2 = io_b_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _mulRawFN_io_b_out_sig_T_3 = {_mulRawFN_io_b_out_sig_T_1, _mulRawFN_io_b_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign mulRawFN_io_b_out_sig = _mulRawFN_io_b_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] MulRawFN_30 mulRawFN ( // @[MulRecFN.scala:113:26] .io_a_isNaN (mulRawFN_io_a_out_isNaN), // @[rawFloatFromRecFN.scala:55:23] .io_a_isInf (mulRawFN_io_a_out_isInf), // @[rawFloatFromRecFN.scala:55:23] .io_a_isZero (mulRawFN_io_a_out_isZero), // @[rawFloatFromRecFN.scala:55:23] .io_a_sign (mulRawFN_io_a_out_sign), // @[rawFloatFromRecFN.scala:55:23] .io_a_sExp (mulRawFN_io_a_out_sExp), // @[rawFloatFromRecFN.scala:55:23] .io_a_sig (mulRawFN_io_a_out_sig), // @[rawFloatFromRecFN.scala:55:23] .io_b_isNaN (mulRawFN_io_b_out_isNaN), // @[rawFloatFromRecFN.scala:55:23] .io_b_isInf (mulRawFN_io_b_out_isInf), // @[rawFloatFromRecFN.scala:55:23] .io_b_isZero (mulRawFN_io_b_out_isZero), // @[rawFloatFromRecFN.scala:55:23] .io_b_sign (mulRawFN_io_b_out_sign), // @[rawFloatFromRecFN.scala:55:23] .io_b_sExp (mulRawFN_io_b_out_sExp), // @[rawFloatFromRecFN.scala:55:23] .io_b_sig (mulRawFN_io_b_out_sig), // @[rawFloatFromRecFN.scala:55:23] .io_invalidExc (_mulRawFN_io_invalidExc), .io_rawOut_isNaN (_mulRawFN_io_rawOut_isNaN), .io_rawOut_isInf (_mulRawFN_io_rawOut_isInf), .io_rawOut_isZero (_mulRawFN_io_rawOut_isZero), .io_rawOut_sign (_mulRawFN_io_rawOut_sign), .io_rawOut_sExp (_mulRawFN_io_rawOut_sExp), .io_rawOut_sig (_mulRawFN_io_rawOut_sig) ); // @[MulRecFN.scala:113:26] RoundRawFNToRecFN_e8_s24_98 roundRawFNToRecFN ( // @[MulRecFN.scala:121:15] .io_invalidExc (_mulRawFN_io_invalidExc), // @[MulRecFN.scala:113:26] .io_in_isNaN (_mulRawFN_io_rawOut_isNaN), // @[MulRecFN.scala:113:26] .io_in_isInf (_mulRawFN_io_rawOut_isInf), // @[MulRecFN.scala:113:26] .io_in_isZero (_mulRawFN_io_rawOut_isZero), // @[MulRecFN.scala:113:26] .io_in_sign (_mulRawFN_io_rawOut_sign), // @[MulRecFN.scala:113:26] .io_in_sExp (_mulRawFN_io_rawOut_sExp), // @[MulRecFN.scala:113:26] .io_in_sig (_mulRawFN_io_rawOut_sig), // @[MulRecFN.scala:113:26] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags) ); // @[MulRecFN.scala:121:15] assign io_out = io_out_0; // @[MulRecFN.scala:100:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module L2MemHelperLatencyInjection_13 : input clock : Clock input reset : Reset output auto : { master_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}}} output io : { flip userif : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt, size : UInt, data : UInt<256>, cmd : UInt}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<256>}}, flip no_memops_inflight : UInt<1>}, flip latency_inject_cycles : UInt<64>, flip sfence : UInt<1>, ptw : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { valid : UInt<1>, bits : { addr : UInt<27>, need_gpa : UInt<1>, vstage1 : UInt<1>, stage2 : UInt<1>}}}, flip resp : { valid : UInt<1>, bits : { ae_ptw : UInt<1>, ae_final : UInt<1>, pf : UInt<1>, gf : UInt<1>, hr : UInt<1>, hw : UInt<1>, hx : UInt<1>, pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, level : UInt<2>, fragmented_superpage : UInt<1>, homogeneous : UInt<1>, gpa : { valid : UInt<1>, bits : UInt<39>}, gpa_is_pte : UInt<1>}}, flip ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, flip gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], flip customCSRs : { csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[4]}}, flip status : { valid : UInt<1>, bits : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}} wire masterNodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}} invalidate masterNodeOut.d.bits.corrupt invalidate masterNodeOut.d.bits.data invalidate masterNodeOut.d.bits.denied invalidate masterNodeOut.d.bits.sink invalidate masterNodeOut.d.bits.source invalidate masterNodeOut.d.bits.size invalidate masterNodeOut.d.bits.param invalidate masterNodeOut.d.bits.opcode invalidate masterNodeOut.d.valid invalidate masterNodeOut.d.ready invalidate masterNodeOut.a.bits.corrupt invalidate masterNodeOut.a.bits.data invalidate masterNodeOut.a.bits.mask invalidate masterNodeOut.a.bits.address invalidate masterNodeOut.a.bits.source invalidate masterNodeOut.a.bits.size invalidate masterNodeOut.a.bits.param invalidate masterNodeOut.a.bits.opcode invalidate masterNodeOut.a.valid invalidate masterNodeOut.a.ready connect auto.master_out, masterNodeOut wire request_input : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt, size : UInt, data : UInt<256>, cmd : UInt}} connect request_input, io.userif.req wire response_output : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<256>}} connect io.userif.resp, response_output reg status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, clock when io.status.valid : regreset loginfo_cycles : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T = add(loginfo_cycles, UInt<1>(0h1)) node _loginfo_cycles_T_1 = tail(_loginfo_cycles_T, 1) connect loginfo_cycles, _loginfo_cycles_T_1 node _T = asUInt(reset) node _T_1 = eq(_T, UInt<1>(0h0)) when _T_1 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles) : printf node _T_2 = asUInt(reset) node _T_3 = eq(_T_2, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "[seq_writer] setting status.dprv to: %x compare %x\n", io.status.bits.dprv, UInt<2>(0h3)) : printf_1 connect status, io.status.bits inst tlb of DTLB_15 connect tlb.clock, clock connect tlb.reset, reset connect tlb.io.req.valid, request_input.valid connect tlb.io.req.bits.vaddr, request_input.bits.addr connect tlb.io.req.bits.size, request_input.bits.size connect tlb.io.req.bits.cmd, request_input.bits.cmd connect tlb.io.req.bits.passthrough, UInt<1>(0h0) node _tlb_ready_T = eq(tlb.io.resp.miss, UInt<1>(0h0)) node tlb_ready = and(tlb.io.req.ready, _tlb_ready_T) invalidate tlb.io.req.bits.prv invalidate tlb.io.req.bits.v invalidate tlb.io.sfence.bits.hv invalidate tlb.io.sfence.bits.hg connect tlb.io.ptw.customCSRs, io.ptw.customCSRs connect tlb.io.ptw.pmp[0], io.ptw.pmp[0] connect tlb.io.ptw.pmp[1], io.ptw.pmp[1] connect tlb.io.ptw.pmp[2], io.ptw.pmp[2] connect tlb.io.ptw.pmp[3], io.ptw.pmp[3] connect tlb.io.ptw.pmp[4], io.ptw.pmp[4] connect tlb.io.ptw.pmp[5], io.ptw.pmp[5] connect tlb.io.ptw.pmp[6], io.ptw.pmp[6] connect tlb.io.ptw.pmp[7], io.ptw.pmp[7] connect tlb.io.ptw.gstatus, io.ptw.gstatus connect tlb.io.ptw.hstatus, io.ptw.hstatus connect tlb.io.ptw.status, io.ptw.status connect tlb.io.ptw.vsatp, io.ptw.vsatp connect tlb.io.ptw.hgatp, io.ptw.hgatp connect tlb.io.ptw.ptbr, io.ptw.ptbr connect tlb.io.ptw.resp, io.ptw.resp connect io.ptw.req.bits, tlb.io.ptw.req.bits connect io.ptw.req.valid, tlb.io.ptw.req.valid connect tlb.io.ptw.req.ready, io.ptw.req.ready connect tlb.io.ptw.status.uie, status.uie connect tlb.io.ptw.status.sie, status.sie connect tlb.io.ptw.status.hie, status.hie connect tlb.io.ptw.status.mie, status.mie connect tlb.io.ptw.status.upie, status.upie connect tlb.io.ptw.status.spie, status.spie connect tlb.io.ptw.status.ube, status.ube connect tlb.io.ptw.status.mpie, status.mpie connect tlb.io.ptw.status.spp, status.spp connect tlb.io.ptw.status.vs, status.vs connect tlb.io.ptw.status.mpp, status.mpp connect tlb.io.ptw.status.fs, status.fs connect tlb.io.ptw.status.xs, status.xs connect tlb.io.ptw.status.mprv, status.mprv connect tlb.io.ptw.status.sum, status.sum connect tlb.io.ptw.status.mxr, status.mxr connect tlb.io.ptw.status.tvm, status.tvm connect tlb.io.ptw.status.tw, status.tw connect tlb.io.ptw.status.tsr, status.tsr connect tlb.io.ptw.status.zero1, status.zero1 connect tlb.io.ptw.status.sd_rv32, status.sd_rv32 connect tlb.io.ptw.status.uxl, status.uxl connect tlb.io.ptw.status.sxl, status.sxl connect tlb.io.ptw.status.sbe, status.sbe connect tlb.io.ptw.status.mbe, status.mbe connect tlb.io.ptw.status.gva, status.gva connect tlb.io.ptw.status.mpv, status.mpv connect tlb.io.ptw.status.zero2, status.zero2 connect tlb.io.ptw.status.sd, status.sd connect tlb.io.ptw.status.v, status.v connect tlb.io.ptw.status.prv, status.prv connect tlb.io.ptw.status.dv, status.dv connect tlb.io.ptw.status.dprv, status.dprv connect tlb.io.ptw.status.isa, status.isa connect tlb.io.ptw.status.wfi, status.wfi connect tlb.io.ptw.status.cease, status.cease connect tlb.io.ptw.status.debug, status.debug connect tlb.io.sfence.valid, io.sfence connect tlb.io.sfence.bits.rs1, UInt<1>(0h0) connect tlb.io.sfence.bits.rs2, UInt<1>(0h0) connect tlb.io.sfence.bits.addr, UInt<1>(0h0) connect tlb.io.sfence.bits.asid, UInt<1>(0h0) connect tlb.io.kill, UInt<1>(0h0) inst outstanding_req_addr of Queue128_L2InternalTracking_9 connect outstanding_req_addr.clock, clock connect outstanding_req_addr.reset, reset inst tags_for_issue_Q of Queue64_UInt5_9 connect tags_for_issue_Q.clock, clock connect tags_for_issue_Q.reset, reset connect tags_for_issue_Q.io.enq.valid, UInt<1>(0h0) invalidate tags_for_issue_Q.io.enq.bits regreset tags_init_reg : UInt<6>, clock, reset, UInt<6>(0h0) node _T_4 = neq(tags_init_reg, UInt<6>(0h20)) when _T_4 : connect tags_for_issue_Q.io.enq.bits, tags_init_reg connect tags_for_issue_Q.io.enq.valid, UInt<1>(0h1) when tags_for_issue_Q.io.enq.ready : regreset loginfo_cycles_1 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_2 = add(loginfo_cycles_1, UInt<1>(0h1)) node _loginfo_cycles_T_3 = tail(_loginfo_cycles_T_2, 1) connect loginfo_cycles_1, _loginfo_cycles_T_3 node _T_5 = asUInt(reset) node _T_6 = eq(_T_5, UInt<1>(0h0)) when _T_6 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_1) : printf_2 node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : printf(clock, UInt<1>(0h1), "[seq_writer] tags_for_issue_Q init with value %d\n", tags_for_issue_Q.io.enq.bits) : printf_3 node _tags_init_reg_T = add(tags_init_reg, UInt<1>(0h1)) node _tags_init_reg_T_1 = tail(_tags_init_reg_T, 1) connect tags_init_reg, _tags_init_reg_T_1 node _addr_mask_check_T = dshl(UInt<64>(0h1), request_input.bits.size) node _addr_mask_check_T_1 = sub(_addr_mask_check_T, UInt<1>(0h1)) node addr_mask_check = tail(_addr_mask_check_T_1, 1) node _assertcheck_T = eq(request_input.valid, UInt<1>(0h0)) node _assertcheck_T_1 = and(request_input.bits.addr, addr_mask_check) node _assertcheck_T_2 = eq(_assertcheck_T_1, UInt<1>(0h0)) node _assertcheck_T_3 = or(_assertcheck_T, _assertcheck_T_2) reg assertcheck : UInt<1>, clock connect assertcheck, _assertcheck_T_3 node _T_9 = eq(assertcheck, UInt<1>(0h0)) when _T_9 : regreset loginfo_cycles_2 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_4 = add(loginfo_cycles_2, UInt<1>(0h1)) node _loginfo_cycles_T_5 = tail(_loginfo_cycles_T_4, 1) connect loginfo_cycles_2, _loginfo_cycles_T_5 node _T_10 = asUInt(reset) node _T_11 = eq(_T_10, UInt<1>(0h0)) when _T_11 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_2) : printf_4 node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : printf(clock, UInt<1>(0h1), "[seq_writer] L2IF: access addr must be aligned to write width\n") : printf_5 node _T_14 = asUInt(reset) node _T_15 = eq(_T_14, UInt<1>(0h0)) when _T_15 : node _T_16 = eq(assertcheck, UInt<1>(0h0)) when _T_16 : printf(clock, UInt<1>(0h1), "Assertion failed: [seq_writer] L2IF: access addr must be aligned to write width\n\n at L2MemHelperLatencyInjection.scala:114 assert(assertcheck,\n") : printf_6 assert(clock, assertcheck, UInt<1>(0h1), "") : assert regreset global_memop_accepted : UInt<64>, clock, reset, UInt<64>(0h0) node _T_17 = and(io.userif.req.ready, io.userif.req.valid) when _T_17 : node _global_memop_accepted_T = add(global_memop_accepted, UInt<1>(0h1)) node _global_memop_accepted_T_1 = tail(_global_memop_accepted_T, 1) connect global_memop_accepted, _global_memop_accepted_T_1 regreset global_memop_sent : UInt<64>, clock, reset, UInt<64>(0h0) regreset global_memop_ackd : UInt<64>, clock, reset, UInt<64>(0h0) regreset global_memop_resp_to_user : UInt<64>, clock, reset, UInt<64>(0h0) node _io_userif_no_memops_inflight_T = eq(global_memop_accepted, global_memop_ackd) connect io.userif.no_memops_inflight, _io_userif_no_memops_inflight_T node _free_outstanding_op_slots_T = sub(global_memop_sent, global_memop_ackd) node _free_outstanding_op_slots_T_1 = tail(_free_outstanding_op_slots_T, 1) node free_outstanding_op_slots = lt(_free_outstanding_op_slots_T_1, UInt<6>(0h20)) node _assert_free_outstanding_op_slots_T = sub(global_memop_sent, global_memop_ackd) node _assert_free_outstanding_op_slots_T_1 = tail(_assert_free_outstanding_op_slots_T, 1) node assert_free_outstanding_op_slots = leq(_assert_free_outstanding_op_slots_T_1, UInt<6>(0h20)) node _T_18 = eq(assert_free_outstanding_op_slots, UInt<1>(0h0)) when _T_18 : regreset loginfo_cycles_3 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_6 = add(loginfo_cycles_3, UInt<1>(0h1)) node _loginfo_cycles_T_7 = tail(_loginfo_cycles_T_6, 1) connect loginfo_cycles_3, _loginfo_cycles_T_7 node _T_19 = asUInt(reset) node _T_20 = eq(_T_19, UInt<1>(0h0)) when _T_20 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_3) : printf_7 node _T_21 = asUInt(reset) node _T_22 = eq(_T_21, UInt<1>(0h0)) when _T_22 : printf(clock, UInt<1>(0h1), "[seq_writer] L2IF: Too many outstanding requests for tag count.\n") : printf_8 node _T_23 = asUInt(reset) node _T_24 = eq(_T_23, UInt<1>(0h0)) when _T_24 : node _T_25 = eq(assert_free_outstanding_op_slots, UInt<1>(0h0)) when _T_25 : printf(clock, UInt<1>(0h1), "Assertion failed: [seq_writer] L2IF: Too many outstanding requests for tag count.\n\n at L2MemHelperLatencyInjection.scala:136 assert(assert_free_outstanding_op_slots,\n") : printf_9 assert(clock, assert_free_outstanding_op_slots, UInt<1>(0h1), "") : assert_1 node _T_26 = and(request_input.ready, request_input.valid) when _T_26 : node _global_memop_sent_T = add(global_memop_sent, UInt<1>(0h1)) node _global_memop_sent_T_1 = tail(_global_memop_sent_T, 1) connect global_memop_sent, _global_memop_sent_T_1 regreset cur_cycle : UInt<64>, clock, reset, UInt<64>(0h0) node _cur_cycle_T = add(cur_cycle, UInt<1>(0h1)) node _cur_cycle_T_1 = tail(_cur_cycle_T, 1) connect cur_cycle, _cur_cycle_T_1 inst request_latency_injection_q of LatencyInjectionQueue_26 connect request_latency_injection_q.clock, clock connect request_latency_injection_q.reset, reset connect request_latency_injection_q.io.latency_cycles, io.latency_inject_cycles invalidate request_latency_injection_q.io.enq.bits.corrupt invalidate request_latency_injection_q.io.enq.bits.data invalidate request_latency_injection_q.io.enq.bits.mask invalidate request_latency_injection_q.io.enq.bits.address invalidate request_latency_injection_q.io.enq.bits.source invalidate request_latency_injection_q.io.enq.bits.size invalidate request_latency_injection_q.io.enq.bits.param invalidate request_latency_injection_q.io.enq.bits.opcode node _T_27 = eq(request_input.bits.cmd, UInt<1>(0h0)) when _T_27 : node _legal_T = leq(UInt<1>(0h0), request_input.bits.size) node _legal_T_1 = leq(request_input.bits.size, UInt<4>(0hc)) node _legal_T_2 = and(_legal_T, _legal_T_1) node _legal_T_3 = or(UInt<1>(0h0), _legal_T_2) node _legal_T_4 = xor(tlb.io.resp.paddr, UInt<14>(0h3000)) node _legal_T_5 = cvt(_legal_T_4) node _legal_T_6 = and(_legal_T_5, asSInt(UInt<33>(0h9a013000))) node _legal_T_7 = asSInt(_legal_T_6) node _legal_T_8 = eq(_legal_T_7, asSInt(UInt<1>(0h0))) node _legal_T_9 = and(_legal_T_3, _legal_T_8) node _legal_T_10 = leq(UInt<1>(0h0), request_input.bits.size) node _legal_T_11 = leq(request_input.bits.size, UInt<3>(0h6)) node _legal_T_12 = and(_legal_T_10, _legal_T_11) node _legal_T_13 = or(UInt<1>(0h0), _legal_T_12) node _legal_T_14 = xor(tlb.io.resp.paddr, UInt<1>(0h0)) node _legal_T_15 = cvt(_legal_T_14) node _legal_T_16 = and(_legal_T_15, asSInt(UInt<33>(0h9a012000))) node _legal_T_17 = asSInt(_legal_T_16) node _legal_T_18 = eq(_legal_T_17, asSInt(UInt<1>(0h0))) node _legal_T_19 = xor(tlb.io.resp.paddr, UInt<17>(0h10000)) node _legal_T_20 = cvt(_legal_T_19) node _legal_T_21 = and(_legal_T_20, asSInt(UInt<33>(0h98013000))) node _legal_T_22 = asSInt(_legal_T_21) node _legal_T_23 = eq(_legal_T_22, asSInt(UInt<1>(0h0))) node _legal_T_24 = xor(tlb.io.resp.paddr, UInt<17>(0h10000)) node _legal_T_25 = cvt(_legal_T_24) node _legal_T_26 = and(_legal_T_25, asSInt(UInt<33>(0h9a010000))) node _legal_T_27 = asSInt(_legal_T_26) node _legal_T_28 = eq(_legal_T_27, asSInt(UInt<1>(0h0))) node _legal_T_29 = xor(tlb.io.resp.paddr, UInt<26>(0h2000000)) node _legal_T_30 = cvt(_legal_T_29) node _legal_T_31 = and(_legal_T_30, asSInt(UInt<33>(0h9a010000))) node _legal_T_32 = asSInt(_legal_T_31) node _legal_T_33 = eq(_legal_T_32, asSInt(UInt<1>(0h0))) node _legal_T_34 = xor(tlb.io.resp.paddr, UInt<28>(0h8000000)) node _legal_T_35 = cvt(_legal_T_34) node _legal_T_36 = and(_legal_T_35, asSInt(UInt<33>(0h98000000))) node _legal_T_37 = asSInt(_legal_T_36) node _legal_T_38 = eq(_legal_T_37, asSInt(UInt<1>(0h0))) node _legal_T_39 = xor(tlb.io.resp.paddr, UInt<28>(0h8000000)) node _legal_T_40 = cvt(_legal_T_39) node _legal_T_41 = and(_legal_T_40, asSInt(UInt<33>(0h9a010000))) node _legal_T_42 = asSInt(_legal_T_41) node _legal_T_43 = eq(_legal_T_42, asSInt(UInt<1>(0h0))) node _legal_T_44 = xor(tlb.io.resp.paddr, UInt<29>(0h10000000)) node _legal_T_45 = cvt(_legal_T_44) node _legal_T_46 = and(_legal_T_45, asSInt(UInt<33>(0h9a013000))) node _legal_T_47 = asSInt(_legal_T_46) node _legal_T_48 = eq(_legal_T_47, asSInt(UInt<1>(0h0))) node _legal_T_49 = xor(tlb.io.resp.paddr, UInt<32>(0h80000000)) node _legal_T_50 = cvt(_legal_T_49) node _legal_T_51 = and(_legal_T_50, asSInt(UInt<33>(0h90000000))) node _legal_T_52 = asSInt(_legal_T_51) node _legal_T_53 = eq(_legal_T_52, asSInt(UInt<1>(0h0))) node _legal_T_54 = or(_legal_T_18, _legal_T_23) node _legal_T_55 = or(_legal_T_54, _legal_T_28) node _legal_T_56 = or(_legal_T_55, _legal_T_33) node _legal_T_57 = or(_legal_T_56, _legal_T_38) node _legal_T_58 = or(_legal_T_57, _legal_T_43) node _legal_T_59 = or(_legal_T_58, _legal_T_48) node _legal_T_60 = or(_legal_T_59, _legal_T_53) node _legal_T_61 = and(_legal_T_13, _legal_T_60) node _legal_T_62 = or(UInt<1>(0h0), _legal_T_9) node legal = or(_legal_T_62, _legal_T_61) wire bundle : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>} connect bundle.opcode, UInt<3>(0h4) connect bundle.param, UInt<1>(0h0) connect bundle.size, request_input.bits.size connect bundle.source, tags_for_issue_Q.io.deq.bits connect bundle.address, tlb.io.resp.paddr node _a_mask_sizeOH_T = or(request_input.bits.size, UInt<5>(0h0)) node _a_mask_sizeOH_shiftAmount_T = pad(_a_mask_sizeOH_T, 3) node a_mask_sizeOH_shiftAmount = bits(_a_mask_sizeOH_shiftAmount_T, 2, 0) node _a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), a_mask_sizeOH_shiftAmount) node _a_mask_sizeOH_T_2 = bits(_a_mask_sizeOH_T_1, 4, 0) node a_mask_sizeOH = or(_a_mask_sizeOH_T_2, UInt<1>(0h1)) node a_mask_sub_sub_sub_sub_sub_0_1 = geq(request_input.bits.size, UInt<3>(0h5)) node a_mask_sub_sub_sub_sub_size = bits(a_mask_sizeOH, 4, 4) node a_mask_sub_sub_sub_sub_bit = bits(tlb.io.resp.paddr, 4, 4) node a_mask_sub_sub_sub_sub_nbit = eq(a_mask_sub_sub_sub_sub_bit, UInt<1>(0h0)) node a_mask_sub_sub_sub_sub_0_2 = and(UInt<1>(0h1), a_mask_sub_sub_sub_sub_nbit) node _a_mask_sub_sub_sub_sub_acc_T = and(a_mask_sub_sub_sub_sub_size, a_mask_sub_sub_sub_sub_0_2) node a_mask_sub_sub_sub_sub_0_1 = or(a_mask_sub_sub_sub_sub_sub_0_1, _a_mask_sub_sub_sub_sub_acc_T) node a_mask_sub_sub_sub_sub_1_2 = and(UInt<1>(0h1), a_mask_sub_sub_sub_sub_bit) node _a_mask_sub_sub_sub_sub_acc_T_1 = and(a_mask_sub_sub_sub_sub_size, a_mask_sub_sub_sub_sub_1_2) node a_mask_sub_sub_sub_sub_1_1 = or(a_mask_sub_sub_sub_sub_sub_0_1, _a_mask_sub_sub_sub_sub_acc_T_1) node a_mask_sub_sub_sub_size = bits(a_mask_sizeOH, 3, 3) node a_mask_sub_sub_sub_bit = bits(tlb.io.resp.paddr, 3, 3) node a_mask_sub_sub_sub_nbit = eq(a_mask_sub_sub_sub_bit, UInt<1>(0h0)) node a_mask_sub_sub_sub_0_2 = and(a_mask_sub_sub_sub_sub_0_2, a_mask_sub_sub_sub_nbit) node _a_mask_sub_sub_sub_acc_T = and(a_mask_sub_sub_sub_size, a_mask_sub_sub_sub_0_2) node a_mask_sub_sub_sub_0_1 = or(a_mask_sub_sub_sub_sub_0_1, _a_mask_sub_sub_sub_acc_T) node a_mask_sub_sub_sub_1_2 = and(a_mask_sub_sub_sub_sub_0_2, a_mask_sub_sub_sub_bit) node _a_mask_sub_sub_sub_acc_T_1 = and(a_mask_sub_sub_sub_size, a_mask_sub_sub_sub_1_2) node a_mask_sub_sub_sub_1_1 = or(a_mask_sub_sub_sub_sub_0_1, _a_mask_sub_sub_sub_acc_T_1) node a_mask_sub_sub_sub_2_2 = and(a_mask_sub_sub_sub_sub_1_2, a_mask_sub_sub_sub_nbit) node _a_mask_sub_sub_sub_acc_T_2 = and(a_mask_sub_sub_sub_size, a_mask_sub_sub_sub_2_2) node a_mask_sub_sub_sub_2_1 = or(a_mask_sub_sub_sub_sub_1_1, _a_mask_sub_sub_sub_acc_T_2) node a_mask_sub_sub_sub_3_2 = and(a_mask_sub_sub_sub_sub_1_2, a_mask_sub_sub_sub_bit) node _a_mask_sub_sub_sub_acc_T_3 = and(a_mask_sub_sub_sub_size, a_mask_sub_sub_sub_3_2) node a_mask_sub_sub_sub_3_1 = or(a_mask_sub_sub_sub_sub_1_1, _a_mask_sub_sub_sub_acc_T_3) node a_mask_sub_sub_size = bits(a_mask_sizeOH, 2, 2) node a_mask_sub_sub_bit = bits(tlb.io.resp.paddr, 2, 2) node a_mask_sub_sub_nbit = eq(a_mask_sub_sub_bit, UInt<1>(0h0)) node a_mask_sub_sub_0_2 = and(a_mask_sub_sub_sub_0_2, a_mask_sub_sub_nbit) node _a_mask_sub_sub_acc_T = and(a_mask_sub_sub_size, a_mask_sub_sub_0_2) node a_mask_sub_sub_0_1 = or(a_mask_sub_sub_sub_0_1, _a_mask_sub_sub_acc_T) node a_mask_sub_sub_1_2 = and(a_mask_sub_sub_sub_0_2, a_mask_sub_sub_bit) node _a_mask_sub_sub_acc_T_1 = and(a_mask_sub_sub_size, a_mask_sub_sub_1_2) node a_mask_sub_sub_1_1 = or(a_mask_sub_sub_sub_0_1, _a_mask_sub_sub_acc_T_1) node a_mask_sub_sub_2_2 = and(a_mask_sub_sub_sub_1_2, a_mask_sub_sub_nbit) node _a_mask_sub_sub_acc_T_2 = and(a_mask_sub_sub_size, a_mask_sub_sub_2_2) node a_mask_sub_sub_2_1 = or(a_mask_sub_sub_sub_1_1, _a_mask_sub_sub_acc_T_2) node a_mask_sub_sub_3_2 = and(a_mask_sub_sub_sub_1_2, a_mask_sub_sub_bit) node _a_mask_sub_sub_acc_T_3 = and(a_mask_sub_sub_size, a_mask_sub_sub_3_2) node a_mask_sub_sub_3_1 = or(a_mask_sub_sub_sub_1_1, _a_mask_sub_sub_acc_T_3) node a_mask_sub_sub_4_2 = and(a_mask_sub_sub_sub_2_2, a_mask_sub_sub_nbit) node _a_mask_sub_sub_acc_T_4 = and(a_mask_sub_sub_size, a_mask_sub_sub_4_2) node a_mask_sub_sub_4_1 = or(a_mask_sub_sub_sub_2_1, _a_mask_sub_sub_acc_T_4) node a_mask_sub_sub_5_2 = and(a_mask_sub_sub_sub_2_2, a_mask_sub_sub_bit) node _a_mask_sub_sub_acc_T_5 = and(a_mask_sub_sub_size, a_mask_sub_sub_5_2) node a_mask_sub_sub_5_1 = or(a_mask_sub_sub_sub_2_1, _a_mask_sub_sub_acc_T_5) node a_mask_sub_sub_6_2 = and(a_mask_sub_sub_sub_3_2, a_mask_sub_sub_nbit) node _a_mask_sub_sub_acc_T_6 = and(a_mask_sub_sub_size, a_mask_sub_sub_6_2) node a_mask_sub_sub_6_1 = or(a_mask_sub_sub_sub_3_1, _a_mask_sub_sub_acc_T_6) node a_mask_sub_sub_7_2 = and(a_mask_sub_sub_sub_3_2, a_mask_sub_sub_bit) node _a_mask_sub_sub_acc_T_7 = and(a_mask_sub_sub_size, a_mask_sub_sub_7_2) node a_mask_sub_sub_7_1 = or(a_mask_sub_sub_sub_3_1, _a_mask_sub_sub_acc_T_7) node a_mask_sub_size = bits(a_mask_sizeOH, 1, 1) node a_mask_sub_bit = bits(tlb.io.resp.paddr, 1, 1) node a_mask_sub_nbit = eq(a_mask_sub_bit, UInt<1>(0h0)) node a_mask_sub_0_2 = and(a_mask_sub_sub_0_2, a_mask_sub_nbit) node _a_mask_sub_acc_T = and(a_mask_sub_size, a_mask_sub_0_2) node a_mask_sub_0_1 = or(a_mask_sub_sub_0_1, _a_mask_sub_acc_T) node a_mask_sub_1_2 = and(a_mask_sub_sub_0_2, a_mask_sub_bit) node _a_mask_sub_acc_T_1 = and(a_mask_sub_size, a_mask_sub_1_2) node a_mask_sub_1_1 = or(a_mask_sub_sub_0_1, _a_mask_sub_acc_T_1) node a_mask_sub_2_2 = and(a_mask_sub_sub_1_2, a_mask_sub_nbit) node _a_mask_sub_acc_T_2 = and(a_mask_sub_size, a_mask_sub_2_2) node a_mask_sub_2_1 = or(a_mask_sub_sub_1_1, _a_mask_sub_acc_T_2) node a_mask_sub_3_2 = and(a_mask_sub_sub_1_2, a_mask_sub_bit) node _a_mask_sub_acc_T_3 = and(a_mask_sub_size, a_mask_sub_3_2) node a_mask_sub_3_1 = or(a_mask_sub_sub_1_1, _a_mask_sub_acc_T_3) node a_mask_sub_4_2 = and(a_mask_sub_sub_2_2, a_mask_sub_nbit) node _a_mask_sub_acc_T_4 = and(a_mask_sub_size, a_mask_sub_4_2) node a_mask_sub_4_1 = or(a_mask_sub_sub_2_1, _a_mask_sub_acc_T_4) node a_mask_sub_5_2 = and(a_mask_sub_sub_2_2, a_mask_sub_bit) node _a_mask_sub_acc_T_5 = and(a_mask_sub_size, a_mask_sub_5_2) node a_mask_sub_5_1 = or(a_mask_sub_sub_2_1, _a_mask_sub_acc_T_5) node a_mask_sub_6_2 = and(a_mask_sub_sub_3_2, a_mask_sub_nbit) node _a_mask_sub_acc_T_6 = and(a_mask_sub_size, a_mask_sub_6_2) node a_mask_sub_6_1 = or(a_mask_sub_sub_3_1, _a_mask_sub_acc_T_6) node a_mask_sub_7_2 = and(a_mask_sub_sub_3_2, a_mask_sub_bit) node _a_mask_sub_acc_T_7 = and(a_mask_sub_size, a_mask_sub_7_2) node a_mask_sub_7_1 = or(a_mask_sub_sub_3_1, _a_mask_sub_acc_T_7) node a_mask_sub_8_2 = and(a_mask_sub_sub_4_2, a_mask_sub_nbit) node _a_mask_sub_acc_T_8 = and(a_mask_sub_size, a_mask_sub_8_2) node a_mask_sub_8_1 = or(a_mask_sub_sub_4_1, _a_mask_sub_acc_T_8) node a_mask_sub_9_2 = and(a_mask_sub_sub_4_2, a_mask_sub_bit) node _a_mask_sub_acc_T_9 = and(a_mask_sub_size, a_mask_sub_9_2) node a_mask_sub_9_1 = or(a_mask_sub_sub_4_1, _a_mask_sub_acc_T_9) node a_mask_sub_10_2 = and(a_mask_sub_sub_5_2, a_mask_sub_nbit) node _a_mask_sub_acc_T_10 = and(a_mask_sub_size, a_mask_sub_10_2) node a_mask_sub_10_1 = or(a_mask_sub_sub_5_1, _a_mask_sub_acc_T_10) node a_mask_sub_11_2 = and(a_mask_sub_sub_5_2, a_mask_sub_bit) node _a_mask_sub_acc_T_11 = and(a_mask_sub_size, a_mask_sub_11_2) node a_mask_sub_11_1 = or(a_mask_sub_sub_5_1, _a_mask_sub_acc_T_11) node a_mask_sub_12_2 = and(a_mask_sub_sub_6_2, a_mask_sub_nbit) node _a_mask_sub_acc_T_12 = and(a_mask_sub_size, a_mask_sub_12_2) node a_mask_sub_12_1 = or(a_mask_sub_sub_6_1, _a_mask_sub_acc_T_12) node a_mask_sub_13_2 = and(a_mask_sub_sub_6_2, a_mask_sub_bit) node _a_mask_sub_acc_T_13 = and(a_mask_sub_size, a_mask_sub_13_2) node a_mask_sub_13_1 = or(a_mask_sub_sub_6_1, _a_mask_sub_acc_T_13) node a_mask_sub_14_2 = and(a_mask_sub_sub_7_2, a_mask_sub_nbit) node _a_mask_sub_acc_T_14 = and(a_mask_sub_size, a_mask_sub_14_2) node a_mask_sub_14_1 = or(a_mask_sub_sub_7_1, _a_mask_sub_acc_T_14) node a_mask_sub_15_2 = and(a_mask_sub_sub_7_2, a_mask_sub_bit) node _a_mask_sub_acc_T_15 = and(a_mask_sub_size, a_mask_sub_15_2) node a_mask_sub_15_1 = or(a_mask_sub_sub_7_1, _a_mask_sub_acc_T_15) node a_mask_size = bits(a_mask_sizeOH, 0, 0) node a_mask_bit = bits(tlb.io.resp.paddr, 0, 0) node a_mask_nbit = eq(a_mask_bit, UInt<1>(0h0)) node a_mask_eq = and(a_mask_sub_0_2, a_mask_nbit) node _a_mask_acc_T = and(a_mask_size, a_mask_eq) node a_mask_acc = or(a_mask_sub_0_1, _a_mask_acc_T) node a_mask_eq_1 = and(a_mask_sub_0_2, a_mask_bit) node _a_mask_acc_T_1 = and(a_mask_size, a_mask_eq_1) node a_mask_acc_1 = or(a_mask_sub_0_1, _a_mask_acc_T_1) node a_mask_eq_2 = and(a_mask_sub_1_2, a_mask_nbit) node _a_mask_acc_T_2 = and(a_mask_size, a_mask_eq_2) node a_mask_acc_2 = or(a_mask_sub_1_1, _a_mask_acc_T_2) node a_mask_eq_3 = and(a_mask_sub_1_2, a_mask_bit) node _a_mask_acc_T_3 = and(a_mask_size, a_mask_eq_3) node a_mask_acc_3 = or(a_mask_sub_1_1, _a_mask_acc_T_3) node a_mask_eq_4 = and(a_mask_sub_2_2, a_mask_nbit) node _a_mask_acc_T_4 = and(a_mask_size, a_mask_eq_4) node a_mask_acc_4 = or(a_mask_sub_2_1, _a_mask_acc_T_4) node a_mask_eq_5 = and(a_mask_sub_2_2, a_mask_bit) node _a_mask_acc_T_5 = and(a_mask_size, a_mask_eq_5) node a_mask_acc_5 = or(a_mask_sub_2_1, _a_mask_acc_T_5) node a_mask_eq_6 = and(a_mask_sub_3_2, a_mask_nbit) node _a_mask_acc_T_6 = and(a_mask_size, a_mask_eq_6) node a_mask_acc_6 = or(a_mask_sub_3_1, _a_mask_acc_T_6) node a_mask_eq_7 = and(a_mask_sub_3_2, a_mask_bit) node _a_mask_acc_T_7 = and(a_mask_size, a_mask_eq_7) node a_mask_acc_7 = or(a_mask_sub_3_1, _a_mask_acc_T_7) node a_mask_eq_8 = and(a_mask_sub_4_2, a_mask_nbit) node _a_mask_acc_T_8 = and(a_mask_size, a_mask_eq_8) node a_mask_acc_8 = or(a_mask_sub_4_1, _a_mask_acc_T_8) node a_mask_eq_9 = and(a_mask_sub_4_2, a_mask_bit) node _a_mask_acc_T_9 = and(a_mask_size, a_mask_eq_9) node a_mask_acc_9 = or(a_mask_sub_4_1, _a_mask_acc_T_9) node a_mask_eq_10 = and(a_mask_sub_5_2, a_mask_nbit) node _a_mask_acc_T_10 = and(a_mask_size, a_mask_eq_10) node a_mask_acc_10 = or(a_mask_sub_5_1, _a_mask_acc_T_10) node a_mask_eq_11 = and(a_mask_sub_5_2, a_mask_bit) node _a_mask_acc_T_11 = and(a_mask_size, a_mask_eq_11) node a_mask_acc_11 = or(a_mask_sub_5_1, _a_mask_acc_T_11) node a_mask_eq_12 = and(a_mask_sub_6_2, a_mask_nbit) node _a_mask_acc_T_12 = and(a_mask_size, a_mask_eq_12) node a_mask_acc_12 = or(a_mask_sub_6_1, _a_mask_acc_T_12) node a_mask_eq_13 = and(a_mask_sub_6_2, a_mask_bit) node _a_mask_acc_T_13 = and(a_mask_size, a_mask_eq_13) node a_mask_acc_13 = or(a_mask_sub_6_1, _a_mask_acc_T_13) node a_mask_eq_14 = and(a_mask_sub_7_2, a_mask_nbit) node _a_mask_acc_T_14 = and(a_mask_size, a_mask_eq_14) node a_mask_acc_14 = or(a_mask_sub_7_1, _a_mask_acc_T_14) node a_mask_eq_15 = and(a_mask_sub_7_2, a_mask_bit) node _a_mask_acc_T_15 = and(a_mask_size, a_mask_eq_15) node a_mask_acc_15 = or(a_mask_sub_7_1, _a_mask_acc_T_15) node a_mask_eq_16 = and(a_mask_sub_8_2, a_mask_nbit) node _a_mask_acc_T_16 = and(a_mask_size, a_mask_eq_16) node a_mask_acc_16 = or(a_mask_sub_8_1, _a_mask_acc_T_16) node a_mask_eq_17 = and(a_mask_sub_8_2, a_mask_bit) node _a_mask_acc_T_17 = and(a_mask_size, a_mask_eq_17) node a_mask_acc_17 = or(a_mask_sub_8_1, _a_mask_acc_T_17) node a_mask_eq_18 = and(a_mask_sub_9_2, a_mask_nbit) node _a_mask_acc_T_18 = and(a_mask_size, a_mask_eq_18) node a_mask_acc_18 = or(a_mask_sub_9_1, _a_mask_acc_T_18) node a_mask_eq_19 = and(a_mask_sub_9_2, a_mask_bit) node _a_mask_acc_T_19 = and(a_mask_size, a_mask_eq_19) node a_mask_acc_19 = or(a_mask_sub_9_1, _a_mask_acc_T_19) node a_mask_eq_20 = and(a_mask_sub_10_2, a_mask_nbit) node _a_mask_acc_T_20 = and(a_mask_size, a_mask_eq_20) node a_mask_acc_20 = or(a_mask_sub_10_1, _a_mask_acc_T_20) node a_mask_eq_21 = and(a_mask_sub_10_2, a_mask_bit) node _a_mask_acc_T_21 = and(a_mask_size, a_mask_eq_21) node a_mask_acc_21 = or(a_mask_sub_10_1, _a_mask_acc_T_21) node a_mask_eq_22 = and(a_mask_sub_11_2, a_mask_nbit) node _a_mask_acc_T_22 = and(a_mask_size, a_mask_eq_22) node a_mask_acc_22 = or(a_mask_sub_11_1, _a_mask_acc_T_22) node a_mask_eq_23 = and(a_mask_sub_11_2, a_mask_bit) node _a_mask_acc_T_23 = and(a_mask_size, a_mask_eq_23) node a_mask_acc_23 = or(a_mask_sub_11_1, _a_mask_acc_T_23) node a_mask_eq_24 = and(a_mask_sub_12_2, a_mask_nbit) node _a_mask_acc_T_24 = and(a_mask_size, a_mask_eq_24) node a_mask_acc_24 = or(a_mask_sub_12_1, _a_mask_acc_T_24) node a_mask_eq_25 = and(a_mask_sub_12_2, a_mask_bit) node _a_mask_acc_T_25 = and(a_mask_size, a_mask_eq_25) node a_mask_acc_25 = or(a_mask_sub_12_1, _a_mask_acc_T_25) node a_mask_eq_26 = and(a_mask_sub_13_2, a_mask_nbit) node _a_mask_acc_T_26 = and(a_mask_size, a_mask_eq_26) node a_mask_acc_26 = or(a_mask_sub_13_1, _a_mask_acc_T_26) node a_mask_eq_27 = and(a_mask_sub_13_2, a_mask_bit) node _a_mask_acc_T_27 = and(a_mask_size, a_mask_eq_27) node a_mask_acc_27 = or(a_mask_sub_13_1, _a_mask_acc_T_27) node a_mask_eq_28 = and(a_mask_sub_14_2, a_mask_nbit) node _a_mask_acc_T_28 = and(a_mask_size, a_mask_eq_28) node a_mask_acc_28 = or(a_mask_sub_14_1, _a_mask_acc_T_28) node a_mask_eq_29 = and(a_mask_sub_14_2, a_mask_bit) node _a_mask_acc_T_29 = and(a_mask_size, a_mask_eq_29) node a_mask_acc_29 = or(a_mask_sub_14_1, _a_mask_acc_T_29) node a_mask_eq_30 = and(a_mask_sub_15_2, a_mask_nbit) node _a_mask_acc_T_30 = and(a_mask_size, a_mask_eq_30) node a_mask_acc_30 = or(a_mask_sub_15_1, _a_mask_acc_T_30) node a_mask_eq_31 = and(a_mask_sub_15_2, a_mask_bit) node _a_mask_acc_T_31 = and(a_mask_size, a_mask_eq_31) node a_mask_acc_31 = or(a_mask_sub_15_1, _a_mask_acc_T_31) node a_mask_lo_lo_lo_lo = cat(a_mask_acc_1, a_mask_acc) node a_mask_lo_lo_lo_hi = cat(a_mask_acc_3, a_mask_acc_2) node a_mask_lo_lo_lo = cat(a_mask_lo_lo_lo_hi, a_mask_lo_lo_lo_lo) node a_mask_lo_lo_hi_lo = cat(a_mask_acc_5, a_mask_acc_4) node a_mask_lo_lo_hi_hi = cat(a_mask_acc_7, a_mask_acc_6) node a_mask_lo_lo_hi = cat(a_mask_lo_lo_hi_hi, a_mask_lo_lo_hi_lo) node a_mask_lo_lo = cat(a_mask_lo_lo_hi, a_mask_lo_lo_lo) node a_mask_lo_hi_lo_lo = cat(a_mask_acc_9, a_mask_acc_8) node a_mask_lo_hi_lo_hi = cat(a_mask_acc_11, a_mask_acc_10) node a_mask_lo_hi_lo = cat(a_mask_lo_hi_lo_hi, a_mask_lo_hi_lo_lo) node a_mask_lo_hi_hi_lo = cat(a_mask_acc_13, a_mask_acc_12) node a_mask_lo_hi_hi_hi = cat(a_mask_acc_15, a_mask_acc_14) node a_mask_lo_hi_hi = cat(a_mask_lo_hi_hi_hi, a_mask_lo_hi_hi_lo) node a_mask_lo_hi = cat(a_mask_lo_hi_hi, a_mask_lo_hi_lo) node a_mask_lo = cat(a_mask_lo_hi, a_mask_lo_lo) node a_mask_hi_lo_lo_lo = cat(a_mask_acc_17, a_mask_acc_16) node a_mask_hi_lo_lo_hi = cat(a_mask_acc_19, a_mask_acc_18) node a_mask_hi_lo_lo = cat(a_mask_hi_lo_lo_hi, a_mask_hi_lo_lo_lo) node a_mask_hi_lo_hi_lo = cat(a_mask_acc_21, a_mask_acc_20) node a_mask_hi_lo_hi_hi = cat(a_mask_acc_23, a_mask_acc_22) node a_mask_hi_lo_hi = cat(a_mask_hi_lo_hi_hi, a_mask_hi_lo_hi_lo) node a_mask_hi_lo = cat(a_mask_hi_lo_hi, a_mask_hi_lo_lo) node a_mask_hi_hi_lo_lo = cat(a_mask_acc_25, a_mask_acc_24) node a_mask_hi_hi_lo_hi = cat(a_mask_acc_27, a_mask_acc_26) node a_mask_hi_hi_lo = cat(a_mask_hi_hi_lo_hi, a_mask_hi_hi_lo_lo) node a_mask_hi_hi_hi_lo = cat(a_mask_acc_29, a_mask_acc_28) node a_mask_hi_hi_hi_hi = cat(a_mask_acc_31, a_mask_acc_30) node a_mask_hi_hi_hi = cat(a_mask_hi_hi_hi_hi, a_mask_hi_hi_hi_lo) node a_mask_hi_hi = cat(a_mask_hi_hi_hi, a_mask_hi_hi_lo) node a_mask_hi = cat(a_mask_hi_hi, a_mask_hi_lo) node _a_mask_T = cat(a_mask_hi, a_mask_lo) connect bundle.mask, _a_mask_T invalidate bundle.data connect bundle.corrupt, UInt<1>(0h0) connect request_latency_injection_q.io.enq.bits.corrupt, bundle.corrupt connect request_latency_injection_q.io.enq.bits.data, bundle.data connect request_latency_injection_q.io.enq.bits.mask, bundle.mask connect request_latency_injection_q.io.enq.bits.address, bundle.address connect request_latency_injection_q.io.enq.bits.source, bundle.source connect request_latency_injection_q.io.enq.bits.size, bundle.size connect request_latency_injection_q.io.enq.bits.param, bundle.param connect request_latency_injection_q.io.enq.bits.opcode, bundle.opcode else : node _T_28 = eq(request_input.bits.cmd, UInt<1>(0h1)) when _T_28 : node _T_29 = bits(request_input.bits.addr, 4, 0) node _T_30 = shl(_T_29, 3) node _T_31 = dshl(request_input.bits.data, _T_30) node _legal_T_63 = leq(UInt<1>(0h0), request_input.bits.size) node _legal_T_64 = leq(request_input.bits.size, UInt<4>(0hc)) node _legal_T_65 = and(_legal_T_63, _legal_T_64) node _legal_T_66 = or(UInt<1>(0h0), _legal_T_65) node _legal_T_67 = xor(tlb.io.resp.paddr, UInt<14>(0h3000)) node _legal_T_68 = cvt(_legal_T_67) node _legal_T_69 = and(_legal_T_68, asSInt(UInt<33>(0h9a113000))) node _legal_T_70 = asSInt(_legal_T_69) node _legal_T_71 = eq(_legal_T_70, asSInt(UInt<1>(0h0))) node _legal_T_72 = and(_legal_T_66, _legal_T_71) node _legal_T_73 = leq(UInt<1>(0h0), request_input.bits.size) node _legal_T_74 = leq(request_input.bits.size, UInt<3>(0h6)) node _legal_T_75 = and(_legal_T_73, _legal_T_74) node _legal_T_76 = or(UInt<1>(0h0), _legal_T_75) node _legal_T_77 = xor(tlb.io.resp.paddr, UInt<1>(0h0)) node _legal_T_78 = cvt(_legal_T_77) node _legal_T_79 = and(_legal_T_78, asSInt(UInt<33>(0h9a112000))) node _legal_T_80 = asSInt(_legal_T_79) node _legal_T_81 = eq(_legal_T_80, asSInt(UInt<1>(0h0))) node _legal_T_82 = xor(tlb.io.resp.paddr, UInt<21>(0h100000)) node _legal_T_83 = cvt(_legal_T_82) node _legal_T_84 = and(_legal_T_83, asSInt(UInt<33>(0h9a103000))) node _legal_T_85 = asSInt(_legal_T_84) node _legal_T_86 = eq(_legal_T_85, asSInt(UInt<1>(0h0))) node _legal_T_87 = xor(tlb.io.resp.paddr, UInt<26>(0h2000000)) node _legal_T_88 = cvt(_legal_T_87) node _legal_T_89 = and(_legal_T_88, asSInt(UInt<33>(0h9a110000))) node _legal_T_90 = asSInt(_legal_T_89) node _legal_T_91 = eq(_legal_T_90, asSInt(UInt<1>(0h0))) node _legal_T_92 = xor(tlb.io.resp.paddr, UInt<26>(0h2010000)) node _legal_T_93 = cvt(_legal_T_92) node _legal_T_94 = and(_legal_T_93, asSInt(UInt<33>(0h9a113000))) node _legal_T_95 = asSInt(_legal_T_94) node _legal_T_96 = eq(_legal_T_95, asSInt(UInt<1>(0h0))) node _legal_T_97 = xor(tlb.io.resp.paddr, UInt<28>(0h8000000)) node _legal_T_98 = cvt(_legal_T_97) node _legal_T_99 = and(_legal_T_98, asSInt(UInt<33>(0h98000000))) node _legal_T_100 = asSInt(_legal_T_99) node _legal_T_101 = eq(_legal_T_100, asSInt(UInt<1>(0h0))) node _legal_T_102 = xor(tlb.io.resp.paddr, UInt<28>(0h8000000)) node _legal_T_103 = cvt(_legal_T_102) node _legal_T_104 = and(_legal_T_103, asSInt(UInt<33>(0h9a110000))) node _legal_T_105 = asSInt(_legal_T_104) node _legal_T_106 = eq(_legal_T_105, asSInt(UInt<1>(0h0))) node _legal_T_107 = xor(tlb.io.resp.paddr, UInt<29>(0h10000000)) node _legal_T_108 = cvt(_legal_T_107) node _legal_T_109 = and(_legal_T_108, asSInt(UInt<33>(0h9a113000))) node _legal_T_110 = asSInt(_legal_T_109) node _legal_T_111 = eq(_legal_T_110, asSInt(UInt<1>(0h0))) node _legal_T_112 = xor(tlb.io.resp.paddr, UInt<32>(0h80000000)) node _legal_T_113 = cvt(_legal_T_112) node _legal_T_114 = and(_legal_T_113, asSInt(UInt<33>(0h90000000))) node _legal_T_115 = asSInt(_legal_T_114) node _legal_T_116 = eq(_legal_T_115, asSInt(UInt<1>(0h0))) node _legal_T_117 = or(_legal_T_81, _legal_T_86) node _legal_T_118 = or(_legal_T_117, _legal_T_91) node _legal_T_119 = or(_legal_T_118, _legal_T_96) node _legal_T_120 = or(_legal_T_119, _legal_T_101) node _legal_T_121 = or(_legal_T_120, _legal_T_106) node _legal_T_122 = or(_legal_T_121, _legal_T_111) node _legal_T_123 = or(_legal_T_122, _legal_T_116) node _legal_T_124 = and(_legal_T_76, _legal_T_123) node _legal_T_125 = or(UInt<1>(0h0), UInt<1>(0h0)) node _legal_T_126 = xor(tlb.io.resp.paddr, UInt<17>(0h10000)) node _legal_T_127 = cvt(_legal_T_126) node _legal_T_128 = and(_legal_T_127, asSInt(UInt<33>(0h9a110000))) node _legal_T_129 = asSInt(_legal_T_128) node _legal_T_130 = eq(_legal_T_129, asSInt(UInt<1>(0h0))) node _legal_T_131 = and(_legal_T_125, _legal_T_130) node _legal_T_132 = or(UInt<1>(0h0), _legal_T_72) node _legal_T_133 = or(_legal_T_132, _legal_T_124) node legal_1 = or(_legal_T_133, _legal_T_131) wire bundle_1 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>} connect bundle_1.opcode, UInt<1>(0h0) connect bundle_1.param, UInt<1>(0h0) connect bundle_1.size, request_input.bits.size connect bundle_1.source, tags_for_issue_Q.io.deq.bits connect bundle_1.address, tlb.io.resp.paddr node _a_mask_sizeOH_T_3 = or(request_input.bits.size, UInt<5>(0h0)) node _a_mask_sizeOH_shiftAmount_T_1 = pad(_a_mask_sizeOH_T_3, 3) node a_mask_sizeOH_shiftAmount_1 = bits(_a_mask_sizeOH_shiftAmount_T_1, 2, 0) node _a_mask_sizeOH_T_4 = dshl(UInt<1>(0h1), a_mask_sizeOH_shiftAmount_1) node _a_mask_sizeOH_T_5 = bits(_a_mask_sizeOH_T_4, 4, 0) node a_mask_sizeOH_1 = or(_a_mask_sizeOH_T_5, UInt<1>(0h1)) node a_mask_sub_sub_sub_sub_sub_0_1_1 = geq(request_input.bits.size, UInt<3>(0h5)) node a_mask_sub_sub_sub_sub_size_1 = bits(a_mask_sizeOH_1, 4, 4) node a_mask_sub_sub_sub_sub_bit_1 = bits(tlb.io.resp.paddr, 4, 4) node a_mask_sub_sub_sub_sub_nbit_1 = eq(a_mask_sub_sub_sub_sub_bit_1, UInt<1>(0h0)) node a_mask_sub_sub_sub_sub_0_2_1 = and(UInt<1>(0h1), a_mask_sub_sub_sub_sub_nbit_1) node _a_mask_sub_sub_sub_sub_acc_T_2 = and(a_mask_sub_sub_sub_sub_size_1, a_mask_sub_sub_sub_sub_0_2_1) node a_mask_sub_sub_sub_sub_0_1_1 = or(a_mask_sub_sub_sub_sub_sub_0_1_1, _a_mask_sub_sub_sub_sub_acc_T_2) node a_mask_sub_sub_sub_sub_1_2_1 = and(UInt<1>(0h1), a_mask_sub_sub_sub_sub_bit_1) node _a_mask_sub_sub_sub_sub_acc_T_3 = and(a_mask_sub_sub_sub_sub_size_1, a_mask_sub_sub_sub_sub_1_2_1) node a_mask_sub_sub_sub_sub_1_1_1 = or(a_mask_sub_sub_sub_sub_sub_0_1_1, _a_mask_sub_sub_sub_sub_acc_T_3) node a_mask_sub_sub_sub_size_1 = bits(a_mask_sizeOH_1, 3, 3) node a_mask_sub_sub_sub_bit_1 = bits(tlb.io.resp.paddr, 3, 3) node a_mask_sub_sub_sub_nbit_1 = eq(a_mask_sub_sub_sub_bit_1, UInt<1>(0h0)) node a_mask_sub_sub_sub_0_2_1 = and(a_mask_sub_sub_sub_sub_0_2_1, a_mask_sub_sub_sub_nbit_1) node _a_mask_sub_sub_sub_acc_T_4 = and(a_mask_sub_sub_sub_size_1, a_mask_sub_sub_sub_0_2_1) node a_mask_sub_sub_sub_0_1_1 = or(a_mask_sub_sub_sub_sub_0_1_1, _a_mask_sub_sub_sub_acc_T_4) node a_mask_sub_sub_sub_1_2_1 = and(a_mask_sub_sub_sub_sub_0_2_1, a_mask_sub_sub_sub_bit_1) node _a_mask_sub_sub_sub_acc_T_5 = and(a_mask_sub_sub_sub_size_1, a_mask_sub_sub_sub_1_2_1) node a_mask_sub_sub_sub_1_1_1 = or(a_mask_sub_sub_sub_sub_0_1_1, _a_mask_sub_sub_sub_acc_T_5) node a_mask_sub_sub_sub_2_2_1 = and(a_mask_sub_sub_sub_sub_1_2_1, a_mask_sub_sub_sub_nbit_1) node _a_mask_sub_sub_sub_acc_T_6 = and(a_mask_sub_sub_sub_size_1, a_mask_sub_sub_sub_2_2_1) node a_mask_sub_sub_sub_2_1_1 = or(a_mask_sub_sub_sub_sub_1_1_1, _a_mask_sub_sub_sub_acc_T_6) node a_mask_sub_sub_sub_3_2_1 = and(a_mask_sub_sub_sub_sub_1_2_1, a_mask_sub_sub_sub_bit_1) node _a_mask_sub_sub_sub_acc_T_7 = and(a_mask_sub_sub_sub_size_1, a_mask_sub_sub_sub_3_2_1) node a_mask_sub_sub_sub_3_1_1 = or(a_mask_sub_sub_sub_sub_1_1_1, _a_mask_sub_sub_sub_acc_T_7) node a_mask_sub_sub_size_1 = bits(a_mask_sizeOH_1, 2, 2) node a_mask_sub_sub_bit_1 = bits(tlb.io.resp.paddr, 2, 2) node a_mask_sub_sub_nbit_1 = eq(a_mask_sub_sub_bit_1, UInt<1>(0h0)) node a_mask_sub_sub_0_2_1 = and(a_mask_sub_sub_sub_0_2_1, a_mask_sub_sub_nbit_1) node _a_mask_sub_sub_acc_T_8 = and(a_mask_sub_sub_size_1, a_mask_sub_sub_0_2_1) node a_mask_sub_sub_0_1_1 = or(a_mask_sub_sub_sub_0_1_1, _a_mask_sub_sub_acc_T_8) node a_mask_sub_sub_1_2_1 = and(a_mask_sub_sub_sub_0_2_1, a_mask_sub_sub_bit_1) node _a_mask_sub_sub_acc_T_9 = and(a_mask_sub_sub_size_1, a_mask_sub_sub_1_2_1) node a_mask_sub_sub_1_1_1 = or(a_mask_sub_sub_sub_0_1_1, _a_mask_sub_sub_acc_T_9) node a_mask_sub_sub_2_2_1 = and(a_mask_sub_sub_sub_1_2_1, a_mask_sub_sub_nbit_1) node _a_mask_sub_sub_acc_T_10 = and(a_mask_sub_sub_size_1, a_mask_sub_sub_2_2_1) node a_mask_sub_sub_2_1_1 = or(a_mask_sub_sub_sub_1_1_1, _a_mask_sub_sub_acc_T_10) node a_mask_sub_sub_3_2_1 = and(a_mask_sub_sub_sub_1_2_1, a_mask_sub_sub_bit_1) node _a_mask_sub_sub_acc_T_11 = and(a_mask_sub_sub_size_1, a_mask_sub_sub_3_2_1) node a_mask_sub_sub_3_1_1 = or(a_mask_sub_sub_sub_1_1_1, _a_mask_sub_sub_acc_T_11) node a_mask_sub_sub_4_2_1 = and(a_mask_sub_sub_sub_2_2_1, a_mask_sub_sub_nbit_1) node _a_mask_sub_sub_acc_T_12 = and(a_mask_sub_sub_size_1, a_mask_sub_sub_4_2_1) node a_mask_sub_sub_4_1_1 = or(a_mask_sub_sub_sub_2_1_1, _a_mask_sub_sub_acc_T_12) node a_mask_sub_sub_5_2_1 = and(a_mask_sub_sub_sub_2_2_1, a_mask_sub_sub_bit_1) node _a_mask_sub_sub_acc_T_13 = and(a_mask_sub_sub_size_1, a_mask_sub_sub_5_2_1) node a_mask_sub_sub_5_1_1 = or(a_mask_sub_sub_sub_2_1_1, _a_mask_sub_sub_acc_T_13) node a_mask_sub_sub_6_2_1 = and(a_mask_sub_sub_sub_3_2_1, a_mask_sub_sub_nbit_1) node _a_mask_sub_sub_acc_T_14 = and(a_mask_sub_sub_size_1, a_mask_sub_sub_6_2_1) node a_mask_sub_sub_6_1_1 = or(a_mask_sub_sub_sub_3_1_1, _a_mask_sub_sub_acc_T_14) node a_mask_sub_sub_7_2_1 = and(a_mask_sub_sub_sub_3_2_1, a_mask_sub_sub_bit_1) node _a_mask_sub_sub_acc_T_15 = and(a_mask_sub_sub_size_1, a_mask_sub_sub_7_2_1) node a_mask_sub_sub_7_1_1 = or(a_mask_sub_sub_sub_3_1_1, _a_mask_sub_sub_acc_T_15) node a_mask_sub_size_1 = bits(a_mask_sizeOH_1, 1, 1) node a_mask_sub_bit_1 = bits(tlb.io.resp.paddr, 1, 1) node a_mask_sub_nbit_1 = eq(a_mask_sub_bit_1, UInt<1>(0h0)) node a_mask_sub_0_2_1 = and(a_mask_sub_sub_0_2_1, a_mask_sub_nbit_1) node _a_mask_sub_acc_T_16 = and(a_mask_sub_size_1, a_mask_sub_0_2_1) node a_mask_sub_0_1_1 = or(a_mask_sub_sub_0_1_1, _a_mask_sub_acc_T_16) node a_mask_sub_1_2_1 = and(a_mask_sub_sub_0_2_1, a_mask_sub_bit_1) node _a_mask_sub_acc_T_17 = and(a_mask_sub_size_1, a_mask_sub_1_2_1) node a_mask_sub_1_1_1 = or(a_mask_sub_sub_0_1_1, _a_mask_sub_acc_T_17) node a_mask_sub_2_2_1 = and(a_mask_sub_sub_1_2_1, a_mask_sub_nbit_1) node _a_mask_sub_acc_T_18 = and(a_mask_sub_size_1, a_mask_sub_2_2_1) node a_mask_sub_2_1_1 = or(a_mask_sub_sub_1_1_1, _a_mask_sub_acc_T_18) node a_mask_sub_3_2_1 = and(a_mask_sub_sub_1_2_1, a_mask_sub_bit_1) node _a_mask_sub_acc_T_19 = and(a_mask_sub_size_1, a_mask_sub_3_2_1) node a_mask_sub_3_1_1 = or(a_mask_sub_sub_1_1_1, _a_mask_sub_acc_T_19) node a_mask_sub_4_2_1 = and(a_mask_sub_sub_2_2_1, a_mask_sub_nbit_1) node _a_mask_sub_acc_T_20 = and(a_mask_sub_size_1, a_mask_sub_4_2_1) node a_mask_sub_4_1_1 = or(a_mask_sub_sub_2_1_1, _a_mask_sub_acc_T_20) node a_mask_sub_5_2_1 = and(a_mask_sub_sub_2_2_1, a_mask_sub_bit_1) node _a_mask_sub_acc_T_21 = and(a_mask_sub_size_1, a_mask_sub_5_2_1) node a_mask_sub_5_1_1 = or(a_mask_sub_sub_2_1_1, _a_mask_sub_acc_T_21) node a_mask_sub_6_2_1 = and(a_mask_sub_sub_3_2_1, a_mask_sub_nbit_1) node _a_mask_sub_acc_T_22 = and(a_mask_sub_size_1, a_mask_sub_6_2_1) node a_mask_sub_6_1_1 = or(a_mask_sub_sub_3_1_1, _a_mask_sub_acc_T_22) node a_mask_sub_7_2_1 = and(a_mask_sub_sub_3_2_1, a_mask_sub_bit_1) node _a_mask_sub_acc_T_23 = and(a_mask_sub_size_1, a_mask_sub_7_2_1) node a_mask_sub_7_1_1 = or(a_mask_sub_sub_3_1_1, _a_mask_sub_acc_T_23) node a_mask_sub_8_2_1 = and(a_mask_sub_sub_4_2_1, a_mask_sub_nbit_1) node _a_mask_sub_acc_T_24 = and(a_mask_sub_size_1, a_mask_sub_8_2_1) node a_mask_sub_8_1_1 = or(a_mask_sub_sub_4_1_1, _a_mask_sub_acc_T_24) node a_mask_sub_9_2_1 = and(a_mask_sub_sub_4_2_1, a_mask_sub_bit_1) node _a_mask_sub_acc_T_25 = and(a_mask_sub_size_1, a_mask_sub_9_2_1) node a_mask_sub_9_1_1 = or(a_mask_sub_sub_4_1_1, _a_mask_sub_acc_T_25) node a_mask_sub_10_2_1 = and(a_mask_sub_sub_5_2_1, a_mask_sub_nbit_1) node _a_mask_sub_acc_T_26 = and(a_mask_sub_size_1, a_mask_sub_10_2_1) node a_mask_sub_10_1_1 = or(a_mask_sub_sub_5_1_1, _a_mask_sub_acc_T_26) node a_mask_sub_11_2_1 = and(a_mask_sub_sub_5_2_1, a_mask_sub_bit_1) node _a_mask_sub_acc_T_27 = and(a_mask_sub_size_1, a_mask_sub_11_2_1) node a_mask_sub_11_1_1 = or(a_mask_sub_sub_5_1_1, _a_mask_sub_acc_T_27) node a_mask_sub_12_2_1 = and(a_mask_sub_sub_6_2_1, a_mask_sub_nbit_1) node _a_mask_sub_acc_T_28 = and(a_mask_sub_size_1, a_mask_sub_12_2_1) node a_mask_sub_12_1_1 = or(a_mask_sub_sub_6_1_1, _a_mask_sub_acc_T_28) node a_mask_sub_13_2_1 = and(a_mask_sub_sub_6_2_1, a_mask_sub_bit_1) node _a_mask_sub_acc_T_29 = and(a_mask_sub_size_1, a_mask_sub_13_2_1) node a_mask_sub_13_1_1 = or(a_mask_sub_sub_6_1_1, _a_mask_sub_acc_T_29) node a_mask_sub_14_2_1 = and(a_mask_sub_sub_7_2_1, a_mask_sub_nbit_1) node _a_mask_sub_acc_T_30 = and(a_mask_sub_size_1, a_mask_sub_14_2_1) node a_mask_sub_14_1_1 = or(a_mask_sub_sub_7_1_1, _a_mask_sub_acc_T_30) node a_mask_sub_15_2_1 = and(a_mask_sub_sub_7_2_1, a_mask_sub_bit_1) node _a_mask_sub_acc_T_31 = and(a_mask_sub_size_1, a_mask_sub_15_2_1) node a_mask_sub_15_1_1 = or(a_mask_sub_sub_7_1_1, _a_mask_sub_acc_T_31) node a_mask_size_1 = bits(a_mask_sizeOH_1, 0, 0) node a_mask_bit_1 = bits(tlb.io.resp.paddr, 0, 0) node a_mask_nbit_1 = eq(a_mask_bit_1, UInt<1>(0h0)) node a_mask_eq_32 = and(a_mask_sub_0_2_1, a_mask_nbit_1) node _a_mask_acc_T_32 = and(a_mask_size_1, a_mask_eq_32) node a_mask_acc_32 = or(a_mask_sub_0_1_1, _a_mask_acc_T_32) node a_mask_eq_33 = and(a_mask_sub_0_2_1, a_mask_bit_1) node _a_mask_acc_T_33 = and(a_mask_size_1, a_mask_eq_33) node a_mask_acc_33 = or(a_mask_sub_0_1_1, _a_mask_acc_T_33) node a_mask_eq_34 = and(a_mask_sub_1_2_1, a_mask_nbit_1) node _a_mask_acc_T_34 = and(a_mask_size_1, a_mask_eq_34) node a_mask_acc_34 = or(a_mask_sub_1_1_1, _a_mask_acc_T_34) node a_mask_eq_35 = and(a_mask_sub_1_2_1, a_mask_bit_1) node _a_mask_acc_T_35 = and(a_mask_size_1, a_mask_eq_35) node a_mask_acc_35 = or(a_mask_sub_1_1_1, _a_mask_acc_T_35) node a_mask_eq_36 = and(a_mask_sub_2_2_1, a_mask_nbit_1) node _a_mask_acc_T_36 = and(a_mask_size_1, a_mask_eq_36) node a_mask_acc_36 = or(a_mask_sub_2_1_1, _a_mask_acc_T_36) node a_mask_eq_37 = and(a_mask_sub_2_2_1, a_mask_bit_1) node _a_mask_acc_T_37 = and(a_mask_size_1, a_mask_eq_37) node a_mask_acc_37 = or(a_mask_sub_2_1_1, _a_mask_acc_T_37) node a_mask_eq_38 = and(a_mask_sub_3_2_1, a_mask_nbit_1) node _a_mask_acc_T_38 = and(a_mask_size_1, a_mask_eq_38) node a_mask_acc_38 = or(a_mask_sub_3_1_1, _a_mask_acc_T_38) node a_mask_eq_39 = and(a_mask_sub_3_2_1, a_mask_bit_1) node _a_mask_acc_T_39 = and(a_mask_size_1, a_mask_eq_39) node a_mask_acc_39 = or(a_mask_sub_3_1_1, _a_mask_acc_T_39) node a_mask_eq_40 = and(a_mask_sub_4_2_1, a_mask_nbit_1) node _a_mask_acc_T_40 = and(a_mask_size_1, a_mask_eq_40) node a_mask_acc_40 = or(a_mask_sub_4_1_1, _a_mask_acc_T_40) node a_mask_eq_41 = and(a_mask_sub_4_2_1, a_mask_bit_1) node _a_mask_acc_T_41 = and(a_mask_size_1, a_mask_eq_41) node a_mask_acc_41 = or(a_mask_sub_4_1_1, _a_mask_acc_T_41) node a_mask_eq_42 = and(a_mask_sub_5_2_1, a_mask_nbit_1) node _a_mask_acc_T_42 = and(a_mask_size_1, a_mask_eq_42) node a_mask_acc_42 = or(a_mask_sub_5_1_1, _a_mask_acc_T_42) node a_mask_eq_43 = and(a_mask_sub_5_2_1, a_mask_bit_1) node _a_mask_acc_T_43 = and(a_mask_size_1, a_mask_eq_43) node a_mask_acc_43 = or(a_mask_sub_5_1_1, _a_mask_acc_T_43) node a_mask_eq_44 = and(a_mask_sub_6_2_1, a_mask_nbit_1) node _a_mask_acc_T_44 = and(a_mask_size_1, a_mask_eq_44) node a_mask_acc_44 = or(a_mask_sub_6_1_1, _a_mask_acc_T_44) node a_mask_eq_45 = and(a_mask_sub_6_2_1, a_mask_bit_1) node _a_mask_acc_T_45 = and(a_mask_size_1, a_mask_eq_45) node a_mask_acc_45 = or(a_mask_sub_6_1_1, _a_mask_acc_T_45) node a_mask_eq_46 = and(a_mask_sub_7_2_1, a_mask_nbit_1) node _a_mask_acc_T_46 = and(a_mask_size_1, a_mask_eq_46) node a_mask_acc_46 = or(a_mask_sub_7_1_1, _a_mask_acc_T_46) node a_mask_eq_47 = and(a_mask_sub_7_2_1, a_mask_bit_1) node _a_mask_acc_T_47 = and(a_mask_size_1, a_mask_eq_47) node a_mask_acc_47 = or(a_mask_sub_7_1_1, _a_mask_acc_T_47) node a_mask_eq_48 = and(a_mask_sub_8_2_1, a_mask_nbit_1) node _a_mask_acc_T_48 = and(a_mask_size_1, a_mask_eq_48) node a_mask_acc_48 = or(a_mask_sub_8_1_1, _a_mask_acc_T_48) node a_mask_eq_49 = and(a_mask_sub_8_2_1, a_mask_bit_1) node _a_mask_acc_T_49 = and(a_mask_size_1, a_mask_eq_49) node a_mask_acc_49 = or(a_mask_sub_8_1_1, _a_mask_acc_T_49) node a_mask_eq_50 = and(a_mask_sub_9_2_1, a_mask_nbit_1) node _a_mask_acc_T_50 = and(a_mask_size_1, a_mask_eq_50) node a_mask_acc_50 = or(a_mask_sub_9_1_1, _a_mask_acc_T_50) node a_mask_eq_51 = and(a_mask_sub_9_2_1, a_mask_bit_1) node _a_mask_acc_T_51 = and(a_mask_size_1, a_mask_eq_51) node a_mask_acc_51 = or(a_mask_sub_9_1_1, _a_mask_acc_T_51) node a_mask_eq_52 = and(a_mask_sub_10_2_1, a_mask_nbit_1) node _a_mask_acc_T_52 = and(a_mask_size_1, a_mask_eq_52) node a_mask_acc_52 = or(a_mask_sub_10_1_1, _a_mask_acc_T_52) node a_mask_eq_53 = and(a_mask_sub_10_2_1, a_mask_bit_1) node _a_mask_acc_T_53 = and(a_mask_size_1, a_mask_eq_53) node a_mask_acc_53 = or(a_mask_sub_10_1_1, _a_mask_acc_T_53) node a_mask_eq_54 = and(a_mask_sub_11_2_1, a_mask_nbit_1) node _a_mask_acc_T_54 = and(a_mask_size_1, a_mask_eq_54) node a_mask_acc_54 = or(a_mask_sub_11_1_1, _a_mask_acc_T_54) node a_mask_eq_55 = and(a_mask_sub_11_2_1, a_mask_bit_1) node _a_mask_acc_T_55 = and(a_mask_size_1, a_mask_eq_55) node a_mask_acc_55 = or(a_mask_sub_11_1_1, _a_mask_acc_T_55) node a_mask_eq_56 = and(a_mask_sub_12_2_1, a_mask_nbit_1) node _a_mask_acc_T_56 = and(a_mask_size_1, a_mask_eq_56) node a_mask_acc_56 = or(a_mask_sub_12_1_1, _a_mask_acc_T_56) node a_mask_eq_57 = and(a_mask_sub_12_2_1, a_mask_bit_1) node _a_mask_acc_T_57 = and(a_mask_size_1, a_mask_eq_57) node a_mask_acc_57 = or(a_mask_sub_12_1_1, _a_mask_acc_T_57) node a_mask_eq_58 = and(a_mask_sub_13_2_1, a_mask_nbit_1) node _a_mask_acc_T_58 = and(a_mask_size_1, a_mask_eq_58) node a_mask_acc_58 = or(a_mask_sub_13_1_1, _a_mask_acc_T_58) node a_mask_eq_59 = and(a_mask_sub_13_2_1, a_mask_bit_1) node _a_mask_acc_T_59 = and(a_mask_size_1, a_mask_eq_59) node a_mask_acc_59 = or(a_mask_sub_13_1_1, _a_mask_acc_T_59) node a_mask_eq_60 = and(a_mask_sub_14_2_1, a_mask_nbit_1) node _a_mask_acc_T_60 = and(a_mask_size_1, a_mask_eq_60) node a_mask_acc_60 = or(a_mask_sub_14_1_1, _a_mask_acc_T_60) node a_mask_eq_61 = and(a_mask_sub_14_2_1, a_mask_bit_1) node _a_mask_acc_T_61 = and(a_mask_size_1, a_mask_eq_61) node a_mask_acc_61 = or(a_mask_sub_14_1_1, _a_mask_acc_T_61) node a_mask_eq_62 = and(a_mask_sub_15_2_1, a_mask_nbit_1) node _a_mask_acc_T_62 = and(a_mask_size_1, a_mask_eq_62) node a_mask_acc_62 = or(a_mask_sub_15_1_1, _a_mask_acc_T_62) node a_mask_eq_63 = and(a_mask_sub_15_2_1, a_mask_bit_1) node _a_mask_acc_T_63 = and(a_mask_size_1, a_mask_eq_63) node a_mask_acc_63 = or(a_mask_sub_15_1_1, _a_mask_acc_T_63) node a_mask_lo_lo_lo_lo_1 = cat(a_mask_acc_33, a_mask_acc_32) node a_mask_lo_lo_lo_hi_1 = cat(a_mask_acc_35, a_mask_acc_34) node a_mask_lo_lo_lo_1 = cat(a_mask_lo_lo_lo_hi_1, a_mask_lo_lo_lo_lo_1) node a_mask_lo_lo_hi_lo_1 = cat(a_mask_acc_37, a_mask_acc_36) node a_mask_lo_lo_hi_hi_1 = cat(a_mask_acc_39, a_mask_acc_38) node a_mask_lo_lo_hi_1 = cat(a_mask_lo_lo_hi_hi_1, a_mask_lo_lo_hi_lo_1) node a_mask_lo_lo_1 = cat(a_mask_lo_lo_hi_1, a_mask_lo_lo_lo_1) node a_mask_lo_hi_lo_lo_1 = cat(a_mask_acc_41, a_mask_acc_40) node a_mask_lo_hi_lo_hi_1 = cat(a_mask_acc_43, a_mask_acc_42) node a_mask_lo_hi_lo_1 = cat(a_mask_lo_hi_lo_hi_1, a_mask_lo_hi_lo_lo_1) node a_mask_lo_hi_hi_lo_1 = cat(a_mask_acc_45, a_mask_acc_44) node a_mask_lo_hi_hi_hi_1 = cat(a_mask_acc_47, a_mask_acc_46) node a_mask_lo_hi_hi_1 = cat(a_mask_lo_hi_hi_hi_1, a_mask_lo_hi_hi_lo_1) node a_mask_lo_hi_1 = cat(a_mask_lo_hi_hi_1, a_mask_lo_hi_lo_1) node a_mask_lo_1 = cat(a_mask_lo_hi_1, a_mask_lo_lo_1) node a_mask_hi_lo_lo_lo_1 = cat(a_mask_acc_49, a_mask_acc_48) node a_mask_hi_lo_lo_hi_1 = cat(a_mask_acc_51, a_mask_acc_50) node a_mask_hi_lo_lo_1 = cat(a_mask_hi_lo_lo_hi_1, a_mask_hi_lo_lo_lo_1) node a_mask_hi_lo_hi_lo_1 = cat(a_mask_acc_53, a_mask_acc_52) node a_mask_hi_lo_hi_hi_1 = cat(a_mask_acc_55, a_mask_acc_54) node a_mask_hi_lo_hi_1 = cat(a_mask_hi_lo_hi_hi_1, a_mask_hi_lo_hi_lo_1) node a_mask_hi_lo_1 = cat(a_mask_hi_lo_hi_1, a_mask_hi_lo_lo_1) node a_mask_hi_hi_lo_lo_1 = cat(a_mask_acc_57, a_mask_acc_56) node a_mask_hi_hi_lo_hi_1 = cat(a_mask_acc_59, a_mask_acc_58) node a_mask_hi_hi_lo_1 = cat(a_mask_hi_hi_lo_hi_1, a_mask_hi_hi_lo_lo_1) node a_mask_hi_hi_hi_lo_1 = cat(a_mask_acc_61, a_mask_acc_60) node a_mask_hi_hi_hi_hi_1 = cat(a_mask_acc_63, a_mask_acc_62) node a_mask_hi_hi_hi_1 = cat(a_mask_hi_hi_hi_hi_1, a_mask_hi_hi_hi_lo_1) node a_mask_hi_hi_1 = cat(a_mask_hi_hi_hi_1, a_mask_hi_hi_lo_1) node a_mask_hi_1 = cat(a_mask_hi_hi_1, a_mask_hi_lo_1) node _a_mask_T_1 = cat(a_mask_hi_1, a_mask_lo_1) connect bundle_1.mask, _a_mask_T_1 connect bundle_1.data, _T_31 connect bundle_1.corrupt, UInt<1>(0h0) connect request_latency_injection_q.io.enq.bits.corrupt, bundle_1.corrupt connect request_latency_injection_q.io.enq.bits.data, bundle_1.data connect request_latency_injection_q.io.enq.bits.mask, bundle_1.mask connect request_latency_injection_q.io.enq.bits.address, bundle_1.address connect request_latency_injection_q.io.enq.bits.source, bundle_1.source connect request_latency_injection_q.io.enq.bits.size, bundle_1.size connect request_latency_injection_q.io.enq.bits.param, bundle_1.param connect request_latency_injection_q.io.enq.bits.opcode, bundle_1.opcode else : when request_input.valid : regreset loginfo_cycles_4 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_8 = add(loginfo_cycles_4, UInt<1>(0h1)) node _loginfo_cycles_T_9 = tail(_loginfo_cycles_T_8, 1) connect loginfo_cycles_4, _loginfo_cycles_T_9 node _T_32 = asUInt(reset) node _T_33 = eq(_T_32, UInt<1>(0h0)) when _T_33 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_4) : printf_10 node _T_34 = asUInt(reset) node _T_35 = eq(_T_34, UInt<1>(0h0)) when _T_35 : printf(clock, UInt<1>(0h1), "[seq_writer] ERR") : printf_11 node _T_36 = asUInt(reset) node _T_37 = eq(_T_36, UInt<1>(0h0)) when _T_37 : node _T_38 = eq(UInt<1>(0h0), UInt<1>(0h0)) when _T_38 : printf(clock, UInt<1>(0h1), "Assertion failed: ERR\n at L2MemHelperLatencyInjection.scala:178 assert(false.B, \"ERR\")\n") : printf_12 assert(clock, UInt<1>(0h0), UInt<1>(0h1), "") : assert_2 inst Queue4_L2RespInternal of Queue4_L2RespInternal_306 connect Queue4_L2RespInternal.clock, clock connect Queue4_L2RespInternal.reset, reset inst Queue4_L2RespInternal_1 of Queue4_L2RespInternal_307 connect Queue4_L2RespInternal_1.clock, clock connect Queue4_L2RespInternal_1.reset, reset inst Queue4_L2RespInternal_2 of Queue4_L2RespInternal_308 connect Queue4_L2RespInternal_2.clock, clock connect Queue4_L2RespInternal_2.reset, reset inst Queue4_L2RespInternal_3 of Queue4_L2RespInternal_309 connect Queue4_L2RespInternal_3.clock, clock connect Queue4_L2RespInternal_3.reset, reset inst Queue4_L2RespInternal_4 of Queue4_L2RespInternal_310 connect Queue4_L2RespInternal_4.clock, clock connect Queue4_L2RespInternal_4.reset, reset inst Queue4_L2RespInternal_5 of Queue4_L2RespInternal_311 connect Queue4_L2RespInternal_5.clock, clock connect Queue4_L2RespInternal_5.reset, reset inst Queue4_L2RespInternal_6 of Queue4_L2RespInternal_312 connect Queue4_L2RespInternal_6.clock, clock connect Queue4_L2RespInternal_6.reset, reset inst Queue4_L2RespInternal_7 of Queue4_L2RespInternal_313 connect Queue4_L2RespInternal_7.clock, clock connect Queue4_L2RespInternal_7.reset, reset inst Queue4_L2RespInternal_8 of Queue4_L2RespInternal_314 connect Queue4_L2RespInternal_8.clock, clock connect Queue4_L2RespInternal_8.reset, reset inst Queue4_L2RespInternal_9 of Queue4_L2RespInternal_315 connect Queue4_L2RespInternal_9.clock, clock connect Queue4_L2RespInternal_9.reset, reset inst Queue4_L2RespInternal_10 of Queue4_L2RespInternal_316 connect Queue4_L2RespInternal_10.clock, clock connect Queue4_L2RespInternal_10.reset, reset inst Queue4_L2RespInternal_11 of Queue4_L2RespInternal_317 connect Queue4_L2RespInternal_11.clock, clock connect Queue4_L2RespInternal_11.reset, reset inst Queue4_L2RespInternal_12 of Queue4_L2RespInternal_318 connect Queue4_L2RespInternal_12.clock, clock connect Queue4_L2RespInternal_12.reset, reset inst Queue4_L2RespInternal_13 of Queue4_L2RespInternal_319 connect Queue4_L2RespInternal_13.clock, clock connect Queue4_L2RespInternal_13.reset, reset inst Queue4_L2RespInternal_14 of Queue4_L2RespInternal_320 connect Queue4_L2RespInternal_14.clock, clock connect Queue4_L2RespInternal_14.reset, reset inst Queue4_L2RespInternal_15 of Queue4_L2RespInternal_321 connect Queue4_L2RespInternal_15.clock, clock connect Queue4_L2RespInternal_15.reset, reset inst Queue4_L2RespInternal_16 of Queue4_L2RespInternal_322 connect Queue4_L2RespInternal_16.clock, clock connect Queue4_L2RespInternal_16.reset, reset inst Queue4_L2RespInternal_17 of Queue4_L2RespInternal_323 connect Queue4_L2RespInternal_17.clock, clock connect Queue4_L2RespInternal_17.reset, reset inst Queue4_L2RespInternal_18 of Queue4_L2RespInternal_324 connect Queue4_L2RespInternal_18.clock, clock connect Queue4_L2RespInternal_18.reset, reset inst Queue4_L2RespInternal_19 of Queue4_L2RespInternal_325 connect Queue4_L2RespInternal_19.clock, clock connect Queue4_L2RespInternal_19.reset, reset inst Queue4_L2RespInternal_20 of Queue4_L2RespInternal_326 connect Queue4_L2RespInternal_20.clock, clock connect Queue4_L2RespInternal_20.reset, reset inst Queue4_L2RespInternal_21 of Queue4_L2RespInternal_327 connect Queue4_L2RespInternal_21.clock, clock connect Queue4_L2RespInternal_21.reset, reset inst Queue4_L2RespInternal_22 of Queue4_L2RespInternal_328 connect Queue4_L2RespInternal_22.clock, clock connect Queue4_L2RespInternal_22.reset, reset inst Queue4_L2RespInternal_23 of Queue4_L2RespInternal_329 connect Queue4_L2RespInternal_23.clock, clock connect Queue4_L2RespInternal_23.reset, reset inst Queue4_L2RespInternal_24 of Queue4_L2RespInternal_330 connect Queue4_L2RespInternal_24.clock, clock connect Queue4_L2RespInternal_24.reset, reset inst Queue4_L2RespInternal_25 of Queue4_L2RespInternal_331 connect Queue4_L2RespInternal_25.clock, clock connect Queue4_L2RespInternal_25.reset, reset inst Queue4_L2RespInternal_26 of Queue4_L2RespInternal_332 connect Queue4_L2RespInternal_26.clock, clock connect Queue4_L2RespInternal_26.reset, reset inst Queue4_L2RespInternal_27 of Queue4_L2RespInternal_333 connect Queue4_L2RespInternal_27.clock, clock connect Queue4_L2RespInternal_27.reset, reset inst Queue4_L2RespInternal_28 of Queue4_L2RespInternal_334 connect Queue4_L2RespInternal_28.clock, clock connect Queue4_L2RespInternal_28.reset, reset inst Queue4_L2RespInternal_29 of Queue4_L2RespInternal_335 connect Queue4_L2RespInternal_29.clock, clock connect Queue4_L2RespInternal_29.reset, reset inst Queue4_L2RespInternal_30 of Queue4_L2RespInternal_336 connect Queue4_L2RespInternal_30.clock, clock connect Queue4_L2RespInternal_30.reset, reset inst Queue4_L2RespInternal_31 of Queue4_L2RespInternal_337 connect Queue4_L2RespInternal_31.clock, clock connect Queue4_L2RespInternal_31.reset, reset node _current_request_tag_has_response_space_T = eq(UInt<1>(0h0), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_1 = and(Queue4_L2RespInternal.io.enq.ready, _current_request_tag_has_response_space_T) node _current_request_tag_has_response_space_T_2 = eq(UInt<1>(0h1), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_3 = and(Queue4_L2RespInternal_1.io.enq.ready, _current_request_tag_has_response_space_T_2) node _current_request_tag_has_response_space_T_4 = eq(UInt<2>(0h2), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_5 = and(Queue4_L2RespInternal_2.io.enq.ready, _current_request_tag_has_response_space_T_4) node _current_request_tag_has_response_space_T_6 = eq(UInt<2>(0h3), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_7 = and(Queue4_L2RespInternal_3.io.enq.ready, _current_request_tag_has_response_space_T_6) node _current_request_tag_has_response_space_T_8 = eq(UInt<3>(0h4), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_9 = and(Queue4_L2RespInternal_4.io.enq.ready, _current_request_tag_has_response_space_T_8) node _current_request_tag_has_response_space_T_10 = eq(UInt<3>(0h5), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_11 = and(Queue4_L2RespInternal_5.io.enq.ready, _current_request_tag_has_response_space_T_10) node _current_request_tag_has_response_space_T_12 = eq(UInt<3>(0h6), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_13 = and(Queue4_L2RespInternal_6.io.enq.ready, _current_request_tag_has_response_space_T_12) node _current_request_tag_has_response_space_T_14 = eq(UInt<3>(0h7), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_15 = and(Queue4_L2RespInternal_7.io.enq.ready, _current_request_tag_has_response_space_T_14) node _current_request_tag_has_response_space_T_16 = eq(UInt<4>(0h8), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_17 = and(Queue4_L2RespInternal_8.io.enq.ready, _current_request_tag_has_response_space_T_16) node _current_request_tag_has_response_space_T_18 = eq(UInt<4>(0h9), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_19 = and(Queue4_L2RespInternal_9.io.enq.ready, _current_request_tag_has_response_space_T_18) node _current_request_tag_has_response_space_T_20 = eq(UInt<4>(0ha), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_21 = and(Queue4_L2RespInternal_10.io.enq.ready, _current_request_tag_has_response_space_T_20) node _current_request_tag_has_response_space_T_22 = eq(UInt<4>(0hb), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_23 = and(Queue4_L2RespInternal_11.io.enq.ready, _current_request_tag_has_response_space_T_22) node _current_request_tag_has_response_space_T_24 = eq(UInt<4>(0hc), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_25 = and(Queue4_L2RespInternal_12.io.enq.ready, _current_request_tag_has_response_space_T_24) node _current_request_tag_has_response_space_T_26 = eq(UInt<4>(0hd), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_27 = and(Queue4_L2RespInternal_13.io.enq.ready, _current_request_tag_has_response_space_T_26) node _current_request_tag_has_response_space_T_28 = eq(UInt<4>(0he), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_29 = and(Queue4_L2RespInternal_14.io.enq.ready, _current_request_tag_has_response_space_T_28) node _current_request_tag_has_response_space_T_30 = eq(UInt<4>(0hf), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_31 = and(Queue4_L2RespInternal_15.io.enq.ready, _current_request_tag_has_response_space_T_30) node _current_request_tag_has_response_space_T_32 = eq(UInt<5>(0h10), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_33 = and(Queue4_L2RespInternal_16.io.enq.ready, _current_request_tag_has_response_space_T_32) node _current_request_tag_has_response_space_T_34 = eq(UInt<5>(0h11), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_35 = and(Queue4_L2RespInternal_17.io.enq.ready, _current_request_tag_has_response_space_T_34) node _current_request_tag_has_response_space_T_36 = eq(UInt<5>(0h12), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_37 = and(Queue4_L2RespInternal_18.io.enq.ready, _current_request_tag_has_response_space_T_36) node _current_request_tag_has_response_space_T_38 = eq(UInt<5>(0h13), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_39 = and(Queue4_L2RespInternal_19.io.enq.ready, _current_request_tag_has_response_space_T_38) node _current_request_tag_has_response_space_T_40 = eq(UInt<5>(0h14), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_41 = and(Queue4_L2RespInternal_20.io.enq.ready, _current_request_tag_has_response_space_T_40) node _current_request_tag_has_response_space_T_42 = eq(UInt<5>(0h15), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_43 = and(Queue4_L2RespInternal_21.io.enq.ready, _current_request_tag_has_response_space_T_42) node _current_request_tag_has_response_space_T_44 = eq(UInt<5>(0h16), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_45 = and(Queue4_L2RespInternal_22.io.enq.ready, _current_request_tag_has_response_space_T_44) node _current_request_tag_has_response_space_T_46 = eq(UInt<5>(0h17), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_47 = and(Queue4_L2RespInternal_23.io.enq.ready, _current_request_tag_has_response_space_T_46) node _current_request_tag_has_response_space_T_48 = eq(UInt<5>(0h18), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_49 = and(Queue4_L2RespInternal_24.io.enq.ready, _current_request_tag_has_response_space_T_48) node _current_request_tag_has_response_space_T_50 = eq(UInt<5>(0h19), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_51 = and(Queue4_L2RespInternal_25.io.enq.ready, _current_request_tag_has_response_space_T_50) node _current_request_tag_has_response_space_T_52 = eq(UInt<5>(0h1a), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_53 = and(Queue4_L2RespInternal_26.io.enq.ready, _current_request_tag_has_response_space_T_52) node _current_request_tag_has_response_space_T_54 = eq(UInt<5>(0h1b), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_55 = and(Queue4_L2RespInternal_27.io.enq.ready, _current_request_tag_has_response_space_T_54) node _current_request_tag_has_response_space_T_56 = eq(UInt<5>(0h1c), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_57 = and(Queue4_L2RespInternal_28.io.enq.ready, _current_request_tag_has_response_space_T_56) node _current_request_tag_has_response_space_T_58 = eq(UInt<5>(0h1d), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_59 = and(Queue4_L2RespInternal_29.io.enq.ready, _current_request_tag_has_response_space_T_58) node _current_request_tag_has_response_space_T_60 = eq(UInt<5>(0h1e), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_61 = and(Queue4_L2RespInternal_30.io.enq.ready, _current_request_tag_has_response_space_T_60) node _current_request_tag_has_response_space_T_62 = eq(UInt<5>(0h1f), tags_for_issue_Q.io.deq.bits) node _current_request_tag_has_response_space_T_63 = and(Queue4_L2RespInternal_31.io.enq.ready, _current_request_tag_has_response_space_T_62) node _current_request_tag_has_response_space_T_64 = or(_current_request_tag_has_response_space_T_1, _current_request_tag_has_response_space_T_3) node _current_request_tag_has_response_space_T_65 = or(_current_request_tag_has_response_space_T_64, _current_request_tag_has_response_space_T_5) node _current_request_tag_has_response_space_T_66 = or(_current_request_tag_has_response_space_T_65, _current_request_tag_has_response_space_T_7) node _current_request_tag_has_response_space_T_67 = or(_current_request_tag_has_response_space_T_66, _current_request_tag_has_response_space_T_9) node _current_request_tag_has_response_space_T_68 = or(_current_request_tag_has_response_space_T_67, _current_request_tag_has_response_space_T_11) node _current_request_tag_has_response_space_T_69 = or(_current_request_tag_has_response_space_T_68, _current_request_tag_has_response_space_T_13) node _current_request_tag_has_response_space_T_70 = or(_current_request_tag_has_response_space_T_69, _current_request_tag_has_response_space_T_15) node _current_request_tag_has_response_space_T_71 = or(_current_request_tag_has_response_space_T_70, _current_request_tag_has_response_space_T_17) node _current_request_tag_has_response_space_T_72 = or(_current_request_tag_has_response_space_T_71, _current_request_tag_has_response_space_T_19) node _current_request_tag_has_response_space_T_73 = or(_current_request_tag_has_response_space_T_72, _current_request_tag_has_response_space_T_21) node _current_request_tag_has_response_space_T_74 = or(_current_request_tag_has_response_space_T_73, _current_request_tag_has_response_space_T_23) node _current_request_tag_has_response_space_T_75 = or(_current_request_tag_has_response_space_T_74, _current_request_tag_has_response_space_T_25) node _current_request_tag_has_response_space_T_76 = or(_current_request_tag_has_response_space_T_75, _current_request_tag_has_response_space_T_27) node _current_request_tag_has_response_space_T_77 = or(_current_request_tag_has_response_space_T_76, _current_request_tag_has_response_space_T_29) node _current_request_tag_has_response_space_T_78 = or(_current_request_tag_has_response_space_T_77, _current_request_tag_has_response_space_T_31) node _current_request_tag_has_response_space_T_79 = or(_current_request_tag_has_response_space_T_78, _current_request_tag_has_response_space_T_33) node _current_request_tag_has_response_space_T_80 = or(_current_request_tag_has_response_space_T_79, _current_request_tag_has_response_space_T_35) node _current_request_tag_has_response_space_T_81 = or(_current_request_tag_has_response_space_T_80, _current_request_tag_has_response_space_T_37) node _current_request_tag_has_response_space_T_82 = or(_current_request_tag_has_response_space_T_81, _current_request_tag_has_response_space_T_39) node _current_request_tag_has_response_space_T_83 = or(_current_request_tag_has_response_space_T_82, _current_request_tag_has_response_space_T_41) node _current_request_tag_has_response_space_T_84 = or(_current_request_tag_has_response_space_T_83, _current_request_tag_has_response_space_T_43) node _current_request_tag_has_response_space_T_85 = or(_current_request_tag_has_response_space_T_84, _current_request_tag_has_response_space_T_45) node _current_request_tag_has_response_space_T_86 = or(_current_request_tag_has_response_space_T_85, _current_request_tag_has_response_space_T_47) node _current_request_tag_has_response_space_T_87 = or(_current_request_tag_has_response_space_T_86, _current_request_tag_has_response_space_T_49) node _current_request_tag_has_response_space_T_88 = or(_current_request_tag_has_response_space_T_87, _current_request_tag_has_response_space_T_51) node _current_request_tag_has_response_space_T_89 = or(_current_request_tag_has_response_space_T_88, _current_request_tag_has_response_space_T_53) node _current_request_tag_has_response_space_T_90 = or(_current_request_tag_has_response_space_T_89, _current_request_tag_has_response_space_T_55) node _current_request_tag_has_response_space_T_91 = or(_current_request_tag_has_response_space_T_90, _current_request_tag_has_response_space_T_57) node _current_request_tag_has_response_space_T_92 = or(_current_request_tag_has_response_space_T_91, _current_request_tag_has_response_space_T_59) node _current_request_tag_has_response_space_T_93 = or(_current_request_tag_has_response_space_T_92, _current_request_tag_has_response_space_T_61) node current_request_tag_has_response_space = or(_current_request_tag_has_response_space_T_93, _current_request_tag_has_response_space_T_63) node _outstanding_req_addr_io_enq_bits_addrindex_T = and(request_input.bits.addr, UInt<5>(0h1f)) connect outstanding_req_addr.io.enq.bits.addrindex, _outstanding_req_addr_io_enq_bits_addrindex_T connect outstanding_req_addr.io.enq.bits.tag, tags_for_issue_Q.io.deq.bits node _request_latency_injection_q_io_enq_valid_T = and(request_input.valid, tlb_ready) node _request_latency_injection_q_io_enq_valid_T_1 = and(_request_latency_injection_q_io_enq_valid_T, outstanding_req_addr.io.enq.ready) node _request_latency_injection_q_io_enq_valid_T_2 = and(_request_latency_injection_q_io_enq_valid_T_1, free_outstanding_op_slots) node _request_latency_injection_q_io_enq_valid_T_3 = and(_request_latency_injection_q_io_enq_valid_T_2, tags_for_issue_Q.io.deq.valid) node _request_latency_injection_q_io_enq_valid_T_4 = and(_request_latency_injection_q_io_enq_valid_T_3, current_request_tag_has_response_space) connect request_latency_injection_q.io.enq.valid, _request_latency_injection_q_io_enq_valid_T_4 node _request_input_ready_T = and(request_latency_injection_q.io.enq.ready, tlb_ready) node _request_input_ready_T_1 = and(_request_input_ready_T, outstanding_req_addr.io.enq.ready) node _request_input_ready_T_2 = and(_request_input_ready_T_1, free_outstanding_op_slots) node _request_input_ready_T_3 = and(_request_input_ready_T_2, tags_for_issue_Q.io.deq.valid) node _request_input_ready_T_4 = and(_request_input_ready_T_3, current_request_tag_has_response_space) connect request_input.ready, _request_input_ready_T_4 node _outstanding_req_addr_io_enq_valid_T = and(request_input.valid, request_latency_injection_q.io.enq.ready) node _outstanding_req_addr_io_enq_valid_T_1 = and(_outstanding_req_addr_io_enq_valid_T, tlb_ready) node _outstanding_req_addr_io_enq_valid_T_2 = and(_outstanding_req_addr_io_enq_valid_T_1, free_outstanding_op_slots) node _outstanding_req_addr_io_enq_valid_T_3 = and(_outstanding_req_addr_io_enq_valid_T_2, tags_for_issue_Q.io.deq.valid) node _outstanding_req_addr_io_enq_valid_T_4 = and(_outstanding_req_addr_io_enq_valid_T_3, current_request_tag_has_response_space) connect outstanding_req_addr.io.enq.valid, _outstanding_req_addr_io_enq_valid_T_4 node _tags_for_issue_Q_io_deq_ready_T = and(request_input.valid, request_latency_injection_q.io.enq.ready) node _tags_for_issue_Q_io_deq_ready_T_1 = and(_tags_for_issue_Q_io_deq_ready_T, tlb_ready) node _tags_for_issue_Q_io_deq_ready_T_2 = and(_tags_for_issue_Q_io_deq_ready_T_1, outstanding_req_addr.io.enq.ready) node _tags_for_issue_Q_io_deq_ready_T_3 = and(_tags_for_issue_Q_io_deq_ready_T_2, free_outstanding_op_slots) node _tags_for_issue_Q_io_deq_ready_T_4 = and(_tags_for_issue_Q_io_deq_ready_T_3, current_request_tag_has_response_space) connect tags_for_issue_Q.io.deq.ready, _tags_for_issue_Q_io_deq_ready_T_4 connect masterNodeOut.a.bits, request_latency_injection_q.io.deq.bits connect masterNodeOut.a.valid, request_latency_injection_q.io.deq.valid connect request_latency_injection_q.io.deq.ready, masterNodeOut.a.ready node _T_39 = and(masterNodeOut.a.ready, masterNodeOut.a.valid) when _T_39 : node _T_40 = eq(request_input.bits.cmd, UInt<1>(0h0)) when _T_40 : regreset loginfo_cycles_5 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_10 = add(loginfo_cycles_5, UInt<1>(0h1)) node _loginfo_cycles_T_11 = tail(_loginfo_cycles_T_10, 1) connect loginfo_cycles_5, _loginfo_cycles_T_11 node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_5) : printf_13 node _T_43 = asUInt(reset) node _T_44 = eq(_T_43, UInt<1>(0h0)) when _T_44 : printf(clock, UInt<1>(0h1), "[seq_writer] L2IF: req(read) vaddr: 0x%x, paddr: 0x%x, wid: 0x%x, opnum: %d, sendtag: %d\n", request_input.bits.addr, tlb.io.resp.paddr, request_input.bits.size, global_memop_sent, tags_for_issue_Q.io.deq.bits) : printf_14 node _T_45 = and(request_input.valid, request_latency_injection_q.io.enq.ready) node _T_46 = and(_T_45, tlb_ready) node _T_47 = and(_T_46, outstanding_req_addr.io.enq.ready) node _T_48 = and(_T_47, free_outstanding_op_slots) node _T_49 = and(_T_48, tags_for_issue_Q.io.deq.valid) node _T_50 = and(_T_49, current_request_tag_has_response_space) when _T_50 : node _T_51 = eq(request_input.bits.cmd, UInt<1>(0h1)) when _T_51 : regreset loginfo_cycles_6 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_12 = add(loginfo_cycles_6, UInt<1>(0h1)) node _loginfo_cycles_T_13 = tail(_loginfo_cycles_T_12, 1) connect loginfo_cycles_6, _loginfo_cycles_T_13 node _printf_T = asUInt(reset) node _printf_T_1 = eq(_printf_T, UInt<1>(0h0)) when _printf_T_1 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_6) : printf_15 node _T_52 = asUInt(reset) node _T_53 = eq(_T_52, UInt<1>(0h0)) when _T_53 : printf(clock, UInt<1>(0h1), "") : printf_16 node _printf_T_2 = asUInt(reset) node _printf_T_3 = eq(_printf_T_2, UInt<1>(0h0)) when _printf_T_3 : printf(clock, UInt<1>(0h1), "[seq_writer] L2IF: req(write) vaddr: 0x%x, paddr: 0x%x, wid: 0x%x, data: 0x%x, opnum: %d, sendtag: %d\n", request_input.bits.addr, tlb.io.resp.paddr, request_input.bits.size, request_input.bits.data, global_memop_sent, tags_for_issue_Q.io.deq.bits) : printf_17 node _T_54 = asUInt(reset) node _T_55 = eq(_T_54, UInt<1>(0h0)) when _T_55 : printf(clock, UInt<1>(0h1), "") : printf_18 node _T_56 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_57 = lt(UInt<1>(0h0), _T_56) when _T_57 : node _T_58 = add(request_input.bits.addr, UInt<1>(0h0)) node _T_59 = tail(_T_58, 1) node _T_60 = dshr(request_input.bits.data, UInt<1>(0h0)) node _T_61 = bits(_T_60, 7, 0) regreset loginfo_cycles_7 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_14 = add(loginfo_cycles_7, UInt<1>(0h1)) node _loginfo_cycles_T_15 = tail(_loginfo_cycles_T_14, 1) connect loginfo_cycles_7, _loginfo_cycles_T_15 node _T_62 = asUInt(reset) node _T_63 = eq(_T_62, UInt<1>(0h0)) when _T_63 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_7) : printf_19 node _T_64 = asUInt(reset) node _T_65 = eq(_T_64, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [seq_writer]\n", _T_59, _T_61) : printf_20 node _T_66 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_67 = lt(UInt<1>(0h1), _T_66) when _T_67 : node _T_68 = add(request_input.bits.addr, UInt<1>(0h1)) node _T_69 = tail(_T_68, 1) node _T_70 = dshr(request_input.bits.data, UInt<4>(0h8)) node _T_71 = bits(_T_70, 7, 0) regreset loginfo_cycles_8 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_16 = add(loginfo_cycles_8, UInt<1>(0h1)) node _loginfo_cycles_T_17 = tail(_loginfo_cycles_T_16, 1) connect loginfo_cycles_8, _loginfo_cycles_T_17 node _T_72 = asUInt(reset) node _T_73 = eq(_T_72, UInt<1>(0h0)) when _T_73 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_8) : printf_21 node _T_74 = asUInt(reset) node _T_75 = eq(_T_74, UInt<1>(0h0)) when _T_75 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [seq_writer]\n", _T_69, _T_71) : printf_22 node _T_76 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_77 = lt(UInt<2>(0h2), _T_76) when _T_77 : node _T_78 = add(request_input.bits.addr, UInt<2>(0h2)) node _T_79 = tail(_T_78, 1) node _T_80 = dshr(request_input.bits.data, UInt<5>(0h10)) node _T_81 = bits(_T_80, 7, 0) regreset loginfo_cycles_9 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_18 = add(loginfo_cycles_9, UInt<1>(0h1)) node _loginfo_cycles_T_19 = tail(_loginfo_cycles_T_18, 1) connect loginfo_cycles_9, _loginfo_cycles_T_19 node _T_82 = asUInt(reset) node _T_83 = eq(_T_82, UInt<1>(0h0)) when _T_83 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_9) : printf_23 node _T_84 = asUInt(reset) node _T_85 = eq(_T_84, UInt<1>(0h0)) when _T_85 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [seq_writer]\n", _T_79, _T_81) : printf_24 node _T_86 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_87 = lt(UInt<2>(0h3), _T_86) when _T_87 : node _T_88 = add(request_input.bits.addr, UInt<2>(0h3)) node _T_89 = tail(_T_88, 1) node _T_90 = dshr(request_input.bits.data, UInt<5>(0h18)) node _T_91 = bits(_T_90, 7, 0) regreset loginfo_cycles_10 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_20 = add(loginfo_cycles_10, UInt<1>(0h1)) node _loginfo_cycles_T_21 = tail(_loginfo_cycles_T_20, 1) connect loginfo_cycles_10, _loginfo_cycles_T_21 node _T_92 = asUInt(reset) node _T_93 = eq(_T_92, UInt<1>(0h0)) when _T_93 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_10) : printf_25 node _T_94 = asUInt(reset) node _T_95 = eq(_T_94, UInt<1>(0h0)) when _T_95 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [seq_writer]\n", _T_89, _T_91) : printf_26 node _T_96 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_97 = lt(UInt<3>(0h4), _T_96) when _T_97 : node _T_98 = add(request_input.bits.addr, UInt<3>(0h4)) node _T_99 = tail(_T_98, 1) node _T_100 = dshr(request_input.bits.data, UInt<6>(0h20)) node _T_101 = bits(_T_100, 7, 0) regreset loginfo_cycles_11 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_22 = add(loginfo_cycles_11, UInt<1>(0h1)) node _loginfo_cycles_T_23 = tail(_loginfo_cycles_T_22, 1) connect loginfo_cycles_11, _loginfo_cycles_T_23 node _T_102 = asUInt(reset) node _T_103 = eq(_T_102, UInt<1>(0h0)) when _T_103 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_11) : printf_27 node _T_104 = asUInt(reset) node _T_105 = eq(_T_104, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [seq_writer]\n", _T_99, _T_101) : printf_28 node _T_106 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_107 = lt(UInt<3>(0h5), _T_106) when _T_107 : node _T_108 = add(request_input.bits.addr, UInt<3>(0h5)) node _T_109 = tail(_T_108, 1) node _T_110 = dshr(request_input.bits.data, UInt<6>(0h28)) node _T_111 = bits(_T_110, 7, 0) regreset loginfo_cycles_12 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_24 = add(loginfo_cycles_12, UInt<1>(0h1)) node _loginfo_cycles_T_25 = tail(_loginfo_cycles_T_24, 1) connect loginfo_cycles_12, _loginfo_cycles_T_25 node _T_112 = asUInt(reset) node _T_113 = eq(_T_112, UInt<1>(0h0)) when _T_113 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_12) : printf_29 node _T_114 = asUInt(reset) node _T_115 = eq(_T_114, UInt<1>(0h0)) when _T_115 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [seq_writer]\n", _T_109, _T_111) : printf_30 node _T_116 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_117 = lt(UInt<3>(0h6), _T_116) when _T_117 : node _T_118 = add(request_input.bits.addr, UInt<3>(0h6)) node _T_119 = tail(_T_118, 1) node _T_120 = dshr(request_input.bits.data, UInt<6>(0h30)) node _T_121 = bits(_T_120, 7, 0) regreset loginfo_cycles_13 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_26 = add(loginfo_cycles_13, UInt<1>(0h1)) node _loginfo_cycles_T_27 = tail(_loginfo_cycles_T_26, 1) connect loginfo_cycles_13, _loginfo_cycles_T_27 node _T_122 = asUInt(reset) node _T_123 = eq(_T_122, UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_13) : printf_31 node _T_124 = asUInt(reset) node _T_125 = eq(_T_124, UInt<1>(0h0)) when _T_125 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [seq_writer]\n", _T_119, _T_121) : printf_32 node _T_126 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_127 = lt(UInt<3>(0h7), _T_126) when _T_127 : node _T_128 = add(request_input.bits.addr, UInt<3>(0h7)) node _T_129 = tail(_T_128, 1) node _T_130 = dshr(request_input.bits.data, UInt<6>(0h38)) node _T_131 = bits(_T_130, 7, 0) regreset loginfo_cycles_14 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_28 = add(loginfo_cycles_14, UInt<1>(0h1)) node _loginfo_cycles_T_29 = tail(_loginfo_cycles_T_28, 1) connect loginfo_cycles_14, _loginfo_cycles_T_29 node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_14) : printf_33 node _T_134 = asUInt(reset) node _T_135 = eq(_T_134, UInt<1>(0h0)) when _T_135 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [seq_writer]\n", _T_129, _T_131) : printf_34 node _T_136 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_137 = lt(UInt<4>(0h8), _T_136) when _T_137 : node _T_138 = add(request_input.bits.addr, UInt<4>(0h8)) node _T_139 = tail(_T_138, 1) node _T_140 = dshr(request_input.bits.data, UInt<7>(0h40)) node _T_141 = bits(_T_140, 7, 0) regreset loginfo_cycles_15 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_30 = add(loginfo_cycles_15, UInt<1>(0h1)) node _loginfo_cycles_T_31 = tail(_loginfo_cycles_T_30, 1) connect loginfo_cycles_15, _loginfo_cycles_T_31 node _T_142 = asUInt(reset) node _T_143 = eq(_T_142, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_15) : printf_35 node _T_144 = asUInt(reset) node _T_145 = eq(_T_144, UInt<1>(0h0)) when _T_145 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [seq_writer]\n", _T_139, _T_141) : printf_36 node _T_146 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_147 = lt(UInt<4>(0h9), _T_146) when _T_147 : node _T_148 = add(request_input.bits.addr, UInt<4>(0h9)) node _T_149 = tail(_T_148, 1) node _T_150 = dshr(request_input.bits.data, UInt<7>(0h48)) node _T_151 = bits(_T_150, 7, 0) regreset loginfo_cycles_16 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_32 = add(loginfo_cycles_16, UInt<1>(0h1)) node _loginfo_cycles_T_33 = tail(_loginfo_cycles_T_32, 1) connect loginfo_cycles_16, _loginfo_cycles_T_33 node _T_152 = asUInt(reset) node _T_153 = eq(_T_152, UInt<1>(0h0)) when _T_153 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_16) : printf_37 node _T_154 = asUInt(reset) node _T_155 = eq(_T_154, UInt<1>(0h0)) when _T_155 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [seq_writer]\n", _T_149, _T_151) : printf_38 node _T_156 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_157 = lt(UInt<4>(0ha), _T_156) when _T_157 : node _T_158 = add(request_input.bits.addr, UInt<4>(0ha)) node _T_159 = tail(_T_158, 1) node _T_160 = dshr(request_input.bits.data, UInt<7>(0h50)) node _T_161 = bits(_T_160, 7, 0) regreset loginfo_cycles_17 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_34 = add(loginfo_cycles_17, UInt<1>(0h1)) node _loginfo_cycles_T_35 = tail(_loginfo_cycles_T_34, 1) connect loginfo_cycles_17, _loginfo_cycles_T_35 node _T_162 = asUInt(reset) node _T_163 = eq(_T_162, UInt<1>(0h0)) when _T_163 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_17) : printf_39 node _T_164 = asUInt(reset) node _T_165 = eq(_T_164, UInt<1>(0h0)) when _T_165 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [seq_writer]\n", _T_159, _T_161) : printf_40 node _T_166 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_167 = lt(UInt<4>(0hb), _T_166) when _T_167 : node _T_168 = add(request_input.bits.addr, UInt<4>(0hb)) node _T_169 = tail(_T_168, 1) node _T_170 = dshr(request_input.bits.data, UInt<7>(0h58)) node _T_171 = bits(_T_170, 7, 0) regreset loginfo_cycles_18 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_36 = add(loginfo_cycles_18, UInt<1>(0h1)) node _loginfo_cycles_T_37 = tail(_loginfo_cycles_T_36, 1) connect loginfo_cycles_18, _loginfo_cycles_T_37 node _T_172 = asUInt(reset) node _T_173 = eq(_T_172, UInt<1>(0h0)) when _T_173 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_18) : printf_41 node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [seq_writer]\n", _T_169, _T_171) : printf_42 node _T_176 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_177 = lt(UInt<4>(0hc), _T_176) when _T_177 : node _T_178 = add(request_input.bits.addr, UInt<4>(0hc)) node _T_179 = tail(_T_178, 1) node _T_180 = dshr(request_input.bits.data, UInt<7>(0h60)) node _T_181 = bits(_T_180, 7, 0) regreset loginfo_cycles_19 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_38 = add(loginfo_cycles_19, UInt<1>(0h1)) node _loginfo_cycles_T_39 = tail(_loginfo_cycles_T_38, 1) connect loginfo_cycles_19, _loginfo_cycles_T_39 node _T_182 = asUInt(reset) node _T_183 = eq(_T_182, UInt<1>(0h0)) when _T_183 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_19) : printf_43 node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [seq_writer]\n", _T_179, _T_181) : printf_44 node _T_186 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_187 = lt(UInt<4>(0hd), _T_186) when _T_187 : node _T_188 = add(request_input.bits.addr, UInt<4>(0hd)) node _T_189 = tail(_T_188, 1) node _T_190 = dshr(request_input.bits.data, UInt<7>(0h68)) node _T_191 = bits(_T_190, 7, 0) regreset loginfo_cycles_20 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_40 = add(loginfo_cycles_20, UInt<1>(0h1)) node _loginfo_cycles_T_41 = tail(_loginfo_cycles_T_40, 1) connect loginfo_cycles_20, _loginfo_cycles_T_41 node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_20) : printf_45 node _T_194 = asUInt(reset) node _T_195 = eq(_T_194, UInt<1>(0h0)) when _T_195 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [seq_writer]\n", _T_189, _T_191) : printf_46 node _T_196 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_197 = lt(UInt<4>(0he), _T_196) when _T_197 : node _T_198 = add(request_input.bits.addr, UInt<4>(0he)) node _T_199 = tail(_T_198, 1) node _T_200 = dshr(request_input.bits.data, UInt<7>(0h70)) node _T_201 = bits(_T_200, 7, 0) regreset loginfo_cycles_21 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_42 = add(loginfo_cycles_21, UInt<1>(0h1)) node _loginfo_cycles_T_43 = tail(_loginfo_cycles_T_42, 1) connect loginfo_cycles_21, _loginfo_cycles_T_43 node _T_202 = asUInt(reset) node _T_203 = eq(_T_202, UInt<1>(0h0)) when _T_203 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_21) : printf_47 node _T_204 = asUInt(reset) node _T_205 = eq(_T_204, UInt<1>(0h0)) when _T_205 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [seq_writer]\n", _T_199, _T_201) : printf_48 node _T_206 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_207 = lt(UInt<4>(0hf), _T_206) when _T_207 : node _T_208 = add(request_input.bits.addr, UInt<4>(0hf)) node _T_209 = tail(_T_208, 1) node _T_210 = dshr(request_input.bits.data, UInt<7>(0h78)) node _T_211 = bits(_T_210, 7, 0) regreset loginfo_cycles_22 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_44 = add(loginfo_cycles_22, UInt<1>(0h1)) node _loginfo_cycles_T_45 = tail(_loginfo_cycles_T_44, 1) connect loginfo_cycles_22, _loginfo_cycles_T_45 node _T_212 = asUInt(reset) node _T_213 = eq(_T_212, UInt<1>(0h0)) when _T_213 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_22) : printf_49 node _T_214 = asUInt(reset) node _T_215 = eq(_T_214, UInt<1>(0h0)) when _T_215 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [seq_writer]\n", _T_209, _T_211) : printf_50 node _T_216 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_217 = lt(UInt<5>(0h10), _T_216) when _T_217 : node _T_218 = add(request_input.bits.addr, UInt<5>(0h10)) node _T_219 = tail(_T_218, 1) node _T_220 = dshr(request_input.bits.data, UInt<8>(0h80)) node _T_221 = bits(_T_220, 7, 0) regreset loginfo_cycles_23 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_46 = add(loginfo_cycles_23, UInt<1>(0h1)) node _loginfo_cycles_T_47 = tail(_loginfo_cycles_T_46, 1) connect loginfo_cycles_23, _loginfo_cycles_T_47 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_23) : printf_51 node _T_224 = asUInt(reset) node _T_225 = eq(_T_224, UInt<1>(0h0)) when _T_225 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [seq_writer]\n", _T_219, _T_221) : printf_52 node _T_226 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_227 = lt(UInt<5>(0h11), _T_226) when _T_227 : node _T_228 = add(request_input.bits.addr, UInt<5>(0h11)) node _T_229 = tail(_T_228, 1) node _T_230 = dshr(request_input.bits.data, UInt<8>(0h88)) node _T_231 = bits(_T_230, 7, 0) regreset loginfo_cycles_24 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_48 = add(loginfo_cycles_24, UInt<1>(0h1)) node _loginfo_cycles_T_49 = tail(_loginfo_cycles_T_48, 1) connect loginfo_cycles_24, _loginfo_cycles_T_49 node _T_232 = asUInt(reset) node _T_233 = eq(_T_232, UInt<1>(0h0)) when _T_233 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_24) : printf_53 node _T_234 = asUInt(reset) node _T_235 = eq(_T_234, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [seq_writer]\n", _T_229, _T_231) : printf_54 node _T_236 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_237 = lt(UInt<5>(0h12), _T_236) when _T_237 : node _T_238 = add(request_input.bits.addr, UInt<5>(0h12)) node _T_239 = tail(_T_238, 1) node _T_240 = dshr(request_input.bits.data, UInt<8>(0h90)) node _T_241 = bits(_T_240, 7, 0) regreset loginfo_cycles_25 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_50 = add(loginfo_cycles_25, UInt<1>(0h1)) node _loginfo_cycles_T_51 = tail(_loginfo_cycles_T_50, 1) connect loginfo_cycles_25, _loginfo_cycles_T_51 node _T_242 = asUInt(reset) node _T_243 = eq(_T_242, UInt<1>(0h0)) when _T_243 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_25) : printf_55 node _T_244 = asUInt(reset) node _T_245 = eq(_T_244, UInt<1>(0h0)) when _T_245 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [seq_writer]\n", _T_239, _T_241) : printf_56 node _T_246 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_247 = lt(UInt<5>(0h13), _T_246) when _T_247 : node _T_248 = add(request_input.bits.addr, UInt<5>(0h13)) node _T_249 = tail(_T_248, 1) node _T_250 = dshr(request_input.bits.data, UInt<8>(0h98)) node _T_251 = bits(_T_250, 7, 0) regreset loginfo_cycles_26 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_52 = add(loginfo_cycles_26, UInt<1>(0h1)) node _loginfo_cycles_T_53 = tail(_loginfo_cycles_T_52, 1) connect loginfo_cycles_26, _loginfo_cycles_T_53 node _T_252 = asUInt(reset) node _T_253 = eq(_T_252, UInt<1>(0h0)) when _T_253 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_26) : printf_57 node _T_254 = asUInt(reset) node _T_255 = eq(_T_254, UInt<1>(0h0)) when _T_255 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [seq_writer]\n", _T_249, _T_251) : printf_58 node _T_256 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_257 = lt(UInt<5>(0h14), _T_256) when _T_257 : node _T_258 = add(request_input.bits.addr, UInt<5>(0h14)) node _T_259 = tail(_T_258, 1) node _T_260 = dshr(request_input.bits.data, UInt<8>(0ha0)) node _T_261 = bits(_T_260, 7, 0) regreset loginfo_cycles_27 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_54 = add(loginfo_cycles_27, UInt<1>(0h1)) node _loginfo_cycles_T_55 = tail(_loginfo_cycles_T_54, 1) connect loginfo_cycles_27, _loginfo_cycles_T_55 node _T_262 = asUInt(reset) node _T_263 = eq(_T_262, UInt<1>(0h0)) when _T_263 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_27) : printf_59 node _T_264 = asUInt(reset) node _T_265 = eq(_T_264, UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [seq_writer]\n", _T_259, _T_261) : printf_60 node _T_266 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_267 = lt(UInt<5>(0h15), _T_266) when _T_267 : node _T_268 = add(request_input.bits.addr, UInt<5>(0h15)) node _T_269 = tail(_T_268, 1) node _T_270 = dshr(request_input.bits.data, UInt<8>(0ha8)) node _T_271 = bits(_T_270, 7, 0) regreset loginfo_cycles_28 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_56 = add(loginfo_cycles_28, UInt<1>(0h1)) node _loginfo_cycles_T_57 = tail(_loginfo_cycles_T_56, 1) connect loginfo_cycles_28, _loginfo_cycles_T_57 node _T_272 = asUInt(reset) node _T_273 = eq(_T_272, UInt<1>(0h0)) when _T_273 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_28) : printf_61 node _T_274 = asUInt(reset) node _T_275 = eq(_T_274, UInt<1>(0h0)) when _T_275 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [seq_writer]\n", _T_269, _T_271) : printf_62 node _T_276 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_277 = lt(UInt<5>(0h16), _T_276) when _T_277 : node _T_278 = add(request_input.bits.addr, UInt<5>(0h16)) node _T_279 = tail(_T_278, 1) node _T_280 = dshr(request_input.bits.data, UInt<8>(0hb0)) node _T_281 = bits(_T_280, 7, 0) regreset loginfo_cycles_29 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_58 = add(loginfo_cycles_29, UInt<1>(0h1)) node _loginfo_cycles_T_59 = tail(_loginfo_cycles_T_58, 1) connect loginfo_cycles_29, _loginfo_cycles_T_59 node _T_282 = asUInt(reset) node _T_283 = eq(_T_282, UInt<1>(0h0)) when _T_283 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_29) : printf_63 node _T_284 = asUInt(reset) node _T_285 = eq(_T_284, UInt<1>(0h0)) when _T_285 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [seq_writer]\n", _T_279, _T_281) : printf_64 node _T_286 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_287 = lt(UInt<5>(0h17), _T_286) when _T_287 : node _T_288 = add(request_input.bits.addr, UInt<5>(0h17)) node _T_289 = tail(_T_288, 1) node _T_290 = dshr(request_input.bits.data, UInt<8>(0hb8)) node _T_291 = bits(_T_290, 7, 0) regreset loginfo_cycles_30 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_60 = add(loginfo_cycles_30, UInt<1>(0h1)) node _loginfo_cycles_T_61 = tail(_loginfo_cycles_T_60, 1) connect loginfo_cycles_30, _loginfo_cycles_T_61 node _T_292 = asUInt(reset) node _T_293 = eq(_T_292, UInt<1>(0h0)) when _T_293 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_30) : printf_65 node _T_294 = asUInt(reset) node _T_295 = eq(_T_294, UInt<1>(0h0)) when _T_295 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [seq_writer]\n", _T_289, _T_291) : printf_66 node _T_296 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_297 = lt(UInt<5>(0h18), _T_296) when _T_297 : node _T_298 = add(request_input.bits.addr, UInt<5>(0h18)) node _T_299 = tail(_T_298, 1) node _T_300 = dshr(request_input.bits.data, UInt<8>(0hc0)) node _T_301 = bits(_T_300, 7, 0) regreset loginfo_cycles_31 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_62 = add(loginfo_cycles_31, UInt<1>(0h1)) node _loginfo_cycles_T_63 = tail(_loginfo_cycles_T_62, 1) connect loginfo_cycles_31, _loginfo_cycles_T_63 node _T_302 = asUInt(reset) node _T_303 = eq(_T_302, UInt<1>(0h0)) when _T_303 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_31) : printf_67 node _T_304 = asUInt(reset) node _T_305 = eq(_T_304, UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [seq_writer]\n", _T_299, _T_301) : printf_68 node _T_306 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_307 = lt(UInt<5>(0h19), _T_306) when _T_307 : node _T_308 = add(request_input.bits.addr, UInt<5>(0h19)) node _T_309 = tail(_T_308, 1) node _T_310 = dshr(request_input.bits.data, UInt<8>(0hc8)) node _T_311 = bits(_T_310, 7, 0) regreset loginfo_cycles_32 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_64 = add(loginfo_cycles_32, UInt<1>(0h1)) node _loginfo_cycles_T_65 = tail(_loginfo_cycles_T_64, 1) connect loginfo_cycles_32, _loginfo_cycles_T_65 node _T_312 = asUInt(reset) node _T_313 = eq(_T_312, UInt<1>(0h0)) when _T_313 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_32) : printf_69 node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [seq_writer]\n", _T_309, _T_311) : printf_70 node _T_316 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_317 = lt(UInt<5>(0h1a), _T_316) when _T_317 : node _T_318 = add(request_input.bits.addr, UInt<5>(0h1a)) node _T_319 = tail(_T_318, 1) node _T_320 = dshr(request_input.bits.data, UInt<8>(0hd0)) node _T_321 = bits(_T_320, 7, 0) regreset loginfo_cycles_33 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_66 = add(loginfo_cycles_33, UInt<1>(0h1)) node _loginfo_cycles_T_67 = tail(_loginfo_cycles_T_66, 1) connect loginfo_cycles_33, _loginfo_cycles_T_67 node _T_322 = asUInt(reset) node _T_323 = eq(_T_322, UInt<1>(0h0)) when _T_323 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_33) : printf_71 node _T_324 = asUInt(reset) node _T_325 = eq(_T_324, UInt<1>(0h0)) when _T_325 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [seq_writer]\n", _T_319, _T_321) : printf_72 node _T_326 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_327 = lt(UInt<5>(0h1b), _T_326) when _T_327 : node _T_328 = add(request_input.bits.addr, UInt<5>(0h1b)) node _T_329 = tail(_T_328, 1) node _T_330 = dshr(request_input.bits.data, UInt<8>(0hd8)) node _T_331 = bits(_T_330, 7, 0) regreset loginfo_cycles_34 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_68 = add(loginfo_cycles_34, UInt<1>(0h1)) node _loginfo_cycles_T_69 = tail(_loginfo_cycles_T_68, 1) connect loginfo_cycles_34, _loginfo_cycles_T_69 node _T_332 = asUInt(reset) node _T_333 = eq(_T_332, UInt<1>(0h0)) when _T_333 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_34) : printf_73 node _T_334 = asUInt(reset) node _T_335 = eq(_T_334, UInt<1>(0h0)) when _T_335 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [seq_writer]\n", _T_329, _T_331) : printf_74 node _T_336 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_337 = lt(UInt<5>(0h1c), _T_336) when _T_337 : node _T_338 = add(request_input.bits.addr, UInt<5>(0h1c)) node _T_339 = tail(_T_338, 1) node _T_340 = dshr(request_input.bits.data, UInt<8>(0he0)) node _T_341 = bits(_T_340, 7, 0) regreset loginfo_cycles_35 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_70 = add(loginfo_cycles_35, UInt<1>(0h1)) node _loginfo_cycles_T_71 = tail(_loginfo_cycles_T_70, 1) connect loginfo_cycles_35, _loginfo_cycles_T_71 node _T_342 = asUInt(reset) node _T_343 = eq(_T_342, UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_35) : printf_75 node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [seq_writer]\n", _T_339, _T_341) : printf_76 node _T_346 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_347 = lt(UInt<5>(0h1d), _T_346) when _T_347 : node _T_348 = add(request_input.bits.addr, UInt<5>(0h1d)) node _T_349 = tail(_T_348, 1) node _T_350 = dshr(request_input.bits.data, UInt<8>(0he8)) node _T_351 = bits(_T_350, 7, 0) regreset loginfo_cycles_36 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_72 = add(loginfo_cycles_36, UInt<1>(0h1)) node _loginfo_cycles_T_73 = tail(_loginfo_cycles_T_72, 1) connect loginfo_cycles_36, _loginfo_cycles_T_73 node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_36) : printf_77 node _T_354 = asUInt(reset) node _T_355 = eq(_T_354, UInt<1>(0h0)) when _T_355 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [seq_writer]\n", _T_349, _T_351) : printf_78 node _T_356 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_357 = lt(UInt<5>(0h1e), _T_356) when _T_357 : node _T_358 = add(request_input.bits.addr, UInt<5>(0h1e)) node _T_359 = tail(_T_358, 1) node _T_360 = dshr(request_input.bits.data, UInt<8>(0hf0)) node _T_361 = bits(_T_360, 7, 0) regreset loginfo_cycles_37 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_74 = add(loginfo_cycles_37, UInt<1>(0h1)) node _loginfo_cycles_T_75 = tail(_loginfo_cycles_T_74, 1) connect loginfo_cycles_37, _loginfo_cycles_T_75 node _T_362 = asUInt(reset) node _T_363 = eq(_T_362, UInt<1>(0h0)) when _T_363 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_37) : printf_79 node _T_364 = asUInt(reset) node _T_365 = eq(_T_364, UInt<1>(0h0)) when _T_365 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [seq_writer]\n", _T_359, _T_361) : printf_80 node _T_366 = dshl(UInt<1>(0h1), request_input.bits.size) node _T_367 = lt(UInt<5>(0h1f), _T_366) when _T_367 : node _T_368 = add(request_input.bits.addr, UInt<5>(0h1f)) node _T_369 = tail(_T_368, 1) node _T_370 = dshr(request_input.bits.data, UInt<8>(0hf8)) node _T_371 = bits(_T_370, 7, 0) regreset loginfo_cycles_38 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_76 = add(loginfo_cycles_38, UInt<1>(0h1)) node _loginfo_cycles_T_77 = tail(_loginfo_cycles_T_76, 1) connect loginfo_cycles_38, _loginfo_cycles_T_77 node _T_372 = asUInt(reset) node _T_373 = eq(_T_372, UInt<1>(0h0)) when _T_373 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_38) : printf_81 node _T_374 = asUInt(reset) node _T_375 = eq(_T_374, UInt<1>(0h0)) when _T_375 : printf(clock, UInt<1>(0h1), "WRITE_BYTE ADDR: 0x%x BYTE: 0x%x [seq_writer]\n", _T_369, _T_371) : printf_82 inst response_latency_injection_q of LatencyInjectionQueue_27 connect response_latency_injection_q.clock, clock connect response_latency_injection_q.reset, reset connect response_latency_injection_q.io.latency_cycles, io.latency_inject_cycles connect response_latency_injection_q.io.enq, masterNodeOut.d node _selectQready_T = eq(UInt<1>(0h0), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_1 = and(Queue4_L2RespInternal.io.enq.ready, _selectQready_T) node _selectQready_T_2 = eq(UInt<1>(0h1), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_3 = and(Queue4_L2RespInternal_1.io.enq.ready, _selectQready_T_2) node _selectQready_T_4 = eq(UInt<2>(0h2), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_5 = and(Queue4_L2RespInternal_2.io.enq.ready, _selectQready_T_4) node _selectQready_T_6 = eq(UInt<2>(0h3), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_7 = and(Queue4_L2RespInternal_3.io.enq.ready, _selectQready_T_6) node _selectQready_T_8 = eq(UInt<3>(0h4), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_9 = and(Queue4_L2RespInternal_4.io.enq.ready, _selectQready_T_8) node _selectQready_T_10 = eq(UInt<3>(0h5), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_11 = and(Queue4_L2RespInternal_5.io.enq.ready, _selectQready_T_10) node _selectQready_T_12 = eq(UInt<3>(0h6), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_13 = and(Queue4_L2RespInternal_6.io.enq.ready, _selectQready_T_12) node _selectQready_T_14 = eq(UInt<3>(0h7), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_15 = and(Queue4_L2RespInternal_7.io.enq.ready, _selectQready_T_14) node _selectQready_T_16 = eq(UInt<4>(0h8), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_17 = and(Queue4_L2RespInternal_8.io.enq.ready, _selectQready_T_16) node _selectQready_T_18 = eq(UInt<4>(0h9), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_19 = and(Queue4_L2RespInternal_9.io.enq.ready, _selectQready_T_18) node _selectQready_T_20 = eq(UInt<4>(0ha), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_21 = and(Queue4_L2RespInternal_10.io.enq.ready, _selectQready_T_20) node _selectQready_T_22 = eq(UInt<4>(0hb), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_23 = and(Queue4_L2RespInternal_11.io.enq.ready, _selectQready_T_22) node _selectQready_T_24 = eq(UInt<4>(0hc), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_25 = and(Queue4_L2RespInternal_12.io.enq.ready, _selectQready_T_24) node _selectQready_T_26 = eq(UInt<4>(0hd), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_27 = and(Queue4_L2RespInternal_13.io.enq.ready, _selectQready_T_26) node _selectQready_T_28 = eq(UInt<4>(0he), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_29 = and(Queue4_L2RespInternal_14.io.enq.ready, _selectQready_T_28) node _selectQready_T_30 = eq(UInt<4>(0hf), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_31 = and(Queue4_L2RespInternal_15.io.enq.ready, _selectQready_T_30) node _selectQready_T_32 = eq(UInt<5>(0h10), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_33 = and(Queue4_L2RespInternal_16.io.enq.ready, _selectQready_T_32) node _selectQready_T_34 = eq(UInt<5>(0h11), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_35 = and(Queue4_L2RespInternal_17.io.enq.ready, _selectQready_T_34) node _selectQready_T_36 = eq(UInt<5>(0h12), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_37 = and(Queue4_L2RespInternal_18.io.enq.ready, _selectQready_T_36) node _selectQready_T_38 = eq(UInt<5>(0h13), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_39 = and(Queue4_L2RespInternal_19.io.enq.ready, _selectQready_T_38) node _selectQready_T_40 = eq(UInt<5>(0h14), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_41 = and(Queue4_L2RespInternal_20.io.enq.ready, _selectQready_T_40) node _selectQready_T_42 = eq(UInt<5>(0h15), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_43 = and(Queue4_L2RespInternal_21.io.enq.ready, _selectQready_T_42) node _selectQready_T_44 = eq(UInt<5>(0h16), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_45 = and(Queue4_L2RespInternal_22.io.enq.ready, _selectQready_T_44) node _selectQready_T_46 = eq(UInt<5>(0h17), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_47 = and(Queue4_L2RespInternal_23.io.enq.ready, _selectQready_T_46) node _selectQready_T_48 = eq(UInt<5>(0h18), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_49 = and(Queue4_L2RespInternal_24.io.enq.ready, _selectQready_T_48) node _selectQready_T_50 = eq(UInt<5>(0h19), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_51 = and(Queue4_L2RespInternal_25.io.enq.ready, _selectQready_T_50) node _selectQready_T_52 = eq(UInt<5>(0h1a), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_53 = and(Queue4_L2RespInternal_26.io.enq.ready, _selectQready_T_52) node _selectQready_T_54 = eq(UInt<5>(0h1b), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_55 = and(Queue4_L2RespInternal_27.io.enq.ready, _selectQready_T_54) node _selectQready_T_56 = eq(UInt<5>(0h1c), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_57 = and(Queue4_L2RespInternal_28.io.enq.ready, _selectQready_T_56) node _selectQready_T_58 = eq(UInt<5>(0h1d), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_59 = and(Queue4_L2RespInternal_29.io.enq.ready, _selectQready_T_58) node _selectQready_T_60 = eq(UInt<5>(0h1e), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_61 = and(Queue4_L2RespInternal_30.io.enq.ready, _selectQready_T_60) node _selectQready_T_62 = eq(UInt<5>(0h1f), response_latency_injection_q.io.deq.bits.source) node _selectQready_T_63 = and(Queue4_L2RespInternal_31.io.enq.ready, _selectQready_T_62) node _selectQready_T_64 = or(_selectQready_T_1, _selectQready_T_3) node _selectQready_T_65 = or(_selectQready_T_64, _selectQready_T_5) node _selectQready_T_66 = or(_selectQready_T_65, _selectQready_T_7) node _selectQready_T_67 = or(_selectQready_T_66, _selectQready_T_9) node _selectQready_T_68 = or(_selectQready_T_67, _selectQready_T_11) node _selectQready_T_69 = or(_selectQready_T_68, _selectQready_T_13) node _selectQready_T_70 = or(_selectQready_T_69, _selectQready_T_15) node _selectQready_T_71 = or(_selectQready_T_70, _selectQready_T_17) node _selectQready_T_72 = or(_selectQready_T_71, _selectQready_T_19) node _selectQready_T_73 = or(_selectQready_T_72, _selectQready_T_21) node _selectQready_T_74 = or(_selectQready_T_73, _selectQready_T_23) node _selectQready_T_75 = or(_selectQready_T_74, _selectQready_T_25) node _selectQready_T_76 = or(_selectQready_T_75, _selectQready_T_27) node _selectQready_T_77 = or(_selectQready_T_76, _selectQready_T_29) node _selectQready_T_78 = or(_selectQready_T_77, _selectQready_T_31) node _selectQready_T_79 = or(_selectQready_T_78, _selectQready_T_33) node _selectQready_T_80 = or(_selectQready_T_79, _selectQready_T_35) node _selectQready_T_81 = or(_selectQready_T_80, _selectQready_T_37) node _selectQready_T_82 = or(_selectQready_T_81, _selectQready_T_39) node _selectQready_T_83 = or(_selectQready_T_82, _selectQready_T_41) node _selectQready_T_84 = or(_selectQready_T_83, _selectQready_T_43) node _selectQready_T_85 = or(_selectQready_T_84, _selectQready_T_45) node _selectQready_T_86 = or(_selectQready_T_85, _selectQready_T_47) node _selectQready_T_87 = or(_selectQready_T_86, _selectQready_T_49) node _selectQready_T_88 = or(_selectQready_T_87, _selectQready_T_51) node _selectQready_T_89 = or(_selectQready_T_88, _selectQready_T_53) node _selectQready_T_90 = or(_selectQready_T_89, _selectQready_T_55) node _selectQready_T_91 = or(_selectQready_T_90, _selectQready_T_57) node _selectQready_T_92 = or(_selectQready_T_91, _selectQready_T_59) node _selectQready_T_93 = or(_selectQready_T_92, _selectQready_T_61) node selectQready = or(_selectQready_T_93, _selectQready_T_63) node _T_376 = and(selectQready, response_latency_injection_q.io.deq.valid) when _T_376 : connect tags_for_issue_Q.io.enq.valid, UInt<1>(0h1) connect tags_for_issue_Q.io.enq.bits, response_latency_injection_q.io.deq.bits.source node _T_377 = and(selectQready, response_latency_injection_q.io.deq.valid) node _T_378 = and(_T_377, tags_for_issue_Q.io.enq.valid) when _T_378 : regreset loginfo_cycles_39 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_78 = add(loginfo_cycles_39, UInt<1>(0h1)) node _loginfo_cycles_T_79 = tail(_loginfo_cycles_T_78, 1) connect loginfo_cycles_39, _loginfo_cycles_T_79 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_39) : printf_83 node _T_381 = asUInt(reset) node _T_382 = eq(_T_381, UInt<1>(0h0)) when _T_382 : printf(clock, UInt<1>(0h1), "[seq_writer] tags_for_issue_Q add back tag %d\n", tags_for_issue_Q.io.enq.bits) : printf_84 node _response_latency_injection_q_io_deq_ready_T = and(selectQready, tags_for_issue_Q.io.enq.ready) connect response_latency_injection_q.io.deq.ready, _response_latency_injection_q_io_deq_ready_T node _T_383 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_384 = eq(response_latency_injection_q.io.deq.bits.source, UInt<1>(0h0)) node _T_385 = and(_T_383, _T_384) connect Queue4_L2RespInternal.io.enq.valid, _T_385 connect Queue4_L2RespInternal.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_386 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_387 = eq(response_latency_injection_q.io.deq.bits.source, UInt<1>(0h1)) node _T_388 = and(_T_386, _T_387) connect Queue4_L2RespInternal_1.io.enq.valid, _T_388 connect Queue4_L2RespInternal_1.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_389 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_390 = eq(response_latency_injection_q.io.deq.bits.source, UInt<2>(0h2)) node _T_391 = and(_T_389, _T_390) connect Queue4_L2RespInternal_2.io.enq.valid, _T_391 connect Queue4_L2RespInternal_2.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_392 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_393 = eq(response_latency_injection_q.io.deq.bits.source, UInt<2>(0h3)) node _T_394 = and(_T_392, _T_393) connect Queue4_L2RespInternal_3.io.enq.valid, _T_394 connect Queue4_L2RespInternal_3.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_395 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_396 = eq(response_latency_injection_q.io.deq.bits.source, UInt<3>(0h4)) node _T_397 = and(_T_395, _T_396) connect Queue4_L2RespInternal_4.io.enq.valid, _T_397 connect Queue4_L2RespInternal_4.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_398 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_399 = eq(response_latency_injection_q.io.deq.bits.source, UInt<3>(0h5)) node _T_400 = and(_T_398, _T_399) connect Queue4_L2RespInternal_5.io.enq.valid, _T_400 connect Queue4_L2RespInternal_5.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_401 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_402 = eq(response_latency_injection_q.io.deq.bits.source, UInt<3>(0h6)) node _T_403 = and(_T_401, _T_402) connect Queue4_L2RespInternal_6.io.enq.valid, _T_403 connect Queue4_L2RespInternal_6.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_404 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_405 = eq(response_latency_injection_q.io.deq.bits.source, UInt<3>(0h7)) node _T_406 = and(_T_404, _T_405) connect Queue4_L2RespInternal_7.io.enq.valid, _T_406 connect Queue4_L2RespInternal_7.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_407 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_408 = eq(response_latency_injection_q.io.deq.bits.source, UInt<4>(0h8)) node _T_409 = and(_T_407, _T_408) connect Queue4_L2RespInternal_8.io.enq.valid, _T_409 connect Queue4_L2RespInternal_8.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_410 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_411 = eq(response_latency_injection_q.io.deq.bits.source, UInt<4>(0h9)) node _T_412 = and(_T_410, _T_411) connect Queue4_L2RespInternal_9.io.enq.valid, _T_412 connect Queue4_L2RespInternal_9.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_413 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_414 = eq(response_latency_injection_q.io.deq.bits.source, UInt<4>(0ha)) node _T_415 = and(_T_413, _T_414) connect Queue4_L2RespInternal_10.io.enq.valid, _T_415 connect Queue4_L2RespInternal_10.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_416 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_417 = eq(response_latency_injection_q.io.deq.bits.source, UInt<4>(0hb)) node _T_418 = and(_T_416, _T_417) connect Queue4_L2RespInternal_11.io.enq.valid, _T_418 connect Queue4_L2RespInternal_11.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_419 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_420 = eq(response_latency_injection_q.io.deq.bits.source, UInt<4>(0hc)) node _T_421 = and(_T_419, _T_420) connect Queue4_L2RespInternal_12.io.enq.valid, _T_421 connect Queue4_L2RespInternal_12.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_422 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_423 = eq(response_latency_injection_q.io.deq.bits.source, UInt<4>(0hd)) node _T_424 = and(_T_422, _T_423) connect Queue4_L2RespInternal_13.io.enq.valid, _T_424 connect Queue4_L2RespInternal_13.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_425 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_426 = eq(response_latency_injection_q.io.deq.bits.source, UInt<4>(0he)) node _T_427 = and(_T_425, _T_426) connect Queue4_L2RespInternal_14.io.enq.valid, _T_427 connect Queue4_L2RespInternal_14.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_428 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_429 = eq(response_latency_injection_q.io.deq.bits.source, UInt<4>(0hf)) node _T_430 = and(_T_428, _T_429) connect Queue4_L2RespInternal_15.io.enq.valid, _T_430 connect Queue4_L2RespInternal_15.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_431 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_432 = eq(response_latency_injection_q.io.deq.bits.source, UInt<5>(0h10)) node _T_433 = and(_T_431, _T_432) connect Queue4_L2RespInternal_16.io.enq.valid, _T_433 connect Queue4_L2RespInternal_16.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_434 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_435 = eq(response_latency_injection_q.io.deq.bits.source, UInt<5>(0h11)) node _T_436 = and(_T_434, _T_435) connect Queue4_L2RespInternal_17.io.enq.valid, _T_436 connect Queue4_L2RespInternal_17.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_437 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_438 = eq(response_latency_injection_q.io.deq.bits.source, UInt<5>(0h12)) node _T_439 = and(_T_437, _T_438) connect Queue4_L2RespInternal_18.io.enq.valid, _T_439 connect Queue4_L2RespInternal_18.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_440 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_441 = eq(response_latency_injection_q.io.deq.bits.source, UInt<5>(0h13)) node _T_442 = and(_T_440, _T_441) connect Queue4_L2RespInternal_19.io.enq.valid, _T_442 connect Queue4_L2RespInternal_19.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_443 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_444 = eq(response_latency_injection_q.io.deq.bits.source, UInt<5>(0h14)) node _T_445 = and(_T_443, _T_444) connect Queue4_L2RespInternal_20.io.enq.valid, _T_445 connect Queue4_L2RespInternal_20.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_446 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_447 = eq(response_latency_injection_q.io.deq.bits.source, UInt<5>(0h15)) node _T_448 = and(_T_446, _T_447) connect Queue4_L2RespInternal_21.io.enq.valid, _T_448 connect Queue4_L2RespInternal_21.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_449 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_450 = eq(response_latency_injection_q.io.deq.bits.source, UInt<5>(0h16)) node _T_451 = and(_T_449, _T_450) connect Queue4_L2RespInternal_22.io.enq.valid, _T_451 connect Queue4_L2RespInternal_22.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_452 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_453 = eq(response_latency_injection_q.io.deq.bits.source, UInt<5>(0h17)) node _T_454 = and(_T_452, _T_453) connect Queue4_L2RespInternal_23.io.enq.valid, _T_454 connect Queue4_L2RespInternal_23.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_455 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_456 = eq(response_latency_injection_q.io.deq.bits.source, UInt<5>(0h18)) node _T_457 = and(_T_455, _T_456) connect Queue4_L2RespInternal_24.io.enq.valid, _T_457 connect Queue4_L2RespInternal_24.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_458 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_459 = eq(response_latency_injection_q.io.deq.bits.source, UInt<5>(0h19)) node _T_460 = and(_T_458, _T_459) connect Queue4_L2RespInternal_25.io.enq.valid, _T_460 connect Queue4_L2RespInternal_25.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_461 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_462 = eq(response_latency_injection_q.io.deq.bits.source, UInt<5>(0h1a)) node _T_463 = and(_T_461, _T_462) connect Queue4_L2RespInternal_26.io.enq.valid, _T_463 connect Queue4_L2RespInternal_26.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_464 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_465 = eq(response_latency_injection_q.io.deq.bits.source, UInt<5>(0h1b)) node _T_466 = and(_T_464, _T_465) connect Queue4_L2RespInternal_27.io.enq.valid, _T_466 connect Queue4_L2RespInternal_27.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_467 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_468 = eq(response_latency_injection_q.io.deq.bits.source, UInt<5>(0h1c)) node _T_469 = and(_T_467, _T_468) connect Queue4_L2RespInternal_28.io.enq.valid, _T_469 connect Queue4_L2RespInternal_28.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_470 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_471 = eq(response_latency_injection_q.io.deq.bits.source, UInt<5>(0h1d)) node _T_472 = and(_T_470, _T_471) connect Queue4_L2RespInternal_29.io.enq.valid, _T_472 connect Queue4_L2RespInternal_29.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_473 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_474 = eq(response_latency_injection_q.io.deq.bits.source, UInt<5>(0h1e)) node _T_475 = and(_T_473, _T_474) connect Queue4_L2RespInternal_30.io.enq.valid, _T_475 connect Queue4_L2RespInternal_30.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _T_476 = and(response_latency_injection_q.io.deq.valid, tags_for_issue_Q.io.enq.ready) node _T_477 = eq(response_latency_injection_q.io.deq.bits.source, UInt<5>(0h1f)) node _T_478 = and(_T_476, _T_477) connect Queue4_L2RespInternal_31.io.enq.valid, _T_478 connect Queue4_L2RespInternal_31.io.enq.bits.data, response_latency_injection_q.io.deq.bits.data node _queueValid_T = eq(UInt<1>(0h0), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_1 = and(Queue4_L2RespInternal.io.deq.valid, _queueValid_T) node _queueValid_T_2 = eq(UInt<1>(0h1), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_3 = and(Queue4_L2RespInternal_1.io.deq.valid, _queueValid_T_2) node _queueValid_T_4 = eq(UInt<2>(0h2), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_5 = and(Queue4_L2RespInternal_2.io.deq.valid, _queueValid_T_4) node _queueValid_T_6 = eq(UInt<2>(0h3), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_7 = and(Queue4_L2RespInternal_3.io.deq.valid, _queueValid_T_6) node _queueValid_T_8 = eq(UInt<3>(0h4), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_9 = and(Queue4_L2RespInternal_4.io.deq.valid, _queueValid_T_8) node _queueValid_T_10 = eq(UInt<3>(0h5), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_11 = and(Queue4_L2RespInternal_5.io.deq.valid, _queueValid_T_10) node _queueValid_T_12 = eq(UInt<3>(0h6), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_13 = and(Queue4_L2RespInternal_6.io.deq.valid, _queueValid_T_12) node _queueValid_T_14 = eq(UInt<3>(0h7), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_15 = and(Queue4_L2RespInternal_7.io.deq.valid, _queueValid_T_14) node _queueValid_T_16 = eq(UInt<4>(0h8), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_17 = and(Queue4_L2RespInternal_8.io.deq.valid, _queueValid_T_16) node _queueValid_T_18 = eq(UInt<4>(0h9), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_19 = and(Queue4_L2RespInternal_9.io.deq.valid, _queueValid_T_18) node _queueValid_T_20 = eq(UInt<4>(0ha), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_21 = and(Queue4_L2RespInternal_10.io.deq.valid, _queueValid_T_20) node _queueValid_T_22 = eq(UInt<4>(0hb), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_23 = and(Queue4_L2RespInternal_11.io.deq.valid, _queueValid_T_22) node _queueValid_T_24 = eq(UInt<4>(0hc), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_25 = and(Queue4_L2RespInternal_12.io.deq.valid, _queueValid_T_24) node _queueValid_T_26 = eq(UInt<4>(0hd), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_27 = and(Queue4_L2RespInternal_13.io.deq.valid, _queueValid_T_26) node _queueValid_T_28 = eq(UInt<4>(0he), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_29 = and(Queue4_L2RespInternal_14.io.deq.valid, _queueValid_T_28) node _queueValid_T_30 = eq(UInt<4>(0hf), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_31 = and(Queue4_L2RespInternal_15.io.deq.valid, _queueValid_T_30) node _queueValid_T_32 = eq(UInt<5>(0h10), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_33 = and(Queue4_L2RespInternal_16.io.deq.valid, _queueValid_T_32) node _queueValid_T_34 = eq(UInt<5>(0h11), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_35 = and(Queue4_L2RespInternal_17.io.deq.valid, _queueValid_T_34) node _queueValid_T_36 = eq(UInt<5>(0h12), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_37 = and(Queue4_L2RespInternal_18.io.deq.valid, _queueValid_T_36) node _queueValid_T_38 = eq(UInt<5>(0h13), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_39 = and(Queue4_L2RespInternal_19.io.deq.valid, _queueValid_T_38) node _queueValid_T_40 = eq(UInt<5>(0h14), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_41 = and(Queue4_L2RespInternal_20.io.deq.valid, _queueValid_T_40) node _queueValid_T_42 = eq(UInt<5>(0h15), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_43 = and(Queue4_L2RespInternal_21.io.deq.valid, _queueValid_T_42) node _queueValid_T_44 = eq(UInt<5>(0h16), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_45 = and(Queue4_L2RespInternal_22.io.deq.valid, _queueValid_T_44) node _queueValid_T_46 = eq(UInt<5>(0h17), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_47 = and(Queue4_L2RespInternal_23.io.deq.valid, _queueValid_T_46) node _queueValid_T_48 = eq(UInt<5>(0h18), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_49 = and(Queue4_L2RespInternal_24.io.deq.valid, _queueValid_T_48) node _queueValid_T_50 = eq(UInt<5>(0h19), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_51 = and(Queue4_L2RespInternal_25.io.deq.valid, _queueValid_T_50) node _queueValid_T_52 = eq(UInt<5>(0h1a), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_53 = and(Queue4_L2RespInternal_26.io.deq.valid, _queueValid_T_52) node _queueValid_T_54 = eq(UInt<5>(0h1b), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_55 = and(Queue4_L2RespInternal_27.io.deq.valid, _queueValid_T_54) node _queueValid_T_56 = eq(UInt<5>(0h1c), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_57 = and(Queue4_L2RespInternal_28.io.deq.valid, _queueValid_T_56) node _queueValid_T_58 = eq(UInt<5>(0h1d), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_59 = and(Queue4_L2RespInternal_29.io.deq.valid, _queueValid_T_58) node _queueValid_T_60 = eq(UInt<5>(0h1e), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_61 = and(Queue4_L2RespInternal_30.io.deq.valid, _queueValid_T_60) node _queueValid_T_62 = eq(UInt<5>(0h1f), outstanding_req_addr.io.deq.bits.tag) node _queueValid_T_63 = and(Queue4_L2RespInternal_31.io.deq.valid, _queueValid_T_62) node _queueValid_T_64 = or(_queueValid_T_1, _queueValid_T_3) node _queueValid_T_65 = or(_queueValid_T_64, _queueValid_T_5) node _queueValid_T_66 = or(_queueValid_T_65, _queueValid_T_7) node _queueValid_T_67 = or(_queueValid_T_66, _queueValid_T_9) node _queueValid_T_68 = or(_queueValid_T_67, _queueValid_T_11) node _queueValid_T_69 = or(_queueValid_T_68, _queueValid_T_13) node _queueValid_T_70 = or(_queueValid_T_69, _queueValid_T_15) node _queueValid_T_71 = or(_queueValid_T_70, _queueValid_T_17) node _queueValid_T_72 = or(_queueValid_T_71, _queueValid_T_19) node _queueValid_T_73 = or(_queueValid_T_72, _queueValid_T_21) node _queueValid_T_74 = or(_queueValid_T_73, _queueValid_T_23) node _queueValid_T_75 = or(_queueValid_T_74, _queueValid_T_25) node _queueValid_T_76 = or(_queueValid_T_75, _queueValid_T_27) node _queueValid_T_77 = or(_queueValid_T_76, _queueValid_T_29) node _queueValid_T_78 = or(_queueValid_T_77, _queueValid_T_31) node _queueValid_T_79 = or(_queueValid_T_78, _queueValid_T_33) node _queueValid_T_80 = or(_queueValid_T_79, _queueValid_T_35) node _queueValid_T_81 = or(_queueValid_T_80, _queueValid_T_37) node _queueValid_T_82 = or(_queueValid_T_81, _queueValid_T_39) node _queueValid_T_83 = or(_queueValid_T_82, _queueValid_T_41) node _queueValid_T_84 = or(_queueValid_T_83, _queueValid_T_43) node _queueValid_T_85 = or(_queueValid_T_84, _queueValid_T_45) node _queueValid_T_86 = or(_queueValid_T_85, _queueValid_T_47) node _queueValid_T_87 = or(_queueValid_T_86, _queueValid_T_49) node _queueValid_T_88 = or(_queueValid_T_87, _queueValid_T_51) node _queueValid_T_89 = or(_queueValid_T_88, _queueValid_T_53) node _queueValid_T_90 = or(_queueValid_T_89, _queueValid_T_55) node _queueValid_T_91 = or(_queueValid_T_90, _queueValid_T_57) node _queueValid_T_92 = or(_queueValid_T_91, _queueValid_T_59) node _queueValid_T_93 = or(_queueValid_T_92, _queueValid_T_61) node queueValid = or(_queueValid_T_93, _queueValid_T_63) node resultdata_is_current_q = eq(UInt<1>(0h0), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data : UInt<256> when resultdata_is_current_q : node _resultdata_data_T = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_1 = dshr(Queue4_L2RespInternal.io.deq.bits.data, _resultdata_data_T) connect resultdata_data, _resultdata_data_T_1 else : connect resultdata_data, UInt<1>(0h0) node resultdata_is_current_q_1 = eq(UInt<1>(0h1), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_1 : UInt<256> when resultdata_is_current_q_1 : node _resultdata_data_T_2 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_3 = dshr(Queue4_L2RespInternal_1.io.deq.bits.data, _resultdata_data_T_2) connect resultdata_data_1, _resultdata_data_T_3 else : connect resultdata_data_1, UInt<1>(0h0) node resultdata_is_current_q_2 = eq(UInt<2>(0h2), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_2 : UInt<256> when resultdata_is_current_q_2 : node _resultdata_data_T_4 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_5 = dshr(Queue4_L2RespInternal_2.io.deq.bits.data, _resultdata_data_T_4) connect resultdata_data_2, _resultdata_data_T_5 else : connect resultdata_data_2, UInt<1>(0h0) node resultdata_is_current_q_3 = eq(UInt<2>(0h3), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_3 : UInt<256> when resultdata_is_current_q_3 : node _resultdata_data_T_6 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_7 = dshr(Queue4_L2RespInternal_3.io.deq.bits.data, _resultdata_data_T_6) connect resultdata_data_3, _resultdata_data_T_7 else : connect resultdata_data_3, UInt<1>(0h0) node resultdata_is_current_q_4 = eq(UInt<3>(0h4), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_4 : UInt<256> when resultdata_is_current_q_4 : node _resultdata_data_T_8 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_9 = dshr(Queue4_L2RespInternal_4.io.deq.bits.data, _resultdata_data_T_8) connect resultdata_data_4, _resultdata_data_T_9 else : connect resultdata_data_4, UInt<1>(0h0) node resultdata_is_current_q_5 = eq(UInt<3>(0h5), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_5 : UInt<256> when resultdata_is_current_q_5 : node _resultdata_data_T_10 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_11 = dshr(Queue4_L2RespInternal_5.io.deq.bits.data, _resultdata_data_T_10) connect resultdata_data_5, _resultdata_data_T_11 else : connect resultdata_data_5, UInt<1>(0h0) node resultdata_is_current_q_6 = eq(UInt<3>(0h6), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_6 : UInt<256> when resultdata_is_current_q_6 : node _resultdata_data_T_12 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_13 = dshr(Queue4_L2RespInternal_6.io.deq.bits.data, _resultdata_data_T_12) connect resultdata_data_6, _resultdata_data_T_13 else : connect resultdata_data_6, UInt<1>(0h0) node resultdata_is_current_q_7 = eq(UInt<3>(0h7), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_7 : UInt<256> when resultdata_is_current_q_7 : node _resultdata_data_T_14 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_15 = dshr(Queue4_L2RespInternal_7.io.deq.bits.data, _resultdata_data_T_14) connect resultdata_data_7, _resultdata_data_T_15 else : connect resultdata_data_7, UInt<1>(0h0) node resultdata_is_current_q_8 = eq(UInt<4>(0h8), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_8 : UInt<256> when resultdata_is_current_q_8 : node _resultdata_data_T_16 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_17 = dshr(Queue4_L2RespInternal_8.io.deq.bits.data, _resultdata_data_T_16) connect resultdata_data_8, _resultdata_data_T_17 else : connect resultdata_data_8, UInt<1>(0h0) node resultdata_is_current_q_9 = eq(UInt<4>(0h9), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_9 : UInt<256> when resultdata_is_current_q_9 : node _resultdata_data_T_18 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_19 = dshr(Queue4_L2RespInternal_9.io.deq.bits.data, _resultdata_data_T_18) connect resultdata_data_9, _resultdata_data_T_19 else : connect resultdata_data_9, UInt<1>(0h0) node resultdata_is_current_q_10 = eq(UInt<4>(0ha), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_10 : UInt<256> when resultdata_is_current_q_10 : node _resultdata_data_T_20 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_21 = dshr(Queue4_L2RespInternal_10.io.deq.bits.data, _resultdata_data_T_20) connect resultdata_data_10, _resultdata_data_T_21 else : connect resultdata_data_10, UInt<1>(0h0) node resultdata_is_current_q_11 = eq(UInt<4>(0hb), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_11 : UInt<256> when resultdata_is_current_q_11 : node _resultdata_data_T_22 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_23 = dshr(Queue4_L2RespInternal_11.io.deq.bits.data, _resultdata_data_T_22) connect resultdata_data_11, _resultdata_data_T_23 else : connect resultdata_data_11, UInt<1>(0h0) node resultdata_is_current_q_12 = eq(UInt<4>(0hc), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_12 : UInt<256> when resultdata_is_current_q_12 : node _resultdata_data_T_24 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_25 = dshr(Queue4_L2RespInternal_12.io.deq.bits.data, _resultdata_data_T_24) connect resultdata_data_12, _resultdata_data_T_25 else : connect resultdata_data_12, UInt<1>(0h0) node resultdata_is_current_q_13 = eq(UInt<4>(0hd), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_13 : UInt<256> when resultdata_is_current_q_13 : node _resultdata_data_T_26 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_27 = dshr(Queue4_L2RespInternal_13.io.deq.bits.data, _resultdata_data_T_26) connect resultdata_data_13, _resultdata_data_T_27 else : connect resultdata_data_13, UInt<1>(0h0) node resultdata_is_current_q_14 = eq(UInt<4>(0he), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_14 : UInt<256> when resultdata_is_current_q_14 : node _resultdata_data_T_28 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_29 = dshr(Queue4_L2RespInternal_14.io.deq.bits.data, _resultdata_data_T_28) connect resultdata_data_14, _resultdata_data_T_29 else : connect resultdata_data_14, UInt<1>(0h0) node resultdata_is_current_q_15 = eq(UInt<4>(0hf), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_15 : UInt<256> when resultdata_is_current_q_15 : node _resultdata_data_T_30 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_31 = dshr(Queue4_L2RespInternal_15.io.deq.bits.data, _resultdata_data_T_30) connect resultdata_data_15, _resultdata_data_T_31 else : connect resultdata_data_15, UInt<1>(0h0) node resultdata_is_current_q_16 = eq(UInt<5>(0h10), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_16 : UInt<256> when resultdata_is_current_q_16 : node _resultdata_data_T_32 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_33 = dshr(Queue4_L2RespInternal_16.io.deq.bits.data, _resultdata_data_T_32) connect resultdata_data_16, _resultdata_data_T_33 else : connect resultdata_data_16, UInt<1>(0h0) node resultdata_is_current_q_17 = eq(UInt<5>(0h11), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_17 : UInt<256> when resultdata_is_current_q_17 : node _resultdata_data_T_34 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_35 = dshr(Queue4_L2RespInternal_17.io.deq.bits.data, _resultdata_data_T_34) connect resultdata_data_17, _resultdata_data_T_35 else : connect resultdata_data_17, UInt<1>(0h0) node resultdata_is_current_q_18 = eq(UInt<5>(0h12), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_18 : UInt<256> when resultdata_is_current_q_18 : node _resultdata_data_T_36 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_37 = dshr(Queue4_L2RespInternal_18.io.deq.bits.data, _resultdata_data_T_36) connect resultdata_data_18, _resultdata_data_T_37 else : connect resultdata_data_18, UInt<1>(0h0) node resultdata_is_current_q_19 = eq(UInt<5>(0h13), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_19 : UInt<256> when resultdata_is_current_q_19 : node _resultdata_data_T_38 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_39 = dshr(Queue4_L2RespInternal_19.io.deq.bits.data, _resultdata_data_T_38) connect resultdata_data_19, _resultdata_data_T_39 else : connect resultdata_data_19, UInt<1>(0h0) node resultdata_is_current_q_20 = eq(UInt<5>(0h14), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_20 : UInt<256> when resultdata_is_current_q_20 : node _resultdata_data_T_40 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_41 = dshr(Queue4_L2RespInternal_20.io.deq.bits.data, _resultdata_data_T_40) connect resultdata_data_20, _resultdata_data_T_41 else : connect resultdata_data_20, UInt<1>(0h0) node resultdata_is_current_q_21 = eq(UInt<5>(0h15), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_21 : UInt<256> when resultdata_is_current_q_21 : node _resultdata_data_T_42 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_43 = dshr(Queue4_L2RespInternal_21.io.deq.bits.data, _resultdata_data_T_42) connect resultdata_data_21, _resultdata_data_T_43 else : connect resultdata_data_21, UInt<1>(0h0) node resultdata_is_current_q_22 = eq(UInt<5>(0h16), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_22 : UInt<256> when resultdata_is_current_q_22 : node _resultdata_data_T_44 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_45 = dshr(Queue4_L2RespInternal_22.io.deq.bits.data, _resultdata_data_T_44) connect resultdata_data_22, _resultdata_data_T_45 else : connect resultdata_data_22, UInt<1>(0h0) node resultdata_is_current_q_23 = eq(UInt<5>(0h17), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_23 : UInt<256> when resultdata_is_current_q_23 : node _resultdata_data_T_46 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_47 = dshr(Queue4_L2RespInternal_23.io.deq.bits.data, _resultdata_data_T_46) connect resultdata_data_23, _resultdata_data_T_47 else : connect resultdata_data_23, UInt<1>(0h0) node resultdata_is_current_q_24 = eq(UInt<5>(0h18), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_24 : UInt<256> when resultdata_is_current_q_24 : node _resultdata_data_T_48 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_49 = dshr(Queue4_L2RespInternal_24.io.deq.bits.data, _resultdata_data_T_48) connect resultdata_data_24, _resultdata_data_T_49 else : connect resultdata_data_24, UInt<1>(0h0) node resultdata_is_current_q_25 = eq(UInt<5>(0h19), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_25 : UInt<256> when resultdata_is_current_q_25 : node _resultdata_data_T_50 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_51 = dshr(Queue4_L2RespInternal_25.io.deq.bits.data, _resultdata_data_T_50) connect resultdata_data_25, _resultdata_data_T_51 else : connect resultdata_data_25, UInt<1>(0h0) node resultdata_is_current_q_26 = eq(UInt<5>(0h1a), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_26 : UInt<256> when resultdata_is_current_q_26 : node _resultdata_data_T_52 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_53 = dshr(Queue4_L2RespInternal_26.io.deq.bits.data, _resultdata_data_T_52) connect resultdata_data_26, _resultdata_data_T_53 else : connect resultdata_data_26, UInt<1>(0h0) node resultdata_is_current_q_27 = eq(UInt<5>(0h1b), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_27 : UInt<256> when resultdata_is_current_q_27 : node _resultdata_data_T_54 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_55 = dshr(Queue4_L2RespInternal_27.io.deq.bits.data, _resultdata_data_T_54) connect resultdata_data_27, _resultdata_data_T_55 else : connect resultdata_data_27, UInt<1>(0h0) node resultdata_is_current_q_28 = eq(UInt<5>(0h1c), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_28 : UInt<256> when resultdata_is_current_q_28 : node _resultdata_data_T_56 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_57 = dshr(Queue4_L2RespInternal_28.io.deq.bits.data, _resultdata_data_T_56) connect resultdata_data_28, _resultdata_data_T_57 else : connect resultdata_data_28, UInt<1>(0h0) node resultdata_is_current_q_29 = eq(UInt<5>(0h1d), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_29 : UInt<256> when resultdata_is_current_q_29 : node _resultdata_data_T_58 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_59 = dshr(Queue4_L2RespInternal_29.io.deq.bits.data, _resultdata_data_T_58) connect resultdata_data_29, _resultdata_data_T_59 else : connect resultdata_data_29, UInt<1>(0h0) node resultdata_is_current_q_30 = eq(UInt<5>(0h1e), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_30 : UInt<256> when resultdata_is_current_q_30 : node _resultdata_data_T_60 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_61 = dshr(Queue4_L2RespInternal_30.io.deq.bits.data, _resultdata_data_T_60) connect resultdata_data_30, _resultdata_data_T_61 else : connect resultdata_data_30, UInt<1>(0h0) node resultdata_is_current_q_31 = eq(UInt<5>(0h1f), outstanding_req_addr.io.deq.bits.tag) wire resultdata_data_31 : UInt<256> when resultdata_is_current_q_31 : node _resultdata_data_T_62 = shl(outstanding_req_addr.io.deq.bits.addrindex, 3) node _resultdata_data_T_63 = dshr(Queue4_L2RespInternal_31.io.deq.bits.data, _resultdata_data_T_62) connect resultdata_data_31, _resultdata_data_T_63 else : connect resultdata_data_31, UInt<1>(0h0) node _resultdata_T = or(resultdata_data, resultdata_data_1) node _resultdata_T_1 = or(_resultdata_T, resultdata_data_2) node _resultdata_T_2 = or(_resultdata_T_1, resultdata_data_3) node _resultdata_T_3 = or(_resultdata_T_2, resultdata_data_4) node _resultdata_T_4 = or(_resultdata_T_3, resultdata_data_5) node _resultdata_T_5 = or(_resultdata_T_4, resultdata_data_6) node _resultdata_T_6 = or(_resultdata_T_5, resultdata_data_7) node _resultdata_T_7 = or(_resultdata_T_6, resultdata_data_8) node _resultdata_T_8 = or(_resultdata_T_7, resultdata_data_9) node _resultdata_T_9 = or(_resultdata_T_8, resultdata_data_10) node _resultdata_T_10 = or(_resultdata_T_9, resultdata_data_11) node _resultdata_T_11 = or(_resultdata_T_10, resultdata_data_12) node _resultdata_T_12 = or(_resultdata_T_11, resultdata_data_13) node _resultdata_T_13 = or(_resultdata_T_12, resultdata_data_14) node _resultdata_T_14 = or(_resultdata_T_13, resultdata_data_15) node _resultdata_T_15 = or(_resultdata_T_14, resultdata_data_16) node _resultdata_T_16 = or(_resultdata_T_15, resultdata_data_17) node _resultdata_T_17 = or(_resultdata_T_16, resultdata_data_18) node _resultdata_T_18 = or(_resultdata_T_17, resultdata_data_19) node _resultdata_T_19 = or(_resultdata_T_18, resultdata_data_20) node _resultdata_T_20 = or(_resultdata_T_19, resultdata_data_21) node _resultdata_T_21 = or(_resultdata_T_20, resultdata_data_22) node _resultdata_T_22 = or(_resultdata_T_21, resultdata_data_23) node _resultdata_T_23 = or(_resultdata_T_22, resultdata_data_24) node _resultdata_T_24 = or(_resultdata_T_23, resultdata_data_25) node _resultdata_T_25 = or(_resultdata_T_24, resultdata_data_26) node _resultdata_T_26 = or(_resultdata_T_25, resultdata_data_27) node _resultdata_T_27 = or(_resultdata_T_26, resultdata_data_28) node _resultdata_T_28 = or(_resultdata_T_27, resultdata_data_29) node _resultdata_T_29 = or(_resultdata_T_28, resultdata_data_30) node resultdata = or(_resultdata_T_29, resultdata_data_31) connect response_output.bits.data, resultdata node _response_output_valid_T = and(queueValid, outstanding_req_addr.io.deq.valid) connect response_output.valid, _response_output_valid_T node _outstanding_req_addr_io_deq_ready_T = and(queueValid, response_output.ready) connect outstanding_req_addr.io.deq.ready, _outstanding_req_addr_io_deq_ready_T node _T_479 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_480 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<1>(0h0)) node _T_481 = and(_T_479, _T_480) connect Queue4_L2RespInternal.io.deq.ready, _T_481 node _T_482 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_483 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<1>(0h1)) node _T_484 = and(_T_482, _T_483) connect Queue4_L2RespInternal_1.io.deq.ready, _T_484 node _T_485 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_486 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<2>(0h2)) node _T_487 = and(_T_485, _T_486) connect Queue4_L2RespInternal_2.io.deq.ready, _T_487 node _T_488 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_489 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<2>(0h3)) node _T_490 = and(_T_488, _T_489) connect Queue4_L2RespInternal_3.io.deq.ready, _T_490 node _T_491 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_492 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<3>(0h4)) node _T_493 = and(_T_491, _T_492) connect Queue4_L2RespInternal_4.io.deq.ready, _T_493 node _T_494 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_495 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<3>(0h5)) node _T_496 = and(_T_494, _T_495) connect Queue4_L2RespInternal_5.io.deq.ready, _T_496 node _T_497 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_498 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<3>(0h6)) node _T_499 = and(_T_497, _T_498) connect Queue4_L2RespInternal_6.io.deq.ready, _T_499 node _T_500 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_501 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<3>(0h7)) node _T_502 = and(_T_500, _T_501) connect Queue4_L2RespInternal_7.io.deq.ready, _T_502 node _T_503 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_504 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<4>(0h8)) node _T_505 = and(_T_503, _T_504) connect Queue4_L2RespInternal_8.io.deq.ready, _T_505 node _T_506 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_507 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<4>(0h9)) node _T_508 = and(_T_506, _T_507) connect Queue4_L2RespInternal_9.io.deq.ready, _T_508 node _T_509 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_510 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<4>(0ha)) node _T_511 = and(_T_509, _T_510) connect Queue4_L2RespInternal_10.io.deq.ready, _T_511 node _T_512 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_513 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<4>(0hb)) node _T_514 = and(_T_512, _T_513) connect Queue4_L2RespInternal_11.io.deq.ready, _T_514 node _T_515 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_516 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<4>(0hc)) node _T_517 = and(_T_515, _T_516) connect Queue4_L2RespInternal_12.io.deq.ready, _T_517 node _T_518 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_519 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<4>(0hd)) node _T_520 = and(_T_518, _T_519) connect Queue4_L2RespInternal_13.io.deq.ready, _T_520 node _T_521 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_522 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<4>(0he)) node _T_523 = and(_T_521, _T_522) connect Queue4_L2RespInternal_14.io.deq.ready, _T_523 node _T_524 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_525 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<4>(0hf)) node _T_526 = and(_T_524, _T_525) connect Queue4_L2RespInternal_15.io.deq.ready, _T_526 node _T_527 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_528 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<5>(0h10)) node _T_529 = and(_T_527, _T_528) connect Queue4_L2RespInternal_16.io.deq.ready, _T_529 node _T_530 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_531 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<5>(0h11)) node _T_532 = and(_T_530, _T_531) connect Queue4_L2RespInternal_17.io.deq.ready, _T_532 node _T_533 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_534 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<5>(0h12)) node _T_535 = and(_T_533, _T_534) connect Queue4_L2RespInternal_18.io.deq.ready, _T_535 node _T_536 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_537 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<5>(0h13)) node _T_538 = and(_T_536, _T_537) connect Queue4_L2RespInternal_19.io.deq.ready, _T_538 node _T_539 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_540 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<5>(0h14)) node _T_541 = and(_T_539, _T_540) connect Queue4_L2RespInternal_20.io.deq.ready, _T_541 node _T_542 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_543 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<5>(0h15)) node _T_544 = and(_T_542, _T_543) connect Queue4_L2RespInternal_21.io.deq.ready, _T_544 node _T_545 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_546 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<5>(0h16)) node _T_547 = and(_T_545, _T_546) connect Queue4_L2RespInternal_22.io.deq.ready, _T_547 node _T_548 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_549 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<5>(0h17)) node _T_550 = and(_T_548, _T_549) connect Queue4_L2RespInternal_23.io.deq.ready, _T_550 node _T_551 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_552 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<5>(0h18)) node _T_553 = and(_T_551, _T_552) connect Queue4_L2RespInternal_24.io.deq.ready, _T_553 node _T_554 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_555 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<5>(0h19)) node _T_556 = and(_T_554, _T_555) connect Queue4_L2RespInternal_25.io.deq.ready, _T_556 node _T_557 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_558 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<5>(0h1a)) node _T_559 = and(_T_557, _T_558) connect Queue4_L2RespInternal_26.io.deq.ready, _T_559 node _T_560 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_561 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<5>(0h1b)) node _T_562 = and(_T_560, _T_561) connect Queue4_L2RespInternal_27.io.deq.ready, _T_562 node _T_563 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_564 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<5>(0h1c)) node _T_565 = and(_T_563, _T_564) connect Queue4_L2RespInternal_28.io.deq.ready, _T_565 node _T_566 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_567 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<5>(0h1d)) node _T_568 = and(_T_566, _T_567) connect Queue4_L2RespInternal_29.io.deq.ready, _T_568 node _T_569 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_570 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<5>(0h1e)) node _T_571 = and(_T_569, _T_570) connect Queue4_L2RespInternal_30.io.deq.ready, _T_571 node _T_572 = and(response_output.ready, outstanding_req_addr.io.deq.valid) node _T_573 = eq(outstanding_req_addr.io.deq.bits.tag, UInt<5>(0h1f)) node _T_574 = and(_T_572, _T_573) connect Queue4_L2RespInternal_31.io.deq.ready, _T_574 node _T_575 = and(masterNodeOut.d.ready, masterNodeOut.d.valid) when _T_575 : node opdata = bits(masterNodeOut.d.bits.opcode, 0, 0) when opdata : regreset loginfo_cycles_40 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_80 = add(loginfo_cycles_40, UInt<1>(0h1)) node _loginfo_cycles_T_81 = tail(_loginfo_cycles_T_80, 1) connect loginfo_cycles_40, _loginfo_cycles_T_81 node _T_576 = asUInt(reset) node _T_577 = eq(_T_576, UInt<1>(0h0)) when _T_577 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_40) : printf_85 node _T_578 = asUInt(reset) node _T_579 = eq(_T_578, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "[seq_writer] L2IF: resp(read) data: 0x%x, opnum: %d, gettag: %d\n", masterNodeOut.d.bits.data, global_memop_ackd, masterNodeOut.d.bits.source) : printf_86 else : regreset loginfo_cycles_41 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_82 = add(loginfo_cycles_41, UInt<1>(0h1)) node _loginfo_cycles_T_83 = tail(_loginfo_cycles_T_82, 1) connect loginfo_cycles_41, _loginfo_cycles_T_83 node _T_580 = asUInt(reset) node _T_581 = eq(_T_580, UInt<1>(0h0)) when _T_581 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_41) : printf_87 node _T_582 = asUInt(reset) node _T_583 = eq(_T_582, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "[seq_writer] L2IF: resp(write) opnum: %d, gettag: %d\n", global_memop_ackd, masterNodeOut.d.bits.source) : printf_88 node _T_584 = and(response_output.ready, response_output.valid) when _T_584 : regreset loginfo_cycles_42 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_84 = add(loginfo_cycles_42, UInt<1>(0h1)) node _loginfo_cycles_T_85 = tail(_loginfo_cycles_T_84, 1) connect loginfo_cycles_42, _loginfo_cycles_T_85 node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_42) : printf_89 node _T_587 = asUInt(reset) node _T_588 = eq(_T_587, UInt<1>(0h0)) when _T_588 : printf(clock, UInt<1>(0h1), "[seq_writer] L2IF: realresp() data: 0x%x, opnum: %d, gettag: %d\n", resultdata, global_memop_resp_to_user, outstanding_req_addr.io.deq.bits.tag) : printf_90 node _T_589 = and(response_latency_injection_q.io.deq.ready, response_latency_injection_q.io.deq.valid) when _T_589 : node _global_memop_ackd_T = add(global_memop_ackd, UInt<1>(0h1)) node _global_memop_ackd_T_1 = tail(_global_memop_ackd_T, 1) connect global_memop_ackd, _global_memop_ackd_T_1 node _T_590 = and(response_output.ready, response_output.valid) when _T_590 : node _global_memop_resp_to_user_T = add(global_memop_resp_to_user, UInt<1>(0h1)) node _global_memop_resp_to_user_T_1 = tail(_global_memop_resp_to_user_T, 1) connect global_memop_resp_to_user, _global_memop_resp_to_user_T_1 extmodule plusarg_reader_142 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_143 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32	module L2MemHelperLatencyInjection_13( // @[L2MemHelperLatencyInjection.scala:29:7] input clock, // @[L2MemHelperLatencyInjection.scala:29:7] input reset, // @[L2MemHelperLatencyInjection.scala:29:7] input auto_master_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_master_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_master_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_master_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_master_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_master_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_master_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [31:0] auto_master_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [255:0] auto_master_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_master_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_master_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_master_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_master_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_master_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_master_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_master_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_master_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_master_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [255:0] auto_master_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_master_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output io_userif_req_ready, // @[L2MemHelperLatencyInjection.scala:33:14] input io_userif_req_valid, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_userif_req_bits_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input [2:0] io_userif_req_bits_size, // @[L2MemHelperLatencyInjection.scala:33:14] input [255:0] io_userif_req_bits_data, // @[L2MemHelperLatencyInjection.scala:33:14] input io_userif_req_bits_cmd, // @[L2MemHelperLatencyInjection.scala:33:14] input io_userif_resp_ready, // @[L2MemHelperLatencyInjection.scala:33:14] output io_userif_resp_valid, // @[L2MemHelperLatencyInjection.scala:33:14] output [255:0] io_userif_resp_bits_data, // @[L2MemHelperLatencyInjection.scala:33:14] output io_userif_no_memops_inflight, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_latency_inject_cycles, // @[L2MemHelperLatencyInjection.scala:33:14] input io_sfence, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_req_ready, // @[L2MemHelperLatencyInjection.scala:33:14] output io_ptw_req_valid, // @[L2MemHelperLatencyInjection.scala:33:14] output [26:0] io_ptw_req_bits_bits_addr, // @[L2MemHelperLatencyInjection.scala:33:14] output io_ptw_req_bits_bits_need_gpa, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_valid, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_ae_ptw, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_ae_final, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pf, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_gf, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_hr, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_hw, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_hx, // @[L2MemHelperLatencyInjection.scala:33:14] input [9:0] io_ptw_resp_bits_pte_reserved_for_future, // @[L2MemHelperLatencyInjection.scala:33:14] input [43:0] io_ptw_resp_bits_pte_ppn, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_resp_bits_pte_reserved_for_software, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pte_d, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pte_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pte_g, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pte_u, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pte_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pte_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pte_r, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_pte_v, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_resp_bits_level, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_homogeneous, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_gpa_valid, // @[L2MemHelperLatencyInjection.scala:33:14] input [38:0] io_ptw_resp_bits_gpa_bits, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_resp_bits_gpa_is_pte, // @[L2MemHelperLatencyInjection.scala:33:14] input [3:0] io_ptw_ptbr_mode, // @[L2MemHelperLatencyInjection.scala:33:14] input [43:0] io_ptw_ptbr_ppn, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_debug, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_cease, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_wfi, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_status_isa, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_status_dprv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_dv, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_status_prv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_v, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_mpv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_gva, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_tsr, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_tw, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_tvm, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_mxr, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_sum, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_mprv, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_status_fs, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_status_mpp, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_spp, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_mpie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_spie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_mie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_status_sie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_hstatus_spvp, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_hstatus_spv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_hstatus_gva, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_debug, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_cease, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_wfi, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_gstatus_isa, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_gstatus_dprv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_dv, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_gstatus_prv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_v, // @[L2MemHelperLatencyInjection.scala:33:14] input [22:0] io_ptw_gstatus_zero2, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_mpv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_gva, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_mbe, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_sbe, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_gstatus_sxl, // @[L2MemHelperLatencyInjection.scala:33:14] input [7:0] io_ptw_gstatus_zero1, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_tsr, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_tw, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_tvm, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_mxr, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_sum, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_mprv, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_gstatus_fs, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_gstatus_mpp, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_gstatus_vs, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_spp, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_mpie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_ube, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_spie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_upie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_mie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_hie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_sie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_gstatus_uie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_0_cfg_l, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_pmp_0_cfg_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_0_cfg_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_0_cfg_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_0_cfg_r, // @[L2MemHelperLatencyInjection.scala:33:14] input [29:0] io_ptw_pmp_0_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_pmp_0_mask, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_1_cfg_l, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_pmp_1_cfg_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_1_cfg_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_1_cfg_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_1_cfg_r, // @[L2MemHelperLatencyInjection.scala:33:14] input [29:0] io_ptw_pmp_1_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_pmp_1_mask, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_2_cfg_l, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_pmp_2_cfg_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_2_cfg_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_2_cfg_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_2_cfg_r, // @[L2MemHelperLatencyInjection.scala:33:14] input [29:0] io_ptw_pmp_2_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_pmp_2_mask, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_3_cfg_l, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_pmp_3_cfg_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_3_cfg_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_3_cfg_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_3_cfg_r, // @[L2MemHelperLatencyInjection.scala:33:14] input [29:0] io_ptw_pmp_3_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_pmp_3_mask, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_4_cfg_l, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_pmp_4_cfg_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_4_cfg_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_4_cfg_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_4_cfg_r, // @[L2MemHelperLatencyInjection.scala:33:14] input [29:0] io_ptw_pmp_4_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_pmp_4_mask, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_5_cfg_l, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_pmp_5_cfg_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_5_cfg_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_5_cfg_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_5_cfg_r, // @[L2MemHelperLatencyInjection.scala:33:14] input [29:0] io_ptw_pmp_5_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_pmp_5_mask, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_6_cfg_l, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_pmp_6_cfg_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_6_cfg_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_6_cfg_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_6_cfg_r, // @[L2MemHelperLatencyInjection.scala:33:14] input [29:0] io_ptw_pmp_6_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_pmp_6_mask, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_7_cfg_l, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_ptw_pmp_7_cfg_a, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_7_cfg_x, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_7_cfg_w, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_pmp_7_cfg_r, // @[L2MemHelperLatencyInjection.scala:33:14] input [29:0] io_ptw_pmp_7_addr, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_ptw_pmp_7_mask, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_customCSRs_csrs_0_ren, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_customCSRs_csrs_0_wen, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_ptw_customCSRs_csrs_0_wdata, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_ptw_customCSRs_csrs_0_value, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_customCSRs_csrs_1_ren, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_customCSRs_csrs_1_wen, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_ptw_customCSRs_csrs_1_wdata, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_ptw_customCSRs_csrs_1_value, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_customCSRs_csrs_2_ren, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_customCSRs_csrs_2_wen, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_ptw_customCSRs_csrs_2_wdata, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_ptw_customCSRs_csrs_2_value, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_customCSRs_csrs_3_ren, // @[L2MemHelperLatencyInjection.scala:33:14] input io_ptw_customCSRs_csrs_3_wen, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_ptw_customCSRs_csrs_3_wdata, // @[L2MemHelperLatencyInjection.scala:33:14] input [63:0] io_ptw_customCSRs_csrs_3_value, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_valid, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_debug, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_cease, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_wfi, // @[L2MemHelperLatencyInjection.scala:33:14] input [31:0] io_status_bits_isa, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_status_bits_dprv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_dv, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_status_bits_prv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_v, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_sd, // @[L2MemHelperLatencyInjection.scala:33:14] input [22:0] io_status_bits_zero2, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_mpv, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_gva, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_mbe, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_sbe, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_status_bits_sxl, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_status_bits_uxl, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_sd_rv32, // @[L2MemHelperLatencyInjection.scala:33:14] input [7:0] io_status_bits_zero1, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_tsr, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_tw, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_tvm, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_mxr, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_sum, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_mprv, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_status_bits_xs, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_status_bits_fs, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_status_bits_mpp, // @[L2MemHelperLatencyInjection.scala:33:14] input [1:0] io_status_bits_vs, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_spp, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_mpie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_ube, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_spie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_upie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_mie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_hie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_sie, // @[L2MemHelperLatencyInjection.scala:33:14] input io_status_bits_uie // @[L2MemHelperLatencyInjection.scala:33:14] ); wire _response_latency_injection_q_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:245:44] wire [4:0] _response_latency_injection_q_io_deq_bits_source; // @[L2MemHelperLatencyInjection.scala:245:44] wire [255:0] _response_latency_injection_q_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:245:44] wire _Queue4_L2RespInternal_31_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_31_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_31_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_30_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_30_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_30_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_29_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_29_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_29_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_28_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_28_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_28_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_27_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_27_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_27_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_26_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_26_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_26_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_25_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_25_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_25_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_24_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_24_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_24_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_23_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_23_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_23_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_22_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_22_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_22_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_21_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_21_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_21_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_20_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_20_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_20_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_19_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_19_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_19_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_18_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_18_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_18_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_17_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_17_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_17_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_16_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_16_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_16_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_15_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_15_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_15_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_14_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_14_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_14_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_13_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_13_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_13_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_12_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_12_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_12_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_11_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_11_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_11_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_10_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_10_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_10_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_9_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_9_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_9_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_8_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_8_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_8_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_7_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_7_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_7_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_6_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_6_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_6_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_5_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_5_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_5_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_4_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_4_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_4_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_3_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_3_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_3_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_2_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_2_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_2_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_1_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_1_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_1_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11] wire _Queue4_L2RespInternal_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11] wire [255:0] _Queue4_L2RespInternal_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11] wire _request_latency_injection_q_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:151:43] wire _tags_for_issue_Q_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:94:32] wire _tags_for_issue_Q_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:94:32] wire [4:0] _tags_for_issue_Q_io_deq_bits; // @[L2MemHelperLatencyInjection.scala:94:32] wire _outstanding_req_addr_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:91:36] wire _outstanding_req_addr_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:91:36] wire [4:0] _outstanding_req_addr_io_deq_bits_addrindex; // @[L2MemHelperLatencyInjection.scala:91:36] wire [4:0] _outstanding_req_addr_io_deq_bits_tag; // @[L2MemHelperLatencyInjection.scala:91:36] wire _tlb_io_req_ready; // @[L2MemHelperLatencyInjection.scala:68:19] wire _tlb_io_resp_miss; // @[L2MemHelperLatencyInjection.scala:68:19] wire [31:0] _tlb_io_resp_paddr; // @[L2MemHelperLatencyInjection.scala:68:19] wire auto_master_out_a_ready_0 = auto_master_out_a_ready; // @[L2MemHelperLatencyInjection.scala:29:7] wire auto_master_out_d_valid_0 = auto_master_out_d_valid; // @[L2MemHelperLatencyInjection.scala:29:7] wire [2:0] auto_master_out_d_bits_opcode_0 = auto_master_out_d_bits_opcode; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] auto_master_out_d_bits_param_0 = auto_master_out_d_bits_param; // @[L2MemHelperLatencyInjection.scala:29:7] wire [3:0] auto_master_out_d_bits_size_0 = auto_master_out_d_bits_size; // @[L2MemHelperLatencyInjection.scala:29:7] wire [4:0] auto_master_out_d_bits_source_0 = auto_master_out_d_bits_source; // @[L2MemHelperLatencyInjection.scala:29:7] wire [2:0] auto_master_out_d_bits_sink_0 = auto_master_out_d_bits_sink; // @[L2MemHelperLatencyInjection.scala:29:7] wire auto_master_out_d_bits_denied_0 = auto_master_out_d_bits_denied; // @[L2MemHelperLatencyInjection.scala:29:7] wire [255:0] auto_master_out_d_bits_data_0 = auto_master_out_d_bits_data; // @[L2MemHelperLatencyInjection.scala:29:7] wire auto_master_out_d_bits_corrupt_0 = auto_master_out_d_bits_corrupt; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_userif_req_valid_0 = io_userif_req_valid; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_userif_req_bits_addr_0 = io_userif_req_bits_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire [2:0] io_userif_req_bits_size_0 = io_userif_req_bits_size; // @[L2MemHelperLatencyInjection.scala:29:7] wire [255:0] io_userif_req_bits_data_0 = io_userif_req_bits_data; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_userif_req_bits_cmd_0 = io_userif_req_bits_cmd; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_userif_resp_ready_0 = io_userif_resp_ready; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_latency_inject_cycles_0 = io_latency_inject_cycles; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_sfence_0 = io_sfence; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_req_ready_0 = io_ptw_req_ready; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_valid_0 = io_ptw_resp_valid; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_ae_ptw_0 = io_ptw_resp_bits_ae_ptw; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_ae_final_0 = io_ptw_resp_bits_ae_final; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pf_0 = io_ptw_resp_bits_pf; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_gf_0 = io_ptw_resp_bits_gf; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_hr_0 = io_ptw_resp_bits_hr; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_hw_0 = io_ptw_resp_bits_hw; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_hx_0 = io_ptw_resp_bits_hx; // @[L2MemHelperLatencyInjection.scala:29:7] wire [9:0] io_ptw_resp_bits_pte_reserved_for_future_0 = io_ptw_resp_bits_pte_reserved_for_future; // @[L2MemHelperLatencyInjection.scala:29:7] wire [43:0] io_ptw_resp_bits_pte_ppn_0 = io_ptw_resp_bits_pte_ppn; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_resp_bits_pte_reserved_for_software_0 = io_ptw_resp_bits_pte_reserved_for_software; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pte_d_0 = io_ptw_resp_bits_pte_d; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pte_a_0 = io_ptw_resp_bits_pte_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pte_g_0 = io_ptw_resp_bits_pte_g; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pte_u_0 = io_ptw_resp_bits_pte_u; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pte_x_0 = io_ptw_resp_bits_pte_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pte_w_0 = io_ptw_resp_bits_pte_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pte_r_0 = io_ptw_resp_bits_pte_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_pte_v_0 = io_ptw_resp_bits_pte_v; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_resp_bits_level_0 = io_ptw_resp_bits_level; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_homogeneous_0 = io_ptw_resp_bits_homogeneous; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_gpa_valid_0 = io_ptw_resp_bits_gpa_valid; // @[L2MemHelperLatencyInjection.scala:29:7] wire [38:0] io_ptw_resp_bits_gpa_bits_0 = io_ptw_resp_bits_gpa_bits; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_gpa_is_pte_0 = io_ptw_resp_bits_gpa_is_pte; // @[L2MemHelperLatencyInjection.scala:29:7] wire [3:0] io_ptw_ptbr_mode_0 = io_ptw_ptbr_mode; // @[L2MemHelperLatencyInjection.scala:29:7] wire [43:0] io_ptw_ptbr_ppn_0 = io_ptw_ptbr_ppn; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_debug_0 = io_ptw_status_debug; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_cease_0 = io_ptw_status_cease; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_wfi_0 = io_ptw_status_wfi; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_status_isa_0 = io_ptw_status_isa; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_status_dprv_0 = io_ptw_status_dprv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_dv_0 = io_ptw_status_dv; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_status_prv_0 = io_ptw_status_prv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_v_0 = io_ptw_status_v; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_mpv_0 = io_ptw_status_mpv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_gva_0 = io_ptw_status_gva; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_tsr_0 = io_ptw_status_tsr; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_tw_0 = io_ptw_status_tw; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_tvm_0 = io_ptw_status_tvm; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_mxr_0 = io_ptw_status_mxr; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_sum_0 = io_ptw_status_sum; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_mprv_0 = io_ptw_status_mprv; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_status_fs_0 = io_ptw_status_fs; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_status_mpp_0 = io_ptw_status_mpp; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_spp_0 = io_ptw_status_spp; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_mpie_0 = io_ptw_status_mpie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_spie_0 = io_ptw_status_spie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_mie_0 = io_ptw_status_mie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_sie_0 = io_ptw_status_sie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_hstatus_spvp_0 = io_ptw_hstatus_spvp; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_hstatus_spv_0 = io_ptw_hstatus_spv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_hstatus_gva_0 = io_ptw_hstatus_gva; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_debug_0 = io_ptw_gstatus_debug; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_cease_0 = io_ptw_gstatus_cease; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_wfi_0 = io_ptw_gstatus_wfi; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_gstatus_isa_0 = io_ptw_gstatus_isa; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_gstatus_dprv_0 = io_ptw_gstatus_dprv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_dv_0 = io_ptw_gstatus_dv; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_gstatus_prv_0 = io_ptw_gstatus_prv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_v_0 = io_ptw_gstatus_v; // @[L2MemHelperLatencyInjection.scala:29:7] wire [22:0] io_ptw_gstatus_zero2_0 = io_ptw_gstatus_zero2; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_mpv_0 = io_ptw_gstatus_mpv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_gva_0 = io_ptw_gstatus_gva; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_mbe_0 = io_ptw_gstatus_mbe; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_sbe_0 = io_ptw_gstatus_sbe; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_gstatus_sxl_0 = io_ptw_gstatus_sxl; // @[L2MemHelperLatencyInjection.scala:29:7] wire [7:0] io_ptw_gstatus_zero1_0 = io_ptw_gstatus_zero1; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_tsr_0 = io_ptw_gstatus_tsr; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_tw_0 = io_ptw_gstatus_tw; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_tvm_0 = io_ptw_gstatus_tvm; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_mxr_0 = io_ptw_gstatus_mxr; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_sum_0 = io_ptw_gstatus_sum; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_mprv_0 = io_ptw_gstatus_mprv; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_gstatus_fs_0 = io_ptw_gstatus_fs; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_gstatus_mpp_0 = io_ptw_gstatus_mpp; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_gstatus_vs_0 = io_ptw_gstatus_vs; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_spp_0 = io_ptw_gstatus_spp; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_mpie_0 = io_ptw_gstatus_mpie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_ube_0 = io_ptw_gstatus_ube; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_spie_0 = io_ptw_gstatus_spie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_upie_0 = io_ptw_gstatus_upie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_mie_0 = io_ptw_gstatus_mie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_hie_0 = io_ptw_gstatus_hie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_sie_0 = io_ptw_gstatus_sie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_uie_0 = io_ptw_gstatus_uie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_0_cfg_l_0 = io_ptw_pmp_0_cfg_l; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_0_cfg_a_0 = io_ptw_pmp_0_cfg_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_0_cfg_x_0 = io_ptw_pmp_0_cfg_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_0_cfg_w_0 = io_ptw_pmp_0_cfg_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_0_cfg_r_0 = io_ptw_pmp_0_cfg_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_pmp_0_addr_0 = io_ptw_pmp_0_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_pmp_0_mask_0 = io_ptw_pmp_0_mask; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_1_cfg_l_0 = io_ptw_pmp_1_cfg_l; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_1_cfg_a_0 = io_ptw_pmp_1_cfg_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_1_cfg_x_0 = io_ptw_pmp_1_cfg_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_1_cfg_w_0 = io_ptw_pmp_1_cfg_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_1_cfg_r_0 = io_ptw_pmp_1_cfg_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_pmp_1_addr_0 = io_ptw_pmp_1_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_pmp_1_mask_0 = io_ptw_pmp_1_mask; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_2_cfg_l_0 = io_ptw_pmp_2_cfg_l; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_2_cfg_a_0 = io_ptw_pmp_2_cfg_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_2_cfg_x_0 = io_ptw_pmp_2_cfg_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_2_cfg_w_0 = io_ptw_pmp_2_cfg_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_2_cfg_r_0 = io_ptw_pmp_2_cfg_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_pmp_2_addr_0 = io_ptw_pmp_2_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_pmp_2_mask_0 = io_ptw_pmp_2_mask; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_3_cfg_l_0 = io_ptw_pmp_3_cfg_l; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_3_cfg_a_0 = io_ptw_pmp_3_cfg_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_3_cfg_x_0 = io_ptw_pmp_3_cfg_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_3_cfg_w_0 = io_ptw_pmp_3_cfg_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_3_cfg_r_0 = io_ptw_pmp_3_cfg_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_pmp_3_addr_0 = io_ptw_pmp_3_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_pmp_3_mask_0 = io_ptw_pmp_3_mask; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_4_cfg_l_0 = io_ptw_pmp_4_cfg_l; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_4_cfg_a_0 = io_ptw_pmp_4_cfg_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_4_cfg_x_0 = io_ptw_pmp_4_cfg_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_4_cfg_w_0 = io_ptw_pmp_4_cfg_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_4_cfg_r_0 = io_ptw_pmp_4_cfg_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_pmp_4_addr_0 = io_ptw_pmp_4_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_pmp_4_mask_0 = io_ptw_pmp_4_mask; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_5_cfg_l_0 = io_ptw_pmp_5_cfg_l; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_5_cfg_a_0 = io_ptw_pmp_5_cfg_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_5_cfg_x_0 = io_ptw_pmp_5_cfg_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_5_cfg_w_0 = io_ptw_pmp_5_cfg_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_5_cfg_r_0 = io_ptw_pmp_5_cfg_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_pmp_5_addr_0 = io_ptw_pmp_5_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_pmp_5_mask_0 = io_ptw_pmp_5_mask; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_6_cfg_l_0 = io_ptw_pmp_6_cfg_l; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_6_cfg_a_0 = io_ptw_pmp_6_cfg_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_6_cfg_x_0 = io_ptw_pmp_6_cfg_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_6_cfg_w_0 = io_ptw_pmp_6_cfg_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_6_cfg_r_0 = io_ptw_pmp_6_cfg_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_pmp_6_addr_0 = io_ptw_pmp_6_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_pmp_6_mask_0 = io_ptw_pmp_6_mask; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_7_cfg_l_0 = io_ptw_pmp_7_cfg_l; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_7_cfg_a_0 = io_ptw_pmp_7_cfg_a; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_7_cfg_x_0 = io_ptw_pmp_7_cfg_x; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_7_cfg_w_0 = io_ptw_pmp_7_cfg_w; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_pmp_7_cfg_r_0 = io_ptw_pmp_7_cfg_r; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_pmp_7_addr_0 = io_ptw_pmp_7_addr; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_ptw_pmp_7_mask_0 = io_ptw_pmp_7_mask; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_0_ren_0 = io_ptw_customCSRs_csrs_0_ren; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_0_wen_0 = io_ptw_customCSRs_csrs_0_wen; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_0_wdata_0 = io_ptw_customCSRs_csrs_0_wdata; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_0_value_0 = io_ptw_customCSRs_csrs_0_value; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_1_ren_0 = io_ptw_customCSRs_csrs_1_ren; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_1_wen_0 = io_ptw_customCSRs_csrs_1_wen; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_1_wdata_0 = io_ptw_customCSRs_csrs_1_wdata; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_1_value_0 = io_ptw_customCSRs_csrs_1_value; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_2_ren_0 = io_ptw_customCSRs_csrs_2_ren; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_2_wen_0 = io_ptw_customCSRs_csrs_2_wen; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_2_wdata_0 = io_ptw_customCSRs_csrs_2_wdata; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_2_value_0 = io_ptw_customCSRs_csrs_2_value; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_3_ren_0 = io_ptw_customCSRs_csrs_3_ren; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_3_wen_0 = io_ptw_customCSRs_csrs_3_wen; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_3_wdata_0 = io_ptw_customCSRs_csrs_3_wdata; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_3_value_0 = io_ptw_customCSRs_csrs_3_value; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_valid_0 = io_status_valid; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_debug_0 = io_status_bits_debug; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_cease_0 = io_status_bits_cease; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_wfi_0 = io_status_bits_wfi; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] io_status_bits_isa_0 = io_status_bits_isa; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_status_bits_dprv_0 = io_status_bits_dprv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_dv_0 = io_status_bits_dv; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_status_bits_prv_0 = io_status_bits_prv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_v_0 = io_status_bits_v; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_sd_0 = io_status_bits_sd; // @[L2MemHelperLatencyInjection.scala:29:7] wire [22:0] io_status_bits_zero2_0 = io_status_bits_zero2; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_mpv_0 = io_status_bits_mpv; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_gva_0 = io_status_bits_gva; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_mbe_0 = io_status_bits_mbe; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_sbe_0 = io_status_bits_sbe; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_status_bits_sxl_0 = io_status_bits_sxl; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_status_bits_uxl_0 = io_status_bits_uxl; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_sd_rv32_0 = io_status_bits_sd_rv32; // @[L2MemHelperLatencyInjection.scala:29:7] wire [7:0] io_status_bits_zero1_0 = io_status_bits_zero1; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_tsr_0 = io_status_bits_tsr; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_tw_0 = io_status_bits_tw; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_tvm_0 = io_status_bits_tvm; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_mxr_0 = io_status_bits_mxr; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_sum_0 = io_status_bits_sum; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_mprv_0 = io_status_bits_mprv; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_status_bits_xs_0 = io_status_bits_xs; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_status_bits_fs_0 = io_status_bits_fs; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_status_bits_mpp_0 = io_status_bits_mpp; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_status_bits_vs_0 = io_status_bits_vs; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_spp_0 = io_status_bits_spp; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_mpie_0 = io_status_bits_mpie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_ube_0 = io_status_bits_ube; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_spie_0 = io_status_bits_spie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_upie_0 = io_status_bits_upie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_mie_0 = io_status_bits_mie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_hie_0 = io_status_bits_hie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_sie_0 = io_status_bits_sie; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_status_bits_uie_0 = io_status_bits_uie; // @[L2MemHelperLatencyInjection.scala:29:7] wire _printf_T = reset; // @[annotations.scala:102:49] wire _printf_T_2 = reset; // @[annotations.scala:102:49] wire io_ptw_req_bits_bits_vstage1 = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_req_bits_bits_stage2 = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_resp_bits_fragmented_superpage = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_mbe = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_sbe = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_sd_rv32 = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_ube = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_upie = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_hie = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_uie = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_hstatus_vtsr = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_hstatus_vtw = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_hstatus_vtvm = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_hstatus_hu = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_hstatus_vsbe = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_0_set = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_1_set = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_2_stall = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_2_set = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_3_stall = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_customCSRs_csrs_3_set = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire bundle_corrupt = 1'h0; // @[Edges.scala:460:17] wire _legal_T_125 = 1'h0; // @[Parameters.scala:684:29] wire _legal_T_131 = 1'h0; // @[Parameters.scala:684:54] wire bundle_1_corrupt = 1'h0; // @[Edges.scala:480:17] wire [15:0] io_ptw_ptbr_asid = 16'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_req_bits_valid = 1'h1; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_status_sd = 1'h1; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_gstatus_sd = 1'h1; // @[L2MemHelperLatencyInjection.scala:29:7] wire _legal_T = 1'h1; // @[Parameters.scala:92:28] wire _legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _legal_T_63 = 1'h1; // @[Parameters.scala:92:28] wire _legal_T_64 = 1'h1; // @[Parameters.scala:92:38] wire _legal_T_65 = 1'h1; // @[Parameters.scala:92:33] wire _legal_T_66 = 1'h1; // @[Parameters.scala:684:29] wire _legal_T_73 = 1'h1; // @[Parameters.scala:92:28] wire [22:0] io_ptw_status_zero2 = 23'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [7:0] io_ptw_status_zero1 = 8'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_status_xs = 2'h3; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_gstatus_xs = 2'h3; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_status_vs = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_0_cfg_res = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_1_cfg_res = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_2_cfg_res = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_3_cfg_res = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_4_cfg_res = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_5_cfg_res = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_6_cfg_res = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_pmp_7_cfg_res = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_status_sxl = 2'h2; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_status_uxl = 2'h2; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_hstatus_vsxl = 2'h2; // @[L2MemHelperLatencyInjection.scala:29:7] wire [1:0] io_ptw_gstatus_uxl = 2'h2; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_2_sdata = 64'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [63:0] io_ptw_customCSRs_csrs_3_sdata = 64'h0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [2:0] bundle_param = 3'h0; // @[Edges.scala:460:17] wire [2:0] bundle_1_opcode = 3'h0; // @[Edges.scala:480:17] wire [2:0] bundle_1_param = 3'h0; // @[Edges.scala:480:17] wire [255:0] bundle_data = 256'h0; // @[Edges.scala:460:17] wire [2:0] bundle_opcode = 3'h4; // @[Edges.scala:460:17] wire masterNodeOut_a_ready = auto_master_out_a_ready_0; // @[MixedNode.scala:542:17] wire masterNodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] masterNodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] masterNodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] masterNodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [4:0] masterNodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] masterNodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [31:0] masterNodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [255:0] masterNodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire masterNodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire masterNodeOut_d_ready; // @[MixedNode.scala:542:17] wire masterNodeOut_d_valid = auto_master_out_d_valid_0; // @[MixedNode.scala:542:17] wire [2:0] masterNodeOut_d_bits_opcode = auto_master_out_d_bits_opcode_0; // @[MixedNode.scala:542:17] wire [1:0] masterNodeOut_d_bits_param = auto_master_out_d_bits_param_0; // @[MixedNode.scala:542:17] wire [3:0] masterNodeOut_d_bits_size = auto_master_out_d_bits_size_0; // @[MixedNode.scala:542:17] wire [4:0] masterNodeOut_d_bits_source = auto_master_out_d_bits_source_0; // @[MixedNode.scala:542:17] wire [2:0] masterNodeOut_d_bits_sink = auto_master_out_d_bits_sink_0; // @[MixedNode.scala:542:17] wire masterNodeOut_d_bits_denied = auto_master_out_d_bits_denied_0; // @[MixedNode.scala:542:17] wire [255:0] masterNodeOut_d_bits_data = auto_master_out_d_bits_data_0; // @[MixedNode.scala:542:17] wire masterNodeOut_d_bits_corrupt = auto_master_out_d_bits_corrupt_0; // @[MixedNode.scala:542:17] wire request_input_ready; // @[L2MemHelperLatencyInjection.scala:44:27] wire request_input_valid = io_userif_req_valid_0; // @[L2MemHelperLatencyInjection.scala:29:7, :44:27] wire [63:0] request_input_bits_addr = io_userif_req_bits_addr_0; // @[L2MemHelperLatencyInjection.scala:29:7, :44:27] wire [2:0] request_input_bits_size = io_userif_req_bits_size_0; // @[L2MemHelperLatencyInjection.scala:29:7, :44:27] wire [255:0] request_input_bits_data = io_userif_req_bits_data_0; // @[L2MemHelperLatencyInjection.scala:29:7, :44:27] wire request_input_bits_cmd = io_userif_req_bits_cmd_0; // @[L2MemHelperLatencyInjection.scala:29:7, :44:27] wire response_output_ready = io_userif_resp_ready_0; // @[L2MemHelperLatencyInjection.scala:29:7, :53:29] wire response_output_valid; // @[L2MemHelperLatencyInjection.scala:53:29] wire [255:0] response_output_bits_data; // @[L2MemHelperLatencyInjection.scala:53:29] wire _io_userif_no_memops_inflight_T; // @[L2MemHelperLatencyInjection.scala:128:57] wire [2:0] auto_master_out_a_bits_opcode_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [2:0] auto_master_out_a_bits_param_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [3:0] auto_master_out_a_bits_size_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [4:0] auto_master_out_a_bits_source_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] auto_master_out_a_bits_address_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [31:0] auto_master_out_a_bits_mask_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [255:0] auto_master_out_a_bits_data_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire auto_master_out_a_bits_corrupt_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire auto_master_out_a_valid_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire auto_master_out_d_ready_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_userif_req_ready_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [255:0] io_userif_resp_bits_data_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_userif_resp_valid_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_userif_no_memops_inflight_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire [26:0] io_ptw_req_bits_bits_addr_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_req_bits_bits_need_gpa_0; // @[L2MemHelperLatencyInjection.scala:29:7] wire io_ptw_req_valid_0; // @[L2MemHelperLatencyInjection.scala:29:7] assign auto_master_out_a_valid_0 = masterNodeOut_a_valid; // @[MixedNode.scala:542:17] assign auto_master_out_a_bits_opcode_0 = masterNodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign auto_master_out_a_bits_param_0 = masterNodeOut_a_bits_param; // @[MixedNode.scala:542:17] assign auto_master_out_a_bits_size_0 = masterNodeOut_a_bits_size; // @[MixedNode.scala:542:17] assign auto_master_out_a_bits_source_0 = masterNodeOut_a_bits_source; // @[MixedNode.scala:542:17] assign auto_master_out_a_bits_address_0 = masterNodeOut_a_bits_address; // @[MixedNode.scala:542:17] assign auto_master_out_a_bits_mask_0 = masterNodeOut_a_bits_mask; // @[MixedNode.scala:542:17] assign auto_master_out_a_bits_data_0 = masterNodeOut_a_bits_data; // @[MixedNode.scala:542:17] assign auto_master_out_a_bits_corrupt_0 = masterNodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign auto_master_out_d_ready_0 = masterNodeOut_d_ready; // @[MixedNode.scala:542:17] wire _request_input_ready_T_4; // @[Misc.scala:26:53] assign io_userif_req_ready_0 = request_input_ready; // @[L2MemHelperLatencyInjection.scala:29:7, :44:27] wire _response_output_valid_T; // @[Misc.scala:26:53] assign io_userif_resp_valid_0 = response_output_valid; // @[L2MemHelperLatencyInjection.scala:29:7, :53:29] wire [255:0] resultdata; // @[L2MemHelperLatencyInjection.scala:307:15] assign io_userif_resp_bits_data_0 = response_output_bits_data; // @[L2MemHelperLatencyInjection.scala:29:7, :53:29] reg status_debug; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_cease; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_wfi; // @[L2MemHelperLatencyInjection.scala:62:19] reg [31:0] status_isa; // @[L2MemHelperLatencyInjection.scala:62:19] reg [1:0] status_dprv; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_dv; // @[L2MemHelperLatencyInjection.scala:62:19] reg [1:0] status_prv; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_v; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_sd; // @[L2MemHelperLatencyInjection.scala:62:19] reg [22:0] status_zero2; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_mpv; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_gva; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_mbe; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_sbe; // @[L2MemHelperLatencyInjection.scala:62:19] reg [1:0] status_sxl; // @[L2MemHelperLatencyInjection.scala:62:19] reg [1:0] status_uxl; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_sd_rv32; // @[L2MemHelperLatencyInjection.scala:62:19] reg [7:0] status_zero1; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_tsr; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_tw; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_tvm; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_mxr; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_sum; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_mprv; // @[L2MemHelperLatencyInjection.scala:62:19] reg [1:0] status_xs; // @[L2MemHelperLatencyInjection.scala:62:19] reg [1:0] status_fs; // @[L2MemHelperLatencyInjection.scala:62:19] reg [1:0] status_mpp; // @[L2MemHelperLatencyInjection.scala:62:19] reg [1:0] status_vs; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_spp; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_mpie; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_ube; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_spie; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_upie; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_mie; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_hie; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_sie; // @[L2MemHelperLatencyInjection.scala:62:19] reg status_uie; // @[L2MemHelperLatencyInjection.scala:62:19] reg [63:0] loginfo_cycles; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T = {1'h0, loginfo_cycles} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1 = _loginfo_cycles_T[63:0]; // @[Util.scala:19:38] wire _tlb_ready_T = ~_tlb_io_resp_miss; // @[L2MemHelperLatencyInjection.scala:68:19, :74:39] wire tlb_ready = _tlb_io_req_ready & _tlb_ready_T; // @[L2MemHelperLatencyInjection.scala:68:19, :74:{36,39}] reg [5:0] tags_init_reg; // @[L2MemHelperLatencyInjection.scala:98:30] wire _T_4 = tags_init_reg != 6'h20; // @[L2MemHelperLatencyInjection.scala:98:30, :99:23] reg [63:0] loginfo_cycles_1; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_2 = {1'h0, loginfo_cycles_1} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_3 = _loginfo_cycles_T_2[63:0]; // @[Util.scala:19:38] wire [6:0] _tags_init_reg_T = {1'h0, tags_init_reg} + 7'h1; // @[L2MemHelperLatencyInjection.scala:98:30, :104:38] wire [5:0] _tags_init_reg_T_1 = _tags_init_reg_T[5:0]; // @[L2MemHelperLatencyInjection.scala:104:38] wire [70:0] _addr_mask_check_T = 71'h1 << request_input_bits_size; // @[L2MemHelperLatencyInjection.scala:44:27, :108:36] wire [71:0] _addr_mask_check_T_1 = {1'h0, _addr_mask_check_T} - 72'h1; // @[L2MemHelperLatencyInjection.scala:108:{36,64}] wire [70:0] addr_mask_check = _addr_mask_check_T_1[70:0]; // @[L2MemHelperLatencyInjection.scala:108:64] wire _assertcheck_T = ~request_input_valid; // @[L2MemHelperLatencyInjection.scala:44:27, :109:30] wire [70:0] _assertcheck_T_1 = {7'h0, addr_mask_check[63:0] & request_input_bits_addr}; // @[L2MemHelperLatencyInjection.scala:44:27, :108:64, :109:81] wire _assertcheck_T_2 = _assertcheck_T_1 == 71'h0; // @[L2MemHelperLatencyInjection.scala:108:64, :109:{81,100}] wire _assertcheck_T_3 = _assertcheck_T \| _assertcheck_T_2; // @[L2MemHelperLatencyInjection.scala:109:{30,52,100}] reg assertcheck; // @[L2MemHelperLatencyInjection.scala:109:28] reg [63:0] loginfo_cycles_2; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_4 = {1'h0, loginfo_cycles_2} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_5 = _loginfo_cycles_T_4[63:0]; // @[Util.scala:19:38] reg [63:0] global_memop_accepted; // @[L2MemHelperLatencyInjection.scala:117:38] wire [64:0] _global_memop_accepted_T = {1'h0, global_memop_accepted} + 65'h1; // @[L2MemHelperLatencyInjection.scala:117:38, :119:52] wire [63:0] _global_memop_accepted_T_1 = _global_memop_accepted_T[63:0]; // @[L2MemHelperLatencyInjection.scala:119:52] reg [63:0] global_memop_sent; // @[L2MemHelperLatencyInjection.scala:122:34] reg [63:0] global_memop_ackd; // @[L2MemHelperLatencyInjection.scala:124:34] reg [63:0] global_memop_resp_to_user; // @[L2MemHelperLatencyInjection.scala:126:42] assign _io_userif_no_memops_inflight_T = global_memop_accepted == global_memop_ackd; // @[L2MemHelperLatencyInjection.scala:117:38, :124:34, :128:57] assign io_userif_no_memops_inflight_0 = _io_userif_no_memops_inflight_T; // @[L2MemHelperLatencyInjection.scala:29:7, :128:57] wire [64:0] _GEN = {1'h0, global_memop_sent}; // @[L2MemHelperLatencyInjection.scala:122:34, :130:54] wire [64:0] _GEN_0 = {1'h0, global_memop_ackd}; // @[L2MemHelperLatencyInjection.scala:124:34, :130:54] wire [64:0] _GEN_1 = _GEN - _GEN_0; // @[L2MemHelperLatencyInjection.scala:130:54] wire [64:0] _free_outstanding_op_slots_T; // @[L2MemHelperLatencyInjection.scala:130:54] assign _free_outstanding_op_slots_T = _GEN_1; // @[L2MemHelperLatencyInjection.scala:130:54] wire [64:0] _assert_free_outstanding_op_slots_T; // @[L2MemHelperLatencyInjection.scala:131:61] assign _assert_free_outstanding_op_slots_T = _GEN_1; // @[L2MemHelperLatencyInjection.scala:130:54, :131:61] wire [63:0] _free_outstanding_op_slots_T_1 = _free_outstanding_op_slots_T[63:0]; // @[L2MemHelperLatencyInjection.scala:130:54] wire free_outstanding_op_slots = _free_outstanding_op_slots_T_1 < 64'h20; // @[L2MemHelperLatencyInjection.scala:130:{54,75}] wire [63:0] _assert_free_outstanding_op_slots_T_1 = _assert_free_outstanding_op_slots_T[63:0]; // @[L2MemHelperLatencyInjection.scala:131:61] wire assert_free_outstanding_op_slots = _assert_free_outstanding_op_slots_T_1 < 64'h21; // @[L2MemHelperLatencyInjection.scala:131:{61,82}] reg [63:0] loginfo_cycles_3; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_6 = {1'h0, loginfo_cycles_3} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_7 = _loginfo_cycles_T_6[63:0]; // @[Util.scala:19:38] wire [64:0] _global_memop_sent_T = _GEN + 65'h1; // @[L2MemHelperLatencyInjection.scala:130:54, :140:44] wire [63:0] _global_memop_sent_T_1 = _global_memop_sent_T[63:0]; // @[L2MemHelperLatencyInjection.scala:140:44] reg [63:0] cur_cycle; // @[L2MemHelperLatencyInjection.scala:146:26] wire [64:0] _cur_cycle_T = {1'h0, cur_cycle} + 65'h1; // @[L2MemHelperLatencyInjection.scala:146:26, :147:26] wire [63:0] _cur_cycle_T_1 = _cur_cycle_T[63:0]; // @[L2MemHelperLatencyInjection.scala:147:26] wire [31:0] _GEN_2 = {_tlb_io_resp_paddr[31:14], _tlb_io_resp_paddr[13:0] ^ 14'h3000}; // @[Parameters.scala:137:31] wire [31:0] _legal_T_4; // @[Parameters.scala:137:31] assign _legal_T_4 = _GEN_2; // @[Parameters.scala:137:31] wire [31:0] _legal_T_67; // @[Parameters.scala:137:31] assign _legal_T_67 = _GEN_2; // @[Parameters.scala:137:31] wire [32:0] _legal_T_5 = {1'h0, _legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_6 = _legal_T_5 & 33'h9A013000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_7 = _legal_T_6; // @[Parameters.scala:137:46] wire _legal_T_8 = _legal_T_7 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_T_9 = _legal_T_8; // @[Parameters.scala:684:54] wire _legal_T_62 = _legal_T_9; // @[Parameters.scala:684:54, :686:26] wire _GEN_3 = request_input_bits_size != 3'h7; // @[Parameters.scala:92:38] wire _legal_T_11; // @[Parameters.scala:92:38] assign _legal_T_11 = _GEN_3; // @[Parameters.scala:92:38] wire _legal_T_74; // @[Parameters.scala:92:38] assign _legal_T_74 = _GEN_3; // @[Parameters.scala:92:38] wire _legal_T_12 = _legal_T_11; // @[Parameters.scala:92:{33,38}] wire _legal_T_13 = _legal_T_12; // @[Parameters.scala:684:29] wire [31:0] _legal_T_14; // @[Parameters.scala:137:31] wire [32:0] _legal_T_15 = {1'h0, _legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_16 = _legal_T_15 & 33'h9A012000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_17 = _legal_T_16; // @[Parameters.scala:137:46] wire _legal_T_18 = _legal_T_17 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_4 = {_tlb_io_resp_paddr[31:17], _tlb_io_resp_paddr[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31] wire [31:0] _legal_T_19; // @[Parameters.scala:137:31] assign _legal_T_19 = _GEN_4; // @[Parameters.scala:137:31] wire [31:0] _legal_T_24; // @[Parameters.scala:137:31] assign _legal_T_24 = _GEN_4; // @[Parameters.scala:137:31] wire [31:0] _legal_T_126; // @[Parameters.scala:137:31] assign _legal_T_126 = _GEN_4; // @[Parameters.scala:137:31] wire [32:0] _legal_T_20 = {1'h0, _legal_T_19}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_21 = _legal_T_20 & 33'h98013000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_22 = _legal_T_21; // @[Parameters.scala:137:46] wire _legal_T_23 = _legal_T_22 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _legal_T_25 = {1'h0, _legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_26 = _legal_T_25 & 33'h9A010000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_27 = _legal_T_26; // @[Parameters.scala:137:46] wire _legal_T_28 = _legal_T_27 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_5 = {_tlb_io_resp_paddr[31:26], _tlb_io_resp_paddr[25:0] ^ 26'h2000000}; // @[Parameters.scala:137:31] wire [31:0] _legal_T_29; // @[Parameters.scala:137:31] assign _legal_T_29 = _GEN_5; // @[Parameters.scala:137:31] wire [31:0] _legal_T_87; // @[Parameters.scala:137:31] assign _legal_T_87 = _GEN_5; // @[Parameters.scala:137:31] wire [32:0] _legal_T_30 = {1'h0, _legal_T_29}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_31 = _legal_T_30 & 33'h9A010000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_32 = _legal_T_31; // @[Parameters.scala:137:46] wire _legal_T_33 = _legal_T_32 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_6 = {_tlb_io_resp_paddr[31:28], _tlb_io_resp_paddr[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31] wire [31:0] _legal_T_34; // @[Parameters.scala:137:31] assign _legal_T_34 = _GEN_6; // @[Parameters.scala:137:31] wire [31:0] _legal_T_39; // @[Parameters.scala:137:31] assign _legal_T_39 = _GEN_6; // @[Parameters.scala:137:31] wire [31:0] _legal_T_97; // @[Parameters.scala:137:31] assign _legal_T_97 = _GEN_6; // @[Parameters.scala:137:31] wire [31:0] _legal_T_102; // @[Parameters.scala:137:31] assign _legal_T_102 = _GEN_6; // @[Parameters.scala:137:31] wire [32:0] _legal_T_35 = {1'h0, _legal_T_34}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_36 = _legal_T_35 & 33'h98000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_37 = _legal_T_36; // @[Parameters.scala:137:46] wire _legal_T_38 = _legal_T_37 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _legal_T_40 = {1'h0, _legal_T_39}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_41 = _legal_T_40 & 33'h9A010000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_42 = _legal_T_41; // @[Parameters.scala:137:46] wire _legal_T_43 = _legal_T_42 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_7 = {_tlb_io_resp_paddr[31:29], _tlb_io_resp_paddr[28:0] ^ 29'h10000000}; // @[Parameters.scala:137:31] wire [31:0] _legal_T_44; // @[Parameters.scala:137:31] assign _legal_T_44 = _GEN_7; // @[Parameters.scala:137:31] wire [31:0] _legal_T_107; // @[Parameters.scala:137:31] assign _legal_T_107 = _GEN_7; // @[Parameters.scala:137:31] wire [32:0] _legal_T_45 = {1'h0, _legal_T_44}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_46 = _legal_T_45 & 33'h9A013000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_47 = _legal_T_46; // @[Parameters.scala:137:46] wire _legal_T_48 = _legal_T_47 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_8 = _tlb_io_resp_paddr ^ 32'h80000000; // @[Parameters.scala:137:31] wire [31:0] _legal_T_49; // @[Parameters.scala:137:31] assign _legal_T_49 = _GEN_8; // @[Parameters.scala:137:31] wire [31:0] _legal_T_112; // @[Parameters.scala:137:31] assign _legal_T_112 = _GEN_8; // @[Parameters.scala:137:31] wire [32:0] _legal_T_50 = {1'h0, _legal_T_49}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_51 = _legal_T_50 & 33'h90000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_52 = _legal_T_51; // @[Parameters.scala:137:46] wire _legal_T_53 = _legal_T_52 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_T_54 = _legal_T_18 \| _legal_T_23; // @[Parameters.scala:685:42] wire _legal_T_55 = _legal_T_54 \| _legal_T_28; // @[Parameters.scala:685:42] wire _legal_T_56 = _legal_T_55 \| _legal_T_33; // @[Parameters.scala:685:42] wire _legal_T_57 = _legal_T_56 \| _legal_T_38; // @[Parameters.scala:685:42] wire _legal_T_58 = _legal_T_57 \| _legal_T_43; // @[Parameters.scala:685:42] wire _legal_T_59 = _legal_T_58 \| _legal_T_48; // @[Parameters.scala:685:42] wire _legal_T_60 = _legal_T_59 \| _legal_T_53; // @[Parameters.scala:685:42] wire _legal_T_61 = _legal_T_13 & _legal_T_60; // @[Parameters.scala:684:{29,54}, :685:42] wire legal = _legal_T_62 \| _legal_T_61; // @[Parameters.scala:684:54, :686:26] wire [31:0] _a_mask_T; // @[Misc.scala:222:10] wire [3:0] bundle_size; // @[Edges.scala:460:17] wire [4:0] bundle_source; // @[Edges.scala:460:17] wire [31:0] bundle_address; // @[Edges.scala:460:17] wire [31:0] bundle_mask; // @[Edges.scala:460:17] wire [3:0] _GEN_9 = {1'h0, request_input_bits_size}; // @[Edges.scala:463:15] assign bundle_size = _GEN_9; // @[Edges.scala:460:17, :463:15] wire [3:0] bundle_1_size; // @[Edges.scala:480:17] assign bundle_1_size = _GEN_9; // @[Edges.scala:463:15, :480:17] wire [4:0] _GEN_10 = {2'h0, request_input_bits_size}; // @[Misc.scala:202:34] wire [4:0] _a_mask_sizeOH_T; // @[Misc.scala:202:34] assign _a_mask_sizeOH_T = _GEN_10; // @[Misc.scala:202:34] wire [4:0] _a_mask_sizeOH_T_3; // @[Misc.scala:202:34] assign _a_mask_sizeOH_T_3 = _GEN_10; // @[Misc.scala:202:34] wire [4:0] _a_mask_sizeOH_shiftAmount_T = _a_mask_sizeOH_T; // @[OneHot.scala:64:31] wire [2:0] a_mask_sizeOH_shiftAmount = _a_mask_sizeOH_shiftAmount_T[2:0]; // @[OneHot.scala:64:{31,49}] wire [7:0] _a_mask_sizeOH_T_1 = 8'h1 << a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [4:0] _a_mask_sizeOH_T_2 = _a_mask_sizeOH_T_1[4:0]; // @[OneHot.scala:65:{12,27}] wire [4:0] a_mask_sizeOH = {_a_mask_sizeOH_T_2[4:1], 1'h1}; // @[OneHot.scala:65:27] wire _GEN_11 = request_input_bits_size > 3'h4; // @[Misc.scala:206:21] wire a_mask_sub_sub_sub_sub_sub_0_1; // @[Misc.scala:206:21] assign a_mask_sub_sub_sub_sub_sub_0_1 = _GEN_11; // @[Misc.scala:206:21] wire a_mask_sub_sub_sub_sub_sub_0_1_1; // @[Misc.scala:206:21] assign a_mask_sub_sub_sub_sub_sub_0_1_1 = _GEN_11; // @[Misc.scala:206:21] wire a_mask_sub_sub_sub_sub_size = a_mask_sizeOH[4]; // @[Misc.scala:202:81, :209:26] wire a_mask_sub_sub_sub_sub_bit = _tlb_io_resp_paddr[4]; // @[Misc.scala:210:26] wire a_mask_sub_sub_sub_sub_bit_1 = _tlb_io_resp_paddr[4]; // @[Misc.scala:210:26] wire a_mask_sub_sub_sub_sub_1_2 = a_mask_sub_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_sub_sub_sub_nbit = ~a_mask_sub_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire a_mask_sub_sub_sub_sub_0_2 = a_mask_sub_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_sub_sub_sub_acc_T = a_mask_sub_sub_sub_sub_size & a_mask_sub_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_sub_sub_0_1 = a_mask_sub_sub_sub_sub_sub_0_1 \| _a_mask_sub_sub_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _a_mask_sub_sub_sub_sub_acc_T_1 = a_mask_sub_sub_sub_sub_size & a_mask_sub_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_sub_sub_1_1 = a_mask_sub_sub_sub_sub_sub_0_1 \| _a_mask_sub_sub_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire a_mask_sub_sub_sub_size = a_mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26] wire a_mask_sub_sub_sub_bit = _tlb_io_resp_paddr[3]; // @[Misc.scala:210:26] wire a_mask_sub_sub_sub_bit_1 = _tlb_io_resp_paddr[3]; // @[Misc.scala:210:26] wire a_mask_sub_sub_sub_nbit = ~a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire a_mask_sub_sub_sub_0_2 = a_mask_sub_sub_sub_sub_0_2 & a_mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_sub_sub_acc_T = a_mask_sub_sub_sub_size & a_mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_sub_0_1 = a_mask_sub_sub_sub_sub_0_1 \| _a_mask_sub_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_sub_1_2 = a_mask_sub_sub_sub_sub_0_2 & a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_sub_sub_acc_T_1 = a_mask_sub_sub_sub_size & a_mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_sub_1_1 = a_mask_sub_sub_sub_sub_0_1 \| _a_mask_sub_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_sub_2_2 = a_mask_sub_sub_sub_sub_1_2 & a_mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_sub_sub_acc_T_2 = a_mask_sub_sub_sub_size & a_mask_sub_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_sub_2_1 = a_mask_sub_sub_sub_sub_1_1 \| _a_mask_sub_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_sub_3_2 = a_mask_sub_sub_sub_sub_1_2 & a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_sub_sub_acc_T_3 = a_mask_sub_sub_sub_size & a_mask_sub_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_sub_3_1 = a_mask_sub_sub_sub_sub_1_1 \| _a_mask_sub_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_size = a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire a_mask_sub_sub_bit = _tlb_io_resp_paddr[2]; // @[Misc.scala:210:26] wire a_mask_sub_sub_bit_1 = _tlb_io_resp_paddr[2]; // @[Misc.scala:210:26] wire a_mask_sub_sub_nbit = ~a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire a_mask_sub_sub_0_2 = a_mask_sub_sub_sub_0_2 & a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_sub_acc_T = a_mask_sub_sub_size & a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_0_1 = a_mask_sub_sub_sub_0_1 \| _a_mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_1_2 = a_mask_sub_sub_sub_0_2 & a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_sub_acc_T_1 = a_mask_sub_sub_size & a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_1_1 = a_mask_sub_sub_sub_0_1 \| _a_mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_2_2 = a_mask_sub_sub_sub_1_2 & a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_sub_acc_T_2 = a_mask_sub_sub_size & a_mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_2_1 = a_mask_sub_sub_sub_1_1 \| _a_mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_3_2 = a_mask_sub_sub_sub_1_2 & a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_sub_acc_T_3 = a_mask_sub_sub_size & a_mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_3_1 = a_mask_sub_sub_sub_1_1 \| _a_mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_4_2 = a_mask_sub_sub_sub_2_2 & a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_sub_acc_T_4 = a_mask_sub_sub_size & a_mask_sub_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_4_1 = a_mask_sub_sub_sub_2_1 \| _a_mask_sub_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_5_2 = a_mask_sub_sub_sub_2_2 & a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_sub_acc_T_5 = a_mask_sub_sub_size & a_mask_sub_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_5_1 = a_mask_sub_sub_sub_2_1 \| _a_mask_sub_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_6_2 = a_mask_sub_sub_sub_3_2 & a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_sub_acc_T_6 = a_mask_sub_sub_size & a_mask_sub_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_6_1 = a_mask_sub_sub_sub_3_1 \| _a_mask_sub_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_7_2 = a_mask_sub_sub_sub_3_2 & a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_sub_acc_T_7 = a_mask_sub_sub_size & a_mask_sub_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_7_1 = a_mask_sub_sub_sub_3_1 \| _a_mask_sub_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire a_mask_sub_size = a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire a_mask_sub_bit = _tlb_io_resp_paddr[1]; // @[Misc.scala:210:26] wire a_mask_sub_bit_1 = _tlb_io_resp_paddr[1]; // @[Misc.scala:210:26] wire a_mask_sub_nbit = ~a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire a_mask_sub_0_2 = a_mask_sub_sub_0_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T = a_mask_sub_size & a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_0_1 = a_mask_sub_sub_0_1 \| _a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire a_mask_sub_1_2 = a_mask_sub_sub_0_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_1 = a_mask_sub_size & a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_1_1 = a_mask_sub_sub_0_1 \| _a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire a_mask_sub_2_2 = a_mask_sub_sub_1_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_2 = a_mask_sub_size & a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_2_1 = a_mask_sub_sub_1_1 \| _a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire a_mask_sub_3_2 = a_mask_sub_sub_1_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_3 = a_mask_sub_size & a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_3_1 = a_mask_sub_sub_1_1 \| _a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire a_mask_sub_4_2 = a_mask_sub_sub_2_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_4 = a_mask_sub_size & a_mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_4_1 = a_mask_sub_sub_2_1 \| _a_mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire a_mask_sub_5_2 = a_mask_sub_sub_2_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_5 = a_mask_sub_size & a_mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_5_1 = a_mask_sub_sub_2_1 \| _a_mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire a_mask_sub_6_2 = a_mask_sub_sub_3_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_6 = a_mask_sub_size & a_mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_6_1 = a_mask_sub_sub_3_1 \| _a_mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire a_mask_sub_7_2 = a_mask_sub_sub_3_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_7 = a_mask_sub_size & a_mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_7_1 = a_mask_sub_sub_3_1 \| _a_mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire a_mask_sub_8_2 = a_mask_sub_sub_4_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_8 = a_mask_sub_size & a_mask_sub_8_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_8_1 = a_mask_sub_sub_4_1 \| _a_mask_sub_acc_T_8; // @[Misc.scala:215:{29,38}] wire a_mask_sub_9_2 = a_mask_sub_sub_4_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_9 = a_mask_sub_size & a_mask_sub_9_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_9_1 = a_mask_sub_sub_4_1 \| _a_mask_sub_acc_T_9; // @[Misc.scala:215:{29,38}] wire a_mask_sub_10_2 = a_mask_sub_sub_5_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_10 = a_mask_sub_size & a_mask_sub_10_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_10_1 = a_mask_sub_sub_5_1 \| _a_mask_sub_acc_T_10; // @[Misc.scala:215:{29,38}] wire a_mask_sub_11_2 = a_mask_sub_sub_5_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_11 = a_mask_sub_size & a_mask_sub_11_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_11_1 = a_mask_sub_sub_5_1 \| _a_mask_sub_acc_T_11; // @[Misc.scala:215:{29,38}] wire a_mask_sub_12_2 = a_mask_sub_sub_6_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_12 = a_mask_sub_size & a_mask_sub_12_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_12_1 = a_mask_sub_sub_6_1 \| _a_mask_sub_acc_T_12; // @[Misc.scala:215:{29,38}] wire a_mask_sub_13_2 = a_mask_sub_sub_6_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_13 = a_mask_sub_size & a_mask_sub_13_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_13_1 = a_mask_sub_sub_6_1 \| _a_mask_sub_acc_T_13; // @[Misc.scala:215:{29,38}] wire a_mask_sub_14_2 = a_mask_sub_sub_7_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_14 = a_mask_sub_size & a_mask_sub_14_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_14_1 = a_mask_sub_sub_7_1 \| _a_mask_sub_acc_T_14; // @[Misc.scala:215:{29,38}] wire a_mask_sub_15_2 = a_mask_sub_sub_7_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_15 = a_mask_sub_size & a_mask_sub_15_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_15_1 = a_mask_sub_sub_7_1 \| _a_mask_sub_acc_T_15; // @[Misc.scala:215:{29,38}] wire a_mask_size = a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire a_mask_bit = _tlb_io_resp_paddr[0]; // @[Misc.scala:210:26] wire a_mask_bit_1 = _tlb_io_resp_paddr[0]; // @[Misc.scala:210:26] wire a_mask_nbit = ~a_mask_bit; // @[Misc.scala:210:26, :211:20] wire a_mask_eq = a_mask_sub_0_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T = a_mask_size & a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc = a_mask_sub_0_1 \| _a_mask_acc_T; // @[Misc.scala:215:{29,38}] wire a_mask_eq_1 = a_mask_sub_0_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_1 = a_mask_size & a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_1 = a_mask_sub_0_1 \| _a_mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire a_mask_eq_2 = a_mask_sub_1_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_2 = a_mask_size & a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_2 = a_mask_sub_1_1 \| _a_mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire a_mask_eq_3 = a_mask_sub_1_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_3 = a_mask_size & a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_3 = a_mask_sub_1_1 \| _a_mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire a_mask_eq_4 = a_mask_sub_2_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_4 = a_mask_size & a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_4 = a_mask_sub_2_1 \| _a_mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire a_mask_eq_5 = a_mask_sub_2_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_5 = a_mask_size & a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_5 = a_mask_sub_2_1 \| _a_mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire a_mask_eq_6 = a_mask_sub_3_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_6 = a_mask_size & a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_6 = a_mask_sub_3_1 \| _a_mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire a_mask_eq_7 = a_mask_sub_3_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_7 = a_mask_size & a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_7 = a_mask_sub_3_1 \| _a_mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire a_mask_eq_8 = a_mask_sub_4_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_8 = a_mask_size & a_mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_8 = a_mask_sub_4_1 \| _a_mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire a_mask_eq_9 = a_mask_sub_4_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_9 = a_mask_size & a_mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_9 = a_mask_sub_4_1 \| _a_mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire a_mask_eq_10 = a_mask_sub_5_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_10 = a_mask_size & a_mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_10 = a_mask_sub_5_1 \| _a_mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire a_mask_eq_11 = a_mask_sub_5_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_11 = a_mask_size & a_mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_11 = a_mask_sub_5_1 \| _a_mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire a_mask_eq_12 = a_mask_sub_6_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_12 = a_mask_size & a_mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_12 = a_mask_sub_6_1 \| _a_mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire a_mask_eq_13 = a_mask_sub_6_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_13 = a_mask_size & a_mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_13 = a_mask_sub_6_1 \| _a_mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire a_mask_eq_14 = a_mask_sub_7_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_14 = a_mask_size & a_mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_14 = a_mask_sub_7_1 \| _a_mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire a_mask_eq_15 = a_mask_sub_7_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_15 = a_mask_size & a_mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_15 = a_mask_sub_7_1 \| _a_mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire a_mask_eq_16 = a_mask_sub_8_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_16 = a_mask_size & a_mask_eq_16; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_16 = a_mask_sub_8_1 \| _a_mask_acc_T_16; // @[Misc.scala:215:{29,38}] wire a_mask_eq_17 = a_mask_sub_8_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_17 = a_mask_size & a_mask_eq_17; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_17 = a_mask_sub_8_1 \| _a_mask_acc_T_17; // @[Misc.scala:215:{29,38}] wire a_mask_eq_18 = a_mask_sub_9_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_18 = a_mask_size & a_mask_eq_18; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_18 = a_mask_sub_9_1 \| _a_mask_acc_T_18; // @[Misc.scala:215:{29,38}] wire a_mask_eq_19 = a_mask_sub_9_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_19 = a_mask_size & a_mask_eq_19; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_19 = a_mask_sub_9_1 \| _a_mask_acc_T_19; // @[Misc.scala:215:{29,38}] wire a_mask_eq_20 = a_mask_sub_10_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_20 = a_mask_size & a_mask_eq_20; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_20 = a_mask_sub_10_1 \| _a_mask_acc_T_20; // @[Misc.scala:215:{29,38}] wire a_mask_eq_21 = a_mask_sub_10_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_21 = a_mask_size & a_mask_eq_21; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_21 = a_mask_sub_10_1 \| _a_mask_acc_T_21; // @[Misc.scala:215:{29,38}] wire a_mask_eq_22 = a_mask_sub_11_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_22 = a_mask_size & a_mask_eq_22; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_22 = a_mask_sub_11_1 \| _a_mask_acc_T_22; // @[Misc.scala:215:{29,38}] wire a_mask_eq_23 = a_mask_sub_11_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_23 = a_mask_size & a_mask_eq_23; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_23 = a_mask_sub_11_1 \| _a_mask_acc_T_23; // @[Misc.scala:215:{29,38}] wire a_mask_eq_24 = a_mask_sub_12_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_24 = a_mask_size & a_mask_eq_24; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_24 = a_mask_sub_12_1 \| _a_mask_acc_T_24; // @[Misc.scala:215:{29,38}] wire a_mask_eq_25 = a_mask_sub_12_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_25 = a_mask_size & a_mask_eq_25; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_25 = a_mask_sub_12_1 \| _a_mask_acc_T_25; // @[Misc.scala:215:{29,38}] wire a_mask_eq_26 = a_mask_sub_13_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_26 = a_mask_size & a_mask_eq_26; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_26 = a_mask_sub_13_1 \| _a_mask_acc_T_26; // @[Misc.scala:215:{29,38}] wire a_mask_eq_27 = a_mask_sub_13_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_27 = a_mask_size & a_mask_eq_27; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_27 = a_mask_sub_13_1 \| _a_mask_acc_T_27; // @[Misc.scala:215:{29,38}] wire a_mask_eq_28 = a_mask_sub_14_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_28 = a_mask_size & a_mask_eq_28; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_28 = a_mask_sub_14_1 \| _a_mask_acc_T_28; // @[Misc.scala:215:{29,38}] wire a_mask_eq_29 = a_mask_sub_14_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_29 = a_mask_size & a_mask_eq_29; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_29 = a_mask_sub_14_1 \| _a_mask_acc_T_29; // @[Misc.scala:215:{29,38}] wire a_mask_eq_30 = a_mask_sub_15_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_30 = a_mask_size & a_mask_eq_30; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_30 = a_mask_sub_15_1 \| _a_mask_acc_T_30; // @[Misc.scala:215:{29,38}] wire a_mask_eq_31 = a_mask_sub_15_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_31 = a_mask_size & a_mask_eq_31; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_31 = a_mask_sub_15_1 \| _a_mask_acc_T_31; // @[Misc.scala:215:{29,38}] wire [1:0] a_mask_lo_lo_lo_lo = {a_mask_acc_1, a_mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_lo_lo_lo_hi = {a_mask_acc_3, a_mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_lo_lo_lo = {a_mask_lo_lo_lo_hi, a_mask_lo_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_lo_hi_lo = {a_mask_acc_5, a_mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_lo_lo_hi_hi = {a_mask_acc_7, a_mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_lo_lo_hi = {a_mask_lo_lo_hi_hi, a_mask_lo_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] a_mask_lo_lo = {a_mask_lo_lo_hi, a_mask_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_hi_lo_lo = {a_mask_acc_9, a_mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_lo_hi_lo_hi = {a_mask_acc_11, a_mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_lo_hi_lo = {a_mask_lo_hi_lo_hi, a_mask_lo_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_hi_hi_lo = {a_mask_acc_13, a_mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_lo_hi_hi_hi = {a_mask_acc_15, a_mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_lo_hi_hi = {a_mask_lo_hi_hi_hi, a_mask_lo_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] a_mask_lo_hi = {a_mask_lo_hi_hi, a_mask_lo_hi_lo}; // @[Misc.scala:222:10] wire [15:0] a_mask_lo = {a_mask_lo_hi, a_mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_lo_lo_lo = {a_mask_acc_17, a_mask_acc_16}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_hi_lo_lo_hi = {a_mask_acc_19, a_mask_acc_18}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_hi_lo_lo = {a_mask_hi_lo_lo_hi, a_mask_hi_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_lo_hi_lo = {a_mask_acc_21, a_mask_acc_20}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_hi_lo_hi_hi = {a_mask_acc_23, a_mask_acc_22}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_hi_lo_hi = {a_mask_hi_lo_hi_hi, a_mask_hi_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] a_mask_hi_lo = {a_mask_hi_lo_hi, a_mask_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_hi_lo_lo = {a_mask_acc_25, a_mask_acc_24}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_hi_hi_lo_hi = {a_mask_acc_27, a_mask_acc_26}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_hi_hi_lo = {a_mask_hi_hi_lo_hi, a_mask_hi_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_hi_hi_lo = {a_mask_acc_29, a_mask_acc_28}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_hi_hi_hi_hi = {a_mask_acc_31, a_mask_acc_30}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_hi_hi_hi = {a_mask_hi_hi_hi_hi, a_mask_hi_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] a_mask_hi_hi = {a_mask_hi_hi_hi, a_mask_hi_hi_lo}; // @[Misc.scala:222:10] wire [15:0] a_mask_hi = {a_mask_hi_hi, a_mask_hi_lo}; // @[Misc.scala:222:10] assign _a_mask_T = {a_mask_hi, a_mask_lo}; // @[Misc.scala:222:10] assign bundle_mask = _a_mask_T; // @[Misc.scala:222:10] wire [510:0] _T_31 = {255'h0, request_input_bits_data} << {503'h0, request_input_bits_addr[4:0], 3'h0}; // @[L2MemHelperLatencyInjection.scala:44:27, :172:{58,86}] wire [32:0] _legal_T_68 = {1'h0, _legal_T_67}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_69 = _legal_T_68 & 33'h9A113000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_70 = _legal_T_69; // @[Parameters.scala:137:46] wire _legal_T_71 = _legal_T_70 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_T_72 = _legal_T_71; // @[Parameters.scala:684:54] wire _legal_T_132 = _legal_T_72; // @[Parameters.scala:684:54, :686:26] wire _legal_T_75 = _legal_T_74; // @[Parameters.scala:92:{33,38}] wire _legal_T_76 = _legal_T_75; // @[Parameters.scala:684:29] wire [31:0] _legal_T_77; // @[Parameters.scala:137:31] wire [32:0] _legal_T_78 = {1'h0, _legal_T_77}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_79 = _legal_T_78 & 33'h9A112000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_80 = _legal_T_79; // @[Parameters.scala:137:46] wire _legal_T_81 = _legal_T_80 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _legal_T_82 = {_tlb_io_resp_paddr[31:21], _tlb_io_resp_paddr[20:0] ^ 21'h100000}; // @[Parameters.scala:137:31] wire [32:0] _legal_T_83 = {1'h0, _legal_T_82}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_84 = _legal_T_83 & 33'h9A103000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_85 = _legal_T_84; // @[Parameters.scala:137:46] wire _legal_T_86 = _legal_T_85 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _legal_T_88 = {1'h0, _legal_T_87}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_89 = _legal_T_88 & 33'h9A110000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_90 = _legal_T_89; // @[Parameters.scala:137:46] wire _legal_T_91 = _legal_T_90 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _legal_T_92 = {_tlb_io_resp_paddr[31:26], _tlb_io_resp_paddr[25:0] ^ 26'h2010000}; // @[Parameters.scala:137:31] wire [32:0] _legal_T_93 = {1'h0, _legal_T_92}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_94 = _legal_T_93 & 33'h9A113000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_95 = _legal_T_94; // @[Parameters.scala:137:46] wire _legal_T_96 = _legal_T_95 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _legal_T_98 = {1'h0, _legal_T_97}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_99 = _legal_T_98 & 33'h98000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_100 = _legal_T_99; // @[Parameters.scala:137:46] wire _legal_T_101 = _legal_T_100 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _legal_T_103 = {1'h0, _legal_T_102}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_104 = _legal_T_103 & 33'h9A110000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_105 = _legal_T_104; // @[Parameters.scala:137:46] wire _legal_T_106 = _legal_T_105 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _legal_T_108 = {1'h0, _legal_T_107}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_109 = _legal_T_108 & 33'h9A113000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_110 = _legal_T_109; // @[Parameters.scala:137:46] wire _legal_T_111 = _legal_T_110 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _legal_T_113 = {1'h0, _legal_T_112}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_114 = _legal_T_113 & 33'h90000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_115 = _legal_T_114; // @[Parameters.scala:137:46] wire _legal_T_116 = _legal_T_115 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_T_117 = _legal_T_81 \| _legal_T_86; // @[Parameters.scala:685:42] wire _legal_T_118 = _legal_T_117 \| _legal_T_91; // @[Parameters.scala:685:42] wire _legal_T_119 = _legal_T_118 \| _legal_T_96; // @[Parameters.scala:685:42] wire _legal_T_120 = _legal_T_119 \| _legal_T_101; // @[Parameters.scala:685:42] wire _legal_T_121 = _legal_T_120 \| _legal_T_106; // @[Parameters.scala:685:42] wire _legal_T_122 = _legal_T_121 \| _legal_T_111; // @[Parameters.scala:685:42] wire _legal_T_123 = _legal_T_122 \| _legal_T_116; // @[Parameters.scala:685:42] wire _legal_T_124 = _legal_T_76 & _legal_T_123; // @[Parameters.scala:684:{29,54}, :685:42] wire [32:0] _legal_T_127 = {1'h0, _legal_T_126}; // @[Parameters.scala:137:{31,41}] wire [32:0] _legal_T_128 = _legal_T_127 & 33'h9A110000; // @[Parameters.scala:137:{41,46}] wire [32:0] _legal_T_129 = _legal_T_128; // @[Parameters.scala:137:46] wire _legal_T_130 = _legal_T_129 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _legal_T_133 = _legal_T_132 \| _legal_T_124; // @[Parameters.scala:684:54, :686:26] wire legal_1 = _legal_T_133; // @[Parameters.scala:686:26] wire [31:0] _a_mask_T_1; // @[Misc.scala:222:10] wire [4:0] bundle_1_source; // @[Edges.scala:480:17] wire [31:0] bundle_1_address; // @[Edges.scala:480:17] wire [31:0] bundle_1_mask; // @[Edges.scala:480:17] wire [255:0] bundle_1_data; // @[Edges.scala:480:17] wire [4:0] _a_mask_sizeOH_shiftAmount_T_1 = _a_mask_sizeOH_T_3; // @[OneHot.scala:64:31] wire [2:0] a_mask_sizeOH_shiftAmount_1 = _a_mask_sizeOH_shiftAmount_T_1[2:0]; // @[OneHot.scala:64:{31,49}] wire [7:0] _a_mask_sizeOH_T_4 = 8'h1 << a_mask_sizeOH_shiftAmount_1; // @[OneHot.scala:64:49, :65:12] wire [4:0] _a_mask_sizeOH_T_5 = _a_mask_sizeOH_T_4[4:0]; // @[OneHot.scala:65:{12,27}] wire [4:0] a_mask_sizeOH_1 = {_a_mask_sizeOH_T_5[4:1], 1'h1}; // @[OneHot.scala:65:27] wire a_mask_sub_sub_sub_sub_size_1 = a_mask_sizeOH_1[4]; // @[Misc.scala:202:81, :209:26] wire a_mask_sub_sub_sub_sub_1_2_1 = a_mask_sub_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire a_mask_sub_sub_sub_sub_nbit_1 = ~a_mask_sub_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire a_mask_sub_sub_sub_sub_0_2_1 = a_mask_sub_sub_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_sub_sub_sub_acc_T_2 = a_mask_sub_sub_sub_sub_size_1 & a_mask_sub_sub_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_sub_sub_0_1_1 = a_mask_sub_sub_sub_sub_sub_0_1_1 \| _a_mask_sub_sub_sub_sub_acc_T_2; // @[Misc.scala:206:21, :215:{29,38}] wire _a_mask_sub_sub_sub_sub_acc_T_3 = a_mask_sub_sub_sub_sub_size_1 & a_mask_sub_sub_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_sub_sub_1_1_1 = a_mask_sub_sub_sub_sub_sub_0_1_1 \| _a_mask_sub_sub_sub_sub_acc_T_3; // @[Misc.scala:206:21, :215:{29,38}] wire a_mask_sub_sub_sub_size_1 = a_mask_sizeOH_1[3]; // @[Misc.scala:202:81, :209:26] wire a_mask_sub_sub_sub_nbit_1 = ~a_mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire a_mask_sub_sub_sub_0_2_1 = a_mask_sub_sub_sub_sub_0_2_1 & a_mask_sub_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_sub_sub_acc_T_4 = a_mask_sub_sub_sub_size_1 & a_mask_sub_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_sub_0_1_1 = a_mask_sub_sub_sub_sub_0_1_1 \| _a_mask_sub_sub_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_sub_1_2_1 = a_mask_sub_sub_sub_sub_0_2_1 & a_mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_sub_sub_acc_T_5 = a_mask_sub_sub_sub_size_1 & a_mask_sub_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_sub_1_1_1 = a_mask_sub_sub_sub_sub_0_1_1 \| _a_mask_sub_sub_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_sub_2_2_1 = a_mask_sub_sub_sub_sub_1_2_1 & a_mask_sub_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_sub_sub_acc_T_6 = a_mask_sub_sub_sub_size_1 & a_mask_sub_sub_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_sub_2_1_1 = a_mask_sub_sub_sub_sub_1_1_1 \| _a_mask_sub_sub_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_sub_3_2_1 = a_mask_sub_sub_sub_sub_1_2_1 & a_mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_sub_sub_acc_T_7 = a_mask_sub_sub_sub_size_1 & a_mask_sub_sub_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_sub_3_1_1 = a_mask_sub_sub_sub_sub_1_1_1 \| _a_mask_sub_sub_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_size_1 = a_mask_sizeOH_1[2]; // @[Misc.scala:202:81, :209:26] wire a_mask_sub_sub_nbit_1 = ~a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire a_mask_sub_sub_0_2_1 = a_mask_sub_sub_sub_0_2_1 & a_mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_sub_acc_T_8 = a_mask_sub_sub_size_1 & a_mask_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_0_1_1 = a_mask_sub_sub_sub_0_1_1 \| _a_mask_sub_sub_acc_T_8; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_1_2_1 = a_mask_sub_sub_sub_0_2_1 & a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_sub_acc_T_9 = a_mask_sub_sub_size_1 & a_mask_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_1_1_1 = a_mask_sub_sub_sub_0_1_1 \| _a_mask_sub_sub_acc_T_9; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_2_2_1 = a_mask_sub_sub_sub_1_2_1 & a_mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_sub_acc_T_10 = a_mask_sub_sub_size_1 & a_mask_sub_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_2_1_1 = a_mask_sub_sub_sub_1_1_1 \| _a_mask_sub_sub_acc_T_10; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_3_2_1 = a_mask_sub_sub_sub_1_2_1 & a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_sub_acc_T_11 = a_mask_sub_sub_size_1 & a_mask_sub_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_3_1_1 = a_mask_sub_sub_sub_1_1_1 \| _a_mask_sub_sub_acc_T_11; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_4_2_1 = a_mask_sub_sub_sub_2_2_1 & a_mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_sub_acc_T_12 = a_mask_sub_sub_size_1 & a_mask_sub_sub_4_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_4_1_1 = a_mask_sub_sub_sub_2_1_1 \| _a_mask_sub_sub_acc_T_12; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_5_2_1 = a_mask_sub_sub_sub_2_2_1 & a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_sub_acc_T_13 = a_mask_sub_sub_size_1 & a_mask_sub_sub_5_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_5_1_1 = a_mask_sub_sub_sub_2_1_1 \| _a_mask_sub_sub_acc_T_13; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_6_2_1 = a_mask_sub_sub_sub_3_2_1 & a_mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_sub_acc_T_14 = a_mask_sub_sub_size_1 & a_mask_sub_sub_6_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_6_1_1 = a_mask_sub_sub_sub_3_1_1 \| _a_mask_sub_sub_acc_T_14; // @[Misc.scala:215:{29,38}] wire a_mask_sub_sub_7_2_1 = a_mask_sub_sub_sub_3_2_1 & a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_sub_acc_T_15 = a_mask_sub_sub_size_1 & a_mask_sub_sub_7_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_sub_7_1_1 = a_mask_sub_sub_sub_3_1_1 \| _a_mask_sub_sub_acc_T_15; // @[Misc.scala:215:{29,38}] wire a_mask_sub_size_1 = a_mask_sizeOH_1[1]; // @[Misc.scala:202:81, :209:26] wire a_mask_sub_nbit_1 = ~a_mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire a_mask_sub_0_2_1 = a_mask_sub_sub_0_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_16 = a_mask_sub_size_1 & a_mask_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_0_1_1 = a_mask_sub_sub_0_1_1 \| _a_mask_sub_acc_T_16; // @[Misc.scala:215:{29,38}] wire a_mask_sub_1_2_1 = a_mask_sub_sub_0_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_17 = a_mask_sub_size_1 & a_mask_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_1_1_1 = a_mask_sub_sub_0_1_1 \| _a_mask_sub_acc_T_17; // @[Misc.scala:215:{29,38}] wire a_mask_sub_2_2_1 = a_mask_sub_sub_1_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_18 = a_mask_sub_size_1 & a_mask_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_2_1_1 = a_mask_sub_sub_1_1_1 \| _a_mask_sub_acc_T_18; // @[Misc.scala:215:{29,38}] wire a_mask_sub_3_2_1 = a_mask_sub_sub_1_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_19 = a_mask_sub_size_1 & a_mask_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_3_1_1 = a_mask_sub_sub_1_1_1 \| _a_mask_sub_acc_T_19; // @[Misc.scala:215:{29,38}] wire a_mask_sub_4_2_1 = a_mask_sub_sub_2_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_20 = a_mask_sub_size_1 & a_mask_sub_4_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_4_1_1 = a_mask_sub_sub_2_1_1 \| _a_mask_sub_acc_T_20; // @[Misc.scala:215:{29,38}] wire a_mask_sub_5_2_1 = a_mask_sub_sub_2_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_21 = a_mask_sub_size_1 & a_mask_sub_5_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_5_1_1 = a_mask_sub_sub_2_1_1 \| _a_mask_sub_acc_T_21; // @[Misc.scala:215:{29,38}] wire a_mask_sub_6_2_1 = a_mask_sub_sub_3_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_22 = a_mask_sub_size_1 & a_mask_sub_6_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_6_1_1 = a_mask_sub_sub_3_1_1 \| _a_mask_sub_acc_T_22; // @[Misc.scala:215:{29,38}] wire a_mask_sub_7_2_1 = a_mask_sub_sub_3_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_23 = a_mask_sub_size_1 & a_mask_sub_7_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_7_1_1 = a_mask_sub_sub_3_1_1 \| _a_mask_sub_acc_T_23; // @[Misc.scala:215:{29,38}] wire a_mask_sub_8_2_1 = a_mask_sub_sub_4_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_24 = a_mask_sub_size_1 & a_mask_sub_8_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_8_1_1 = a_mask_sub_sub_4_1_1 \| _a_mask_sub_acc_T_24; // @[Misc.scala:215:{29,38}] wire a_mask_sub_9_2_1 = a_mask_sub_sub_4_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_25 = a_mask_sub_size_1 & a_mask_sub_9_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_9_1_1 = a_mask_sub_sub_4_1_1 \| _a_mask_sub_acc_T_25; // @[Misc.scala:215:{29,38}] wire a_mask_sub_10_2_1 = a_mask_sub_sub_5_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_26 = a_mask_sub_size_1 & a_mask_sub_10_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_10_1_1 = a_mask_sub_sub_5_1_1 \| _a_mask_sub_acc_T_26; // @[Misc.scala:215:{29,38}] wire a_mask_sub_11_2_1 = a_mask_sub_sub_5_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_27 = a_mask_sub_size_1 & a_mask_sub_11_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_11_1_1 = a_mask_sub_sub_5_1_1 \| _a_mask_sub_acc_T_27; // @[Misc.scala:215:{29,38}] wire a_mask_sub_12_2_1 = a_mask_sub_sub_6_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_28 = a_mask_sub_size_1 & a_mask_sub_12_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_12_1_1 = a_mask_sub_sub_6_1_1 \| _a_mask_sub_acc_T_28; // @[Misc.scala:215:{29,38}] wire a_mask_sub_13_2_1 = a_mask_sub_sub_6_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_29 = a_mask_sub_size_1 & a_mask_sub_13_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_13_1_1 = a_mask_sub_sub_6_1_1 \| _a_mask_sub_acc_T_29; // @[Misc.scala:215:{29,38}] wire a_mask_sub_14_2_1 = a_mask_sub_sub_7_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_sub_acc_T_30 = a_mask_sub_size_1 & a_mask_sub_14_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_14_1_1 = a_mask_sub_sub_7_1_1 \| _a_mask_sub_acc_T_30; // @[Misc.scala:215:{29,38}] wire a_mask_sub_15_2_1 = a_mask_sub_sub_7_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_sub_acc_T_31 = a_mask_sub_size_1 & a_mask_sub_15_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_sub_15_1_1 = a_mask_sub_sub_7_1_1 \| _a_mask_sub_acc_T_31; // @[Misc.scala:215:{29,38}] wire a_mask_size_1 = a_mask_sizeOH_1[0]; // @[Misc.scala:202:81, :209:26] wire a_mask_nbit_1 = ~a_mask_bit_1; // @[Misc.scala:210:26, :211:20] wire a_mask_eq_32 = a_mask_sub_0_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_32 = a_mask_size_1 & a_mask_eq_32; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_32 = a_mask_sub_0_1_1 \| _a_mask_acc_T_32; // @[Misc.scala:215:{29,38}] wire a_mask_eq_33 = a_mask_sub_0_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_33 = a_mask_size_1 & a_mask_eq_33; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_33 = a_mask_sub_0_1_1 \| _a_mask_acc_T_33; // @[Misc.scala:215:{29,38}] wire a_mask_eq_34 = a_mask_sub_1_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_34 = a_mask_size_1 & a_mask_eq_34; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_34 = a_mask_sub_1_1_1 \| _a_mask_acc_T_34; // @[Misc.scala:215:{29,38}] wire a_mask_eq_35 = a_mask_sub_1_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_35 = a_mask_size_1 & a_mask_eq_35; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_35 = a_mask_sub_1_1_1 \| _a_mask_acc_T_35; // @[Misc.scala:215:{29,38}] wire a_mask_eq_36 = a_mask_sub_2_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_36 = a_mask_size_1 & a_mask_eq_36; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_36 = a_mask_sub_2_1_1 \| _a_mask_acc_T_36; // @[Misc.scala:215:{29,38}] wire a_mask_eq_37 = a_mask_sub_2_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_37 = a_mask_size_1 & a_mask_eq_37; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_37 = a_mask_sub_2_1_1 \| _a_mask_acc_T_37; // @[Misc.scala:215:{29,38}] wire a_mask_eq_38 = a_mask_sub_3_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_38 = a_mask_size_1 & a_mask_eq_38; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_38 = a_mask_sub_3_1_1 \| _a_mask_acc_T_38; // @[Misc.scala:215:{29,38}] wire a_mask_eq_39 = a_mask_sub_3_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_39 = a_mask_size_1 & a_mask_eq_39; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_39 = a_mask_sub_3_1_1 \| _a_mask_acc_T_39; // @[Misc.scala:215:{29,38}] wire a_mask_eq_40 = a_mask_sub_4_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_40 = a_mask_size_1 & a_mask_eq_40; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_40 = a_mask_sub_4_1_1 \| _a_mask_acc_T_40; // @[Misc.scala:215:{29,38}] wire a_mask_eq_41 = a_mask_sub_4_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_41 = a_mask_size_1 & a_mask_eq_41; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_41 = a_mask_sub_4_1_1 \| _a_mask_acc_T_41; // @[Misc.scala:215:{29,38}] wire a_mask_eq_42 = a_mask_sub_5_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_42 = a_mask_size_1 & a_mask_eq_42; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_42 = a_mask_sub_5_1_1 \| _a_mask_acc_T_42; // @[Misc.scala:215:{29,38}] wire a_mask_eq_43 = a_mask_sub_5_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_43 = a_mask_size_1 & a_mask_eq_43; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_43 = a_mask_sub_5_1_1 \| _a_mask_acc_T_43; // @[Misc.scala:215:{29,38}] wire a_mask_eq_44 = a_mask_sub_6_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_44 = a_mask_size_1 & a_mask_eq_44; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_44 = a_mask_sub_6_1_1 \| _a_mask_acc_T_44; // @[Misc.scala:215:{29,38}] wire a_mask_eq_45 = a_mask_sub_6_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_45 = a_mask_size_1 & a_mask_eq_45; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_45 = a_mask_sub_6_1_1 \| _a_mask_acc_T_45; // @[Misc.scala:215:{29,38}] wire a_mask_eq_46 = a_mask_sub_7_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_46 = a_mask_size_1 & a_mask_eq_46; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_46 = a_mask_sub_7_1_1 \| _a_mask_acc_T_46; // @[Misc.scala:215:{29,38}] wire a_mask_eq_47 = a_mask_sub_7_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_47 = a_mask_size_1 & a_mask_eq_47; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_47 = a_mask_sub_7_1_1 \| _a_mask_acc_T_47; // @[Misc.scala:215:{29,38}] wire a_mask_eq_48 = a_mask_sub_8_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_48 = a_mask_size_1 & a_mask_eq_48; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_48 = a_mask_sub_8_1_1 \| _a_mask_acc_T_48; // @[Misc.scala:215:{29,38}] wire a_mask_eq_49 = a_mask_sub_8_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_49 = a_mask_size_1 & a_mask_eq_49; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_49 = a_mask_sub_8_1_1 \| _a_mask_acc_T_49; // @[Misc.scala:215:{29,38}] wire a_mask_eq_50 = a_mask_sub_9_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_50 = a_mask_size_1 & a_mask_eq_50; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_50 = a_mask_sub_9_1_1 \| _a_mask_acc_T_50; // @[Misc.scala:215:{29,38}] wire a_mask_eq_51 = a_mask_sub_9_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_51 = a_mask_size_1 & a_mask_eq_51; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_51 = a_mask_sub_9_1_1 \| _a_mask_acc_T_51; // @[Misc.scala:215:{29,38}] wire a_mask_eq_52 = a_mask_sub_10_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_52 = a_mask_size_1 & a_mask_eq_52; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_52 = a_mask_sub_10_1_1 \| _a_mask_acc_T_52; // @[Misc.scala:215:{29,38}] wire a_mask_eq_53 = a_mask_sub_10_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_53 = a_mask_size_1 & a_mask_eq_53; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_53 = a_mask_sub_10_1_1 \| _a_mask_acc_T_53; // @[Misc.scala:215:{29,38}] wire a_mask_eq_54 = a_mask_sub_11_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_54 = a_mask_size_1 & a_mask_eq_54; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_54 = a_mask_sub_11_1_1 \| _a_mask_acc_T_54; // @[Misc.scala:215:{29,38}] wire a_mask_eq_55 = a_mask_sub_11_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_55 = a_mask_size_1 & a_mask_eq_55; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_55 = a_mask_sub_11_1_1 \| _a_mask_acc_T_55; // @[Misc.scala:215:{29,38}] wire a_mask_eq_56 = a_mask_sub_12_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_56 = a_mask_size_1 & a_mask_eq_56; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_56 = a_mask_sub_12_1_1 \| _a_mask_acc_T_56; // @[Misc.scala:215:{29,38}] wire a_mask_eq_57 = a_mask_sub_12_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_57 = a_mask_size_1 & a_mask_eq_57; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_57 = a_mask_sub_12_1_1 \| _a_mask_acc_T_57; // @[Misc.scala:215:{29,38}] wire a_mask_eq_58 = a_mask_sub_13_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_58 = a_mask_size_1 & a_mask_eq_58; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_58 = a_mask_sub_13_1_1 \| _a_mask_acc_T_58; // @[Misc.scala:215:{29,38}] wire a_mask_eq_59 = a_mask_sub_13_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_59 = a_mask_size_1 & a_mask_eq_59; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_59 = a_mask_sub_13_1_1 \| _a_mask_acc_T_59; // @[Misc.scala:215:{29,38}] wire a_mask_eq_60 = a_mask_sub_14_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_60 = a_mask_size_1 & a_mask_eq_60; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_60 = a_mask_sub_14_1_1 \| _a_mask_acc_T_60; // @[Misc.scala:215:{29,38}] wire a_mask_eq_61 = a_mask_sub_14_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_61 = a_mask_size_1 & a_mask_eq_61; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_61 = a_mask_sub_14_1_1 \| _a_mask_acc_T_61; // @[Misc.scala:215:{29,38}] wire a_mask_eq_62 = a_mask_sub_15_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _a_mask_acc_T_62 = a_mask_size_1 & a_mask_eq_62; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_62 = a_mask_sub_15_1_1 \| _a_mask_acc_T_62; // @[Misc.scala:215:{29,38}] wire a_mask_eq_63 = a_mask_sub_15_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _a_mask_acc_T_63 = a_mask_size_1 & a_mask_eq_63; // @[Misc.scala:209:26, :214:27, :215:38] wire a_mask_acc_63 = a_mask_sub_15_1_1 \| _a_mask_acc_T_63; // @[Misc.scala:215:{29,38}] wire [1:0] a_mask_lo_lo_lo_lo_1 = {a_mask_acc_33, a_mask_acc_32}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_lo_lo_lo_hi_1 = {a_mask_acc_35, a_mask_acc_34}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_lo_lo_lo_1 = {a_mask_lo_lo_lo_hi_1, a_mask_lo_lo_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_lo_hi_lo_1 = {a_mask_acc_37, a_mask_acc_36}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_lo_lo_hi_hi_1 = {a_mask_acc_39, a_mask_acc_38}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_lo_lo_hi_1 = {a_mask_lo_lo_hi_hi_1, a_mask_lo_lo_hi_lo_1}; // @[Misc.scala:222:10] wire [7:0] a_mask_lo_lo_1 = {a_mask_lo_lo_hi_1, a_mask_lo_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_hi_lo_lo_1 = {a_mask_acc_41, a_mask_acc_40}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_lo_hi_lo_hi_1 = {a_mask_acc_43, a_mask_acc_42}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_lo_hi_lo_1 = {a_mask_lo_hi_lo_hi_1, a_mask_lo_hi_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] a_mask_lo_hi_hi_lo_1 = {a_mask_acc_45, a_mask_acc_44}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_lo_hi_hi_hi_1 = {a_mask_acc_47, a_mask_acc_46}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_lo_hi_hi_1 = {a_mask_lo_hi_hi_hi_1, a_mask_lo_hi_hi_lo_1}; // @[Misc.scala:222:10] wire [7:0] a_mask_lo_hi_1 = {a_mask_lo_hi_hi_1, a_mask_lo_hi_lo_1}; // @[Misc.scala:222:10] wire [15:0] a_mask_lo_1 = {a_mask_lo_hi_1, a_mask_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_lo_lo_lo_1 = {a_mask_acc_49, a_mask_acc_48}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_hi_lo_lo_hi_1 = {a_mask_acc_51, a_mask_acc_50}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_hi_lo_lo_1 = {a_mask_hi_lo_lo_hi_1, a_mask_hi_lo_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_lo_hi_lo_1 = {a_mask_acc_53, a_mask_acc_52}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_hi_lo_hi_hi_1 = {a_mask_acc_55, a_mask_acc_54}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_hi_lo_hi_1 = {a_mask_hi_lo_hi_hi_1, a_mask_hi_lo_hi_lo_1}; // @[Misc.scala:222:10] wire [7:0] a_mask_hi_lo_1 = {a_mask_hi_lo_hi_1, a_mask_hi_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_hi_lo_lo_1 = {a_mask_acc_57, a_mask_acc_56}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_hi_hi_lo_hi_1 = {a_mask_acc_59, a_mask_acc_58}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_hi_hi_lo_1 = {a_mask_hi_hi_lo_hi_1, a_mask_hi_hi_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] a_mask_hi_hi_hi_lo_1 = {a_mask_acc_61, a_mask_acc_60}; // @[Misc.scala:215:29, :222:10] wire [1:0] a_mask_hi_hi_hi_hi_1 = {a_mask_acc_63, a_mask_acc_62}; // @[Misc.scala:215:29, :222:10] wire [3:0] a_mask_hi_hi_hi_1 = {a_mask_hi_hi_hi_hi_1, a_mask_hi_hi_hi_lo_1}; // @[Misc.scala:222:10] wire [7:0] a_mask_hi_hi_1 = {a_mask_hi_hi_hi_1, a_mask_hi_hi_lo_1}; // @[Misc.scala:222:10] wire [15:0] a_mask_hi_1 = {a_mask_hi_hi_1, a_mask_hi_lo_1}; // @[Misc.scala:222:10] assign _a_mask_T_1 = {a_mask_hi_1, a_mask_lo_1}; // @[Misc.scala:222:10] assign bundle_1_mask = _a_mask_T_1; // @[Misc.scala:222:10] assign bundle_1_data = _T_31[255:0]; // @[Edges.scala:480:17, :489:15] reg [63:0] loginfo_cycles_4; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_8 = {1'h0, loginfo_cycles_4} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_9 = _loginfo_cycles_T_8[63:0]; // @[Util.scala:19:38] wire _current_request_tag_has_response_space_T = _tags_for_issue_Q_io_deq_bits == 5'h0; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_1 = _Queue4_L2RespInternal_io_enq_ready & _current_request_tag_has_response_space_T; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_2 = _tags_for_issue_Q_io_deq_bits == 5'h1; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_3 = _Queue4_L2RespInternal_1_io_enq_ready & _current_request_tag_has_response_space_T_2; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_4 = _tags_for_issue_Q_io_deq_bits == 5'h2; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_5 = _Queue4_L2RespInternal_2_io_enq_ready & _current_request_tag_has_response_space_T_4; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_6 = _tags_for_issue_Q_io_deq_bits == 5'h3; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_7 = _Queue4_L2RespInternal_3_io_enq_ready & _current_request_tag_has_response_space_T_6; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_8 = _tags_for_issue_Q_io_deq_bits == 5'h4; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_9 = _Queue4_L2RespInternal_4_io_enq_ready & _current_request_tag_has_response_space_T_8; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_10 = _tags_for_issue_Q_io_deq_bits == 5'h5; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_11 = _Queue4_L2RespInternal_5_io_enq_ready & _current_request_tag_has_response_space_T_10; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_12 = _tags_for_issue_Q_io_deq_bits == 5'h6; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_13 = _Queue4_L2RespInternal_6_io_enq_ready & _current_request_tag_has_response_space_T_12; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_14 = _tags_for_issue_Q_io_deq_bits == 5'h7; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_15 = _Queue4_L2RespInternal_7_io_enq_ready & _current_request_tag_has_response_space_T_14; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_16 = _tags_for_issue_Q_io_deq_bits == 5'h8; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_17 = _Queue4_L2RespInternal_8_io_enq_ready & _current_request_tag_has_response_space_T_16; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_18 = _tags_for_issue_Q_io_deq_bits == 5'h9; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_19 = _Queue4_L2RespInternal_9_io_enq_ready & _current_request_tag_has_response_space_T_18; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_20 = _tags_for_issue_Q_io_deq_bits == 5'hA; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_21 = _Queue4_L2RespInternal_10_io_enq_ready & _current_request_tag_has_response_space_T_20; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_22 = _tags_for_issue_Q_io_deq_bits == 5'hB; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_23 = _Queue4_L2RespInternal_11_io_enq_ready & _current_request_tag_has_response_space_T_22; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_24 = _tags_for_issue_Q_io_deq_bits == 5'hC; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_25 = _Queue4_L2RespInternal_12_io_enq_ready & _current_request_tag_has_response_space_T_24; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_26 = _tags_for_issue_Q_io_deq_bits == 5'hD; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_27 = _Queue4_L2RespInternal_13_io_enq_ready & _current_request_tag_has_response_space_T_26; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_28 = _tags_for_issue_Q_io_deq_bits == 5'hE; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_29 = _Queue4_L2RespInternal_14_io_enq_ready & _current_request_tag_has_response_space_T_28; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_30 = _tags_for_issue_Q_io_deq_bits == 5'hF; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_31 = _Queue4_L2RespInternal_15_io_enq_ready & _current_request_tag_has_response_space_T_30; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_32 = _tags_for_issue_Q_io_deq_bits == 5'h10; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_33 = _Queue4_L2RespInternal_16_io_enq_ready & _current_request_tag_has_response_space_T_32; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_34 = _tags_for_issue_Q_io_deq_bits == 5'h11; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_35 = _Queue4_L2RespInternal_17_io_enq_ready & _current_request_tag_has_response_space_T_34; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_36 = _tags_for_issue_Q_io_deq_bits == 5'h12; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_37 = _Queue4_L2RespInternal_18_io_enq_ready & _current_request_tag_has_response_space_T_36; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_38 = _tags_for_issue_Q_io_deq_bits == 5'h13; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_39 = _Queue4_L2RespInternal_19_io_enq_ready & _current_request_tag_has_response_space_T_38; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_40 = _tags_for_issue_Q_io_deq_bits == 5'h14; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_41 = _Queue4_L2RespInternal_20_io_enq_ready & _current_request_tag_has_response_space_T_40; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_42 = _tags_for_issue_Q_io_deq_bits == 5'h15; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_43 = _Queue4_L2RespInternal_21_io_enq_ready & _current_request_tag_has_response_space_T_42; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_44 = _tags_for_issue_Q_io_deq_bits == 5'h16; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_45 = _Queue4_L2RespInternal_22_io_enq_ready & _current_request_tag_has_response_space_T_44; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_46 = _tags_for_issue_Q_io_deq_bits == 5'h17; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_47 = _Queue4_L2RespInternal_23_io_enq_ready & _current_request_tag_has_response_space_T_46; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_48 = _tags_for_issue_Q_io_deq_bits == 5'h18; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_49 = _Queue4_L2RespInternal_24_io_enq_ready & _current_request_tag_has_response_space_T_48; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_50 = _tags_for_issue_Q_io_deq_bits == 5'h19; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_51 = _Queue4_L2RespInternal_25_io_enq_ready & _current_request_tag_has_response_space_T_50; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_52 = _tags_for_issue_Q_io_deq_bits == 5'h1A; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_53 = _Queue4_L2RespInternal_26_io_enq_ready & _current_request_tag_has_response_space_T_52; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_54 = _tags_for_issue_Q_io_deq_bits == 5'h1B; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_55 = _Queue4_L2RespInternal_27_io_enq_ready & _current_request_tag_has_response_space_T_54; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_56 = _tags_for_issue_Q_io_deq_bits == 5'h1C; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_57 = _Queue4_L2RespInternal_28_io_enq_ready & _current_request_tag_has_response_space_T_56; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_58 = _tags_for_issue_Q_io_deq_bits == 5'h1D; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_59 = _Queue4_L2RespInternal_29_io_enq_ready & _current_request_tag_has_response_space_T_58; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_60 = _tags_for_issue_Q_io_deq_bits == 5'h1E; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_61 = _Queue4_L2RespInternal_30_io_enq_ready & _current_request_tag_has_response_space_T_60; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_62 = &_tags_for_issue_Q_io_deq_bits; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27] wire _current_request_tag_has_response_space_T_63 = _Queue4_L2RespInternal_31_io_enq_ready & _current_request_tag_has_response_space_T_62; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}] wire _current_request_tag_has_response_space_T_64 = _current_request_tag_has_response_space_T_1 \| _current_request_tag_has_response_space_T_3; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_65 = _current_request_tag_has_response_space_T_64 \| _current_request_tag_has_response_space_T_5; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_66 = _current_request_tag_has_response_space_T_65 \| _current_request_tag_has_response_space_T_7; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_67 = _current_request_tag_has_response_space_T_66 \| _current_request_tag_has_response_space_T_9; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_68 = _current_request_tag_has_response_space_T_67 \| _current_request_tag_has_response_space_T_11; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_69 = _current_request_tag_has_response_space_T_68 \| _current_request_tag_has_response_space_T_13; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_70 = _current_request_tag_has_response_space_T_69 \| _current_request_tag_has_response_space_T_15; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_71 = _current_request_tag_has_response_space_T_70 \| _current_request_tag_has_response_space_T_17; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_72 = _current_request_tag_has_response_space_T_71 \| _current_request_tag_has_response_space_T_19; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_73 = _current_request_tag_has_response_space_T_72 \| _current_request_tag_has_response_space_T_21; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_74 = _current_request_tag_has_response_space_T_73 \| _current_request_tag_has_response_space_T_23; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_75 = _current_request_tag_has_response_space_T_74 \| _current_request_tag_has_response_space_T_25; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_76 = _current_request_tag_has_response_space_T_75 \| _current_request_tag_has_response_space_T_27; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_77 = _current_request_tag_has_response_space_T_76 \| _current_request_tag_has_response_space_T_29; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_78 = _current_request_tag_has_response_space_T_77 \| _current_request_tag_has_response_space_T_31; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_79 = _current_request_tag_has_response_space_T_78 \| _current_request_tag_has_response_space_T_33; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_80 = _current_request_tag_has_response_space_T_79 \| _current_request_tag_has_response_space_T_35; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_81 = _current_request_tag_has_response_space_T_80 \| _current_request_tag_has_response_space_T_37; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_82 = _current_request_tag_has_response_space_T_81 \| _current_request_tag_has_response_space_T_39; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_83 = _current_request_tag_has_response_space_T_82 \| _current_request_tag_has_response_space_T_41; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_84 = _current_request_tag_has_response_space_T_83 \| _current_request_tag_has_response_space_T_43; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_85 = _current_request_tag_has_response_space_T_84 \| _current_request_tag_has_response_space_T_45; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_86 = _current_request_tag_has_response_space_T_85 \| _current_request_tag_has_response_space_T_47; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_87 = _current_request_tag_has_response_space_T_86 \| _current_request_tag_has_response_space_T_49; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_88 = _current_request_tag_has_response_space_T_87 \| _current_request_tag_has_response_space_T_51; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_89 = _current_request_tag_has_response_space_T_88 \| _current_request_tag_has_response_space_T_53; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_90 = _current_request_tag_has_response_space_T_89 \| _current_request_tag_has_response_space_T_55; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_91 = _current_request_tag_has_response_space_T_90 \| _current_request_tag_has_response_space_T_57; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_92 = _current_request_tag_has_response_space_T_91 \| _current_request_tag_has_response_space_T_59; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire _current_request_tag_has_response_space_T_93 = _current_request_tag_has_response_space_T_92 \| _current_request_tag_has_response_space_T_61; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire current_request_tag_has_response_space = _current_request_tag_has_response_space_T_93 \| _current_request_tag_has_response_space_T_63; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15] wire [63:0] _outstanding_req_addr_io_enq_bits_addrindex_T = {59'h0, request_input_bits_addr[4:0]}; // @[L2MemHelperLatencyInjection.scala:44:27, :200:73] wire _request_latency_injection_q_io_enq_valid_T = request_input_valid & tlb_ready; // @[Misc.scala:26:53] wire _request_latency_injection_q_io_enq_valid_T_1 = _request_latency_injection_q_io_enq_valid_T & _outstanding_req_addr_io_enq_ready; // @[Misc.scala:26:53] wire _request_latency_injection_q_io_enq_valid_T_2 = _request_latency_injection_q_io_enq_valid_T_1 & free_outstanding_op_slots; // @[Misc.scala:26:53] wire _request_latency_injection_q_io_enq_valid_T_3 = _request_latency_injection_q_io_enq_valid_T_2 & _tags_for_issue_Q_io_deq_valid; // @[Misc.scala:26:53] wire _request_latency_injection_q_io_enq_valid_T_4 = _request_latency_injection_q_io_enq_valid_T_3 & current_request_tag_has_response_space; // @[Misc.scala:26:53] wire _request_input_ready_T = _request_latency_injection_q_io_enq_ready & tlb_ready; // @[Misc.scala:26:53] wire _request_input_ready_T_1 = _request_input_ready_T & _outstanding_req_addr_io_enq_ready; // @[Misc.scala:26:53] wire _request_input_ready_T_2 = _request_input_ready_T_1 & free_outstanding_op_slots; // @[Misc.scala:26:53] wire _request_input_ready_T_3 = _request_input_ready_T_2 & _tags_for_issue_Q_io_deq_valid; // @[Misc.scala:26:53] assign _request_input_ready_T_4 = _request_input_ready_T_3 & current_request_tag_has_response_space; // @[Misc.scala:26:53] assign request_input_ready = _request_input_ready_T_4; // @[Misc.scala:26:53] wire _T_45 = request_input_valid & _request_latency_injection_q_io_enq_ready; // @[Misc.scala:26:53] wire _outstanding_req_addr_io_enq_valid_T; // @[Misc.scala:26:53] assign _outstanding_req_addr_io_enq_valid_T = _T_45; // @[Misc.scala:26:53] wire _tags_for_issue_Q_io_deq_ready_T; // @[Misc.scala:26:53] assign _tags_for_issue_Q_io_deq_ready_T = _T_45; // @[Misc.scala:26:53] wire _outstanding_req_addr_io_enq_valid_T_1 = _outstanding_req_addr_io_enq_valid_T & tlb_ready; // @[Misc.scala:26:53] wire _outstanding_req_addr_io_enq_valid_T_2 = _outstanding_req_addr_io_enq_valid_T_1 & free_outstanding_op_slots; // @[Misc.scala:26:53] wire _outstanding_req_addr_io_enq_valid_T_3 = _outstanding_req_addr_io_enq_valid_T_2 & _tags_for_issue_Q_io_deq_valid; // @[Misc.scala:26:53] wire _outstanding_req_addr_io_enq_valid_T_4 = _outstanding_req_addr_io_enq_valid_T_3 & current_request_tag_has_response_space; // @[Misc.scala:26:53] wire _tags_for_issue_Q_io_deq_ready_T_1 = _tags_for_issue_Q_io_deq_ready_T & tlb_ready; // @[Misc.scala:26:53] wire _tags_for_issue_Q_io_deq_ready_T_2 = _tags_for_issue_Q_io_deq_ready_T_1 & _outstanding_req_addr_io_enq_ready; // @[Misc.scala:26:53] wire _tags_for_issue_Q_io_deq_ready_T_3 = _tags_for_issue_Q_io_deq_ready_T_2 & free_outstanding_op_slots; // @[Misc.scala:26:53] wire _tags_for_issue_Q_io_deq_ready_T_4 = _tags_for_issue_Q_io_deq_ready_T_3 & current_request_tag_has_response_space; // @[Misc.scala:26:53] reg [63:0] loginfo_cycles_5; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_10 = {1'h0, loginfo_cycles_5} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_11 = _loginfo_cycles_T_10[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_6; // @[Util.scala:26:33] wire [64:0] _loginfo_cycles_T_12 = {1'h0, loginfo_cycles_6} + 65'h1; // @[Util.scala:26:33, :27:38] wire [63:0] _loginfo_cycles_T_13 = _loginfo_cycles_T_12[63:0]; // @[Util.scala:27:38] wire _printf_T_1 = ~_printf_T; // @[annotations.scala:102:49] wire _printf_T_3 = ~_printf_T_2; // @[annotations.scala:102:49] reg [63:0] loginfo_cycles_7; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_14 = {1'h0, loginfo_cycles_7} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_15 = _loginfo_cycles_T_14[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_8; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_16 = {1'h0, loginfo_cycles_8} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_17 = _loginfo_cycles_T_16[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_9; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_18 = {1'h0, loginfo_cycles_9} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_19 = _loginfo_cycles_T_18[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_10; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_20 = {1'h0, loginfo_cycles_10} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_21 = _loginfo_cycles_T_20[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_11; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_22 = {1'h0, loginfo_cycles_11} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_23 = _loginfo_cycles_T_22[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_12; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_24 = {1'h0, loginfo_cycles_12} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_25 = _loginfo_cycles_T_24[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_13; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_26 = {1'h0, loginfo_cycles_13} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_27 = _loginfo_cycles_T_26[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_14; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_28 = {1'h0, loginfo_cycles_14} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_29 = _loginfo_cycles_T_28[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_15; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_30 = {1'h0, loginfo_cycles_15} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_31 = _loginfo_cycles_T_30[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_16; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_32 = {1'h0, loginfo_cycles_16} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_33 = _loginfo_cycles_T_32[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_17; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_34 = {1'h0, loginfo_cycles_17} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_35 = _loginfo_cycles_T_34[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_18; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_36 = {1'h0, loginfo_cycles_18} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_37 = _loginfo_cycles_T_36[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_19; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_38 = {1'h0, loginfo_cycles_19} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_39 = _loginfo_cycles_T_38[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_20; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_40 = {1'h0, loginfo_cycles_20} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_41 = _loginfo_cycles_T_40[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_21; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_42 = {1'h0, loginfo_cycles_21} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_43 = _loginfo_cycles_T_42[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_22; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_44 = {1'h0, loginfo_cycles_22} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_45 = _loginfo_cycles_T_44[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_23; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_46 = {1'h0, loginfo_cycles_23} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_47 = _loginfo_cycles_T_46[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_24; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_48 = {1'h0, loginfo_cycles_24} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_49 = _loginfo_cycles_T_48[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_25; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_50 = {1'h0, loginfo_cycles_25} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_51 = _loginfo_cycles_T_50[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_26; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_52 = {1'h0, loginfo_cycles_26} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_53 = _loginfo_cycles_T_52[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_27; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_54 = {1'h0, loginfo_cycles_27} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_55 = _loginfo_cycles_T_54[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_28; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_56 = {1'h0, loginfo_cycles_28} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_57 = _loginfo_cycles_T_56[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_29; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_58 = {1'h0, loginfo_cycles_29} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_59 = _loginfo_cycles_T_58[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_30; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_60 = {1'h0, loginfo_cycles_30} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_61 = _loginfo_cycles_T_60[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_31; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_62 = {1'h0, loginfo_cycles_31} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_63 = _loginfo_cycles_T_62[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_32; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_64 = {1'h0, loginfo_cycles_32} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_65 = _loginfo_cycles_T_64[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_33; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_66 = {1'h0, loginfo_cycles_33} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_67 = _loginfo_cycles_T_66[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_34; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_68 = {1'h0, loginfo_cycles_34} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_69 = _loginfo_cycles_T_68[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_35; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_70 = {1'h0, loginfo_cycles_35} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_71 = _loginfo_cycles_T_70[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_36; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_72 = {1'h0, loginfo_cycles_36} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_73 = _loginfo_cycles_T_72[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_37; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_74 = {1'h0, loginfo_cycles_37} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_75 = _loginfo_cycles_T_74[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_38; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_76 = {1'h0, loginfo_cycles_38} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_77 = _loginfo_cycles_T_76[63:0]; // @[Util.scala:19:38] wire _selectQready_T = _response_latency_injection_q_io_deq_bits_source == 5'h0; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_1 = _Queue4_L2RespInternal_io_enq_ready & _selectQready_T; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_2 = _response_latency_injection_q_io_deq_bits_source == 5'h1; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_3 = _Queue4_L2RespInternal_1_io_enq_ready & _selectQready_T_2; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_4 = _response_latency_injection_q_io_deq_bits_source == 5'h2; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_5 = _Queue4_L2RespInternal_2_io_enq_ready & _selectQready_T_4; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_6 = _response_latency_injection_q_io_deq_bits_source == 5'h3; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_7 = _Queue4_L2RespInternal_3_io_enq_ready & _selectQready_T_6; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_8 = _response_latency_injection_q_io_deq_bits_source == 5'h4; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_9 = _Queue4_L2RespInternal_4_io_enq_ready & _selectQready_T_8; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_10 = _response_latency_injection_q_io_deq_bits_source == 5'h5; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_11 = _Queue4_L2RespInternal_5_io_enq_ready & _selectQready_T_10; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_12 = _response_latency_injection_q_io_deq_bits_source == 5'h6; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_13 = _Queue4_L2RespInternal_6_io_enq_ready & _selectQready_T_12; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_14 = _response_latency_injection_q_io_deq_bits_source == 5'h7; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_15 = _Queue4_L2RespInternal_7_io_enq_ready & _selectQready_T_14; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_16 = _response_latency_injection_q_io_deq_bits_source == 5'h8; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_17 = _Queue4_L2RespInternal_8_io_enq_ready & _selectQready_T_16; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_18 = _response_latency_injection_q_io_deq_bits_source == 5'h9; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_19 = _Queue4_L2RespInternal_9_io_enq_ready & _selectQready_T_18; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_20 = _response_latency_injection_q_io_deq_bits_source == 5'hA; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_21 = _Queue4_L2RespInternal_10_io_enq_ready & _selectQready_T_20; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_22 = _response_latency_injection_q_io_deq_bits_source == 5'hB; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_23 = _Queue4_L2RespInternal_11_io_enq_ready & _selectQready_T_22; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_24 = _response_latency_injection_q_io_deq_bits_source == 5'hC; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_25 = _Queue4_L2RespInternal_12_io_enq_ready & _selectQready_T_24; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_26 = _response_latency_injection_q_io_deq_bits_source == 5'hD; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_27 = _Queue4_L2RespInternal_13_io_enq_ready & _selectQready_T_26; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_28 = _response_latency_injection_q_io_deq_bits_source == 5'hE; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_29 = _Queue4_L2RespInternal_14_io_enq_ready & _selectQready_T_28; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_30 = _response_latency_injection_q_io_deq_bits_source == 5'hF; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_31 = _Queue4_L2RespInternal_15_io_enq_ready & _selectQready_T_30; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_32 = _response_latency_injection_q_io_deq_bits_source == 5'h10; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_33 = _Queue4_L2RespInternal_16_io_enq_ready & _selectQready_T_32; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_34 = _response_latency_injection_q_io_deq_bits_source == 5'h11; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_35 = _Queue4_L2RespInternal_17_io_enq_ready & _selectQready_T_34; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_36 = _response_latency_injection_q_io_deq_bits_source == 5'h12; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_37 = _Queue4_L2RespInternal_18_io_enq_ready & _selectQready_T_36; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_38 = _response_latency_injection_q_io_deq_bits_source == 5'h13; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_39 = _Queue4_L2RespInternal_19_io_enq_ready & _selectQready_T_38; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_40 = _response_latency_injection_q_io_deq_bits_source == 5'h14; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_41 = _Queue4_L2RespInternal_20_io_enq_ready & _selectQready_T_40; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_42 = _response_latency_injection_q_io_deq_bits_source == 5'h15; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_43 = _Queue4_L2RespInternal_21_io_enq_ready & _selectQready_T_42; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_44 = _response_latency_injection_q_io_deq_bits_source == 5'h16; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_45 = _Queue4_L2RespInternal_22_io_enq_ready & _selectQready_T_44; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_46 = _response_latency_injection_q_io_deq_bits_source == 5'h17; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_47 = _Queue4_L2RespInternal_23_io_enq_ready & _selectQready_T_46; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_48 = _response_latency_injection_q_io_deq_bits_source == 5'h18; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_49 = _Queue4_L2RespInternal_24_io_enq_ready & _selectQready_T_48; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_50 = _response_latency_injection_q_io_deq_bits_source == 5'h19; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_51 = _Queue4_L2RespInternal_25_io_enq_ready & _selectQready_T_50; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_52 = _response_latency_injection_q_io_deq_bits_source == 5'h1A; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_53 = _Queue4_L2RespInternal_26_io_enq_ready & _selectQready_T_52; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_54 = _response_latency_injection_q_io_deq_bits_source == 5'h1B; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_55 = _Queue4_L2RespInternal_27_io_enq_ready & _selectQready_T_54; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_56 = _response_latency_injection_q_io_deq_bits_source == 5'h1C; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_57 = _Queue4_L2RespInternal_28_io_enq_ready & _selectQready_T_56; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_58 = _response_latency_injection_q_io_deq_bits_source == 5'h1D; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_59 = _Queue4_L2RespInternal_29_io_enq_ready & _selectQready_T_58; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_60 = _response_latency_injection_q_io_deq_bits_source == 5'h1E; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_61 = _Queue4_L2RespInternal_30_io_enq_ready & _selectQready_T_60; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_62 = &_response_latency_injection_q_io_deq_bits_source; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27] wire _selectQready_T_63 = _Queue4_L2RespInternal_31_io_enq_ready & _selectQready_T_62; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}] wire _selectQready_T_64 = _selectQready_T_1 \| _selectQready_T_3; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_65 = _selectQready_T_64 \| _selectQready_T_5; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_66 = _selectQready_T_65 \| _selectQready_T_7; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_67 = _selectQready_T_66 \| _selectQready_T_9; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_68 = _selectQready_T_67 \| _selectQready_T_11; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_69 = _selectQready_T_68 \| _selectQready_T_13; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_70 = _selectQready_T_69 \| _selectQready_T_15; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_71 = _selectQready_T_70 \| _selectQready_T_17; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_72 = _selectQready_T_71 \| _selectQready_T_19; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_73 = _selectQready_T_72 \| _selectQready_T_21; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_74 = _selectQready_T_73 \| _selectQready_T_23; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_75 = _selectQready_T_74 \| _selectQready_T_25; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_76 = _selectQready_T_75 \| _selectQready_T_27; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_77 = _selectQready_T_76 \| _selectQready_T_29; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_78 = _selectQready_T_77 \| _selectQready_T_31; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_79 = _selectQready_T_78 \| _selectQready_T_33; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_80 = _selectQready_T_79 \| _selectQready_T_35; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_81 = _selectQready_T_80 \| _selectQready_T_37; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_82 = _selectQready_T_81 \| _selectQready_T_39; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_83 = _selectQready_T_82 \| _selectQready_T_41; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_84 = _selectQready_T_83 \| _selectQready_T_43; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_85 = _selectQready_T_84 \| _selectQready_T_45; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_86 = _selectQready_T_85 \| _selectQready_T_47; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_87 = _selectQready_T_86 \| _selectQready_T_49; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_88 = _selectQready_T_87 \| _selectQready_T_51; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_89 = _selectQready_T_88 \| _selectQready_T_53; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_90 = _selectQready_T_89 \| _selectQready_T_55; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_91 = _selectQready_T_90 \| _selectQready_T_57; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_92 = _selectQready_T_91 \| _selectQready_T_59; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _selectQready_T_93 = _selectQready_T_92 \| _selectQready_T_61; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire selectQready = _selectQready_T_93 \| _selectQready_T_63; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15] wire _T_377 = selectQready & _response_latency_injection_q_io_deq_valid; // @[Misc.scala:26:53] wire tags_for_issue_Q_io_enq_valid = _T_377 \| _T_4; // @[Misc.scala:26:53] wire [4:0] tags_for_issue_Q_io_enq_bits = _T_377 ? _response_latency_injection_q_io_deq_bits_source : tags_init_reg[4:0]; // @[Misc.scala:26:53] reg [63:0] loginfo_cycles_39; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_78 = {1'h0, loginfo_cycles_39} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_79 = _loginfo_cycles_T_78[63:0]; // @[Util.scala:19:38] wire _response_latency_injection_q_io_deq_ready_T = selectQready & _tags_for_issue_Q_io_enq_ready; // @[Misc.scala:26:53] wire _T_476 = _response_latency_injection_q_io_deq_valid & _tags_for_issue_Q_io_enq_ready; // @[Misc.scala:26:53] wire _T_480 = _outstanding_req_addr_io_deq_bits_tag == 5'h0; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T = _T_480; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q = _T_480; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_1 = _Queue4_L2RespInternal_io_deq_valid & _queueValid_T; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_483 = _outstanding_req_addr_io_deq_bits_tag == 5'h1; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_2; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_2 = _T_483; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_1; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_1 = _T_483; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_3 = _Queue4_L2RespInternal_1_io_deq_valid & _queueValid_T_2; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_486 = _outstanding_req_addr_io_deq_bits_tag == 5'h2; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_4; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_4 = _T_486; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_2; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_2 = _T_486; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_5 = _Queue4_L2RespInternal_2_io_deq_valid & _queueValid_T_4; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_489 = _outstanding_req_addr_io_deq_bits_tag == 5'h3; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_6; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_6 = _T_489; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_3; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_3 = _T_489; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_7 = _Queue4_L2RespInternal_3_io_deq_valid & _queueValid_T_6; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_492 = _outstanding_req_addr_io_deq_bits_tag == 5'h4; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_8; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_8 = _T_492; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_4; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_4 = _T_492; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_9 = _Queue4_L2RespInternal_4_io_deq_valid & _queueValid_T_8; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_495 = _outstanding_req_addr_io_deq_bits_tag == 5'h5; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_10; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_10 = _T_495; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_5; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_5 = _T_495; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_11 = _Queue4_L2RespInternal_5_io_deq_valid & _queueValid_T_10; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_498 = _outstanding_req_addr_io_deq_bits_tag == 5'h6; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_12; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_12 = _T_498; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_6; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_6 = _T_498; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_13 = _Queue4_L2RespInternal_6_io_deq_valid & _queueValid_T_12; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_501 = _outstanding_req_addr_io_deq_bits_tag == 5'h7; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_14; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_14 = _T_501; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_7; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_7 = _T_501; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_15 = _Queue4_L2RespInternal_7_io_deq_valid & _queueValid_T_14; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_504 = _outstanding_req_addr_io_deq_bits_tag == 5'h8; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_16; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_16 = _T_504; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_8; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_8 = _T_504; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_17 = _Queue4_L2RespInternal_8_io_deq_valid & _queueValid_T_16; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_507 = _outstanding_req_addr_io_deq_bits_tag == 5'h9; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_18; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_18 = _T_507; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_9; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_9 = _T_507; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_19 = _Queue4_L2RespInternal_9_io_deq_valid & _queueValid_T_18; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_510 = _outstanding_req_addr_io_deq_bits_tag == 5'hA; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_20; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_20 = _T_510; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_10; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_10 = _T_510; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_21 = _Queue4_L2RespInternal_10_io_deq_valid & _queueValid_T_20; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_513 = _outstanding_req_addr_io_deq_bits_tag == 5'hB; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_22; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_22 = _T_513; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_11; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_11 = _T_513; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_23 = _Queue4_L2RespInternal_11_io_deq_valid & _queueValid_T_22; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_516 = _outstanding_req_addr_io_deq_bits_tag == 5'hC; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_24; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_24 = _T_516; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_12; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_12 = _T_516; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_25 = _Queue4_L2RespInternal_12_io_deq_valid & _queueValid_T_24; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_519 = _outstanding_req_addr_io_deq_bits_tag == 5'hD; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_26; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_26 = _T_519; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_13; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_13 = _T_519; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_27 = _Queue4_L2RespInternal_13_io_deq_valid & _queueValid_T_26; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_522 = _outstanding_req_addr_io_deq_bits_tag == 5'hE; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_28; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_28 = _T_522; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_14; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_14 = _T_522; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_29 = _Queue4_L2RespInternal_14_io_deq_valid & _queueValid_T_28; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_525 = _outstanding_req_addr_io_deq_bits_tag == 5'hF; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_30; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_30 = _T_525; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_15; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_15 = _T_525; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_31 = _Queue4_L2RespInternal_15_io_deq_valid & _queueValid_T_30; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_528 = _outstanding_req_addr_io_deq_bits_tag == 5'h10; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_32; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_32 = _T_528; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_16; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_16 = _T_528; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_33 = _Queue4_L2RespInternal_16_io_deq_valid & _queueValid_T_32; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_531 = _outstanding_req_addr_io_deq_bits_tag == 5'h11; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_34; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_34 = _T_531; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_17; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_17 = _T_531; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_35 = _Queue4_L2RespInternal_17_io_deq_valid & _queueValid_T_34; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_534 = _outstanding_req_addr_io_deq_bits_tag == 5'h12; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_36; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_36 = _T_534; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_18; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_18 = _T_534; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_37 = _Queue4_L2RespInternal_18_io_deq_valid & _queueValid_T_36; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_537 = _outstanding_req_addr_io_deq_bits_tag == 5'h13; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_38; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_38 = _T_537; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_19; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_19 = _T_537; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_39 = _Queue4_L2RespInternal_19_io_deq_valid & _queueValid_T_38; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_540 = _outstanding_req_addr_io_deq_bits_tag == 5'h14; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_40; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_40 = _T_540; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_20; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_20 = _T_540; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_41 = _Queue4_L2RespInternal_20_io_deq_valid & _queueValid_T_40; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_543 = _outstanding_req_addr_io_deq_bits_tag == 5'h15; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_42; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_42 = _T_543; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_21; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_21 = _T_543; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_43 = _Queue4_L2RespInternal_21_io_deq_valid & _queueValid_T_42; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_546 = _outstanding_req_addr_io_deq_bits_tag == 5'h16; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_44; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_44 = _T_546; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_22; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_22 = _T_546; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_45 = _Queue4_L2RespInternal_22_io_deq_valid & _queueValid_T_44; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_549 = _outstanding_req_addr_io_deq_bits_tag == 5'h17; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_46; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_46 = _T_549; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_23; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_23 = _T_549; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_47 = _Queue4_L2RespInternal_23_io_deq_valid & _queueValid_T_46; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_552 = _outstanding_req_addr_io_deq_bits_tag == 5'h18; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_48; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_48 = _T_552; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_24; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_24 = _T_552; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_49 = _Queue4_L2RespInternal_24_io_deq_valid & _queueValid_T_48; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_555 = _outstanding_req_addr_io_deq_bits_tag == 5'h19; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_50; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_50 = _T_555; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_25; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_25 = _T_555; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_51 = _Queue4_L2RespInternal_25_io_deq_valid & _queueValid_T_50; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_558 = _outstanding_req_addr_io_deq_bits_tag == 5'h1A; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_52; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_52 = _T_558; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_26; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_26 = _T_558; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_53 = _Queue4_L2RespInternal_26_io_deq_valid & _queueValid_T_52; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_561 = _outstanding_req_addr_io_deq_bits_tag == 5'h1B; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_54; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_54 = _T_561; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_27; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_27 = _T_561; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_55 = _Queue4_L2RespInternal_27_io_deq_valid & _queueValid_T_54; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_564 = _outstanding_req_addr_io_deq_bits_tag == 5'h1C; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_56; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_56 = _T_564; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_28; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_28 = _T_564; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_57 = _Queue4_L2RespInternal_28_io_deq_valid & _queueValid_T_56; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_567 = _outstanding_req_addr_io_deq_bits_tag == 5'h1D; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_58; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_58 = _T_567; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_29; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_29 = _T_567; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_59 = _Queue4_L2RespInternal_29_io_deq_valid & _queueValid_T_58; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _T_570 = _outstanding_req_addr_io_deq_bits_tag == 5'h1E; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_60; // @[L2MemHelperLatencyInjection.scala:287:27] assign _queueValid_T_60 = _T_570; // @[L2MemHelperLatencyInjection.scala:287:27] wire resultdata_is_current_q_30; // @[L2MemHelperLatencyInjection.scala:299:31] assign resultdata_is_current_q_30 = _T_570; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31] wire _queueValid_T_61 = _Queue4_L2RespInternal_30_io_deq_valid & _queueValid_T_60; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _queueValid_T_62 = &_outstanding_req_addr_io_deq_bits_tag; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27] wire _queueValid_T_63 = _Queue4_L2RespInternal_31_io_deq_valid & _queueValid_T_62; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}] wire _queueValid_T_64 = _queueValid_T_1 \| _queueValid_T_3; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_65 = _queueValid_T_64 \| _queueValid_T_5; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_66 = _queueValid_T_65 \| _queueValid_T_7; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_67 = _queueValid_T_66 \| _queueValid_T_9; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_68 = _queueValid_T_67 \| _queueValid_T_11; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_69 = _queueValid_T_68 \| _queueValid_T_13; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_70 = _queueValid_T_69 \| _queueValid_T_15; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_71 = _queueValid_T_70 \| _queueValid_T_17; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_72 = _queueValid_T_71 \| _queueValid_T_19; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_73 = _queueValid_T_72 \| _queueValid_T_21; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_74 = _queueValid_T_73 \| _queueValid_T_23; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_75 = _queueValid_T_74 \| _queueValid_T_25; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_76 = _queueValid_T_75 \| _queueValid_T_27; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_77 = _queueValid_T_76 \| _queueValid_T_29; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_78 = _queueValid_T_77 \| _queueValid_T_31; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_79 = _queueValid_T_78 \| _queueValid_T_33; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_80 = _queueValid_T_79 \| _queueValid_T_35; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_81 = _queueValid_T_80 \| _queueValid_T_37; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_82 = _queueValid_T_81 \| _queueValid_T_39; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_83 = _queueValid_T_82 \| _queueValid_T_41; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_84 = _queueValid_T_83 \| _queueValid_T_43; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_85 = _queueValid_T_84 \| _queueValid_T_45; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_86 = _queueValid_T_85 \| _queueValid_T_47; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_87 = _queueValid_T_86 \| _queueValid_T_49; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_88 = _queueValid_T_87 \| _queueValid_T_51; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_89 = _queueValid_T_88 \| _queueValid_T_53; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_90 = _queueValid_T_89 \| _queueValid_T_55; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_91 = _queueValid_T_90 \| _queueValid_T_57; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_92 = _queueValid_T_91 \| _queueValid_T_59; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire _queueValid_T_93 = _queueValid_T_92 \| _queueValid_T_61; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire queueValid = _queueValid_T_93 \| _queueValid_T_63; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15] wire [255:0] resultdata_data; // @[L2MemHelperLatencyInjection.scala:300:20] wire [7:0] _GEN_12 = {_outstanding_req_addr_io_deq_bits_addrindex, 3'h0}; // @[L2MemHelperLatencyInjection.scala:91:36, :302:78] wire [7:0] _resultdata_data_T; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_2; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_2 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_4; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_4 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_6; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_6 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_8; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_8 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_10; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_10 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_12; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_12 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_14; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_14 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_16; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_16 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_18; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_18 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_20; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_20 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_22; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_22 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_24; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_24 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_26; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_26 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_28; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_28 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_30; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_30 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_32; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_32 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_34; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_34 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_36; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_36 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_38; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_38 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_40; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_40 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_42; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_42 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_44; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_44 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_46; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_46 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_48; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_48 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_50; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_50 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_52; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_52 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_54; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_54 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_56; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_56 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_58; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_58 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_60; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_60 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [7:0] _resultdata_data_T_62; // @[L2MemHelperLatencyInjection.scala:302:78] assign _resultdata_data_T_62 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78] wire [255:0] _resultdata_data_T_1 = _Queue4_L2RespInternal_io_deq_bits_data >> _resultdata_data_T; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data = resultdata_is_current_q ? _resultdata_data_T_1 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_1; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_3 = _Queue4_L2RespInternal_1_io_deq_bits_data >> _resultdata_data_T_2; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_1 = resultdata_is_current_q_1 ? _resultdata_data_T_3 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_2; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_5 = _Queue4_L2RespInternal_2_io_deq_bits_data >> _resultdata_data_T_4; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_2 = resultdata_is_current_q_2 ? _resultdata_data_T_5 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_3; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_7 = _Queue4_L2RespInternal_3_io_deq_bits_data >> _resultdata_data_T_6; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_3 = resultdata_is_current_q_3 ? _resultdata_data_T_7 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_4; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_9 = _Queue4_L2RespInternal_4_io_deq_bits_data >> _resultdata_data_T_8; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_4 = resultdata_is_current_q_4 ? _resultdata_data_T_9 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_5; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_11 = _Queue4_L2RespInternal_5_io_deq_bits_data >> _resultdata_data_T_10; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_5 = resultdata_is_current_q_5 ? _resultdata_data_T_11 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_6; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_13 = _Queue4_L2RespInternal_6_io_deq_bits_data >> _resultdata_data_T_12; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_6 = resultdata_is_current_q_6 ? _resultdata_data_T_13 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_7; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_15 = _Queue4_L2RespInternal_7_io_deq_bits_data >> _resultdata_data_T_14; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_7 = resultdata_is_current_q_7 ? _resultdata_data_T_15 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_8; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_17 = _Queue4_L2RespInternal_8_io_deq_bits_data >> _resultdata_data_T_16; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_8 = resultdata_is_current_q_8 ? _resultdata_data_T_17 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_9; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_19 = _Queue4_L2RespInternal_9_io_deq_bits_data >> _resultdata_data_T_18; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_9 = resultdata_is_current_q_9 ? _resultdata_data_T_19 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_10; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_21 = _Queue4_L2RespInternal_10_io_deq_bits_data >> _resultdata_data_T_20; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_10 = resultdata_is_current_q_10 ? _resultdata_data_T_21 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_11; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_23 = _Queue4_L2RespInternal_11_io_deq_bits_data >> _resultdata_data_T_22; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_11 = resultdata_is_current_q_11 ? _resultdata_data_T_23 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_12; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_25 = _Queue4_L2RespInternal_12_io_deq_bits_data >> _resultdata_data_T_24; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_12 = resultdata_is_current_q_12 ? _resultdata_data_T_25 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_13; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_27 = _Queue4_L2RespInternal_13_io_deq_bits_data >> _resultdata_data_T_26; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_13 = resultdata_is_current_q_13 ? _resultdata_data_T_27 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_14; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_29 = _Queue4_L2RespInternal_14_io_deq_bits_data >> _resultdata_data_T_28; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_14 = resultdata_is_current_q_14 ? _resultdata_data_T_29 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_15; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_31 = _Queue4_L2RespInternal_15_io_deq_bits_data >> _resultdata_data_T_30; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_15 = resultdata_is_current_q_15 ? _resultdata_data_T_31 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_16; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_33 = _Queue4_L2RespInternal_16_io_deq_bits_data >> _resultdata_data_T_32; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_16 = resultdata_is_current_q_16 ? _resultdata_data_T_33 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_17; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_35 = _Queue4_L2RespInternal_17_io_deq_bits_data >> _resultdata_data_T_34; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_17 = resultdata_is_current_q_17 ? _resultdata_data_T_35 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_18; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_37 = _Queue4_L2RespInternal_18_io_deq_bits_data >> _resultdata_data_T_36; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_18 = resultdata_is_current_q_18 ? _resultdata_data_T_37 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_19; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_39 = _Queue4_L2RespInternal_19_io_deq_bits_data >> _resultdata_data_T_38; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_19 = resultdata_is_current_q_19 ? _resultdata_data_T_39 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_20; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_41 = _Queue4_L2RespInternal_20_io_deq_bits_data >> _resultdata_data_T_40; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_20 = resultdata_is_current_q_20 ? _resultdata_data_T_41 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_21; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_43 = _Queue4_L2RespInternal_21_io_deq_bits_data >> _resultdata_data_T_42; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_21 = resultdata_is_current_q_21 ? _resultdata_data_T_43 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_22; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_45 = _Queue4_L2RespInternal_22_io_deq_bits_data >> _resultdata_data_T_44; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_22 = resultdata_is_current_q_22 ? _resultdata_data_T_45 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_23; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_47 = _Queue4_L2RespInternal_23_io_deq_bits_data >> _resultdata_data_T_46; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_23 = resultdata_is_current_q_23 ? _resultdata_data_T_47 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_24; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_49 = _Queue4_L2RespInternal_24_io_deq_bits_data >> _resultdata_data_T_48; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_24 = resultdata_is_current_q_24 ? _resultdata_data_T_49 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_25; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_51 = _Queue4_L2RespInternal_25_io_deq_bits_data >> _resultdata_data_T_50; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_25 = resultdata_is_current_q_25 ? _resultdata_data_T_51 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_26; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_53 = _Queue4_L2RespInternal_26_io_deq_bits_data >> _resultdata_data_T_52; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_26 = resultdata_is_current_q_26 ? _resultdata_data_T_53 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_27; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_55 = _Queue4_L2RespInternal_27_io_deq_bits_data >> _resultdata_data_T_54; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_27 = resultdata_is_current_q_27 ? _resultdata_data_T_55 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_28; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_57 = _Queue4_L2RespInternal_28_io_deq_bits_data >> _resultdata_data_T_56; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_28 = resultdata_is_current_q_28 ? _resultdata_data_T_57 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_29; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_59 = _Queue4_L2RespInternal_29_io_deq_bits_data >> _resultdata_data_T_58; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_29 = resultdata_is_current_q_29 ? _resultdata_data_T_59 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] resultdata_data_30; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_61 = _Queue4_L2RespInternal_30_io_deq_bits_data >> _resultdata_data_T_60; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_30 = resultdata_is_current_q_30 ? _resultdata_data_T_61 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire resultdata_is_current_q_31 = &_outstanding_req_addr_io_deq_bits_tag; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27, :299:31] wire [255:0] resultdata_data_31; // @[L2MemHelperLatencyInjection.scala:300:20] wire [255:0] _resultdata_data_T_63 = _Queue4_L2RespInternal_31_io_deq_bits_data >> _resultdata_data_T_62; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}] assign resultdata_data_31 = resultdata_is_current_q_31 ? _resultdata_data_T_63 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12] wire [255:0] _resultdata_T = resultdata_data \| resultdata_data_1; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_1 = _resultdata_T \| resultdata_data_2; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_2 = _resultdata_T_1 \| resultdata_data_3; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_3 = _resultdata_T_2 \| resultdata_data_4; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_4 = _resultdata_T_3 \| resultdata_data_5; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_5 = _resultdata_T_4 \| resultdata_data_6; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_6 = _resultdata_T_5 \| resultdata_data_7; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_7 = _resultdata_T_6 \| resultdata_data_8; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_8 = _resultdata_T_7 \| resultdata_data_9; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_9 = _resultdata_T_8 \| resultdata_data_10; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_10 = _resultdata_T_9 \| resultdata_data_11; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_11 = _resultdata_T_10 \| resultdata_data_12; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_12 = _resultdata_T_11 \| resultdata_data_13; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_13 = _resultdata_T_12 \| resultdata_data_14; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_14 = _resultdata_T_13 \| resultdata_data_15; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_15 = _resultdata_T_14 \| resultdata_data_16; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_16 = _resultdata_T_15 \| resultdata_data_17; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_17 = _resultdata_T_16 \| resultdata_data_18; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_18 = _resultdata_T_17 \| resultdata_data_19; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_19 = _resultdata_T_18 \| resultdata_data_20; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_20 = _resultdata_T_19 \| resultdata_data_21; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_21 = _resultdata_T_20 \| resultdata_data_22; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_22 = _resultdata_T_21 \| resultdata_data_23; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_23 = _resultdata_T_22 \| resultdata_data_24; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_24 = _resultdata_T_23 \| resultdata_data_25; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_25 = _resultdata_T_24 \| resultdata_data_26; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_26 = _resultdata_T_25 \| resultdata_data_27; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_27 = _resultdata_T_26 \| resultdata_data_28; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_28 = _resultdata_T_27 \| resultdata_data_29; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] wire [255:0] _resultdata_T_29 = _resultdata_T_28 \| resultdata_data_30; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] assign resultdata = _resultdata_T_29 \| resultdata_data_31; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15] assign response_output_bits_data = resultdata; // @[L2MemHelperLatencyInjection.scala:53:29, :307:15] assign _response_output_valid_T = queueValid & _outstanding_req_addr_io_deq_valid; // @[Misc.scala:26:53] assign response_output_valid = _response_output_valid_T; // @[Misc.scala:26:53] wire _outstanding_req_addr_io_deq_ready_T = queueValid & response_output_ready; // @[Misc.scala:26:53] wire _T_572 = response_output_ready & _outstanding_req_addr_io_deq_valid; // @[Misc.scala:26:53] wire opdata = masterNodeOut_d_bits_opcode[0]; // @[Edges.scala:106:36] reg [63:0] loginfo_cycles_40; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_80 = {1'h0, loginfo_cycles_40} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_81 = _loginfo_cycles_T_80[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_41; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_82 = {1'h0, loginfo_cycles_41} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_83 = _loginfo_cycles_T_82[63:0]; // @[Util.scala:19:38] wire _T_590 = response_output_ready & response_output_valid; // @[Decoupled.scala:51:35] reg [63:0] loginfo_cycles_42; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_84 = {1'h0, loginfo_cycles_42} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_85 = _loginfo_cycles_T_84[63:0]; // @[Util.scala:19:38]
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_45 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, b : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _source_ok_T_29 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _source_ok_T_30 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _source_ok_T_31 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _source_ok_T_32 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _source_ok_T_33 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _source_ok_T_34 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _source_ok_T_35 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _source_ok_T_36 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _source_ok_T_37 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _source_ok_T_38 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _source_ok_T_39 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_40 = eq(io.in.a.bits.source, UInt<6>(0h22)) wire _source_ok_WIRE : UInt<1>[21] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 connect _source_ok_WIRE[8], _source_ok_T_28 connect _source_ok_WIRE[9], _source_ok_T_29 connect _source_ok_WIRE[10], _source_ok_T_30 connect _source_ok_WIRE[11], _source_ok_T_31 connect _source_ok_WIRE[12], _source_ok_T_32 connect _source_ok_WIRE[13], _source_ok_T_33 connect _source_ok_WIRE[14], _source_ok_T_34 connect _source_ok_WIRE[15], _source_ok_T_35 connect _source_ok_WIRE[16], _source_ok_T_36 connect _source_ok_WIRE[17], _source_ok_T_37 connect _source_ok_WIRE[18], _source_ok_T_38 connect _source_ok_WIRE[19], _source_ok_T_39 connect _source_ok_WIRE[20], _source_ok_T_40 node _source_ok_T_41 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_42 = or(_source_ok_T_41, _source_ok_WIRE[2]) node _source_ok_T_43 = or(_source_ok_T_42, _source_ok_WIRE[3]) node _source_ok_T_44 = or(_source_ok_T_43, _source_ok_WIRE[4]) node _source_ok_T_45 = or(_source_ok_T_44, _source_ok_WIRE[5]) node _source_ok_T_46 = or(_source_ok_T_45, _source_ok_WIRE[6]) node _source_ok_T_47 = or(_source_ok_T_46, _source_ok_WIRE[7]) node _source_ok_T_48 = or(_source_ok_T_47, _source_ok_WIRE[8]) node _source_ok_T_49 = or(_source_ok_T_48, _source_ok_WIRE[9]) node _source_ok_T_50 = or(_source_ok_T_49, _source_ok_WIRE[10]) node _source_ok_T_51 = or(_source_ok_T_50, _source_ok_WIRE[11]) node _source_ok_T_52 = or(_source_ok_T_51, _source_ok_WIRE[12]) node _source_ok_T_53 = or(_source_ok_T_52, _source_ok_WIRE[13]) node _source_ok_T_54 = or(_source_ok_T_53, _source_ok_WIRE[14]) node _source_ok_T_55 = or(_source_ok_T_54, _source_ok_WIRE[15]) node _source_ok_T_56 = or(_source_ok_T_55, _source_ok_WIRE[16]) node _source_ok_T_57 = or(_source_ok_T_56, _source_ok_WIRE[17]) node _source_ok_T_58 = or(_source_ok_T_57, _source_ok_WIRE[18]) node _source_ok_T_59 = or(_source_ok_T_58, _source_ok_WIRE[19]) node source_ok = or(_source_ok_T_59, _source_ok_WIRE[20]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _T_88 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_89 = eq(_T_88, UInt<1>(0h0)) node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_89, _T_94) node _T_96 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_99 = cvt(_T_98) node _T_100 = and(_T_99, asSInt(UInt<1>(0h0))) node _T_101 = asSInt(_T_100) node _T_102 = eq(_T_101, asSInt(UInt<1>(0h0))) node _T_103 = or(_T_97, _T_102) node _T_104 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_105 = eq(_T_104, UInt<1>(0h0)) node _T_106 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_107 = cvt(_T_106) node _T_108 = and(_T_107, asSInt(UInt<1>(0h0))) node _T_109 = asSInt(_T_108) node _T_110 = eq(_T_109, asSInt(UInt<1>(0h0))) node _T_111 = or(_T_105, _T_110) node _T_112 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_113 = eq(_T_112, UInt<1>(0h0)) node _T_114 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_115 = cvt(_T_114) node _T_116 = and(_T_115, asSInt(UInt<1>(0h0))) node _T_117 = asSInt(_T_116) node _T_118 = eq(_T_117, asSInt(UInt<1>(0h0))) node _T_119 = or(_T_113, _T_118) node _T_120 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_121 = eq(_T_120, UInt<1>(0h0)) node _T_122 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_123 = cvt(_T_122) node _T_124 = and(_T_123, asSInt(UInt<1>(0h0))) node _T_125 = asSInt(_T_124) node _T_126 = eq(_T_125, asSInt(UInt<1>(0h0))) node _T_127 = or(_T_121, _T_126) node _T_128 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_129 = eq(_T_128, UInt<1>(0h0)) node _T_130 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_131 = cvt(_T_130) node _T_132 = and(_T_131, asSInt(UInt<1>(0h0))) node _T_133 = asSInt(_T_132) node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0))) node _T_135 = or(_T_129, _T_134) node _T_136 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_137 = eq(_T_136, UInt<1>(0h0)) node _T_138 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_139 = cvt(_T_138) node _T_140 = and(_T_139, asSInt(UInt<1>(0h0))) node _T_141 = asSInt(_T_140) node _T_142 = eq(_T_141, asSInt(UInt<1>(0h0))) node _T_143 = or(_T_137, _T_142) node _T_144 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_145 = eq(_T_144, UInt<1>(0h0)) node _T_146 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_147 = cvt(_T_146) node _T_148 = and(_T_147, asSInt(UInt<1>(0h0))) node _T_149 = asSInt(_T_148) node _T_150 = eq(_T_149, asSInt(UInt<1>(0h0))) node _T_151 = or(_T_145, _T_150) node _T_152 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_155 = cvt(_T_154) node _T_156 = and(_T_155, asSInt(UInt<1>(0h0))) node _T_157 = asSInt(_T_156) node _T_158 = eq(_T_157, asSInt(UInt<1>(0h0))) node _T_159 = or(_T_153, _T_158) node _T_160 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_161 = eq(_T_160, UInt<1>(0h0)) node _T_162 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_163 = cvt(_T_162) node _T_164 = and(_T_163, asSInt(UInt<1>(0h0))) node _T_165 = asSInt(_T_164) node _T_166 = eq(_T_165, asSInt(UInt<1>(0h0))) node _T_167 = or(_T_161, _T_166) node _T_168 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_169 = eq(_T_168, UInt<1>(0h0)) node _T_170 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_171 = cvt(_T_170) node _T_172 = and(_T_171, asSInt(UInt<1>(0h0))) node _T_173 = asSInt(_T_172) node _T_174 = eq(_T_173, asSInt(UInt<1>(0h0))) node _T_175 = or(_T_169, _T_174) node _T_176 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_177 = eq(_T_176, UInt<1>(0h0)) node _T_178 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_179 = cvt(_T_178) node _T_180 = and(_T_179, asSInt(UInt<1>(0h0))) node _T_181 = asSInt(_T_180) node _T_182 = eq(_T_181, asSInt(UInt<1>(0h0))) node _T_183 = or(_T_177, _T_182) node _T_184 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_185 = eq(_T_184, UInt<1>(0h0)) node _T_186 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_187 = cvt(_T_186) node _T_188 = and(_T_187, asSInt(UInt<1>(0h0))) node _T_189 = asSInt(_T_188) node _T_190 = eq(_T_189, asSInt(UInt<1>(0h0))) node _T_191 = or(_T_185, _T_190) node _T_192 = and(_T_11, _T_24) node _T_193 = and(_T_192, _T_37) node _T_194 = and(_T_193, _T_50) node _T_195 = and(_T_194, _T_63) node _T_196 = and(_T_195, _T_71) node _T_197 = and(_T_196, _T_79) node _T_198 = and(_T_197, _T_87) node _T_199 = and(_T_198, _T_95) node _T_200 = and(_T_199, _T_103) node _T_201 = and(_T_200, _T_111) node _T_202 = and(_T_201, _T_119) node _T_203 = and(_T_202, _T_127) node _T_204 = and(_T_203, _T_135) node _T_205 = and(_T_204, _T_143) node _T_206 = and(_T_205, _T_151) node _T_207 = and(_T_206, _T_159) node _T_208 = and(_T_207, _T_167) node _T_209 = and(_T_208, _T_175) node _T_210 = and(_T_209, _T_183) node _T_211 = and(_T_210, _T_191) node _T_212 = asUInt(reset) node _T_213 = eq(_T_212, UInt<1>(0h0)) when _T_213 : node _T_214 = eq(_T_211, UInt<1>(0h0)) when _T_214 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_211, UInt<1>(0h1), "") : assert_1 node _T_215 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_215 : node _T_216 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_217 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_218 = and(_T_216, _T_217) node _T_219 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_220 = shr(io.in.a.bits.source, 2) node _T_221 = eq(_T_220, UInt<1>(0h0)) node _T_222 = leq(UInt<1>(0h0), uncommonBits_4) node _T_223 = and(_T_221, _T_222) node _T_224 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_225 = and(_T_223, _T_224) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_226 = shr(io.in.a.bits.source, 2) node _T_227 = eq(_T_226, UInt<1>(0h1)) node _T_228 = leq(UInt<1>(0h0), uncommonBits_5) node _T_229 = and(_T_227, _T_228) node _T_230 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_231 = and(_T_229, _T_230) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_232 = shr(io.in.a.bits.source, 2) node _T_233 = eq(_T_232, UInt<2>(0h2)) node _T_234 = leq(UInt<1>(0h0), uncommonBits_6) node _T_235 = and(_T_233, _T_234) node _T_236 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_237 = and(_T_235, _T_236) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_238 = shr(io.in.a.bits.source, 2) node _T_239 = eq(_T_238, UInt<2>(0h3)) node _T_240 = leq(UInt<1>(0h0), uncommonBits_7) node _T_241 = and(_T_239, _T_240) node _T_242 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_243 = and(_T_241, _T_242) node _T_244 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_245 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_246 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_247 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_248 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_249 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_250 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_251 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_252 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_253 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_254 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_255 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_256 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_257 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_258 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_259 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_260 = or(_T_219, _T_225) node _T_261 = or(_T_260, _T_231) node _T_262 = or(_T_261, _T_237) node _T_263 = or(_T_262, _T_243) node _T_264 = or(_T_263, _T_244) node _T_265 = or(_T_264, _T_245) node _T_266 = or(_T_265, _T_246) node _T_267 = or(_T_266, _T_247) node _T_268 = or(_T_267, _T_248) node _T_269 = or(_T_268, _T_249) node _T_270 = or(_T_269, _T_250) node _T_271 = or(_T_270, _T_251) node _T_272 = or(_T_271, _T_252) node _T_273 = or(_T_272, _T_253) node _T_274 = or(_T_273, _T_254) node _T_275 = or(_T_274, _T_255) node _T_276 = or(_T_275, _T_256) node _T_277 = or(_T_276, _T_257) node _T_278 = or(_T_277, _T_258) node _T_279 = or(_T_278, _T_259) node _T_280 = and(_T_218, _T_279) node _T_281 = or(UInt<1>(0h0), _T_280) node _T_282 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_283 = or(UInt<1>(0h0), _T_282) node _T_284 = xor(io.in.a.bits.address, UInt<28>(0h8000040)) node _T_285 = cvt(_T_284) node _T_286 = and(_T_285, asSInt(UInt<17>(0h100c0))) node _T_287 = asSInt(_T_286) node _T_288 = eq(_T_287, asSInt(UInt<1>(0h0))) node _T_289 = xor(io.in.a.bits.address, UInt<32>(0h80000040)) node _T_290 = cvt(_T_289) node _T_291 = and(_T_290, asSInt(UInt<29>(0h100000c0))) node _T_292 = asSInt(_T_291) node _T_293 = eq(_T_292, asSInt(UInt<1>(0h0))) node _T_294 = or(_T_288, _T_293) node _T_295 = and(_T_283, _T_294) node _T_296 = or(UInt<1>(0h0), _T_295) node _T_297 = and(_T_281, _T_296) node _T_298 = asUInt(reset) node _T_299 = eq(_T_298, UInt<1>(0h0)) when _T_299 : node _T_300 = eq(_T_297, UInt<1>(0h0)) when _T_300 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_297, UInt<1>(0h1), "") : assert_2 node _T_301 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_302 = shr(io.in.a.bits.source, 2) node _T_303 = eq(_T_302, UInt<1>(0h0)) node _T_304 = leq(UInt<1>(0h0), uncommonBits_8) node _T_305 = and(_T_303, _T_304) node _T_306 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_307 = and(_T_305, _T_306) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_308 = shr(io.in.a.bits.source, 2) node _T_309 = eq(_T_308, UInt<1>(0h1)) node _T_310 = leq(UInt<1>(0h0), uncommonBits_9) node _T_311 = and(_T_309, _T_310) node _T_312 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_313 = and(_T_311, _T_312) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_314 = shr(io.in.a.bits.source, 2) node _T_315 = eq(_T_314, UInt<2>(0h2)) node _T_316 = leq(UInt<1>(0h0), uncommonBits_10) node _T_317 = and(_T_315, _T_316) node _T_318 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_319 = and(_T_317, _T_318) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_320 = shr(io.in.a.bits.source, 2) node _T_321 = eq(_T_320, UInt<2>(0h3)) node _T_322 = leq(UInt<1>(0h0), uncommonBits_11) node _T_323 = and(_T_321, _T_322) node _T_324 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_325 = and(_T_323, _T_324) node _T_326 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_327 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_328 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_329 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_330 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_331 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_332 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_333 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_334 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_335 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_336 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_337 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_338 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_339 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_340 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_341 = eq(io.in.a.bits.source, UInt<6>(0h22)) wire _WIRE : UInt<1>[21] connect _WIRE[0], _T_301 connect _WIRE[1], _T_307 connect _WIRE[2], _T_313 connect _WIRE[3], _T_319 connect _WIRE[4], _T_325 connect _WIRE[5], _T_326 connect _WIRE[6], _T_327 connect _WIRE[7], _T_328 connect _WIRE[8], _T_329 connect _WIRE[9], _T_330 connect _WIRE[10], _T_331 connect _WIRE[11], _T_332 connect _WIRE[12], _T_333 connect _WIRE[13], _T_334 connect _WIRE[14], _T_335 connect _WIRE[15], _T_336 connect _WIRE[16], _T_337 connect _WIRE[17], _T_338 connect _WIRE[18], _T_339 connect _WIRE[19], _T_340 connect _WIRE[20], _T_341 node _T_342 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_343 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_344 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_345 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_346 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_347 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_348 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_349 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_350 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_351 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_352 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_353 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_354 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_355 = mux(_WIRE[5], _T_342, UInt<1>(0h0)) node _T_356 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_357 = mux(_WIRE[7], _T_343, UInt<1>(0h0)) node _T_358 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_359 = mux(_WIRE[9], _T_344, UInt<1>(0h0)) node _T_360 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_361 = mux(_WIRE[11], _T_345, UInt<1>(0h0)) node _T_362 = mux(_WIRE[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_363 = mux(_WIRE[13], _T_346, UInt<1>(0h0)) node _T_364 = mux(_WIRE[14], UInt<1>(0h0), UInt<1>(0h0)) node _T_365 = mux(_WIRE[15], _T_347, UInt<1>(0h0)) node _T_366 = mux(_WIRE[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_367 = mux(_WIRE[17], _T_348, UInt<1>(0h0)) node _T_368 = mux(_WIRE[18], UInt<1>(0h0), UInt<1>(0h0)) node _T_369 = mux(_WIRE[19], _T_349, UInt<1>(0h0)) node _T_370 = mux(_WIRE[20], UInt<1>(0h0), UInt<1>(0h0)) node _T_371 = or(_T_350, _T_351) node _T_372 = or(_T_371, _T_352) node _T_373 = or(_T_372, _T_353) node _T_374 = or(_T_373, _T_354) node _T_375 = or(_T_374, _T_355) node _T_376 = or(_T_375, _T_356) node _T_377 = or(_T_376, _T_357) node _T_378 = or(_T_377, _T_358) node _T_379 = or(_T_378, _T_359) node _T_380 = or(_T_379, _T_360) node _T_381 = or(_T_380, _T_361) node _T_382 = or(_T_381, _T_362) node _T_383 = or(_T_382, _T_363) node _T_384 = or(_T_383, _T_364) node _T_385 = or(_T_384, _T_365) node _T_386 = or(_T_385, _T_366) node _T_387 = or(_T_386, _T_367) node _T_388 = or(_T_387, _T_368) node _T_389 = or(_T_388, _T_369) node _T_390 = or(_T_389, _T_370) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_390 node _T_391 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_392 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_393 = and(_T_391, _T_392) node _T_394 = or(UInt<1>(0h0), _T_393) node _T_395 = xor(io.in.a.bits.address, UInt<28>(0h8000040)) node _T_396 = cvt(_T_395) node _T_397 = and(_T_396, asSInt(UInt<17>(0h100c0))) node _T_398 = asSInt(_T_397) node _T_399 = eq(_T_398, asSInt(UInt<1>(0h0))) node _T_400 = xor(io.in.a.bits.address, UInt<32>(0h80000040)) node _T_401 = cvt(_T_400) node _T_402 = and(_T_401, asSInt(UInt<29>(0h100000c0))) node _T_403 = asSInt(_T_402) node _T_404 = eq(_T_403, asSInt(UInt<1>(0h0))) node _T_405 = or(_T_399, _T_404) node _T_406 = and(_T_394, _T_405) node _T_407 = or(UInt<1>(0h0), _T_406) node _T_408 = and(_WIRE_1, _T_407) node _T_409 = asUInt(reset) node _T_410 = eq(_T_409, UInt<1>(0h0)) when _T_410 : node _T_411 = eq(_T_408, UInt<1>(0h0)) when _T_411 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_408, UInt<1>(0h1), "") : assert_3 node _T_412 = asUInt(reset) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(source_ok, UInt<1>(0h0)) when _T_414 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_415 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_416 = asUInt(reset) node _T_417 = eq(_T_416, UInt<1>(0h0)) when _T_417 : node _T_418 = eq(_T_415, UInt<1>(0h0)) when _T_418 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_415, UInt<1>(0h1), "") : assert_5 node _T_419 = asUInt(reset) node _T_420 = eq(_T_419, UInt<1>(0h0)) when _T_420 : node _T_421 = eq(is_aligned, UInt<1>(0h0)) when _T_421 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_422 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_423 = asUInt(reset) node _T_424 = eq(_T_423, UInt<1>(0h0)) when _T_424 : node _T_425 = eq(_T_422, UInt<1>(0h0)) when _T_425 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_422, UInt<1>(0h1), "") : assert_7 node _T_426 = not(io.in.a.bits.mask) node _T_427 = eq(_T_426, UInt<1>(0h0)) node _T_428 = asUInt(reset) node _T_429 = eq(_T_428, UInt<1>(0h0)) when _T_429 : node _T_430 = eq(_T_427, UInt<1>(0h0)) when _T_430 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_427, UInt<1>(0h1), "") : assert_8 node _T_431 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_432 = asUInt(reset) node _T_433 = eq(_T_432, UInt<1>(0h0)) when _T_433 : node _T_434 = eq(_T_431, UInt<1>(0h0)) when _T_434 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_431, UInt<1>(0h1), "") : assert_9 node _T_435 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_435 : node _T_436 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_437 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_438 = and(_T_436, _T_437) node _T_439 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_440 = shr(io.in.a.bits.source, 2) node _T_441 = eq(_T_440, UInt<1>(0h0)) node _T_442 = leq(UInt<1>(0h0), uncommonBits_12) node _T_443 = and(_T_441, _T_442) node _T_444 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_445 = and(_T_443, _T_444) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_446 = shr(io.in.a.bits.source, 2) node _T_447 = eq(_T_446, UInt<1>(0h1)) node _T_448 = leq(UInt<1>(0h0), uncommonBits_13) node _T_449 = and(_T_447, _T_448) node _T_450 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_451 = and(_T_449, _T_450) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_452 = shr(io.in.a.bits.source, 2) node _T_453 = eq(_T_452, UInt<2>(0h2)) node _T_454 = leq(UInt<1>(0h0), uncommonBits_14) node _T_455 = and(_T_453, _T_454) node _T_456 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_457 = and(_T_455, _T_456) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_458 = shr(io.in.a.bits.source, 2) node _T_459 = eq(_T_458, UInt<2>(0h3)) node _T_460 = leq(UInt<1>(0h0), uncommonBits_15) node _T_461 = and(_T_459, _T_460) node _T_462 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_463 = and(_T_461, _T_462) node _T_464 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_465 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_466 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_467 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_468 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_469 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_470 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_471 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_472 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_473 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_474 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_475 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_476 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_477 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_478 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_479 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_480 = or(_T_439, _T_445) node _T_481 = or(_T_480, _T_451) node _T_482 = or(_T_481, _T_457) node _T_483 = or(_T_482, _T_463) node _T_484 = or(_T_483, _T_464) node _T_485 = or(_T_484, _T_465) node _T_486 = or(_T_485, _T_466) node _T_487 = or(_T_486, _T_467) node _T_488 = or(_T_487, _T_468) node _T_489 = or(_T_488, _T_469) node _T_490 = or(_T_489, _T_470) node _T_491 = or(_T_490, _T_471) node _T_492 = or(_T_491, _T_472) node _T_493 = or(_T_492, _T_473) node _T_494 = or(_T_493, _T_474) node _T_495 = or(_T_494, _T_475) node _T_496 = or(_T_495, _T_476) node _T_497 = or(_T_496, _T_477) node _T_498 = or(_T_497, _T_478) node _T_499 = or(_T_498, _T_479) node _T_500 = and(_T_438, _T_499) node _T_501 = or(UInt<1>(0h0), _T_500) node _T_502 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_503 = or(UInt<1>(0h0), _T_502) node _T_504 = xor(io.in.a.bits.address, UInt<28>(0h8000040)) node _T_505 = cvt(_T_504) node _T_506 = and(_T_505, asSInt(UInt<17>(0h100c0))) node _T_507 = asSInt(_T_506) node _T_508 = eq(_T_507, asSInt(UInt<1>(0h0))) node _T_509 = xor(io.in.a.bits.address, UInt<32>(0h80000040)) node _T_510 = cvt(_T_509) node _T_511 = and(_T_510, asSInt(UInt<29>(0h100000c0))) node _T_512 = asSInt(_T_511) node _T_513 = eq(_T_512, asSInt(UInt<1>(0h0))) node _T_514 = or(_T_508, _T_513) node _T_515 = and(_T_503, _T_514) node _T_516 = or(UInt<1>(0h0), _T_515) node _T_517 = and(_T_501, _T_516) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_517, UInt<1>(0h1), "") : assert_10 node _T_521 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_522 = shr(io.in.a.bits.source, 2) node _T_523 = eq(_T_522, UInt<1>(0h0)) node _T_524 = leq(UInt<1>(0h0), uncommonBits_16) node _T_525 = and(_T_523, _T_524) node _T_526 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_527 = and(_T_525, _T_526) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_528 = shr(io.in.a.bits.source, 2) node _T_529 = eq(_T_528, UInt<1>(0h1)) node _T_530 = leq(UInt<1>(0h0), uncommonBits_17) node _T_531 = and(_T_529, _T_530) node _T_532 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_533 = and(_T_531, _T_532) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_534 = shr(io.in.a.bits.source, 2) node _T_535 = eq(_T_534, UInt<2>(0h2)) node _T_536 = leq(UInt<1>(0h0), uncommonBits_18) node _T_537 = and(_T_535, _T_536) node _T_538 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_539 = and(_T_537, _T_538) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_540 = shr(io.in.a.bits.source, 2) node _T_541 = eq(_T_540, UInt<2>(0h3)) node _T_542 = leq(UInt<1>(0h0), uncommonBits_19) node _T_543 = and(_T_541, _T_542) node _T_544 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_545 = and(_T_543, _T_544) node _T_546 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_547 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_548 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_549 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_550 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_551 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_552 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_553 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_554 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_555 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_556 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_557 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_558 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_559 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_560 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_561 = eq(io.in.a.bits.source, UInt<6>(0h22)) wire _WIRE_2 : UInt<1>[21] connect _WIRE_2[0], _T_521 connect _WIRE_2[1], _T_527 connect _WIRE_2[2], _T_533 connect _WIRE_2[3], _T_539 connect _WIRE_2[4], _T_545 connect _WIRE_2[5], _T_546 connect _WIRE_2[6], _T_547 connect _WIRE_2[7], _T_548 connect _WIRE_2[8], _T_549 connect _WIRE_2[9], _T_550 connect _WIRE_2[10], _T_551 connect _WIRE_2[11], _T_552 connect _WIRE_2[12], _T_553 connect _WIRE_2[13], _T_554 connect _WIRE_2[14], _T_555 connect _WIRE_2[15], _T_556 connect _WIRE_2[16], _T_557 connect _WIRE_2[17], _T_558 connect _WIRE_2[18], _T_559 connect _WIRE_2[19], _T_560 connect _WIRE_2[20], _T_561 node _T_562 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_563 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_564 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_565 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_566 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_567 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_568 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_569 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_570 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_571 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_572 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_573 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_574 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_575 = mux(_WIRE_2[5], _T_562, UInt<1>(0h0)) node _T_576 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_577 = mux(_WIRE_2[7], _T_563, UInt<1>(0h0)) node _T_578 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_579 = mux(_WIRE_2[9], _T_564, UInt<1>(0h0)) node _T_580 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_581 = mux(_WIRE_2[11], _T_565, UInt<1>(0h0)) node _T_582 = mux(_WIRE_2[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_583 = mux(_WIRE_2[13], _T_566, UInt<1>(0h0)) node _T_584 = mux(_WIRE_2[14], UInt<1>(0h0), UInt<1>(0h0)) node _T_585 = mux(_WIRE_2[15], _T_567, UInt<1>(0h0)) node _T_586 = mux(_WIRE_2[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_587 = mux(_WIRE_2[17], _T_568, UInt<1>(0h0)) node _T_588 = mux(_WIRE_2[18], UInt<1>(0h0), UInt<1>(0h0)) node _T_589 = mux(_WIRE_2[19], _T_569, UInt<1>(0h0)) node _T_590 = mux(_WIRE_2[20], UInt<1>(0h0), UInt<1>(0h0)) node _T_591 = or(_T_570, _T_571) node _T_592 = or(_T_591, _T_572) node _T_593 = or(_T_592, _T_573) node _T_594 = or(_T_593, _T_574) node _T_595 = or(_T_594, _T_575) node _T_596 = or(_T_595, _T_576) node _T_597 = or(_T_596, _T_577) node _T_598 = or(_T_597, _T_578) node _T_599 = or(_T_598, _T_579) node _T_600 = or(_T_599, _T_580) node _T_601 = or(_T_600, _T_581) node _T_602 = or(_T_601, _T_582) node _T_603 = or(_T_602, _T_583) node _T_604 = or(_T_603, _T_584) node _T_605 = or(_T_604, _T_585) node _T_606 = or(_T_605, _T_586) node _T_607 = or(_T_606, _T_587) node _T_608 = or(_T_607, _T_588) node _T_609 = or(_T_608, _T_589) node _T_610 = or(_T_609, _T_590) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_610 node _T_611 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_612 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_613 = and(_T_611, _T_612) node _T_614 = or(UInt<1>(0h0), _T_613) node _T_615 = xor(io.in.a.bits.address, UInt<28>(0h8000040)) node _T_616 = cvt(_T_615) node _T_617 = and(_T_616, asSInt(UInt<17>(0h100c0))) node _T_618 = asSInt(_T_617) node _T_619 = eq(_T_618, asSInt(UInt<1>(0h0))) node _T_620 = xor(io.in.a.bits.address, UInt<32>(0h80000040)) node _T_621 = cvt(_T_620) node _T_622 = and(_T_621, asSInt(UInt<29>(0h100000c0))) node _T_623 = asSInt(_T_622) node _T_624 = eq(_T_623, asSInt(UInt<1>(0h0))) node _T_625 = or(_T_619, _T_624) node _T_626 = and(_T_614, _T_625) node _T_627 = or(UInt<1>(0h0), _T_626) node _T_628 = and(_WIRE_3, _T_627) node _T_629 = asUInt(reset) node _T_630 = eq(_T_629, UInt<1>(0h0)) when _T_630 : node _T_631 = eq(_T_628, UInt<1>(0h0)) when _T_631 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_628, UInt<1>(0h1), "") : assert_11 node _T_632 = asUInt(reset) node _T_633 = eq(_T_632, UInt<1>(0h0)) when _T_633 : node _T_634 = eq(source_ok, UInt<1>(0h0)) when _T_634 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_635 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_636 = asUInt(reset) node _T_637 = eq(_T_636, UInt<1>(0h0)) when _T_637 : node _T_638 = eq(_T_635, UInt<1>(0h0)) when _T_638 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_635, UInt<1>(0h1), "") : assert_13 node _T_639 = asUInt(reset) node _T_640 = eq(_T_639, UInt<1>(0h0)) when _T_640 : node _T_641 = eq(is_aligned, UInt<1>(0h0)) when _T_641 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_642 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_643 = asUInt(reset) node _T_644 = eq(_T_643, UInt<1>(0h0)) when _T_644 : node _T_645 = eq(_T_642, UInt<1>(0h0)) when _T_645 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_642, UInt<1>(0h1), "") : assert_15 node _T_646 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_647 = asUInt(reset) node _T_648 = eq(_T_647, UInt<1>(0h0)) when _T_648 : node _T_649 = eq(_T_646, UInt<1>(0h0)) when _T_649 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_646, UInt<1>(0h1), "") : assert_16 node _T_650 = not(io.in.a.bits.mask) node _T_651 = eq(_T_650, UInt<1>(0h0)) node _T_652 = asUInt(reset) node _T_653 = eq(_T_652, UInt<1>(0h0)) when _T_653 : node _T_654 = eq(_T_651, UInt<1>(0h0)) when _T_654 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_651, UInt<1>(0h1), "") : assert_17 node _T_655 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_656 = asUInt(reset) node _T_657 = eq(_T_656, UInt<1>(0h0)) when _T_657 : node _T_658 = eq(_T_655, UInt<1>(0h0)) when _T_658 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_655, UInt<1>(0h1), "") : assert_18 node _T_659 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_659 : node _T_660 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_661 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_662 = and(_T_660, _T_661) node _T_663 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_664 = shr(io.in.a.bits.source, 2) node _T_665 = eq(_T_664, UInt<1>(0h0)) node _T_666 = leq(UInt<1>(0h0), uncommonBits_20) node _T_667 = and(_T_665, _T_666) node _T_668 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_669 = and(_T_667, _T_668) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_670 = shr(io.in.a.bits.source, 2) node _T_671 = eq(_T_670, UInt<1>(0h1)) node _T_672 = leq(UInt<1>(0h0), uncommonBits_21) node _T_673 = and(_T_671, _T_672) node _T_674 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_675 = and(_T_673, _T_674) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_676 = shr(io.in.a.bits.source, 2) node _T_677 = eq(_T_676, UInt<2>(0h2)) node _T_678 = leq(UInt<1>(0h0), uncommonBits_22) node _T_679 = and(_T_677, _T_678) node _T_680 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_681 = and(_T_679, _T_680) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_682 = shr(io.in.a.bits.source, 2) node _T_683 = eq(_T_682, UInt<2>(0h3)) node _T_684 = leq(UInt<1>(0h0), uncommonBits_23) node _T_685 = and(_T_683, _T_684) node _T_686 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_687 = and(_T_685, _T_686) node _T_688 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_689 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_690 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_691 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_692 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_693 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_694 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_695 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_696 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_697 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_698 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_699 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_700 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_701 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_702 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_703 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_704 = or(_T_663, _T_669) node _T_705 = or(_T_704, _T_675) node _T_706 = or(_T_705, _T_681) node _T_707 = or(_T_706, _T_687) node _T_708 = or(_T_707, _T_688) node _T_709 = or(_T_708, _T_689) node _T_710 = or(_T_709, _T_690) node _T_711 = or(_T_710, _T_691) node _T_712 = or(_T_711, _T_692) node _T_713 = or(_T_712, _T_693) node _T_714 = or(_T_713, _T_694) node _T_715 = or(_T_714, _T_695) node _T_716 = or(_T_715, _T_696) node _T_717 = or(_T_716, _T_697) node _T_718 = or(_T_717, _T_698) node _T_719 = or(_T_718, _T_699) node _T_720 = or(_T_719, _T_700) node _T_721 = or(_T_720, _T_701) node _T_722 = or(_T_721, _T_702) node _T_723 = or(_T_722, _T_703) node _T_724 = and(_T_662, _T_723) node _T_725 = or(UInt<1>(0h0), _T_724) node _T_726 = asUInt(reset) node _T_727 = eq(_T_726, UInt<1>(0h0)) when _T_727 : node _T_728 = eq(_T_725, UInt<1>(0h0)) when _T_728 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_725, UInt<1>(0h1), "") : assert_19 node _T_729 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_730 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_731 = and(_T_729, _T_730) node _T_732 = or(UInt<1>(0h0), _T_731) node _T_733 = xor(io.in.a.bits.address, UInt<28>(0h8000040)) node _T_734 = cvt(_T_733) node _T_735 = and(_T_734, asSInt(UInt<17>(0h100c0))) node _T_736 = asSInt(_T_735) node _T_737 = eq(_T_736, asSInt(UInt<1>(0h0))) node _T_738 = xor(io.in.a.bits.address, UInt<32>(0h80000040)) node _T_739 = cvt(_T_738) node _T_740 = and(_T_739, asSInt(UInt<29>(0h100000c0))) node _T_741 = asSInt(_T_740) node _T_742 = eq(_T_741, asSInt(UInt<1>(0h0))) node _T_743 = or(_T_737, _T_742) node _T_744 = and(_T_732, _T_743) node _T_745 = or(UInt<1>(0h0), _T_744) node _T_746 = asUInt(reset) node _T_747 = eq(_T_746, UInt<1>(0h0)) when _T_747 : node _T_748 = eq(_T_745, UInt<1>(0h0)) when _T_748 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_745, UInt<1>(0h1), "") : assert_20 node _T_749 = asUInt(reset) node _T_750 = eq(_T_749, UInt<1>(0h0)) when _T_750 : node _T_751 = eq(source_ok, UInt<1>(0h0)) when _T_751 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_752 = asUInt(reset) node _T_753 = eq(_T_752, UInt<1>(0h0)) when _T_753 : node _T_754 = eq(is_aligned, UInt<1>(0h0)) when _T_754 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_755 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_756 = asUInt(reset) node _T_757 = eq(_T_756, UInt<1>(0h0)) when _T_757 : node _T_758 = eq(_T_755, UInt<1>(0h0)) when _T_758 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_755, UInt<1>(0h1), "") : assert_23 node _T_759 = eq(io.in.a.bits.mask, mask) node _T_760 = asUInt(reset) node _T_761 = eq(_T_760, UInt<1>(0h0)) when _T_761 : node _T_762 = eq(_T_759, UInt<1>(0h0)) when _T_762 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_759, UInt<1>(0h1), "") : assert_24 node _T_763 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_764 = asUInt(reset) node _T_765 = eq(_T_764, UInt<1>(0h0)) when _T_765 : node _T_766 = eq(_T_763, UInt<1>(0h0)) when _T_766 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_763, UInt<1>(0h1), "") : assert_25 node _T_767 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_767 : node _T_768 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_769 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_770 = and(_T_768, _T_769) node _T_771 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_772 = shr(io.in.a.bits.source, 2) node _T_773 = eq(_T_772, UInt<1>(0h0)) node _T_774 = leq(UInt<1>(0h0), uncommonBits_24) node _T_775 = and(_T_773, _T_774) node _T_776 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_777 = and(_T_775, _T_776) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_778 = shr(io.in.a.bits.source, 2) node _T_779 = eq(_T_778, UInt<1>(0h1)) node _T_780 = leq(UInt<1>(0h0), uncommonBits_25) node _T_781 = and(_T_779, _T_780) node _T_782 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_783 = and(_T_781, _T_782) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_784 = shr(io.in.a.bits.source, 2) node _T_785 = eq(_T_784, UInt<2>(0h2)) node _T_786 = leq(UInt<1>(0h0), uncommonBits_26) node _T_787 = and(_T_785, _T_786) node _T_788 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_789 = and(_T_787, _T_788) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_790 = shr(io.in.a.bits.source, 2) node _T_791 = eq(_T_790, UInt<2>(0h3)) node _T_792 = leq(UInt<1>(0h0), uncommonBits_27) node _T_793 = and(_T_791, _T_792) node _T_794 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_795 = and(_T_793, _T_794) node _T_796 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_797 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_798 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_799 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_800 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_801 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_802 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_803 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_804 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_805 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_806 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_807 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_808 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_809 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_810 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_811 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_812 = or(_T_771, _T_777) node _T_813 = or(_T_812, _T_783) node _T_814 = or(_T_813, _T_789) node _T_815 = or(_T_814, _T_795) node _T_816 = or(_T_815, _T_796) node _T_817 = or(_T_816, _T_797) node _T_818 = or(_T_817, _T_798) node _T_819 = or(_T_818, _T_799) node _T_820 = or(_T_819, _T_800) node _T_821 = or(_T_820, _T_801) node _T_822 = or(_T_821, _T_802) node _T_823 = or(_T_822, _T_803) node _T_824 = or(_T_823, _T_804) node _T_825 = or(_T_824, _T_805) node _T_826 = or(_T_825, _T_806) node _T_827 = or(_T_826, _T_807) node _T_828 = or(_T_827, _T_808) node _T_829 = or(_T_828, _T_809) node _T_830 = or(_T_829, _T_810) node _T_831 = or(_T_830, _T_811) node _T_832 = and(_T_770, _T_831) node _T_833 = or(UInt<1>(0h0), _T_832) node _T_834 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_835 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_836 = and(_T_834, _T_835) node _T_837 = or(UInt<1>(0h0), _T_836) node _T_838 = xor(io.in.a.bits.address, UInt<28>(0h8000040)) node _T_839 = cvt(_T_838) node _T_840 = and(_T_839, asSInt(UInt<17>(0h100c0))) node _T_841 = asSInt(_T_840) node _T_842 = eq(_T_841, asSInt(UInt<1>(0h0))) node _T_843 = xor(io.in.a.bits.address, UInt<32>(0h80000040)) node _T_844 = cvt(_T_843) node _T_845 = and(_T_844, asSInt(UInt<29>(0h100000c0))) node _T_846 = asSInt(_T_845) node _T_847 = eq(_T_846, asSInt(UInt<1>(0h0))) node _T_848 = or(_T_842, _T_847) node _T_849 = and(_T_837, _T_848) node _T_850 = or(UInt<1>(0h0), _T_849) node _T_851 = and(_T_833, _T_850) node _T_852 = asUInt(reset) node _T_853 = eq(_T_852, UInt<1>(0h0)) when _T_853 : node _T_854 = eq(_T_851, UInt<1>(0h0)) when _T_854 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_851, UInt<1>(0h1), "") : assert_26 node _T_855 = asUInt(reset) node _T_856 = eq(_T_855, UInt<1>(0h0)) when _T_856 : node _T_857 = eq(source_ok, UInt<1>(0h0)) when _T_857 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_858 = asUInt(reset) node _T_859 = eq(_T_858, UInt<1>(0h0)) when _T_859 : node _T_860 = eq(is_aligned, UInt<1>(0h0)) when _T_860 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_861 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_862 = asUInt(reset) node _T_863 = eq(_T_862, UInt<1>(0h0)) when _T_863 : node _T_864 = eq(_T_861, UInt<1>(0h0)) when _T_864 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_861, UInt<1>(0h1), "") : assert_29 node _T_865 = eq(io.in.a.bits.mask, mask) node _T_866 = asUInt(reset) node _T_867 = eq(_T_866, UInt<1>(0h0)) when _T_867 : node _T_868 = eq(_T_865, UInt<1>(0h0)) when _T_868 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_865, UInt<1>(0h1), "") : assert_30 node _T_869 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_869 : node _T_870 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_871 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_872 = and(_T_870, _T_871) node _T_873 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_874 = shr(io.in.a.bits.source, 2) node _T_875 = eq(_T_874, UInt<1>(0h0)) node _T_876 = leq(UInt<1>(0h0), uncommonBits_28) node _T_877 = and(_T_875, _T_876) node _T_878 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_879 = and(_T_877, _T_878) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_880 = shr(io.in.a.bits.source, 2) node _T_881 = eq(_T_880, UInt<1>(0h1)) node _T_882 = leq(UInt<1>(0h0), uncommonBits_29) node _T_883 = and(_T_881, _T_882) node _T_884 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_885 = and(_T_883, _T_884) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_886 = shr(io.in.a.bits.source, 2) node _T_887 = eq(_T_886, UInt<2>(0h2)) node _T_888 = leq(UInt<1>(0h0), uncommonBits_30) node _T_889 = and(_T_887, _T_888) node _T_890 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_891 = and(_T_889, _T_890) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_892 = shr(io.in.a.bits.source, 2) node _T_893 = eq(_T_892, UInt<2>(0h3)) node _T_894 = leq(UInt<1>(0h0), uncommonBits_31) node _T_895 = and(_T_893, _T_894) node _T_896 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_897 = and(_T_895, _T_896) node _T_898 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_899 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_900 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_901 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_902 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_903 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_904 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_905 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_906 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_907 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_908 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_909 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_910 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_911 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_912 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_913 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_914 = or(_T_873, _T_879) node _T_915 = or(_T_914, _T_885) node _T_916 = or(_T_915, _T_891) node _T_917 = or(_T_916, _T_897) node _T_918 = or(_T_917, _T_898) node _T_919 = or(_T_918, _T_899) node _T_920 = or(_T_919, _T_900) node _T_921 = or(_T_920, _T_901) node _T_922 = or(_T_921, _T_902) node _T_923 = or(_T_922, _T_903) node _T_924 = or(_T_923, _T_904) node _T_925 = or(_T_924, _T_905) node _T_926 = or(_T_925, _T_906) node _T_927 = or(_T_926, _T_907) node _T_928 = or(_T_927, _T_908) node _T_929 = or(_T_928, _T_909) node _T_930 = or(_T_929, _T_910) node _T_931 = or(_T_930, _T_911) node _T_932 = or(_T_931, _T_912) node _T_933 = or(_T_932, _T_913) node _T_934 = and(_T_872, _T_933) node _T_935 = or(UInt<1>(0h0), _T_934) node _T_936 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_937 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_938 = and(_T_936, _T_937) node _T_939 = or(UInt<1>(0h0), _T_938) node _T_940 = xor(io.in.a.bits.address, UInt<28>(0h8000040)) node _T_941 = cvt(_T_940) node _T_942 = and(_T_941, asSInt(UInt<17>(0h100c0))) node _T_943 = asSInt(_T_942) node _T_944 = eq(_T_943, asSInt(UInt<1>(0h0))) node _T_945 = xor(io.in.a.bits.address, UInt<32>(0h80000040)) node _T_946 = cvt(_T_945) node _T_947 = and(_T_946, asSInt(UInt<29>(0h100000c0))) node _T_948 = asSInt(_T_947) node _T_949 = eq(_T_948, asSInt(UInt<1>(0h0))) node _T_950 = or(_T_944, _T_949) node _T_951 = and(_T_939, _T_950) node _T_952 = or(UInt<1>(0h0), _T_951) node _T_953 = and(_T_935, _T_952) node _T_954 = asUInt(reset) node _T_955 = eq(_T_954, UInt<1>(0h0)) when _T_955 : node _T_956 = eq(_T_953, UInt<1>(0h0)) when _T_956 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_953, UInt<1>(0h1), "") : assert_31 node _T_957 = asUInt(reset) node _T_958 = eq(_T_957, UInt<1>(0h0)) when _T_958 : node _T_959 = eq(source_ok, UInt<1>(0h0)) when _T_959 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_960 = asUInt(reset) node _T_961 = eq(_T_960, UInt<1>(0h0)) when _T_961 : node _T_962 = eq(is_aligned, UInt<1>(0h0)) when _T_962 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_963 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_964 = asUInt(reset) node _T_965 = eq(_T_964, UInt<1>(0h0)) when _T_965 : node _T_966 = eq(_T_963, UInt<1>(0h0)) when _T_966 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_963, UInt<1>(0h1), "") : assert_34 node _T_967 = not(mask) node _T_968 = and(io.in.a.bits.mask, _T_967) node _T_969 = eq(_T_968, UInt<1>(0h0)) node _T_970 = asUInt(reset) node _T_971 = eq(_T_970, UInt<1>(0h0)) when _T_971 : node _T_972 = eq(_T_969, UInt<1>(0h0)) when _T_972 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_969, UInt<1>(0h1), "") : assert_35 node _T_973 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_973 : node _T_974 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_975 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_976 = and(_T_974, _T_975) node _T_977 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_978 = shr(io.in.a.bits.source, 2) node _T_979 = eq(_T_978, UInt<1>(0h0)) node _T_980 = leq(UInt<1>(0h0), uncommonBits_32) node _T_981 = and(_T_979, _T_980) node _T_982 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_983 = and(_T_981, _T_982) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_984 = shr(io.in.a.bits.source, 2) node _T_985 = eq(_T_984, UInt<1>(0h1)) node _T_986 = leq(UInt<1>(0h0), uncommonBits_33) node _T_987 = and(_T_985, _T_986) node _T_988 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_989 = and(_T_987, _T_988) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_990 = shr(io.in.a.bits.source, 2) node _T_991 = eq(_T_990, UInt<2>(0h2)) node _T_992 = leq(UInt<1>(0h0), uncommonBits_34) node _T_993 = and(_T_991, _T_992) node _T_994 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_995 = and(_T_993, _T_994) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_996 = shr(io.in.a.bits.source, 2) node _T_997 = eq(_T_996, UInt<2>(0h3)) node _T_998 = leq(UInt<1>(0h0), uncommonBits_35) node _T_999 = and(_T_997, _T_998) node _T_1000 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_1001 = and(_T_999, _T_1000) node _T_1002 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1003 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1004 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1005 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1006 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1007 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1008 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1009 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1010 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1011 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1012 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1013 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1014 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1015 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1016 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1017 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1018 = or(_T_977, _T_983) node _T_1019 = or(_T_1018, _T_989) node _T_1020 = or(_T_1019, _T_995) node _T_1021 = or(_T_1020, _T_1001) node _T_1022 = or(_T_1021, _T_1002) node _T_1023 = or(_T_1022, _T_1003) node _T_1024 = or(_T_1023, _T_1004) node _T_1025 = or(_T_1024, _T_1005) node _T_1026 = or(_T_1025, _T_1006) node _T_1027 = or(_T_1026, _T_1007) node _T_1028 = or(_T_1027, _T_1008) node _T_1029 = or(_T_1028, _T_1009) node _T_1030 = or(_T_1029, _T_1010) node _T_1031 = or(_T_1030, _T_1011) node _T_1032 = or(_T_1031, _T_1012) node _T_1033 = or(_T_1032, _T_1013) node _T_1034 = or(_T_1033, _T_1014) node _T_1035 = or(_T_1034, _T_1015) node _T_1036 = or(_T_1035, _T_1016) node _T_1037 = or(_T_1036, _T_1017) node _T_1038 = and(_T_976, _T_1037) node _T_1039 = or(UInt<1>(0h0), _T_1038) node _T_1040 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1041 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1042 = and(_T_1040, _T_1041) node _T_1043 = or(UInt<1>(0h0), _T_1042) node _T_1044 = xor(io.in.a.bits.address, UInt<28>(0h8000040)) node _T_1045 = cvt(_T_1044) node _T_1046 = and(_T_1045, asSInt(UInt<17>(0h100c0))) node _T_1047 = asSInt(_T_1046) node _T_1048 = eq(_T_1047, asSInt(UInt<1>(0h0))) node _T_1049 = xor(io.in.a.bits.address, UInt<32>(0h80000040)) node _T_1050 = cvt(_T_1049) node _T_1051 = and(_T_1050, asSInt(UInt<29>(0h100000c0))) node _T_1052 = asSInt(_T_1051) node _T_1053 = eq(_T_1052, asSInt(UInt<1>(0h0))) node _T_1054 = or(_T_1048, _T_1053) node _T_1055 = and(_T_1043, _T_1054) node _T_1056 = or(UInt<1>(0h0), _T_1055) node _T_1057 = and(_T_1039, _T_1056) node _T_1058 = asUInt(reset) node _T_1059 = eq(_T_1058, UInt<1>(0h0)) when _T_1059 : node _T_1060 = eq(_T_1057, UInt<1>(0h0)) when _T_1060 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_1057, UInt<1>(0h1), "") : assert_36 node _T_1061 = asUInt(reset) node _T_1062 = eq(_T_1061, UInt<1>(0h0)) when _T_1062 : node _T_1063 = eq(source_ok, UInt<1>(0h0)) when _T_1063 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_1064 = asUInt(reset) node _T_1065 = eq(_T_1064, UInt<1>(0h0)) when _T_1065 : node _T_1066 = eq(is_aligned, UInt<1>(0h0)) when _T_1066 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_1067 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_1068 = asUInt(reset) node _T_1069 = eq(_T_1068, UInt<1>(0h0)) when _T_1069 : node _T_1070 = eq(_T_1067, UInt<1>(0h0)) when _T_1070 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_1067, UInt<1>(0h1), "") : assert_39 node _T_1071 = eq(io.in.a.bits.mask, mask) node _T_1072 = asUInt(reset) node _T_1073 = eq(_T_1072, UInt<1>(0h0)) when _T_1073 : node _T_1074 = eq(_T_1071, UInt<1>(0h0)) when _T_1074 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_1071, UInt<1>(0h1), "") : assert_40 node _T_1075 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_1075 : node _T_1076 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1077 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1078 = and(_T_1076, _T_1077) node _T_1079 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_1080 = shr(io.in.a.bits.source, 2) node _T_1081 = eq(_T_1080, UInt<1>(0h0)) node _T_1082 = leq(UInt<1>(0h0), uncommonBits_36) node _T_1083 = and(_T_1081, _T_1082) node _T_1084 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_1085 = and(_T_1083, _T_1084) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_1086 = shr(io.in.a.bits.source, 2) node _T_1087 = eq(_T_1086, UInt<1>(0h1)) node _T_1088 = leq(UInt<1>(0h0), uncommonBits_37) node _T_1089 = and(_T_1087, _T_1088) node _T_1090 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_1091 = and(_T_1089, _T_1090) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_1092 = shr(io.in.a.bits.source, 2) node _T_1093 = eq(_T_1092, UInt<2>(0h2)) node _T_1094 = leq(UInt<1>(0h0), uncommonBits_38) node _T_1095 = and(_T_1093, _T_1094) node _T_1096 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_1097 = and(_T_1095, _T_1096) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_1098 = shr(io.in.a.bits.source, 2) node _T_1099 = eq(_T_1098, UInt<2>(0h3)) node _T_1100 = leq(UInt<1>(0h0), uncommonBits_39) node _T_1101 = and(_T_1099, _T_1100) node _T_1102 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_1103 = and(_T_1101, _T_1102) node _T_1104 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1105 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1106 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1107 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1108 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1109 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1110 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1111 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1112 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1113 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1114 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1115 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1116 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1117 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1118 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1119 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1120 = or(_T_1079, _T_1085) node _T_1121 = or(_T_1120, _T_1091) node _T_1122 = or(_T_1121, _T_1097) node _T_1123 = or(_T_1122, _T_1103) node _T_1124 = or(_T_1123, _T_1104) node _T_1125 = or(_T_1124, _T_1105) node _T_1126 = or(_T_1125, _T_1106) node _T_1127 = or(_T_1126, _T_1107) node _T_1128 = or(_T_1127, _T_1108) node _T_1129 = or(_T_1128, _T_1109) node _T_1130 = or(_T_1129, _T_1110) node _T_1131 = or(_T_1130, _T_1111) node _T_1132 = or(_T_1131, _T_1112) node _T_1133 = or(_T_1132, _T_1113) node _T_1134 = or(_T_1133, _T_1114) node _T_1135 = or(_T_1134, _T_1115) node _T_1136 = or(_T_1135, _T_1116) node _T_1137 = or(_T_1136, _T_1117) node _T_1138 = or(_T_1137, _T_1118) node _T_1139 = or(_T_1138, _T_1119) node _T_1140 = and(_T_1078, _T_1139) node _T_1141 = or(UInt<1>(0h0), _T_1140) node _T_1142 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1143 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1144 = and(_T_1142, _T_1143) node _T_1145 = or(UInt<1>(0h0), _T_1144) node _T_1146 = xor(io.in.a.bits.address, UInt<28>(0h8000040)) node _T_1147 = cvt(_T_1146) node _T_1148 = and(_T_1147, asSInt(UInt<17>(0h100c0))) node _T_1149 = asSInt(_T_1148) node _T_1150 = eq(_T_1149, asSInt(UInt<1>(0h0))) node _T_1151 = xor(io.in.a.bits.address, UInt<32>(0h80000040)) node _T_1152 = cvt(_T_1151) node _T_1153 = and(_T_1152, asSInt(UInt<29>(0h100000c0))) node _T_1154 = asSInt(_T_1153) node _T_1155 = eq(_T_1154, asSInt(UInt<1>(0h0))) node _T_1156 = or(_T_1150, _T_1155) node _T_1157 = and(_T_1145, _T_1156) node _T_1158 = or(UInt<1>(0h0), _T_1157) node _T_1159 = and(_T_1141, _T_1158) node _T_1160 = asUInt(reset) node _T_1161 = eq(_T_1160, UInt<1>(0h0)) when _T_1161 : node _T_1162 = eq(_T_1159, UInt<1>(0h0)) when _T_1162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_1159, UInt<1>(0h1), "") : assert_41 node _T_1163 = asUInt(reset) node _T_1164 = eq(_T_1163, UInt<1>(0h0)) when _T_1164 : node _T_1165 = eq(source_ok, UInt<1>(0h0)) when _T_1165 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_1166 = asUInt(reset) node _T_1167 = eq(_T_1166, UInt<1>(0h0)) when _T_1167 : node _T_1168 = eq(is_aligned, UInt<1>(0h0)) when _T_1168 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_1169 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_1170 = asUInt(reset) node _T_1171 = eq(_T_1170, UInt<1>(0h0)) when _T_1171 : node _T_1172 = eq(_T_1169, UInt<1>(0h0)) when _T_1172 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_1169, UInt<1>(0h1), "") : assert_44 node _T_1173 = eq(io.in.a.bits.mask, mask) node _T_1174 = asUInt(reset) node _T_1175 = eq(_T_1174, UInt<1>(0h0)) when _T_1175 : node _T_1176 = eq(_T_1173, UInt<1>(0h0)) when _T_1176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_1173, UInt<1>(0h1), "") : assert_45 node _T_1177 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_1177 : node _T_1178 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1179 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1180 = and(_T_1178, _T_1179) node _T_1181 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_1182 = shr(io.in.a.bits.source, 2) node _T_1183 = eq(_T_1182, UInt<1>(0h0)) node _T_1184 = leq(UInt<1>(0h0), uncommonBits_40) node _T_1185 = and(_T_1183, _T_1184) node _T_1186 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_1187 = and(_T_1185, _T_1186) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_1188 = shr(io.in.a.bits.source, 2) node _T_1189 = eq(_T_1188, UInt<1>(0h1)) node _T_1190 = leq(UInt<1>(0h0), uncommonBits_41) node _T_1191 = and(_T_1189, _T_1190) node _T_1192 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_1193 = and(_T_1191, _T_1192) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_1194 = shr(io.in.a.bits.source, 2) node _T_1195 = eq(_T_1194, UInt<2>(0h2)) node _T_1196 = leq(UInt<1>(0h0), uncommonBits_42) node _T_1197 = and(_T_1195, _T_1196) node _T_1198 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_1199 = and(_T_1197, _T_1198) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_1200 = shr(io.in.a.bits.source, 2) node _T_1201 = eq(_T_1200, UInt<2>(0h3)) node _T_1202 = leq(UInt<1>(0h0), uncommonBits_43) node _T_1203 = and(_T_1201, _T_1202) node _T_1204 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_1205 = and(_T_1203, _T_1204) node _T_1206 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1207 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1208 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1209 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1210 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1211 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1212 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1213 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1214 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1215 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1216 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1217 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1218 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1219 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1220 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1221 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1222 = or(_T_1181, _T_1187) node _T_1223 = or(_T_1222, _T_1193) node _T_1224 = or(_T_1223, _T_1199) node _T_1225 = or(_T_1224, _T_1205) node _T_1226 = or(_T_1225, _T_1206) node _T_1227 = or(_T_1226, _T_1207) node _T_1228 = or(_T_1227, _T_1208) node _T_1229 = or(_T_1228, _T_1209) node _T_1230 = or(_T_1229, _T_1210) node _T_1231 = or(_T_1230, _T_1211) node _T_1232 = or(_T_1231, _T_1212) node _T_1233 = or(_T_1232, _T_1213) node _T_1234 = or(_T_1233, _T_1214) node _T_1235 = or(_T_1234, _T_1215) node _T_1236 = or(_T_1235, _T_1216) node _T_1237 = or(_T_1236, _T_1217) node _T_1238 = or(_T_1237, _T_1218) node _T_1239 = or(_T_1238, _T_1219) node _T_1240 = or(_T_1239, _T_1220) node _T_1241 = or(_T_1240, _T_1221) node _T_1242 = and(_T_1180, _T_1241) node _T_1243 = or(UInt<1>(0h0), _T_1242) node _T_1244 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1245 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1246 = and(_T_1244, _T_1245) node _T_1247 = or(UInt<1>(0h0), _T_1246) node _T_1248 = xor(io.in.a.bits.address, UInt<28>(0h8000040)) node _T_1249 = cvt(_T_1248) node _T_1250 = and(_T_1249, asSInt(UInt<17>(0h100c0))) node _T_1251 = asSInt(_T_1250) node _T_1252 = eq(_T_1251, asSInt(UInt<1>(0h0))) node _T_1253 = xor(io.in.a.bits.address, UInt<32>(0h80000040)) node _T_1254 = cvt(_T_1253) node _T_1255 = and(_T_1254, asSInt(UInt<29>(0h100000c0))) node _T_1256 = asSInt(_T_1255) node _T_1257 = eq(_T_1256, asSInt(UInt<1>(0h0))) node _T_1258 = or(_T_1252, _T_1257) node _T_1259 = and(_T_1247, _T_1258) node _T_1260 = or(UInt<1>(0h0), _T_1259) node _T_1261 = and(_T_1243, _T_1260) node _T_1262 = asUInt(reset) node _T_1263 = eq(_T_1262, UInt<1>(0h0)) when _T_1263 : node _T_1264 = eq(_T_1261, UInt<1>(0h0)) when _T_1264 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1261, UInt<1>(0h1), "") : assert_46 node _T_1265 = asUInt(reset) node _T_1266 = eq(_T_1265, UInt<1>(0h0)) when _T_1266 : node _T_1267 = eq(source_ok, UInt<1>(0h0)) when _T_1267 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1268 = asUInt(reset) node _T_1269 = eq(_T_1268, UInt<1>(0h0)) when _T_1269 : node _T_1270 = eq(is_aligned, UInt<1>(0h0)) when _T_1270 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1271 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1272 = asUInt(reset) node _T_1273 = eq(_T_1272, UInt<1>(0h0)) when _T_1273 : node _T_1274 = eq(_T_1271, UInt<1>(0h0)) when _T_1274 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1271, UInt<1>(0h1), "") : assert_49 node _T_1275 = eq(io.in.a.bits.mask, mask) node _T_1276 = asUInt(reset) node _T_1277 = eq(_T_1276, UInt<1>(0h0)) when _T_1277 : node _T_1278 = eq(_T_1275, UInt<1>(0h0)) when _T_1278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1275, UInt<1>(0h1), "") : assert_50 node _T_1279 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1280 = asUInt(reset) node _T_1281 = eq(_T_1280, UInt<1>(0h0)) when _T_1281 : node _T_1282 = eq(_T_1279, UInt<1>(0h0)) when _T_1282 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1279, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1283 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1284 = asUInt(reset) node _T_1285 = eq(_T_1284, UInt<1>(0h0)) when _T_1285 : node _T_1286 = eq(_T_1283, UInt<1>(0h0)) when _T_1286 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1283, UInt<1>(0h1), "") : assert_52 node _source_ok_T_60 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_61 = shr(io.in.d.bits.source, 2) node _source_ok_T_62 = eq(_source_ok_T_61, UInt<1>(0h0)) node _source_ok_T_63 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_64 = and(_source_ok_T_62, _source_ok_T_63) node _source_ok_T_65 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_66 = and(_source_ok_T_64, _source_ok_T_65) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_67 = shr(io.in.d.bits.source, 2) node _source_ok_T_68 = eq(_source_ok_T_67, UInt<1>(0h1)) node _source_ok_T_69 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_70 = and(_source_ok_T_68, _source_ok_T_69) node _source_ok_T_71 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_72 = and(_source_ok_T_70, _source_ok_T_71) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_73 = shr(io.in.d.bits.source, 2) node _source_ok_T_74 = eq(_source_ok_T_73, UInt<2>(0h2)) node _source_ok_T_75 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_76 = and(_source_ok_T_74, _source_ok_T_75) node _source_ok_T_77 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_78 = and(_source_ok_T_76, _source_ok_T_77) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_79 = shr(io.in.d.bits.source, 2) node _source_ok_T_80 = eq(_source_ok_T_79, UInt<2>(0h3)) node _source_ok_T_81 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_82 = and(_source_ok_T_80, _source_ok_T_81) node _source_ok_T_83 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_84 = and(_source_ok_T_82, _source_ok_T_83) node _source_ok_T_85 = eq(io.in.d.bits.source, UInt<6>(0h3c)) node _source_ok_T_86 = eq(io.in.d.bits.source, UInt<6>(0h3e)) node _source_ok_T_87 = eq(io.in.d.bits.source, UInt<6>(0h38)) node _source_ok_T_88 = eq(io.in.d.bits.source, UInt<6>(0h3a)) node _source_ok_T_89 = eq(io.in.d.bits.source, UInt<6>(0h34)) node _source_ok_T_90 = eq(io.in.d.bits.source, UInt<6>(0h36)) node _source_ok_T_91 = eq(io.in.d.bits.source, UInt<6>(0h30)) node _source_ok_T_92 = eq(io.in.d.bits.source, UInt<6>(0h32)) node _source_ok_T_93 = eq(io.in.d.bits.source, UInt<6>(0h2c)) node _source_ok_T_94 = eq(io.in.d.bits.source, UInt<6>(0h2e)) node _source_ok_T_95 = eq(io.in.d.bits.source, UInt<6>(0h28)) node _source_ok_T_96 = eq(io.in.d.bits.source, UInt<6>(0h2a)) node _source_ok_T_97 = eq(io.in.d.bits.source, UInt<6>(0h24)) node _source_ok_T_98 = eq(io.in.d.bits.source, UInt<6>(0h26)) node _source_ok_T_99 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_100 = eq(io.in.d.bits.source, UInt<6>(0h22)) wire _source_ok_WIRE_1 : UInt<1>[21] connect _source_ok_WIRE_1[0], _source_ok_T_60 connect _source_ok_WIRE_1[1], _source_ok_T_66 connect _source_ok_WIRE_1[2], _source_ok_T_72 connect _source_ok_WIRE_1[3], _source_ok_T_78 connect _source_ok_WIRE_1[4], _source_ok_T_84 connect _source_ok_WIRE_1[5], _source_ok_T_85 connect _source_ok_WIRE_1[6], _source_ok_T_86 connect _source_ok_WIRE_1[7], _source_ok_T_87 connect _source_ok_WIRE_1[8], _source_ok_T_88 connect _source_ok_WIRE_1[9], _source_ok_T_89 connect _source_ok_WIRE_1[10], _source_ok_T_90 connect _source_ok_WIRE_1[11], _source_ok_T_91 connect _source_ok_WIRE_1[12], _source_ok_T_92 connect _source_ok_WIRE_1[13], _source_ok_T_93 connect _source_ok_WIRE_1[14], _source_ok_T_94 connect _source_ok_WIRE_1[15], _source_ok_T_95 connect _source_ok_WIRE_1[16], _source_ok_T_96 connect _source_ok_WIRE_1[17], _source_ok_T_97 connect _source_ok_WIRE_1[18], _source_ok_T_98 connect _source_ok_WIRE_1[19], _source_ok_T_99 connect _source_ok_WIRE_1[20], _source_ok_T_100 node _source_ok_T_101 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_102 = or(_source_ok_T_101, _source_ok_WIRE_1[2]) node _source_ok_T_103 = or(_source_ok_T_102, _source_ok_WIRE_1[3]) node _source_ok_T_104 = or(_source_ok_T_103, _source_ok_WIRE_1[4]) node _source_ok_T_105 = or(_source_ok_T_104, _source_ok_WIRE_1[5]) node _source_ok_T_106 = or(_source_ok_T_105, _source_ok_WIRE_1[6]) node _source_ok_T_107 = or(_source_ok_T_106, _source_ok_WIRE_1[7]) node _source_ok_T_108 = or(_source_ok_T_107, _source_ok_WIRE_1[8]) node _source_ok_T_109 = or(_source_ok_T_108, _source_ok_WIRE_1[9]) node _source_ok_T_110 = or(_source_ok_T_109, _source_ok_WIRE_1[10]) node _source_ok_T_111 = or(_source_ok_T_110, _source_ok_WIRE_1[11]) node _source_ok_T_112 = or(_source_ok_T_111, _source_ok_WIRE_1[12]) node _source_ok_T_113 = or(_source_ok_T_112, _source_ok_WIRE_1[13]) node _source_ok_T_114 = or(_source_ok_T_113, _source_ok_WIRE_1[14]) node _source_ok_T_115 = or(_source_ok_T_114, _source_ok_WIRE_1[15]) node _source_ok_T_116 = or(_source_ok_T_115, _source_ok_WIRE_1[16]) node _source_ok_T_117 = or(_source_ok_T_116, _source_ok_WIRE_1[17]) node _source_ok_T_118 = or(_source_ok_T_117, _source_ok_WIRE_1[18]) node _source_ok_T_119 = or(_source_ok_T_118, _source_ok_WIRE_1[19]) node source_ok_1 = or(_source_ok_T_119, _source_ok_WIRE_1[20]) node sink_ok = lt(io.in.d.bits.sink, UInt<3>(0h7)) node _T_1287 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1287 : node _T_1288 = asUInt(reset) node _T_1289 = eq(_T_1288, UInt<1>(0h0)) when _T_1289 : node _T_1290 = eq(source_ok_1, UInt<1>(0h0)) when _T_1290 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1291 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1292 = asUInt(reset) node _T_1293 = eq(_T_1292, UInt<1>(0h0)) when _T_1293 : node _T_1294 = eq(_T_1291, UInt<1>(0h0)) when _T_1294 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1291, UInt<1>(0h1), "") : assert_54 node _T_1295 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1296 = asUInt(reset) node _T_1297 = eq(_T_1296, UInt<1>(0h0)) when _T_1297 : node _T_1298 = eq(_T_1295, UInt<1>(0h0)) when _T_1298 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1295, UInt<1>(0h1), "") : assert_55 node _T_1299 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1300 = asUInt(reset) node _T_1301 = eq(_T_1300, UInt<1>(0h0)) when _T_1301 : node _T_1302 = eq(_T_1299, UInt<1>(0h0)) when _T_1302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1299, UInt<1>(0h1), "") : assert_56 node _T_1303 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1304 = asUInt(reset) node _T_1305 = eq(_T_1304, UInt<1>(0h0)) when _T_1305 : node _T_1306 = eq(_T_1303, UInt<1>(0h0)) when _T_1306 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1303, UInt<1>(0h1), "") : assert_57 node _T_1307 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1307 : node _T_1308 = asUInt(reset) node _T_1309 = eq(_T_1308, UInt<1>(0h0)) when _T_1309 : node _T_1310 = eq(source_ok_1, UInt<1>(0h0)) when _T_1310 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1311 = asUInt(reset) node _T_1312 = eq(_T_1311, UInt<1>(0h0)) when _T_1312 : node _T_1313 = eq(sink_ok, UInt<1>(0h0)) when _T_1313 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1314 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1315 = asUInt(reset) node _T_1316 = eq(_T_1315, UInt<1>(0h0)) when _T_1316 : node _T_1317 = eq(_T_1314, UInt<1>(0h0)) when _T_1317 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1314, UInt<1>(0h1), "") : assert_60 node _T_1318 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1319 = asUInt(reset) node _T_1320 = eq(_T_1319, UInt<1>(0h0)) when _T_1320 : node _T_1321 = eq(_T_1318, UInt<1>(0h0)) when _T_1321 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1318, UInt<1>(0h1), "") : assert_61 node _T_1322 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1323 = asUInt(reset) node _T_1324 = eq(_T_1323, UInt<1>(0h0)) when _T_1324 : node _T_1325 = eq(_T_1322, UInt<1>(0h0)) when _T_1325 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1322, UInt<1>(0h1), "") : assert_62 node _T_1326 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1327 = asUInt(reset) node _T_1328 = eq(_T_1327, UInt<1>(0h0)) when _T_1328 : node _T_1329 = eq(_T_1326, UInt<1>(0h0)) when _T_1329 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1326, UInt<1>(0h1), "") : assert_63 node _T_1330 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1331 = or(UInt<1>(0h1), _T_1330) node _T_1332 = asUInt(reset) node _T_1333 = eq(_T_1332, UInt<1>(0h0)) when _T_1333 : node _T_1334 = eq(_T_1331, UInt<1>(0h0)) when _T_1334 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1331, UInt<1>(0h1), "") : assert_64 node _T_1335 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1335 : node _T_1336 = asUInt(reset) node _T_1337 = eq(_T_1336, UInt<1>(0h0)) when _T_1337 : node _T_1338 = eq(source_ok_1, UInt<1>(0h0)) when _T_1338 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1339 = asUInt(reset) node _T_1340 = eq(_T_1339, UInt<1>(0h0)) when _T_1340 : node _T_1341 = eq(sink_ok, UInt<1>(0h0)) when _T_1341 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1342 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1343 = asUInt(reset) node _T_1344 = eq(_T_1343, UInt<1>(0h0)) when _T_1344 : node _T_1345 = eq(_T_1342, UInt<1>(0h0)) when _T_1345 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1342, UInt<1>(0h1), "") : assert_67 node _T_1346 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1347 = asUInt(reset) node _T_1348 = eq(_T_1347, UInt<1>(0h0)) when _T_1348 : node _T_1349 = eq(_T_1346, UInt<1>(0h0)) when _T_1349 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1346, UInt<1>(0h1), "") : assert_68 node _T_1350 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1351 = asUInt(reset) node _T_1352 = eq(_T_1351, UInt<1>(0h0)) when _T_1352 : node _T_1353 = eq(_T_1350, UInt<1>(0h0)) when _T_1353 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1350, UInt<1>(0h1), "") : assert_69 node _T_1354 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1355 = or(_T_1354, io.in.d.bits.corrupt) node _T_1356 = asUInt(reset) node _T_1357 = eq(_T_1356, UInt<1>(0h0)) when _T_1357 : node _T_1358 = eq(_T_1355, UInt<1>(0h0)) when _T_1358 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1355, UInt<1>(0h1), "") : assert_70 node _T_1359 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1360 = or(UInt<1>(0h1), _T_1359) node _T_1361 = asUInt(reset) node _T_1362 = eq(_T_1361, UInt<1>(0h0)) when _T_1362 : node _T_1363 = eq(_T_1360, UInt<1>(0h0)) when _T_1363 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1360, UInt<1>(0h1), "") : assert_71 node _T_1364 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1364 : node _T_1365 = asUInt(reset) node _T_1366 = eq(_T_1365, UInt<1>(0h0)) when _T_1366 : node _T_1367 = eq(source_ok_1, UInt<1>(0h0)) when _T_1367 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1368 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1369 = asUInt(reset) node _T_1370 = eq(_T_1369, UInt<1>(0h0)) when _T_1370 : node _T_1371 = eq(_T_1368, UInt<1>(0h0)) when _T_1371 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1368, UInt<1>(0h1), "") : assert_73 node _T_1372 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1373 = asUInt(reset) node _T_1374 = eq(_T_1373, UInt<1>(0h0)) when _T_1374 : node _T_1375 = eq(_T_1372, UInt<1>(0h0)) when _T_1375 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1372, UInt<1>(0h1), "") : assert_74 node _T_1376 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1377 = or(UInt<1>(0h1), _T_1376) node _T_1378 = asUInt(reset) node _T_1379 = eq(_T_1378, UInt<1>(0h0)) when _T_1379 : node _T_1380 = eq(_T_1377, UInt<1>(0h0)) when _T_1380 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1377, UInt<1>(0h1), "") : assert_75 node _T_1381 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1381 : node _T_1382 = asUInt(reset) node _T_1383 = eq(_T_1382, UInt<1>(0h0)) when _T_1383 : node _T_1384 = eq(source_ok_1, UInt<1>(0h0)) when _T_1384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1385 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1386 = asUInt(reset) node _T_1387 = eq(_T_1386, UInt<1>(0h0)) when _T_1387 : node _T_1388 = eq(_T_1385, UInt<1>(0h0)) when _T_1388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1385, UInt<1>(0h1), "") : assert_77 node _T_1389 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1390 = or(_T_1389, io.in.d.bits.corrupt) node _T_1391 = asUInt(reset) node _T_1392 = eq(_T_1391, UInt<1>(0h0)) when _T_1392 : node _T_1393 = eq(_T_1390, UInt<1>(0h0)) when _T_1393 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1390, UInt<1>(0h1), "") : assert_78 node _T_1394 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1395 = or(UInt<1>(0h1), _T_1394) node _T_1396 = asUInt(reset) node _T_1397 = eq(_T_1396, UInt<1>(0h0)) when _T_1397 : node _T_1398 = eq(_T_1395, UInt<1>(0h0)) when _T_1398 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1395, UInt<1>(0h1), "") : assert_79 node _T_1399 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1399 : node _T_1400 = asUInt(reset) node _T_1401 = eq(_T_1400, UInt<1>(0h0)) when _T_1401 : node _T_1402 = eq(source_ok_1, UInt<1>(0h0)) when _T_1402 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1403 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1404 = asUInt(reset) node _T_1405 = eq(_T_1404, UInt<1>(0h0)) when _T_1405 : node _T_1406 = eq(_T_1403, UInt<1>(0h0)) when _T_1406 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1403, UInt<1>(0h1), "") : assert_81 node _T_1407 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1408 = asUInt(reset) node _T_1409 = eq(_T_1408, UInt<1>(0h0)) when _T_1409 : node _T_1410 = eq(_T_1407, UInt<1>(0h0)) when _T_1410 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1407, UInt<1>(0h1), "") : assert_82 node _T_1411 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1412 = or(UInt<1>(0h1), _T_1411) node _T_1413 = asUInt(reset) node _T_1414 = eq(_T_1413, UInt<1>(0h0)) when _T_1414 : node _T_1415 = eq(_T_1412, UInt<1>(0h0)) when _T_1415 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1412, UInt<1>(0h1), "") : assert_83 when io.in.b.valid : node _T_1416 = leq(io.in.b.bits.opcode, UInt<3>(0h6)) node _T_1417 = asUInt(reset) node _T_1418 = eq(_T_1417, UInt<1>(0h0)) when _T_1418 : node _T_1419 = eq(_T_1416, UInt<1>(0h0)) when _T_1419 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1416, UInt<1>(0h1), "") : assert_84 node _T_1420 = eq(io.in.b.bits.source, UInt<5>(0h10)) node _T_1421 = eq(_T_1420, UInt<1>(0h0)) node _T_1422 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1423 = cvt(_T_1422) node _T_1424 = and(_T_1423, asSInt(UInt<1>(0h0))) node _T_1425 = asSInt(_T_1424) node _T_1426 = eq(_T_1425, asSInt(UInt<1>(0h0))) node _T_1427 = or(_T_1421, _T_1426) node _uncommonBits_T_44 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_44 = bits(_uncommonBits_T_44, 1, 0) node _T_1428 = shr(io.in.b.bits.source, 2) node _T_1429 = eq(_T_1428, UInt<1>(0h0)) node _T_1430 = leq(UInt<1>(0h0), uncommonBits_44) node _T_1431 = and(_T_1429, _T_1430) node _T_1432 = leq(uncommonBits_44, UInt<2>(0h3)) node _T_1433 = and(_T_1431, _T_1432) node _T_1434 = eq(_T_1433, UInt<1>(0h0)) node _T_1435 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1436 = cvt(_T_1435) node _T_1437 = and(_T_1436, asSInt(UInt<1>(0h0))) node _T_1438 = asSInt(_T_1437) node _T_1439 = eq(_T_1438, asSInt(UInt<1>(0h0))) node _T_1440 = or(_T_1434, _T_1439) node _uncommonBits_T_45 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0) node _T_1441 = shr(io.in.b.bits.source, 2) node _T_1442 = eq(_T_1441, UInt<1>(0h1)) node _T_1443 = leq(UInt<1>(0h0), uncommonBits_45) node _T_1444 = and(_T_1442, _T_1443) node _T_1445 = leq(uncommonBits_45, UInt<2>(0h3)) node _T_1446 = and(_T_1444, _T_1445) node _T_1447 = eq(_T_1446, UInt<1>(0h0)) node _T_1448 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1449 = cvt(_T_1448) node _T_1450 = and(_T_1449, asSInt(UInt<1>(0h0))) node _T_1451 = asSInt(_T_1450) node _T_1452 = eq(_T_1451, asSInt(UInt<1>(0h0))) node _T_1453 = or(_T_1447, _T_1452) node _uncommonBits_T_46 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_46 = bits(_uncommonBits_T_46, 1, 0) node _T_1454 = shr(io.in.b.bits.source, 2) node _T_1455 = eq(_T_1454, UInt<2>(0h2)) node _T_1456 = leq(UInt<1>(0h0), uncommonBits_46) node _T_1457 = and(_T_1455, _T_1456) node _T_1458 = leq(uncommonBits_46, UInt<2>(0h3)) node _T_1459 = and(_T_1457, _T_1458) node _T_1460 = eq(_T_1459, UInt<1>(0h0)) node _T_1461 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1462 = cvt(_T_1461) node _T_1463 = and(_T_1462, asSInt(UInt<1>(0h0))) node _T_1464 = asSInt(_T_1463) node _T_1465 = eq(_T_1464, asSInt(UInt<1>(0h0))) node _T_1466 = or(_T_1460, _T_1465) node _uncommonBits_T_47 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_47 = bits(_uncommonBits_T_47, 1, 0) node _T_1467 = shr(io.in.b.bits.source, 2) node _T_1468 = eq(_T_1467, UInt<2>(0h3)) node _T_1469 = leq(UInt<1>(0h0), uncommonBits_47) node _T_1470 = and(_T_1468, _T_1469) node _T_1471 = leq(uncommonBits_47, UInt<2>(0h3)) node _T_1472 = and(_T_1470, _T_1471) node _T_1473 = eq(_T_1472, UInt<1>(0h0)) node _T_1474 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1475 = cvt(_T_1474) node _T_1476 = and(_T_1475, asSInt(UInt<1>(0h0))) node _T_1477 = asSInt(_T_1476) node _T_1478 = eq(_T_1477, asSInt(UInt<1>(0h0))) node _T_1479 = or(_T_1473, _T_1478) node _T_1480 = eq(io.in.b.bits.source, UInt<6>(0h3c)) node _T_1481 = eq(_T_1480, UInt<1>(0h0)) node _T_1482 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1483 = cvt(_T_1482) node _T_1484 = and(_T_1483, asSInt(UInt<1>(0h0))) node _T_1485 = asSInt(_T_1484) node _T_1486 = eq(_T_1485, asSInt(UInt<1>(0h0))) node _T_1487 = or(_T_1481, _T_1486) node _T_1488 = eq(io.in.b.bits.source, UInt<6>(0h3e)) node _T_1489 = eq(_T_1488, UInt<1>(0h0)) node _T_1490 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1491 = cvt(_T_1490) node _T_1492 = and(_T_1491, asSInt(UInt<1>(0h0))) node _T_1493 = asSInt(_T_1492) node _T_1494 = eq(_T_1493, asSInt(UInt<1>(0h0))) node _T_1495 = or(_T_1489, _T_1494) node _T_1496 = eq(io.in.b.bits.source, UInt<6>(0h38)) node _T_1497 = eq(_T_1496, UInt<1>(0h0)) node _T_1498 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1499 = cvt(_T_1498) node _T_1500 = and(_T_1499, asSInt(UInt<1>(0h0))) node _T_1501 = asSInt(_T_1500) node _T_1502 = eq(_T_1501, asSInt(UInt<1>(0h0))) node _T_1503 = or(_T_1497, _T_1502) node _T_1504 = eq(io.in.b.bits.source, UInt<6>(0h3a)) node _T_1505 = eq(_T_1504, UInt<1>(0h0)) node _T_1506 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1507 = cvt(_T_1506) node _T_1508 = and(_T_1507, asSInt(UInt<1>(0h0))) node _T_1509 = asSInt(_T_1508) node _T_1510 = eq(_T_1509, asSInt(UInt<1>(0h0))) node _T_1511 = or(_T_1505, _T_1510) node _T_1512 = eq(io.in.b.bits.source, UInt<6>(0h34)) node _T_1513 = eq(_T_1512, UInt<1>(0h0)) node _T_1514 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1515 = cvt(_T_1514) node _T_1516 = and(_T_1515, asSInt(UInt<1>(0h0))) node _T_1517 = asSInt(_T_1516) node _T_1518 = eq(_T_1517, asSInt(UInt<1>(0h0))) node _T_1519 = or(_T_1513, _T_1518) node _T_1520 = eq(io.in.b.bits.source, UInt<6>(0h36)) node _T_1521 = eq(_T_1520, UInt<1>(0h0)) node _T_1522 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1523 = cvt(_T_1522) node _T_1524 = and(_T_1523, asSInt(UInt<1>(0h0))) node _T_1525 = asSInt(_T_1524) node _T_1526 = eq(_T_1525, asSInt(UInt<1>(0h0))) node _T_1527 = or(_T_1521, _T_1526) node _T_1528 = eq(io.in.b.bits.source, UInt<6>(0h30)) node _T_1529 = eq(_T_1528, UInt<1>(0h0)) node _T_1530 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1531 = cvt(_T_1530) node _T_1532 = and(_T_1531, asSInt(UInt<1>(0h0))) node _T_1533 = asSInt(_T_1532) node _T_1534 = eq(_T_1533, asSInt(UInt<1>(0h0))) node _T_1535 = or(_T_1529, _T_1534) node _T_1536 = eq(io.in.b.bits.source, UInt<6>(0h32)) node _T_1537 = eq(_T_1536, UInt<1>(0h0)) node _T_1538 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1539 = cvt(_T_1538) node _T_1540 = and(_T_1539, asSInt(UInt<1>(0h0))) node _T_1541 = asSInt(_T_1540) node _T_1542 = eq(_T_1541, asSInt(UInt<1>(0h0))) node _T_1543 = or(_T_1537, _T_1542) node _T_1544 = eq(io.in.b.bits.source, UInt<6>(0h2c)) node _T_1545 = eq(_T_1544, UInt<1>(0h0)) node _T_1546 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1547 = cvt(_T_1546) node _T_1548 = and(_T_1547, asSInt(UInt<1>(0h0))) node _T_1549 = asSInt(_T_1548) node _T_1550 = eq(_T_1549, asSInt(UInt<1>(0h0))) node _T_1551 = or(_T_1545, _T_1550) node _T_1552 = eq(io.in.b.bits.source, UInt<6>(0h2e)) node _T_1553 = eq(_T_1552, UInt<1>(0h0)) node _T_1554 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1555 = cvt(_T_1554) node _T_1556 = and(_T_1555, asSInt(UInt<1>(0h0))) node _T_1557 = asSInt(_T_1556) node _T_1558 = eq(_T_1557, asSInt(UInt<1>(0h0))) node _T_1559 = or(_T_1553, _T_1558) node _T_1560 = eq(io.in.b.bits.source, UInt<6>(0h28)) node _T_1561 = eq(_T_1560, UInt<1>(0h0)) node _T_1562 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1563 = cvt(_T_1562) node _T_1564 = and(_T_1563, asSInt(UInt<1>(0h0))) node _T_1565 = asSInt(_T_1564) node _T_1566 = eq(_T_1565, asSInt(UInt<1>(0h0))) node _T_1567 = or(_T_1561, _T_1566) node _T_1568 = eq(io.in.b.bits.source, UInt<6>(0h2a)) node _T_1569 = eq(_T_1568, UInt<1>(0h0)) node _T_1570 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1571 = cvt(_T_1570) node _T_1572 = and(_T_1571, asSInt(UInt<1>(0h0))) node _T_1573 = asSInt(_T_1572) node _T_1574 = eq(_T_1573, asSInt(UInt<1>(0h0))) node _T_1575 = or(_T_1569, _T_1574) node _T_1576 = eq(io.in.b.bits.source, UInt<6>(0h24)) node _T_1577 = eq(_T_1576, UInt<1>(0h0)) node _T_1578 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1579 = cvt(_T_1578) node _T_1580 = and(_T_1579, asSInt(UInt<1>(0h0))) node _T_1581 = asSInt(_T_1580) node _T_1582 = eq(_T_1581, asSInt(UInt<1>(0h0))) node _T_1583 = or(_T_1577, _T_1582) node _T_1584 = eq(io.in.b.bits.source, UInt<6>(0h26)) node _T_1585 = eq(_T_1584, UInt<1>(0h0)) node _T_1586 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1587 = cvt(_T_1586) node _T_1588 = and(_T_1587, asSInt(UInt<1>(0h0))) node _T_1589 = asSInt(_T_1588) node _T_1590 = eq(_T_1589, asSInt(UInt<1>(0h0))) node _T_1591 = or(_T_1585, _T_1590) node _T_1592 = eq(io.in.b.bits.source, UInt<6>(0h20)) node _T_1593 = eq(_T_1592, UInt<1>(0h0)) node _T_1594 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1595 = cvt(_T_1594) node _T_1596 = and(_T_1595, asSInt(UInt<1>(0h0))) node _T_1597 = asSInt(_T_1596) node _T_1598 = eq(_T_1597, asSInt(UInt<1>(0h0))) node _T_1599 = or(_T_1593, _T_1598) node _T_1600 = eq(io.in.b.bits.source, UInt<6>(0h22)) node _T_1601 = eq(_T_1600, UInt<1>(0h0)) node _T_1602 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1603 = cvt(_T_1602) node _T_1604 = and(_T_1603, asSInt(UInt<1>(0h0))) node _T_1605 = asSInt(_T_1604) node _T_1606 = eq(_T_1605, asSInt(UInt<1>(0h0))) node _T_1607 = or(_T_1601, _T_1606) node _T_1608 = and(_T_1427, _T_1440) node _T_1609 = and(_T_1608, _T_1453) node _T_1610 = and(_T_1609, _T_1466) node _T_1611 = and(_T_1610, _T_1479) node _T_1612 = and(_T_1611, _T_1487) node _T_1613 = and(_T_1612, _T_1495) node _T_1614 = and(_T_1613, _T_1503) node _T_1615 = and(_T_1614, _T_1511) node _T_1616 = and(_T_1615, _T_1519) node _T_1617 = and(_T_1616, _T_1527) node _T_1618 = and(_T_1617, _T_1535) node _T_1619 = and(_T_1618, _T_1543) node _T_1620 = and(_T_1619, _T_1551) node _T_1621 = and(_T_1620, _T_1559) node _T_1622 = and(_T_1621, _T_1567) node _T_1623 = and(_T_1622, _T_1575) node _T_1624 = and(_T_1623, _T_1583) node _T_1625 = and(_T_1624, _T_1591) node _T_1626 = and(_T_1625, _T_1599) node _T_1627 = and(_T_1626, _T_1607) node _T_1628 = asUInt(reset) node _T_1629 = eq(_T_1628, UInt<1>(0h0)) when _T_1629 : node _T_1630 = eq(_T_1627, UInt<1>(0h0)) when _T_1630 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1627, UInt<1>(0h1), "") : assert_85 node _address_ok_T = xor(io.in.b.bits.address, UInt<28>(0h8000040)) node _address_ok_T_1 = cvt(_address_ok_T) node _address_ok_T_2 = and(_address_ok_T_1, asSInt(UInt<17>(0h100c0))) node _address_ok_T_3 = asSInt(_address_ok_T_2) node _address_ok_T_4 = eq(_address_ok_T_3, asSInt(UInt<1>(0h0))) node _address_ok_T_5 = xor(io.in.b.bits.address, UInt<32>(0h80000040)) node _address_ok_T_6 = cvt(_address_ok_T_5) node _address_ok_T_7 = and(_address_ok_T_6, asSInt(UInt<29>(0h100000c0))) node _address_ok_T_8 = asSInt(_address_ok_T_7) node _address_ok_T_9 = eq(_address_ok_T_8, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE : UInt<1>[2] connect _address_ok_WIRE[0], _address_ok_T_4 connect _address_ok_WIRE[1], _address_ok_T_9 node address_ok = or(_address_ok_WIRE[0], _address_ok_WIRE[1]) node _is_aligned_mask_T_2 = dshl(UInt<6>(0h3f), io.in.b.bits.size) node _is_aligned_mask_T_3 = bits(_is_aligned_mask_T_2, 5, 0) node is_aligned_mask_1 = not(_is_aligned_mask_T_3) node _is_aligned_T_1 = and(io.in.b.bits.address, is_aligned_mask_1) node is_aligned_1 = eq(_is_aligned_T_1, UInt<1>(0h0)) node _mask_sizeOH_T_3 = or(io.in.b.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount_1 = bits(_mask_sizeOH_T_3, 1, 0) node _mask_sizeOH_T_4 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount_1) node _mask_sizeOH_T_5 = bits(_mask_sizeOH_T_4, 2, 0) node mask_sizeOH_1 = or(_mask_sizeOH_T_5, UInt<1>(0h1)) node mask_sub_sub_sub_0_1_1 = geq(io.in.b.bits.size, UInt<2>(0h3)) node mask_sub_sub_size_1 = bits(mask_sizeOH_1, 2, 2) node mask_sub_sub_bit_1 = bits(io.in.b.bits.address, 2, 2) node mask_sub_sub_nbit_1 = eq(mask_sub_sub_bit_1, UInt<1>(0h0)) node mask_sub_sub_0_2_1 = and(UInt<1>(0h1), mask_sub_sub_nbit_1) node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size_1, mask_sub_sub_0_2_1) node mask_sub_sub_0_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_2) node mask_sub_sub_1_2_1 = and(UInt<1>(0h1), mask_sub_sub_bit_1) node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size_1, mask_sub_sub_1_2_1) node mask_sub_sub_1_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_3) node mask_sub_size_1 = bits(mask_sizeOH_1, 1, 1) node mask_sub_bit_1 = bits(io.in.b.bits.address, 1, 1) node mask_sub_nbit_1 = eq(mask_sub_bit_1, UInt<1>(0h0)) node mask_sub_0_2_1 = and(mask_sub_sub_0_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_4 = and(mask_sub_size_1, mask_sub_0_2_1) node mask_sub_0_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_4) node mask_sub_1_2_1 = and(mask_sub_sub_0_2_1, mask_sub_bit_1) node _mask_sub_acc_T_5 = and(mask_sub_size_1, mask_sub_1_2_1) node mask_sub_1_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_5) node mask_sub_2_2_1 = and(mask_sub_sub_1_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_6 = and(mask_sub_size_1, mask_sub_2_2_1) node mask_sub_2_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_6) node mask_sub_3_2_1 = and(mask_sub_sub_1_2_1, mask_sub_bit_1) node _mask_sub_acc_T_7 = and(mask_sub_size_1, mask_sub_3_2_1) node mask_sub_3_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_7) node mask_size_1 = bits(mask_sizeOH_1, 0, 0) node mask_bit_1 = bits(io.in.b.bits.address, 0, 0) node mask_nbit_1 = eq(mask_bit_1, UInt<1>(0h0)) node mask_eq_8 = and(mask_sub_0_2_1, mask_nbit_1) node _mask_acc_T_8 = and(mask_size_1, mask_eq_8) node mask_acc_8 = or(mask_sub_0_1_1, _mask_acc_T_8) node mask_eq_9 = and(mask_sub_0_2_1, mask_bit_1) node _mask_acc_T_9 = and(mask_size_1, mask_eq_9) node mask_acc_9 = or(mask_sub_0_1_1, _mask_acc_T_9) node mask_eq_10 = and(mask_sub_1_2_1, mask_nbit_1) node _mask_acc_T_10 = and(mask_size_1, mask_eq_10) node mask_acc_10 = or(mask_sub_1_1_1, _mask_acc_T_10) node mask_eq_11 = and(mask_sub_1_2_1, mask_bit_1) node _mask_acc_T_11 = and(mask_size_1, mask_eq_11) node mask_acc_11 = or(mask_sub_1_1_1, _mask_acc_T_11) node mask_eq_12 = and(mask_sub_2_2_1, mask_nbit_1) node _mask_acc_T_12 = and(mask_size_1, mask_eq_12) node mask_acc_12 = or(mask_sub_2_1_1, _mask_acc_T_12) node mask_eq_13 = and(mask_sub_2_2_1, mask_bit_1) node _mask_acc_T_13 = and(mask_size_1, mask_eq_13) node mask_acc_13 = or(mask_sub_2_1_1, _mask_acc_T_13) node mask_eq_14 = and(mask_sub_3_2_1, mask_nbit_1) node _mask_acc_T_14 = and(mask_size_1, mask_eq_14) node mask_acc_14 = or(mask_sub_3_1_1, _mask_acc_T_14) node mask_eq_15 = and(mask_sub_3_2_1, mask_bit_1) node _mask_acc_T_15 = and(mask_size_1, mask_eq_15) node mask_acc_15 = or(mask_sub_3_1_1, _mask_acc_T_15) node mask_lo_lo_1 = cat(mask_acc_9, mask_acc_8) node mask_lo_hi_1 = cat(mask_acc_11, mask_acc_10) node mask_lo_1 = cat(mask_lo_hi_1, mask_lo_lo_1) node mask_hi_lo_1 = cat(mask_acc_13, mask_acc_12) node mask_hi_hi_1 = cat(mask_acc_15, mask_acc_14) node mask_hi_1 = cat(mask_hi_hi_1, mask_hi_lo_1) node mask_1 = cat(mask_hi_1, mask_lo_1) node _legal_source_T = eq(io.in.b.bits.source, UInt<5>(0h10)) node _legal_source_uncommonBits_T = or(io.in.b.bits.source, UInt<2>(0h0)) node legal_source_uncommonBits = bits(_legal_source_uncommonBits_T, 1, 0) node _legal_source_T_1 = shr(io.in.b.bits.source, 2) node _legal_source_T_2 = eq(_legal_source_T_1, UInt<1>(0h0)) node _legal_source_T_3 = leq(UInt<1>(0h0), legal_source_uncommonBits) node _legal_source_T_4 = and(_legal_source_T_2, _legal_source_T_3) node _legal_source_T_5 = leq(legal_source_uncommonBits, UInt<2>(0h3)) node _legal_source_T_6 = and(_legal_source_T_4, _legal_source_T_5) node _legal_source_uncommonBits_T_1 = or(io.in.b.bits.source, UInt<2>(0h0)) node legal_source_uncommonBits_1 = bits(_legal_source_uncommonBits_T_1, 1, 0) node _legal_source_T_7 = shr(io.in.b.bits.source, 2) node _legal_source_T_8 = eq(_legal_source_T_7, UInt<1>(0h1)) node _legal_source_T_9 = leq(UInt<1>(0h0), legal_source_uncommonBits_1) node _legal_source_T_10 = and(_legal_source_T_8, _legal_source_T_9) node _legal_source_T_11 = leq(legal_source_uncommonBits_1, UInt<2>(0h3)) node _legal_source_T_12 = and(_legal_source_T_10, _legal_source_T_11) node _legal_source_uncommonBits_T_2 = or(io.in.b.bits.source, UInt<2>(0h0)) node legal_source_uncommonBits_2 = bits(_legal_source_uncommonBits_T_2, 1, 0) node _legal_source_T_13 = shr(io.in.b.bits.source, 2) node _legal_source_T_14 = eq(_legal_source_T_13, UInt<2>(0h2)) node _legal_source_T_15 = leq(UInt<1>(0h0), legal_source_uncommonBits_2) node _legal_source_T_16 = and(_legal_source_T_14, _legal_source_T_15) node _legal_source_T_17 = leq(legal_source_uncommonBits_2, UInt<2>(0h3)) node _legal_source_T_18 = and(_legal_source_T_16, _legal_source_T_17) node _legal_source_uncommonBits_T_3 = or(io.in.b.bits.source, UInt<2>(0h0)) node legal_source_uncommonBits_3 = bits(_legal_source_uncommonBits_T_3, 1, 0) node _legal_source_T_19 = shr(io.in.b.bits.source, 2) node _legal_source_T_20 = eq(_legal_source_T_19, UInt<2>(0h3)) node _legal_source_T_21 = leq(UInt<1>(0h0), legal_source_uncommonBits_3) node _legal_source_T_22 = and(_legal_source_T_20, _legal_source_T_21) node _legal_source_T_23 = leq(legal_source_uncommonBits_3, UInt<2>(0h3)) node _legal_source_T_24 = and(_legal_source_T_22, _legal_source_T_23) node _legal_source_T_25 = eq(io.in.b.bits.source, UInt<6>(0h3c)) node _legal_source_T_26 = eq(io.in.b.bits.source, UInt<6>(0h3e)) node _legal_source_T_27 = eq(io.in.b.bits.source, UInt<6>(0h38)) node _legal_source_T_28 = eq(io.in.b.bits.source, UInt<6>(0h3a)) node _legal_source_T_29 = eq(io.in.b.bits.source, UInt<6>(0h34)) node _legal_source_T_30 = eq(io.in.b.bits.source, UInt<6>(0h36)) node _legal_source_T_31 = eq(io.in.b.bits.source, UInt<6>(0h30)) node _legal_source_T_32 = eq(io.in.b.bits.source, UInt<6>(0h32)) node _legal_source_T_33 = eq(io.in.b.bits.source, UInt<6>(0h2c)) node _legal_source_T_34 = eq(io.in.b.bits.source, UInt<6>(0h2e)) node _legal_source_T_35 = eq(io.in.b.bits.source, UInt<6>(0h28)) node _legal_source_T_36 = eq(io.in.b.bits.source, UInt<6>(0h2a)) node _legal_source_T_37 = eq(io.in.b.bits.source, UInt<6>(0h24)) node _legal_source_T_38 = eq(io.in.b.bits.source, UInt<6>(0h26)) node _legal_source_T_39 = eq(io.in.b.bits.source, UInt<6>(0h20)) node _legal_source_T_40 = eq(io.in.b.bits.source, UInt<6>(0h22)) wire _legal_source_WIRE : UInt<1>[21] connect _legal_source_WIRE[0], _legal_source_T connect _legal_source_WIRE[1], _legal_source_T_6 connect _legal_source_WIRE[2], _legal_source_T_12 connect _legal_source_WIRE[3], _legal_source_T_18 connect _legal_source_WIRE[4], _legal_source_T_24 connect _legal_source_WIRE[5], _legal_source_T_25 connect _legal_source_WIRE[6], _legal_source_T_26 connect _legal_source_WIRE[7], _legal_source_T_27 connect _legal_source_WIRE[8], _legal_source_T_28 connect _legal_source_WIRE[9], _legal_source_T_29 connect _legal_source_WIRE[10], _legal_source_T_30 connect _legal_source_WIRE[11], _legal_source_T_31 connect _legal_source_WIRE[12], _legal_source_T_32 connect _legal_source_WIRE[13], _legal_source_T_33 connect _legal_source_WIRE[14], _legal_source_T_34 connect _legal_source_WIRE[15], _legal_source_T_35 connect _legal_source_WIRE[16], _legal_source_T_36 connect _legal_source_WIRE[17], _legal_source_T_37 connect _legal_source_WIRE[18], _legal_source_T_38 connect _legal_source_WIRE[19], _legal_source_T_39 connect _legal_source_WIRE[20], _legal_source_T_40 node _legal_source_T_41 = mux(_legal_source_WIRE[0], UInt<5>(0h10), UInt<1>(0h0)) node _legal_source_T_42 = mux(_legal_source_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _legal_source_T_43 = mux(_legal_source_WIRE[2], UInt<3>(0h4), UInt<1>(0h0)) node _legal_source_T_44 = mux(_legal_source_WIRE[3], UInt<4>(0h8), UInt<1>(0h0)) node _legal_source_T_45 = mux(_legal_source_WIRE[4], UInt<4>(0hc), UInt<1>(0h0)) node _legal_source_T_46 = mux(_legal_source_WIRE[5], UInt<6>(0h3c), UInt<1>(0h0)) node _legal_source_T_47 = mux(_legal_source_WIRE[6], UInt<6>(0h3e), UInt<1>(0h0)) node _legal_source_T_48 = mux(_legal_source_WIRE[7], UInt<6>(0h38), UInt<1>(0h0)) node _legal_source_T_49 = mux(_legal_source_WIRE[8], UInt<6>(0h3a), UInt<1>(0h0)) node _legal_source_T_50 = mux(_legal_source_WIRE[9], UInt<6>(0h34), UInt<1>(0h0)) node _legal_source_T_51 = mux(_legal_source_WIRE[10], UInt<6>(0h36), UInt<1>(0h0)) node _legal_source_T_52 = mux(_legal_source_WIRE[11], UInt<6>(0h30), UInt<1>(0h0)) node _legal_source_T_53 = mux(_legal_source_WIRE[12], UInt<6>(0h32), UInt<1>(0h0)) node _legal_source_T_54 = mux(_legal_source_WIRE[13], UInt<6>(0h2c), UInt<1>(0h0)) node _legal_source_T_55 = mux(_legal_source_WIRE[14], UInt<6>(0h2e), UInt<1>(0h0)) node _legal_source_T_56 = mux(_legal_source_WIRE[15], UInt<6>(0h28), UInt<1>(0h0)) node _legal_source_T_57 = mux(_legal_source_WIRE[16], UInt<6>(0h2a), UInt<1>(0h0)) node _legal_source_T_58 = mux(_legal_source_WIRE[17], UInt<6>(0h24), UInt<1>(0h0)) node _legal_source_T_59 = mux(_legal_source_WIRE[18], UInt<6>(0h26), UInt<1>(0h0)) node _legal_source_T_60 = mux(_legal_source_WIRE[19], UInt<6>(0h20), UInt<1>(0h0)) node _legal_source_T_61 = mux(_legal_source_WIRE[20], UInt<6>(0h22), UInt<1>(0h0)) node _legal_source_T_62 = or(_legal_source_T_41, _legal_source_T_42) node _legal_source_T_63 = or(_legal_source_T_62, _legal_source_T_43) node _legal_source_T_64 = or(_legal_source_T_63, _legal_source_T_44) node _legal_source_T_65 = or(_legal_source_T_64, _legal_source_T_45) node _legal_source_T_66 = or(_legal_source_T_65, _legal_source_T_46) node _legal_source_T_67 = or(_legal_source_T_66, _legal_source_T_47) node _legal_source_T_68 = or(_legal_source_T_67, _legal_source_T_48) node _legal_source_T_69 = or(_legal_source_T_68, _legal_source_T_49) node _legal_source_T_70 = or(_legal_source_T_69, _legal_source_T_50) node _legal_source_T_71 = or(_legal_source_T_70, _legal_source_T_51) node _legal_source_T_72 = or(_legal_source_T_71, _legal_source_T_52) node _legal_source_T_73 = or(_legal_source_T_72, _legal_source_T_53) node _legal_source_T_74 = or(_legal_source_T_73, _legal_source_T_54) node _legal_source_T_75 = or(_legal_source_T_74, _legal_source_T_55) node _legal_source_T_76 = or(_legal_source_T_75, _legal_source_T_56) node _legal_source_T_77 = or(_legal_source_T_76, _legal_source_T_57) node _legal_source_T_78 = or(_legal_source_T_77, _legal_source_T_58) node _legal_source_T_79 = or(_legal_source_T_78, _legal_source_T_59) node _legal_source_T_80 = or(_legal_source_T_79, _legal_source_T_60) node _legal_source_T_81 = or(_legal_source_T_80, _legal_source_T_61) wire _legal_source_WIRE_1 : UInt<6> connect _legal_source_WIRE_1, _legal_source_T_81 node legal_source = eq(_legal_source_WIRE_1, io.in.b.bits.source) node _T_1631 = eq(io.in.b.bits.opcode, UInt<3>(0h6)) when _T_1631 : node _T_1632 = eq(io.in.b.bits.source, UInt<5>(0h10)) node _uncommonBits_T_48 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0) node _T_1633 = shr(io.in.b.bits.source, 2) node _T_1634 = eq(_T_1633, UInt<1>(0h0)) node _T_1635 = leq(UInt<1>(0h0), uncommonBits_48) node _T_1636 = and(_T_1634, _T_1635) node _T_1637 = leq(uncommonBits_48, UInt<2>(0h3)) node _T_1638 = and(_T_1636, _T_1637) node _uncommonBits_T_49 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_49 = bits(_uncommonBits_T_49, 1, 0) node _T_1639 = shr(io.in.b.bits.source, 2) node _T_1640 = eq(_T_1639, UInt<1>(0h1)) node _T_1641 = leq(UInt<1>(0h0), uncommonBits_49) node _T_1642 = and(_T_1640, _T_1641) node _T_1643 = leq(uncommonBits_49, UInt<2>(0h3)) node _T_1644 = and(_T_1642, _T_1643) node _uncommonBits_T_50 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0) node _T_1645 = shr(io.in.b.bits.source, 2) node _T_1646 = eq(_T_1645, UInt<2>(0h2)) node _T_1647 = leq(UInt<1>(0h0), uncommonBits_50) node _T_1648 = and(_T_1646, _T_1647) node _T_1649 = leq(uncommonBits_50, UInt<2>(0h3)) node _T_1650 = and(_T_1648, _T_1649) node _uncommonBits_T_51 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0) node _T_1651 = shr(io.in.b.bits.source, 2) node _T_1652 = eq(_T_1651, UInt<2>(0h3)) node _T_1653 = leq(UInt<1>(0h0), uncommonBits_51) node _T_1654 = and(_T_1652, _T_1653) node _T_1655 = leq(uncommonBits_51, UInt<2>(0h3)) node _T_1656 = and(_T_1654, _T_1655) node _T_1657 = eq(io.in.b.bits.source, UInt<6>(0h3c)) node _T_1658 = eq(io.in.b.bits.source, UInt<6>(0h3e)) node _T_1659 = eq(io.in.b.bits.source, UInt<6>(0h38)) node _T_1660 = eq(io.in.b.bits.source, UInt<6>(0h3a)) node _T_1661 = eq(io.in.b.bits.source, UInt<6>(0h34)) node _T_1662 = eq(io.in.b.bits.source, UInt<6>(0h36)) node _T_1663 = eq(io.in.b.bits.source, UInt<6>(0h30)) node _T_1664 = eq(io.in.b.bits.source, UInt<6>(0h32)) node _T_1665 = eq(io.in.b.bits.source, UInt<6>(0h2c)) node _T_1666 = eq(io.in.b.bits.source, UInt<6>(0h2e)) node _T_1667 = eq(io.in.b.bits.source, UInt<6>(0h28)) node _T_1668 = eq(io.in.b.bits.source, UInt<6>(0h2a)) node _T_1669 = eq(io.in.b.bits.source, UInt<6>(0h24)) node _T_1670 = eq(io.in.b.bits.source, UInt<6>(0h26)) node _T_1671 = eq(io.in.b.bits.source, UInt<6>(0h20)) node _T_1672 = eq(io.in.b.bits.source, UInt<6>(0h22)) wire _WIRE_4 : UInt<1>[21] connect _WIRE_4[0], _T_1632 connect _WIRE_4[1], _T_1638 connect _WIRE_4[2], _T_1644 connect _WIRE_4[3], _T_1650 connect _WIRE_4[4], _T_1656 connect _WIRE_4[5], _T_1657 connect _WIRE_4[6], _T_1658 connect _WIRE_4[7], _T_1659 connect _WIRE_4[8], _T_1660 connect _WIRE_4[9], _T_1661 connect _WIRE_4[10], _T_1662 connect _WIRE_4[11], _T_1663 connect _WIRE_4[12], _T_1664 connect _WIRE_4[13], _T_1665 connect _WIRE_4[14], _T_1666 connect _WIRE_4[15], _T_1667 connect _WIRE_4[16], _T_1668 connect _WIRE_4[17], _T_1669 connect _WIRE_4[18], _T_1670 connect _WIRE_4[19], _T_1671 connect _WIRE_4[20], _T_1672 node _T_1673 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1674 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1675 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1676 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1677 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1678 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1679 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1680 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1681 = mux(_WIRE_4[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_1682 = mux(_WIRE_4[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1683 = mux(_WIRE_4[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_1684 = mux(_WIRE_4[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_1685 = mux(_WIRE_4[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_1686 = mux(_WIRE_4[5], _T_1673, UInt<1>(0h0)) node _T_1687 = mux(_WIRE_4[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_1688 = mux(_WIRE_4[7], _T_1674, UInt<1>(0h0)) node _T_1689 = mux(_WIRE_4[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_1690 = mux(_WIRE_4[9], _T_1675, UInt<1>(0h0)) node _T_1691 = mux(_WIRE_4[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_1692 = mux(_WIRE_4[11], _T_1676, UInt<1>(0h0)) node _T_1693 = mux(_WIRE_4[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_1694 = mux(_WIRE_4[13], _T_1677, UInt<1>(0h0)) node _T_1695 = mux(_WIRE_4[14], UInt<1>(0h0), UInt<1>(0h0)) node _T_1696 = mux(_WIRE_4[15], _T_1678, UInt<1>(0h0)) node _T_1697 = mux(_WIRE_4[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_1698 = mux(_WIRE_4[17], _T_1679, UInt<1>(0h0)) node _T_1699 = mux(_WIRE_4[18], UInt<1>(0h0), UInt<1>(0h0)) node _T_1700 = mux(_WIRE_4[19], _T_1680, UInt<1>(0h0)) node _T_1701 = mux(_WIRE_4[20], UInt<1>(0h0), UInt<1>(0h0)) node _T_1702 = or(_T_1681, _T_1682) node _T_1703 = or(_T_1702, _T_1683) node _T_1704 = or(_T_1703, _T_1684) node _T_1705 = or(_T_1704, _T_1685) node _T_1706 = or(_T_1705, _T_1686) node _T_1707 = or(_T_1706, _T_1687) node _T_1708 = or(_T_1707, _T_1688) node _T_1709 = or(_T_1708, _T_1689) node _T_1710 = or(_T_1709, _T_1690) node _T_1711 = or(_T_1710, _T_1691) node _T_1712 = or(_T_1711, _T_1692) node _T_1713 = or(_T_1712, _T_1693) node _T_1714 = or(_T_1713, _T_1694) node _T_1715 = or(_T_1714, _T_1695) node _T_1716 = or(_T_1715, _T_1696) node _T_1717 = or(_T_1716, _T_1697) node _T_1718 = or(_T_1717, _T_1698) node _T_1719 = or(_T_1718, _T_1699) node _T_1720 = or(_T_1719, _T_1700) node _T_1721 = or(_T_1720, _T_1701) wire _WIRE_5 : UInt<1> connect _WIRE_5, _T_1721 node _T_1722 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1723 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1724 = and(_T_1722, _T_1723) node _T_1725 = or(UInt<1>(0h0), _T_1724) node _T_1726 = xor(io.in.b.bits.address, UInt<28>(0h8000040)) node _T_1727 = cvt(_T_1726) node _T_1728 = and(_T_1727, asSInt(UInt<17>(0h100c0))) node _T_1729 = asSInt(_T_1728) node _T_1730 = eq(_T_1729, asSInt(UInt<1>(0h0))) node _T_1731 = xor(io.in.b.bits.address, UInt<32>(0h80000040)) node _T_1732 = cvt(_T_1731) node _T_1733 = and(_T_1732, asSInt(UInt<29>(0h100000c0))) node _T_1734 = asSInt(_T_1733) node _T_1735 = eq(_T_1734, asSInt(UInt<1>(0h0))) node _T_1736 = or(_T_1730, _T_1735) node _T_1737 = and(_T_1725, _T_1736) node _T_1738 = or(UInt<1>(0h0), _T_1737) node _T_1739 = and(_WIRE_5, _T_1738) node _T_1740 = asUInt(reset) node _T_1741 = eq(_T_1740, UInt<1>(0h0)) when _T_1741 : node _T_1742 = eq(_T_1739, UInt<1>(0h0)) when _T_1742 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_86 assert(clock, _T_1739, UInt<1>(0h1), "") : assert_86 node _T_1743 = asUInt(reset) node _T_1744 = eq(_T_1743, UInt<1>(0h0)) when _T_1744 : node _T_1745 = eq(address_ok, UInt<1>(0h0)) when _T_1745 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_87 assert(clock, address_ok, UInt<1>(0h1), "") : assert_87 node _T_1746 = asUInt(reset) node _T_1747 = eq(_T_1746, UInt<1>(0h0)) when _T_1747 : node _T_1748 = eq(legal_source, UInt<1>(0h0)) when _T_1748 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_88 assert(clock, legal_source, UInt<1>(0h1), "") : assert_88 node _T_1749 = asUInt(reset) node _T_1750 = eq(_T_1749, UInt<1>(0h0)) when _T_1750 : node _T_1751 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1751 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_89 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_89 node _T_1752 = leq(io.in.b.bits.param, UInt<2>(0h2)) node _T_1753 = asUInt(reset) node _T_1754 = eq(_T_1753, UInt<1>(0h0)) when _T_1754 : node _T_1755 = eq(_T_1752, UInt<1>(0h0)) when _T_1755 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_90 assert(clock, _T_1752, UInt<1>(0h1), "") : assert_90 node _T_1756 = eq(io.in.b.bits.mask, mask_1) node _T_1757 = asUInt(reset) node _T_1758 = eq(_T_1757, UInt<1>(0h0)) when _T_1758 : node _T_1759 = eq(_T_1756, UInt<1>(0h0)) when _T_1759 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_91 assert(clock, _T_1756, UInt<1>(0h1), "") : assert_91 node _T_1760 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1761 = asUInt(reset) node _T_1762 = eq(_T_1761, UInt<1>(0h0)) when _T_1762 : node _T_1763 = eq(_T_1760, UInt<1>(0h0)) when _T_1763 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1760, UInt<1>(0h1), "") : assert_92 node _T_1764 = eq(io.in.b.bits.opcode, UInt<3>(0h4)) when _T_1764 : node _T_1765 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1766 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1767 = and(_T_1765, _T_1766) node _T_1768 = or(UInt<1>(0h0), _T_1767) node _T_1769 = xor(io.in.b.bits.address, UInt<28>(0h8000040)) node _T_1770 = cvt(_T_1769) node _T_1771 = and(_T_1770, asSInt(UInt<17>(0h100c0))) node _T_1772 = asSInt(_T_1771) node _T_1773 = eq(_T_1772, asSInt(UInt<1>(0h0))) node _T_1774 = xor(io.in.b.bits.address, UInt<32>(0h80000040)) node _T_1775 = cvt(_T_1774) node _T_1776 = and(_T_1775, asSInt(UInt<29>(0h100000c0))) node _T_1777 = asSInt(_T_1776) node _T_1778 = eq(_T_1777, asSInt(UInt<1>(0h0))) node _T_1779 = or(_T_1773, _T_1778) node _T_1780 = and(_T_1768, _T_1779) node _T_1781 = or(UInt<1>(0h0), _T_1780) node _T_1782 = and(UInt<1>(0h0), _T_1781) node _T_1783 = asUInt(reset) node _T_1784 = eq(_T_1783, UInt<1>(0h0)) when _T_1784 : node _T_1785 = eq(_T_1782, UInt<1>(0h0)) when _T_1785 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Get type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_93 assert(clock, _T_1782, UInt<1>(0h1), "") : assert_93 node _T_1786 = asUInt(reset) node _T_1787 = eq(_T_1786, UInt<1>(0h0)) when _T_1787 : node _T_1788 = eq(address_ok, UInt<1>(0h0)) when _T_1788 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_94 assert(clock, address_ok, UInt<1>(0h1), "") : assert_94 node _T_1789 = asUInt(reset) node _T_1790 = eq(_T_1789, UInt<1>(0h0)) when _T_1790 : node _T_1791 = eq(legal_source, UInt<1>(0h0)) when _T_1791 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_95 assert(clock, legal_source, UInt<1>(0h1), "") : assert_95 node _T_1792 = asUInt(reset) node _T_1793 = eq(_T_1792, UInt<1>(0h0)) when _T_1793 : node _T_1794 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1794 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_96 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_96 node _T_1795 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1796 = asUInt(reset) node _T_1797 = eq(_T_1796, UInt<1>(0h0)) when _T_1797 : node _T_1798 = eq(_T_1795, UInt<1>(0h0)) when _T_1798 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_97 assert(clock, _T_1795, UInt<1>(0h1), "") : assert_97 node _T_1799 = eq(io.in.b.bits.mask, mask_1) node _T_1800 = asUInt(reset) node _T_1801 = eq(_T_1800, UInt<1>(0h0)) when _T_1801 : node _T_1802 = eq(_T_1799, UInt<1>(0h0)) when _T_1802 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1799, UInt<1>(0h1), "") : assert_98 node _T_1803 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1804 = asUInt(reset) node _T_1805 = eq(_T_1804, UInt<1>(0h0)) when _T_1805 : node _T_1806 = eq(_T_1803, UInt<1>(0h0)) when _T_1806 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_99 assert(clock, _T_1803, UInt<1>(0h1), "") : assert_99 node _T_1807 = eq(io.in.b.bits.opcode, UInt<1>(0h0)) when _T_1807 : node _T_1808 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1809 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1810 = and(_T_1808, _T_1809) node _T_1811 = or(UInt<1>(0h0), _T_1810) node _T_1812 = xor(io.in.b.bits.address, UInt<28>(0h8000040)) node _T_1813 = cvt(_T_1812) node _T_1814 = and(_T_1813, asSInt(UInt<17>(0h100c0))) node _T_1815 = asSInt(_T_1814) node _T_1816 = eq(_T_1815, asSInt(UInt<1>(0h0))) node _T_1817 = xor(io.in.b.bits.address, UInt<32>(0h80000040)) node _T_1818 = cvt(_T_1817) node _T_1819 = and(_T_1818, asSInt(UInt<29>(0h100000c0))) node _T_1820 = asSInt(_T_1819) node _T_1821 = eq(_T_1820, asSInt(UInt<1>(0h0))) node _T_1822 = or(_T_1816, _T_1821) node _T_1823 = and(_T_1811, _T_1822) node _T_1824 = or(UInt<1>(0h0), _T_1823) node _T_1825 = and(UInt<1>(0h0), _T_1824) node _T_1826 = asUInt(reset) node _T_1827 = eq(_T_1826, UInt<1>(0h0)) when _T_1827 : node _T_1828 = eq(_T_1825, UInt<1>(0h0)) when _T_1828 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_100 assert(clock, _T_1825, UInt<1>(0h1), "") : assert_100 node _T_1829 = asUInt(reset) node _T_1830 = eq(_T_1829, UInt<1>(0h0)) when _T_1830 : node _T_1831 = eq(address_ok, UInt<1>(0h0)) when _T_1831 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_101 assert(clock, address_ok, UInt<1>(0h1), "") : assert_101 node _T_1832 = asUInt(reset) node _T_1833 = eq(_T_1832, UInt<1>(0h0)) when _T_1833 : node _T_1834 = eq(legal_source, UInt<1>(0h0)) when _T_1834 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_102 assert(clock, legal_source, UInt<1>(0h1), "") : assert_102 node _T_1835 = asUInt(reset) node _T_1836 = eq(_T_1835, UInt<1>(0h0)) when _T_1836 : node _T_1837 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1837 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_103 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_103 node _T_1838 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1839 = asUInt(reset) node _T_1840 = eq(_T_1839, UInt<1>(0h0)) when _T_1840 : node _T_1841 = eq(_T_1838, UInt<1>(0h0)) when _T_1841 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_104 assert(clock, _T_1838, UInt<1>(0h1), "") : assert_104 node _T_1842 = eq(io.in.b.bits.mask, mask_1) node _T_1843 = asUInt(reset) node _T_1844 = eq(_T_1843, UInt<1>(0h0)) when _T_1844 : node _T_1845 = eq(_T_1842, UInt<1>(0h0)) when _T_1845 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1842, UInt<1>(0h1), "") : assert_105 node _T_1846 = eq(io.in.b.bits.opcode, UInt<1>(0h1)) when _T_1846 : node _T_1847 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1848 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1849 = and(_T_1847, _T_1848) node _T_1850 = or(UInt<1>(0h0), _T_1849) node _T_1851 = xor(io.in.b.bits.address, UInt<28>(0h8000040)) node _T_1852 = cvt(_T_1851) node _T_1853 = and(_T_1852, asSInt(UInt<17>(0h100c0))) node _T_1854 = asSInt(_T_1853) node _T_1855 = eq(_T_1854, asSInt(UInt<1>(0h0))) node _T_1856 = xor(io.in.b.bits.address, UInt<32>(0h80000040)) node _T_1857 = cvt(_T_1856) node _T_1858 = and(_T_1857, asSInt(UInt<29>(0h100000c0))) node _T_1859 = asSInt(_T_1858) node _T_1860 = eq(_T_1859, asSInt(UInt<1>(0h0))) node _T_1861 = or(_T_1855, _T_1860) node _T_1862 = and(_T_1850, _T_1861) node _T_1863 = or(UInt<1>(0h0), _T_1862) node _T_1864 = and(UInt<1>(0h0), _T_1863) node _T_1865 = asUInt(reset) node _T_1866 = eq(_T_1865, UInt<1>(0h0)) when _T_1866 : node _T_1867 = eq(_T_1864, UInt<1>(0h0)) when _T_1867 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1864, UInt<1>(0h1), "") : assert_106 node _T_1868 = asUInt(reset) node _T_1869 = eq(_T_1868, UInt<1>(0h0)) when _T_1869 : node _T_1870 = eq(address_ok, UInt<1>(0h0)) when _T_1870 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, address_ok, UInt<1>(0h1), "") : assert_107 node _T_1871 = asUInt(reset) node _T_1872 = eq(_T_1871, UInt<1>(0h0)) when _T_1872 : node _T_1873 = eq(legal_source, UInt<1>(0h0)) when _T_1873 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_108 assert(clock, legal_source, UInt<1>(0h1), "") : assert_108 node _T_1874 = asUInt(reset) node _T_1875 = eq(_T_1874, UInt<1>(0h0)) when _T_1875 : node _T_1876 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1876 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_109 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_109 node _T_1877 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1878 = asUInt(reset) node _T_1879 = eq(_T_1878, UInt<1>(0h0)) when _T_1879 : node _T_1880 = eq(_T_1877, UInt<1>(0h0)) when _T_1880 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_110 assert(clock, _T_1877, UInt<1>(0h1), "") : assert_110 node _T_1881 = not(mask_1) node _T_1882 = and(io.in.b.bits.mask, _T_1881) node _T_1883 = eq(_T_1882, UInt<1>(0h0)) node _T_1884 = asUInt(reset) node _T_1885 = eq(_T_1884, UInt<1>(0h0)) when _T_1885 : node _T_1886 = eq(_T_1883, UInt<1>(0h0)) when _T_1886 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1883, UInt<1>(0h1), "") : assert_111 node _T_1887 = eq(io.in.b.bits.opcode, UInt<2>(0h2)) when _T_1887 : node _T_1888 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1889 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1890 = and(_T_1888, _T_1889) node _T_1891 = or(UInt<1>(0h0), _T_1890) node _T_1892 = xor(io.in.b.bits.address, UInt<28>(0h8000040)) node _T_1893 = cvt(_T_1892) node _T_1894 = and(_T_1893, asSInt(UInt<17>(0h100c0))) node _T_1895 = asSInt(_T_1894) node _T_1896 = eq(_T_1895, asSInt(UInt<1>(0h0))) node _T_1897 = xor(io.in.b.bits.address, UInt<32>(0h80000040)) node _T_1898 = cvt(_T_1897) node _T_1899 = and(_T_1898, asSInt(UInt<29>(0h100000c0))) node _T_1900 = asSInt(_T_1899) node _T_1901 = eq(_T_1900, asSInt(UInt<1>(0h0))) node _T_1902 = or(_T_1896, _T_1901) node _T_1903 = and(_T_1891, _T_1902) node _T_1904 = or(UInt<1>(0h0), _T_1903) node _T_1905 = and(UInt<1>(0h0), _T_1904) node _T_1906 = asUInt(reset) node _T_1907 = eq(_T_1906, UInt<1>(0h0)) when _T_1907 : node _T_1908 = eq(_T_1905, UInt<1>(0h0)) when _T_1908 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by master (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_112 assert(clock, _T_1905, UInt<1>(0h1), "") : assert_112 node _T_1909 = asUInt(reset) node _T_1910 = eq(_T_1909, UInt<1>(0h0)) when _T_1910 : node _T_1911 = eq(address_ok, UInt<1>(0h0)) when _T_1911 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, address_ok, UInt<1>(0h1), "") : assert_113 node _T_1912 = asUInt(reset) node _T_1913 = eq(_T_1912, UInt<1>(0h0)) when _T_1913 : node _T_1914 = eq(legal_source, UInt<1>(0h0)) when _T_1914 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_114 assert(clock, legal_source, UInt<1>(0h1), "") : assert_114 node _T_1915 = asUInt(reset) node _T_1916 = eq(_T_1915, UInt<1>(0h0)) when _T_1916 : node _T_1917 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1917 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_115 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_115 node _T_1918 = leq(io.in.b.bits.param, UInt<3>(0h4)) node _T_1919 = asUInt(reset) node _T_1920 = eq(_T_1919, UInt<1>(0h0)) when _T_1920 : node _T_1921 = eq(_T_1918, UInt<1>(0h0)) when _T_1921 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_116 assert(clock, _T_1918, UInt<1>(0h1), "") : assert_116 node _T_1922 = eq(io.in.b.bits.mask, mask_1) node _T_1923 = asUInt(reset) node _T_1924 = eq(_T_1923, UInt<1>(0h0)) when _T_1924 : node _T_1925 = eq(_T_1922, UInt<1>(0h0)) when _T_1925 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_117 assert(clock, _T_1922, UInt<1>(0h1), "") : assert_117 node _T_1926 = eq(io.in.b.bits.opcode, UInt<2>(0h3)) when _T_1926 : node _T_1927 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1928 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1929 = and(_T_1927, _T_1928) node _T_1930 = or(UInt<1>(0h0), _T_1929) node _T_1931 = xor(io.in.b.bits.address, UInt<28>(0h8000040)) node _T_1932 = cvt(_T_1931) node _T_1933 = and(_T_1932, asSInt(UInt<17>(0h100c0))) node _T_1934 = asSInt(_T_1933) node _T_1935 = eq(_T_1934, asSInt(UInt<1>(0h0))) node _T_1936 = xor(io.in.b.bits.address, UInt<32>(0h80000040)) node _T_1937 = cvt(_T_1936) node _T_1938 = and(_T_1937, asSInt(UInt<29>(0h100000c0))) node _T_1939 = asSInt(_T_1938) node _T_1940 = eq(_T_1939, asSInt(UInt<1>(0h0))) node _T_1941 = or(_T_1935, _T_1940) node _T_1942 = and(_T_1930, _T_1941) node _T_1943 = or(UInt<1>(0h0), _T_1942) node _T_1944 = and(UInt<1>(0h0), _T_1943) node _T_1945 = asUInt(reset) node _T_1946 = eq(_T_1945, UInt<1>(0h0)) when _T_1946 : node _T_1947 = eq(_T_1944, UInt<1>(0h0)) when _T_1947 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_118 assert(clock, _T_1944, UInt<1>(0h1), "") : assert_118 node _T_1948 = asUInt(reset) node _T_1949 = eq(_T_1948, UInt<1>(0h0)) when _T_1949 : node _T_1950 = eq(address_ok, UInt<1>(0h0)) when _T_1950 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_119 assert(clock, address_ok, UInt<1>(0h1), "") : assert_119 node _T_1951 = asUInt(reset) node _T_1952 = eq(_T_1951, UInt<1>(0h0)) when _T_1952 : node _T_1953 = eq(legal_source, UInt<1>(0h0)) when _T_1953 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_120 assert(clock, legal_source, UInt<1>(0h1), "") : assert_120 node _T_1954 = asUInt(reset) node _T_1955 = eq(_T_1954, UInt<1>(0h0)) when _T_1955 : node _T_1956 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1956 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_121 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_121 node _T_1957 = leq(io.in.b.bits.param, UInt<3>(0h3)) node _T_1958 = asUInt(reset) node _T_1959 = eq(_T_1958, UInt<1>(0h0)) when _T_1959 : node _T_1960 = eq(_T_1957, UInt<1>(0h0)) when _T_1960 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_122 assert(clock, _T_1957, UInt<1>(0h1), "") : assert_122 node _T_1961 = eq(io.in.b.bits.mask, mask_1) node _T_1962 = asUInt(reset) node _T_1963 = eq(_T_1962, UInt<1>(0h0)) when _T_1963 : node _T_1964 = eq(_T_1961, UInt<1>(0h0)) when _T_1964 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_123 assert(clock, _T_1961, UInt<1>(0h1), "") : assert_123 node _T_1965 = eq(io.in.b.bits.opcode, UInt<3>(0h5)) when _T_1965 : node _T_1966 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1967 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1968 = and(_T_1966, _T_1967) node _T_1969 = or(UInt<1>(0h0), _T_1968) node _T_1970 = xor(io.in.b.bits.address, UInt<28>(0h8000040)) node _T_1971 = cvt(_T_1970) node _T_1972 = and(_T_1971, asSInt(UInt<17>(0h100c0))) node _T_1973 = asSInt(_T_1972) node _T_1974 = eq(_T_1973, asSInt(UInt<1>(0h0))) node _T_1975 = xor(io.in.b.bits.address, UInt<32>(0h80000040)) node _T_1976 = cvt(_T_1975) node _T_1977 = and(_T_1976, asSInt(UInt<29>(0h100000c0))) node _T_1978 = asSInt(_T_1977) node _T_1979 = eq(_T_1978, asSInt(UInt<1>(0h0))) node _T_1980 = or(_T_1974, _T_1979) node _T_1981 = and(_T_1969, _T_1980) node _T_1982 = or(UInt<1>(0h0), _T_1981) node _T_1983 = and(UInt<1>(0h0), _T_1982) node _T_1984 = asUInt(reset) node _T_1985 = eq(_T_1984, UInt<1>(0h0)) when _T_1985 : node _T_1986 = eq(_T_1983, UInt<1>(0h0)) when _T_1986 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_124 assert(clock, _T_1983, UInt<1>(0h1), "") : assert_124 node _T_1987 = asUInt(reset) node _T_1988 = eq(_T_1987, UInt<1>(0h0)) when _T_1988 : node _T_1989 = eq(address_ok, UInt<1>(0h0)) when _T_1989 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_125 assert(clock, address_ok, UInt<1>(0h1), "") : assert_125 node _T_1990 = asUInt(reset) node _T_1991 = eq(_T_1990, UInt<1>(0h0)) when _T_1991 : node _T_1992 = eq(legal_source, UInt<1>(0h0)) when _T_1992 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_126 assert(clock, legal_source, UInt<1>(0h1), "") : assert_126 node _T_1993 = asUInt(reset) node _T_1994 = eq(_T_1993, UInt<1>(0h0)) when _T_1994 : node _T_1995 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1995 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_127 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_127 node _T_1996 = eq(io.in.b.bits.mask, mask_1) node _T_1997 = asUInt(reset) node _T_1998 = eq(_T_1997, UInt<1>(0h0)) when _T_1998 : node _T_1999 = eq(_T_1996, UInt<1>(0h0)) when _T_1999 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_128 assert(clock, _T_1996, UInt<1>(0h1), "") : assert_128 node _T_2000 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_2001 = asUInt(reset) node _T_2002 = eq(_T_2001, UInt<1>(0h0)) when _T_2002 : node _T_2003 = eq(_T_2000, UInt<1>(0h0)) when _T_2003 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_129 assert(clock, _T_2000, UInt<1>(0h1), "") : assert_129 when io.in.c.valid : node _T_2004 = leq(io.in.c.bits.opcode, UInt<3>(0h7)) node _T_2005 = asUInt(reset) node _T_2006 = eq(_T_2005, UInt<1>(0h0)) when _T_2006 : node _T_2007 = eq(_T_2004, UInt<1>(0h0)) when _T_2007 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_130 assert(clock, _T_2004, UInt<1>(0h1), "") : assert_130 node _source_ok_T_120 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_8 = or(io.in.c.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0) node _source_ok_T_121 = shr(io.in.c.bits.source, 2) node _source_ok_T_122 = eq(_source_ok_T_121, UInt<1>(0h0)) node _source_ok_T_123 = leq(UInt<1>(0h0), source_ok_uncommonBits_8) node _source_ok_T_124 = and(_source_ok_T_122, _source_ok_T_123) node _source_ok_T_125 = leq(source_ok_uncommonBits_8, UInt<2>(0h3)) node _source_ok_T_126 = and(_source_ok_T_124, _source_ok_T_125) node _source_ok_uncommonBits_T_9 = or(io.in.c.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 1, 0) node _source_ok_T_127 = shr(io.in.c.bits.source, 2) node _source_ok_T_128 = eq(_source_ok_T_127, UInt<1>(0h1)) node _source_ok_T_129 = leq(UInt<1>(0h0), source_ok_uncommonBits_9) node _source_ok_T_130 = and(_source_ok_T_128, _source_ok_T_129) node _source_ok_T_131 = leq(source_ok_uncommonBits_9, UInt<2>(0h3)) node _source_ok_T_132 = and(_source_ok_T_130, _source_ok_T_131) node _source_ok_uncommonBits_T_10 = or(io.in.c.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 1, 0) node _source_ok_T_133 = shr(io.in.c.bits.source, 2) node _source_ok_T_134 = eq(_source_ok_T_133, UInt<2>(0h2)) node _source_ok_T_135 = leq(UInt<1>(0h0), source_ok_uncommonBits_10) node _source_ok_T_136 = and(_source_ok_T_134, _source_ok_T_135) node _source_ok_T_137 = leq(source_ok_uncommonBits_10, UInt<2>(0h3)) node _source_ok_T_138 = and(_source_ok_T_136, _source_ok_T_137) node _source_ok_uncommonBits_T_11 = or(io.in.c.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 1, 0) node _source_ok_T_139 = shr(io.in.c.bits.source, 2) node _source_ok_T_140 = eq(_source_ok_T_139, UInt<2>(0h3)) node _source_ok_T_141 = leq(UInt<1>(0h0), source_ok_uncommonBits_11) node _source_ok_T_142 = and(_source_ok_T_140, _source_ok_T_141) node _source_ok_T_143 = leq(source_ok_uncommonBits_11, UInt<2>(0h3)) node _source_ok_T_144 = and(_source_ok_T_142, _source_ok_T_143) node _source_ok_T_145 = eq(io.in.c.bits.source, UInt<6>(0h3c)) node _source_ok_T_146 = eq(io.in.c.bits.source, UInt<6>(0h3e)) node _source_ok_T_147 = eq(io.in.c.bits.source, UInt<6>(0h38)) node _source_ok_T_148 = eq(io.in.c.bits.source, UInt<6>(0h3a)) node _source_ok_T_149 = eq(io.in.c.bits.source, UInt<6>(0h34)) node _source_ok_T_150 = eq(io.in.c.bits.source, UInt<6>(0h36)) node _source_ok_T_151 = eq(io.in.c.bits.source, UInt<6>(0h30)) node _source_ok_T_152 = eq(io.in.c.bits.source, UInt<6>(0h32)) node _source_ok_T_153 = eq(io.in.c.bits.source, UInt<6>(0h2c)) node _source_ok_T_154 = eq(io.in.c.bits.source, UInt<6>(0h2e)) node _source_ok_T_155 = eq(io.in.c.bits.source, UInt<6>(0h28)) node _source_ok_T_156 = eq(io.in.c.bits.source, UInt<6>(0h2a)) node _source_ok_T_157 = eq(io.in.c.bits.source, UInt<6>(0h24)) node _source_ok_T_158 = eq(io.in.c.bits.source, UInt<6>(0h26)) node _source_ok_T_159 = eq(io.in.c.bits.source, UInt<6>(0h20)) node _source_ok_T_160 = eq(io.in.c.bits.source, UInt<6>(0h22)) wire _source_ok_WIRE_2 : UInt<1>[21] connect _source_ok_WIRE_2[0], _source_ok_T_120 connect _source_ok_WIRE_2[1], _source_ok_T_126 connect _source_ok_WIRE_2[2], _source_ok_T_132 connect _source_ok_WIRE_2[3], _source_ok_T_138 connect _source_ok_WIRE_2[4], _source_ok_T_144 connect _source_ok_WIRE_2[5], _source_ok_T_145 connect _source_ok_WIRE_2[6], _source_ok_T_146 connect _source_ok_WIRE_2[7], _source_ok_T_147 connect _source_ok_WIRE_2[8], _source_ok_T_148 connect _source_ok_WIRE_2[9], _source_ok_T_149 connect _source_ok_WIRE_2[10], _source_ok_T_150 connect _source_ok_WIRE_2[11], _source_ok_T_151 connect _source_ok_WIRE_2[12], _source_ok_T_152 connect _source_ok_WIRE_2[13], _source_ok_T_153 connect _source_ok_WIRE_2[14], _source_ok_T_154 connect _source_ok_WIRE_2[15], _source_ok_T_155 connect _source_ok_WIRE_2[16], _source_ok_T_156 connect _source_ok_WIRE_2[17], _source_ok_T_157 connect _source_ok_WIRE_2[18], _source_ok_T_158 connect _source_ok_WIRE_2[19], _source_ok_T_159 connect _source_ok_WIRE_2[20], _source_ok_T_160 node _source_ok_T_161 = or(_source_ok_WIRE_2[0], _source_ok_WIRE_2[1]) node _source_ok_T_162 = or(_source_ok_T_161, _source_ok_WIRE_2[2]) node _source_ok_T_163 = or(_source_ok_T_162, _source_ok_WIRE_2[3]) node _source_ok_T_164 = or(_source_ok_T_163, _source_ok_WIRE_2[4]) node _source_ok_T_165 = or(_source_ok_T_164, _source_ok_WIRE_2[5]) node _source_ok_T_166 = or(_source_ok_T_165, _source_ok_WIRE_2[6]) node _source_ok_T_167 = or(_source_ok_T_166, _source_ok_WIRE_2[7]) node _source_ok_T_168 = or(_source_ok_T_167, _source_ok_WIRE_2[8]) node _source_ok_T_169 = or(_source_ok_T_168, _source_ok_WIRE_2[9]) node _source_ok_T_170 = or(_source_ok_T_169, _source_ok_WIRE_2[10]) node _source_ok_T_171 = or(_source_ok_T_170, _source_ok_WIRE_2[11]) node _source_ok_T_172 = or(_source_ok_T_171, _source_ok_WIRE_2[12]) node _source_ok_T_173 = or(_source_ok_T_172, _source_ok_WIRE_2[13]) node _source_ok_T_174 = or(_source_ok_T_173, _source_ok_WIRE_2[14]) node _source_ok_T_175 = or(_source_ok_T_174, _source_ok_WIRE_2[15]) node _source_ok_T_176 = or(_source_ok_T_175, _source_ok_WIRE_2[16]) node _source_ok_T_177 = or(_source_ok_T_176, _source_ok_WIRE_2[17]) node _source_ok_T_178 = or(_source_ok_T_177, _source_ok_WIRE_2[18]) node _source_ok_T_179 = or(_source_ok_T_178, _source_ok_WIRE_2[19]) node source_ok_2 = or(_source_ok_T_179, _source_ok_WIRE_2[20]) node _is_aligned_mask_T_4 = dshl(UInt<6>(0h3f), io.in.c.bits.size) node _is_aligned_mask_T_5 = bits(_is_aligned_mask_T_4, 5, 0) node is_aligned_mask_2 = not(_is_aligned_mask_T_5) node _is_aligned_T_2 = and(io.in.c.bits.address, is_aligned_mask_2) node is_aligned_2 = eq(_is_aligned_T_2, UInt<1>(0h0)) node _address_ok_T_10 = xor(io.in.c.bits.address, UInt<28>(0h8000040)) node _address_ok_T_11 = cvt(_address_ok_T_10) node _address_ok_T_12 = and(_address_ok_T_11, asSInt(UInt<17>(0h100c0))) node _address_ok_T_13 = asSInt(_address_ok_T_12) node _address_ok_T_14 = eq(_address_ok_T_13, asSInt(UInt<1>(0h0))) node _address_ok_T_15 = xor(io.in.c.bits.address, UInt<32>(0h80000040)) node _address_ok_T_16 = cvt(_address_ok_T_15) node _address_ok_T_17 = and(_address_ok_T_16, asSInt(UInt<29>(0h100000c0))) node _address_ok_T_18 = asSInt(_address_ok_T_17) node _address_ok_T_19 = eq(_address_ok_T_18, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE_1 : UInt<1>[2] connect _address_ok_WIRE_1[0], _address_ok_T_14 connect _address_ok_WIRE_1[1], _address_ok_T_19 node address_ok_1 = or(_address_ok_WIRE_1[0], _address_ok_WIRE_1[1]) node _T_2008 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _T_2009 = eq(_T_2008, UInt<1>(0h0)) node _T_2010 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2011 = cvt(_T_2010) node _T_2012 = and(_T_2011, asSInt(UInt<1>(0h0))) node _T_2013 = asSInt(_T_2012) node _T_2014 = eq(_T_2013, asSInt(UInt<1>(0h0))) node _T_2015 = or(_T_2009, _T_2014) node _uncommonBits_T_52 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_52 = bits(_uncommonBits_T_52, 1, 0) node _T_2016 = shr(io.in.c.bits.source, 2) node _T_2017 = eq(_T_2016, UInt<1>(0h0)) node _T_2018 = leq(UInt<1>(0h0), uncommonBits_52) node _T_2019 = and(_T_2017, _T_2018) node _T_2020 = leq(uncommonBits_52, UInt<2>(0h3)) node _T_2021 = and(_T_2019, _T_2020) node _T_2022 = eq(_T_2021, UInt<1>(0h0)) node _T_2023 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2024 = cvt(_T_2023) node _T_2025 = and(_T_2024, asSInt(UInt<1>(0h0))) node _T_2026 = asSInt(_T_2025) node _T_2027 = eq(_T_2026, asSInt(UInt<1>(0h0))) node _T_2028 = or(_T_2022, _T_2027) node _uncommonBits_T_53 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_53 = bits(_uncommonBits_T_53, 1, 0) node _T_2029 = shr(io.in.c.bits.source, 2) node _T_2030 = eq(_T_2029, UInt<1>(0h1)) node _T_2031 = leq(UInt<1>(0h0), uncommonBits_53) node _T_2032 = and(_T_2030, _T_2031) node _T_2033 = leq(uncommonBits_53, UInt<2>(0h3)) node _T_2034 = and(_T_2032, _T_2033) node _T_2035 = eq(_T_2034, UInt<1>(0h0)) node _T_2036 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2037 = cvt(_T_2036) node _T_2038 = and(_T_2037, asSInt(UInt<1>(0h0))) node _T_2039 = asSInt(_T_2038) node _T_2040 = eq(_T_2039, asSInt(UInt<1>(0h0))) node _T_2041 = or(_T_2035, _T_2040) node _uncommonBits_T_54 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_54 = bits(_uncommonBits_T_54, 1, 0) node _T_2042 = shr(io.in.c.bits.source, 2) node _T_2043 = eq(_T_2042, UInt<2>(0h2)) node _T_2044 = leq(UInt<1>(0h0), uncommonBits_54) node _T_2045 = and(_T_2043, _T_2044) node _T_2046 = leq(uncommonBits_54, UInt<2>(0h3)) node _T_2047 = and(_T_2045, _T_2046) node _T_2048 = eq(_T_2047, UInt<1>(0h0)) node _T_2049 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2050 = cvt(_T_2049) node _T_2051 = and(_T_2050, asSInt(UInt<1>(0h0))) node _T_2052 = asSInt(_T_2051) node _T_2053 = eq(_T_2052, asSInt(UInt<1>(0h0))) node _T_2054 = or(_T_2048, _T_2053) node _uncommonBits_T_55 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_55 = bits(_uncommonBits_T_55, 1, 0) node _T_2055 = shr(io.in.c.bits.source, 2) node _T_2056 = eq(_T_2055, UInt<2>(0h3)) node _T_2057 = leq(UInt<1>(0h0), uncommonBits_55) node _T_2058 = and(_T_2056, _T_2057) node _T_2059 = leq(uncommonBits_55, UInt<2>(0h3)) node _T_2060 = and(_T_2058, _T_2059) node _T_2061 = eq(_T_2060, UInt<1>(0h0)) node _T_2062 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2063 = cvt(_T_2062) node _T_2064 = and(_T_2063, asSInt(UInt<1>(0h0))) node _T_2065 = asSInt(_T_2064) node _T_2066 = eq(_T_2065, asSInt(UInt<1>(0h0))) node _T_2067 = or(_T_2061, _T_2066) node _T_2068 = eq(io.in.c.bits.source, UInt<6>(0h3c)) node _T_2069 = eq(_T_2068, UInt<1>(0h0)) node _T_2070 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2071 = cvt(_T_2070) node _T_2072 = and(_T_2071, asSInt(UInt<1>(0h0))) node _T_2073 = asSInt(_T_2072) node _T_2074 = eq(_T_2073, asSInt(UInt<1>(0h0))) node _T_2075 = or(_T_2069, _T_2074) node _T_2076 = eq(io.in.c.bits.source, UInt<6>(0h3e)) node _T_2077 = eq(_T_2076, UInt<1>(0h0)) node _T_2078 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2079 = cvt(_T_2078) node _T_2080 = and(_T_2079, asSInt(UInt<1>(0h0))) node _T_2081 = asSInt(_T_2080) node _T_2082 = eq(_T_2081, asSInt(UInt<1>(0h0))) node _T_2083 = or(_T_2077, _T_2082) node _T_2084 = eq(io.in.c.bits.source, UInt<6>(0h38)) node _T_2085 = eq(_T_2084, UInt<1>(0h0)) node _T_2086 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2087 = cvt(_T_2086) node _T_2088 = and(_T_2087, asSInt(UInt<1>(0h0))) node _T_2089 = asSInt(_T_2088) node _T_2090 = eq(_T_2089, asSInt(UInt<1>(0h0))) node _T_2091 = or(_T_2085, _T_2090) node _T_2092 = eq(io.in.c.bits.source, UInt<6>(0h3a)) node _T_2093 = eq(_T_2092, UInt<1>(0h0)) node _T_2094 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2095 = cvt(_T_2094) node _T_2096 = and(_T_2095, asSInt(UInt<1>(0h0))) node _T_2097 = asSInt(_T_2096) node _T_2098 = eq(_T_2097, asSInt(UInt<1>(0h0))) node _T_2099 = or(_T_2093, _T_2098) node _T_2100 = eq(io.in.c.bits.source, UInt<6>(0h34)) node _T_2101 = eq(_T_2100, UInt<1>(0h0)) node _T_2102 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2103 = cvt(_T_2102) node _T_2104 = and(_T_2103, asSInt(UInt<1>(0h0))) node _T_2105 = asSInt(_T_2104) node _T_2106 = eq(_T_2105, asSInt(UInt<1>(0h0))) node _T_2107 = or(_T_2101, _T_2106) node _T_2108 = eq(io.in.c.bits.source, UInt<6>(0h36)) node _T_2109 = eq(_T_2108, UInt<1>(0h0)) node _T_2110 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2111 = cvt(_T_2110) node _T_2112 = and(_T_2111, asSInt(UInt<1>(0h0))) node _T_2113 = asSInt(_T_2112) node _T_2114 = eq(_T_2113, asSInt(UInt<1>(0h0))) node _T_2115 = or(_T_2109, _T_2114) node _T_2116 = eq(io.in.c.bits.source, UInt<6>(0h30)) node _T_2117 = eq(_T_2116, UInt<1>(0h0)) node _T_2118 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2119 = cvt(_T_2118) node _T_2120 = and(_T_2119, asSInt(UInt<1>(0h0))) node _T_2121 = asSInt(_T_2120) node _T_2122 = eq(_T_2121, asSInt(UInt<1>(0h0))) node _T_2123 = or(_T_2117, _T_2122) node _T_2124 = eq(io.in.c.bits.source, UInt<6>(0h32)) node _T_2125 = eq(_T_2124, UInt<1>(0h0)) node _T_2126 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2127 = cvt(_T_2126) node _T_2128 = and(_T_2127, asSInt(UInt<1>(0h0))) node _T_2129 = asSInt(_T_2128) node _T_2130 = eq(_T_2129, asSInt(UInt<1>(0h0))) node _T_2131 = or(_T_2125, _T_2130) node _T_2132 = eq(io.in.c.bits.source, UInt<6>(0h2c)) node _T_2133 = eq(_T_2132, UInt<1>(0h0)) node _T_2134 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2135 = cvt(_T_2134) node _T_2136 = and(_T_2135, asSInt(UInt<1>(0h0))) node _T_2137 = asSInt(_T_2136) node _T_2138 = eq(_T_2137, asSInt(UInt<1>(0h0))) node _T_2139 = or(_T_2133, _T_2138) node _T_2140 = eq(io.in.c.bits.source, UInt<6>(0h2e)) node _T_2141 = eq(_T_2140, UInt<1>(0h0)) node _T_2142 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2143 = cvt(_T_2142) node _T_2144 = and(_T_2143, asSInt(UInt<1>(0h0))) node _T_2145 = asSInt(_T_2144) node _T_2146 = eq(_T_2145, asSInt(UInt<1>(0h0))) node _T_2147 = or(_T_2141, _T_2146) node _T_2148 = eq(io.in.c.bits.source, UInt<6>(0h28)) node _T_2149 = eq(_T_2148, UInt<1>(0h0)) node _T_2150 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2151 = cvt(_T_2150) node _T_2152 = and(_T_2151, asSInt(UInt<1>(0h0))) node _T_2153 = asSInt(_T_2152) node _T_2154 = eq(_T_2153, asSInt(UInt<1>(0h0))) node _T_2155 = or(_T_2149, _T_2154) node _T_2156 = eq(io.in.c.bits.source, UInt<6>(0h2a)) node _T_2157 = eq(_T_2156, UInt<1>(0h0)) node _T_2158 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2159 = cvt(_T_2158) node _T_2160 = and(_T_2159, asSInt(UInt<1>(0h0))) node _T_2161 = asSInt(_T_2160) node _T_2162 = eq(_T_2161, asSInt(UInt<1>(0h0))) node _T_2163 = or(_T_2157, _T_2162) node _T_2164 = eq(io.in.c.bits.source, UInt<6>(0h24)) node _T_2165 = eq(_T_2164, UInt<1>(0h0)) node _T_2166 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2167 = cvt(_T_2166) node _T_2168 = and(_T_2167, asSInt(UInt<1>(0h0))) node _T_2169 = asSInt(_T_2168) node _T_2170 = eq(_T_2169, asSInt(UInt<1>(0h0))) node _T_2171 = or(_T_2165, _T_2170) node _T_2172 = eq(io.in.c.bits.source, UInt<6>(0h26)) node _T_2173 = eq(_T_2172, UInt<1>(0h0)) node _T_2174 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2175 = cvt(_T_2174) node _T_2176 = and(_T_2175, asSInt(UInt<1>(0h0))) node _T_2177 = asSInt(_T_2176) node _T_2178 = eq(_T_2177, asSInt(UInt<1>(0h0))) node _T_2179 = or(_T_2173, _T_2178) node _T_2180 = eq(io.in.c.bits.source, UInt<6>(0h20)) node _T_2181 = eq(_T_2180, UInt<1>(0h0)) node _T_2182 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2183 = cvt(_T_2182) node _T_2184 = and(_T_2183, asSInt(UInt<1>(0h0))) node _T_2185 = asSInt(_T_2184) node _T_2186 = eq(_T_2185, asSInt(UInt<1>(0h0))) node _T_2187 = or(_T_2181, _T_2186) node _T_2188 = eq(io.in.c.bits.source, UInt<6>(0h22)) node _T_2189 = eq(_T_2188, UInt<1>(0h0)) node _T_2190 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2191 = cvt(_T_2190) node _T_2192 = and(_T_2191, asSInt(UInt<1>(0h0))) node _T_2193 = asSInt(_T_2192) node _T_2194 = eq(_T_2193, asSInt(UInt<1>(0h0))) node _T_2195 = or(_T_2189, _T_2194) node _T_2196 = and(_T_2015, _T_2028) node _T_2197 = and(_T_2196, _T_2041) node _T_2198 = and(_T_2197, _T_2054) node _T_2199 = and(_T_2198, _T_2067) node _T_2200 = and(_T_2199, _T_2075) node _T_2201 = and(_T_2200, _T_2083) node _T_2202 = and(_T_2201, _T_2091) node _T_2203 = and(_T_2202, _T_2099) node _T_2204 = and(_T_2203, _T_2107) node _T_2205 = and(_T_2204, _T_2115) node _T_2206 = and(_T_2205, _T_2123) node _T_2207 = and(_T_2206, _T_2131) node _T_2208 = and(_T_2207, _T_2139) node _T_2209 = and(_T_2208, _T_2147) node _T_2210 = and(_T_2209, _T_2155) node _T_2211 = and(_T_2210, _T_2163) node _T_2212 = and(_T_2211, _T_2171) node _T_2213 = and(_T_2212, _T_2179) node _T_2214 = and(_T_2213, _T_2187) node _T_2215 = and(_T_2214, _T_2195) node _T_2216 = asUInt(reset) node _T_2217 = eq(_T_2216, UInt<1>(0h0)) when _T_2217 : node _T_2218 = eq(_T_2215, UInt<1>(0h0)) when _T_2218 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_131 assert(clock, _T_2215, UInt<1>(0h1), "") : assert_131 node _T_2219 = eq(io.in.c.bits.opcode, UInt<3>(0h4)) when _T_2219 : node _T_2220 = asUInt(reset) node _T_2221 = eq(_T_2220, UInt<1>(0h0)) when _T_2221 : node _T_2222 = eq(address_ok_1, UInt<1>(0h0)) when _T_2222 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_132 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_132 node _T_2223 = asUInt(reset) node _T_2224 = eq(_T_2223, UInt<1>(0h0)) when _T_2224 : node _T_2225 = eq(source_ok_2, UInt<1>(0h0)) when _T_2225 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_133 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_133 node _T_2226 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_2227 = asUInt(reset) node _T_2228 = eq(_T_2227, UInt<1>(0h0)) when _T_2228 : node _T_2229 = eq(_T_2226, UInt<1>(0h0)) when _T_2229 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_134 assert(clock, _T_2226, UInt<1>(0h1), "") : assert_134 node _T_2230 = asUInt(reset) node _T_2231 = eq(_T_2230, UInt<1>(0h0)) when _T_2231 : node _T_2232 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2232 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_135 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_135 node _T_2233 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2234 = asUInt(reset) node _T_2235 = eq(_T_2234, UInt<1>(0h0)) when _T_2235 : node _T_2236 = eq(_T_2233, UInt<1>(0h0)) when _T_2236 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_136 assert(clock, _T_2233, UInt<1>(0h1), "") : assert_136 node _T_2237 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2238 = asUInt(reset) node _T_2239 = eq(_T_2238, UInt<1>(0h0)) when _T_2239 : node _T_2240 = eq(_T_2237, UInt<1>(0h0)) when _T_2240 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_137 assert(clock, _T_2237, UInt<1>(0h1), "") : assert_137 node _T_2241 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) when _T_2241 : node _T_2242 = asUInt(reset) node _T_2243 = eq(_T_2242, UInt<1>(0h0)) when _T_2243 : node _T_2244 = eq(address_ok_1, UInt<1>(0h0)) when _T_2244 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_138 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_138 node _T_2245 = asUInt(reset) node _T_2246 = eq(_T_2245, UInt<1>(0h0)) when _T_2246 : node _T_2247 = eq(source_ok_2, UInt<1>(0h0)) when _T_2247 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_139 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_139 node _T_2248 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_2249 = asUInt(reset) node _T_2250 = eq(_T_2249, UInt<1>(0h0)) when _T_2250 : node _T_2251 = eq(_T_2248, UInt<1>(0h0)) when _T_2251 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_140 assert(clock, _T_2248, UInt<1>(0h1), "") : assert_140 node _T_2252 = asUInt(reset) node _T_2253 = eq(_T_2252, UInt<1>(0h0)) when _T_2253 : node _T_2254 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2254 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_141 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_141 node _T_2255 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2256 = asUInt(reset) node _T_2257 = eq(_T_2256, UInt<1>(0h0)) when _T_2257 : node _T_2258 = eq(_T_2255, UInt<1>(0h0)) when _T_2258 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_142 assert(clock, _T_2255, UInt<1>(0h1), "") : assert_142 node _T_2259 = eq(io.in.c.bits.opcode, UInt<3>(0h6)) when _T_2259 : node _T_2260 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2261 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2262 = and(_T_2260, _T_2261) node _T_2263 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _uncommonBits_T_56 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_56 = bits(_uncommonBits_T_56, 1, 0) node _T_2264 = shr(io.in.c.bits.source, 2) node _T_2265 = eq(_T_2264, UInt<1>(0h0)) node _T_2266 = leq(UInt<1>(0h0), uncommonBits_56) node _T_2267 = and(_T_2265, _T_2266) node _T_2268 = leq(uncommonBits_56, UInt<2>(0h3)) node _T_2269 = and(_T_2267, _T_2268) node _uncommonBits_T_57 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_57 = bits(_uncommonBits_T_57, 1, 0) node _T_2270 = shr(io.in.c.bits.source, 2) node _T_2271 = eq(_T_2270, UInt<1>(0h1)) node _T_2272 = leq(UInt<1>(0h0), uncommonBits_57) node _T_2273 = and(_T_2271, _T_2272) node _T_2274 = leq(uncommonBits_57, UInt<2>(0h3)) node _T_2275 = and(_T_2273, _T_2274) node _uncommonBits_T_58 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_58 = bits(_uncommonBits_T_58, 1, 0) node _T_2276 = shr(io.in.c.bits.source, 2) node _T_2277 = eq(_T_2276, UInt<2>(0h2)) node _T_2278 = leq(UInt<1>(0h0), uncommonBits_58) node _T_2279 = and(_T_2277, _T_2278) node _T_2280 = leq(uncommonBits_58, UInt<2>(0h3)) node _T_2281 = and(_T_2279, _T_2280) node _uncommonBits_T_59 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_59 = bits(_uncommonBits_T_59, 1, 0) node _T_2282 = shr(io.in.c.bits.source, 2) node _T_2283 = eq(_T_2282, UInt<2>(0h3)) node _T_2284 = leq(UInt<1>(0h0), uncommonBits_59) node _T_2285 = and(_T_2283, _T_2284) node _T_2286 = leq(uncommonBits_59, UInt<2>(0h3)) node _T_2287 = and(_T_2285, _T_2286) node _T_2288 = eq(io.in.c.bits.source, UInt<6>(0h3c)) node _T_2289 = eq(io.in.c.bits.source, UInt<6>(0h3e)) node _T_2290 = eq(io.in.c.bits.source, UInt<6>(0h38)) node _T_2291 = eq(io.in.c.bits.source, UInt<6>(0h3a)) node _T_2292 = eq(io.in.c.bits.source, UInt<6>(0h34)) node _T_2293 = eq(io.in.c.bits.source, UInt<6>(0h36)) node _T_2294 = eq(io.in.c.bits.source, UInt<6>(0h30)) node _T_2295 = eq(io.in.c.bits.source, UInt<6>(0h32)) node _T_2296 = eq(io.in.c.bits.source, UInt<6>(0h2c)) node _T_2297 = eq(io.in.c.bits.source, UInt<6>(0h2e)) node _T_2298 = eq(io.in.c.bits.source, UInt<6>(0h28)) node _T_2299 = eq(io.in.c.bits.source, UInt<6>(0h2a)) node _T_2300 = eq(io.in.c.bits.source, UInt<6>(0h24)) node _T_2301 = eq(io.in.c.bits.source, UInt<6>(0h26)) node _T_2302 = eq(io.in.c.bits.source, UInt<6>(0h20)) node _T_2303 = eq(io.in.c.bits.source, UInt<6>(0h22)) node _T_2304 = or(_T_2263, _T_2269) node _T_2305 = or(_T_2304, _T_2275) node _T_2306 = or(_T_2305, _T_2281) node _T_2307 = or(_T_2306, _T_2287) node _T_2308 = or(_T_2307, _T_2288) node _T_2309 = or(_T_2308, _T_2289) node _T_2310 = or(_T_2309, _T_2290) node _T_2311 = or(_T_2310, _T_2291) node _T_2312 = or(_T_2311, _T_2292) node _T_2313 = or(_T_2312, _T_2293) node _T_2314 = or(_T_2313, _T_2294) node _T_2315 = or(_T_2314, _T_2295) node _T_2316 = or(_T_2315, _T_2296) node _T_2317 = or(_T_2316, _T_2297) node _T_2318 = or(_T_2317, _T_2298) node _T_2319 = or(_T_2318, _T_2299) node _T_2320 = or(_T_2319, _T_2300) node _T_2321 = or(_T_2320, _T_2301) node _T_2322 = or(_T_2321, _T_2302) node _T_2323 = or(_T_2322, _T_2303) node _T_2324 = and(_T_2262, _T_2323) node _T_2325 = or(UInt<1>(0h0), _T_2324) node _T_2326 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2327 = or(UInt<1>(0h0), _T_2326) node _T_2328 = xor(io.in.c.bits.address, UInt<28>(0h8000040)) node _T_2329 = cvt(_T_2328) node _T_2330 = and(_T_2329, asSInt(UInt<17>(0h100c0))) node _T_2331 = asSInt(_T_2330) node _T_2332 = eq(_T_2331, asSInt(UInt<1>(0h0))) node _T_2333 = xor(io.in.c.bits.address, UInt<32>(0h80000040)) node _T_2334 = cvt(_T_2333) node _T_2335 = and(_T_2334, asSInt(UInt<29>(0h100000c0))) node _T_2336 = asSInt(_T_2335) node _T_2337 = eq(_T_2336, asSInt(UInt<1>(0h0))) node _T_2338 = or(_T_2332, _T_2337) node _T_2339 = and(_T_2327, _T_2338) node _T_2340 = or(UInt<1>(0h0), _T_2339) node _T_2341 = and(_T_2325, _T_2340) node _T_2342 = asUInt(reset) node _T_2343 = eq(_T_2342, UInt<1>(0h0)) when _T_2343 : node _T_2344 = eq(_T_2341, UInt<1>(0h0)) when _T_2344 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_143 assert(clock, _T_2341, UInt<1>(0h1), "") : assert_143 node _T_2345 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _uncommonBits_T_60 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_60 = bits(_uncommonBits_T_60, 1, 0) node _T_2346 = shr(io.in.c.bits.source, 2) node _T_2347 = eq(_T_2346, UInt<1>(0h0)) node _T_2348 = leq(UInt<1>(0h0), uncommonBits_60) node _T_2349 = and(_T_2347, _T_2348) node _T_2350 = leq(uncommonBits_60, UInt<2>(0h3)) node _T_2351 = and(_T_2349, _T_2350) node _uncommonBits_T_61 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_61 = bits(_uncommonBits_T_61, 1, 0) node _T_2352 = shr(io.in.c.bits.source, 2) node _T_2353 = eq(_T_2352, UInt<1>(0h1)) node _T_2354 = leq(UInt<1>(0h0), uncommonBits_61) node _T_2355 = and(_T_2353, _T_2354) node _T_2356 = leq(uncommonBits_61, UInt<2>(0h3)) node _T_2357 = and(_T_2355, _T_2356) node _uncommonBits_T_62 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_62 = bits(_uncommonBits_T_62, 1, 0) node _T_2358 = shr(io.in.c.bits.source, 2) node _T_2359 = eq(_T_2358, UInt<2>(0h2)) node _T_2360 = leq(UInt<1>(0h0), uncommonBits_62) node _T_2361 = and(_T_2359, _T_2360) node _T_2362 = leq(uncommonBits_62, UInt<2>(0h3)) node _T_2363 = and(_T_2361, _T_2362) node _uncommonBits_T_63 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_63 = bits(_uncommonBits_T_63, 1, 0) node _T_2364 = shr(io.in.c.bits.source, 2) node _T_2365 = eq(_T_2364, UInt<2>(0h3)) node _T_2366 = leq(UInt<1>(0h0), uncommonBits_63) node _T_2367 = and(_T_2365, _T_2366) node _T_2368 = leq(uncommonBits_63, UInt<2>(0h3)) node _T_2369 = and(_T_2367, _T_2368) node _T_2370 = eq(io.in.c.bits.source, UInt<6>(0h3c)) node _T_2371 = eq(io.in.c.bits.source, UInt<6>(0h3e)) node _T_2372 = eq(io.in.c.bits.source, UInt<6>(0h38)) node _T_2373 = eq(io.in.c.bits.source, UInt<6>(0h3a)) node _T_2374 = eq(io.in.c.bits.source, UInt<6>(0h34)) node _T_2375 = eq(io.in.c.bits.source, UInt<6>(0h36)) node _T_2376 = eq(io.in.c.bits.source, UInt<6>(0h30)) node _T_2377 = eq(io.in.c.bits.source, UInt<6>(0h32)) node _T_2378 = eq(io.in.c.bits.source, UInt<6>(0h2c)) node _T_2379 = eq(io.in.c.bits.source, UInt<6>(0h2e)) node _T_2380 = eq(io.in.c.bits.source, UInt<6>(0h28)) node _T_2381 = eq(io.in.c.bits.source, UInt<6>(0h2a)) node _T_2382 = eq(io.in.c.bits.source, UInt<6>(0h24)) node _T_2383 = eq(io.in.c.bits.source, UInt<6>(0h26)) node _T_2384 = eq(io.in.c.bits.source, UInt<6>(0h20)) node _T_2385 = eq(io.in.c.bits.source, UInt<6>(0h22)) wire _WIRE_6 : UInt<1>[21] connect _WIRE_6[0], _T_2345 connect _WIRE_6[1], _T_2351 connect _WIRE_6[2], _T_2357 connect _WIRE_6[3], _T_2363 connect _WIRE_6[4], _T_2369 connect _WIRE_6[5], _T_2370 connect _WIRE_6[6], _T_2371 connect _WIRE_6[7], _T_2372 connect _WIRE_6[8], _T_2373 connect _WIRE_6[9], _T_2374 connect _WIRE_6[10], _T_2375 connect _WIRE_6[11], _T_2376 connect _WIRE_6[12], _T_2377 connect _WIRE_6[13], _T_2378 connect _WIRE_6[14], _T_2379 connect _WIRE_6[15], _T_2380 connect _WIRE_6[16], _T_2381 connect _WIRE_6[17], _T_2382 connect _WIRE_6[18], _T_2383 connect _WIRE_6[19], _T_2384 connect _WIRE_6[20], _T_2385 node _T_2386 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2387 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2388 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2389 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2390 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2391 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2392 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2393 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2394 = mux(_WIRE_6[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_2395 = mux(_WIRE_6[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_2396 = mux(_WIRE_6[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_2397 = mux(_WIRE_6[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_2398 = mux(_WIRE_6[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_2399 = mux(_WIRE_6[5], _T_2386, UInt<1>(0h0)) node _T_2400 = mux(_WIRE_6[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_2401 = mux(_WIRE_6[7], _T_2387, UInt<1>(0h0)) node _T_2402 = mux(_WIRE_6[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_2403 = mux(_WIRE_6[9], _T_2388, UInt<1>(0h0)) node _T_2404 = mux(_WIRE_6[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_2405 = mux(_WIRE_6[11], _T_2389, UInt<1>(0h0)) node _T_2406 = mux(_WIRE_6[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_2407 = mux(_WIRE_6[13], _T_2390, UInt<1>(0h0)) node _T_2408 = mux(_WIRE_6[14], UInt<1>(0h0), UInt<1>(0h0)) node _T_2409 = mux(_WIRE_6[15], _T_2391, UInt<1>(0h0)) node _T_2410 = mux(_WIRE_6[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_2411 = mux(_WIRE_6[17], _T_2392, UInt<1>(0h0)) node _T_2412 = mux(_WIRE_6[18], UInt<1>(0h0), UInt<1>(0h0)) node _T_2413 = mux(_WIRE_6[19], _T_2393, UInt<1>(0h0)) node _T_2414 = mux(_WIRE_6[20], UInt<1>(0h0), UInt<1>(0h0)) node _T_2415 = or(_T_2394, _T_2395) node _T_2416 = or(_T_2415, _T_2396) node _T_2417 = or(_T_2416, _T_2397) node _T_2418 = or(_T_2417, _T_2398) node _T_2419 = or(_T_2418, _T_2399) node _T_2420 = or(_T_2419, _T_2400) node _T_2421 = or(_T_2420, _T_2401) node _T_2422 = or(_T_2421, _T_2402) node _T_2423 = or(_T_2422, _T_2403) node _T_2424 = or(_T_2423, _T_2404) node _T_2425 = or(_T_2424, _T_2405) node _T_2426 = or(_T_2425, _T_2406) node _T_2427 = or(_T_2426, _T_2407) node _T_2428 = or(_T_2427, _T_2408) node _T_2429 = or(_T_2428, _T_2409) node _T_2430 = or(_T_2429, _T_2410) node _T_2431 = or(_T_2430, _T_2411) node _T_2432 = or(_T_2431, _T_2412) node _T_2433 = or(_T_2432, _T_2413) node _T_2434 = or(_T_2433, _T_2414) wire _WIRE_7 : UInt<1> connect _WIRE_7, _T_2434 node _T_2435 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2436 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2437 = and(_T_2435, _T_2436) node _T_2438 = or(UInt<1>(0h0), _T_2437) node _T_2439 = xor(io.in.c.bits.address, UInt<28>(0h8000040)) node _T_2440 = cvt(_T_2439) node _T_2441 = and(_T_2440, asSInt(UInt<17>(0h100c0))) node _T_2442 = asSInt(_T_2441) node _T_2443 = eq(_T_2442, asSInt(UInt<1>(0h0))) node _T_2444 = xor(io.in.c.bits.address, UInt<32>(0h80000040)) node _T_2445 = cvt(_T_2444) node _T_2446 = and(_T_2445, asSInt(UInt<29>(0h100000c0))) node _T_2447 = asSInt(_T_2446) node _T_2448 = eq(_T_2447, asSInt(UInt<1>(0h0))) node _T_2449 = or(_T_2443, _T_2448) node _T_2450 = and(_T_2438, _T_2449) node _T_2451 = or(UInt<1>(0h0), _T_2450) node _T_2452 = and(_WIRE_7, _T_2451) node _T_2453 = asUInt(reset) node _T_2454 = eq(_T_2453, UInt<1>(0h0)) when _T_2454 : node _T_2455 = eq(_T_2452, UInt<1>(0h0)) when _T_2455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_144 assert(clock, _T_2452, UInt<1>(0h1), "") : assert_144 node _T_2456 = asUInt(reset) node _T_2457 = eq(_T_2456, UInt<1>(0h0)) when _T_2457 : node _T_2458 = eq(source_ok_2, UInt<1>(0h0)) when _T_2458 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_145 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_145 node _T_2459 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_2460 = asUInt(reset) node _T_2461 = eq(_T_2460, UInt<1>(0h0)) when _T_2461 : node _T_2462 = eq(_T_2459, UInt<1>(0h0)) when _T_2462 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_146 assert(clock, _T_2459, UInt<1>(0h1), "") : assert_146 node _T_2463 = asUInt(reset) node _T_2464 = eq(_T_2463, UInt<1>(0h0)) when _T_2464 : node _T_2465 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2465 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_147 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_147 node _T_2466 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2467 = asUInt(reset) node _T_2468 = eq(_T_2467, UInt<1>(0h0)) when _T_2468 : node _T_2469 = eq(_T_2466, UInt<1>(0h0)) when _T_2469 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_148 assert(clock, _T_2466, UInt<1>(0h1), "") : assert_148 node _T_2470 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2471 = asUInt(reset) node _T_2472 = eq(_T_2471, UInt<1>(0h0)) when _T_2472 : node _T_2473 = eq(_T_2470, UInt<1>(0h0)) when _T_2473 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_149 assert(clock, _T_2470, UInt<1>(0h1), "") : assert_149 node _T_2474 = eq(io.in.c.bits.opcode, UInt<3>(0h7)) when _T_2474 : node _T_2475 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2476 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2477 = and(_T_2475, _T_2476) node _T_2478 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _uncommonBits_T_64 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_64 = bits(_uncommonBits_T_64, 1, 0) node _T_2479 = shr(io.in.c.bits.source, 2) node _T_2480 = eq(_T_2479, UInt<1>(0h0)) node _T_2481 = leq(UInt<1>(0h0), uncommonBits_64) node _T_2482 = and(_T_2480, _T_2481) node _T_2483 = leq(uncommonBits_64, UInt<2>(0h3)) node _T_2484 = and(_T_2482, _T_2483) node _uncommonBits_T_65 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_65 = bits(_uncommonBits_T_65, 1, 0) node _T_2485 = shr(io.in.c.bits.source, 2) node _T_2486 = eq(_T_2485, UInt<1>(0h1)) node _T_2487 = leq(UInt<1>(0h0), uncommonBits_65) node _T_2488 = and(_T_2486, _T_2487) node _T_2489 = leq(uncommonBits_65, UInt<2>(0h3)) node _T_2490 = and(_T_2488, _T_2489) node _uncommonBits_T_66 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_66 = bits(_uncommonBits_T_66, 1, 0) node _T_2491 = shr(io.in.c.bits.source, 2) node _T_2492 = eq(_T_2491, UInt<2>(0h2)) node _T_2493 = leq(UInt<1>(0h0), uncommonBits_66) node _T_2494 = and(_T_2492, _T_2493) node _T_2495 = leq(uncommonBits_66, UInt<2>(0h3)) node _T_2496 = and(_T_2494, _T_2495) node _uncommonBits_T_67 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_67 = bits(_uncommonBits_T_67, 1, 0) node _T_2497 = shr(io.in.c.bits.source, 2) node _T_2498 = eq(_T_2497, UInt<2>(0h3)) node _T_2499 = leq(UInt<1>(0h0), uncommonBits_67) node _T_2500 = and(_T_2498, _T_2499) node _T_2501 = leq(uncommonBits_67, UInt<2>(0h3)) node _T_2502 = and(_T_2500, _T_2501) node _T_2503 = eq(io.in.c.bits.source, UInt<6>(0h3c)) node _T_2504 = eq(io.in.c.bits.source, UInt<6>(0h3e)) node _T_2505 = eq(io.in.c.bits.source, UInt<6>(0h38)) node _T_2506 = eq(io.in.c.bits.source, UInt<6>(0h3a)) node _T_2507 = eq(io.in.c.bits.source, UInt<6>(0h34)) node _T_2508 = eq(io.in.c.bits.source, UInt<6>(0h36)) node _T_2509 = eq(io.in.c.bits.source, UInt<6>(0h30)) node _T_2510 = eq(io.in.c.bits.source, UInt<6>(0h32)) node _T_2511 = eq(io.in.c.bits.source, UInt<6>(0h2c)) node _T_2512 = eq(io.in.c.bits.source, UInt<6>(0h2e)) node _T_2513 = eq(io.in.c.bits.source, UInt<6>(0h28)) node _T_2514 = eq(io.in.c.bits.source, UInt<6>(0h2a)) node _T_2515 = eq(io.in.c.bits.source, UInt<6>(0h24)) node _T_2516 = eq(io.in.c.bits.source, UInt<6>(0h26)) node _T_2517 = eq(io.in.c.bits.source, UInt<6>(0h20)) node _T_2518 = eq(io.in.c.bits.source, UInt<6>(0h22)) node _T_2519 = or(_T_2478, _T_2484) node _T_2520 = or(_T_2519, _T_2490) node _T_2521 = or(_T_2520, _T_2496) node _T_2522 = or(_T_2521, _T_2502) node _T_2523 = or(_T_2522, _T_2503) node _T_2524 = or(_T_2523, _T_2504) node _T_2525 = or(_T_2524, _T_2505) node _T_2526 = or(_T_2525, _T_2506) node _T_2527 = or(_T_2526, _T_2507) node _T_2528 = or(_T_2527, _T_2508) node _T_2529 = or(_T_2528, _T_2509) node _T_2530 = or(_T_2529, _T_2510) node _T_2531 = or(_T_2530, _T_2511) node _T_2532 = or(_T_2531, _T_2512) node _T_2533 = or(_T_2532, _T_2513) node _T_2534 = or(_T_2533, _T_2514) node _T_2535 = or(_T_2534, _T_2515) node _T_2536 = or(_T_2535, _T_2516) node _T_2537 = or(_T_2536, _T_2517) node _T_2538 = or(_T_2537, _T_2518) node _T_2539 = and(_T_2477, _T_2538) node _T_2540 = or(UInt<1>(0h0), _T_2539) node _T_2541 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2542 = or(UInt<1>(0h0), _T_2541) node _T_2543 = xor(io.in.c.bits.address, UInt<28>(0h8000040)) node _T_2544 = cvt(_T_2543) node _T_2545 = and(_T_2544, asSInt(UInt<17>(0h100c0))) node _T_2546 = asSInt(_T_2545) node _T_2547 = eq(_T_2546, asSInt(UInt<1>(0h0))) node _T_2548 = xor(io.in.c.bits.address, UInt<32>(0h80000040)) node _T_2549 = cvt(_T_2548) node _T_2550 = and(_T_2549, asSInt(UInt<29>(0h100000c0))) node _T_2551 = asSInt(_T_2550) node _T_2552 = eq(_T_2551, asSInt(UInt<1>(0h0))) node _T_2553 = or(_T_2547, _T_2552) node _T_2554 = and(_T_2542, _T_2553) node _T_2555 = or(UInt<1>(0h0), _T_2554) node _T_2556 = and(_T_2540, _T_2555) node _T_2557 = asUInt(reset) node _T_2558 = eq(_T_2557, UInt<1>(0h0)) when _T_2558 : node _T_2559 = eq(_T_2556, UInt<1>(0h0)) when _T_2559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_150 assert(clock, _T_2556, UInt<1>(0h1), "") : assert_150 node _T_2560 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _uncommonBits_T_68 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_68 = bits(_uncommonBits_T_68, 1, 0) node _T_2561 = shr(io.in.c.bits.source, 2) node _T_2562 = eq(_T_2561, UInt<1>(0h0)) node _T_2563 = leq(UInt<1>(0h0), uncommonBits_68) node _T_2564 = and(_T_2562, _T_2563) node _T_2565 = leq(uncommonBits_68, UInt<2>(0h3)) node _T_2566 = and(_T_2564, _T_2565) node _uncommonBits_T_69 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_69 = bits(_uncommonBits_T_69, 1, 0) node _T_2567 = shr(io.in.c.bits.source, 2) node _T_2568 = eq(_T_2567, UInt<1>(0h1)) node _T_2569 = leq(UInt<1>(0h0), uncommonBits_69) node _T_2570 = and(_T_2568, _T_2569) node _T_2571 = leq(uncommonBits_69, UInt<2>(0h3)) node _T_2572 = and(_T_2570, _T_2571) node _uncommonBits_T_70 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_70 = bits(_uncommonBits_T_70, 1, 0) node _T_2573 = shr(io.in.c.bits.source, 2) node _T_2574 = eq(_T_2573, UInt<2>(0h2)) node _T_2575 = leq(UInt<1>(0h0), uncommonBits_70) node _T_2576 = and(_T_2574, _T_2575) node _T_2577 = leq(uncommonBits_70, UInt<2>(0h3)) node _T_2578 = and(_T_2576, _T_2577) node _uncommonBits_T_71 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_71 = bits(_uncommonBits_T_71, 1, 0) node _T_2579 = shr(io.in.c.bits.source, 2) node _T_2580 = eq(_T_2579, UInt<2>(0h3)) node _T_2581 = leq(UInt<1>(0h0), uncommonBits_71) node _T_2582 = and(_T_2580, _T_2581) node _T_2583 = leq(uncommonBits_71, UInt<2>(0h3)) node _T_2584 = and(_T_2582, _T_2583) node _T_2585 = eq(io.in.c.bits.source, UInt<6>(0h3c)) node _T_2586 = eq(io.in.c.bits.source, UInt<6>(0h3e)) node _T_2587 = eq(io.in.c.bits.source, UInt<6>(0h38)) node _T_2588 = eq(io.in.c.bits.source, UInt<6>(0h3a)) node _T_2589 = eq(io.in.c.bits.source, UInt<6>(0h34)) node _T_2590 = eq(io.in.c.bits.source, UInt<6>(0h36)) node _T_2591 = eq(io.in.c.bits.source, UInt<6>(0h30)) node _T_2592 = eq(io.in.c.bits.source, UInt<6>(0h32)) node _T_2593 = eq(io.in.c.bits.source, UInt<6>(0h2c)) node _T_2594 = eq(io.in.c.bits.source, UInt<6>(0h2e)) node _T_2595 = eq(io.in.c.bits.source, UInt<6>(0h28)) node _T_2596 = eq(io.in.c.bits.source, UInt<6>(0h2a)) node _T_2597 = eq(io.in.c.bits.source, UInt<6>(0h24)) node _T_2598 = eq(io.in.c.bits.source, UInt<6>(0h26)) node _T_2599 = eq(io.in.c.bits.source, UInt<6>(0h20)) node _T_2600 = eq(io.in.c.bits.source, UInt<6>(0h22)) wire _WIRE_8 : UInt<1>[21] connect _WIRE_8[0], _T_2560 connect _WIRE_8[1], _T_2566 connect _WIRE_8[2], _T_2572 connect _WIRE_8[3], _T_2578 connect _WIRE_8[4], _T_2584 connect _WIRE_8[5], _T_2585 connect _WIRE_8[6], _T_2586 connect _WIRE_8[7], _T_2587 connect _WIRE_8[8], _T_2588 connect _WIRE_8[9], _T_2589 connect _WIRE_8[10], _T_2590 connect _WIRE_8[11], _T_2591 connect _WIRE_8[12], _T_2592 connect _WIRE_8[13], _T_2593 connect _WIRE_8[14], _T_2594 connect _WIRE_8[15], _T_2595 connect _WIRE_8[16], _T_2596 connect _WIRE_8[17], _T_2597 connect _WIRE_8[18], _T_2598 connect _WIRE_8[19], _T_2599 connect _WIRE_8[20], _T_2600 node _T_2601 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2602 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2603 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2604 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2605 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2606 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2607 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2608 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2609 = mux(_WIRE_8[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_2610 = mux(_WIRE_8[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_2611 = mux(_WIRE_8[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_2612 = mux(_WIRE_8[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_2613 = mux(_WIRE_8[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_2614 = mux(_WIRE_8[5], _T_2601, UInt<1>(0h0)) node _T_2615 = mux(_WIRE_8[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_2616 = mux(_WIRE_8[7], _T_2602, UInt<1>(0h0)) node _T_2617 = mux(_WIRE_8[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_2618 = mux(_WIRE_8[9], _T_2603, UInt<1>(0h0)) node _T_2619 = mux(_WIRE_8[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_2620 = mux(_WIRE_8[11], _T_2604, UInt<1>(0h0)) node _T_2621 = mux(_WIRE_8[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_2622 = mux(_WIRE_8[13], _T_2605, UInt<1>(0h0)) node _T_2623 = mux(_WIRE_8[14], UInt<1>(0h0), UInt<1>(0h0)) node _T_2624 = mux(_WIRE_8[15], _T_2606, UInt<1>(0h0)) node _T_2625 = mux(_WIRE_8[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_2626 = mux(_WIRE_8[17], _T_2607, UInt<1>(0h0)) node _T_2627 = mux(_WIRE_8[18], UInt<1>(0h0), UInt<1>(0h0)) node _T_2628 = mux(_WIRE_8[19], _T_2608, UInt<1>(0h0)) node _T_2629 = mux(_WIRE_8[20], UInt<1>(0h0), UInt<1>(0h0)) node _T_2630 = or(_T_2609, _T_2610) node _T_2631 = or(_T_2630, _T_2611) node _T_2632 = or(_T_2631, _T_2612) node _T_2633 = or(_T_2632, _T_2613) node _T_2634 = or(_T_2633, _T_2614) node _T_2635 = or(_T_2634, _T_2615) node _T_2636 = or(_T_2635, _T_2616) node _T_2637 = or(_T_2636, _T_2617) node _T_2638 = or(_T_2637, _T_2618) node _T_2639 = or(_T_2638, _T_2619) node _T_2640 = or(_T_2639, _T_2620) node _T_2641 = or(_T_2640, _T_2621) node _T_2642 = or(_T_2641, _T_2622) node _T_2643 = or(_T_2642, _T_2623) node _T_2644 = or(_T_2643, _T_2624) node _T_2645 = or(_T_2644, _T_2625) node _T_2646 = or(_T_2645, _T_2626) node _T_2647 = or(_T_2646, _T_2627) node _T_2648 = or(_T_2647, _T_2628) node _T_2649 = or(_T_2648, _T_2629) wire _WIRE_9 : UInt<1> connect _WIRE_9, _T_2649 node _T_2650 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2651 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2652 = and(_T_2650, _T_2651) node _T_2653 = or(UInt<1>(0h0), _T_2652) node _T_2654 = xor(io.in.c.bits.address, UInt<28>(0h8000040)) node _T_2655 = cvt(_T_2654) node _T_2656 = and(_T_2655, asSInt(UInt<17>(0h100c0))) node _T_2657 = asSInt(_T_2656) node _T_2658 = eq(_T_2657, asSInt(UInt<1>(0h0))) node _T_2659 = xor(io.in.c.bits.address, UInt<32>(0h80000040)) node _T_2660 = cvt(_T_2659) node _T_2661 = and(_T_2660, asSInt(UInt<29>(0h100000c0))) node _T_2662 = asSInt(_T_2661) node _T_2663 = eq(_T_2662, asSInt(UInt<1>(0h0))) node _T_2664 = or(_T_2658, _T_2663) node _T_2665 = and(_T_2653, _T_2664) node _T_2666 = or(UInt<1>(0h0), _T_2665) node _T_2667 = and(_WIRE_9, _T_2666) node _T_2668 = asUInt(reset) node _T_2669 = eq(_T_2668, UInt<1>(0h0)) when _T_2669 : node _T_2670 = eq(_T_2667, UInt<1>(0h0)) when _T_2670 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_151 assert(clock, _T_2667, UInt<1>(0h1), "") : assert_151 node _T_2671 = asUInt(reset) node _T_2672 = eq(_T_2671, UInt<1>(0h0)) when _T_2672 : node _T_2673 = eq(source_ok_2, UInt<1>(0h0)) when _T_2673 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_152 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_152 node _T_2674 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_2675 = asUInt(reset) node _T_2676 = eq(_T_2675, UInt<1>(0h0)) when _T_2676 : node _T_2677 = eq(_T_2674, UInt<1>(0h0)) when _T_2677 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_153 assert(clock, _T_2674, UInt<1>(0h1), "") : assert_153 node _T_2678 = asUInt(reset) node _T_2679 = eq(_T_2678, UInt<1>(0h0)) when _T_2679 : node _T_2680 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2680 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_154 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_154 node _T_2681 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2682 = asUInt(reset) node _T_2683 = eq(_T_2682, UInt<1>(0h0)) when _T_2683 : node _T_2684 = eq(_T_2681, UInt<1>(0h0)) when _T_2684 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_155 assert(clock, _T_2681, UInt<1>(0h1), "") : assert_155 node _T_2685 = eq(io.in.c.bits.opcode, UInt<1>(0h0)) when _T_2685 : node _T_2686 = asUInt(reset) node _T_2687 = eq(_T_2686, UInt<1>(0h0)) when _T_2687 : node _T_2688 = eq(address_ok_1, UInt<1>(0h0)) when _T_2688 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_156 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_156 node _T_2689 = asUInt(reset) node _T_2690 = eq(_T_2689, UInt<1>(0h0)) when _T_2690 : node _T_2691 = eq(source_ok_2, UInt<1>(0h0)) when _T_2691 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_157 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_157 node _T_2692 = asUInt(reset) node _T_2693 = eq(_T_2692, UInt<1>(0h0)) when _T_2693 : node _T_2694 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2694 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_158 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_158 node _T_2695 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2696 = asUInt(reset) node _T_2697 = eq(_T_2696, UInt<1>(0h0)) when _T_2697 : node _T_2698 = eq(_T_2695, UInt<1>(0h0)) when _T_2698 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_159 assert(clock, _T_2695, UInt<1>(0h1), "") : assert_159 node _T_2699 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2700 = asUInt(reset) node _T_2701 = eq(_T_2700, UInt<1>(0h0)) when _T_2701 : node _T_2702 = eq(_T_2699, UInt<1>(0h0)) when _T_2702 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_160 assert(clock, _T_2699, UInt<1>(0h1), "") : assert_160 node _T_2703 = eq(io.in.c.bits.opcode, UInt<1>(0h1)) when _T_2703 : node _T_2704 = asUInt(reset) node _T_2705 = eq(_T_2704, UInt<1>(0h0)) when _T_2705 : node _T_2706 = eq(address_ok_1, UInt<1>(0h0)) when _T_2706 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_161 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_161 node _T_2707 = asUInt(reset) node _T_2708 = eq(_T_2707, UInt<1>(0h0)) when _T_2708 : node _T_2709 = eq(source_ok_2, UInt<1>(0h0)) when _T_2709 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_162 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_162 node _T_2710 = asUInt(reset) node _T_2711 = eq(_T_2710, UInt<1>(0h0)) when _T_2711 : node _T_2712 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2712 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_163 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_163 node _T_2713 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2714 = asUInt(reset) node _T_2715 = eq(_T_2714, UInt<1>(0h0)) when _T_2715 : node _T_2716 = eq(_T_2713, UInt<1>(0h0)) when _T_2716 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_164 assert(clock, _T_2713, UInt<1>(0h1), "") : assert_164 node _T_2717 = eq(io.in.c.bits.opcode, UInt<2>(0h2)) when _T_2717 : node _T_2718 = asUInt(reset) node _T_2719 = eq(_T_2718, UInt<1>(0h0)) when _T_2719 : node _T_2720 = eq(address_ok_1, UInt<1>(0h0)) when _T_2720 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_165 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_165 node _T_2721 = asUInt(reset) node _T_2722 = eq(_T_2721, UInt<1>(0h0)) when _T_2722 : node _T_2723 = eq(source_ok_2, UInt<1>(0h0)) when _T_2723 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_166 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_166 node _T_2724 = asUInt(reset) node _T_2725 = eq(_T_2724, UInt<1>(0h0)) when _T_2725 : node _T_2726 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2726 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_167 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_167 node _T_2727 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2728 = asUInt(reset) node _T_2729 = eq(_T_2728, UInt<1>(0h0)) when _T_2729 : node _T_2730 = eq(_T_2727, UInt<1>(0h0)) when _T_2730 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_168 assert(clock, _T_2727, UInt<1>(0h1), "") : assert_168 node _T_2731 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2732 = asUInt(reset) node _T_2733 = eq(_T_2732, UInt<1>(0h0)) when _T_2733 : node _T_2734 = eq(_T_2731, UInt<1>(0h0)) when _T_2734 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_169 assert(clock, _T_2731, UInt<1>(0h1), "") : assert_169 when io.in.e.valid : node sink_ok_1 = lt(io.in.e.bits.sink, UInt<3>(0h7)) node _T_2735 = asUInt(reset) node _T_2736 = eq(_T_2735, UInt<1>(0h0)) when _T_2736 : node _T_2737 = eq(sink_ok_1, UInt<1>(0h0)) when _T_2737 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channels carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_170 assert(clock, sink_ok_1, UInt<1>(0h1), "") : assert_170 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_2738 = eq(a_first, UInt<1>(0h0)) node _T_2739 = and(io.in.a.valid, _T_2738) when _T_2739 : node _T_2740 = eq(io.in.a.bits.opcode, opcode) node _T_2741 = asUInt(reset) node _T_2742 = eq(_T_2741, UInt<1>(0h0)) when _T_2742 : node _T_2743 = eq(_T_2740, UInt<1>(0h0)) when _T_2743 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_171 assert(clock, _T_2740, UInt<1>(0h1), "") : assert_171 node _T_2744 = eq(io.in.a.bits.param, param) node _T_2745 = asUInt(reset) node _T_2746 = eq(_T_2745, UInt<1>(0h0)) when _T_2746 : node _T_2747 = eq(_T_2744, UInt<1>(0h0)) when _T_2747 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_172 assert(clock, _T_2744, UInt<1>(0h1), "") : assert_172 node _T_2748 = eq(io.in.a.bits.size, size) node _T_2749 = asUInt(reset) node _T_2750 = eq(_T_2749, UInt<1>(0h0)) when _T_2750 : node _T_2751 = eq(_T_2748, UInt<1>(0h0)) when _T_2751 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_173 assert(clock, _T_2748, UInt<1>(0h1), "") : assert_173 node _T_2752 = eq(io.in.a.bits.source, source) node _T_2753 = asUInt(reset) node _T_2754 = eq(_T_2753, UInt<1>(0h0)) when _T_2754 : node _T_2755 = eq(_T_2752, UInt<1>(0h0)) when _T_2755 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_174 assert(clock, _T_2752, UInt<1>(0h1), "") : assert_174 node _T_2756 = eq(io.in.a.bits.address, address) node _T_2757 = asUInt(reset) node _T_2758 = eq(_T_2757, UInt<1>(0h0)) when _T_2758 : node _T_2759 = eq(_T_2756, UInt<1>(0h0)) when _T_2759 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_175 assert(clock, _T_2756, UInt<1>(0h1), "") : assert_175 node _T_2760 = and(io.in.a.ready, io.in.a.valid) node _T_2761 = and(_T_2760, a_first) when _T_2761 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_2762 = eq(d_first, UInt<1>(0h0)) node _T_2763 = and(io.in.d.valid, _T_2762) when _T_2763 : node _T_2764 = eq(io.in.d.bits.opcode, opcode_1) node _T_2765 = asUInt(reset) node _T_2766 = eq(_T_2765, UInt<1>(0h0)) when _T_2766 : node _T_2767 = eq(_T_2764, UInt<1>(0h0)) when _T_2767 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_176 assert(clock, _T_2764, UInt<1>(0h1), "") : assert_176 node _T_2768 = eq(io.in.d.bits.param, param_1) node _T_2769 = asUInt(reset) node _T_2770 = eq(_T_2769, UInt<1>(0h0)) when _T_2770 : node _T_2771 = eq(_T_2768, UInt<1>(0h0)) when _T_2771 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_177 assert(clock, _T_2768, UInt<1>(0h1), "") : assert_177 node _T_2772 = eq(io.in.d.bits.size, size_1) node _T_2773 = asUInt(reset) node _T_2774 = eq(_T_2773, UInt<1>(0h0)) when _T_2774 : node _T_2775 = eq(_T_2772, UInt<1>(0h0)) when _T_2775 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_178 assert(clock, _T_2772, UInt<1>(0h1), "") : assert_178 node _T_2776 = eq(io.in.d.bits.source, source_1) node _T_2777 = asUInt(reset) node _T_2778 = eq(_T_2777, UInt<1>(0h0)) when _T_2778 : node _T_2779 = eq(_T_2776, UInt<1>(0h0)) when _T_2779 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_179 assert(clock, _T_2776, UInt<1>(0h1), "") : assert_179 node _T_2780 = eq(io.in.d.bits.sink, sink) node _T_2781 = asUInt(reset) node _T_2782 = eq(_T_2781, UInt<1>(0h0)) when _T_2782 : node _T_2783 = eq(_T_2780, UInt<1>(0h0)) when _T_2783 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_180 assert(clock, _T_2780, UInt<1>(0h1), "") : assert_180 node _T_2784 = eq(io.in.d.bits.denied, denied) node _T_2785 = asUInt(reset) node _T_2786 = eq(_T_2785, UInt<1>(0h0)) when _T_2786 : node _T_2787 = eq(_T_2784, UInt<1>(0h0)) when _T_2787 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_181 assert(clock, _T_2784, UInt<1>(0h1), "") : assert_181 node _T_2788 = and(io.in.d.ready, io.in.d.valid) node _T_2789 = and(_T_2788, d_first) when _T_2789 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied node _b_first_T = and(io.in.b.ready, io.in.b.valid) node _b_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.b.bits.size) node _b_first_beats1_decode_T_1 = bits(_b_first_beats1_decode_T, 5, 0) node _b_first_beats1_decode_T_2 = not(_b_first_beats1_decode_T_1) node b_first_beats1_decode = shr(_b_first_beats1_decode_T_2, 3) node _b_first_beats1_opdata_T = bits(io.in.b.bits.opcode, 2, 2) node b_first_beats1_opdata = eq(_b_first_beats1_opdata_T, UInt<1>(0h0)) node b_first_beats1 = mux(UInt<1>(0h0), b_first_beats1_decode, UInt<1>(0h0)) regreset b_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _b_first_counter1_T = sub(b_first_counter, UInt<1>(0h1)) node b_first_counter1 = tail(_b_first_counter1_T, 1) node b_first = eq(b_first_counter, UInt<1>(0h0)) node _b_first_last_T = eq(b_first_counter, UInt<1>(0h1)) node _b_first_last_T_1 = eq(b_first_beats1, UInt<1>(0h0)) node b_first_last = or(_b_first_last_T, _b_first_last_T_1) node b_first_done = and(b_first_last, _b_first_T) node _b_first_count_T = not(b_first_counter1) node b_first_count = and(b_first_beats1, _b_first_count_T) when _b_first_T : node _b_first_counter_T = mux(b_first, b_first_beats1, b_first_counter1) connect b_first_counter, _b_first_counter_T reg opcode_2 : UInt, clock reg param_2 : UInt, clock reg size_2 : UInt, clock reg source_2 : UInt, clock reg address_1 : UInt, clock node _T_2790 = eq(b_first, UInt<1>(0h0)) node _T_2791 = and(io.in.b.valid, _T_2790) when _T_2791 : node _T_2792 = eq(io.in.b.bits.opcode, opcode_2) node _T_2793 = asUInt(reset) node _T_2794 = eq(_T_2793, UInt<1>(0h0)) when _T_2794 : node _T_2795 = eq(_T_2792, UInt<1>(0h0)) when _T_2795 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_182 assert(clock, _T_2792, UInt<1>(0h1), "") : assert_182 node _T_2796 = eq(io.in.b.bits.param, param_2) node _T_2797 = asUInt(reset) node _T_2798 = eq(_T_2797, UInt<1>(0h0)) when _T_2798 : node _T_2799 = eq(_T_2796, UInt<1>(0h0)) when _T_2799 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_183 assert(clock, _T_2796, UInt<1>(0h1), "") : assert_183 node _T_2800 = eq(io.in.b.bits.size, size_2) node _T_2801 = asUInt(reset) node _T_2802 = eq(_T_2801, UInt<1>(0h0)) when _T_2802 : node _T_2803 = eq(_T_2800, UInt<1>(0h0)) when _T_2803 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_184 assert(clock, _T_2800, UInt<1>(0h1), "") : assert_184 node _T_2804 = eq(io.in.b.bits.source, source_2) node _T_2805 = asUInt(reset) node _T_2806 = eq(_T_2805, UInt<1>(0h0)) when _T_2806 : node _T_2807 = eq(_T_2804, UInt<1>(0h0)) when _T_2807 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_185 assert(clock, _T_2804, UInt<1>(0h1), "") : assert_185 node _T_2808 = eq(io.in.b.bits.address, address_1) node _T_2809 = asUInt(reset) node _T_2810 = eq(_T_2809, UInt<1>(0h0)) when _T_2810 : node _T_2811 = eq(_T_2808, UInt<1>(0h0)) when _T_2811 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_186 assert(clock, _T_2808, UInt<1>(0h1), "") : assert_186 node _T_2812 = and(io.in.b.ready, io.in.b.valid) node _T_2813 = and(_T_2812, b_first) when _T_2813 : connect opcode_2, io.in.b.bits.opcode connect param_2, io.in.b.bits.param connect size_2, io.in.b.bits.size connect source_2, io.in.b.bits.source connect address_1, io.in.b.bits.address node _c_first_T = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.c.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T reg opcode_3 : UInt, clock reg param_3 : UInt, clock reg size_3 : UInt, clock reg source_3 : UInt, clock reg address_2 : UInt, clock node _T_2814 = eq(c_first, UInt<1>(0h0)) node _T_2815 = and(io.in.c.valid, _T_2814) when _T_2815 : node _T_2816 = eq(io.in.c.bits.opcode, opcode_3) node _T_2817 = asUInt(reset) node _T_2818 = eq(_T_2817, UInt<1>(0h0)) when _T_2818 : node _T_2819 = eq(_T_2816, UInt<1>(0h0)) when _T_2819 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_187 assert(clock, _T_2816, UInt<1>(0h1), "") : assert_187 node _T_2820 = eq(io.in.c.bits.param, param_3) node _T_2821 = asUInt(reset) node _T_2822 = eq(_T_2821, UInt<1>(0h0)) when _T_2822 : node _T_2823 = eq(_T_2820, UInt<1>(0h0)) when _T_2823 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_188 assert(clock, _T_2820, UInt<1>(0h1), "") : assert_188 node _T_2824 = eq(io.in.c.bits.size, size_3) node _T_2825 = asUInt(reset) node _T_2826 = eq(_T_2825, UInt<1>(0h0)) when _T_2826 : node _T_2827 = eq(_T_2824, UInt<1>(0h0)) when _T_2827 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_189 assert(clock, _T_2824, UInt<1>(0h1), "") : assert_189 node _T_2828 = eq(io.in.c.bits.source, source_3) node _T_2829 = asUInt(reset) node _T_2830 = eq(_T_2829, UInt<1>(0h0)) when _T_2830 : node _T_2831 = eq(_T_2828, UInt<1>(0h0)) when _T_2831 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_190 assert(clock, _T_2828, UInt<1>(0h1), "") : assert_190 node _T_2832 = eq(io.in.c.bits.address, address_2) node _T_2833 = asUInt(reset) node _T_2834 = eq(_T_2833, UInt<1>(0h0)) when _T_2834 : node _T_2835 = eq(_T_2832, UInt<1>(0h0)) when _T_2835 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_191 assert(clock, _T_2832, UInt<1>(0h1), "") : assert_191 node _T_2836 = and(io.in.c.ready, io.in.c.valid) node _T_2837 = and(_T_2836, c_first) when _T_2837 : connect opcode_3, io.in.c.bits.opcode connect param_3, io.in.c.bits.param connect size_3, io.in.c.bits.size connect source_3, io.in.c.bits.source connect address_2, io.in.c.bits.address regreset inflight : UInt<63>, clock, reset, UInt<63>(0h0) regreset inflight_opcodes : UInt<252>, clock, reset, UInt<252>(0h0) regreset inflight_sizes : UInt<252>, clock, reset, UInt<252>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<63> connect a_set, UInt<63>(0h0) wire a_set_wo_ready : UInt<63> connect a_set_wo_ready, UInt<63>(0h0) wire a_opcodes_set : UInt<252> connect a_opcodes_set, UInt<252>(0h0) wire a_sizes_set : UInt<252> connect a_sizes_set, UInt<252>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_2838 = and(io.in.a.valid, a_first_1) node _T_2839 = and(_T_2838, UInt<1>(0h1)) when _T_2839 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_2840 = and(io.in.a.ready, io.in.a.valid) node _T_2841 = and(_T_2840, a_first_1) node _T_2842 = and(_T_2841, UInt<1>(0h1)) when _T_2842 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_2843 = dshr(inflight, io.in.a.bits.source) node _T_2844 = bits(_T_2843, 0, 0) node _T_2845 = eq(_T_2844, UInt<1>(0h0)) node _T_2846 = asUInt(reset) node _T_2847 = eq(_T_2846, UInt<1>(0h0)) when _T_2847 : node _T_2848 = eq(_T_2845, UInt<1>(0h0)) when _T_2848 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_192 assert(clock, _T_2845, UInt<1>(0h1), "") : assert_192 wire d_clr : UInt<63> connect d_clr, UInt<63>(0h0) wire d_clr_wo_ready : UInt<63> connect d_clr_wo_ready, UInt<63>(0h0) wire d_opcodes_clr : UInt<252> connect d_opcodes_clr, UInt<252>(0h0) wire d_sizes_clr : UInt<252> connect d_sizes_clr, UInt<252>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2849 = and(io.in.d.valid, d_first_1) node _T_2850 = and(_T_2849, UInt<1>(0h1)) node _T_2851 = eq(d_release_ack, UInt<1>(0h0)) node _T_2852 = and(_T_2850, _T_2851) when _T_2852 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_2853 = and(io.in.d.ready, io.in.d.valid) node _T_2854 = and(_T_2853, d_first_1) node _T_2855 = and(_T_2854, UInt<1>(0h1)) node _T_2856 = eq(d_release_ack, UInt<1>(0h0)) node _T_2857 = and(_T_2855, _T_2856) when _T_2857 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_2858 = and(io.in.d.valid, d_first_1) node _T_2859 = and(_T_2858, UInt<1>(0h1)) node _T_2860 = eq(d_release_ack, UInt<1>(0h0)) node _T_2861 = and(_T_2859, _T_2860) when _T_2861 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_2862 = dshr(inflight, io.in.d.bits.source) node _T_2863 = bits(_T_2862, 0, 0) node _T_2864 = or(_T_2863, same_cycle_resp) node _T_2865 = asUInt(reset) node _T_2866 = eq(_T_2865, UInt<1>(0h0)) when _T_2866 : node _T_2867 = eq(_T_2864, UInt<1>(0h0)) when _T_2867 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_193 assert(clock, _T_2864, UInt<1>(0h1), "") : assert_193 when same_cycle_resp : node _T_2868 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_2869 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_2870 = or(_T_2868, _T_2869) node _T_2871 = asUInt(reset) node _T_2872 = eq(_T_2871, UInt<1>(0h0)) when _T_2872 : node _T_2873 = eq(_T_2870, UInt<1>(0h0)) when _T_2873 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_194 assert(clock, _T_2870, UInt<1>(0h1), "") : assert_194 node _T_2874 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_2875 = asUInt(reset) node _T_2876 = eq(_T_2875, UInt<1>(0h0)) when _T_2876 : node _T_2877 = eq(_T_2874, UInt<1>(0h0)) when _T_2877 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_195 assert(clock, _T_2874, UInt<1>(0h1), "") : assert_195 else : node _T_2878 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_2879 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_2880 = or(_T_2878, _T_2879) node _T_2881 = asUInt(reset) node _T_2882 = eq(_T_2881, UInt<1>(0h0)) when _T_2882 : node _T_2883 = eq(_T_2880, UInt<1>(0h0)) when _T_2883 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_196 assert(clock, _T_2880, UInt<1>(0h1), "") : assert_196 node _T_2884 = eq(io.in.d.bits.size, a_size_lookup) node _T_2885 = asUInt(reset) node _T_2886 = eq(_T_2885, UInt<1>(0h0)) when _T_2886 : node _T_2887 = eq(_T_2884, UInt<1>(0h0)) when _T_2887 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_197 assert(clock, _T_2884, UInt<1>(0h1), "") : assert_197 node _T_2888 = and(io.in.d.valid, d_first_1) node _T_2889 = and(_T_2888, a_first_1) node _T_2890 = and(_T_2889, io.in.a.valid) node _T_2891 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_2892 = and(_T_2890, _T_2891) node _T_2893 = eq(d_release_ack, UInt<1>(0h0)) node _T_2894 = and(_T_2892, _T_2893) when _T_2894 : node _T_2895 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2896 = or(_T_2895, io.in.a.ready) node _T_2897 = asUInt(reset) node _T_2898 = eq(_T_2897, UInt<1>(0h0)) when _T_2898 : node _T_2899 = eq(_T_2896, UInt<1>(0h0)) when _T_2899 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_198 assert(clock, _T_2896, UInt<1>(0h1), "") : assert_198 node _T_2900 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_2901 = orr(a_set_wo_ready) node _T_2902 = eq(_T_2901, UInt<1>(0h0)) node _T_2903 = or(_T_2900, _T_2902) node _T_2904 = asUInt(reset) node _T_2905 = eq(_T_2904, UInt<1>(0h0)) when _T_2905 : node _T_2906 = eq(_T_2903, UInt<1>(0h0)) when _T_2906 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_199 assert(clock, _T_2903, UInt<1>(0h1), "") : assert_199 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_116 node _T_2907 = orr(inflight) node _T_2908 = eq(_T_2907, UInt<1>(0h0)) node _T_2909 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_2910 = or(_T_2908, _T_2909) node _T_2911 = lt(watchdog, plusarg_reader.out) node _T_2912 = or(_T_2910, _T_2911) node _T_2913 = asUInt(reset) node _T_2914 = eq(_T_2913, UInt<1>(0h0)) when _T_2914 : node _T_2915 = eq(_T_2912, UInt<1>(0h0)) when _T_2915 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_200 assert(clock, _T_2912, UInt<1>(0h1), "") : assert_200 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_2916 = and(io.in.a.ready, io.in.a.valid) node _T_2917 = and(io.in.d.ready, io.in.d.valid) node _T_2918 = or(_T_2916, _T_2917) when _T_2918 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<63>, clock, reset, UInt<63>(0h0) regreset inflight_opcodes_1 : UInt<252>, clock, reset, UInt<252>(0h0) regreset inflight_sizes_1 : UInt<252>, clock, reset, UInt<252>(0h0) node _c_first_T_1 = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.c.bits.size) node _c_first_beats1_decode_T_4 = bits(_c_first_beats1_decode_T_3, 5, 0) node _c_first_beats1_decode_T_5 = not(_c_first_beats1_decode_T_4) node c_first_beats1_decode_1 = shr(_c_first_beats1_decode_T_5, 3) node c_first_beats1_opdata_1 = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1_1 = mux(c_first_beats1_opdata_1, c_first_beats1_decode_1, UInt<1>(0h0)) regreset c_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T_1 = sub(c_first_counter_1, UInt<1>(0h1)) node c_first_counter1_1 = tail(_c_first_counter1_T_1, 1) node c_first_1 = eq(c_first_counter_1, UInt<1>(0h0)) node _c_first_last_T_2 = eq(c_first_counter_1, UInt<1>(0h1)) node _c_first_last_T_3 = eq(c_first_beats1_1, UInt<1>(0h0)) node c_first_last_1 = or(_c_first_last_T_2, _c_first_last_T_3) node c_first_done_1 = and(c_first_last_1, _c_first_T_1) node _c_first_count_T_1 = not(c_first_counter1_1) node c_first_count_1 = and(c_first_beats1_1, _c_first_count_T_1) when _c_first_T_1 : node _c_first_counter_T_1 = mux(c_first_1, c_first_beats1_1, c_first_counter1_1) connect c_first_counter_1, _c_first_counter_T_1 node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<63> connect c_set, UInt<63>(0h0) wire c_set_wo_ready : UInt<63> connect c_set_wo_ready, UInt<63>(0h0) wire c_opcodes_set : UInt<252> connect c_opcodes_set, UInt<252>(0h0) wire c_sizes_set : UInt<252> connect c_sizes_set, UInt<252>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) node _T_2919 = and(io.in.c.valid, c_first_1) node _T_2920 = bits(io.in.c.bits.opcode, 2, 2) node _T_2921 = bits(io.in.c.bits.opcode, 1, 1) node _T_2922 = and(_T_2920, _T_2921) node _T_2923 = and(_T_2919, _T_2922) when _T_2923 : node _c_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T node _T_2924 = and(io.in.c.ready, io.in.c.valid) node _T_2925 = and(_T_2924, c_first_1) node _T_2926 = bits(io.in.c.bits.opcode, 2, 2) node _T_2927 = bits(io.in.c.bits.opcode, 1, 1) node _T_2928 = and(_T_2926, _T_2927) node _T_2929 = and(_T_2925, _T_2928) when _T_2929 : node _c_set_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set, _c_set_T node _c_opcodes_set_interm_T = dshl(io.in.c.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 node _c_sizes_set_interm_T = dshl(io.in.c.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 node _c_opcodes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 node _c_sizes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 node _T_2930 = dshr(inflight_1, io.in.c.bits.source) node _T_2931 = bits(_T_2930, 0, 0) node _T_2932 = eq(_T_2931, UInt<1>(0h0)) node _T_2933 = asUInt(reset) node _T_2934 = eq(_T_2933, UInt<1>(0h0)) when _T_2934 : node _T_2935 = eq(_T_2932, UInt<1>(0h0)) when _T_2935 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_201 assert(clock, _T_2932, UInt<1>(0h1), "") : assert_201 node _c_probe_ack_T = eq(io.in.c.bits.opcode, UInt<3>(0h4)) node _c_probe_ack_T_1 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<63> connect d_clr_1, UInt<63>(0h0) wire d_clr_wo_ready_1 : UInt<63> connect d_clr_wo_ready_1, UInt<63>(0h0) wire d_opcodes_clr_1 : UInt<252> connect d_opcodes_clr_1, UInt<252>(0h0) wire d_sizes_clr_1 : UInt<252> connect d_sizes_clr_1, UInt<252>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2936 = and(io.in.d.valid, d_first_2) node _T_2937 = and(_T_2936, UInt<1>(0h1)) node _T_2938 = and(_T_2937, d_release_ack_1) when _T_2938 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_2939 = and(io.in.d.ready, io.in.d.valid) node _T_2940 = and(_T_2939, d_first_2) node _T_2941 = and(_T_2940, UInt<1>(0h1)) node _T_2942 = and(_T_2941, d_release_ack_1) when _T_2942 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_2943 = and(io.in.d.valid, d_first_2) node _T_2944 = and(_T_2943, UInt<1>(0h1)) node _T_2945 = and(_T_2944, d_release_ack_1) when _T_2945 : node _same_cycle_resp_T_3 = and(io.in.c.valid, c_first_1) node _same_cycle_resp_T_4 = bits(io.in.c.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(io.in.c.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) node _same_cycle_resp_T_8 = eq(io.in.c.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_2946 = dshr(inflight_1, io.in.d.bits.source) node _T_2947 = bits(_T_2946, 0, 0) node _T_2948 = or(_T_2947, same_cycle_resp_1) node _T_2949 = asUInt(reset) node _T_2950 = eq(_T_2949, UInt<1>(0h0)) when _T_2950 : node _T_2951 = eq(_T_2948, UInt<1>(0h0)) when _T_2951 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_202 assert(clock, _T_2948, UInt<1>(0h1), "") : assert_202 when same_cycle_resp_1 : node _T_2952 = eq(io.in.d.bits.size, io.in.c.bits.size) node _T_2953 = asUInt(reset) node _T_2954 = eq(_T_2953, UInt<1>(0h0)) when _T_2954 : node _T_2955 = eq(_T_2952, UInt<1>(0h0)) when _T_2955 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_203 assert(clock, _T_2952, UInt<1>(0h1), "") : assert_203 else : node _T_2956 = eq(io.in.d.bits.size, c_size_lookup) node _T_2957 = asUInt(reset) node _T_2958 = eq(_T_2957, UInt<1>(0h0)) when _T_2958 : node _T_2959 = eq(_T_2956, UInt<1>(0h0)) when _T_2959 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_204 assert(clock, _T_2956, UInt<1>(0h1), "") : assert_204 node _T_2960 = and(io.in.d.valid, d_first_2) node _T_2961 = and(_T_2960, c_first_1) node _T_2962 = and(_T_2961, io.in.c.valid) node _T_2963 = eq(io.in.c.bits.source, io.in.d.bits.source) node _T_2964 = and(_T_2962, _T_2963) node _T_2965 = and(_T_2964, d_release_ack_1) node _T_2966 = eq(c_probe_ack, UInt<1>(0h0)) node _T_2967 = and(_T_2965, _T_2966) when _T_2967 : node _T_2968 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2969 = or(_T_2968, io.in.c.ready) node _T_2970 = asUInt(reset) node _T_2971 = eq(_T_2970, UInt<1>(0h0)) when _T_2971 : node _T_2972 = eq(_T_2969, UInt<1>(0h0)) when _T_2972 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_205 assert(clock, _T_2969, UInt<1>(0h1), "") : assert_205 node _T_2973 = orr(c_set_wo_ready) when _T_2973 : node _T_2974 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_2975 = asUInt(reset) node _T_2976 = eq(_T_2975, UInt<1>(0h0)) when _T_2976 : node _T_2977 = eq(_T_2974, UInt<1>(0h0)) when _T_2977 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_206 assert(clock, _T_2974, UInt<1>(0h1), "") : assert_206 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_117 node _T_2978 = orr(inflight_1) node _T_2979 = eq(_T_2978, UInt<1>(0h0)) node _T_2980 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_2981 = or(_T_2979, _T_2980) node _T_2982 = lt(watchdog_1, plusarg_reader_1.out) node _T_2983 = or(_T_2981, _T_2982) node _T_2984 = asUInt(reset) node _T_2985 = eq(_T_2984, UInt<1>(0h0)) when _T_2985 : node _T_2986 = eq(_T_2983, UInt<1>(0h0)) when _T_2986 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_207 assert(clock, _T_2983, UInt<1>(0h1), "") : assert_207 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 node _T_2987 = and(io.in.c.ready, io.in.c.valid) node _T_2988 = and(io.in.d.ready, io.in.d.valid) node _T_2989 = or(_T_2987, _T_2988) when _T_2989 : connect watchdog_1, UInt<1>(0h0) regreset inflight_2 : UInt<7>, clock, reset, UInt<7>(0h0) node _d_first_T_3 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_9 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_10 = bits(_d_first_beats1_decode_T_9, 5, 0) node _d_first_beats1_decode_T_11 = not(_d_first_beats1_decode_T_10) node d_first_beats1_decode_3 = shr(_d_first_beats1_decode_T_11, 3) node d_first_beats1_opdata_3 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_3 = mux(d_first_beats1_opdata_3, d_first_beats1_decode_3, UInt<1>(0h0)) regreset d_first_counter_3 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_3 = sub(d_first_counter_3, UInt<1>(0h1)) node d_first_counter1_3 = tail(_d_first_counter1_T_3, 1) node d_first_3 = eq(d_first_counter_3, UInt<1>(0h0)) node _d_first_last_T_6 = eq(d_first_counter_3, UInt<1>(0h1)) node _d_first_last_T_7 = eq(d_first_beats1_3, UInt<1>(0h0)) node d_first_last_3 = or(_d_first_last_T_6, _d_first_last_T_7) node d_first_done_3 = and(d_first_last_3, _d_first_T_3) node _d_first_count_T_3 = not(d_first_counter1_3) node d_first_count_3 = and(d_first_beats1_3, _d_first_count_T_3) when _d_first_T_3 : node _d_first_counter_T_3 = mux(d_first_3, d_first_beats1_3, d_first_counter1_3) connect d_first_counter_3, _d_first_counter_T_3 wire d_set : UInt<7> connect d_set, UInt<7>(0h0) node _T_2990 = and(io.in.d.ready, io.in.d.valid) node _T_2991 = and(_T_2990, d_first_3) node _T_2992 = bits(io.in.d.bits.opcode, 2, 2) node _T_2993 = bits(io.in.d.bits.opcode, 1, 1) node _T_2994 = eq(_T_2993, UInt<1>(0h0)) node _T_2995 = and(_T_2992, _T_2994) node _T_2996 = and(_T_2991, _T_2995) when _T_2996 : node _d_set_T = dshl(UInt<1>(0h1), io.in.d.bits.sink) connect d_set, _d_set_T node _T_2997 = dshr(inflight_2, io.in.d.bits.sink) node _T_2998 = bits(_T_2997, 0, 0) node _T_2999 = eq(_T_2998, UInt<1>(0h0)) node _T_3000 = asUInt(reset) node _T_3001 = eq(_T_3000, UInt<1>(0h0)) when _T_3001 : node _T_3002 = eq(_T_2999, UInt<1>(0h0)) when _T_3002 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel re-used a sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_208 assert(clock, _T_2999, UInt<1>(0h1), "") : assert_208 wire e_clr : UInt<7> connect e_clr, UInt<7>(0h0) node _T_3003 = and(io.in.e.ready, io.in.e.valid) node _T_3004 = and(_T_3003, UInt<1>(0h1)) node _T_3005 = and(_T_3004, UInt<1>(0h1)) when _T_3005 : node _e_clr_T = dshl(UInt<1>(0h1), io.in.e.bits.sink) connect e_clr, _e_clr_T node _T_3006 = or(d_set, inflight_2) node _T_3007 = dshr(_T_3006, io.in.e.bits.sink) node _T_3008 = bits(_T_3007, 0, 0) node _T_3009 = asUInt(reset) node _T_3010 = eq(_T_3009, UInt<1>(0h0)) when _T_3010 : node _T_3011 = eq(_T_3008, UInt<1>(0h0)) when _T_3011 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_209 assert(clock, _T_3008, UInt<1>(0h1), "") : assert_209 node _inflight_T_6 = or(inflight_2, d_set) node _inflight_T_7 = not(e_clr) node _inflight_T_8 = and(_inflight_T_6, _inflight_T_7) connect inflight_2, _inflight_T_8 extmodule plusarg_reader_118 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_119 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32	module TLMonitor_45( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_b_ready, // @[Monitor.scala:20:14] input io_in_b_valid, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14] input [5:0] io_in_b_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input io_in_c_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [2:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire [12:0] _GEN_0 = {10'h0, io_in_c_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [2:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [5:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _d_first_T_3 = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala:51:35] reg [2:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [5:0] source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [2:0] b_first_counter; // @[Edges.scala:229:27] reg [1:0] param_2; // @[Monitor.scala:411:22] reg [5:0] source_2; // @[Monitor.scala:413:22] reg [31:0] address_1; // @[Monitor.scala:414:22] wire _c_first_T_1 = io_in_c_ready & io_in_c_valid; // @[Decoupled.scala:51:35] reg [2:0] c_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [2:0] size_3; // @[Monitor.scala:517:22] reg [5:0] source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [62:0] inflight; // @[Monitor.scala:614:27] reg [251:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [251:0] inflight_sizes; // @[Monitor.scala:618:33] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire [63:0] _GEN_1 = {58'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35] wire _GEN_2 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_3 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] wire [63:0] _GEN_4 = {58'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [62:0] inflight_1; // @[Monitor.scala:726:35] reg [251:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [2:0] c_first_counter_1; // @[Edges.scala:229:27] wire c_first_1 = c_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _GEN_5 = io_in_c_bits_opcode[2] & io_in_c_bits_opcode[1]; // @[Edges.scala:68:{36,40,51}] wire [63:0] _GEN_6 = {58'h0, io_in_c_bits_source}; // @[OneHot.scala:58:35] wire _GEN_7 = _c_first_T_1 & c_first_1 & _GEN_5; // @[Decoupled.scala:51:35] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] reg [6:0] inflight_2; // @[Monitor.scala:828:27] reg [2:0] d_first_counter_3; // @[Edges.scala:229:27] wire d_first_3 = d_first_counter_3 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _GEN_8 = _d_first_T_3 & d_first_3 & io_in_d_bits_opcode[2] & ~(io_in_d_bits_opcode[1]); // @[Decoupled.scala:51:35] wire [7:0] _d_set_T = 8'h1 << io_in_d_bits_sink; // @[OneHot.scala:58:35] wire [6:0] d_set = _GEN_8 ? _d_set_T[6:0] : 7'h0; // @[OneHot.scala:58:35]
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_61 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_61( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] output io_q // @[ShiftReg.scala:36:14] ); wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_48 : output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node rawIn_exp = bits(io.in, 31, 23) node _rawIn_isZero_T = bits(rawIn_exp, 8, 6) node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0)) node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7) node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3)) wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T) connect rawIn.isNaN, _rawIn_out_isNaN_T_1 node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0)) node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1) connect rawIn.isInf, _rawIn_out_isInf_T_2 connect rawIn.isZero, rawIn_isZero node _rawIn_out_sign_T = bits(io.in, 32, 32) connect rawIn.sign, _rawIn_out_sign_T node _rawIn_out_sExp_T = cvt(rawIn_exp) connect rawIn.sExp, _rawIn_out_sExp_T node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0)) node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T) node _rawIn_out_sig_T_2 = bits(io.in, 22, 0) node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2) connect rawIn.sig, _rawIn_out_sig_T_3 node _io_out_T = shl(io.in, 0) connect io.out, _io_out_T node _io_exceptionFlags_T = bits(rawIn.sig, 22, 22) node _io_exceptionFlags_T_1 = eq(_io_exceptionFlags_T, UInt<1>(0h0)) node _io_exceptionFlags_T_2 = and(rawIn.isNaN, _io_exceptionFlags_T_1) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, UInt<4>(0h0)) connect io.exceptionFlags, _io_exceptionFlags_T_3	module RecFNToRecFN_48( // @[RecFNToRecFN.scala:44:5] input [32:0] io_in, // @[RecFNToRecFN.scala:48:16] output [32:0] io_out // @[RecFNToRecFN.scala:48:16] ); wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5] wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16] wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16] wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35] wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54] wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5] wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5] wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35] wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}] wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46] assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54] assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_80 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_80( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_UInt_5 : input clock : Clock input reset : Reset output io : { flip x : UInt, y : UInt} connect io.y, io.x	module OptimizationBarrier_UInt_5( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [2:0] io_x, // @[package.scala:268:18] output [2:0] io_y // @[package.scala:268:18] ); wire [2:0] io_x_0 = io_x; // @[package.scala:267:30] wire [2:0] io_y_0 = io_x_0; // @[package.scala:267:30] assign io_y = io_y_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TileClockGater : input clock : Clock input reset : Reset output auto : { flip clock_gater_in_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip clock_gater_in_0 : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}}, clock_gater_out : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}}} wire clock_gaterOut : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}} invalidate clock_gaterOut.member.allClocks_uncore.reset invalidate clock_gaterOut.member.allClocks_uncore.clock wire clock_gaterIn : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}} invalidate clock_gaterIn.member.allClocks_uncore.reset invalidate clock_gaterIn.member.allClocks_uncore.clock connect clock_gaterOut, clock_gaterIn wire clock_gaterIn_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate clock_gaterIn_1.d.bits.corrupt invalidate clock_gaterIn_1.d.bits.data invalidate clock_gaterIn_1.d.bits.denied invalidate clock_gaterIn_1.d.bits.sink invalidate clock_gaterIn_1.d.bits.source invalidate clock_gaterIn_1.d.bits.size invalidate clock_gaterIn_1.d.bits.param invalidate clock_gaterIn_1.d.bits.opcode invalidate clock_gaterIn_1.d.valid invalidate clock_gaterIn_1.d.ready invalidate clock_gaterIn_1.a.bits.corrupt invalidate clock_gaterIn_1.a.bits.data invalidate clock_gaterIn_1.a.bits.mask invalidate clock_gaterIn_1.a.bits.address invalidate clock_gaterIn_1.a.bits.source invalidate clock_gaterIn_1.a.bits.size invalidate clock_gaterIn_1.a.bits.param invalidate clock_gaterIn_1.a.bits.opcode invalidate clock_gaterIn_1.a.valid invalidate clock_gaterIn_1.a.ready inst monitor of TLMonitor_42 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, clock_gaterIn_1.d.bits.corrupt connect monitor.io.in.d.bits.data, clock_gaterIn_1.d.bits.data connect monitor.io.in.d.bits.denied, clock_gaterIn_1.d.bits.denied connect monitor.io.in.d.bits.sink, clock_gaterIn_1.d.bits.sink connect monitor.io.in.d.bits.source, clock_gaterIn_1.d.bits.source connect monitor.io.in.d.bits.size, clock_gaterIn_1.d.bits.size connect monitor.io.in.d.bits.param, clock_gaterIn_1.d.bits.param connect monitor.io.in.d.bits.opcode, clock_gaterIn_1.d.bits.opcode connect monitor.io.in.d.valid, clock_gaterIn_1.d.valid connect monitor.io.in.d.ready, clock_gaterIn_1.d.ready connect monitor.io.in.a.bits.corrupt, clock_gaterIn_1.a.bits.corrupt connect monitor.io.in.a.bits.data, clock_gaterIn_1.a.bits.data connect monitor.io.in.a.bits.mask, clock_gaterIn_1.a.bits.mask connect monitor.io.in.a.bits.address, clock_gaterIn_1.a.bits.address connect monitor.io.in.a.bits.source, clock_gaterIn_1.a.bits.source connect monitor.io.in.a.bits.size, clock_gaterIn_1.a.bits.size connect monitor.io.in.a.bits.param, clock_gaterIn_1.a.bits.param connect monitor.io.in.a.bits.opcode, clock_gaterIn_1.a.bits.opcode connect monitor.io.in.a.valid, clock_gaterIn_1.a.valid connect monitor.io.in.a.ready, clock_gaterIn_1.a.ready connect auto.clock_gater_out, clock_gaterOut connect clock_gaterIn, auto.clock_gater_in_0 connect clock_gaterIn_1, auto.clock_gater_in_1 inst regs_0 of AsyncResetRegVec_w1_i1 connect regs_0.clock, clock connect regs_0.reset, clock_gaterIn.member.allClocks_uncore.reset connect clock_gaterOut.member.allClocks_uncore, clock_gaterIn.member.allClocks_uncore wire in : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}} node _in_bits_read_T = eq(clock_gaterIn_1.a.bits.opcode, UInt<3>(0h4)) connect in.bits.read, _in_bits_read_T node _in_bits_index_T = shr(clock_gaterIn_1.a.bits.address, 3) connect in.bits.index, _in_bits_index_T connect in.bits.data, clock_gaterIn_1.a.bits.data connect in.bits.mask, clock_gaterIn_1.a.bits.mask connect in.bits.extra.tlrr_extra.source, clock_gaterIn_1.a.bits.source connect in.bits.extra.tlrr_extra.size, clock_gaterIn_1.a.bits.size wire out : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, data : UInt<64>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}} wire out_front : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}} connect out_front.bits, in.bits node out_maskMatch = not(UInt<9>(0h0)) node out_findex = and(out_front.bits.index, out_maskMatch) node out_bindex = and(out_front.bits.index, out_maskMatch) node _out_T = eq(out_findex, UInt<9>(0h0)) node _out_T_1 = eq(out_bindex, UInt<9>(0h0)) wire out_rivalid : UInt<1>[1] wire out_wivalid : UInt<1>[1] wire out_roready : UInt<1>[1] wire out_woready : UInt<1>[1] node _out_frontMask_T = bits(out_front.bits.mask, 0, 0) node _out_frontMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_frontMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_frontMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_frontMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_frontMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_frontMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_frontMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_frontMask_T_8 = mux(_out_frontMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_9 = mux(_out_frontMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_10 = mux(_out_frontMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_11 = mux(_out_frontMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_12 = mux(_out_frontMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_13 = mux(_out_frontMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_14 = mux(_out_frontMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_15 = mux(_out_frontMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_frontMask_lo_lo = cat(_out_frontMask_T_9, _out_frontMask_T_8) node out_frontMask_lo_hi = cat(_out_frontMask_T_11, _out_frontMask_T_10) node out_frontMask_lo = cat(out_frontMask_lo_hi, out_frontMask_lo_lo) node out_frontMask_hi_lo = cat(_out_frontMask_T_13, _out_frontMask_T_12) node out_frontMask_hi_hi = cat(_out_frontMask_T_15, _out_frontMask_T_14) node out_frontMask_hi = cat(out_frontMask_hi_hi, out_frontMask_hi_lo) node out_frontMask = cat(out_frontMask_hi, out_frontMask_lo) node _out_backMask_T = bits(out_front.bits.mask, 0, 0) node _out_backMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_backMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_backMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_backMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_backMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_backMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_backMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_backMask_T_8 = mux(_out_backMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_9 = mux(_out_backMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_10 = mux(_out_backMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_11 = mux(_out_backMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_12 = mux(_out_backMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_13 = mux(_out_backMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_14 = mux(_out_backMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_15 = mux(_out_backMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_backMask_lo_lo = cat(_out_backMask_T_9, _out_backMask_T_8) node out_backMask_lo_hi = cat(_out_backMask_T_11, _out_backMask_T_10) node out_backMask_lo = cat(out_backMask_lo_hi, out_backMask_lo_lo) node out_backMask_hi_lo = cat(_out_backMask_T_13, _out_backMask_T_12) node out_backMask_hi_hi = cat(_out_backMask_T_15, _out_backMask_T_14) node out_backMask_hi = cat(out_backMask_hi_hi, out_backMask_hi_lo) node out_backMask = cat(out_backMask_hi, out_backMask_lo) node _out_rimask_T = bits(out_frontMask, 0, 0) node out_rimask = orr(_out_rimask_T) node _out_wimask_T = bits(out_frontMask, 0, 0) node out_wimask = andr(_out_wimask_T) node _out_romask_T = bits(out_backMask, 0, 0) node out_romask = orr(_out_romask_T) node _out_womask_T = bits(out_backMask, 0, 0) node out_womask = andr(_out_womask_T) node out_f_rivalid = and(out_rivalid[0], out_rimask) node out_f_roready = and(out_roready[0], out_romask) node out_f_wivalid = and(out_wivalid[0], out_wimask) node out_f_woready = and(out_woready[0], out_womask) node _out_T_2 = bits(out_front.bits.data, 0, 0) connect regs_0.io.en, out_f_woready connect regs_0.io.d, _out_T_2 node _out_T_3 = eq(out_rimask, UInt<1>(0h0)) node _out_T_4 = eq(out_wimask, UInt<1>(0h0)) node _out_T_5 = eq(out_romask, UInt<1>(0h0)) node _out_T_6 = eq(out_womask, UInt<1>(0h0)) node _out_T_7 = or(regs_0.io.q, UInt<1>(0h0)) node _out_T_8 = bits(_out_T_7, 0, 0) node _out_frontSel_T = dshl(UInt<1>(0h1), UInt<1>(0h0)) node out_frontSel_0 = bits(_out_frontSel_T, 0, 0) node out_frontSel_1 = bits(_out_frontSel_T, 1, 1) node _out_backSel_T = dshl(UInt<1>(0h1), UInt<1>(0h0)) node out_backSel_0 = bits(_out_backSel_T, 0, 0) node out_backSel_1 = bits(_out_backSel_T, 1, 1) node _out_rifireMux_T = and(in.valid, out_front.ready) node _out_rifireMux_T_1 = and(_out_rifireMux_T, out_front.bits.read) wire out_rifireMux_out : UInt<1> node _out_rifireMux_T_2 = and(_out_rifireMux_T_1, out_frontSel_0) node _out_rifireMux_T_3 = and(_out_rifireMux_T_2, _out_T) connect out_rifireMux_out, UInt<1>(0h1) connect out_rivalid[0], _out_rifireMux_T_3 node _out_rifireMux_T_4 = eq(_out_T, UInt<1>(0h0)) node _out_rifireMux_T_5 = or(out_rifireMux_out, _out_rifireMux_T_4) node _out_rifireMux_T_6 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_rifireMux_WIRE : UInt<1>[1] connect _out_rifireMux_WIRE[0], _out_rifireMux_T_5 node out_rifireMux = mux(_out_rifireMux_T_6, UInt<1>(0h1), _out_rifireMux_WIRE[0]) node _out_wifireMux_T = and(in.valid, out_front.ready) node _out_wifireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wifireMux_T_2 = and(_out_wifireMux_T, _out_wifireMux_T_1) wire out_wifireMux_out : UInt<1> node _out_wifireMux_T_3 = and(_out_wifireMux_T_2, out_frontSel_0) node _out_wifireMux_T_4 = and(_out_wifireMux_T_3, _out_T) connect out_wifireMux_out, UInt<1>(0h1) connect out_wivalid[0], _out_wifireMux_T_4 node _out_wifireMux_T_5 = eq(_out_T, UInt<1>(0h0)) node _out_wifireMux_T_6 = or(out_wifireMux_out, _out_wifireMux_T_5) node _out_wifireMux_T_7 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_wifireMux_WIRE : UInt<1>[1] connect _out_wifireMux_WIRE[0], _out_wifireMux_T_6 node out_wifireMux = mux(_out_wifireMux_T_7, UInt<1>(0h1), _out_wifireMux_WIRE[0]) node _out_rofireMux_T = and(out_front.valid, out.ready) node _out_rofireMux_T_1 = and(_out_rofireMux_T, out_front.bits.read) wire out_rofireMux_out : UInt<1> node _out_rofireMux_T_2 = and(_out_rofireMux_T_1, out_backSel_0) node _out_rofireMux_T_3 = and(_out_rofireMux_T_2, _out_T_1) connect out_rofireMux_out, UInt<1>(0h1) connect out_roready[0], _out_rofireMux_T_3 node _out_rofireMux_T_4 = eq(_out_T_1, UInt<1>(0h0)) node _out_rofireMux_T_5 = or(out_rofireMux_out, _out_rofireMux_T_4) node _out_rofireMux_T_6 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_rofireMux_WIRE : UInt<1>[1] connect _out_rofireMux_WIRE[0], _out_rofireMux_T_5 node out_rofireMux = mux(_out_rofireMux_T_6, UInt<1>(0h1), _out_rofireMux_WIRE[0]) node _out_wofireMux_T = and(out_front.valid, out.ready) node _out_wofireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wofireMux_T_2 = and(_out_wofireMux_T, _out_wofireMux_T_1) wire out_wofireMux_out : UInt<1> node _out_wofireMux_T_3 = and(_out_wofireMux_T_2, out_backSel_0) node _out_wofireMux_T_4 = and(_out_wofireMux_T_3, _out_T_1) connect out_wofireMux_out, UInt<1>(0h1) connect out_woready[0], _out_wofireMux_T_4 node _out_wofireMux_T_5 = eq(_out_T_1, UInt<1>(0h0)) node _out_wofireMux_T_6 = or(out_wofireMux_out, _out_wofireMux_T_5) node _out_wofireMux_T_7 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_wofireMux_WIRE : UInt<1>[1] connect _out_wofireMux_WIRE[0], _out_wofireMux_T_6 node out_wofireMux = mux(_out_wofireMux_T_7, UInt<1>(0h1), _out_wofireMux_WIRE[0]) node out_iready = mux(out_front.bits.read, out_rifireMux, out_wifireMux) node out_oready = mux(out_front.bits.read, out_rofireMux, out_wofireMux) node _out_in_ready_T = and(out_front.ready, out_iready) connect in.ready, _out_in_ready_T node _out_front_valid_T = and(in.valid, out_iready) connect out_front.valid, _out_front_valid_T node _out_front_ready_T = and(out.ready, out_oready) connect out_front.ready, _out_front_ready_T node _out_out_valid_T = and(out_front.valid, out_oready) connect out.valid, _out_out_valid_T connect out.bits.read, out_front.bits.read node _out_out_bits_data_T = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_out_bits_data_WIRE : UInt<1>[1] connect _out_out_bits_data_WIRE[0], _out_T_1 node _out_out_bits_data_T_1 = mux(_out_out_bits_data_T, UInt<1>(0h1), _out_out_bits_data_WIRE[0]) node _out_out_bits_data_T_2 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_out_bits_data_WIRE_1 : UInt<1>[1] connect _out_out_bits_data_WIRE_1[0], _out_T_8 node _out_out_bits_data_T_3 = mux(_out_out_bits_data_T_2, UInt<1>(0h0), _out_out_bits_data_WIRE_1[0]) node _out_out_bits_data_T_4 = mux(_out_out_bits_data_T_1, _out_out_bits_data_T_3, UInt<1>(0h0)) connect out.bits.data, _out_out_bits_data_T_4 connect out.bits.extra, out_front.bits.extra connect in.valid, clock_gaterIn_1.a.valid connect clock_gaterIn_1.a.ready, in.ready connect clock_gaterIn_1.d.valid, out.valid connect out.ready, clock_gaterIn_1.d.ready wire clock_gaterIn_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} connect clock_gaterIn_d_bits_d.opcode, UInt<1>(0h0) connect clock_gaterIn_d_bits_d.param, UInt<1>(0h0) connect clock_gaterIn_d_bits_d.size, out.bits.extra.tlrr_extra.size connect clock_gaterIn_d_bits_d.source, out.bits.extra.tlrr_extra.source connect clock_gaterIn_d_bits_d.sink, UInt<1>(0h0) connect clock_gaterIn_d_bits_d.denied, UInt<1>(0h0) invalidate clock_gaterIn_d_bits_d.data connect clock_gaterIn_d_bits_d.corrupt, UInt<1>(0h0) connect clock_gaterIn_1.d.bits.corrupt, clock_gaterIn_d_bits_d.corrupt connect clock_gaterIn_1.d.bits.data, clock_gaterIn_d_bits_d.data connect clock_gaterIn_1.d.bits.denied, clock_gaterIn_d_bits_d.denied connect clock_gaterIn_1.d.bits.sink, clock_gaterIn_d_bits_d.sink connect clock_gaterIn_1.d.bits.source, clock_gaterIn_d_bits_d.source connect clock_gaterIn_1.d.bits.size, clock_gaterIn_d_bits_d.size connect clock_gaterIn_1.d.bits.param, clock_gaterIn_d_bits_d.param connect clock_gaterIn_1.d.bits.opcode, clock_gaterIn_d_bits_d.opcode connect clock_gaterIn_1.d.bits.data, out.bits.data node _clock_gaterIn_d_bits_opcode_T = mux(out.bits.read, UInt<1>(0h1), UInt<1>(0h0)) connect clock_gaterIn_1.d.bits.opcode, _clock_gaterIn_d_bits_opcode_T wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<21>(0h0) connect _WIRE.bits.source, UInt<11>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<21>(0h0) connect _WIRE_2.bits.source, UInt<11>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) extmodule plusarg_reader_88 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_89 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32	module TileClockGater( // @[TileClockGater.scala:27:25] input clock, // @[TileClockGater.scala:27:25] input reset, // @[TileClockGater.scala:27:25] output auto_clock_gater_in_1_a_ready, // @[LazyModuleImp.scala:107:25] input auto_clock_gater_in_1_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_clock_gater_in_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_clock_gater_in_1_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_clock_gater_in_1_a_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_clock_gater_in_1_a_bits_source, // @[LazyModuleImp.scala:107:25] input [20:0] auto_clock_gater_in_1_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_clock_gater_in_1_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_clock_gater_in_1_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_clock_gater_in_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_clock_gater_in_1_d_ready, // @[LazyModuleImp.scala:107:25] output auto_clock_gater_in_1_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_clock_gater_in_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_clock_gater_in_1_d_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_clock_gater_in_1_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_clock_gater_in_1_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_clock_gater_in_0_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25] input auto_clock_gater_in_0_member_allClocks_uncore_reset, // @[LazyModuleImp.scala:107:25] output auto_clock_gater_out_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25] output auto_clock_gater_out_member_allClocks_uncore_reset // @[LazyModuleImp.scala:107:25] ); wire out_front_valid; // @[RegisterRouter.scala:87:24] wire out_front_ready; // @[RegisterRouter.scala:87:24] wire out_bits_read; // @[RegisterRouter.scala:87:24] wire [10:0] out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [8:0] in_bits_index; // @[RegisterRouter.scala:73:18] wire in_bits_read; // @[RegisterRouter.scala:73:18] wire auto_clock_gater_in_1_a_valid_0 = auto_clock_gater_in_1_a_valid; // @[TileClockGater.scala:27:25] wire [2:0] auto_clock_gater_in_1_a_bits_opcode_0 = auto_clock_gater_in_1_a_bits_opcode; // @[TileClockGater.scala:27:25] wire [2:0] auto_clock_gater_in_1_a_bits_param_0 = auto_clock_gater_in_1_a_bits_param; // @[TileClockGater.scala:27:25] wire [1:0] auto_clock_gater_in_1_a_bits_size_0 = auto_clock_gater_in_1_a_bits_size; // @[TileClockGater.scala:27:25] wire [10:0] auto_clock_gater_in_1_a_bits_source_0 = auto_clock_gater_in_1_a_bits_source; // @[TileClockGater.scala:27:25] wire [20:0] auto_clock_gater_in_1_a_bits_address_0 = auto_clock_gater_in_1_a_bits_address; // @[TileClockGater.scala:27:25] wire [7:0] auto_clock_gater_in_1_a_bits_mask_0 = auto_clock_gater_in_1_a_bits_mask; // @[TileClockGater.scala:27:25] wire [63:0] auto_clock_gater_in_1_a_bits_data_0 = auto_clock_gater_in_1_a_bits_data; // @[TileClockGater.scala:27:25] wire auto_clock_gater_in_1_a_bits_corrupt_0 = auto_clock_gater_in_1_a_bits_corrupt; // @[TileClockGater.scala:27:25] wire auto_clock_gater_in_1_d_ready_0 = auto_clock_gater_in_1_d_ready; // @[TileClockGater.scala:27:25] wire auto_clock_gater_in_0_member_allClocks_uncore_clock_0 = auto_clock_gater_in_0_member_allClocks_uncore_clock; // @[TileClockGater.scala:27:25] wire auto_clock_gater_in_0_member_allClocks_uncore_reset_0 = auto_clock_gater_in_0_member_allClocks_uncore_reset; // @[TileClockGater.scala:27:25] wire [1:0] _out_frontSel_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _out_backSel_T = 2'h1; // @[OneHot.scala:58:35] wire [8:0] out_maskMatch = 9'h1FF; // @[RegisterRouter.scala:87:24] wire out_frontSel_0 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_backSel_0 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_rofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_iready = 1'h1; // @[RegisterRouter.scala:87:24] wire out_oready = 1'h1; // @[RegisterRouter.scala:87:24] wire [2:0] clock_gaterIn_d_bits_d_opcode = 3'h0; // @[Edges.scala:792:17] wire [63:0] clock_gaterIn_d_bits_d_data = 64'h0; // @[Edges.scala:792:17] wire auto_clock_gater_in_1_d_bits_sink = 1'h0; // @[TileClockGater.scala:27:25] wire auto_clock_gater_in_1_d_bits_denied = 1'h0; // @[TileClockGater.scala:27:25] wire auto_clock_gater_in_1_d_bits_corrupt = 1'h0; // @[TileClockGater.scala:27:25] wire clock_gaterIn_1_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire clock_gaterIn_1_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire clock_gaterIn_1_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire out_frontSel_1 = 1'h0; // @[RegisterRouter.scala:87:24] wire out_backSel_1 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_6 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wifireMux_T_7 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_rofireMux_T_6 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wofireMux_T_7 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T_2 = 1'h0; // @[MuxLiteral.scala:49:17] wire clock_gaterIn_d_bits_d_sink = 1'h0; // @[Edges.scala:792:17] wire clock_gaterIn_d_bits_d_denied = 1'h0; // @[Edges.scala:792:17] wire clock_gaterIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:792:17] wire [1:0] auto_clock_gater_in_1_d_bits_param = 2'h0; // @[TileClockGater.scala:27:25] wire clock_gaterIn_1_a_ready; // @[MixedNode.scala:551:17] wire [1:0] clock_gaterIn_1_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] clock_gaterIn_d_bits_d_param = 2'h0; // @[Edges.scala:792:17] wire clock_gaterIn_1_a_valid = auto_clock_gater_in_1_a_valid_0; // @[MixedNode.scala:551:17] wire [2:0] clock_gaterIn_1_a_bits_opcode = auto_clock_gater_in_1_a_bits_opcode_0; // @[MixedNode.scala:551:17] wire [2:0] clock_gaterIn_1_a_bits_param = auto_clock_gater_in_1_a_bits_param_0; // @[MixedNode.scala:551:17] wire [1:0] clock_gaterIn_1_a_bits_size = auto_clock_gater_in_1_a_bits_size_0; // @[MixedNode.scala:551:17] wire [10:0] clock_gaterIn_1_a_bits_source = auto_clock_gater_in_1_a_bits_source_0; // @[MixedNode.scala:551:17] wire [20:0] clock_gaterIn_1_a_bits_address = auto_clock_gater_in_1_a_bits_address_0; // @[MixedNode.scala:551:17] wire [7:0] clock_gaterIn_1_a_bits_mask = auto_clock_gater_in_1_a_bits_mask_0; // @[MixedNode.scala:551:17] wire [63:0] clock_gaterIn_1_a_bits_data = auto_clock_gater_in_1_a_bits_data_0; // @[MixedNode.scala:551:17] wire clock_gaterIn_1_a_bits_corrupt = auto_clock_gater_in_1_a_bits_corrupt_0; // @[MixedNode.scala:551:17] wire clock_gaterIn_1_d_ready = auto_clock_gater_in_1_d_ready_0; // @[MixedNode.scala:551:17] wire clock_gaterIn_1_d_valid; // @[MixedNode.scala:551:17] wire [2:0] clock_gaterIn_1_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] clock_gaterIn_1_d_bits_size; // @[MixedNode.scala:551:17] wire [10:0] clock_gaterIn_1_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] clock_gaterIn_1_d_bits_data; // @[MixedNode.scala:551:17] wire clock_gaterIn_member_allClocks_uncore_clock = auto_clock_gater_in_0_member_allClocks_uncore_clock_0; // @[MixedNode.scala:551:17] wire clock_gaterOut_member_allClocks_uncore_clock; // @[MixedNode.scala:542:17] wire clock_gaterIn_member_allClocks_uncore_reset = auto_clock_gater_in_0_member_allClocks_uncore_reset_0; // @[MixedNode.scala:551:17] wire clock_gaterOut_member_allClocks_uncore_reset; // @[MixedNode.scala:542:17] wire auto_clock_gater_in_1_a_ready_0; // @[TileClockGater.scala:27:25] wire [2:0] auto_clock_gater_in_1_d_bits_opcode_0; // @[TileClockGater.scala:27:25] wire [1:0] auto_clock_gater_in_1_d_bits_size_0; // @[TileClockGater.scala:27:25] wire [10:0] auto_clock_gater_in_1_d_bits_source_0; // @[TileClockGater.scala:27:25] wire [63:0] auto_clock_gater_in_1_d_bits_data_0; // @[TileClockGater.scala:27:25] wire auto_clock_gater_in_1_d_valid_0; // @[TileClockGater.scala:27:25] wire auto_clock_gater_out_member_allClocks_uncore_clock_0; // @[TileClockGater.scala:27:25] wire auto_clock_gater_out_member_allClocks_uncore_reset_0; // @[TileClockGater.scala:27:25] assign auto_clock_gater_out_member_allClocks_uncore_clock_0 = clock_gaterOut_member_allClocks_uncore_clock; // @[MixedNode.scala:542:17] assign auto_clock_gater_out_member_allClocks_uncore_reset_0 = clock_gaterOut_member_allClocks_uncore_reset; // @[MixedNode.scala:542:17] assign clock_gaterOut_member_allClocks_uncore_clock = clock_gaterIn_member_allClocks_uncore_clock; // @[MixedNode.scala:542:17, :551:17] assign clock_gaterOut_member_allClocks_uncore_reset = clock_gaterIn_member_allClocks_uncore_reset; // @[MixedNode.scala:542:17, :551:17] wire in_ready; // @[RegisterRouter.scala:73:18] assign auto_clock_gater_in_1_a_ready_0 = clock_gaterIn_1_a_ready; // @[MixedNode.scala:551:17] wire in_valid = clock_gaterIn_1_a_valid; // @[RegisterRouter.scala:73:18] wire [1:0] in_bits_extra_tlrr_extra_size = clock_gaterIn_1_a_bits_size; // @[RegisterRouter.scala:73:18] wire [10:0] in_bits_extra_tlrr_extra_source = clock_gaterIn_1_a_bits_source; // @[RegisterRouter.scala:73:18] wire [7:0] in_bits_mask = clock_gaterIn_1_a_bits_mask; // @[RegisterRouter.scala:73:18] wire [63:0] in_bits_data = clock_gaterIn_1_a_bits_data; // @[RegisterRouter.scala:73:18] wire out_ready = clock_gaterIn_1_d_ready; // @[RegisterRouter.scala:87:24] wire out_valid; // @[RegisterRouter.scala:87:24] assign auto_clock_gater_in_1_d_valid_0 = clock_gaterIn_1_d_valid; // @[MixedNode.scala:551:17] assign auto_clock_gater_in_1_d_bits_opcode_0 = clock_gaterIn_1_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] clock_gaterIn_d_bits_d_size; // @[Edges.scala:792:17] assign auto_clock_gater_in_1_d_bits_size_0 = clock_gaterIn_1_d_bits_size; // @[MixedNode.scala:551:17] wire [10:0] clock_gaterIn_d_bits_d_source; // @[Edges.scala:792:17] assign auto_clock_gater_in_1_d_bits_source_0 = clock_gaterIn_1_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] out_bits_data; // @[RegisterRouter.scala:87:24] assign auto_clock_gater_in_1_d_bits_data_0 = clock_gaterIn_1_d_bits_data; // @[MixedNode.scala:551:17] wire _out_in_ready_T; // @[RegisterRouter.scala:87:24] assign clock_gaterIn_1_a_ready = in_ready; // @[RegisterRouter.scala:73:18] wire _in_bits_read_T; // @[RegisterRouter.scala:74:36] wire _out_front_valid_T = in_valid; // @[RegisterRouter.scala:73:18, :87:24] wire out_front_bits_read = in_bits_read; // @[RegisterRouter.scala:73:18, :87:24] wire [8:0] out_front_bits_index = in_bits_index; // @[RegisterRouter.scala:73:18, :87:24] wire [63:0] out_front_bits_data = in_bits_data; // @[RegisterRouter.scala:73:18, :87:24] wire [7:0] out_front_bits_mask = in_bits_mask; // @[RegisterRouter.scala:73:18, :87:24] wire [10:0] out_front_bits_extra_tlrr_extra_source = in_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:73:18, :87:24] wire [1:0] out_front_bits_extra_tlrr_extra_size = in_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:73:18, :87:24] assign _in_bits_read_T = clock_gaterIn_1_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36] assign in_bits_read = _in_bits_read_T; // @[RegisterRouter.scala:73:18, :74:36] wire [17:0] _in_bits_index_T = clock_gaterIn_1_a_bits_address[20:3]; // @[Edges.scala:192:34] assign in_bits_index = _in_bits_index_T[8:0]; // @[RegisterRouter.scala:73:18, :75:19] wire _out_front_ready_T = out_ready; // @[RegisterRouter.scala:87:24] wire _out_out_valid_T; // @[RegisterRouter.scala:87:24] assign clock_gaterIn_1_d_valid = out_valid; // @[RegisterRouter.scala:87:24] wire _clock_gaterIn_d_bits_opcode_T = out_bits_read; // @[RegisterRouter.scala:87:24, :105:25] assign clock_gaterIn_1_d_bits_data = out_bits_data; // @[RegisterRouter.scala:87:24] assign clock_gaterIn_d_bits_d_source = out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [1:0] out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign clock_gaterIn_d_bits_d_size = out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign _out_in_ready_T = out_front_ready; // @[RegisterRouter.scala:87:24] assign _out_out_valid_T = out_front_valid; // @[RegisterRouter.scala:87:24] assign out_bits_read = out_front_bits_read; // @[RegisterRouter.scala:87:24] wire [8:0] out_findex = out_front_bits_index; // @[RegisterRouter.scala:87:24] wire [8:0] out_bindex = out_front_bits_index; // @[RegisterRouter.scala:87:24] assign out_bits_extra_tlrr_extra_source = out_front_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] assign out_bits_extra_tlrr_extra_size = out_front_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] wire _out_T = out_findex == 9'h0; // @[RegisterRouter.scala:87:24] wire _out_T_1 = out_bindex == 9'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_0 = _out_T_1; // @[MuxLiteral.scala:49:48] wire out_rivalid_0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire out_wivalid_0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire out_roready_0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire out_woready_0; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_8 = {8{_out_frontMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_9 = {8{_out_frontMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_10 = {8{_out_frontMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_11 = {8{_out_frontMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_12 = {8{_out_frontMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_13 = {8{_out_frontMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_14 = {8{_out_frontMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_15 = {8{_out_frontMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_lo = {_out_frontMask_T_9, _out_frontMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_hi = {_out_frontMask_T_11, _out_frontMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_lo = {out_frontMask_lo_hi, out_frontMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_lo = {_out_frontMask_T_13, _out_frontMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_hi = {_out_frontMask_T_15, _out_frontMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_hi = {out_frontMask_hi_hi, out_frontMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_frontMask = {out_frontMask_hi, out_frontMask_lo}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_8 = {8{_out_backMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_9 = {8{_out_backMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_10 = {8{_out_backMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_11 = {8{_out_backMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_12 = {8{_out_backMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_13 = {8{_out_backMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_14 = {8{_out_backMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_15 = {8{_out_backMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_lo = {_out_backMask_T_9, _out_backMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_hi = {_out_backMask_T_11, _out_backMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_lo = {out_backMask_lo_hi, out_backMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_lo = {_out_backMask_T_13, _out_backMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_hi = {_out_backMask_T_15, _out_backMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_hi = {out_backMask_hi_hi, out_backMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_backMask = {out_backMask_hi, out_backMask_lo}; // @[RegisterRouter.scala:87:24] wire _out_rimask_T = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire out_rimask = _out_rimask_T; // @[RegisterRouter.scala:87:24] wire out_wimask = _out_wimask_T; // @[RegisterRouter.scala:87:24] wire _out_romask_T = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_womask_T = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire out_romask = _out_romask_T; // @[RegisterRouter.scala:87:24] wire out_womask = _out_womask_T; // @[RegisterRouter.scala:87:24] wire out_f_rivalid = out_rivalid_0 & out_rimask; // @[RegisterRouter.scala:87:24] wire out_f_roready = out_roready_0 & out_romask; // @[RegisterRouter.scala:87:24] wire out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala:87:24] wire out_f_woready = out_woready_0 & out_womask; // @[RegisterRouter.scala:87:24] wire _out_T_2 = out_front_bits_data[0]; // @[RegisterRouter.scala:87:24] wire _out_T_3 = ~out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_4 = ~out_wimask; // @[RegisterRouter.scala:87:24] wire _out_T_5 = ~out_romask; // @[RegisterRouter.scala:87:24] wire _out_T_6 = ~out_womask; // @[RegisterRouter.scala:87:24] wire _out_T_7; // @[RegisterRouter.scala:87:24] wire _out_T_8 = _out_T_7; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_1_0 = _out_T_8; // @[MuxLiteral.scala:49:48] wire _GEN = in_valid & out_front_ready; // @[RegisterRouter.scala:73:18, :87:24] wire _out_rifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T = _GEN; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T = _GEN; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1 = _out_rifireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_2 = _out_rifireMux_T_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_3 = _out_rifireMux_T_2 & _out_T; // @[RegisterRouter.scala:87:24] assign out_rivalid_0 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_4 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_2 = _out_wifireMux_T & _out_wifireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_3 = _out_wifireMux_T_2; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_4 = _out_wifireMux_T_3 & _out_T; // @[RegisterRouter.scala:87:24] assign out_wivalid_0 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_5 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _GEN_0 = out_front_valid & out_ready; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1 = _out_rofireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_2 = _out_rofireMux_T_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_3 = _out_rofireMux_T_2 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_roready_0 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_4 = ~_out_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_2 = _out_wofireMux_T & _out_wofireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_3 = _out_wofireMux_T_2; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_4 = _out_wofireMux_T_3 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_woready_0 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_5 = ~_out_T_1; // @[RegisterRouter.scala:87:24] assign in_ready = _out_in_ready_T; // @[RegisterRouter.scala:73:18, :87:24] assign out_front_valid = _out_front_valid_T; // @[RegisterRouter.scala:87:24] assign out_front_ready = _out_front_ready_T; // @[RegisterRouter.scala:87:24] assign out_valid = _out_out_valid_T; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_T_1 = _out_out_bits_data_WIRE_0; // @[MuxLiteral.scala:49:{10,48}] wire _out_out_bits_data_T_3 = _out_out_bits_data_WIRE_1_0; // @[MuxLiteral.scala:49:{10,48}] wire _out_out_bits_data_T_4 = _out_out_bits_data_T_1 & _out_out_bits_data_T_3; // @[MuxLiteral.scala:49:10] assign out_bits_data = {63'h0, _out_out_bits_data_T_4}; // @[RegisterRouter.scala:87:24] assign clock_gaterIn_1_d_bits_size = clock_gaterIn_d_bits_d_size; // @[Edges.scala:792:17] assign clock_gaterIn_1_d_bits_source = clock_gaterIn_d_bits_d_source; // @[Edges.scala:792:17] assign clock_gaterIn_1_d_bits_opcode = {2'h0, _clock_gaterIn_d_bits_opcode_T}; // @[RegisterRouter.scala:105:{19,25}] TLMonitor_42 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (clock_gaterIn_1_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (clock_gaterIn_1_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (clock_gaterIn_1_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (clock_gaterIn_1_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (clock_gaterIn_1_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (clock_gaterIn_1_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (clock_gaterIn_1_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (clock_gaterIn_1_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (clock_gaterIn_1_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (clock_gaterIn_1_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (clock_gaterIn_1_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (clock_gaterIn_1_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (clock_gaterIn_1_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_size (clock_gaterIn_1_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (clock_gaterIn_1_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_data (clock_gaterIn_1_d_bits_data) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] AsyncResetRegVec_w1_i1 regs_0 ( // @[TileClockGater.scala:33:53] .clock (clock), .reset (clock_gaterIn_member_allClocks_uncore_reset), // @[MixedNode.scala:551:17] .io_d (_out_T_2), // @[RegisterRouter.scala:87:24] .io_q (_out_T_7), .io_en (out_f_woready) // @[RegisterRouter.scala:87:24] ); // @[TileClockGater.scala:33:53] assign auto_clock_gater_in_1_a_ready = auto_clock_gater_in_1_a_ready_0; // @[TileClockGater.scala:27:25] assign auto_clock_gater_in_1_d_valid = auto_clock_gater_in_1_d_valid_0; // @[TileClockGater.scala:27:25] assign auto_clock_gater_in_1_d_bits_opcode = auto_clock_gater_in_1_d_bits_opcode_0; // @[TileClockGater.scala:27:25] assign auto_clock_gater_in_1_d_bits_size = auto_clock_gater_in_1_d_bits_size_0; // @[TileClockGater.scala:27:25] assign auto_clock_gater_in_1_d_bits_source = auto_clock_gater_in_1_d_bits_source_0; // @[TileClockGater.scala:27:25] assign auto_clock_gater_in_1_d_bits_data = auto_clock_gater_in_1_d_bits_data_0; // @[TileClockGater.scala:27:25] assign auto_clock_gater_out_member_allClocks_uncore_clock = auto_clock_gater_out_member_allClocks_uncore_clock_0; // @[TileClockGater.scala:27:25] assign auto_clock_gater_out_member_allClocks_uncore_reset = auto_clock_gater_out_member_allClocks_uncore_reset_0; // @[TileClockGater.scala:27:25] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLFragmenter_Debug : input clock : Clock input reset : Reset output auto : { flip anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate anonIn.d.bits.corrupt invalidate anonIn.d.bits.data invalidate anonIn.d.bits.denied invalidate anonIn.d.bits.sink invalidate anonIn.d.bits.source invalidate anonIn.d.bits.size invalidate anonIn.d.bits.param invalidate anonIn.d.bits.opcode invalidate anonIn.d.valid invalidate anonIn.d.ready invalidate anonIn.a.bits.corrupt invalidate anonIn.a.bits.data invalidate anonIn.a.bits.mask invalidate anonIn.a.bits.address invalidate anonIn.a.bits.source invalidate anonIn.a.bits.size invalidate anonIn.a.bits.param invalidate anonIn.a.bits.opcode invalidate anonIn.a.valid invalidate anonIn.a.ready inst monitor of TLMonitor_38 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, anonIn.d.bits.corrupt connect monitor.io.in.d.bits.data, anonIn.d.bits.data connect monitor.io.in.d.bits.denied, anonIn.d.bits.denied connect monitor.io.in.d.bits.sink, anonIn.d.bits.sink connect monitor.io.in.d.bits.source, anonIn.d.bits.source connect monitor.io.in.d.bits.size, anonIn.d.bits.size connect monitor.io.in.d.bits.param, anonIn.d.bits.param connect monitor.io.in.d.bits.opcode, anonIn.d.bits.opcode connect monitor.io.in.d.valid, anonIn.d.valid connect monitor.io.in.d.ready, anonIn.d.ready connect monitor.io.in.a.bits.corrupt, anonIn.a.bits.corrupt connect monitor.io.in.a.bits.data, anonIn.a.bits.data connect monitor.io.in.a.bits.mask, anonIn.a.bits.mask connect monitor.io.in.a.bits.address, anonIn.a.bits.address connect monitor.io.in.a.bits.source, anonIn.a.bits.source connect monitor.io.in.a.bits.size, anonIn.a.bits.size connect monitor.io.in.a.bits.param, anonIn.a.bits.param connect monitor.io.in.a.bits.opcode, anonIn.a.bits.opcode connect monitor.io.in.a.valid, anonIn.a.valid connect monitor.io.in.a.ready, anonIn.a.ready wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate anonOut.d.bits.corrupt invalidate anonOut.d.bits.data invalidate anonOut.d.bits.denied invalidate anonOut.d.bits.sink invalidate anonOut.d.bits.source invalidate anonOut.d.bits.size invalidate anonOut.d.bits.param invalidate anonOut.d.bits.opcode invalidate anonOut.d.valid invalidate anonOut.d.ready invalidate anonOut.a.bits.corrupt invalidate anonOut.a.bits.data invalidate anonOut.a.bits.mask invalidate anonOut.a.bits.address invalidate anonOut.a.bits.source invalidate anonOut.a.bits.size invalidate anonOut.a.bits.param invalidate anonOut.a.bits.opcode invalidate anonOut.a.valid invalidate anonOut.a.ready connect auto.anon_out, anonOut connect anonIn, auto.anon_in regreset acknum : UInt<3>, clock, reset, UInt<3>(0h0) reg dOrig : UInt, clock regreset dToggle : UInt<1>, clock, reset, UInt<1>(0h0) node dFragnum = bits(anonOut.d.bits.source, 2, 0) node dFirst = eq(acknum, UInt<1>(0h0)) node dLast = eq(dFragnum, UInt<1>(0h0)) node dsizeOH_shiftAmount = bits(anonOut.d.bits.size, 1, 0) node _dsizeOH_T = dshl(UInt<1>(0h1), dsizeOH_shiftAmount) node dsizeOH = bits(_dsizeOH_T, 3, 0) node _dsizeOH1_T = dshl(UInt<3>(0h7), anonOut.d.bits.size) node _dsizeOH1_T_1 = bits(_dsizeOH1_T, 2, 0) node dsizeOH1 = not(_dsizeOH1_T_1) node dHasData = bits(anonOut.d.bits.opcode, 0, 0) node acknum_fragment = shl(dFragnum, 0) node acknum_size = shr(dsizeOH1, 3) node _T = eq(anonOut.d.valid, UInt<1>(0h0)) node _T_1 = and(acknum_fragment, acknum_size) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = or(_T, _T_2) node _T_4 = asUInt(reset) node _T_5 = eq(_T_4, UInt<1>(0h0)) when _T_5 : node _T_6 = eq(_T_3, UInt<1>(0h0)) when _T_6 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:214 assert (!out.d.valid \|\| (acknum_fragment & acknum_size) === 0.U)\n") : printf assert(clock, _T_3, UInt<1>(0h1), "") : assert node _dFirst_acknum_T = mux(dHasData, acknum_size, UInt<1>(0h0)) node dFirst_acknum = or(acknum_fragment, _dFirst_acknum_T) node _ack_decrement_T = shr(dsizeOH, 3) node ack_decrement = mux(dHasData, UInt<1>(0h1), _ack_decrement_T) node _dFirst_size_T = shl(dFragnum, 3) node _dFirst_size_T_1 = or(_dFirst_size_T, dsizeOH1) node _dFirst_size_T_2 = shl(_dFirst_size_T_1, 1) node _dFirst_size_T_3 = or(_dFirst_size_T_2, UInt<1>(0h1)) node _dFirst_size_T_4 = cat(UInt<1>(0h0), _dFirst_size_T_1) node _dFirst_size_T_5 = not(_dFirst_size_T_4) node _dFirst_size_T_6 = and(_dFirst_size_T_3, _dFirst_size_T_5) node dFirst_size_hi = bits(_dFirst_size_T_6, 6, 4) node dFirst_size_lo = bits(_dFirst_size_T_6, 3, 0) node _dFirst_size_T_7 = orr(dFirst_size_hi) node _dFirst_size_T_8 = or(dFirst_size_hi, dFirst_size_lo) node dFirst_size_hi_1 = bits(_dFirst_size_T_8, 3, 2) node dFirst_size_lo_1 = bits(_dFirst_size_T_8, 1, 0) node _dFirst_size_T_9 = orr(dFirst_size_hi_1) node _dFirst_size_T_10 = or(dFirst_size_hi_1, dFirst_size_lo_1) node _dFirst_size_T_11 = bits(_dFirst_size_T_10, 1, 1) node _dFirst_size_T_12 = cat(_dFirst_size_T_9, _dFirst_size_T_11) node dFirst_size = cat(_dFirst_size_T_7, _dFirst_size_T_12) node _T_7 = and(anonOut.d.ready, anonOut.d.valid) when _T_7 : node _acknum_T = sub(acknum, ack_decrement) node _acknum_T_1 = tail(_acknum_T, 1) node _acknum_T_2 = mux(dFirst, dFirst_acknum, _acknum_T_1) connect acknum, _acknum_T_2 when dFirst : connect dOrig, dFirst_size node _dToggle_T = bits(anonOut.d.bits.source, 3, 3) connect dToggle, _dToggle_T node _drop_T = eq(dHasData, UInt<1>(0h0)) node _drop_T_1 = mux(UInt<1>(0h0), dFirst, dLast) node _drop_T_2 = eq(_drop_T_1, UInt<1>(0h0)) node drop = and(_drop_T, _drop_T_2) node _anonOut_d_ready_T = or(anonIn.d.ready, drop) connect anonOut.d.ready, _anonOut_d_ready_T node _anonIn_d_valid_T = eq(drop, UInt<1>(0h0)) node _anonIn_d_valid_T_1 = and(anonOut.d.valid, _anonIn_d_valid_T) connect anonIn.d.valid, _anonIn_d_valid_T_1 connect anonIn.d.bits.corrupt, anonOut.d.bits.corrupt connect anonIn.d.bits.data, anonOut.d.bits.data connect anonIn.d.bits.denied, anonOut.d.bits.denied connect anonIn.d.bits.sink, anonOut.d.bits.sink connect anonIn.d.bits.source, anonOut.d.bits.source connect anonIn.d.bits.size, anonOut.d.bits.size connect anonIn.d.bits.param, anonOut.d.bits.param connect anonIn.d.bits.opcode, anonOut.d.bits.opcode node _anonIn_d_bits_source_T = shr(anonOut.d.bits.source, 4) connect anonIn.d.bits.source, _anonIn_d_bits_source_T node _anonIn_d_bits_size_T = mux(dFirst, dFirst_size, dOrig) connect anonIn.d.bits.size, _anonIn_d_bits_size_T inst repeater of Repeater_TLBundleA_a12d64s8k1z3u connect repeater.clock, clock connect repeater.reset, reset connect repeater.io.enq, anonIn.a node _find_T = xor(repeater.io.deq.bits.address, UInt<1>(0h0)) node _find_T_1 = cvt(_find_T) node _find_T_2 = and(_find_T_1, asSInt(UInt<1>(0h0))) node _find_T_3 = asSInt(_find_T_2) node _find_T_4 = eq(_find_T_3, asSInt(UInt<1>(0h0))) wire find : UInt<1>[1] connect find[0], _find_T_4 node _limit_T = eq(UInt<1>(0h0), repeater.io.deq.bits.opcode) node _limit_T_1 = mux(_limit_T, UInt<2>(0h3), UInt<2>(0h3)) node _limit_T_2 = eq(UInt<1>(0h1), repeater.io.deq.bits.opcode) node _limit_T_3 = mux(_limit_T_2, UInt<2>(0h3), _limit_T_1) node _limit_T_4 = eq(UInt<2>(0h2), repeater.io.deq.bits.opcode) node _limit_T_5 = mux(_limit_T_4, UInt<2>(0h3), _limit_T_3) node _limit_T_6 = eq(UInt<2>(0h3), repeater.io.deq.bits.opcode) node _limit_T_7 = mux(_limit_T_6, UInt<2>(0h3), _limit_T_5) node _limit_T_8 = eq(UInt<3>(0h4), repeater.io.deq.bits.opcode) node _limit_T_9 = mux(_limit_T_8, UInt<2>(0h3), _limit_T_7) node _limit_T_10 = eq(UInt<3>(0h5), repeater.io.deq.bits.opcode) node limit = mux(_limit_T_10, UInt<2>(0h3), _limit_T_9) node _aFrag_T = gt(repeater.io.deq.bits.size, limit) node aFrag = mux(_aFrag_T, limit, repeater.io.deq.bits.size) node _aOrigOH1_T = dshl(UInt<6>(0h3f), repeater.io.deq.bits.size) node _aOrigOH1_T_1 = bits(_aOrigOH1_T, 5, 0) node aOrigOH1 = not(_aOrigOH1_T_1) node _aFragOH1_T = dshl(UInt<3>(0h7), aFrag) node _aFragOH1_T_1 = bits(_aFragOH1_T, 2, 0) node aFragOH1 = not(_aFragOH1_T_1) node _aHasData_opdata_T = bits(repeater.io.deq.bits.opcode, 2, 2) node aHasData = eq(_aHasData_opdata_T, UInt<1>(0h0)) node aMask = mux(aHasData, UInt<1>(0h0), aFragOH1) regreset gennum : UInt<3>, clock, reset, UInt<3>(0h0) node aFirst = eq(gennum, UInt<1>(0h0)) node _old_gennum1_T = shr(aOrigOH1, 3) node _old_gennum1_T_1 = sub(gennum, UInt<1>(0h1)) node _old_gennum1_T_2 = tail(_old_gennum1_T_1, 1) node old_gennum1 = mux(aFirst, _old_gennum1_T, _old_gennum1_T_2) node _new_gennum_T = not(old_gennum1) node _new_gennum_T_1 = shr(aMask, 3) node _new_gennum_T_2 = or(_new_gennum_T, _new_gennum_T_1) node new_gennum = not(_new_gennum_T_2) node _aFragnum_T = shr(old_gennum1, 0) node _aFragnum_T_1 = not(_aFragnum_T) node _aFragnum_T_2 = shr(aFragOH1, 3) node _aFragnum_T_3 = or(_aFragnum_T_1, _aFragnum_T_2) node aFragnum = not(_aFragnum_T_3) node aLast = eq(aFragnum, UInt<1>(0h0)) reg aToggle_r : UInt<1>, clock when aFirst : connect aToggle_r, dToggle node _aToggle_T = mux(aFirst, dToggle, aToggle_r) node aToggle = eq(_aToggle_T, UInt<1>(0h0)) node _T_8 = and(anonOut.a.ready, anonOut.a.valid) when _T_8 : connect gennum, new_gennum node _repeater_io_repeat_T = eq(aHasData, UInt<1>(0h0)) node _repeater_io_repeat_T_1 = neq(aFragnum, UInt<1>(0h0)) node _repeater_io_repeat_T_2 = and(_repeater_io_repeat_T, _repeater_io_repeat_T_1) connect repeater.io.repeat, _repeater_io_repeat_T_2 connect anonOut.a.bits, repeater.io.deq.bits connect anonOut.a.valid, repeater.io.deq.valid connect repeater.io.deq.ready, anonOut.a.ready node _anonOut_a_bits_address_T = shl(old_gennum1, 3) node _anonOut_a_bits_address_T_1 = not(aOrigOH1) node _anonOut_a_bits_address_T_2 = or(_anonOut_a_bits_address_T, _anonOut_a_bits_address_T_1) node _anonOut_a_bits_address_T_3 = or(_anonOut_a_bits_address_T_2, aFragOH1) node _anonOut_a_bits_address_T_4 = or(_anonOut_a_bits_address_T_3, UInt<3>(0h7)) node _anonOut_a_bits_address_T_5 = not(_anonOut_a_bits_address_T_4) node _anonOut_a_bits_address_T_6 = or(repeater.io.deq.bits.address, _anonOut_a_bits_address_T_5) connect anonOut.a.bits.address, _anonOut_a_bits_address_T_6 node anonOut_a_bits_source_hi = cat(repeater.io.deq.bits.source, aToggle) node _anonOut_a_bits_source_T = cat(anonOut_a_bits_source_hi, aFragnum) connect anonOut.a.bits.source, _anonOut_a_bits_source_T connect anonOut.a.bits.size, aFrag node _T_9 = eq(repeater.io.full, UInt<1>(0h0)) node _T_10 = eq(aHasData, UInt<1>(0h0)) node _T_11 = or(_T_9, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:321 assert (!repeater.io.full \|\| !aHasData)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 connect anonOut.a.bits.data, anonIn.a.bits.data node _T_15 = eq(repeater.io.full, UInt<1>(0h0)) node _T_16 = eq(repeater.io.deq.bits.mask, UInt<8>(0hff)) node _T_17 = or(_T_15, _T_16) node _T_18 = asUInt(reset) node _T_19 = eq(_T_18, UInt<1>(0h0)) when _T_19 : node _T_20 = eq(_T_17, UInt<1>(0h0)) when _T_20 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:324 assert (!repeater.io.full \|\| in_a.bits.mask === fullMask)\n") : printf_2 assert(clock, _T_17, UInt<1>(0h1), "") : assert_2 node _anonOut_a_bits_mask_T = mux(repeater.io.full, UInt<8>(0hff), anonIn.a.bits.mask) connect anonOut.a.bits.mask, _anonOut_a_bits_mask_T wire anonOut_a_bits_user_out : { } wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<12>(0h0) connect _WIRE.bits.source, UInt<8>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<12>(0h0) connect _WIRE_2.bits.source, UInt<8>(0h0) connect _WIRE_2.bits.size, UInt<3>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.mask, UInt<8>(0h0) connect _WIRE_6.bits.address, UInt<12>(0h0) connect _WIRE_6.bits.source, UInt<12>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.ready, UInt<1>(0h1) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<12>(0h0) connect _WIRE_8.bits.source, UInt<12>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready connect _WIRE_9.valid, UInt<1>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_10.bits.sink, UInt<1>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready connect _WIRE_11.valid, UInt<1>(0h0)	module TLFragmenter_Debug( // @[Fragmenter.scala:92:9] input clock, // @[Fragmenter.scala:92:9] input reset, // @[Fragmenter.scala:92:9] output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [11:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [11:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [11:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [11:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire _repeater_io_full; // @[Fragmenter.scala:274:30] wire _repeater_io_enq_ready; // @[Fragmenter.scala:274:30] wire _repeater_io_deq_valid; // @[Fragmenter.scala:274:30] wire [2:0] _repeater_io_deq_bits_opcode; // @[Fragmenter.scala:274:30] wire [2:0] _repeater_io_deq_bits_size; // @[Fragmenter.scala:274:30] wire [7:0] _repeater_io_deq_bits_source; // @[Fragmenter.scala:274:30] wire [11:0] _repeater_io_deq_bits_address; // @[Fragmenter.scala:274:30] wire [7:0] _repeater_io_deq_bits_mask; // @[Fragmenter.scala:274:30] reg [2:0] acknum; // @[Fragmenter.scala:201:29] reg [2:0] dOrig; // @[Fragmenter.scala:202:24] reg dToggle; // @[Fragmenter.scala:203:30] wire dFirst = acknum == 3'h0; // @[Fragmenter.scala:201:29, :205:29] wire [5:0] _dsizeOH1_T = 6'h7 << auto_anon_out_d_bits_size; // @[package.scala:243:71] wire [2:0] _GEN = ~(auto_anon_out_d_bits_source[2:0]); // @[package.scala:241:49] wire [2:0] dFirst_size_hi = auto_anon_out_d_bits_source[2:0] & {1'h1, _GEN[2:1]}; // @[OneHot.scala:30:18] wire [2:0] _dFirst_size_T_8 = {1'h0, dFirst_size_hi[2:1]} \| ~(_dsizeOH1_T[2:0]) & {_GEN[0], _dsizeOH1_T[2:1]}; // @[OneHot.scala:30:18, :31:18, :32:28] wire [2:0] dFirst_size = {\|dFirst_size_hi, \|(_dFirst_size_T_8[2:1]), _dFirst_size_T_8[2] \| _dFirst_size_T_8[0]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}] wire drop = ~(auto_anon_out_d_bits_opcode[0]) & (\|(auto_anon_out_d_bits_source[2:0])); // @[Fragmenter.scala:204:41, :206:30, :234:{20,30}] wire anonOut_d_ready = auto_anon_in_d_ready \| drop; // @[Fragmenter.scala:234:30, :235:35] wire anonIn_d_valid = auto_anon_out_d_valid & ~drop; // @[Fragmenter.scala:234:30, :236:{36,39}] wire [2:0] anonIn_d_bits_size = dFirst ? dFirst_size : dOrig; // @[OneHot.scala:32:10] wire [12:0] _aOrigOH1_T = 13'h3F << _repeater_io_deq_bits_size; // @[package.scala:243:71] reg [2:0] gennum; // @[Fragmenter.scala:303:29] wire aFirst = gennum == 3'h0; // @[Fragmenter.scala:303:29, :304:29] wire [2:0] aFragnum = aFirst ? ~(_aOrigOH1_T[5:3]) : gennum - 3'h1; // @[package.scala:243:{46,71,76}] reg aToggle_r; // @[Fragmenter.scala:309:54]
Generate the Verilog code corresponding to this FIRRTL code module Router_16 : input clock : Clock input reset : Reset output auto : { debug_out : { va_stall : UInt[4], sa_stall : UInt[4]}, egress_nodes_out_2 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, ingress_id : UInt}}}, egress_nodes_out_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, ingress_id : UInt}}}, egress_nodes_out_0 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, ingress_id : UInt}}}, flip ingress_nodes_in_2 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, egress_id : UInt}}}, flip ingress_nodes_in_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, egress_id : UInt}}}, flip ingress_nodes_in_0 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, egress_id : UInt}}}, source_nodes_out : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1], flip credit_return : UInt<2>, flip vc_free : UInt<2>}, flip dest_nodes_in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1], flip credit_return : UInt<2>, flip vc_free : UInt<2>}} wire destNodesIn : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1], flip credit_return : UInt<2>, flip vc_free : UInt<2>} invalidate destNodesIn.vc_free invalidate destNodesIn.credit_return invalidate destNodesIn.flit[0].bits.virt_channel_id invalidate destNodesIn.flit[0].bits.flow.egress_node_id invalidate destNodesIn.flit[0].bits.flow.egress_node invalidate destNodesIn.flit[0].bits.flow.ingress_node_id invalidate destNodesIn.flit[0].bits.flow.ingress_node invalidate destNodesIn.flit[0].bits.flow.vnet_id invalidate destNodesIn.flit[0].bits.payload invalidate destNodesIn.flit[0].bits.tail invalidate destNodesIn.flit[0].bits.head invalidate destNodesIn.flit[0].valid inst monitor of NoCMonitor_46 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.vc_free, destNodesIn.vc_free connect monitor.io.in.credit_return, destNodesIn.credit_return connect monitor.io.in.flit[0].bits.virt_channel_id, destNodesIn.flit[0].bits.virt_channel_id connect monitor.io.in.flit[0].bits.flow.egress_node_id, destNodesIn.flit[0].bits.flow.egress_node_id connect monitor.io.in.flit[0].bits.flow.egress_node, destNodesIn.flit[0].bits.flow.egress_node connect monitor.io.in.flit[0].bits.flow.ingress_node_id, destNodesIn.flit[0].bits.flow.ingress_node_id connect monitor.io.in.flit[0].bits.flow.ingress_node, destNodesIn.flit[0].bits.flow.ingress_node connect monitor.io.in.flit[0].bits.flow.vnet_id, destNodesIn.flit[0].bits.flow.vnet_id connect monitor.io.in.flit[0].bits.payload, destNodesIn.flit[0].bits.payload connect monitor.io.in.flit[0].bits.tail, destNodesIn.flit[0].bits.tail connect monitor.io.in.flit[0].bits.head, destNodesIn.flit[0].bits.head connect monitor.io.in.flit[0].valid, destNodesIn.flit[0].valid wire sourceNodesOut : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1], flip credit_return : UInt<2>, flip vc_free : UInt<2>} invalidate sourceNodesOut.vc_free invalidate sourceNodesOut.credit_return invalidate sourceNodesOut.flit[0].bits.virt_channel_id invalidate sourceNodesOut.flit[0].bits.flow.egress_node_id invalidate sourceNodesOut.flit[0].bits.flow.egress_node invalidate sourceNodesOut.flit[0].bits.flow.ingress_node_id invalidate sourceNodesOut.flit[0].bits.flow.ingress_node invalidate sourceNodesOut.flit[0].bits.flow.vnet_id invalidate sourceNodesOut.flit[0].bits.payload invalidate sourceNodesOut.flit[0].bits.tail invalidate sourceNodesOut.flit[0].bits.head invalidate sourceNodesOut.flit[0].valid wire ingressNodesIn : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, egress_id : UInt}}} invalidate ingressNodesIn.flit.bits.egress_id invalidate ingressNodesIn.flit.bits.payload invalidate ingressNodesIn.flit.bits.tail invalidate ingressNodesIn.flit.bits.head invalidate ingressNodesIn.flit.valid invalidate ingressNodesIn.flit.ready wire ingressNodesIn_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, egress_id : UInt}}} invalidate ingressNodesIn_1.flit.bits.egress_id invalidate ingressNodesIn_1.flit.bits.payload invalidate ingressNodesIn_1.flit.bits.tail invalidate ingressNodesIn_1.flit.bits.head invalidate ingressNodesIn_1.flit.valid invalidate ingressNodesIn_1.flit.ready wire ingressNodesIn_2 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, egress_id : UInt}}} invalidate ingressNodesIn_2.flit.bits.egress_id invalidate ingressNodesIn_2.flit.bits.payload invalidate ingressNodesIn_2.flit.bits.tail invalidate ingressNodesIn_2.flit.bits.head invalidate ingressNodesIn_2.flit.valid invalidate ingressNodesIn_2.flit.ready wire egressNodesOut : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, ingress_id : UInt}}} invalidate egressNodesOut.flit.bits.ingress_id invalidate egressNodesOut.flit.bits.payload invalidate egressNodesOut.flit.bits.tail invalidate egressNodesOut.flit.bits.head invalidate egressNodesOut.flit.valid invalidate egressNodesOut.flit.ready wire egressNodesOut_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, ingress_id : UInt}}} invalidate egressNodesOut_1.flit.bits.ingress_id invalidate egressNodesOut_1.flit.bits.payload invalidate egressNodesOut_1.flit.bits.tail invalidate egressNodesOut_1.flit.bits.head invalidate egressNodesOut_1.flit.valid invalidate egressNodesOut_1.flit.ready wire egressNodesOut_2 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, ingress_id : UInt}}} invalidate egressNodesOut_2.flit.bits.ingress_id invalidate egressNodesOut_2.flit.bits.payload invalidate egressNodesOut_2.flit.bits.tail invalidate egressNodesOut_2.flit.bits.head invalidate egressNodesOut_2.flit.valid invalidate egressNodesOut_2.flit.ready wire debugNodeOut : { va_stall : UInt[4], sa_stall : UInt[4]} invalidate debugNodeOut.sa_stall[0] invalidate debugNodeOut.sa_stall[1] invalidate debugNodeOut.sa_stall[2] invalidate debugNodeOut.sa_stall[3] invalidate debugNodeOut.va_stall[0] invalidate debugNodeOut.va_stall[1] invalidate debugNodeOut.va_stall[2] invalidate debugNodeOut.va_stall[3] connect destNodesIn, auto.dest_nodes_in connect auto.source_nodes_out, sourceNodesOut connect ingressNodesIn, auto.ingress_nodes_in_0 connect ingressNodesIn_1, auto.ingress_nodes_in_1 connect ingressNodesIn_2, auto.ingress_nodes_in_2 connect auto.egress_nodes_out_0, egressNodesOut connect auto.egress_nodes_out_1, egressNodesOut_1 connect auto.egress_nodes_out_2, egressNodesOut_2 connect auto.debug_out, debugNodeOut inst input_unit_0_from_4 of InputUnit_46 connect input_unit_0_from_4.clock, clock connect input_unit_0_from_4.reset, reset inst ingress_unit_1_from_0 of IngressUnit_31 connect ingress_unit_1_from_0.clock, clock connect ingress_unit_1_from_0.reset, reset inst ingress_unit_2_from_1 of IngressUnit_32 connect ingress_unit_2_from_1.clock, clock connect ingress_unit_2_from_1.reset, reset inst ingress_unit_3_from_13 of IngressUnit_33 connect ingress_unit_3_from_13.clock, clock connect ingress_unit_3_from_13.reset, reset inst output_unit_0_to_1 of OutputUnit_46 connect output_unit_0_to_1.clock, clock connect output_unit_0_to_1.reset, reset inst egress_unit_1_to_0 of EgressUnit_23 connect egress_unit_1_to_0.clock, clock connect egress_unit_1_to_0.reset, reset inst egress_unit_2_to_1 of EgressUnit_24 connect egress_unit_2_to_1.clock, clock connect egress_unit_2_to_1.reset, reset inst egress_unit_3_to_13 of EgressUnit_25 connect egress_unit_3_to_13.clock, clock connect egress_unit_3_to_13.reset, reset inst switch of Switch_16 connect switch.clock, clock connect switch.reset, reset inst switch_allocator of SwitchAllocator_16 connect switch_allocator.clock, clock connect switch_allocator.reset, reset inst vc_allocator of RotatingSingleVCAllocator_16 connect vc_allocator.clock, clock connect vc_allocator.reset, reset inst route_computer of RouteComputer_16 connect route_computer.clock, clock connect route_computer.reset, reset node _fires_count_T = and(vc_allocator.io.req.`0`.ready, vc_allocator.io.req.`0`.valid) node _fires_count_T_1 = and(vc_allocator.io.req.`1`.ready, vc_allocator.io.req.`1`.valid) node _fires_count_T_2 = and(vc_allocator.io.req.`2`.ready, vc_allocator.io.req.`2`.valid) node _fires_count_T_3 = and(vc_allocator.io.req.`3`.ready, vc_allocator.io.req.`3`.valid) node _fires_count_T_4 = add(_fires_count_T, _fires_count_T_1) node _fires_count_T_5 = bits(_fires_count_T_4, 1, 0) node _fires_count_T_6 = add(_fires_count_T_2, _fires_count_T_3) node _fires_count_T_7 = bits(_fires_count_T_6, 1, 0) node _fires_count_T_8 = add(_fires_count_T_5, _fires_count_T_7) node _fires_count_T_9 = bits(_fires_count_T_8, 2, 0) wire fires_count : UInt connect fires_count, _fires_count_T_9 connect input_unit_0_from_4.io.in, destNodesIn connect ingress_unit_1_from_0.io.in, ingressNodesIn.flit connect ingress_unit_2_from_1.io.in, ingressNodesIn_1.flit connect ingress_unit_3_from_13.io.in, ingressNodesIn_2.flit connect output_unit_0_to_1.io.out.vc_free, sourceNodesOut.vc_free connect output_unit_0_to_1.io.out.credit_return, sourceNodesOut.credit_return connect sourceNodesOut.flit, output_unit_0_to_1.io.out.flit connect egressNodesOut.flit.bits, egress_unit_1_to_0.io.out.bits connect egressNodesOut.flit.valid, egress_unit_1_to_0.io.out.valid connect egress_unit_1_to_0.io.out.ready, egressNodesOut.flit.ready connect egressNodesOut_1.flit.bits, egress_unit_2_to_1.io.out.bits connect egressNodesOut_1.flit.valid, egress_unit_2_to_1.io.out.valid connect egress_unit_2_to_1.io.out.ready, egressNodesOut_1.flit.ready connect egressNodesOut_2.flit.bits, egress_unit_3_to_13.io.out.bits connect egressNodesOut_2.flit.valid, egress_unit_3_to_13.io.out.valid connect egress_unit_3_to_13.io.out.ready, egressNodesOut_2.flit.ready connect route_computer.io.req.`0`, input_unit_0_from_4.io.router_req connect route_computer.io.req.`1`, ingress_unit_1_from_0.io.router_req connect route_computer.io.req.`2`, ingress_unit_2_from_1.io.router_req connect route_computer.io.req.`3`, ingress_unit_3_from_13.io.router_req connect input_unit_0_from_4.io.router_resp, route_computer.io.resp.`0` connect ingress_unit_1_from_0.io.router_resp, route_computer.io.resp.`1` connect ingress_unit_2_from_1.io.router_resp, route_computer.io.resp.`2` connect ingress_unit_3_from_13.io.router_resp, route_computer.io.resp.`3` connect vc_allocator.io.req.`0`, input_unit_0_from_4.io.vcalloc_req connect vc_allocator.io.req.`1`, ingress_unit_1_from_0.io.vcalloc_req connect vc_allocator.io.req.`2`, ingress_unit_2_from_1.io.vcalloc_req connect vc_allocator.io.req.`3`, ingress_unit_3_from_13.io.vcalloc_req connect input_unit_0_from_4.io.vcalloc_resp, vc_allocator.io.resp.`0` connect ingress_unit_1_from_0.io.vcalloc_resp, vc_allocator.io.resp.`1` connect ingress_unit_2_from_1.io.vcalloc_resp, vc_allocator.io.resp.`2` connect ingress_unit_3_from_13.io.vcalloc_resp, vc_allocator.io.resp.`3` connect output_unit_0_to_1.io.allocs, vc_allocator.io.out_allocs.`0` connect egress_unit_1_to_0.io.allocs, vc_allocator.io.out_allocs.`1` connect egress_unit_2_to_1.io.allocs, vc_allocator.io.out_allocs.`2` connect egress_unit_3_to_13.io.allocs, vc_allocator.io.out_allocs.`3` connect vc_allocator.io.channel_status.`0`[0].flow.egress_node_id, output_unit_0_to_1.io.channel_status[0].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[0].flow.egress_node, output_unit_0_to_1.io.channel_status[0].flow.egress_node connect vc_allocator.io.channel_status.`0`[0].flow.ingress_node_id, output_unit_0_to_1.io.channel_status[0].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[0].flow.ingress_node, output_unit_0_to_1.io.channel_status[0].flow.ingress_node connect vc_allocator.io.channel_status.`0`[0].flow.vnet_id, output_unit_0_to_1.io.channel_status[0].flow.vnet_id connect vc_allocator.io.channel_status.`0`[0].occupied, output_unit_0_to_1.io.channel_status[0].occupied connect vc_allocator.io.channel_status.`0`[1].flow.egress_node_id, output_unit_0_to_1.io.channel_status[1].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[1].flow.egress_node, output_unit_0_to_1.io.channel_status[1].flow.egress_node connect vc_allocator.io.channel_status.`0`[1].flow.ingress_node_id, output_unit_0_to_1.io.channel_status[1].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[1].flow.ingress_node, output_unit_0_to_1.io.channel_status[1].flow.ingress_node connect vc_allocator.io.channel_status.`0`[1].flow.vnet_id, output_unit_0_to_1.io.channel_status[1].flow.vnet_id connect vc_allocator.io.channel_status.`0`[1].occupied, output_unit_0_to_1.io.channel_status[1].occupied connect vc_allocator.io.channel_status.`1`[0].flow.egress_node_id, egress_unit_1_to_0.io.channel_status[0].flow.egress_node_id connect vc_allocator.io.channel_status.`1`[0].flow.egress_node, egress_unit_1_to_0.io.channel_status[0].flow.egress_node connect vc_allocator.io.channel_status.`1`[0].flow.ingress_node_id, egress_unit_1_to_0.io.channel_status[0].flow.ingress_node_id connect vc_allocator.io.channel_status.`1`[0].flow.ingress_node, egress_unit_1_to_0.io.channel_status[0].flow.ingress_node connect vc_allocator.io.channel_status.`1`[0].flow.vnet_id, egress_unit_1_to_0.io.channel_status[0].flow.vnet_id connect vc_allocator.io.channel_status.`1`[0].occupied, egress_unit_1_to_0.io.channel_status[0].occupied connect vc_allocator.io.channel_status.`2`[0].flow.egress_node_id, egress_unit_2_to_1.io.channel_status[0].flow.egress_node_id connect vc_allocator.io.channel_status.`2`[0].flow.egress_node, egress_unit_2_to_1.io.channel_status[0].flow.egress_node connect vc_allocator.io.channel_status.`2`[0].flow.ingress_node_id, egress_unit_2_to_1.io.channel_status[0].flow.ingress_node_id connect vc_allocator.io.channel_status.`2`[0].flow.ingress_node, egress_unit_2_to_1.io.channel_status[0].flow.ingress_node connect vc_allocator.io.channel_status.`2`[0].flow.vnet_id, egress_unit_2_to_1.io.channel_status[0].flow.vnet_id connect vc_allocator.io.channel_status.`2`[0].occupied, egress_unit_2_to_1.io.channel_status[0].occupied connect vc_allocator.io.channel_status.`3`[0].flow.egress_node_id, egress_unit_3_to_13.io.channel_status[0].flow.egress_node_id connect vc_allocator.io.channel_status.`3`[0].flow.egress_node, egress_unit_3_to_13.io.channel_status[0].flow.egress_node connect vc_allocator.io.channel_status.`3`[0].flow.ingress_node_id, egress_unit_3_to_13.io.channel_status[0].flow.ingress_node_id connect vc_allocator.io.channel_status.`3`[0].flow.ingress_node, egress_unit_3_to_13.io.channel_status[0].flow.ingress_node connect vc_allocator.io.channel_status.`3`[0].flow.vnet_id, egress_unit_3_to_13.io.channel_status[0].flow.vnet_id connect vc_allocator.io.channel_status.`3`[0].occupied, egress_unit_3_to_13.io.channel_status[0].occupied connect input_unit_0_from_4.io.out_credit_available.`0`[0], output_unit_0_to_1.io.credit_available[0] connect input_unit_0_from_4.io.out_credit_available.`0`[1], output_unit_0_to_1.io.credit_available[1] connect input_unit_0_from_4.io.out_credit_available.`1`[0], egress_unit_1_to_0.io.credit_available[0] connect input_unit_0_from_4.io.out_credit_available.`2`[0], egress_unit_2_to_1.io.credit_available[0] connect input_unit_0_from_4.io.out_credit_available.`3`[0], egress_unit_3_to_13.io.credit_available[0] connect ingress_unit_1_from_0.io.out_credit_available.`0`[0], output_unit_0_to_1.io.credit_available[0] connect ingress_unit_1_from_0.io.out_credit_available.`0`[1], output_unit_0_to_1.io.credit_available[1] connect ingress_unit_1_from_0.io.out_credit_available.`1`[0], egress_unit_1_to_0.io.credit_available[0] connect ingress_unit_1_from_0.io.out_credit_available.`2`[0], egress_unit_2_to_1.io.credit_available[0] connect ingress_unit_1_from_0.io.out_credit_available.`3`[0], egress_unit_3_to_13.io.credit_available[0] connect ingress_unit_2_from_1.io.out_credit_available.`0`[0], output_unit_0_to_1.io.credit_available[0] connect ingress_unit_2_from_1.io.out_credit_available.`0`[1], output_unit_0_to_1.io.credit_available[1] connect ingress_unit_2_from_1.io.out_credit_available.`1`[0], egress_unit_1_to_0.io.credit_available[0] connect ingress_unit_2_from_1.io.out_credit_available.`2`[0], egress_unit_2_to_1.io.credit_available[0] connect ingress_unit_2_from_1.io.out_credit_available.`3`[0], egress_unit_3_to_13.io.credit_available[0] connect ingress_unit_3_from_13.io.out_credit_available.`0`[0], output_unit_0_to_1.io.credit_available[0] connect ingress_unit_3_from_13.io.out_credit_available.`0`[1], output_unit_0_to_1.io.credit_available[1] connect ingress_unit_3_from_13.io.out_credit_available.`1`[0], egress_unit_1_to_0.io.credit_available[0] connect ingress_unit_3_from_13.io.out_credit_available.`2`[0], egress_unit_2_to_1.io.credit_available[0] connect ingress_unit_3_from_13.io.out_credit_available.`3`[0], egress_unit_3_to_13.io.credit_available[0] connect switch_allocator.io.req.`0`[0], input_unit_0_from_4.io.salloc_req[0] connect switch_allocator.io.req.`1`[0], ingress_unit_1_from_0.io.salloc_req[0] connect switch_allocator.io.req.`2`[0], ingress_unit_2_from_1.io.salloc_req[0] connect switch_allocator.io.req.`3`[0], ingress_unit_3_from_13.io.salloc_req[0] connect output_unit_0_to_1.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`0`[0].tail connect output_unit_0_to_1.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`0`[0].alloc connect output_unit_0_to_1.io.credit_alloc[1].tail, switch_allocator.io.credit_alloc.`0`[1].tail connect output_unit_0_to_1.io.credit_alloc[1].alloc, switch_allocator.io.credit_alloc.`0`[1].alloc connect egress_unit_1_to_0.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`1`[0].tail connect egress_unit_1_to_0.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`1`[0].alloc connect egress_unit_2_to_1.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`2`[0].tail connect egress_unit_2_to_1.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`2`[0].alloc connect egress_unit_3_to_13.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`3`[0].tail connect egress_unit_3_to_13.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`3`[0].alloc connect switch.io.in.`0`[0], input_unit_0_from_4.io.out[0] connect switch.io.in.`1`[0], ingress_unit_1_from_0.io.out[0] connect switch.io.in.`2`[0], ingress_unit_2_from_1.io.out[0] connect switch.io.in.`3`[0], ingress_unit_3_from_13.io.out[0] connect output_unit_0_to_1.io.in, switch.io.out.`0` connect egress_unit_1_to_0.io.in, switch.io.out.`1` connect egress_unit_2_to_1.io.in, switch.io.out.`2` connect egress_unit_3_to_13.io.in, switch.io.out.`3` connect switch.io.sel.`0`[0].`0`[0], switch_allocator.io.switch_sel.`0`[0].`0`[0] connect switch.io.sel.`0`[0].`1`[0], switch_allocator.io.switch_sel.`0`[0].`1`[0] connect switch.io.sel.`0`[0].`2`[0], switch_allocator.io.switch_sel.`0`[0].`2`[0] connect switch.io.sel.`0`[0].`3`[0], switch_allocator.io.switch_sel.`0`[0].`3`[0] connect switch.io.sel.`1`[0].`0`[0], switch_allocator.io.switch_sel.`1`[0].`0`[0] connect switch.io.sel.`1`[0].`1`[0], switch_allocator.io.switch_sel.`1`[0].`1`[0] connect switch.io.sel.`1`[0].`2`[0], switch_allocator.io.switch_sel.`1`[0].`2`[0] connect switch.io.sel.`1`[0].`3`[0], switch_allocator.io.switch_sel.`1`[0].`3`[0] connect switch.io.sel.`2`[0].`0`[0], switch_allocator.io.switch_sel.`2`[0].`0`[0] connect switch.io.sel.`2`[0].`1`[0], switch_allocator.io.switch_sel.`2`[0].`1`[0] connect switch.io.sel.`2`[0].`2`[0], switch_allocator.io.switch_sel.`2`[0].`2`[0] connect switch.io.sel.`2`[0].`3`[0], switch_allocator.io.switch_sel.`2`[0].`3`[0] connect switch.io.sel.`3`[0].`0`[0], switch_allocator.io.switch_sel.`3`[0].`0`[0] connect switch.io.sel.`3`[0].`1`[0], switch_allocator.io.switch_sel.`3`[0].`1`[0] connect switch.io.sel.`3`[0].`2`[0], switch_allocator.io.switch_sel.`3`[0].`2`[0] connect switch.io.sel.`3`[0].`3`[0], switch_allocator.io.switch_sel.`3`[0].`3`[0] connect input_unit_0_from_4.io.block, UInt<1>(0h0) connect ingress_unit_1_from_0.io.block, UInt<1>(0h0) connect ingress_unit_2_from_1.io.block, UInt<1>(0h0) connect ingress_unit_3_from_13.io.block, UInt<1>(0h0) connect debugNodeOut.va_stall[0], input_unit_0_from_4.io.debug.va_stall connect debugNodeOut.va_stall[1], ingress_unit_1_from_0.io.debug.va_stall connect debugNodeOut.va_stall[2], ingress_unit_2_from_1.io.debug.va_stall connect debugNodeOut.va_stall[3], ingress_unit_3_from_13.io.debug.va_stall connect debugNodeOut.sa_stall[0], input_unit_0_from_4.io.debug.sa_stall connect debugNodeOut.sa_stall[1], ingress_unit_1_from_0.io.debug.sa_stall connect debugNodeOut.sa_stall[2], ingress_unit_2_from_1.io.debug.sa_stall connect debugNodeOut.sa_stall[3], ingress_unit_3_from_13.io.debug.sa_stall regreset debug_tsc : UInt<64>, clock, reset, UInt<64>(0h0) node _debug_tsc_T = add(debug_tsc, UInt<1>(0h1)) node _debug_tsc_T_1 = tail(_debug_tsc_T, 1) connect debug_tsc, _debug_tsc_T_1 regreset debug_sample : UInt<64>, clock, reset, UInt<64>(0h0) node _debug_sample_T = add(debug_sample, UInt<1>(0h1)) node _debug_sample_T_1 = tail(_debug_sample_T, 1) connect debug_sample, _debug_sample_T_1 inst plusarg_reader of plusarg_reader_42 node _T = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_1 = tail(_T, 1) node _T_2 = eq(debug_sample, _T_1) when _T_2 : connect debug_sample, UInt<1>(0h0) regreset util_ctr : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T = add(util_ctr, destNodesIn.flit[0].valid) node _util_ctr_T_1 = tail(_util_ctr_T, 1) connect util_ctr, _util_ctr_T_1 node _fired_T = or(fired, destNodesIn.flit[0].valid) connect fired, _fired_T node _T_3 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_4 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_5 = tail(_T_4, 1) node _T_6 = eq(debug_sample, _T_5) node _T_7 = and(_T_3, _T_6) node _T_8 = and(_T_7, fired) when _T_8 : node _T_9 = asUInt(reset) node _T_10 = eq(_T_9, UInt<1>(0h0)) when _T_10 : printf(clock, UInt<1>(0h1), "nocsample %d 4 0 %d\n", debug_tsc, util_ctr) : printf connect fired, destNodesIn.flit[0].valid node _T_11 = and(ingressNodesIn.flit.ready, ingressNodesIn.flit.valid) regreset util_ctr_1 : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T_2 = add(util_ctr_1, _T_11) node _util_ctr_T_3 = tail(_util_ctr_T_2, 1) connect util_ctr_1, _util_ctr_T_3 node _fired_T_1 = or(fired_1, _T_11) connect fired_1, _fired_T_1 node _T_12 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_13 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_14 = tail(_T_13, 1) node _T_15 = eq(debug_sample, _T_14) node _T_16 = and(_T_12, _T_15) node _T_17 = and(_T_16, fired_1) when _T_17 : node _T_18 = asUInt(reset) node _T_19 = eq(_T_18, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "nocsample %d i0 0 %d\n", debug_tsc, util_ctr_1) : printf_1 connect fired_1, _T_11 node _T_20 = and(ingressNodesIn_1.flit.ready, ingressNodesIn_1.flit.valid) regreset util_ctr_2 : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T_4 = add(util_ctr_2, _T_20) node _util_ctr_T_5 = tail(_util_ctr_T_4, 1) connect util_ctr_2, _util_ctr_T_5 node _fired_T_2 = or(fired_2, _T_20) connect fired_2, _fired_T_2 node _T_21 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_22 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_23 = tail(_T_22, 1) node _T_24 = eq(debug_sample, _T_23) node _T_25 = and(_T_21, _T_24) node _T_26 = and(_T_25, fired_2) when _T_26 : node _T_27 = asUInt(reset) node _T_28 = eq(_T_27, UInt<1>(0h0)) when _T_28 : printf(clock, UInt<1>(0h1), "nocsample %d i1 0 %d\n", debug_tsc, util_ctr_2) : printf_2 connect fired_2, _T_20 node _T_29 = and(ingressNodesIn_2.flit.ready, ingressNodesIn_2.flit.valid) regreset util_ctr_3 : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired_3 : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T_6 = add(util_ctr_3, _T_29) node _util_ctr_T_7 = tail(_util_ctr_T_6, 1) connect util_ctr_3, _util_ctr_T_7 node _fired_T_3 = or(fired_3, _T_29) connect fired_3, _fired_T_3 node _T_30 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_31 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_32 = tail(_T_31, 1) node _T_33 = eq(debug_sample, _T_32) node _T_34 = and(_T_30, _T_33) node _T_35 = and(_T_34, fired_3) when _T_35 : node _T_36 = asUInt(reset) node _T_37 = eq(_T_36, UInt<1>(0h0)) when _T_37 : printf(clock, UInt<1>(0h1), "nocsample %d i13 0 %d\n", debug_tsc, util_ctr_3) : printf_3 connect fired_3, _T_29 node _T_38 = and(egressNodesOut.flit.ready, egressNodesOut.flit.valid) regreset util_ctr_4 : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired_4 : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T_8 = add(util_ctr_4, _T_38) node _util_ctr_T_9 = tail(_util_ctr_T_8, 1) connect util_ctr_4, _util_ctr_T_9 node _fired_T_4 = or(fired_4, _T_38) connect fired_4, _fired_T_4 node _T_39 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_40 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_41 = tail(_T_40, 1) node _T_42 = eq(debug_sample, _T_41) node _T_43 = and(_T_39, _T_42) node _T_44 = and(_T_43, fired_4) when _T_44 : node _T_45 = asUInt(reset) node _T_46 = eq(_T_45, UInt<1>(0h0)) when _T_46 : printf(clock, UInt<1>(0h1), "nocsample %d 0 e0 %d\n", debug_tsc, util_ctr_4) : printf_4 connect fired_4, _T_38 node _T_47 = and(egressNodesOut_1.flit.ready, egressNodesOut_1.flit.valid) regreset util_ctr_5 : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired_5 : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T_10 = add(util_ctr_5, _T_47) node _util_ctr_T_11 = tail(_util_ctr_T_10, 1) connect util_ctr_5, _util_ctr_T_11 node _fired_T_5 = or(fired_5, _T_47) connect fired_5, _fired_T_5 node _T_48 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_49 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_50 = tail(_T_49, 1) node _T_51 = eq(debug_sample, _T_50) node _T_52 = and(_T_48, _T_51) node _T_53 = and(_T_52, fired_5) when _T_53 : node _T_54 = asUInt(reset) node _T_55 = eq(_T_54, UInt<1>(0h0)) when _T_55 : printf(clock, UInt<1>(0h1), "nocsample %d 0 e1 %d\n", debug_tsc, util_ctr_5) : printf_5 connect fired_5, _T_47 node _T_56 = and(egressNodesOut_2.flit.ready, egressNodesOut_2.flit.valid) regreset util_ctr_6 : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired_6 : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T_12 = add(util_ctr_6, _T_56) node _util_ctr_T_13 = tail(_util_ctr_T_12, 1) connect util_ctr_6, _util_ctr_T_13 node _fired_T_6 = or(fired_6, _T_56) connect fired_6, _fired_T_6 node _T_57 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_58 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_59 = tail(_T_58, 1) node _T_60 = eq(debug_sample, _T_59) node _T_61 = and(_T_57, _T_60) node _T_62 = and(_T_61, fired_6) when _T_62 : node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : printf(clock, UInt<1>(0h1), "nocsample %d 0 e13 %d\n", debug_tsc, util_ctr_6) : printf_6 connect fired_6, _T_56	module Router_16( // @[Router.scala:89:25] input clock, // @[Router.scala:89:25] input reset, // @[Router.scala:89:25] output auto_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25] output auto_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25] output auto_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25] output auto_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25] input auto_egress_nodes_out_2_flit_ready, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_2_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_2_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_2_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input auto_egress_nodes_out_1_flit_ready, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_1_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_1_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25] output [36:0] auto_egress_nodes_out_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input auto_egress_nodes_out_0_flit_ready, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_0_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_0_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_2_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_ingress_nodes_in_1_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_1_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_1_flit_bits_head, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input [36:0] auto_ingress_nodes_in_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [4:0] auto_ingress_nodes_in_1_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_0_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [36:0] auto_source_nodes_out_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_source_nodes_out_credit_return, // @[LazyModuleImp.scala:107:25] input [1:0] auto_source_nodes_out_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [36:0] auto_dest_nodes_in_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [1:0] auto_dest_nodes_in_credit_return, // @[LazyModuleImp.scala:107:25] output [1:0] auto_dest_nodes_in_vc_free // @[LazyModuleImp.scala:107:25] ); wire [19:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire _vc_allocator_io_req_2_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_0_ready; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_3_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_2_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_1_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_3_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_2_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_1_0; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_3_0_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_2_0_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_0_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_0_alloc; // @[Router.scala:133:30] wire _switch_allocator_io_req_2_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_0_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_3_0_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_3_0_tail; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_0_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_0_tail; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_0_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_0_tail; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_0_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_3_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_3_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_2_0; // @[Router.scala:132:34] wire _switch_io_out_3_0_valid; // @[Router.scala:131:24] wire _switch_io_out_3_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_3_0_bits_tail; // @[Router.scala:131:24] wire [36:0] _switch_io_out_3_0_bits_payload; // @[Router.scala:131:24] wire _switch_io_out_2_0_valid; // @[Router.scala:131:24] wire _switch_io_out_2_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_2_0_bits_tail; // @[Router.scala:131:24] wire [36:0] _switch_io_out_2_0_bits_payload; // @[Router.scala:131:24] wire [3:0] _switch_io_out_2_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_2_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire _switch_io_out_1_0_valid; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_tail; // @[Router.scala:131:24] wire [36:0] _switch_io_out_1_0_bits_payload; // @[Router.scala:131:24] wire _switch_io_out_0_0_valid; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_tail; // @[Router.scala:131:24] wire [36:0] _switch_io_out_0_0_bits_payload; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_0_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_0_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_0_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_0_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _egress_unit_3_to_13_io_credit_available_0; // @[Router.scala:125:13] wire _egress_unit_3_to_13_io_channel_status_0_occupied; // @[Router.scala:125:13] wire _egress_unit_3_to_13_io_out_valid; // @[Router.scala:125:13] wire _egress_unit_2_to_1_io_credit_available_0; // @[Router.scala:125:13] wire _egress_unit_2_to_1_io_channel_status_0_occupied; // @[Router.scala:125:13] wire _egress_unit_2_to_1_io_out_valid; // @[Router.scala:125:13] wire _egress_unit_1_to_0_io_credit_available_0; // @[Router.scala:125:13] wire _egress_unit_1_to_0_io_channel_status_0_occupied; // @[Router.scala:125:13] wire _egress_unit_1_to_0_io_out_valid; // @[Router.scala:125:13] wire _output_unit_0_to_1_io_credit_available_0; // @[Router.scala:122:13] wire _output_unit_0_to_1_io_channel_status_0_occupied; // @[Router.scala:122:13] wire _ingress_unit_2_from_1_io_vcalloc_req_valid; // @[Router.scala:116:13] wire _ingress_unit_2_from_1_io_vcalloc_req_bits_vc_sel_3_0; // @[Router.scala:116:13] wire _ingress_unit_2_from_1_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:116:13] wire _ingress_unit_2_from_1_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:116:13] wire _ingress_unit_2_from_1_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:116:13] wire _ingress_unit_2_from_1_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:116:13] wire _ingress_unit_2_from_1_io_salloc_req_0_valid; // @[Router.scala:116:13] wire _ingress_unit_2_from_1_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:116:13] wire _ingress_unit_2_from_1_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:116:13] wire _ingress_unit_2_from_1_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:116:13] wire _ingress_unit_2_from_1_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:116:13] wire _ingress_unit_2_from_1_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:116:13] wire _ingress_unit_2_from_1_io_salloc_req_0_bits_tail; // @[Router.scala:116:13] wire _ingress_unit_2_from_1_io_out_0_valid; // @[Router.scala:116:13] wire _ingress_unit_2_from_1_io_out_0_bits_flit_head; // @[Router.scala:116:13] wire _ingress_unit_2_from_1_io_out_0_bits_flit_tail; // @[Router.scala:116:13] wire [36:0] _ingress_unit_2_from_1_io_out_0_bits_flit_payload; // @[Router.scala:116:13] wire _ingress_unit_2_from_1_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:116:13] wire [3:0] _ingress_unit_2_from_1_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:116:13] wire [1:0] _ingress_unit_2_from_1_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:116:13] wire [3:0] _ingress_unit_2_from_1_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:116:13] wire [1:0] _ingress_unit_2_from_1_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:116:13] wire _ingress_unit_2_from_1_io_out_0_bits_out_virt_channel; // @[Router.scala:116:13] wire _ingress_unit_2_from_1_io_in_ready; // @[Router.scala:116:13] wire _input_unit_0_from_4_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_0_from_4_io_vcalloc_req_bits_vc_sel_3_0; // @[Router.scala:112:13] wire _input_unit_0_from_4_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_0_from_4_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_0_from_4_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_4_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:112:13] wire _input_unit_0_from_4_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_0_from_4_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_0_from_4_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_0_from_4_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_4_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_0_from_4_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [36:0] _input_unit_0_from_4_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire _input_unit_0_from_4_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_4_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_4_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_4_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_4_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [2:0] fires_count = {1'h0, {1'h0, _vc_allocator_io_req_2_ready & _ingress_unit_2_from_1_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_0_ready & _input_unit_0_from_4_io_vcalloc_req_valid}}; // @[Decoupled.scala:51:35] reg [63:0] debug_tsc; // @[Router.scala:195:28] reg [63:0] debug_sample; // @[Router.scala:197:31] wire _GEN = debug_sample == {44'h0, _plusarg_reader_out - 20'h1}; // @[PlusArg.scala:80:11] reg [63:0] util_ctr; // @[Router.scala:203:29] reg fired; // @[Router.scala:204:26] wire _GEN_0 = (\|_plusarg_reader_out) & _GEN; // @[PlusArg.scala:80:11] wire _GEN_1 = _GEN_0 & fired; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_2; // @[Router.scala:203:29] reg fired_2; // @[Router.scala:204:26] wire _GEN_2 = _GEN_0 & fired_2; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_4; // @[Router.scala:203:29] reg fired_4; // @[Router.scala:204:26] wire _GEN_3 = _GEN_0 & fired_4; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_5; // @[Router.scala:203:29] reg fired_5; // @[Router.scala:204:26] wire _GEN_4 = _GEN_0 & fired_5; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_6; // @[Router.scala:203:29] reg fired_6; // @[Router.scala:204:26] wire _GEN_5 = _GEN_0 & fired_6; // @[Router.scala:204:26, :207:{33,71}]
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNPipe_l2_e5_s11_4 : input clock : Clock input reset : Reset output io : { flip validin : UInt<1>, flip op : UInt<2>, flip a : UInt<17>, flip b : UInt<17>, flip c : UInt<17>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<17>, exceptionFlags : UInt<5>, validout : UInt<1>} inst mulAddRecFNToRaw_preMul of MulAddRecFNToRaw_preMul_e5_s11_4 inst mulAddRecFNToRaw_postMul of MulAddRecFNToRaw_postMul_e5_s11_4 connect mulAddRecFNToRaw_preMul.io.op, io.op connect mulAddRecFNToRaw_preMul.io.a, io.a connect mulAddRecFNToRaw_preMul.io.b, io.b connect mulAddRecFNToRaw_preMul.io.c, io.c node _mulAddResult_T = mul(mulAddRecFNToRaw_preMul.io.mulAddA, mulAddRecFNToRaw_preMul.io.mulAddB) node mulAddResult = add(_mulAddResult_T, mulAddRecFNToRaw_preMul.io.mulAddC) wire valid_stage0 : UInt<1> wire roundingMode_stage0 : UInt<3> wire detectTininess_stage0 : UInt<1> regreset mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v, io.validin reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<7>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<4>, highAlignedSigC : UInt<13>, bit0AlignedSigC : UInt<1>}, clock when io.validin : connect mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b, mulAddRecFNToRaw_preMul.io.toPostMul wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out : { valid : UInt<1>, bits : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<7>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<4>, highAlignedSigC : UInt<13>, bit0AlignedSigC : UInt<1>}} connect mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.valid, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v connect mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b connect mulAddRecFNToRaw_postMul.io.fromPreMul.bit0AlignedSigC, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.bit0AlignedSigC connect mulAddRecFNToRaw_postMul.io.fromPreMul.highAlignedSigC, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.highAlignedSigC connect mulAddRecFNToRaw_postMul.io.fromPreMul.CDom_CAlignDist, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.CDom_CAlignDist connect mulAddRecFNToRaw_postMul.io.fromPreMul.CIsDominant, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.CIsDominant connect mulAddRecFNToRaw_postMul.io.fromPreMul.doSubMags, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.doSubMags connect mulAddRecFNToRaw_postMul.io.fromPreMul.sExpSum, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.sExpSum connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroC, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isZeroC connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfC, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isInfC connect mulAddRecFNToRaw_postMul.io.fromPreMul.isNaNC, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isNaNC connect mulAddRecFNToRaw_postMul.io.fromPreMul.signProd, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.signProd connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroB, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isZeroB connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfB, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isInfB connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroA, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isZeroA connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfA, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isInfA connect mulAddRecFNToRaw_postMul.io.fromPreMul.isNaNAOrB, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isNaNAOrB connect mulAddRecFNToRaw_postMul.io.fromPreMul.isSigNaNAny, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isSigNaNAny regreset mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v, io.validin reg mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b : UInt<23>, clock when io.validin : connect mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b, mulAddResult wire mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out : { valid : UInt<1>, bits : UInt<23>} connect mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out.valid, mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v connect mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out.bits, mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b connect mulAddRecFNToRaw_postMul.io.mulAddResult, mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out.bits regreset mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v, io.validin reg mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b : UInt<3>, clock when io.validin : connect mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b, io.roundingMode wire mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out : { valid : UInt<1>, bits : UInt<3>} connect mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out.valid, mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v connect mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out.bits, mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b connect mulAddRecFNToRaw_postMul.io.roundingMode, mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out.bits regreset roundingMode_stage0_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect roundingMode_stage0_pipe_v, io.validin reg roundingMode_stage0_pipe_b : UInt<3>, clock when io.validin : connect roundingMode_stage0_pipe_b, io.roundingMode wire roundingMode_stage0_pipe_out : { valid : UInt<1>, bits : UInt<3>} connect roundingMode_stage0_pipe_out.valid, roundingMode_stage0_pipe_v connect roundingMode_stage0_pipe_out.bits, roundingMode_stage0_pipe_b connect roundingMode_stage0, roundingMode_stage0_pipe_out.bits regreset detectTininess_stage0_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect detectTininess_stage0_pipe_v, io.validin reg detectTininess_stage0_pipe_b : UInt<1>, clock when io.validin : connect detectTininess_stage0_pipe_b, io.detectTininess wire detectTininess_stage0_pipe_out : { valid : UInt<1>, bits : UInt<1>} connect detectTininess_stage0_pipe_out.valid, detectTininess_stage0_pipe_v connect detectTininess_stage0_pipe_out.bits, detectTininess_stage0_pipe_b connect detectTininess_stage0, detectTininess_stage0_pipe_out.bits regreset valid_stage0_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect valid_stage0_pipe_v, io.validin reg valid_stage0_pipe_b : UInt<1>, clock when io.validin : connect valid_stage0_pipe_b, UInt<1>(0h0) wire valid_stage0_pipe_out : { valid : UInt<1>, bits : UInt<1>} connect valid_stage0_pipe_out.valid, valid_stage0_pipe_v connect valid_stage0_pipe_out.bits, valid_stage0_pipe_b connect valid_stage0, valid_stage0_pipe_out.valid inst roundRawFNToRecFN of RoundRawFNToRecFN_e5_s11_8 regreset roundRawFNToRecFN_io_invalidExc_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect roundRawFNToRecFN_io_invalidExc_pipe_v, valid_stage0 reg roundRawFNToRecFN_io_invalidExc_pipe_b : UInt<1>, clock when valid_stage0 : connect roundRawFNToRecFN_io_invalidExc_pipe_b, mulAddRecFNToRaw_postMul.io.invalidExc wire roundRawFNToRecFN_io_invalidExc_pipe_out : { valid : UInt<1>, bits : UInt<1>} connect roundRawFNToRecFN_io_invalidExc_pipe_out.valid, roundRawFNToRecFN_io_invalidExc_pipe_v connect roundRawFNToRecFN_io_invalidExc_pipe_out.bits, roundRawFNToRecFN_io_invalidExc_pipe_b connect roundRawFNToRecFN.io.invalidExc, roundRawFNToRecFN_io_invalidExc_pipe_out.bits regreset roundRawFNToRecFN_io_in_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect roundRawFNToRecFN_io_in_pipe_v, valid_stage0 reg roundRawFNToRecFN_io_in_pipe_b : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<14>}, clock when valid_stage0 : connect roundRawFNToRecFN_io_in_pipe_b, mulAddRecFNToRaw_postMul.io.rawOut wire roundRawFNToRecFN_io_in_pipe_out : { valid : UInt<1>, bits : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<14>}} connect roundRawFNToRecFN_io_in_pipe_out.valid, roundRawFNToRecFN_io_in_pipe_v connect roundRawFNToRecFN_io_in_pipe_out.bits, roundRawFNToRecFN_io_in_pipe_b connect roundRawFNToRecFN.io.in.sig, roundRawFNToRecFN_io_in_pipe_out.bits.sig connect roundRawFNToRecFN.io.in.sExp, roundRawFNToRecFN_io_in_pipe_out.bits.sExp connect roundRawFNToRecFN.io.in.sign, roundRawFNToRecFN_io_in_pipe_out.bits.sign connect roundRawFNToRecFN.io.in.isZero, roundRawFNToRecFN_io_in_pipe_out.bits.isZero connect roundRawFNToRecFN.io.in.isInf, roundRawFNToRecFN_io_in_pipe_out.bits.isInf connect roundRawFNToRecFN.io.in.isNaN, roundRawFNToRecFN_io_in_pipe_out.bits.isNaN regreset roundRawFNToRecFN_io_roundingMode_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect roundRawFNToRecFN_io_roundingMode_pipe_v, valid_stage0 reg roundRawFNToRecFN_io_roundingMode_pipe_b : UInt<3>, clock when valid_stage0 : connect roundRawFNToRecFN_io_roundingMode_pipe_b, roundingMode_stage0 wire roundRawFNToRecFN_io_roundingMode_pipe_out : { valid : UInt<1>, bits : UInt<3>} connect roundRawFNToRecFN_io_roundingMode_pipe_out.valid, roundRawFNToRecFN_io_roundingMode_pipe_v connect roundRawFNToRecFN_io_roundingMode_pipe_out.bits, roundRawFNToRecFN_io_roundingMode_pipe_b connect roundRawFNToRecFN.io.roundingMode, roundRawFNToRecFN_io_roundingMode_pipe_out.bits regreset roundRawFNToRecFN_io_detectTininess_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect roundRawFNToRecFN_io_detectTininess_pipe_v, valid_stage0 reg roundRawFNToRecFN_io_detectTininess_pipe_b : UInt<1>, clock when valid_stage0 : connect roundRawFNToRecFN_io_detectTininess_pipe_b, detectTininess_stage0 wire roundRawFNToRecFN_io_detectTininess_pipe_out : { valid : UInt<1>, bits : UInt<1>} connect roundRawFNToRecFN_io_detectTininess_pipe_out.valid, roundRawFNToRecFN_io_detectTininess_pipe_v connect roundRawFNToRecFN_io_detectTininess_pipe_out.bits, roundRawFNToRecFN_io_detectTininess_pipe_b connect roundRawFNToRecFN.io.detectTininess, roundRawFNToRecFN_io_detectTininess_pipe_out.bits regreset io_validout_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect io_validout_pipe_v, valid_stage0 reg io_validout_pipe_b : UInt<1>, clock when valid_stage0 : connect io_validout_pipe_b, UInt<1>(0h0) wire io_validout_pipe_out : { valid : UInt<1>, bits : UInt<1>} connect io_validout_pipe_out.valid, io_validout_pipe_v connect io_validout_pipe_out.bits, io_validout_pipe_b connect io.validout, io_validout_pipe_out.valid connect roundRawFNToRecFN.io.infiniteExc, UInt<1>(0h0) connect io.out, roundRawFNToRecFN.io.out connect io.exceptionFlags, roundRawFNToRecFN.io.exceptionFlags	module MulAddRecFNPipe_l2_e5_s11_4( // @[FPU.scala:633:7] input clock, // @[FPU.scala:633:7] input reset, // @[FPU.scala:633:7] input io_validin, // @[FPU.scala:638:16] input [1:0] io_op, // @[FPU.scala:638:16] input [16:0] io_a, // @[FPU.scala:638:16] input [16:0] io_b, // @[FPU.scala:638:16] input [16:0] io_c, // @[FPU.scala:638:16] input [2:0] io_roundingMode, // @[FPU.scala:638:16] output [16:0] io_out, // @[FPU.scala:638:16] output [4:0] io_exceptionFlags, // @[FPU.scala:638:16] output io_validout // @[FPU.scala:638:16] ); wire _mulAddRecFNToRaw_postMul_io_invalidExc; // @[FPU.scala:655:42] wire _mulAddRecFNToRaw_postMul_io_rawOut_isNaN; // @[FPU.scala:655:42] wire _mulAddRecFNToRaw_postMul_io_rawOut_isInf; // @[FPU.scala:655:42] wire _mulAddRecFNToRaw_postMul_io_rawOut_isZero; // @[FPU.scala:655:42] wire _mulAddRecFNToRaw_postMul_io_rawOut_sign; // @[FPU.scala:655:42] wire [6:0] _mulAddRecFNToRaw_postMul_io_rawOut_sExp; // @[FPU.scala:655:42] wire [13:0] _mulAddRecFNToRaw_postMul_io_rawOut_sig; // @[FPU.scala:655:42] wire [10:0] _mulAddRecFNToRaw_preMul_io_mulAddA; // @[FPU.scala:654:41] wire [10:0] _mulAddRecFNToRaw_preMul_io_mulAddB; // @[FPU.scala:654:41] wire [21:0] _mulAddRecFNToRaw_preMul_io_mulAddC; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfB; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_signProd; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfC; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC; // @[FPU.scala:654:41] wire [6:0] _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant; // @[FPU.scala:654:41] wire [3:0] _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist; // @[FPU.scala:654:41] wire [12:0] _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC; // @[FPU.scala:654:41] wire io_validin_0 = io_validin; // @[FPU.scala:633:7] wire [1:0] io_op_0 = io_op; // @[FPU.scala:633:7] wire [16:0] io_a_0 = io_a; // @[FPU.scala:633:7] wire [16:0] io_b_0 = io_b; // @[FPU.scala:633:7] wire [16:0] io_c_0 = io_c; // @[FPU.scala:633:7] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[FPU.scala:633:7] wire io_detectTininess = 1'h1; // @[FPU.scala:633:7] wire detectTininess_stage0 = 1'h1; // @[FPU.scala:669:37] wire detectTininess_stage0_pipe_out_bits = 1'h1; // @[Valid.scala:135:21] wire valid_stage0_pipe_out_bits = 1'h0; // @[Valid.scala:135:21] wire io_validout_pipe_out_bits = 1'h0; // @[Valid.scala:135:21] wire io_validout_pipe_out_valid; // @[Valid.scala:135:21] wire [16:0] io_out_0; // @[FPU.scala:633:7] wire [4:0] io_exceptionFlags_0; // @[FPU.scala:633:7] wire io_validout_0; // @[FPU.scala:633:7] wire [21:0] _mulAddResult_T = {11'h0, _mulAddRecFNToRaw_preMul_io_mulAddA} * {11'h0, _mulAddRecFNToRaw_preMul_io_mulAddB}; // @[FPU.scala:654:41, :663:45] wire [22:0] mulAddResult = {1'h0, _mulAddResult_T} + {1'h0, _mulAddRecFNToRaw_preMul_io_mulAddC}; // @[FPU.scala:654:41, :663:45, :664:50] wire valid_stage0_pipe_out_valid; // @[Valid.scala:135:21] wire valid_stage0; // @[FPU.scala:667:28] wire [2:0] roundingMode_stage0_pipe_out_bits; // @[Valid.scala:135:21] wire [2:0] roundingMode_stage0; // @[FPU.scala:668:35] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v; // @[Valid.scala:141:24] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_valid = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v; // @[Valid.scala:135:21, :141:24] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isSigNaNAny = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isNaNAOrB = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfA = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroA = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfB = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroB = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_signProd = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isNaNC = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfC = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroC = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC; // @[Valid.scala:135:21, :142:26] reg [6:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum; // @[Valid.scala:142:26] wire [6:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_sExpSum = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_doSubMags = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_CIsDominant = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant; // @[Valid.scala:135:21, :142:26] reg [3:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist; // @[Valid.scala:142:26] wire [3:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_CDom_CAlignDist = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist; // @[Valid.scala:135:21, :142:26] reg [12:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC; // @[Valid.scala:142:26] wire [12:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_highAlignedSigC = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_bit0AlignedSigC = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v; // @[Valid.scala:141:24] wire mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out_valid = mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v; // @[Valid.scala:135:21, :141:24] reg [22:0] mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b; // @[Valid.scala:142:26] wire [22:0] mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out_bits = mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v; // @[Valid.scala:141:24] wire mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out_valid = mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v; // @[Valid.scala:135:21, :141:24] reg [2:0] mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b; // @[Valid.scala:142:26] wire [2:0] mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out_bits = mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b; // @[Valid.scala:135:21, :142:26] reg roundingMode_stage0_pipe_v; // @[Valid.scala:141:24] wire roundingMode_stage0_pipe_out_valid = roundingMode_stage0_pipe_v; // @[Valid.scala:135:21, :141:24] reg [2:0] roundingMode_stage0_pipe_b; // @[Valid.scala:142:26] assign roundingMode_stage0_pipe_out_bits = roundingMode_stage0_pipe_b; // @[Valid.scala:135:21, :142:26] assign roundingMode_stage0 = roundingMode_stage0_pipe_out_bits; // @[Valid.scala:135:21] reg detectTininess_stage0_pipe_v; // @[Valid.scala:141:24] wire detectTininess_stage0_pipe_out_valid = detectTininess_stage0_pipe_v; // @[Valid.scala:135:21, :141:24] reg valid_stage0_pipe_v; // @[Valid.scala:141:24] assign valid_stage0_pipe_out_valid = valid_stage0_pipe_v; // @[Valid.scala:135:21, :141:24] assign valid_stage0 = valid_stage0_pipe_out_valid; // @[Valid.scala:135:21] reg roundRawFNToRecFN_io_invalidExc_pipe_v; // @[Valid.scala:141:24] wire roundRawFNToRecFN_io_invalidExc_pipe_out_valid = roundRawFNToRecFN_io_invalidExc_pipe_v; // @[Valid.scala:135:21, :141:24] reg roundRawFNToRecFN_io_invalidExc_pipe_b; // @[Valid.scala:142:26] wire roundRawFNToRecFN_io_invalidExc_pipe_out_bits = roundRawFNToRecFN_io_invalidExc_pipe_b; // @[Valid.scala:135:21, :142:26] reg roundRawFNToRecFN_io_in_pipe_v; // @[Valid.scala:141:24] wire roundRawFNToRecFN_io_in_pipe_out_valid = roundRawFNToRecFN_io_in_pipe_v; // @[Valid.scala:135:21, :141:24] reg roundRawFNToRecFN_io_in_pipe_b_isNaN; // @[Valid.scala:142:26] wire roundRawFNToRecFN_io_in_pipe_out_bits_isNaN = roundRawFNToRecFN_io_in_pipe_b_isNaN; // @[Valid.scala:135:21, :142:26] reg roundRawFNToRecFN_io_in_pipe_b_isInf; // @[Valid.scala:142:26] wire roundRawFNToRecFN_io_in_pipe_out_bits_isInf = roundRawFNToRecFN_io_in_pipe_b_isInf; // @[Valid.scala:135:21, :142:26] reg roundRawFNToRecFN_io_in_pipe_b_isZero; // @[Valid.scala:142:26] wire roundRawFNToRecFN_io_in_pipe_out_bits_isZero = roundRawFNToRecFN_io_in_pipe_b_isZero; // @[Valid.scala:135:21, :142:26] reg roundRawFNToRecFN_io_in_pipe_b_sign; // @[Valid.scala:142:26] wire roundRawFNToRecFN_io_in_pipe_out_bits_sign = roundRawFNToRecFN_io_in_pipe_b_sign; // @[Valid.scala:135:21, :142:26] reg [6:0] roundRawFNToRecFN_io_in_pipe_b_sExp; // @[Valid.scala:142:26] wire [6:0] roundRawFNToRecFN_io_in_pipe_out_bits_sExp = roundRawFNToRecFN_io_in_pipe_b_sExp; // @[Valid.scala:135:21, :142:26] reg [13:0] roundRawFNToRecFN_io_in_pipe_b_sig; // @[Valid.scala:142:26] wire [13:0] roundRawFNToRecFN_io_in_pipe_out_bits_sig = roundRawFNToRecFN_io_in_pipe_b_sig; // @[Valid.scala:135:21, :142:26] reg roundRawFNToRecFN_io_roundingMode_pipe_v; // @[Valid.scala:141:24] wire roundRawFNToRecFN_io_roundingMode_pipe_out_valid = roundRawFNToRecFN_io_roundingMode_pipe_v; // @[Valid.scala:135:21, :141:24] reg [2:0] roundRawFNToRecFN_io_roundingMode_pipe_b; // @[Valid.scala:142:26] wire [2:0] roundRawFNToRecFN_io_roundingMode_pipe_out_bits = roundRawFNToRecFN_io_roundingMode_pipe_b; // @[Valid.scala:135:21, :142:26] reg roundRawFNToRecFN_io_detectTininess_pipe_v; // @[Valid.scala:141:24] wire roundRawFNToRecFN_io_detectTininess_pipe_out_valid = roundRawFNToRecFN_io_detectTininess_pipe_v; // @[Valid.scala:135:21, :141:24] reg roundRawFNToRecFN_io_detectTininess_pipe_b; // @[Valid.scala:142:26] wire roundRawFNToRecFN_io_detectTininess_pipe_out_bits = roundRawFNToRecFN_io_detectTininess_pipe_b; // @[Valid.scala:135:21, :142:26] reg io_validout_pipe_v; // @[Valid.scala:141:24] assign io_validout_pipe_out_valid = io_validout_pipe_v; // @[Valid.scala:135:21, :141:24] assign io_validout_0 = io_validout_pipe_out_valid; // @[Valid.scala:135:21] always @(posedge clock) begin // @[FPU.scala:633:7] if (reset) begin // @[FPU.scala:633:7] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v <= 1'h0; // @[Valid.scala:141:24] mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v <= 1'h0; // @[Valid.scala:141:24] mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v <= 1'h0; // @[Valid.scala:141:24] roundingMode_stage0_pipe_v <= 1'h0; // @[Valid.scala:141:24] detectTininess_stage0_pipe_v <= 1'h0; // @[Valid.scala:141:24] valid_stage0_pipe_v <= 1'h0; // @[Valid.scala:141:24] roundRawFNToRecFN_io_invalidExc_pipe_v <= 1'h0; // @[Valid.scala:141:24] roundRawFNToRecFN_io_in_pipe_v <= 1'h0; // @[Valid.scala:141:24] roundRawFNToRecFN_io_roundingMode_pipe_v <= 1'h0; // @[Valid.scala:141:24] roundRawFNToRecFN_io_detectTininess_pipe_v <= 1'h0; // @[Valid.scala:141:24] io_validout_pipe_v <= 1'h0; // @[Valid.scala:141:24] end else begin // @[FPU.scala:633:7] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v <= io_validin_0; // @[Valid.scala:141:24] mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v <= io_validin_0; // @[Valid.scala:141:24] mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v <= io_validin_0; // @[Valid.scala:141:24] roundingMode_stage0_pipe_v <= io_validin_0; // @[Valid.scala:141:24] detectTininess_stage0_pipe_v <= io_validin_0; // @[Valid.scala:141:24] valid_stage0_pipe_v <= io_validin_0; // @[Valid.scala:141:24] roundRawFNToRecFN_io_invalidExc_pipe_v <= valid_stage0; // @[Valid.scala:141:24] roundRawFNToRecFN_io_in_pipe_v <= valid_stage0; // @[Valid.scala:141:24] roundRawFNToRecFN_io_roundingMode_pipe_v <= valid_stage0; // @[Valid.scala:141:24] roundRawFNToRecFN_io_detectTininess_pipe_v <= valid_stage0; // @[Valid.scala:141:24] io_validout_pipe_v <= valid_stage0; // @[Valid.scala:141:24] end if (io_validin_0) begin // @[FPU.scala:633:7] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny <= _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB <= _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA <= _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA <= _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB <= _mulAddRecFNToRaw_preMul_io_toPostMul_isInfB; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB <= _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd <= _mulAddRecFNToRaw_preMul_io_toPostMul_signProd; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC <= _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC <= _mulAddRecFNToRaw_preMul_io_toPostMul_isInfC; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC <= _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum <= _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags <= _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant <= _mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist <= _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC <= _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC <= _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b <= mulAddResult; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b <= io_roundingMode_0; // @[Valid.scala:142:26] roundingMode_stage0_pipe_b <= io_roundingMode_0; // @[Valid.scala:142:26] end if (valid_stage0) begin // @[FPU.scala:667:28] roundRawFNToRecFN_io_invalidExc_pipe_b <= _mulAddRecFNToRaw_postMul_io_invalidExc; // @[Valid.scala:142:26] roundRawFNToRecFN_io_in_pipe_b_isNaN <= _mulAddRecFNToRaw_postMul_io_rawOut_isNaN; // @[Valid.scala:142:26] roundRawFNToRecFN_io_in_pipe_b_isInf <= _mulAddRecFNToRaw_postMul_io_rawOut_isInf; // @[Valid.scala:142:26] roundRawFNToRecFN_io_in_pipe_b_isZero <= _mulAddRecFNToRaw_postMul_io_rawOut_isZero; // @[Valid.scala:142:26] roundRawFNToRecFN_io_in_pipe_b_sign <= _mulAddRecFNToRaw_postMul_io_rawOut_sign; // @[Valid.scala:142:26] roundRawFNToRecFN_io_in_pipe_b_sExp <= _mulAddRecFNToRaw_postMul_io_rawOut_sExp; // @[Valid.scala:142:26] roundRawFNToRecFN_io_in_pipe_b_sig <= _mulAddRecFNToRaw_postMul_io_rawOut_sig; // @[Valid.scala:142:26] roundRawFNToRecFN_io_roundingMode_pipe_b <= roundingMode_stage0; // @[Valid.scala:142:26] end roundRawFNToRecFN_io_detectTininess_pipe_b <= valid_stage0 \| roundRawFNToRecFN_io_detectTininess_pipe_b; // @[Valid.scala:142:26] always @(posedge) MulAddRecFNToRaw_preMul_e5_s11_4 mulAddRecFNToRaw_preMul ( // @[FPU.scala:654:41] .io_op (io_op_0), // @[FPU.scala:633:7] .io_a (io_a_0), // @[FPU.scala:633:7] .io_b (io_b_0), // @[FPU.scala:633:7] .io_c (io_c_0), // @[FPU.scala:633:7] .io_mulAddA (_mulAddRecFNToRaw_preMul_io_mulAddA), .io_mulAddB (_mulAddRecFNToRaw_preMul_io_mulAddB), .io_mulAddC (_mulAddRecFNToRaw_preMul_io_mulAddC), .io_toPostMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny), .io_toPostMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB), .io_toPostMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA), .io_toPostMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA), .io_toPostMul_isInfB (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfB), .io_toPostMul_isZeroB (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB), .io_toPostMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd), .io_toPostMul_isNaNC (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC), .io_toPostMul_isInfC (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfC), .io_toPostMul_isZeroC (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC), .io_toPostMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum), .io_toPostMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags), .io_toPostMul_CIsDominant (_mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant), .io_toPostMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist), .io_toPostMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC), .io_toPostMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC) ); // @[FPU.scala:654:41] MulAddRecFNToRaw_postMul_e5_s11_4 mulAddRecFNToRaw_postMul ( // @[FPU.scala:655:42] .io_fromPreMul_isSigNaNAny (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isSigNaNAny), // @[Valid.scala:135:21] .io_fromPreMul_isNaNAOrB (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isNaNAOrB), // @[Valid.scala:135:21] .io_fromPreMul_isInfA (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfA), // @[Valid.scala:135:21] .io_fromPreMul_isZeroA (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroA), // @[Valid.scala:135:21] .io_fromPreMul_isInfB (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfB), // @[Valid.scala:135:21] .io_fromPreMul_isZeroB (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroB), // @[Valid.scala:135:21] .io_fromPreMul_signProd (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_signProd), // @[Valid.scala:135:21] .io_fromPreMul_isNaNC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isNaNC), // @[Valid.scala:135:21] .io_fromPreMul_isInfC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfC), // @[Valid.scala:135:21] .io_fromPreMul_isZeroC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroC), // @[Valid.scala:135:21] .io_fromPreMul_sExpSum (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_sExpSum), // @[Valid.scala:135:21] .io_fromPreMul_doSubMags (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_doSubMags), // @[Valid.scala:135:21] .io_fromPreMul_CIsDominant (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_CIsDominant), // @[Valid.scala:135:21] .io_fromPreMul_CDom_CAlignDist (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_CDom_CAlignDist), // @[Valid.scala:135:21] .io_fromPreMul_highAlignedSigC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_highAlignedSigC), // @[Valid.scala:135:21] .io_fromPreMul_bit0AlignedSigC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_bit0AlignedSigC), // @[Valid.scala:135:21] .io_mulAddResult (mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out_bits), // @[Valid.scala:135:21] .io_roundingMode (mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out_bits), // @[Valid.scala:135:21] .io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc), .io_rawOut_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN), .io_rawOut_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf), .io_rawOut_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero), .io_rawOut_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign), .io_rawOut_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp), .io_rawOut_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig) ); // @[FPU.scala:655:42] RoundRawFNToRecFN_e5_s11_8 roundRawFNToRecFN ( // @[FPU.scala:682:35] .io_invalidExc (roundRawFNToRecFN_io_invalidExc_pipe_out_bits), // @[Valid.scala:135:21] .io_in_isNaN (roundRawFNToRecFN_io_in_pipe_out_bits_isNaN), // @[Valid.scala:135:21] .io_in_isInf (roundRawFNToRecFN_io_in_pipe_out_bits_isInf), // @[Valid.scala:135:21] .io_in_isZero (roundRawFNToRecFN_io_in_pipe_out_bits_isZero), // @[Valid.scala:135:21] .io_in_sign (roundRawFNToRecFN_io_in_pipe_out_bits_sign), // @[Valid.scala:135:21] .io_in_sExp (roundRawFNToRecFN_io_in_pipe_out_bits_sExp), // @[Valid.scala:135:21] .io_in_sig (roundRawFNToRecFN_io_in_pipe_out_bits_sig), // @[Valid.scala:135:21] .io_roundingMode (roundRawFNToRecFN_io_roundingMode_pipe_out_bits), // @[Valid.scala:135:21] .io_detectTininess (roundRawFNToRecFN_io_detectTininess_pipe_out_bits), // @[Valid.scala:135:21] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags_0) ); // @[FPU.scala:682:35] assign io_out = io_out_0; // @[FPU.scala:633:7] assign io_exceptionFlags = io_exceptionFlags_0; // @[FPU.scala:633:7] assign io_validout = io_validout_0; // @[FPU.scala:633:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_158 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_274 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0	module AsyncResetSynchronizerShiftReg_w1_d3_i0_158( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_274 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module IntXbar_i2_o1 : output auto : { flip anon_in_1 : UInt<1>[5], flip anon_in_0 : UInt<1>[5], anon_out : UInt<1>[10]} wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset wire anonIn : UInt<1>[5] invalidate anonIn[0] invalidate anonIn[1] invalidate anonIn[2] invalidate anonIn[3] invalidate anonIn[4] wire anonIn_1 : UInt<1>[5] invalidate anonIn_1[0] invalidate anonIn_1[1] invalidate anonIn_1[2] invalidate anonIn_1[3] invalidate anonIn_1[4] wire anonOut : UInt<1>[10] invalidate anonOut[0] invalidate anonOut[1] invalidate anonOut[2] invalidate anonOut[3] invalidate anonOut[4] invalidate anonOut[5] invalidate anonOut[6] invalidate anonOut[7] invalidate anonOut[8] invalidate anonOut[9] connect auto.anon_out, anonOut connect anonIn, auto.anon_in_0 connect anonIn_1, auto.anon_in_1 connect anonOut[0], anonIn[0] connect anonOut[1], anonIn[1] connect anonOut[2], anonIn[2] connect anonOut[3], anonIn[3] connect anonOut[4], anonIn[4] connect anonOut[5], anonIn_1[0] connect anonOut[6], anonIn_1[1] connect anonOut[7], anonIn_1[2] connect anonOut[8], anonIn_1[3] connect anonOut[9], anonIn_1[4]	module IntXbar_i2_o1( // @[Xbar.scala:22:9] input auto_anon_in_1_0, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_1, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_2, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_3, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_4, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_0, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_1, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_2, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_3, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_4, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1, // @[LazyModuleImp.scala:107:25] output auto_anon_out_2, // @[LazyModuleImp.scala:107:25] output auto_anon_out_3, // @[LazyModuleImp.scala:107:25] output auto_anon_out_4, // @[LazyModuleImp.scala:107:25] output auto_anon_out_5, // @[LazyModuleImp.scala:107:25] output auto_anon_out_6, // @[LazyModuleImp.scala:107:25] output auto_anon_out_7, // @[LazyModuleImp.scala:107:25] output auto_anon_out_8, // @[LazyModuleImp.scala:107:25] output auto_anon_out_9 // @[LazyModuleImp.scala:107:25] ); wire auto_anon_in_1_0_0 = auto_anon_in_1_0; // @[Xbar.scala:22:9] wire auto_anon_in_1_1_0 = auto_anon_in_1_1; // @[Xbar.scala:22:9] wire auto_anon_in_1_2_0 = auto_anon_in_1_2; // @[Xbar.scala:22:9] wire auto_anon_in_1_3_0 = auto_anon_in_1_3; // @[Xbar.scala:22:9] wire auto_anon_in_1_4_0 = auto_anon_in_1_4; // @[Xbar.scala:22:9] wire auto_anon_in_0_0_0 = auto_anon_in_0_0; // @[Xbar.scala:22:9] wire auto_anon_in_0_1_0 = auto_anon_in_0_1; // @[Xbar.scala:22:9] wire auto_anon_in_0_2_0 = auto_anon_in_0_2; // @[Xbar.scala:22:9] wire auto_anon_in_0_3_0 = auto_anon_in_0_3; // @[Xbar.scala:22:9] wire auto_anon_in_0_4_0 = auto_anon_in_0_4; // @[Xbar.scala:22:9] wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire anonIn_1_0 = auto_anon_in_1_0_0; // @[Xbar.scala:22:9] wire anonIn_1_1 = auto_anon_in_1_1_0; // @[Xbar.scala:22:9] wire anonIn_1_2 = auto_anon_in_1_2_0; // @[Xbar.scala:22:9] wire anonIn_1_3 = auto_anon_in_1_3_0; // @[Xbar.scala:22:9] wire anonIn_1_4 = auto_anon_in_1_4_0; // @[Xbar.scala:22:9] wire anonIn_0 = auto_anon_in_0_0_0; // @[Xbar.scala:22:9] wire anonIn_1 = auto_anon_in_0_1_0; // @[Xbar.scala:22:9] wire anonIn_2 = auto_anon_in_0_2_0; // @[Xbar.scala:22:9] wire anonIn_3 = auto_anon_in_0_3_0; // @[Xbar.scala:22:9] wire anonIn_4 = auto_anon_in_0_4_0; // @[Xbar.scala:22:9] wire anonOut_0; // @[MixedNode.scala:542:17] wire anonOut_1; // @[MixedNode.scala:542:17] wire anonOut_2; // @[MixedNode.scala:542:17] wire anonOut_3; // @[MixedNode.scala:542:17] wire anonOut_4; // @[MixedNode.scala:542:17] wire anonOut_5; // @[MixedNode.scala:542:17] wire anonOut_6; // @[MixedNode.scala:542:17] wire anonOut_7; // @[MixedNode.scala:542:17] wire anonOut_8; // @[MixedNode.scala:542:17] wire anonOut_9; // @[MixedNode.scala:542:17] wire auto_anon_out_0_0; // @[Xbar.scala:22:9] wire auto_anon_out_1_0; // @[Xbar.scala:22:9] wire auto_anon_out_2_0; // @[Xbar.scala:22:9] wire auto_anon_out_3_0; // @[Xbar.scala:22:9] wire auto_anon_out_4_0; // @[Xbar.scala:22:9] wire auto_anon_out_5_0; // @[Xbar.scala:22:9] wire auto_anon_out_6_0; // @[Xbar.scala:22:9] wire auto_anon_out_7_0; // @[Xbar.scala:22:9] wire auto_anon_out_8_0; // @[Xbar.scala:22:9] wire auto_anon_out_9_0; // @[Xbar.scala:22:9] assign anonOut_0 = anonIn_0; // @[MixedNode.scala:542:17, :551:17] assign anonOut_1 = anonIn_1; // @[MixedNode.scala:542:17, :551:17] assign anonOut_2 = anonIn_2; // @[MixedNode.scala:542:17, :551:17] assign anonOut_3 = anonIn_3; // @[MixedNode.scala:542:17, :551:17] assign anonOut_4 = anonIn_4; // @[MixedNode.scala:542:17, :551:17] assign anonOut_5 = anonIn_1_0; // @[MixedNode.scala:542:17, :551:17] assign anonOut_6 = anonIn_1_1; // @[MixedNode.scala:542:17, :551:17] assign anonOut_7 = anonIn_1_2; // @[MixedNode.scala:542:17, :551:17] assign anonOut_8 = anonIn_1_3; // @[MixedNode.scala:542:17, :551:17] assign anonOut_9 = anonIn_1_4; // @[MixedNode.scala:542:17, :551:17] assign auto_anon_out_0_0 = anonOut_0; // @[Xbar.scala:22:9] assign auto_anon_out_1_0 = anonOut_1; // @[Xbar.scala:22:9] assign auto_anon_out_2_0 = anonOut_2; // @[Xbar.scala:22:9] assign auto_anon_out_3_0 = anonOut_3; // @[Xbar.scala:22:9] assign auto_anon_out_4_0 = anonOut_4; // @[Xbar.scala:22:9] assign auto_anon_out_5_0 = anonOut_5; // @[Xbar.scala:22:9] assign auto_anon_out_6_0 = anonOut_6; // @[Xbar.scala:22:9] assign auto_anon_out_7_0 = anonOut_7; // @[Xbar.scala:22:9] assign auto_anon_out_8_0 = anonOut_8; // @[Xbar.scala:22:9] assign auto_anon_out_9_0 = anonOut_9; // @[Xbar.scala:22:9] assign auto_anon_out_0 = auto_anon_out_0_0; // @[Xbar.scala:22:9] assign auto_anon_out_1 = auto_anon_out_1_0; // @[Xbar.scala:22:9] assign auto_anon_out_2 = auto_anon_out_2_0; // @[Xbar.scala:22:9] assign auto_anon_out_3 = auto_anon_out_3_0; // @[Xbar.scala:22:9] assign auto_anon_out_4 = auto_anon_out_4_0; // @[Xbar.scala:22:9] assign auto_anon_out_5 = auto_anon_out_5_0; // @[Xbar.scala:22:9] assign auto_anon_out_6 = auto_anon_out_6_0; // @[Xbar.scala:22:9] assign auto_anon_out_7 = auto_anon_out_7_0; // @[Xbar.scala:22:9] assign auto_anon_out_8 = auto_anon_out_8_0; // @[Xbar.scala:22:9] assign auto_anon_out_9 = auto_anon_out_9_0; // @[Xbar.scala:22:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie11_is53_oe8_os24_6 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0)) node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1)) node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3)) node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4)) node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6)) node _roundMagUp_T = and(roundingMode_min, io.in.sign) node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0)) node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1) node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2) node sAdjustedExp = add(io.in.sExp, asSInt(UInt<12>(0h900))) node _adjustedSig_T = bits(io.in.sig, 53, 28) node _adjustedSig_T_1 = bits(io.in.sig, 27, 0) node _adjustedSig_T_2 = orr(_adjustedSig_T_1) node adjustedSig = cat(_adjustedSig_T, _adjustedSig_T_2) wire common_expOut : UInt<9> wire common_fractOut : UInt<23> wire common_overflow : UInt<1> wire common_totalUnderflow : UInt<1> wire common_underflow : UInt<1> wire common_inexact : UInt<1> node _roundMask_T = bits(sAdjustedExp, 8, 0) node _roundMask_T_1 = not(_roundMask_T) node roundMask_msb = bits(_roundMask_T_1, 8, 8) node roundMask_lsbs = bits(_roundMask_T_1, 7, 0) node roundMask_msb_1 = bits(roundMask_lsbs, 7, 7) node roundMask_lsbs_1 = bits(roundMask_lsbs, 6, 0) node roundMask_msb_2 = bits(roundMask_lsbs_1, 6, 6) node roundMask_lsbs_2 = bits(roundMask_lsbs_1, 5, 0) node roundMask_shift = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_2) node _roundMask_T_2 = bits(roundMask_shift, 63, 42) node _roundMask_T_3 = bits(_roundMask_T_2, 15, 0) node _roundMask_T_4 = shl(UInt<8>(0hff), 8) node _roundMask_T_5 = xor(UInt<16>(0hffff), _roundMask_T_4) node _roundMask_T_6 = shr(_roundMask_T_3, 8) node _roundMask_T_7 = and(_roundMask_T_6, _roundMask_T_5) node _roundMask_T_8 = bits(_roundMask_T_3, 7, 0) node _roundMask_T_9 = shl(_roundMask_T_8, 8) node _roundMask_T_10 = not(_roundMask_T_5) node _roundMask_T_11 = and(_roundMask_T_9, _roundMask_T_10) node _roundMask_T_12 = or(_roundMask_T_7, _roundMask_T_11) node _roundMask_T_13 = bits(_roundMask_T_5, 11, 0) node _roundMask_T_14 = shl(_roundMask_T_13, 4) node _roundMask_T_15 = xor(_roundMask_T_5, _roundMask_T_14) node _roundMask_T_16 = shr(_roundMask_T_12, 4) node _roundMask_T_17 = and(_roundMask_T_16, _roundMask_T_15) node _roundMask_T_18 = bits(_roundMask_T_12, 11, 0) node _roundMask_T_19 = shl(_roundMask_T_18, 4) node _roundMask_T_20 = not(_roundMask_T_15) node _roundMask_T_21 = and(_roundMask_T_19, _roundMask_T_20) node _roundMask_T_22 = or(_roundMask_T_17, _roundMask_T_21) node _roundMask_T_23 = bits(_roundMask_T_15, 13, 0) node _roundMask_T_24 = shl(_roundMask_T_23, 2) node _roundMask_T_25 = xor(_roundMask_T_15, _roundMask_T_24) node _roundMask_T_26 = shr(_roundMask_T_22, 2) node _roundMask_T_27 = and(_roundMask_T_26, _roundMask_T_25) node _roundMask_T_28 = bits(_roundMask_T_22, 13, 0) node _roundMask_T_29 = shl(_roundMask_T_28, 2) node _roundMask_T_30 = not(_roundMask_T_25) node _roundMask_T_31 = and(_roundMask_T_29, _roundMask_T_30) node _roundMask_T_32 = or(_roundMask_T_27, _roundMask_T_31) node _roundMask_T_33 = bits(_roundMask_T_25, 14, 0) node _roundMask_T_34 = shl(_roundMask_T_33, 1) node _roundMask_T_35 = xor(_roundMask_T_25, _roundMask_T_34) node _roundMask_T_36 = shr(_roundMask_T_32, 1) node _roundMask_T_37 = and(_roundMask_T_36, _roundMask_T_35) node _roundMask_T_38 = bits(_roundMask_T_32, 14, 0) node _roundMask_T_39 = shl(_roundMask_T_38, 1) node _roundMask_T_40 = not(_roundMask_T_35) node _roundMask_T_41 = and(_roundMask_T_39, _roundMask_T_40) node _roundMask_T_42 = or(_roundMask_T_37, _roundMask_T_41) node _roundMask_T_43 = bits(_roundMask_T_2, 21, 16) node _roundMask_T_44 = bits(_roundMask_T_43, 3, 0) node _roundMask_T_45 = bits(_roundMask_T_44, 1, 0) node _roundMask_T_46 = bits(_roundMask_T_45, 0, 0) node _roundMask_T_47 = bits(_roundMask_T_45, 1, 1) node _roundMask_T_48 = cat(_roundMask_T_46, _roundMask_T_47) node _roundMask_T_49 = bits(_roundMask_T_44, 3, 2) node _roundMask_T_50 = bits(_roundMask_T_49, 0, 0) node _roundMask_T_51 = bits(_roundMask_T_49, 1, 1) node _roundMask_T_52 = cat(_roundMask_T_50, _roundMask_T_51) node _roundMask_T_53 = cat(_roundMask_T_48, _roundMask_T_52) node _roundMask_T_54 = bits(_roundMask_T_43, 5, 4) node _roundMask_T_55 = bits(_roundMask_T_54, 0, 0) node _roundMask_T_56 = bits(_roundMask_T_54, 1, 1) node _roundMask_T_57 = cat(_roundMask_T_55, _roundMask_T_56) node _roundMask_T_58 = cat(_roundMask_T_53, _roundMask_T_57) node _roundMask_T_59 = cat(_roundMask_T_42, _roundMask_T_58) node _roundMask_T_60 = not(_roundMask_T_59) node _roundMask_T_61 = mux(roundMask_msb_2, UInt<1>(0h0), _roundMask_T_60) node _roundMask_T_62 = not(_roundMask_T_61) node _roundMask_T_63 = cat(_roundMask_T_62, UInt<3>(0h7)) node roundMask_msb_3 = bits(roundMask_lsbs_1, 6, 6) node roundMask_lsbs_3 = bits(roundMask_lsbs_1, 5, 0) node roundMask_shift_1 = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_3) node _roundMask_T_64 = bits(roundMask_shift_1, 2, 0) node _roundMask_T_65 = bits(_roundMask_T_64, 1, 0) node _roundMask_T_66 = bits(_roundMask_T_65, 0, 0) node _roundMask_T_67 = bits(_roundMask_T_65, 1, 1) node _roundMask_T_68 = cat(_roundMask_T_66, _roundMask_T_67) node _roundMask_T_69 = bits(_roundMask_T_64, 2, 2) node _roundMask_T_70 = cat(_roundMask_T_68, _roundMask_T_69) node _roundMask_T_71 = mux(roundMask_msb_3, _roundMask_T_70, UInt<1>(0h0)) node _roundMask_T_72 = mux(roundMask_msb_1, _roundMask_T_63, _roundMask_T_71) node _roundMask_T_73 = mux(roundMask_msb, _roundMask_T_72, UInt<1>(0h0)) node _roundMask_T_74 = or(_roundMask_T_73, UInt<1>(0h0)) node roundMask = cat(_roundMask_T_74, UInt<2>(0h3)) node _shiftedRoundMask_T = cat(UInt<1>(0h0), roundMask) node shiftedRoundMask = shr(_shiftedRoundMask_T, 1) node _roundPosMask_T = not(shiftedRoundMask) node roundPosMask = and(_roundPosMask_T, roundMask) node _roundPosBit_T = and(adjustedSig, roundPosMask) node roundPosBit = orr(_roundPosBit_T) node _anyRoundExtra_T = and(adjustedSig, shiftedRoundMask) node anyRoundExtra = orr(_anyRoundExtra_T) node anyRound = or(roundPosBit, anyRoundExtra) node _roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _roundIncr_T_1 = and(_roundIncr_T, roundPosBit) node _roundIncr_T_2 = and(roundMagUp, anyRound) node roundIncr = or(_roundIncr_T_1, _roundIncr_T_2) node _roundedSig_T = or(adjustedSig, roundMask) node _roundedSig_T_1 = shr(_roundedSig_T, 2) node _roundedSig_T_2 = add(_roundedSig_T_1, UInt<1>(0h1)) node _roundedSig_T_3 = and(roundingMode_near_even, roundPosBit) node _roundedSig_T_4 = eq(anyRoundExtra, UInt<1>(0h0)) node _roundedSig_T_5 = and(_roundedSig_T_3, _roundedSig_T_4) node _roundedSig_T_6 = shr(roundMask, 1) node _roundedSig_T_7 = mux(_roundedSig_T_5, _roundedSig_T_6, UInt<26>(0h0)) node _roundedSig_T_8 = not(_roundedSig_T_7) node _roundedSig_T_9 = and(_roundedSig_T_2, _roundedSig_T_8) node _roundedSig_T_10 = not(roundMask) node _roundedSig_T_11 = and(adjustedSig, _roundedSig_T_10) node _roundedSig_T_12 = shr(_roundedSig_T_11, 2) node _roundedSig_T_13 = and(roundingMode_odd, anyRound) node _roundedSig_T_14 = shr(roundPosMask, 1) node _roundedSig_T_15 = mux(_roundedSig_T_13, _roundedSig_T_14, UInt<1>(0h0)) node _roundedSig_T_16 = or(_roundedSig_T_12, _roundedSig_T_15) node roundedSig = mux(roundIncr, _roundedSig_T_9, _roundedSig_T_16) node _sRoundedExp_T = shr(roundedSig, 24) node _sRoundedExp_T_1 = cvt(_sRoundedExp_T) node sRoundedExp = add(sAdjustedExp, _sRoundedExp_T_1) node _common_expOut_T = bits(sRoundedExp, 8, 0) connect common_expOut, _common_expOut_T node _common_fractOut_T = bits(roundedSig, 23, 1) node _common_fractOut_T_1 = bits(roundedSig, 22, 0) node _common_fractOut_T_2 = mux(UInt<1>(0h0), _common_fractOut_T, _common_fractOut_T_1) connect common_fractOut, _common_fractOut_T_2 node _common_overflow_T = shr(sRoundedExp, 7) node _common_overflow_T_1 = geq(_common_overflow_T, asSInt(UInt<3>(0h3))) connect common_overflow, _common_overflow_T_1 node _common_totalUnderflow_T = lt(sRoundedExp, asSInt(UInt<8>(0h6b))) connect common_totalUnderflow, _common_totalUnderflow_T node _unboundedRange_roundPosBit_T = bits(adjustedSig, 2, 2) node _unboundedRange_roundPosBit_T_1 = bits(adjustedSig, 1, 1) node unboundedRange_roundPosBit = mux(UInt<1>(0h0), _unboundedRange_roundPosBit_T, _unboundedRange_roundPosBit_T_1) node _unboundedRange_anyRound_T = bits(adjustedSig, 2, 2) node _unboundedRange_anyRound_T_1 = and(UInt<1>(0h0), _unboundedRange_anyRound_T) node _unboundedRange_anyRound_T_2 = bits(adjustedSig, 1, 0) node _unboundedRange_anyRound_T_3 = orr(_unboundedRange_anyRound_T_2) node unboundedRange_anyRound = or(_unboundedRange_anyRound_T_1, _unboundedRange_anyRound_T_3) node _unboundedRange_roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _unboundedRange_roundIncr_T_1 = and(_unboundedRange_roundIncr_T, unboundedRange_roundPosBit) node _unboundedRange_roundIncr_T_2 = and(roundMagUp, unboundedRange_anyRound) node unboundedRange_roundIncr = or(_unboundedRange_roundIncr_T_1, _unboundedRange_roundIncr_T_2) node _roundCarry_T = bits(roundedSig, 25, 25) node _roundCarry_T_1 = bits(roundedSig, 24, 24) node roundCarry = mux(UInt<1>(0h0), _roundCarry_T, _roundCarry_T_1) node _common_underflow_T = shr(sAdjustedExp, 8) node _common_underflow_T_1 = leq(_common_underflow_T, asSInt(UInt<1>(0h0))) node _common_underflow_T_2 = and(anyRound, _common_underflow_T_1) node _common_underflow_T_3 = bits(roundMask, 3, 3) node _common_underflow_T_4 = bits(roundMask, 2, 2) node _common_underflow_T_5 = mux(UInt<1>(0h0), _common_underflow_T_3, _common_underflow_T_4) node _common_underflow_T_6 = and(_common_underflow_T_2, _common_underflow_T_5) node _common_underflow_T_7 = eq(io.detectTininess, UInt<1>(0h1)) node _common_underflow_T_8 = bits(roundMask, 4, 4) node _common_underflow_T_9 = bits(roundMask, 3, 3) node _common_underflow_T_10 = mux(UInt<1>(0h0), _common_underflow_T_8, _common_underflow_T_9) node _common_underflow_T_11 = eq(_common_underflow_T_10, UInt<1>(0h0)) node _common_underflow_T_12 = and(_common_underflow_T_7, _common_underflow_T_11) node _common_underflow_T_13 = and(_common_underflow_T_12, roundCarry) node _common_underflow_T_14 = and(_common_underflow_T_13, roundPosBit) node _common_underflow_T_15 = and(_common_underflow_T_14, unboundedRange_roundIncr) node _common_underflow_T_16 = eq(_common_underflow_T_15, UInt<1>(0h0)) node _common_underflow_T_17 = and(_common_underflow_T_6, _common_underflow_T_16) node _common_underflow_T_18 = or(common_totalUnderflow, _common_underflow_T_17) connect common_underflow, _common_underflow_T_18 node _common_inexact_T = or(common_totalUnderflow, anyRound) connect common_inexact, _common_inexact_T node isNaNOut = or(io.invalidExc, io.in.isNaN) node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf) node _commonCase_T = eq(isNaNOut, UInt<1>(0h0)) node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0)) node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1) node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0)) node commonCase = and(_commonCase_T_2, _commonCase_T_3) node overflow = and(commonCase, common_overflow) node underflow = and(commonCase, common_underflow) node _inexact_T = and(commonCase, common_inexact) node inexact = or(overflow, _inexact_T) node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag) node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp) node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow) node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd) node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1) node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0)) node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T) node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp) node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T) node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign) node _expOut_T = or(io.in.isZero, common_totalUnderflow) node _expOut_T_1 = mux(_expOut_T, UInt<9>(0h1c0), UInt<1>(0h0)) node _expOut_T_2 = not(_expOut_T_1) node _expOut_T_3 = and(common_expOut, _expOut_T_2) node _expOut_T_4 = not(UInt<9>(0h6b)) node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0)) node _expOut_T_6 = not(_expOut_T_5) node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6) node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<9>(0h80), UInt<1>(0h0)) node _expOut_T_9 = not(_expOut_T_8) node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9) node _expOut_T_11 = mux(notNaN_isInfOut, UInt<9>(0h40), UInt<1>(0h0)) node _expOut_T_12 = not(_expOut_T_11) node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12) node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<9>(0h6b), UInt<1>(0h0)) node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14) node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<9>(0h17f), UInt<1>(0h0)) node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16) node _expOut_T_18 = mux(notNaN_isInfOut, UInt<9>(0h180), UInt<1>(0h0)) node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18) node _expOut_T_20 = mux(isNaNOut, UInt<9>(0h1c0), UInt<1>(0h0)) node expOut = or(_expOut_T_19, _expOut_T_20) node _fractOut_T = or(isNaNOut, io.in.isZero) node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow) node _fractOut_T_2 = mux(isNaNOut, UInt<23>(0h400000), UInt<1>(0h0)) node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut) node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<23>(0h7fffff), UInt<23>(0h0)) node fractOut = or(_fractOut_T_3, _fractOut_T_4) node _io_out_T = cat(signOut, expOut) node _io_out_T_1 = cat(_io_out_T, fractOut) connect io.out, _io_out_T_1 node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc) node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow) node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact) connect io.exceptionFlags, _io_exceptionFlags_T_3	module RoundAnyRawFNToRecFN_ie11_is53_oe8_os24_6( // @[RoundAnyRawFNToRecFN.scala:48:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16] input [12:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16] input [53:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16] input [2:0] io_roundingMode, // @[RoundAnyRawFNToRecFN.scala:58:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [12:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [53:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [15:0] _roundMask_T_5 = 16'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_4 = 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_10 = 16'hFF00; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_13 = 12'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_14 = 16'hFF0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_15 = 16'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_20 = 16'hF0F0; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_23 = 14'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_24 = 16'h3C3C; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_25 = 16'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_30 = 16'hCCCC; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_33 = 15'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_34 = 16'h6666; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_35 = 16'h5555; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_40 = 16'hAAAA; // @[primitives.scala:77:20] wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5] wire _common_underflow_T_7 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:222:49] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire _unboundedRange_anyRound_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:205:30] wire notNaN_isSpecialInfOut = io_in_isInf_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :236:49] wire [32:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33] wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_near_even = io_roundingMode_0 == 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :90:53] wire roundingMode_minMag = io_roundingMode_0 == 3'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :91:53] wire roundingMode_min = io_roundingMode_0 == 3'h2; // @[RoundAnyRawFNToRecFN.scala:48:5, :92:53] wire roundingMode_max = io_roundingMode_0 == 3'h3; // @[RoundAnyRawFNToRecFN.scala:48:5, :93:53] wire roundingMode_near_maxMag = io_roundingMode_0 == 3'h4; // @[RoundAnyRawFNToRecFN.scala:48:5, :94:53] wire roundingMode_odd = io_roundingMode_0 == 3'h6; // @[RoundAnyRawFNToRecFN.scala:48:5, :95:53] wire _roundMagUp_T = roundingMode_min & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :92:53, :98:27] wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66] wire _roundMagUp_T_2 = roundingMode_max & _roundMagUp_T_1; // @[RoundAnyRawFNToRecFN.scala:93:53, :98:{63,66}] wire roundMagUp = _roundMagUp_T \| _roundMagUp_T_2; // @[RoundAnyRawFNToRecFN.scala:98:{27,42,63}] wire [13:0] sAdjustedExp = {io_in_sExp_0[12], io_in_sExp_0} - 14'h700; // @[RoundAnyRawFNToRecFN.scala:48:5, :110:24] wire [25:0] _adjustedSig_T = io_in_sig_0[53:28]; // @[RoundAnyRawFNToRecFN.scala:48:5, :116:23] wire [27:0] _adjustedSig_T_1 = io_in_sig_0[27:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :117:26] wire _adjustedSig_T_2 = \|_adjustedSig_T_1; // @[RoundAnyRawFNToRecFN.scala:117:{26,60}] wire [26:0] adjustedSig = {_adjustedSig_T, _adjustedSig_T_2}; // @[RoundAnyRawFNToRecFN.scala:116:{23,66}, :117:60] wire [8:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37] wire [8:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31] wire [22:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16] wire [22:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31] wire _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:196:50] wire common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37] wire _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:200:31] wire common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37] wire _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:217:40] wire common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37] wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49] wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37] wire [8:0] _roundMask_T = sAdjustedExp[8:0]; // @[RoundAnyRawFNToRecFN.scala:110:24, :156:37] wire [8:0] _roundMask_T_1 = ~_roundMask_T; // @[primitives.scala:52:21] wire roundMask_msb = _roundMask_T_1[8]; // @[primitives.scala:52:21, :58:25] wire [7:0] roundMask_lsbs = _roundMask_T_1[7:0]; // @[primitives.scala:52:21, :59:26] wire roundMask_msb_1 = roundMask_lsbs[7]; // @[primitives.scala:58:25, :59:26] wire [6:0] roundMask_lsbs_1 = roundMask_lsbs[6:0]; // @[primitives.scala:59:26] wire roundMask_msb_2 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire roundMask_msb_3 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire [5:0] roundMask_lsbs_2 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [5:0] roundMask_lsbs_3 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> roundMask_lsbs_2); // @[primitives.scala:59:26, :76:56] wire [21:0] _roundMask_T_2 = roundMask_shift[63:42]; // @[primitives.scala:76:56, :78:22] wire [15:0] _roundMask_T_3 = _roundMask_T_2[15:0]; // @[primitives.scala:77:20, :78:22] wire [7:0] _roundMask_T_6 = _roundMask_T_3[15:8]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_7 = {8'h0, _roundMask_T_6}; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_8 = _roundMask_T_3[7:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_9 = {_roundMask_T_8, 8'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_11 = _roundMask_T_9 & 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_12 = _roundMask_T_7 \| _roundMask_T_11; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_16 = _roundMask_T_12[15:4]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_17 = {4'h0, _roundMask_T_16 & 12'hF0F}; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_18 = _roundMask_T_12[11:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_19 = {_roundMask_T_18, 4'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_21 = _roundMask_T_19 & 16'hF0F0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_22 = _roundMask_T_17 \| _roundMask_T_21; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_26 = _roundMask_T_22[15:2]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_27 = {2'h0, _roundMask_T_26 & 14'h3333}; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_28 = _roundMask_T_22[13:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_29 = {_roundMask_T_28, 2'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_31 = _roundMask_T_29 & 16'hCCCC; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_32 = _roundMask_T_27 \| _roundMask_T_31; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_36 = _roundMask_T_32[15:1]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_37 = {1'h0, _roundMask_T_36 & 15'h5555}; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_38 = _roundMask_T_32[14:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_39 = {_roundMask_T_38, 1'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_41 = _roundMask_T_39 & 16'hAAAA; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_42 = _roundMask_T_37 \| _roundMask_T_41; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_43 = _roundMask_T_2[21:16]; // @[primitives.scala:77:20, :78:22] wire [3:0] _roundMask_T_44 = _roundMask_T_43[3:0]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_45 = _roundMask_T_44[1:0]; // @[primitives.scala:77:20] wire _roundMask_T_46 = _roundMask_T_45[0]; // @[primitives.scala:77:20] wire _roundMask_T_47 = _roundMask_T_45[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_48 = {_roundMask_T_46, _roundMask_T_47}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_49 = _roundMask_T_44[3:2]; // @[primitives.scala:77:20] wire _roundMask_T_50 = _roundMask_T_49[0]; // @[primitives.scala:77:20] wire _roundMask_T_51 = _roundMask_T_49[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_52 = {_roundMask_T_50, _roundMask_T_51}; // @[primitives.scala:77:20] wire [3:0] _roundMask_T_53 = {_roundMask_T_48, _roundMask_T_52}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_54 = _roundMask_T_43[5:4]; // @[primitives.scala:77:20] wire _roundMask_T_55 = _roundMask_T_54[0]; // @[primitives.scala:77:20] wire _roundMask_T_56 = _roundMask_T_54[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_57 = {_roundMask_T_55, _roundMask_T_56}; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_58 = {_roundMask_T_53, _roundMask_T_57}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_59 = {_roundMask_T_42, _roundMask_T_58}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_60 = ~_roundMask_T_59; // @[primitives.scala:73:32, :77:20] wire [21:0] _roundMask_T_61 = roundMask_msb_2 ? 22'h0 : _roundMask_T_60; // @[primitives.scala:58:25, :73:{21,32}] wire [21:0] _roundMask_T_62 = ~_roundMask_T_61; // @[primitives.scala:73:{17,21}] wire [24:0] _roundMask_T_63 = {_roundMask_T_62, 3'h7}; // @[primitives.scala:68:58, :73:17] wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> roundMask_lsbs_3); // @[primitives.scala:59:26, :76:56] wire [2:0] _roundMask_T_64 = roundMask_shift_1[2:0]; // @[primitives.scala:76:56, :78:22] wire [1:0] _roundMask_T_65 = _roundMask_T_64[1:0]; // @[primitives.scala:77:20, :78:22] wire _roundMask_T_66 = _roundMask_T_65[0]; // @[primitives.scala:77:20] wire _roundMask_T_67 = _roundMask_T_65[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_68 = {_roundMask_T_66, _roundMask_T_67}; // @[primitives.scala:77:20] wire _roundMask_T_69 = _roundMask_T_64[2]; // @[primitives.scala:77:20, :78:22] wire [2:0] _roundMask_T_70 = {_roundMask_T_68, _roundMask_T_69}; // @[primitives.scala:77:20] wire [2:0] _roundMask_T_71 = roundMask_msb_3 ? _roundMask_T_70 : 3'h0; // @[primitives.scala:58:25, :62:24, :77:20] wire [24:0] _roundMask_T_72 = roundMask_msb_1 ? _roundMask_T_63 : {22'h0, _roundMask_T_71}; // @[primitives.scala:58:25, :62:24, :67:24, :68:58] wire [24:0] _roundMask_T_73 = roundMask_msb ? _roundMask_T_72 : 25'h0; // @[primitives.scala:58:25, :62:24, :67:24] wire [24:0] _roundMask_T_74 = _roundMask_T_73; // @[primitives.scala:62:24] wire [26:0] roundMask = {_roundMask_T_74, 2'h3}; // @[RoundAnyRawFNToRecFN.scala:159:{23,42}] wire [27:0] _shiftedRoundMask_T = {1'h0, roundMask}; // @[RoundAnyRawFNToRecFN.scala:159:42, :162:41] wire [26:0] shiftedRoundMask = _shiftedRoundMask_T[27:1]; // @[RoundAnyRawFNToRecFN.scala:162:{41,53}] wire [26:0] _roundPosMask_T = ~shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:162:53, :163:28] wire [26:0] roundPosMask = _roundPosMask_T & roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :163:{28,46}] wire [26:0] _roundPosBit_T = adjustedSig & roundPosMask; // @[RoundAnyRawFNToRecFN.scala:116:66, :163:46, :164:40] wire roundPosBit = \|_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}] wire [26:0] _anyRoundExtra_T = adjustedSig & shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:116:66, :162:53, :165:42] wire anyRoundExtra = \|_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}] wire anyRound = roundPosBit \| anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36] wire _GEN = roundingMode_near_even \| roundingMode_near_maxMag; // @[RoundAnyRawFNToRecFN.scala:90:53, :94:53, :169:38] wire _roundIncr_T; // @[RoundAnyRawFNToRecFN.scala:169:38] assign _roundIncr_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38] wire _unboundedRange_roundIncr_T; // @[RoundAnyRawFNToRecFN.scala:207:38] assign _unboundedRange_roundIncr_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38, :207:38] wire _overflow_roundMagUp_T; // @[RoundAnyRawFNToRecFN.scala:243:32] assign _overflow_roundMagUp_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38, :243:32] wire _roundIncr_T_1 = _roundIncr_T & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:{38,67}] wire _roundIncr_T_2 = roundMagUp & anyRound; // @[RoundAnyRawFNToRecFN.scala:98:42, :166:36, :171:29] wire roundIncr = _roundIncr_T_1 \| _roundIncr_T_2; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31, :171:29] wire [26:0] _roundedSig_T = adjustedSig \| roundMask; // @[RoundAnyRawFNToRecFN.scala:116:66, :159:42, :174:32] wire [24:0] _roundedSig_T_1 = _roundedSig_T[26:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}] wire [25:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 26'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}] wire _roundedSig_T_3 = roundingMode_near_even & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:90:53, :164:56, :175:49] wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30] wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30] wire [25:0] _roundedSig_T_6 = roundMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:159:42, :177:35] wire [25:0] _roundedSig_T_7 = _roundedSig_T_5 ? _roundedSig_T_6 : 26'h0; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}, :177:35] wire [25:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}] wire [25:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21] wire [26:0] _roundedSig_T_10 = ~roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :180:32] wire [26:0] _roundedSig_T_11 = adjustedSig & _roundedSig_T_10; // @[RoundAnyRawFNToRecFN.scala:116:66, :180:{30,32}] wire [24:0] _roundedSig_T_12 = _roundedSig_T_11[26:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}] wire _roundedSig_T_13 = roundingMode_odd & anyRound; // @[RoundAnyRawFNToRecFN.scala:95:53, :166:36, :181:42] wire [25:0] _roundedSig_T_14 = roundPosMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:163:46, :181:67] wire [25:0] _roundedSig_T_15 = _roundedSig_T_13 ? _roundedSig_T_14 : 26'h0; // @[RoundAnyRawFNToRecFN.scala:181:{24,42,67}] wire [25:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12} \| _roundedSig_T_15; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}, :181:24] wire [25:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47] wire [1:0] _sRoundedExp_T = roundedSig[25:24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54] wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}] wire [14:0] sRoundedExp = {sAdjustedExp[13], sAdjustedExp} + {{12{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:110:24, :185:{40,76}] assign _common_expOut_T = sRoundedExp[8:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37] assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37] wire [22:0] _common_fractOut_T = roundedSig[23:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27] wire [22:0] _common_fractOut_T_1 = roundedSig[22:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27] assign _common_fractOut_T_2 = _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:189:16, :191:27] assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16] wire [7:0] _common_overflow_T = sRoundedExp[14:7]; // @[RoundAnyRawFNToRecFN.scala:185:40, :196:30] assign _common_overflow_T_1 = $signed(_common_overflow_T) > 8'sh2; // @[RoundAnyRawFNToRecFN.scala:196:{30,50}] assign common_overflow = _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:124:37, :196:50] assign _common_totalUnderflow_T = $signed(sRoundedExp) < 15'sh6B; // @[RoundAnyRawFNToRecFN.scala:185:40, :200:31] assign common_totalUnderflow = _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:125:37, :200:31] wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:116:66, :203:45] wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:116:66, :203:45, :205:44] wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:116:66, :203:61] wire unboundedRange_roundPosBit = _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:203:{16,61}] wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:116:66, :205:63] wire _unboundedRange_anyRound_T_3 = \|_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}] wire unboundedRange_anyRound = _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{49,70}] wire _unboundedRange_roundIncr_T_1 = _unboundedRange_roundIncr_T & unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:{38,67}] wire _unboundedRange_roundIncr_T_2 = roundMagUp & unboundedRange_anyRound; // @[RoundAnyRawFNToRecFN.scala:98:42, :205:49, :209:29] wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1 \| _unboundedRange_roundIncr_T_2; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46, :209:29] wire _roundCarry_T = roundedSig[25]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27] wire _roundCarry_T_1 = roundedSig[24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27] wire roundCarry = _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:211:16, :213:27] wire [5:0] _common_underflow_T = sAdjustedExp[13:8]; // @[RoundAnyRawFNToRecFN.scala:110:24, :220:49] wire _common_underflow_T_1 = $signed(_common_underflow_T) < 6'sh1; // @[RoundAnyRawFNToRecFN.scala:220:{49,64}] wire _common_underflow_T_2 = anyRound & _common_underflow_T_1; // @[RoundAnyRawFNToRecFN.scala:166:36, :220:{32,64}] wire _common_underflow_T_3 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57] wire _common_underflow_T_9 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57, :225:49] wire _common_underflow_T_4 = roundMask[2]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:71] wire _common_underflow_T_5 = _common_underflow_T_4; // @[RoundAnyRawFNToRecFN.scala:221:{30,71}] wire _common_underflow_T_6 = _common_underflow_T_2 & _common_underflow_T_5; // @[RoundAnyRawFNToRecFN.scala:220:{32,72}, :221:30] wire _common_underflow_T_8 = roundMask[4]; // @[RoundAnyRawFNToRecFN.scala:159:42, :224:49] wire _common_underflow_T_10 = _common_underflow_T_9; // @[RoundAnyRawFNToRecFN.scala:223:39, :225:49] wire _common_underflow_T_11 = ~_common_underflow_T_10; // @[RoundAnyRawFNToRecFN.scala:223:{34,39}] wire _common_underflow_T_12 = _common_underflow_T_11; // @[RoundAnyRawFNToRecFN.scala:222:77, :223:34] wire _common_underflow_T_13 = _common_underflow_T_12 & roundCarry; // @[RoundAnyRawFNToRecFN.scala:211:16, :222:77, :226:38] wire _common_underflow_T_14 = _common_underflow_T_13 & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :226:38, :227:45] wire _common_underflow_T_15 = _common_underflow_T_14 & unboundedRange_roundIncr; // @[RoundAnyRawFNToRecFN.scala:208:46, :227:{45,60}] wire _common_underflow_T_16 = ~_common_underflow_T_15; // @[RoundAnyRawFNToRecFN.scala:222:27, :227:60] wire _common_underflow_T_17 = _common_underflow_T_6 & _common_underflow_T_16; // @[RoundAnyRawFNToRecFN.scala:220:72, :221:76, :222:27] assign _common_underflow_T_18 = common_totalUnderflow \| _common_underflow_T_17; // @[RoundAnyRawFNToRecFN.scala:125:37, :217:40, :221:76] assign common_underflow = _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:126:37, :217:40] assign _common_inexact_T = common_totalUnderflow \| anyRound; // @[RoundAnyRawFNToRecFN.scala:125:37, :166:36, :230:49] assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49] wire isNaNOut = io_invalidExc_0 \| io_in_isNaN_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34] wire _commonCase_T = ~isNaNOut; // @[RoundAnyRawFNToRecFN.scala:235:34, :237:22] wire _commonCase_T_1 = ~notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :237:36] wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1; // @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}] wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64] wire commonCase = _commonCase_T_2 & _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}] wire overflow = commonCase & common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32] wire underflow = commonCase & common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37, :237:61, :239:32] wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43] wire inexact = overflow \| _inexact_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}] wire overflow_roundMagUp = _overflow_roundMagUp_T \| roundMagUp; // @[RoundAnyRawFNToRecFN.scala:98:42, :243:{32,60}] wire _pegMinNonzeroMagOut_T = commonCase & common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :237:61, :245:20] wire _pegMinNonzeroMagOut_T_1 = roundMagUp \| roundingMode_odd; // @[RoundAnyRawFNToRecFN.scala:95:53, :98:42, :245:60] wire pegMinNonzeroMagOut = _pegMinNonzeroMagOut_T & _pegMinNonzeroMagOut_T_1; // @[RoundAnyRawFNToRecFN.scala:245:{20,45,60}] wire _pegMaxFiniteMagOut_T = ~overflow_roundMagUp; // @[RoundAnyRawFNToRecFN.scala:243:60, :246:42] wire pegMaxFiniteMagOut = overflow & _pegMaxFiniteMagOut_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :246:{39,42}] wire _notNaN_isInfOut_T = overflow & overflow_roundMagUp; // @[RoundAnyRawFNToRecFN.scala:238:32, :243:60, :248:45] wire notNaN_isInfOut = notNaN_isSpecialInfOut \| _notNaN_isInfOut_T; // @[RoundAnyRawFNToRecFN.scala:236:49, :248:{32,45}] wire signOut = ~isNaNOut & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22] wire _expOut_T = io_in_isZero_0 \| common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:48:5, :125:37, :253:32] wire [8:0] _expOut_T_1 = _expOut_T ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}] wire [8:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}] wire [8:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14] wire [8:0] _expOut_T_5 = pegMinNonzeroMagOut ? 9'h194 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:245:45, :257:18] wire [8:0] _expOut_T_6 = ~_expOut_T_5; // @[RoundAnyRawFNToRecFN.scala:257:{14,18}] wire [8:0] _expOut_T_7 = _expOut_T_3 & _expOut_T_6; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17, :257:14] wire [8:0] _expOut_T_8 = {1'h0, pegMaxFiniteMagOut, 7'h0}; // @[RoundAnyRawFNToRecFN.scala:246:39, :261:18] wire [8:0] _expOut_T_9 = ~_expOut_T_8; // @[RoundAnyRawFNToRecFN.scala:261:{14,18}] wire [8:0] _expOut_T_10 = _expOut_T_7 & _expOut_T_9; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17, :261:14] wire [8:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 6'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18] wire [8:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}] wire [8:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14] wire [8:0] _expOut_T_14 = pegMinNonzeroMagOut ? 9'h6B : 9'h0; // @[RoundAnyRawFNToRecFN.scala:245:45, :269:16] wire [8:0] _expOut_T_15 = _expOut_T_13 \| _expOut_T_14; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18, :269:16] wire [8:0] _expOut_T_16 = pegMaxFiniteMagOut ? 9'h17F : 9'h0; // @[RoundAnyRawFNToRecFN.scala:246:39, :273:16] wire [8:0] _expOut_T_17 = _expOut_T_15 \| _expOut_T_16; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15, :273:16] wire [8:0] _expOut_T_18 = notNaN_isInfOut ? 9'h180 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16] wire [8:0] _expOut_T_19 = _expOut_T_17 \| _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16] wire [8:0] _expOut_T_20 = isNaNOut ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:235:34, :278:16] wire [8:0] expOut = _expOut_T_19 \| _expOut_T_20; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16] wire _fractOut_T = isNaNOut \| io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22] wire _fractOut_T_1 = _fractOut_T \| common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :280:{22,38}] wire [22:0] _fractOut_T_2 = {isNaNOut, 22'h0}; // @[RoundAnyRawFNToRecFN.scala:235:34, :281:16] wire [22:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16] wire [22:0] _fractOut_T_4 = {23{pegMaxFiniteMagOut}}; // @[RoundAnyRawFNToRecFN.scala:246:39, :284:13] wire [22:0] fractOut = _fractOut_T_3 \| _fractOut_T_4; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11, :284:13] wire [9:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23] assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}] assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33] wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, 1'h0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:23] wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, overflow}; // @[RoundAnyRawFNToRecFN.scala:238:32, :288:{23,41}] wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, underflow}; // @[RoundAnyRawFNToRecFN.scala:239:32, :288:{41,53}] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}] assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetRegVec_w1_i0_52 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>} node _reg_T = asAsyncReset(reset) regreset reg : UInt<1>, clock, _reg_T, UInt<1>(0h0) when io.en : connect reg, io.d connect io.q, reg	module AsyncResetRegVec_w1_i0_52( // @[AsyncResetReg.scala:56:7] input clock, // @[AsyncResetReg.scala:56:7] input reset, // @[AsyncResetReg.scala:56:7] input io_d, // @[AsyncResetReg.scala:59:14] output io_q // @[AsyncResetReg.scala:59:14] ); wire io_d_0 = io_d; // @[AsyncResetReg.scala:56:7] wire _reg_T = reset; // @[AsyncResetReg.scala:61:29] wire io_en = 1'h1; // @[AsyncResetReg.scala:56:7, :59:14] wire io_q_0; // @[AsyncResetReg.scala:56:7] reg reg_0; // @[AsyncResetReg.scala:61:50] assign io_q_0 = reg_0; // @[AsyncResetReg.scala:56:7, :61:50] always @(posedge clock or posedge _reg_T) begin // @[AsyncResetReg.scala:56:7, :61:29] if (_reg_T) // @[AsyncResetReg.scala:56:7, :61:29] reg_0 <= 1'h0; // @[AsyncResetReg.scala:61:50] else // @[AsyncResetReg.scala:56:7] reg_0 <= io_d_0; // @[AsyncResetReg.scala:56:7, :61:50] always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_122 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<6>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_15 : node _T_16 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_17 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_18 = and(_T_16, _T_17) node _T_19 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_20 = and(_T_18, _T_19) node _T_21 = or(UInt<1>(0h0), _T_20) node _T_22 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_23 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_24 = cvt(_T_23) node _T_25 = and(_T_24, asSInt(UInt<14>(0h2000))) node _T_26 = asSInt(_T_25) node _T_27 = eq(_T_26, asSInt(UInt<1>(0h0))) node _T_28 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_29 = cvt(_T_28) node _T_30 = and(_T_29, asSInt(UInt<13>(0h1000))) node _T_31 = asSInt(_T_30) node _T_32 = eq(_T_31, asSInt(UInt<1>(0h0))) node _T_33 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_39 = cvt(_T_38) node _T_40 = and(_T_39, asSInt(UInt<18>(0h2f000))) node _T_41 = asSInt(_T_40) node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0))) node _T_43 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_44 = cvt(_T_43) node _T_45 = and(_T_44, asSInt(UInt<17>(0h10000))) node _T_46 = asSInt(_T_45) node _T_47 = eq(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_54 = cvt(_T_53) node _T_55 = and(_T_54, asSInt(UInt<27>(0h4000000))) node _T_56 = asSInt(_T_55) node _T_57 = eq(_T_56, asSInt(UInt<1>(0h0))) node _T_58 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<13>(0h1000))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_27, _T_32) node _T_64 = or(_T_63, _T_37) node _T_65 = or(_T_64, _T_42) node _T_66 = or(_T_65, _T_47) node _T_67 = or(_T_66, _T_52) node _T_68 = or(_T_67, _T_57) node _T_69 = or(_T_68, _T_62) node _T_70 = and(_T_22, _T_69) node _T_71 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_72 = or(UInt<1>(0h0), _T_71) node _T_73 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_74 = cvt(_T_73) node _T_75 = and(_T_74, asSInt(UInt<17>(0h10000))) node _T_76 = asSInt(_T_75) node _T_77 = eq(_T_76, asSInt(UInt<1>(0h0))) node _T_78 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_79 = cvt(_T_78) node _T_80 = and(_T_79, asSInt(UInt<29>(0h10000000))) node _T_81 = asSInt(_T_80) node _T_82 = eq(_T_81, asSInt(UInt<1>(0h0))) node _T_83 = or(_T_77, _T_82) node _T_84 = and(_T_72, _T_83) node _T_85 = or(UInt<1>(0h0), _T_70) node _T_86 = or(_T_85, _T_84) node _T_87 = and(_T_21, _T_86) node _T_88 = asUInt(reset) node _T_89 = eq(_T_88, UInt<1>(0h0)) when _T_89 : node _T_90 = eq(_T_87, UInt<1>(0h0)) when _T_90 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_87, UInt<1>(0h1), "") : assert_2 node _T_91 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_92 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_93 = and(_T_91, _T_92) node _T_94 = or(UInt<1>(0h0), _T_93) node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<14>(0h2000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_101 = cvt(_T_100) node _T_102 = and(_T_101, asSInt(UInt<13>(0h1000))) node _T_103 = asSInt(_T_102) node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0))) node _T_105 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_106 = cvt(_T_105) node _T_107 = and(_T_106, asSInt(UInt<17>(0h10000))) node _T_108 = asSInt(_T_107) node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0))) node _T_110 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<18>(0h2f000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_116 = cvt(_T_115) node _T_117 = and(_T_116, asSInt(UInt<17>(0h10000))) node _T_118 = asSInt(_T_117) node _T_119 = eq(_T_118, asSInt(UInt<1>(0h0))) node _T_120 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_121 = cvt(_T_120) node _T_122 = and(_T_121, asSInt(UInt<13>(0h1000))) node _T_123 = asSInt(_T_122) node _T_124 = eq(_T_123, asSInt(UInt<1>(0h0))) node _T_125 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_126 = cvt(_T_125) node _T_127 = and(_T_126, asSInt(UInt<17>(0h10000))) node _T_128 = asSInt(_T_127) node _T_129 = eq(_T_128, asSInt(UInt<1>(0h0))) node _T_130 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_131 = cvt(_T_130) node _T_132 = and(_T_131, asSInt(UInt<27>(0h4000000))) node _T_133 = asSInt(_T_132) node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0))) node _T_135 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_136 = cvt(_T_135) node _T_137 = and(_T_136, asSInt(UInt<13>(0h1000))) node _T_138 = asSInt(_T_137) node _T_139 = eq(_T_138, asSInt(UInt<1>(0h0))) node _T_140 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_141 = cvt(_T_140) node _T_142 = and(_T_141, asSInt(UInt<29>(0h10000000))) node _T_143 = asSInt(_T_142) node _T_144 = eq(_T_143, asSInt(UInt<1>(0h0))) node _T_145 = or(_T_99, _T_104) node _T_146 = or(_T_145, _T_109) node _T_147 = or(_T_146, _T_114) node _T_148 = or(_T_147, _T_119) node _T_149 = or(_T_148, _T_124) node _T_150 = or(_T_149, _T_129) node _T_151 = or(_T_150, _T_134) node _T_152 = or(_T_151, _T_139) node _T_153 = or(_T_152, _T_144) node _T_154 = and(_T_94, _T_153) node _T_155 = or(UInt<1>(0h0), _T_154) node _T_156 = and(UInt<1>(0h0), _T_155) node _T_157 = asUInt(reset) node _T_158 = eq(_T_157, UInt<1>(0h0)) when _T_158 : node _T_159 = eq(_T_156, UInt<1>(0h0)) when _T_159 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_156, UInt<1>(0h1), "") : assert_3 node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_163 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_164 = asUInt(reset) node _T_165 = eq(_T_164, UInt<1>(0h0)) when _T_165 : node _T_166 = eq(_T_163, UInt<1>(0h0)) when _T_166 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_163, UInt<1>(0h1), "") : assert_5 node _T_167 = asUInt(reset) node _T_168 = eq(_T_167, UInt<1>(0h0)) when _T_168 : node _T_169 = eq(is_aligned, UInt<1>(0h0)) when _T_169 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_170 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_171 = asUInt(reset) node _T_172 = eq(_T_171, UInt<1>(0h0)) when _T_172 : node _T_173 = eq(_T_170, UInt<1>(0h0)) when _T_173 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_170, UInt<1>(0h1), "") : assert_7 node _T_174 = not(io.in.a.bits.mask) node _T_175 = eq(_T_174, UInt<1>(0h0)) node _T_176 = asUInt(reset) node _T_177 = eq(_T_176, UInt<1>(0h0)) when _T_177 : node _T_178 = eq(_T_175, UInt<1>(0h0)) when _T_178 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_175, UInt<1>(0h1), "") : assert_8 node _T_179 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(_T_179, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_179, UInt<1>(0h1), "") : assert_9 node _T_183 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_183 : node _T_184 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_185 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_186 = and(_T_184, _T_185) node _T_187 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_188 = and(_T_186, _T_187) node _T_189 = or(UInt<1>(0h0), _T_188) node _T_190 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_191 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_192 = cvt(_T_191) node _T_193 = and(_T_192, asSInt(UInt<14>(0h2000))) node _T_194 = asSInt(_T_193) node _T_195 = eq(_T_194, asSInt(UInt<1>(0h0))) node _T_196 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_197 = cvt(_T_196) node _T_198 = and(_T_197, asSInt(UInt<13>(0h1000))) node _T_199 = asSInt(_T_198) node _T_200 = eq(_T_199, asSInt(UInt<1>(0h0))) node _T_201 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_202 = cvt(_T_201) node _T_203 = and(_T_202, asSInt(UInt<17>(0h10000))) node _T_204 = asSInt(_T_203) node _T_205 = eq(_T_204, asSInt(UInt<1>(0h0))) node _T_206 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_207 = cvt(_T_206) node _T_208 = and(_T_207, asSInt(UInt<18>(0h2f000))) node _T_209 = asSInt(_T_208) node _T_210 = eq(_T_209, asSInt(UInt<1>(0h0))) node _T_211 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<17>(0h10000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_217 = cvt(_T_216) node _T_218 = and(_T_217, asSInt(UInt<13>(0h1000))) node _T_219 = asSInt(_T_218) node _T_220 = eq(_T_219, asSInt(UInt<1>(0h0))) node _T_221 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_222 = cvt(_T_221) node _T_223 = and(_T_222, asSInt(UInt<27>(0h4000000))) node _T_224 = asSInt(_T_223) node _T_225 = eq(_T_224, asSInt(UInt<1>(0h0))) node _T_226 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<13>(0h1000))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = or(_T_195, _T_200) node _T_232 = or(_T_231, _T_205) node _T_233 = or(_T_232, _T_210) node _T_234 = or(_T_233, _T_215) node _T_235 = or(_T_234, _T_220) node _T_236 = or(_T_235, _T_225) node _T_237 = or(_T_236, _T_230) node _T_238 = and(_T_190, _T_237) node _T_239 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_240 = or(UInt<1>(0h0), _T_239) node _T_241 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_242 = cvt(_T_241) node _T_243 = and(_T_242, asSInt(UInt<17>(0h10000))) node _T_244 = asSInt(_T_243) node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0))) node _T_246 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_247 = cvt(_T_246) node _T_248 = and(_T_247, asSInt(UInt<29>(0h10000000))) node _T_249 = asSInt(_T_248) node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0))) node _T_251 = or(_T_245, _T_250) node _T_252 = and(_T_240, _T_251) node _T_253 = or(UInt<1>(0h0), _T_238) node _T_254 = or(_T_253, _T_252) node _T_255 = and(_T_189, _T_254) node _T_256 = asUInt(reset) node _T_257 = eq(_T_256, UInt<1>(0h0)) when _T_257 : node _T_258 = eq(_T_255, UInt<1>(0h0)) when _T_258 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_255, UInt<1>(0h1), "") : assert_10 node _T_259 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_260 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_261 = and(_T_259, _T_260) node _T_262 = or(UInt<1>(0h0), _T_261) node _T_263 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_264 = cvt(_T_263) node _T_265 = and(_T_264, asSInt(UInt<14>(0h2000))) node _T_266 = asSInt(_T_265) node _T_267 = eq(_T_266, asSInt(UInt<1>(0h0))) node _T_268 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_269 = cvt(_T_268) node _T_270 = and(_T_269, asSInt(UInt<13>(0h1000))) node _T_271 = asSInt(_T_270) node _T_272 = eq(_T_271, asSInt(UInt<1>(0h0))) node _T_273 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_274 = cvt(_T_273) node _T_275 = and(_T_274, asSInt(UInt<17>(0h10000))) node _T_276 = asSInt(_T_275) node _T_277 = eq(_T_276, asSInt(UInt<1>(0h0))) node _T_278 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_279 = cvt(_T_278) node _T_280 = and(_T_279, asSInt(UInt<18>(0h2f000))) node _T_281 = asSInt(_T_280) node _T_282 = eq(_T_281, asSInt(UInt<1>(0h0))) node _T_283 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_284 = cvt(_T_283) node _T_285 = and(_T_284, asSInt(UInt<17>(0h10000))) node _T_286 = asSInt(_T_285) node _T_287 = eq(_T_286, asSInt(UInt<1>(0h0))) node _T_288 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_289 = cvt(_T_288) node _T_290 = and(_T_289, asSInt(UInt<13>(0h1000))) node _T_291 = asSInt(_T_290) node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0))) node _T_293 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_294 = cvt(_T_293) node _T_295 = and(_T_294, asSInt(UInt<17>(0h10000))) node _T_296 = asSInt(_T_295) node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0))) node _T_298 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_299 = cvt(_T_298) node _T_300 = and(_T_299, asSInt(UInt<27>(0h4000000))) node _T_301 = asSInt(_T_300) node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0))) node _T_303 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_304 = cvt(_T_303) node _T_305 = and(_T_304, asSInt(UInt<13>(0h1000))) node _T_306 = asSInt(_T_305) node _T_307 = eq(_T_306, asSInt(UInt<1>(0h0))) node _T_308 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_309 = cvt(_T_308) node _T_310 = and(_T_309, asSInt(UInt<29>(0h10000000))) node _T_311 = asSInt(_T_310) node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0))) node _T_313 = or(_T_267, _T_272) node _T_314 = or(_T_313, _T_277) node _T_315 = or(_T_314, _T_282) node _T_316 = or(_T_315, _T_287) node _T_317 = or(_T_316, _T_292) node _T_318 = or(_T_317, _T_297) node _T_319 = or(_T_318, _T_302) node _T_320 = or(_T_319, _T_307) node _T_321 = or(_T_320, _T_312) node _T_322 = and(_T_262, _T_321) node _T_323 = or(UInt<1>(0h0), _T_322) node _T_324 = and(UInt<1>(0h0), _T_323) node _T_325 = asUInt(reset) node _T_326 = eq(_T_325, UInt<1>(0h0)) when _T_326 : node _T_327 = eq(_T_324, UInt<1>(0h0)) when _T_327 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_324, UInt<1>(0h1), "") : assert_11 node _T_328 = asUInt(reset) node _T_329 = eq(_T_328, UInt<1>(0h0)) when _T_329 : node _T_330 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_330 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_331 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_332 = asUInt(reset) node _T_333 = eq(_T_332, UInt<1>(0h0)) when _T_333 : node _T_334 = eq(_T_331, UInt<1>(0h0)) when _T_334 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_331, UInt<1>(0h1), "") : assert_13 node _T_335 = asUInt(reset) node _T_336 = eq(_T_335, UInt<1>(0h0)) when _T_336 : node _T_337 = eq(is_aligned, UInt<1>(0h0)) when _T_337 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_338 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(_T_338, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_338, UInt<1>(0h1), "") : assert_15 node _T_342 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_343 = asUInt(reset) node _T_344 = eq(_T_343, UInt<1>(0h0)) when _T_344 : node _T_345 = eq(_T_342, UInt<1>(0h0)) when _T_345 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_342, UInt<1>(0h1), "") : assert_16 node _T_346 = not(io.in.a.bits.mask) node _T_347 = eq(_T_346, UInt<1>(0h0)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_347, UInt<1>(0h1), "") : assert_17 node _T_351 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_351, UInt<1>(0h1), "") : assert_18 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _T_359 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_360 = and(_T_358, _T_359) node _T_361 = or(UInt<1>(0h0), _T_360) node _T_362 = asUInt(reset) node _T_363 = eq(_T_362, UInt<1>(0h0)) when _T_363 : node _T_364 = eq(_T_361, UInt<1>(0h0)) when _T_364 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_361, UInt<1>(0h1), "") : assert_19 node _T_365 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_366 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_367 = and(_T_365, _T_366) node _T_368 = or(UInt<1>(0h0), _T_367) node _T_369 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_370 = cvt(_T_369) node _T_371 = and(_T_370, asSInt(UInt<13>(0h1000))) node _T_372 = asSInt(_T_371) node _T_373 = eq(_T_372, asSInt(UInt<1>(0h0))) node _T_374 = and(_T_368, _T_373) node _T_375 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_376 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_377 = and(_T_375, _T_376) node _T_378 = or(UInt<1>(0h0), _T_377) node _T_379 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_380 = cvt(_T_379) node _T_381 = and(_T_380, asSInt(UInt<14>(0h2000))) node _T_382 = asSInt(_T_381) node _T_383 = eq(_T_382, asSInt(UInt<1>(0h0))) node _T_384 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_385 = cvt(_T_384) node _T_386 = and(_T_385, asSInt(UInt<17>(0h10000))) node _T_387 = asSInt(_T_386) node _T_388 = eq(_T_387, asSInt(UInt<1>(0h0))) node _T_389 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_390 = cvt(_T_389) node _T_391 = and(_T_390, asSInt(UInt<18>(0h2f000))) node _T_392 = asSInt(_T_391) node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0))) node _T_394 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_395 = cvt(_T_394) node _T_396 = and(_T_395, asSInt(UInt<17>(0h10000))) node _T_397 = asSInt(_T_396) node _T_398 = eq(_T_397, asSInt(UInt<1>(0h0))) node _T_399 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_400 = cvt(_T_399) node _T_401 = and(_T_400, asSInt(UInt<13>(0h1000))) node _T_402 = asSInt(_T_401) node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0))) node _T_404 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_405 = cvt(_T_404) node _T_406 = and(_T_405, asSInt(UInt<17>(0h10000))) node _T_407 = asSInt(_T_406) node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0))) node _T_409 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_410 = cvt(_T_409) node _T_411 = and(_T_410, asSInt(UInt<27>(0h4000000))) node _T_412 = asSInt(_T_411) node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0))) node _T_414 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_415 = cvt(_T_414) node _T_416 = and(_T_415, asSInt(UInt<13>(0h1000))) node _T_417 = asSInt(_T_416) node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0))) node _T_419 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_420 = cvt(_T_419) node _T_421 = and(_T_420, asSInt(UInt<29>(0h10000000))) node _T_422 = asSInt(_T_421) node _T_423 = eq(_T_422, asSInt(UInt<1>(0h0))) node _T_424 = or(_T_383, _T_388) node _T_425 = or(_T_424, _T_393) node _T_426 = or(_T_425, _T_398) node _T_427 = or(_T_426, _T_403) node _T_428 = or(_T_427, _T_408) node _T_429 = or(_T_428, _T_413) node _T_430 = or(_T_429, _T_418) node _T_431 = or(_T_430, _T_423) node _T_432 = and(_T_378, _T_431) node _T_433 = or(UInt<1>(0h0), _T_374) node _T_434 = or(_T_433, _T_432) node _T_435 = asUInt(reset) node _T_436 = eq(_T_435, UInt<1>(0h0)) when _T_436 : node _T_437 = eq(_T_434, UInt<1>(0h0)) when _T_437 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_434, UInt<1>(0h1), "") : assert_20 node _T_438 = asUInt(reset) node _T_439 = eq(_T_438, UInt<1>(0h0)) when _T_439 : node _T_440 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_440 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(is_aligned, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_444 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_445 = asUInt(reset) node _T_446 = eq(_T_445, UInt<1>(0h0)) when _T_446 : node _T_447 = eq(_T_444, UInt<1>(0h0)) when _T_447 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_444, UInt<1>(0h1), "") : assert_23 node _T_448 = eq(io.in.a.bits.mask, mask) node _T_449 = asUInt(reset) node _T_450 = eq(_T_449, UInt<1>(0h0)) when _T_450 : node _T_451 = eq(_T_448, UInt<1>(0h0)) when _T_451 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_448, UInt<1>(0h1), "") : assert_24 node _T_452 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(_T_452, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_452, UInt<1>(0h1), "") : assert_25 node _T_456 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_456 : node _T_457 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_458 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_459 = and(_T_457, _T_458) node _T_460 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_461 = and(_T_459, _T_460) node _T_462 = or(UInt<1>(0h0), _T_461) node _T_463 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_464 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_465 = and(_T_463, _T_464) node _T_466 = or(UInt<1>(0h0), _T_465) node _T_467 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_468 = cvt(_T_467) node _T_469 = and(_T_468, asSInt(UInt<13>(0h1000))) node _T_470 = asSInt(_T_469) node _T_471 = eq(_T_470, asSInt(UInt<1>(0h0))) node _T_472 = and(_T_466, _T_471) node _T_473 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_474 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_475 = and(_T_473, _T_474) node _T_476 = or(UInt<1>(0h0), _T_475) node _T_477 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_478 = cvt(_T_477) node _T_479 = and(_T_478, asSInt(UInt<14>(0h2000))) node _T_480 = asSInt(_T_479) node _T_481 = eq(_T_480, asSInt(UInt<1>(0h0))) node _T_482 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_483 = cvt(_T_482) node _T_484 = and(_T_483, asSInt(UInt<18>(0h2f000))) node _T_485 = asSInt(_T_484) node _T_486 = eq(_T_485, asSInt(UInt<1>(0h0))) node _T_487 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_488 = cvt(_T_487) node _T_489 = and(_T_488, asSInt(UInt<17>(0h10000))) node _T_490 = asSInt(_T_489) node _T_491 = eq(_T_490, asSInt(UInt<1>(0h0))) node _T_492 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_493 = cvt(_T_492) node _T_494 = and(_T_493, asSInt(UInt<13>(0h1000))) node _T_495 = asSInt(_T_494) node _T_496 = eq(_T_495, asSInt(UInt<1>(0h0))) node _T_497 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_498 = cvt(_T_497) node _T_499 = and(_T_498, asSInt(UInt<17>(0h10000))) node _T_500 = asSInt(_T_499) node _T_501 = eq(_T_500, asSInt(UInt<1>(0h0))) node _T_502 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_503 = cvt(_T_502) node _T_504 = and(_T_503, asSInt(UInt<27>(0h4000000))) node _T_505 = asSInt(_T_504) node _T_506 = eq(_T_505, asSInt(UInt<1>(0h0))) node _T_507 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_508 = cvt(_T_507) node _T_509 = and(_T_508, asSInt(UInt<13>(0h1000))) node _T_510 = asSInt(_T_509) node _T_511 = eq(_T_510, asSInt(UInt<1>(0h0))) node _T_512 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_513 = cvt(_T_512) node _T_514 = and(_T_513, asSInt(UInt<29>(0h10000000))) node _T_515 = asSInt(_T_514) node _T_516 = eq(_T_515, asSInt(UInt<1>(0h0))) node _T_517 = or(_T_481, _T_486) node _T_518 = or(_T_517, _T_491) node _T_519 = or(_T_518, _T_496) node _T_520 = or(_T_519, _T_501) node _T_521 = or(_T_520, _T_506) node _T_522 = or(_T_521, _T_511) node _T_523 = or(_T_522, _T_516) node _T_524 = and(_T_476, _T_523) node _T_525 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_526 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_527 = cvt(_T_526) node _T_528 = and(_T_527, asSInt(UInt<17>(0h10000))) node _T_529 = asSInt(_T_528) node _T_530 = eq(_T_529, asSInt(UInt<1>(0h0))) node _T_531 = and(_T_525, _T_530) node _T_532 = or(UInt<1>(0h0), _T_472) node _T_533 = or(_T_532, _T_524) node _T_534 = or(_T_533, _T_531) node _T_535 = and(_T_462, _T_534) node _T_536 = asUInt(reset) node _T_537 = eq(_T_536, UInt<1>(0h0)) when _T_537 : node _T_538 = eq(_T_535, UInt<1>(0h0)) when _T_538 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_535, UInt<1>(0h1), "") : assert_26 node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_542 = asUInt(reset) node _T_543 = eq(_T_542, UInt<1>(0h0)) when _T_543 : node _T_544 = eq(is_aligned, UInt<1>(0h0)) when _T_544 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_545 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_546 = asUInt(reset) node _T_547 = eq(_T_546, UInt<1>(0h0)) when _T_547 : node _T_548 = eq(_T_545, UInt<1>(0h0)) when _T_548 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_545, UInt<1>(0h1), "") : assert_29 node _T_549 = eq(io.in.a.bits.mask, mask) node _T_550 = asUInt(reset) node _T_551 = eq(_T_550, UInt<1>(0h0)) when _T_551 : node _T_552 = eq(_T_549, UInt<1>(0h0)) when _T_552 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_549, UInt<1>(0h1), "") : assert_30 node _T_553 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_553 : node _T_554 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_555 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_556 = and(_T_554, _T_555) node _T_557 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_558 = and(_T_556, _T_557) node _T_559 = or(UInt<1>(0h0), _T_558) node _T_560 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_561 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_562 = and(_T_560, _T_561) node _T_563 = or(UInt<1>(0h0), _T_562) node _T_564 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_565 = cvt(_T_564) node _T_566 = and(_T_565, asSInt(UInt<13>(0h1000))) node _T_567 = asSInt(_T_566) node _T_568 = eq(_T_567, asSInt(UInt<1>(0h0))) node _T_569 = and(_T_563, _T_568) node _T_570 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_571 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_572 = and(_T_570, _T_571) node _T_573 = or(UInt<1>(0h0), _T_572) node _T_574 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_575 = cvt(_T_574) node _T_576 = and(_T_575, asSInt(UInt<14>(0h2000))) node _T_577 = asSInt(_T_576) node _T_578 = eq(_T_577, asSInt(UInt<1>(0h0))) node _T_579 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_580 = cvt(_T_579) node _T_581 = and(_T_580, asSInt(UInt<18>(0h2f000))) node _T_582 = asSInt(_T_581) node _T_583 = eq(_T_582, asSInt(UInt<1>(0h0))) node _T_584 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_585 = cvt(_T_584) node _T_586 = and(_T_585, asSInt(UInt<17>(0h10000))) node _T_587 = asSInt(_T_586) node _T_588 = eq(_T_587, asSInt(UInt<1>(0h0))) node _T_589 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_590 = cvt(_T_589) node _T_591 = and(_T_590, asSInt(UInt<13>(0h1000))) node _T_592 = asSInt(_T_591) node _T_593 = eq(_T_592, asSInt(UInt<1>(0h0))) node _T_594 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_595 = cvt(_T_594) node _T_596 = and(_T_595, asSInt(UInt<17>(0h10000))) node _T_597 = asSInt(_T_596) node _T_598 = eq(_T_597, asSInt(UInt<1>(0h0))) node _T_599 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_600 = cvt(_T_599) node _T_601 = and(_T_600, asSInt(UInt<27>(0h4000000))) node _T_602 = asSInt(_T_601) node _T_603 = eq(_T_602, asSInt(UInt<1>(0h0))) node _T_604 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_605 = cvt(_T_604) node _T_606 = and(_T_605, asSInt(UInt<13>(0h1000))) node _T_607 = asSInt(_T_606) node _T_608 = eq(_T_607, asSInt(UInt<1>(0h0))) node _T_609 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_610 = cvt(_T_609) node _T_611 = and(_T_610, asSInt(UInt<29>(0h10000000))) node _T_612 = asSInt(_T_611) node _T_613 = eq(_T_612, asSInt(UInt<1>(0h0))) node _T_614 = or(_T_578, _T_583) node _T_615 = or(_T_614, _T_588) node _T_616 = or(_T_615, _T_593) node _T_617 = or(_T_616, _T_598) node _T_618 = or(_T_617, _T_603) node _T_619 = or(_T_618, _T_608) node _T_620 = or(_T_619, _T_613) node _T_621 = and(_T_573, _T_620) node _T_622 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_623 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_624 = cvt(_T_623) node _T_625 = and(_T_624, asSInt(UInt<17>(0h10000))) node _T_626 = asSInt(_T_625) node _T_627 = eq(_T_626, asSInt(UInt<1>(0h0))) node _T_628 = and(_T_622, _T_627) node _T_629 = or(UInt<1>(0h0), _T_569) node _T_630 = or(_T_629, _T_621) node _T_631 = or(_T_630, _T_628) node _T_632 = and(_T_559, _T_631) node _T_633 = asUInt(reset) node _T_634 = eq(_T_633, UInt<1>(0h0)) when _T_634 : node _T_635 = eq(_T_632, UInt<1>(0h0)) when _T_635 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_632, UInt<1>(0h1), "") : assert_31 node _T_636 = asUInt(reset) node _T_637 = eq(_T_636, UInt<1>(0h0)) when _T_637 : node _T_638 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_638 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_639 = asUInt(reset) node _T_640 = eq(_T_639, UInt<1>(0h0)) when _T_640 : node _T_641 = eq(is_aligned, UInt<1>(0h0)) when _T_641 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_642 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_643 = asUInt(reset) node _T_644 = eq(_T_643, UInt<1>(0h0)) when _T_644 : node _T_645 = eq(_T_642, UInt<1>(0h0)) when _T_645 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_642, UInt<1>(0h1), "") : assert_34 node _T_646 = not(mask) node _T_647 = and(io.in.a.bits.mask, _T_646) node _T_648 = eq(_T_647, UInt<1>(0h0)) node _T_649 = asUInt(reset) node _T_650 = eq(_T_649, UInt<1>(0h0)) when _T_650 : node _T_651 = eq(_T_648, UInt<1>(0h0)) when _T_651 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_648, UInt<1>(0h1), "") : assert_35 node _T_652 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_652 : node _T_653 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_654 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_655 = and(_T_653, _T_654) node _T_656 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_657 = and(_T_655, _T_656) node _T_658 = or(UInt<1>(0h0), _T_657) node _T_659 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_660 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_661 = and(_T_659, _T_660) node _T_662 = or(UInt<1>(0h0), _T_661) node _T_663 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_664 = cvt(_T_663) node _T_665 = and(_T_664, asSInt(UInt<14>(0h2000))) node _T_666 = asSInt(_T_665) node _T_667 = eq(_T_666, asSInt(UInt<1>(0h0))) node _T_668 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_669 = cvt(_T_668) node _T_670 = and(_T_669, asSInt(UInt<13>(0h1000))) node _T_671 = asSInt(_T_670) node _T_672 = eq(_T_671, asSInt(UInt<1>(0h0))) node _T_673 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_674 = cvt(_T_673) node _T_675 = and(_T_674, asSInt(UInt<18>(0h2f000))) node _T_676 = asSInt(_T_675) node _T_677 = eq(_T_676, asSInt(UInt<1>(0h0))) node _T_678 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_679 = cvt(_T_678) node _T_680 = and(_T_679, asSInt(UInt<17>(0h10000))) node _T_681 = asSInt(_T_680) node _T_682 = eq(_T_681, asSInt(UInt<1>(0h0))) node _T_683 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_684 = cvt(_T_683) node _T_685 = and(_T_684, asSInt(UInt<13>(0h1000))) node _T_686 = asSInt(_T_685) node _T_687 = eq(_T_686, asSInt(UInt<1>(0h0))) node _T_688 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_689 = cvt(_T_688) node _T_690 = and(_T_689, asSInt(UInt<27>(0h4000000))) node _T_691 = asSInt(_T_690) node _T_692 = eq(_T_691, asSInt(UInt<1>(0h0))) node _T_693 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_694 = cvt(_T_693) node _T_695 = and(_T_694, asSInt(UInt<13>(0h1000))) node _T_696 = asSInt(_T_695) node _T_697 = eq(_T_696, asSInt(UInt<1>(0h0))) node _T_698 = or(_T_667, _T_672) node _T_699 = or(_T_698, _T_677) node _T_700 = or(_T_699, _T_682) node _T_701 = or(_T_700, _T_687) node _T_702 = or(_T_701, _T_692) node _T_703 = or(_T_702, _T_697) node _T_704 = and(_T_662, _T_703) node _T_705 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_706 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_707 = cvt(_T_706) node _T_708 = and(_T_707, asSInt(UInt<17>(0h10000))) node _T_709 = asSInt(_T_708) node _T_710 = eq(_T_709, asSInt(UInt<1>(0h0))) node _T_711 = and(_T_705, _T_710) node _T_712 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_713 = leq(io.in.a.bits.size, UInt<3>(0h4)) node _T_714 = and(_T_712, _T_713) node _T_715 = or(UInt<1>(0h0), _T_714) node _T_716 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_717 = cvt(_T_716) node _T_718 = and(_T_717, asSInt(UInt<17>(0h10000))) node _T_719 = asSInt(_T_718) node _T_720 = eq(_T_719, asSInt(UInt<1>(0h0))) node _T_721 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_722 = cvt(_T_721) node _T_723 = and(_T_722, asSInt(UInt<29>(0h10000000))) node _T_724 = asSInt(_T_723) node _T_725 = eq(_T_724, asSInt(UInt<1>(0h0))) node _T_726 = or(_T_720, _T_725) node _T_727 = and(_T_715, _T_726) node _T_728 = or(UInt<1>(0h0), _T_704) node _T_729 = or(_T_728, _T_711) node _T_730 = or(_T_729, _T_727) node _T_731 = and(_T_658, _T_730) node _T_732 = asUInt(reset) node _T_733 = eq(_T_732, UInt<1>(0h0)) when _T_733 : node _T_734 = eq(_T_731, UInt<1>(0h0)) when _T_734 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_731, UInt<1>(0h1), "") : assert_36 node _T_735 = asUInt(reset) node _T_736 = eq(_T_735, UInt<1>(0h0)) when _T_736 : node _T_737 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_737 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_738 = asUInt(reset) node _T_739 = eq(_T_738, UInt<1>(0h0)) when _T_739 : node _T_740 = eq(is_aligned, UInt<1>(0h0)) when _T_740 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_741 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_742 = asUInt(reset) node _T_743 = eq(_T_742, UInt<1>(0h0)) when _T_743 : node _T_744 = eq(_T_741, UInt<1>(0h0)) when _T_744 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_741, UInt<1>(0h1), "") : assert_39 node _T_745 = eq(io.in.a.bits.mask, mask) node _T_746 = asUInt(reset) node _T_747 = eq(_T_746, UInt<1>(0h0)) when _T_747 : node _T_748 = eq(_T_745, UInt<1>(0h0)) when _T_748 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_745, UInt<1>(0h1), "") : assert_40 node _T_749 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_749 : node _T_750 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_751 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_752 = and(_T_750, _T_751) node _T_753 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_754 = and(_T_752, _T_753) node _T_755 = or(UInt<1>(0h0), _T_754) node _T_756 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_757 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_758 = and(_T_756, _T_757) node _T_759 = or(UInt<1>(0h0), _T_758) node _T_760 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_761 = cvt(_T_760) node _T_762 = and(_T_761, asSInt(UInt<14>(0h2000))) node _T_763 = asSInt(_T_762) node _T_764 = eq(_T_763, asSInt(UInt<1>(0h0))) node _T_765 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_766 = cvt(_T_765) node _T_767 = and(_T_766, asSInt(UInt<13>(0h1000))) node _T_768 = asSInt(_T_767) node _T_769 = eq(_T_768, asSInt(UInt<1>(0h0))) node _T_770 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_771 = cvt(_T_770) node _T_772 = and(_T_771, asSInt(UInt<18>(0h2f000))) node _T_773 = asSInt(_T_772) node _T_774 = eq(_T_773, asSInt(UInt<1>(0h0))) node _T_775 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_776 = cvt(_T_775) node _T_777 = and(_T_776, asSInt(UInt<17>(0h10000))) node _T_778 = asSInt(_T_777) node _T_779 = eq(_T_778, asSInt(UInt<1>(0h0))) node _T_780 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_781 = cvt(_T_780) node _T_782 = and(_T_781, asSInt(UInt<13>(0h1000))) node _T_783 = asSInt(_T_782) node _T_784 = eq(_T_783, asSInt(UInt<1>(0h0))) node _T_785 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_786 = cvt(_T_785) node _T_787 = and(_T_786, asSInt(UInt<27>(0h4000000))) node _T_788 = asSInt(_T_787) node _T_789 = eq(_T_788, asSInt(UInt<1>(0h0))) node _T_790 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_791 = cvt(_T_790) node _T_792 = and(_T_791, asSInt(UInt<13>(0h1000))) node _T_793 = asSInt(_T_792) node _T_794 = eq(_T_793, asSInt(UInt<1>(0h0))) node _T_795 = or(_T_764, _T_769) node _T_796 = or(_T_795, _T_774) node _T_797 = or(_T_796, _T_779) node _T_798 = or(_T_797, _T_784) node _T_799 = or(_T_798, _T_789) node _T_800 = or(_T_799, _T_794) node _T_801 = and(_T_759, _T_800) node _T_802 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_803 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_804 = cvt(_T_803) node _T_805 = and(_T_804, asSInt(UInt<17>(0h10000))) node _T_806 = asSInt(_T_805) node _T_807 = eq(_T_806, asSInt(UInt<1>(0h0))) node _T_808 = and(_T_802, _T_807) node _T_809 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_810 = leq(io.in.a.bits.size, UInt<3>(0h4)) node _T_811 = and(_T_809, _T_810) node _T_812 = or(UInt<1>(0h0), _T_811) node _T_813 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_814 = cvt(_T_813) node _T_815 = and(_T_814, asSInt(UInt<17>(0h10000))) node _T_816 = asSInt(_T_815) node _T_817 = eq(_T_816, asSInt(UInt<1>(0h0))) node _T_818 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_819 = cvt(_T_818) node _T_820 = and(_T_819, asSInt(UInt<29>(0h10000000))) node _T_821 = asSInt(_T_820) node _T_822 = eq(_T_821, asSInt(UInt<1>(0h0))) node _T_823 = or(_T_817, _T_822) node _T_824 = and(_T_812, _T_823) node _T_825 = or(UInt<1>(0h0), _T_801) node _T_826 = or(_T_825, _T_808) node _T_827 = or(_T_826, _T_824) node _T_828 = and(_T_755, _T_827) node _T_829 = asUInt(reset) node _T_830 = eq(_T_829, UInt<1>(0h0)) when _T_830 : node _T_831 = eq(_T_828, UInt<1>(0h0)) when _T_831 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_828, UInt<1>(0h1), "") : assert_41 node _T_832 = asUInt(reset) node _T_833 = eq(_T_832, UInt<1>(0h0)) when _T_833 : node _T_834 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_834 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_835 = asUInt(reset) node _T_836 = eq(_T_835, UInt<1>(0h0)) when _T_836 : node _T_837 = eq(is_aligned, UInt<1>(0h0)) when _T_837 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_838 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_839 = asUInt(reset) node _T_840 = eq(_T_839, UInt<1>(0h0)) when _T_840 : node _T_841 = eq(_T_838, UInt<1>(0h0)) when _T_841 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_838, UInt<1>(0h1), "") : assert_44 node _T_842 = eq(io.in.a.bits.mask, mask) node _T_843 = asUInt(reset) node _T_844 = eq(_T_843, UInt<1>(0h0)) when _T_844 : node _T_845 = eq(_T_842, UInt<1>(0h0)) when _T_845 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_842, UInt<1>(0h1), "") : assert_45 node _T_846 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_846 : node _T_847 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_848 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_849 = and(_T_847, _T_848) node _T_850 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_851 = and(_T_849, _T_850) node _T_852 = or(UInt<1>(0h0), _T_851) node _T_853 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_854 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_855 = and(_T_853, _T_854) node _T_856 = or(UInt<1>(0h0), _T_855) node _T_857 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_858 = cvt(_T_857) node _T_859 = and(_T_858, asSInt(UInt<13>(0h1000))) node _T_860 = asSInt(_T_859) node _T_861 = eq(_T_860, asSInt(UInt<1>(0h0))) node _T_862 = and(_T_856, _T_861) node _T_863 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_864 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_865 = cvt(_T_864) node _T_866 = and(_T_865, asSInt(UInt<14>(0h2000))) node _T_867 = asSInt(_T_866) node _T_868 = eq(_T_867, asSInt(UInt<1>(0h0))) node _T_869 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_870 = cvt(_T_869) node _T_871 = and(_T_870, asSInt(UInt<17>(0h10000))) node _T_872 = asSInt(_T_871) node _T_873 = eq(_T_872, asSInt(UInt<1>(0h0))) node _T_874 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_875 = cvt(_T_874) node _T_876 = and(_T_875, asSInt(UInt<18>(0h2f000))) node _T_877 = asSInt(_T_876) node _T_878 = eq(_T_877, asSInt(UInt<1>(0h0))) node _T_879 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_880 = cvt(_T_879) node _T_881 = and(_T_880, asSInt(UInt<17>(0h10000))) node _T_882 = asSInt(_T_881) node _T_883 = eq(_T_882, asSInt(UInt<1>(0h0))) node _T_884 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_885 = cvt(_T_884) node _T_886 = and(_T_885, asSInt(UInt<13>(0h1000))) node _T_887 = asSInt(_T_886) node _T_888 = eq(_T_887, asSInt(UInt<1>(0h0))) node _T_889 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_890 = cvt(_T_889) node _T_891 = and(_T_890, asSInt(UInt<27>(0h4000000))) node _T_892 = asSInt(_T_891) node _T_893 = eq(_T_892, asSInt(UInt<1>(0h0))) node _T_894 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_895 = cvt(_T_894) node _T_896 = and(_T_895, asSInt(UInt<13>(0h1000))) node _T_897 = asSInt(_T_896) node _T_898 = eq(_T_897, asSInt(UInt<1>(0h0))) node _T_899 = or(_T_868, _T_873) node _T_900 = or(_T_899, _T_878) node _T_901 = or(_T_900, _T_883) node _T_902 = or(_T_901, _T_888) node _T_903 = or(_T_902, _T_893) node _T_904 = or(_T_903, _T_898) node _T_905 = and(_T_863, _T_904) node _T_906 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_907 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_908 = and(_T_906, _T_907) node _T_909 = or(UInt<1>(0h0), _T_908) node _T_910 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_911 = cvt(_T_910) node _T_912 = and(_T_911, asSInt(UInt<17>(0h10000))) node _T_913 = asSInt(_T_912) node _T_914 = eq(_T_913, asSInt(UInt<1>(0h0))) node _T_915 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_916 = cvt(_T_915) node _T_917 = and(_T_916, asSInt(UInt<29>(0h10000000))) node _T_918 = asSInt(_T_917) node _T_919 = eq(_T_918, asSInt(UInt<1>(0h0))) node _T_920 = or(_T_914, _T_919) node _T_921 = and(_T_909, _T_920) node _T_922 = or(UInt<1>(0h0), _T_862) node _T_923 = or(_T_922, _T_905) node _T_924 = or(_T_923, _T_921) node _T_925 = and(_T_852, _T_924) node _T_926 = asUInt(reset) node _T_927 = eq(_T_926, UInt<1>(0h0)) when _T_927 : node _T_928 = eq(_T_925, UInt<1>(0h0)) when _T_928 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_925, UInt<1>(0h1), "") : assert_46 node _T_929 = asUInt(reset) node _T_930 = eq(_T_929, UInt<1>(0h0)) when _T_930 : node _T_931 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_931 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_932 = asUInt(reset) node _T_933 = eq(_T_932, UInt<1>(0h0)) when _T_933 : node _T_934 = eq(is_aligned, UInt<1>(0h0)) when _T_934 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_935 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_936 = asUInt(reset) node _T_937 = eq(_T_936, UInt<1>(0h0)) when _T_937 : node _T_938 = eq(_T_935, UInt<1>(0h0)) when _T_938 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_935, UInt<1>(0h1), "") : assert_49 node _T_939 = eq(io.in.a.bits.mask, mask) node _T_940 = asUInt(reset) node _T_941 = eq(_T_940, UInt<1>(0h0)) when _T_941 : node _T_942 = eq(_T_939, UInt<1>(0h0)) when _T_942 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_939, UInt<1>(0h1), "") : assert_50 node _T_943 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_944 = asUInt(reset) node _T_945 = eq(_T_944, UInt<1>(0h0)) when _T_945 : node _T_946 = eq(_T_943, UInt<1>(0h0)) when _T_946 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_943, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_947 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_948 = asUInt(reset) node _T_949 = eq(_T_948, UInt<1>(0h0)) when _T_949 : node _T_950 = eq(_T_947, UInt<1>(0h0)) when _T_950 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_947, UInt<1>(0h1), "") : assert_52 node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_1 node sink_ok = lt(io.in.d.bits.sink, UInt<7>(0h40)) node _T_951 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_951 : node _T_952 = asUInt(reset) node _T_953 = eq(_T_952, UInt<1>(0h0)) when _T_953 : node _T_954 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_954 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_955 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_956 = asUInt(reset) node _T_957 = eq(_T_956, UInt<1>(0h0)) when _T_957 : node _T_958 = eq(_T_955, UInt<1>(0h0)) when _T_958 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_955, UInt<1>(0h1), "") : assert_54 node _T_959 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_960 = asUInt(reset) node _T_961 = eq(_T_960, UInt<1>(0h0)) when _T_961 : node _T_962 = eq(_T_959, UInt<1>(0h0)) when _T_962 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_959, UInt<1>(0h1), "") : assert_55 node _T_963 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_964 = asUInt(reset) node _T_965 = eq(_T_964, UInt<1>(0h0)) when _T_965 : node _T_966 = eq(_T_963, UInt<1>(0h0)) when _T_966 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_963, UInt<1>(0h1), "") : assert_56 node _T_967 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_968 = asUInt(reset) node _T_969 = eq(_T_968, UInt<1>(0h0)) when _T_969 : node _T_970 = eq(_T_967, UInt<1>(0h0)) when _T_970 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_967, UInt<1>(0h1), "") : assert_57 node _T_971 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_971 : node _T_972 = asUInt(reset) node _T_973 = eq(_T_972, UInt<1>(0h0)) when _T_973 : node _T_974 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_974 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_975 = asUInt(reset) node _T_976 = eq(_T_975, UInt<1>(0h0)) when _T_976 : node _T_977 = eq(sink_ok, UInt<1>(0h0)) when _T_977 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_978 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_979 = asUInt(reset) node _T_980 = eq(_T_979, UInt<1>(0h0)) when _T_980 : node _T_981 = eq(_T_978, UInt<1>(0h0)) when _T_981 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_978, UInt<1>(0h1), "") : assert_60 node _T_982 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_983 = asUInt(reset) node _T_984 = eq(_T_983, UInt<1>(0h0)) when _T_984 : node _T_985 = eq(_T_982, UInt<1>(0h0)) when _T_985 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_982, UInt<1>(0h1), "") : assert_61 node _T_986 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_987 = asUInt(reset) node _T_988 = eq(_T_987, UInt<1>(0h0)) when _T_988 : node _T_989 = eq(_T_986, UInt<1>(0h0)) when _T_989 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_986, UInt<1>(0h1), "") : assert_62 node _T_990 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_991 = asUInt(reset) node _T_992 = eq(_T_991, UInt<1>(0h0)) when _T_992 : node _T_993 = eq(_T_990, UInt<1>(0h0)) when _T_993 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_990, UInt<1>(0h1), "") : assert_63 node _T_994 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_995 = or(UInt<1>(0h1), _T_994) node _T_996 = asUInt(reset) node _T_997 = eq(_T_996, UInt<1>(0h0)) when _T_997 : node _T_998 = eq(_T_995, UInt<1>(0h0)) when _T_998 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_995, UInt<1>(0h1), "") : assert_64 node _T_999 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_999 : node _T_1000 = asUInt(reset) node _T_1001 = eq(_T_1000, UInt<1>(0h0)) when _T_1001 : node _T_1002 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1002 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_1003 = asUInt(reset) node _T_1004 = eq(_T_1003, UInt<1>(0h0)) when _T_1004 : node _T_1005 = eq(sink_ok, UInt<1>(0h0)) when _T_1005 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1006 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1007 = asUInt(reset) node _T_1008 = eq(_T_1007, UInt<1>(0h0)) when _T_1008 : node _T_1009 = eq(_T_1006, UInt<1>(0h0)) when _T_1009 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1006, UInt<1>(0h1), "") : assert_67 node _T_1010 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1011 = asUInt(reset) node _T_1012 = eq(_T_1011, UInt<1>(0h0)) when _T_1012 : node _T_1013 = eq(_T_1010, UInt<1>(0h0)) when _T_1013 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1010, UInt<1>(0h1), "") : assert_68 node _T_1014 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1015 = asUInt(reset) node _T_1016 = eq(_T_1015, UInt<1>(0h0)) when _T_1016 : node _T_1017 = eq(_T_1014, UInt<1>(0h0)) when _T_1017 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1014, UInt<1>(0h1), "") : assert_69 node _T_1018 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1019 = or(_T_1018, io.in.d.bits.corrupt) node _T_1020 = asUInt(reset) node _T_1021 = eq(_T_1020, UInt<1>(0h0)) when _T_1021 : node _T_1022 = eq(_T_1019, UInt<1>(0h0)) when _T_1022 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1019, UInt<1>(0h1), "") : assert_70 node _T_1023 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1024 = or(UInt<1>(0h1), _T_1023) node _T_1025 = asUInt(reset) node _T_1026 = eq(_T_1025, UInt<1>(0h0)) when _T_1026 : node _T_1027 = eq(_T_1024, UInt<1>(0h0)) when _T_1027 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1024, UInt<1>(0h1), "") : assert_71 node _T_1028 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1028 : node _T_1029 = asUInt(reset) node _T_1030 = eq(_T_1029, UInt<1>(0h0)) when _T_1030 : node _T_1031 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1031 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_1032 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1033 = asUInt(reset) node _T_1034 = eq(_T_1033, UInt<1>(0h0)) when _T_1034 : node _T_1035 = eq(_T_1032, UInt<1>(0h0)) when _T_1035 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1032, UInt<1>(0h1), "") : assert_73 node _T_1036 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1037 = asUInt(reset) node _T_1038 = eq(_T_1037, UInt<1>(0h0)) when _T_1038 : node _T_1039 = eq(_T_1036, UInt<1>(0h0)) when _T_1039 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1036, UInt<1>(0h1), "") : assert_74 node _T_1040 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1041 = or(UInt<1>(0h1), _T_1040) node _T_1042 = asUInt(reset) node _T_1043 = eq(_T_1042, UInt<1>(0h0)) when _T_1043 : node _T_1044 = eq(_T_1041, UInt<1>(0h0)) when _T_1044 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1041, UInt<1>(0h1), "") : assert_75 node _T_1045 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1045 : node _T_1046 = asUInt(reset) node _T_1047 = eq(_T_1046, UInt<1>(0h0)) when _T_1047 : node _T_1048 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1048 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_1049 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_T_1049, UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1049, UInt<1>(0h1), "") : assert_77 node _T_1053 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1054 = or(_T_1053, io.in.d.bits.corrupt) node _T_1055 = asUInt(reset) node _T_1056 = eq(_T_1055, UInt<1>(0h0)) when _T_1056 : node _T_1057 = eq(_T_1054, UInt<1>(0h0)) when _T_1057 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1054, UInt<1>(0h1), "") : assert_78 node _T_1058 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1059 = or(UInt<1>(0h1), _T_1058) node _T_1060 = asUInt(reset) node _T_1061 = eq(_T_1060, UInt<1>(0h0)) when _T_1061 : node _T_1062 = eq(_T_1059, UInt<1>(0h0)) when _T_1062 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1059, UInt<1>(0h1), "") : assert_79 node _T_1063 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1063 : node _T_1064 = asUInt(reset) node _T_1065 = eq(_T_1064, UInt<1>(0h0)) when _T_1065 : node _T_1066 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1066 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_1067 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1068 = asUInt(reset) node _T_1069 = eq(_T_1068, UInt<1>(0h0)) when _T_1069 : node _T_1070 = eq(_T_1067, UInt<1>(0h0)) when _T_1070 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1067, UInt<1>(0h1), "") : assert_81 node _T_1071 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1072 = asUInt(reset) node _T_1073 = eq(_T_1072, UInt<1>(0h0)) when _T_1073 : node _T_1074 = eq(_T_1071, UInt<1>(0h0)) when _T_1074 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1071, UInt<1>(0h1), "") : assert_82 node _T_1075 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1076 = or(UInt<1>(0h1), _T_1075) node _T_1077 = asUInt(reset) node _T_1078 = eq(_T_1077, UInt<1>(0h0)) when _T_1078 : node _T_1079 = eq(_T_1076, UInt<1>(0h0)) when _T_1079 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1076, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1080 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_1081 = asUInt(reset) node _T_1082 = eq(_T_1081, UInt<1>(0h0)) when _T_1082 : node _T_1083 = eq(_T_1080, UInt<1>(0h0)) when _T_1083 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1080, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_1084 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_1085 = asUInt(reset) node _T_1086 = eq(_T_1085, UInt<1>(0h0)) when _T_1086 : node _T_1087 = eq(_T_1084, UInt<1>(0h0)) when _T_1087 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1084, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}} connect _WIRE_4.bits.sink, UInt<6>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1088 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1089 = asUInt(reset) node _T_1090 = eq(_T_1089, UInt<1>(0h0)) when _T_1090 : node _T_1091 = eq(_T_1088, UInt<1>(0h0)) when _T_1091 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1088, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1092 = eq(a_first, UInt<1>(0h0)) node _T_1093 = and(io.in.a.valid, _T_1092) when _T_1093 : node _T_1094 = eq(io.in.a.bits.opcode, opcode) node _T_1095 = asUInt(reset) node _T_1096 = eq(_T_1095, UInt<1>(0h0)) when _T_1096 : node _T_1097 = eq(_T_1094, UInt<1>(0h0)) when _T_1097 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1094, UInt<1>(0h1), "") : assert_87 node _T_1098 = eq(io.in.a.bits.param, param) node _T_1099 = asUInt(reset) node _T_1100 = eq(_T_1099, UInt<1>(0h0)) when _T_1100 : node _T_1101 = eq(_T_1098, UInt<1>(0h0)) when _T_1101 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1098, UInt<1>(0h1), "") : assert_88 node _T_1102 = eq(io.in.a.bits.size, size) node _T_1103 = asUInt(reset) node _T_1104 = eq(_T_1103, UInt<1>(0h0)) when _T_1104 : node _T_1105 = eq(_T_1102, UInt<1>(0h0)) when _T_1105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1102, UInt<1>(0h1), "") : assert_89 node _T_1106 = eq(io.in.a.bits.source, source) node _T_1107 = asUInt(reset) node _T_1108 = eq(_T_1107, UInt<1>(0h0)) when _T_1108 : node _T_1109 = eq(_T_1106, UInt<1>(0h0)) when _T_1109 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1106, UInt<1>(0h1), "") : assert_90 node _T_1110 = eq(io.in.a.bits.address, address) node _T_1111 = asUInt(reset) node _T_1112 = eq(_T_1111, UInt<1>(0h0)) when _T_1112 : node _T_1113 = eq(_T_1110, UInt<1>(0h0)) when _T_1113 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1110, UInt<1>(0h1), "") : assert_91 node _T_1114 = and(io.in.a.ready, io.in.a.valid) node _T_1115 = and(_T_1114, a_first) when _T_1115 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1116 = eq(d_first, UInt<1>(0h0)) node _T_1117 = and(io.in.d.valid, _T_1116) when _T_1117 : node _T_1118 = eq(io.in.d.bits.opcode, opcode_1) node _T_1119 = asUInt(reset) node _T_1120 = eq(_T_1119, UInt<1>(0h0)) when _T_1120 : node _T_1121 = eq(_T_1118, UInt<1>(0h0)) when _T_1121 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1118, UInt<1>(0h1), "") : assert_92 node _T_1122 = eq(io.in.d.bits.param, param_1) node _T_1123 = asUInt(reset) node _T_1124 = eq(_T_1123, UInt<1>(0h0)) when _T_1124 : node _T_1125 = eq(_T_1122, UInt<1>(0h0)) when _T_1125 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1122, UInt<1>(0h1), "") : assert_93 node _T_1126 = eq(io.in.d.bits.size, size_1) node _T_1127 = asUInt(reset) node _T_1128 = eq(_T_1127, UInt<1>(0h0)) when _T_1128 : node _T_1129 = eq(_T_1126, UInt<1>(0h0)) when _T_1129 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1126, UInt<1>(0h1), "") : assert_94 node _T_1130 = eq(io.in.d.bits.source, source_1) node _T_1131 = asUInt(reset) node _T_1132 = eq(_T_1131, UInt<1>(0h0)) when _T_1132 : node _T_1133 = eq(_T_1130, UInt<1>(0h0)) when _T_1133 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1130, UInt<1>(0h1), "") : assert_95 node _T_1134 = eq(io.in.d.bits.sink, sink) node _T_1135 = asUInt(reset) node _T_1136 = eq(_T_1135, UInt<1>(0h0)) when _T_1136 : node _T_1137 = eq(_T_1134, UInt<1>(0h0)) when _T_1137 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1134, UInt<1>(0h1), "") : assert_96 node _T_1138 = eq(io.in.d.bits.denied, denied) node _T_1139 = asUInt(reset) node _T_1140 = eq(_T_1139, UInt<1>(0h0)) when _T_1140 : node _T_1141 = eq(_T_1138, UInt<1>(0h0)) when _T_1141 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1138, UInt<1>(0h1), "") : assert_97 node _T_1142 = and(io.in.d.ready, io.in.d.valid) node _T_1143 = and(_T_1142, d_first) when _T_1143 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1> connect a_set, UInt<1>(0h0) wire a_set_wo_ready : UInt<1> connect a_set_wo_ready, UInt<1>(0h0) wire a_opcodes_set : UInt<4> connect a_opcodes_set, UInt<4>(0h0) wire a_sizes_set : UInt<8> connect a_sizes_set, UInt<8>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1144 = and(io.in.a.valid, a_first_1) node _T_1145 = and(_T_1144, UInt<1>(0h1)) when _T_1145 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1146 = and(io.in.a.ready, io.in.a.valid) node _T_1147 = and(_T_1146, a_first_1) node _T_1148 = and(_T_1147, UInt<1>(0h1)) when _T_1148 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1149 = dshr(inflight, io.in.a.bits.source) node _T_1150 = bits(_T_1149, 0, 0) node _T_1151 = eq(_T_1150, UInt<1>(0h0)) node _T_1152 = asUInt(reset) node _T_1153 = eq(_T_1152, UInt<1>(0h0)) when _T_1153 : node _T_1154 = eq(_T_1151, UInt<1>(0h0)) when _T_1154 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1151, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1> connect d_clr, UInt<1>(0h0) wire d_clr_wo_ready : UInt<1> connect d_clr_wo_ready, UInt<1>(0h0) wire d_opcodes_clr : UInt<4> connect d_opcodes_clr, UInt<4>(0h0) wire d_sizes_clr : UInt<8> connect d_sizes_clr, UInt<8>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1155 = and(io.in.d.valid, d_first_1) node _T_1156 = and(_T_1155, UInt<1>(0h1)) node _T_1157 = eq(d_release_ack, UInt<1>(0h0)) node _T_1158 = and(_T_1156, _T_1157) when _T_1158 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1159 = and(io.in.d.ready, io.in.d.valid) node _T_1160 = and(_T_1159, d_first_1) node _T_1161 = and(_T_1160, UInt<1>(0h1)) node _T_1162 = eq(d_release_ack, UInt<1>(0h0)) node _T_1163 = and(_T_1161, _T_1162) when _T_1163 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1164 = and(io.in.d.valid, d_first_1) node _T_1165 = and(_T_1164, UInt<1>(0h1)) node _T_1166 = eq(d_release_ack, UInt<1>(0h0)) node _T_1167 = and(_T_1165, _T_1166) when _T_1167 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1168 = dshr(inflight, io.in.d.bits.source) node _T_1169 = bits(_T_1168, 0, 0) node _T_1170 = or(_T_1169, same_cycle_resp) node _T_1171 = asUInt(reset) node _T_1172 = eq(_T_1171, UInt<1>(0h0)) when _T_1172 : node _T_1173 = eq(_T_1170, UInt<1>(0h0)) when _T_1173 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1170, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1174 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1175 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1176 = or(_T_1174, _T_1175) node _T_1177 = asUInt(reset) node _T_1178 = eq(_T_1177, UInt<1>(0h0)) when _T_1178 : node _T_1179 = eq(_T_1176, UInt<1>(0h0)) when _T_1179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1176, UInt<1>(0h1), "") : assert_100 node _T_1180 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1181 = asUInt(reset) node _T_1182 = eq(_T_1181, UInt<1>(0h0)) when _T_1182 : node _T_1183 = eq(_T_1180, UInt<1>(0h0)) when _T_1183 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1180, UInt<1>(0h1), "") : assert_101 else : node _T_1184 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1185 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1186 = or(_T_1184, _T_1185) node _T_1187 = asUInt(reset) node _T_1188 = eq(_T_1187, UInt<1>(0h0)) when _T_1188 : node _T_1189 = eq(_T_1186, UInt<1>(0h0)) when _T_1189 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1186, UInt<1>(0h1), "") : assert_102 node _T_1190 = eq(io.in.d.bits.size, a_size_lookup) node _T_1191 = asUInt(reset) node _T_1192 = eq(_T_1191, UInt<1>(0h0)) when _T_1192 : node _T_1193 = eq(_T_1190, UInt<1>(0h0)) when _T_1193 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1190, UInt<1>(0h1), "") : assert_103 node _T_1194 = and(io.in.d.valid, d_first_1) node _T_1195 = and(_T_1194, a_first_1) node _T_1196 = and(_T_1195, io.in.a.valid) node _T_1197 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1198 = and(_T_1196, _T_1197) node _T_1199 = eq(d_release_ack, UInt<1>(0h0)) node _T_1200 = and(_T_1198, _T_1199) when _T_1200 : node _T_1201 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1202 = or(_T_1201, io.in.a.ready) node _T_1203 = asUInt(reset) node _T_1204 = eq(_T_1203, UInt<1>(0h0)) when _T_1204 : node _T_1205 = eq(_T_1202, UInt<1>(0h0)) when _T_1205 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1202, UInt<1>(0h1), "") : assert_104 node _T_1206 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1207 = orr(a_set_wo_ready) node _T_1208 = eq(_T_1207, UInt<1>(0h0)) node _T_1209 = or(_T_1206, _T_1208) node _T_1210 = asUInt(reset) node _T_1211 = eq(_T_1210, UInt<1>(0h0)) when _T_1211 : node _T_1212 = eq(_T_1209, UInt<1>(0h0)) when _T_1212 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1209, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_294 node _T_1213 = orr(inflight) node _T_1214 = eq(_T_1213, UInt<1>(0h0)) node _T_1215 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1216 = or(_T_1214, _T_1215) node _T_1217 = lt(watchdog, plusarg_reader.out) node _T_1218 = or(_T_1216, _T_1217) node _T_1219 = asUInt(reset) node _T_1220 = eq(_T_1219, UInt<1>(0h0)) when _T_1220 : node _T_1221 = eq(_T_1218, UInt<1>(0h0)) when _T_1221 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1218, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1222 = and(io.in.a.ready, io.in.a.valid) node _T_1223 = and(io.in.d.ready, io.in.d.valid) node _T_1224 = or(_T_1222, _T_1223) when _T_1224 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes_1 : UInt<8>, clock, reset, UInt<8>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<1>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<1>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1> connect c_set, UInt<1>(0h0) wire c_set_wo_ready : UInt<1> connect c_set_wo_ready, UInt<1>(0h0) wire c_opcodes_set : UInt<4> connect c_opcodes_set, UInt<4>(0h0) wire c_sizes_set : UInt<8> connect c_sizes_set, UInt<8>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1225 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1226 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1227 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1228 = and(_T_1226, _T_1227) node _T_1229 = and(_T_1225, _T_1228) when _T_1229 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1230 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1231 = and(_T_1230, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1232 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1233 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1234 = and(_T_1232, _T_1233) node _T_1235 = and(_T_1231, _T_1234) when _T_1235 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<1>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<1>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1236 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1237 = bits(_T_1236, 0, 0) node _T_1238 = eq(_T_1237, UInt<1>(0h0)) node _T_1239 = asUInt(reset) node _T_1240 = eq(_T_1239, UInt<1>(0h0)) when _T_1240 : node _T_1241 = eq(_T_1238, UInt<1>(0h0)) when _T_1241 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1238, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1> connect d_clr_1, UInt<1>(0h0) wire d_clr_wo_ready_1 : UInt<1> connect d_clr_wo_ready_1, UInt<1>(0h0) wire d_opcodes_clr_1 : UInt<4> connect d_opcodes_clr_1, UInt<4>(0h0) wire d_sizes_clr_1 : UInt<8> connect d_sizes_clr_1, UInt<8>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1242 = and(io.in.d.valid, d_first_2) node _T_1243 = and(_T_1242, UInt<1>(0h1)) node _T_1244 = and(_T_1243, d_release_ack_1) when _T_1244 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1245 = and(io.in.d.ready, io.in.d.valid) node _T_1246 = and(_T_1245, d_first_2) node _T_1247 = and(_T_1246, UInt<1>(0h1)) node _T_1248 = and(_T_1247, d_release_ack_1) when _T_1248 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1249 = and(io.in.d.valid, d_first_2) node _T_1250 = and(_T_1249, UInt<1>(0h1)) node _T_1251 = and(_T_1250, d_release_ack_1) when _T_1251 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1252 = dshr(inflight_1, io.in.d.bits.source) node _T_1253 = bits(_T_1252, 0, 0) node _T_1254 = or(_T_1253, same_cycle_resp_1) node _T_1255 = asUInt(reset) node _T_1256 = eq(_T_1255, UInt<1>(0h0)) when _T_1256 : node _T_1257 = eq(_T_1254, UInt<1>(0h0)) when _T_1257 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1254, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<1>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1258 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1259 = asUInt(reset) node _T_1260 = eq(_T_1259, UInt<1>(0h0)) when _T_1260 : node _T_1261 = eq(_T_1258, UInt<1>(0h0)) when _T_1261 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1258, UInt<1>(0h1), "") : assert_109 else : node _T_1262 = eq(io.in.d.bits.size, c_size_lookup) node _T_1263 = asUInt(reset) node _T_1264 = eq(_T_1263, UInt<1>(0h0)) when _T_1264 : node _T_1265 = eq(_T_1262, UInt<1>(0h0)) when _T_1265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1262, UInt<1>(0h1), "") : assert_110 node _T_1266 = and(io.in.d.valid, d_first_2) node _T_1267 = and(_T_1266, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1268 = and(_T_1267, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1269 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1270 = and(_T_1268, _T_1269) node _T_1271 = and(_T_1270, d_release_ack_1) node _T_1272 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1273 = and(_T_1271, _T_1272) when _T_1273 : node _T_1274 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<1>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1275 = or(_T_1274, _WIRE_23.ready) node _T_1276 = asUInt(reset) node _T_1277 = eq(_T_1276, UInt<1>(0h0)) when _T_1277 : node _T_1278 = eq(_T_1275, UInt<1>(0h0)) when _T_1278 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1275, UInt<1>(0h1), "") : assert_111 node _T_1279 = orr(c_set_wo_ready) when _T_1279 : node _T_1280 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1281 = asUInt(reset) node _T_1282 = eq(_T_1281, UInt<1>(0h0)) when _T_1282 : node _T_1283 = eq(_T_1280, UInt<1>(0h0)) when _T_1283 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1280, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_295 node _T_1284 = orr(inflight_1) node _T_1285 = eq(_T_1284, UInt<1>(0h0)) node _T_1286 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1287 = or(_T_1285, _T_1286) node _T_1288 = lt(watchdog_1, plusarg_reader_1.out) node _T_1289 = or(_T_1287, _T_1288) node _T_1290 = asUInt(reset) node _T_1291 = eq(_T_1290, UInt<1>(0h0)) when _T_1291 : node _T_1292 = eq(_T_1289, UInt<1>(0h0)) when _T_1292 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1289, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1293 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1294 = and(io.in.d.ready, io.in.d.valid) node _T_1295 = or(_T_1293, _T_1294) when _T_1295 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_122( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_source, // @[Monitor.scala:20:14] input [5:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [26:0] _GEN = {23'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [8:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [31:0] address; // @[Monitor.scala:391:22] reg [8:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg source_1; // @[Monitor.scala:541:22] reg [5:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [7:0] inflight_sizes; // @[Monitor.scala:618:33] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire a_set = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:36:7, :673:46] wire _GEN_0 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:36:7, :673:46, :674:74] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [1:0] inflight_1; // @[Monitor.scala:726:35] reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module InputUnit_34 : input clock : Clock input reset : Reset output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<2>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[3], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<2>, vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[3], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}}}, flip vcalloc_resp : { vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[3], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}}, flip out_credit_available : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[3], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[3], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}, out_virt_channel : UInt<2>}}[1], debug : { va_stall : UInt<2>, sa_stall : UInt<2>}, flip block : UInt<1>, flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>}} inst input_buffer of InputBuffer_34 connect input_buffer.clock, clock connect input_buffer.reset, reset connect input_buffer.io.enq[0].bits.virt_channel_id, io.in.flit[0].bits.virt_channel_id connect input_buffer.io.enq[0].bits.flow.egress_node_id, io.in.flit[0].bits.flow.egress_node_id connect input_buffer.io.enq[0].bits.flow.egress_node, io.in.flit[0].bits.flow.egress_node connect input_buffer.io.enq[0].bits.flow.ingress_node_id, io.in.flit[0].bits.flow.ingress_node_id connect input_buffer.io.enq[0].bits.flow.ingress_node, io.in.flit[0].bits.flow.ingress_node connect input_buffer.io.enq[0].bits.flow.vnet_id, io.in.flit[0].bits.flow.vnet_id connect input_buffer.io.enq[0].bits.payload, io.in.flit[0].bits.payload connect input_buffer.io.enq[0].bits.tail, io.in.flit[0].bits.tail connect input_buffer.io.enq[0].bits.head, io.in.flit[0].bits.head connect input_buffer.io.enq[0].valid, io.in.flit[0].valid connect input_buffer.io.deq[0].ready, UInt<1>(0h0) connect input_buffer.io.deq[1].ready, UInt<1>(0h0) connect input_buffer.io.deq[2].ready, UInt<1>(0h0) inst route_arbiter of Arbiter3_RouteComputerReq_34 connect route_arbiter.clock, clock connect route_arbiter.reset, reset connect io.router_req.bits, route_arbiter.io.out.bits connect io.router_req.valid, route_arbiter.io.out.valid connect route_arbiter.io.out.ready, io.router_req.ready reg states : { g : UInt<3>, vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[3], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, fifo_deps : UInt<3>}[3], clock node _T = and(io.in.flit[0].valid, io.in.flit[0].bits.head) when _T : node _T_1 = lt(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h3)) node _T_2 = asUInt(reset) node _T_3 = eq(_T_2, UInt<1>(0h0)) when _T_3 : node _T_4 = eq(_T_1, UInt<1>(0h0)) when _T_4 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:207 assert(id < nVirtualChannels.U)\n") : printf assert(clock, _T_1, UInt<1>(0h1), "") : assert node _T_5 = eq(states[io.in.flit[0].bits.virt_channel_id].g, UInt<3>(0h0)) node _T_6 = asUInt(reset) node _T_7 = eq(_T_6, UInt<1>(0h0)) when _T_7 : node _T_8 = eq(_T_5, UInt<1>(0h0)) when _T_8 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:208 assert(states(id).g === g_i)\n") : printf_1 assert(clock, _T_5, UInt<1>(0h1), "") : assert_1 node at_dest = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _states_g_T = mux(at_dest, UInt<3>(0h2), UInt<3>(0h1)) connect states[io.in.flit[0].bits.virt_channel_id].g, _states_g_T connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`4`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`5`[0], UInt<1>(0h0) node _T_9 = eq(UInt<1>(0h0), io.in.flit[0].bits.flow.egress_node_id) when _T_9 : connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`4`[0], UInt<1>(0h1) node _T_10 = eq(UInt<1>(0h1), io.in.flit[0].bits.flow.egress_node_id) when _T_10 : connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`5`[0], UInt<1>(0h1) connect states[io.in.flit[0].bits.virt_channel_id].flow, io.in.flit[0].bits.flow connect route_arbiter.io.in[0].valid, UInt<1>(0h0) invalidate route_arbiter.io.in[0].bits.flow.egress_node_id invalidate route_arbiter.io.in[0].bits.flow.egress_node invalidate route_arbiter.io.in[0].bits.flow.ingress_node_id invalidate route_arbiter.io.in[0].bits.flow.ingress_node invalidate route_arbiter.io.in[0].bits.flow.vnet_id invalidate route_arbiter.io.in[0].bits.src_virt_id node _route_arbiter_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h1)) connect route_arbiter.io.in[1].valid, _route_arbiter_io_in_1_valid_T connect route_arbiter.io.in[1].bits.flow.egress_node_id, states[1].flow.egress_node_id connect route_arbiter.io.in[1].bits.flow.egress_node, states[1].flow.egress_node connect route_arbiter.io.in[1].bits.flow.ingress_node_id, states[1].flow.ingress_node_id connect route_arbiter.io.in[1].bits.flow.ingress_node, states[1].flow.ingress_node connect route_arbiter.io.in[1].bits.flow.vnet_id, states[1].flow.vnet_id connect route_arbiter.io.in[1].bits.src_virt_id, UInt<1>(0h1) node _T_11 = and(route_arbiter.io.in[1].ready, route_arbiter.io.in[1].valid) when _T_11 : connect states[1].g, UInt<3>(0h2) node _route_arbiter_io_in_2_valid_T = eq(states[2].g, UInt<3>(0h1)) connect route_arbiter.io.in[2].valid, _route_arbiter_io_in_2_valid_T connect route_arbiter.io.in[2].bits.flow.egress_node_id, states[2].flow.egress_node_id connect route_arbiter.io.in[2].bits.flow.egress_node, states[2].flow.egress_node connect route_arbiter.io.in[2].bits.flow.ingress_node_id, states[2].flow.ingress_node_id connect route_arbiter.io.in[2].bits.flow.ingress_node, states[2].flow.ingress_node connect route_arbiter.io.in[2].bits.flow.vnet_id, states[2].flow.vnet_id connect route_arbiter.io.in[2].bits.src_virt_id, UInt<2>(0h2) node _T_12 = and(route_arbiter.io.in[2].ready, route_arbiter.io.in[2].valid) when _T_12 : connect states[2].g, UInt<3>(0h2) node _T_13 = and(io.router_req.ready, io.router_req.valid) when _T_13 : node _T_14 = eq(states[io.router_req.bits.src_virt_id].g, UInt<3>(0h1)) node _T_15 = asUInt(reset) node _T_16 = eq(_T_15, UInt<1>(0h0)) when _T_16 : node _T_17 = eq(_T_14, UInt<1>(0h0)) when _T_17 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:241 assert(states(id).g === g_r)\n") : printf_2 assert(clock, _T_14, UInt<1>(0h1), "") : assert_2 connect states[io.router_req.bits.src_virt_id].g, UInt<3>(0h2) node _T_18 = eq(UInt<1>(0h0), io.router_req.bits.src_virt_id) when _T_18 : connect states[0].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[0].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[0].vc_sel.`3`, io.router_resp.vc_sel.`3` connect states[0].vc_sel.`4`, io.router_resp.vc_sel.`4` connect states[0].vc_sel.`5`, io.router_resp.vc_sel.`5` node _T_19 = eq(UInt<1>(0h1), io.router_req.bits.src_virt_id) when _T_19 : connect states[1].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[1].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[1].vc_sel.`3`, io.router_resp.vc_sel.`3` connect states[1].vc_sel.`4`, io.router_resp.vc_sel.`4` connect states[1].vc_sel.`5`, io.router_resp.vc_sel.`5` node _T_20 = eq(UInt<2>(0h2), io.router_req.bits.src_virt_id) when _T_20 : connect states[2].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[2].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[2].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[2].vc_sel.`3`, io.router_resp.vc_sel.`3` connect states[2].vc_sel.`4`, io.router_resp.vc_sel.`4` connect states[2].vc_sel.`5`, io.router_resp.vc_sel.`5` regreset mask : UInt<3>, clock, reset, UInt<3>(0h0) wire vcalloc_reqs : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<2>, vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[3], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}}[3] wire vcalloc_vals : UInt<1>[3] node vcalloc_filter_hi = cat(vcalloc_vals[2], vcalloc_vals[1]) node _vcalloc_filter_T = cat(vcalloc_filter_hi, vcalloc_vals[0]) node vcalloc_filter_hi_1 = cat(vcalloc_vals[2], vcalloc_vals[1]) node _vcalloc_filter_T_1 = cat(vcalloc_filter_hi_1, vcalloc_vals[0]) node _vcalloc_filter_T_2 = not(mask) node _vcalloc_filter_T_3 = and(_vcalloc_filter_T_1, _vcalloc_filter_T_2) node _vcalloc_filter_T_4 = cat(_vcalloc_filter_T, _vcalloc_filter_T_3) node _vcalloc_filter_T_5 = bits(_vcalloc_filter_T_4, 0, 0) node _vcalloc_filter_T_6 = bits(_vcalloc_filter_T_4, 1, 1) node _vcalloc_filter_T_7 = bits(_vcalloc_filter_T_4, 2, 2) node _vcalloc_filter_T_8 = bits(_vcalloc_filter_T_4, 3, 3) node _vcalloc_filter_T_9 = bits(_vcalloc_filter_T_4, 4, 4) node _vcalloc_filter_T_10 = bits(_vcalloc_filter_T_4, 5, 5) node _vcalloc_filter_T_11 = mux(_vcalloc_filter_T_10, UInt<6>(0h20), UInt<6>(0h0)) node _vcalloc_filter_T_12 = mux(_vcalloc_filter_T_9, UInt<6>(0h10), _vcalloc_filter_T_11) node _vcalloc_filter_T_13 = mux(_vcalloc_filter_T_8, UInt<6>(0h8), _vcalloc_filter_T_12) node _vcalloc_filter_T_14 = mux(_vcalloc_filter_T_7, UInt<6>(0h4), _vcalloc_filter_T_13) node _vcalloc_filter_T_15 = mux(_vcalloc_filter_T_6, UInt<6>(0h2), _vcalloc_filter_T_14) node vcalloc_filter = mux(_vcalloc_filter_T_5, UInt<6>(0h1), _vcalloc_filter_T_15) node _vcalloc_sel_T = bits(vcalloc_filter, 2, 0) node _vcalloc_sel_T_1 = shr(vcalloc_filter, 3) node vcalloc_sel = or(_vcalloc_sel_T, _vcalloc_sel_T_1) node _T_21 = and(io.router_req.ready, io.router_req.valid) when _T_21 : node _mask_T = dshl(UInt<1>(0h1), io.router_req.bits.src_virt_id) node _mask_T_1 = sub(_mask_T, UInt<1>(0h1)) node _mask_T_2 = tail(_mask_T_1, 1) connect mask, _mask_T_2 else : node _T_22 = or(vcalloc_vals[0], vcalloc_vals[1]) node _T_23 = or(_T_22, vcalloc_vals[2]) when _T_23 : node _mask_T_3 = not(UInt<1>(0h0)) node _mask_T_4 = not(UInt<2>(0h0)) node _mask_T_5 = not(UInt<3>(0h0)) node _mask_T_6 = bits(vcalloc_sel, 0, 0) node _mask_T_7 = bits(vcalloc_sel, 1, 1) node _mask_T_8 = bits(vcalloc_sel, 2, 2) node _mask_T_9 = mux(_mask_T_6, _mask_T_3, UInt<1>(0h0)) node _mask_T_10 = mux(_mask_T_7, _mask_T_4, UInt<1>(0h0)) node _mask_T_11 = mux(_mask_T_8, _mask_T_5, UInt<1>(0h0)) node _mask_T_12 = or(_mask_T_9, _mask_T_10) node _mask_T_13 = or(_mask_T_12, _mask_T_11) wire _mask_WIRE : UInt<3> connect _mask_WIRE, _mask_T_13 connect mask, _mask_WIRE node _io_vcalloc_req_valid_T = or(vcalloc_vals[0], vcalloc_vals[1]) node _io_vcalloc_req_valid_T_1 = or(_io_vcalloc_req_valid_T, vcalloc_vals[2]) connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_1 node _io_vcalloc_req_bits_T = bits(vcalloc_sel, 0, 0) node _io_vcalloc_req_bits_T_1 = bits(vcalloc_sel, 1, 1) node _io_vcalloc_req_bits_T_2 = bits(vcalloc_sel, 2, 2) wire _io_vcalloc_req_bits_WIRE : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<2>, vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[3], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}} wire _io_vcalloc_req_bits_WIRE_1 : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[3], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]} wire _io_vcalloc_req_bits_WIRE_2 : UInt<1>[3] node _io_vcalloc_req_bits_T_3 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_4 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_5 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_6 = or(_io_vcalloc_req_bits_T_3, _io_vcalloc_req_bits_T_4) node _io_vcalloc_req_bits_T_7 = or(_io_vcalloc_req_bits_T_6, _io_vcalloc_req_bits_T_5) wire _io_vcalloc_req_bits_WIRE_3 : UInt<1> connect _io_vcalloc_req_bits_WIRE_3, _io_vcalloc_req_bits_T_7 connect _io_vcalloc_req_bits_WIRE_2[0], _io_vcalloc_req_bits_WIRE_3 node _io_vcalloc_req_bits_T_8 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_9 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_10 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_11 = or(_io_vcalloc_req_bits_T_8, _io_vcalloc_req_bits_T_9) node _io_vcalloc_req_bits_T_12 = or(_io_vcalloc_req_bits_T_11, _io_vcalloc_req_bits_T_10) wire _io_vcalloc_req_bits_WIRE_4 : UInt<1> connect _io_vcalloc_req_bits_WIRE_4, _io_vcalloc_req_bits_T_12 connect _io_vcalloc_req_bits_WIRE_2[1], _io_vcalloc_req_bits_WIRE_4 node _io_vcalloc_req_bits_T_13 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_14 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_15 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_16 = or(_io_vcalloc_req_bits_T_13, _io_vcalloc_req_bits_T_14) node _io_vcalloc_req_bits_T_17 = or(_io_vcalloc_req_bits_T_16, _io_vcalloc_req_bits_T_15) wire _io_vcalloc_req_bits_WIRE_5 : UInt<1> connect _io_vcalloc_req_bits_WIRE_5, _io_vcalloc_req_bits_T_17 connect _io_vcalloc_req_bits_WIRE_2[2], _io_vcalloc_req_bits_WIRE_5 connect _io_vcalloc_req_bits_WIRE_1.`0`, _io_vcalloc_req_bits_WIRE_2 wire _io_vcalloc_req_bits_WIRE_6 : UInt<1>[3] node _io_vcalloc_req_bits_T_18 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_19 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_20 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_21 = or(_io_vcalloc_req_bits_T_18, _io_vcalloc_req_bits_T_19) node _io_vcalloc_req_bits_T_22 = or(_io_vcalloc_req_bits_T_21, _io_vcalloc_req_bits_T_20) wire _io_vcalloc_req_bits_WIRE_7 : UInt<1> connect _io_vcalloc_req_bits_WIRE_7, _io_vcalloc_req_bits_T_22 connect _io_vcalloc_req_bits_WIRE_6[0], _io_vcalloc_req_bits_WIRE_7 node _io_vcalloc_req_bits_T_23 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_24 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_25 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_26 = or(_io_vcalloc_req_bits_T_23, _io_vcalloc_req_bits_T_24) node _io_vcalloc_req_bits_T_27 = or(_io_vcalloc_req_bits_T_26, _io_vcalloc_req_bits_T_25) wire _io_vcalloc_req_bits_WIRE_8 : UInt<1> connect _io_vcalloc_req_bits_WIRE_8, _io_vcalloc_req_bits_T_27 connect _io_vcalloc_req_bits_WIRE_6[1], _io_vcalloc_req_bits_WIRE_8 node _io_vcalloc_req_bits_T_28 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_29 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_30 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_31 = or(_io_vcalloc_req_bits_T_28, _io_vcalloc_req_bits_T_29) node _io_vcalloc_req_bits_T_32 = or(_io_vcalloc_req_bits_T_31, _io_vcalloc_req_bits_T_30) wire _io_vcalloc_req_bits_WIRE_9 : UInt<1> connect _io_vcalloc_req_bits_WIRE_9, _io_vcalloc_req_bits_T_32 connect _io_vcalloc_req_bits_WIRE_6[2], _io_vcalloc_req_bits_WIRE_9 connect _io_vcalloc_req_bits_WIRE_1.`1`, _io_vcalloc_req_bits_WIRE_6 wire _io_vcalloc_req_bits_WIRE_10 : UInt<1>[3] node _io_vcalloc_req_bits_T_33 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_34 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_35 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_36 = or(_io_vcalloc_req_bits_T_33, _io_vcalloc_req_bits_T_34) node _io_vcalloc_req_bits_T_37 = or(_io_vcalloc_req_bits_T_36, _io_vcalloc_req_bits_T_35) wire _io_vcalloc_req_bits_WIRE_11 : UInt<1> connect _io_vcalloc_req_bits_WIRE_11, _io_vcalloc_req_bits_T_37 connect _io_vcalloc_req_bits_WIRE_10[0], _io_vcalloc_req_bits_WIRE_11 node _io_vcalloc_req_bits_T_38 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_39 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_40 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_41 = or(_io_vcalloc_req_bits_T_38, _io_vcalloc_req_bits_T_39) node _io_vcalloc_req_bits_T_42 = or(_io_vcalloc_req_bits_T_41, _io_vcalloc_req_bits_T_40) wire _io_vcalloc_req_bits_WIRE_12 : UInt<1> connect _io_vcalloc_req_bits_WIRE_12, _io_vcalloc_req_bits_T_42 connect _io_vcalloc_req_bits_WIRE_10[1], _io_vcalloc_req_bits_WIRE_12 node _io_vcalloc_req_bits_T_43 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_44 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_45 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_46 = or(_io_vcalloc_req_bits_T_43, _io_vcalloc_req_bits_T_44) node _io_vcalloc_req_bits_T_47 = or(_io_vcalloc_req_bits_T_46, _io_vcalloc_req_bits_T_45) wire _io_vcalloc_req_bits_WIRE_13 : UInt<1> connect _io_vcalloc_req_bits_WIRE_13, _io_vcalloc_req_bits_T_47 connect _io_vcalloc_req_bits_WIRE_10[2], _io_vcalloc_req_bits_WIRE_13 connect _io_vcalloc_req_bits_WIRE_1.`2`, _io_vcalloc_req_bits_WIRE_10 wire _io_vcalloc_req_bits_WIRE_14 : UInt<1>[3] node _io_vcalloc_req_bits_T_48 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_49 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_50 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_51 = or(_io_vcalloc_req_bits_T_48, _io_vcalloc_req_bits_T_49) node _io_vcalloc_req_bits_T_52 = or(_io_vcalloc_req_bits_T_51, _io_vcalloc_req_bits_T_50) wire _io_vcalloc_req_bits_WIRE_15 : UInt<1> connect _io_vcalloc_req_bits_WIRE_15, _io_vcalloc_req_bits_T_52 connect _io_vcalloc_req_bits_WIRE_14[0], _io_vcalloc_req_bits_WIRE_15 node _io_vcalloc_req_bits_T_53 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_54 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_55 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_56 = or(_io_vcalloc_req_bits_T_53, _io_vcalloc_req_bits_T_54) node _io_vcalloc_req_bits_T_57 = or(_io_vcalloc_req_bits_T_56, _io_vcalloc_req_bits_T_55) wire _io_vcalloc_req_bits_WIRE_16 : UInt<1> connect _io_vcalloc_req_bits_WIRE_16, _io_vcalloc_req_bits_T_57 connect _io_vcalloc_req_bits_WIRE_14[1], _io_vcalloc_req_bits_WIRE_16 node _io_vcalloc_req_bits_T_58 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_59 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_60 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_61 = or(_io_vcalloc_req_bits_T_58, _io_vcalloc_req_bits_T_59) node _io_vcalloc_req_bits_T_62 = or(_io_vcalloc_req_bits_T_61, _io_vcalloc_req_bits_T_60) wire _io_vcalloc_req_bits_WIRE_17 : UInt<1> connect _io_vcalloc_req_bits_WIRE_17, _io_vcalloc_req_bits_T_62 connect _io_vcalloc_req_bits_WIRE_14[2], _io_vcalloc_req_bits_WIRE_17 connect _io_vcalloc_req_bits_WIRE_1.`3`, _io_vcalloc_req_bits_WIRE_14 wire _io_vcalloc_req_bits_WIRE_18 : UInt<1>[1] node _io_vcalloc_req_bits_T_63 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`4`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_64 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`4`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_65 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`4`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_66 = or(_io_vcalloc_req_bits_T_63, _io_vcalloc_req_bits_T_64) node _io_vcalloc_req_bits_T_67 = or(_io_vcalloc_req_bits_T_66, _io_vcalloc_req_bits_T_65) wire _io_vcalloc_req_bits_WIRE_19 : UInt<1> connect _io_vcalloc_req_bits_WIRE_19, _io_vcalloc_req_bits_T_67 connect _io_vcalloc_req_bits_WIRE_18[0], _io_vcalloc_req_bits_WIRE_19 connect _io_vcalloc_req_bits_WIRE_1.`4`, _io_vcalloc_req_bits_WIRE_18 wire _io_vcalloc_req_bits_WIRE_20 : UInt<1>[1] node _io_vcalloc_req_bits_T_68 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`5`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_69 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`5`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_70 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`5`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_71 = or(_io_vcalloc_req_bits_T_68, _io_vcalloc_req_bits_T_69) node _io_vcalloc_req_bits_T_72 = or(_io_vcalloc_req_bits_T_71, _io_vcalloc_req_bits_T_70) wire _io_vcalloc_req_bits_WIRE_21 : UInt<1> connect _io_vcalloc_req_bits_WIRE_21, _io_vcalloc_req_bits_T_72 connect _io_vcalloc_req_bits_WIRE_20[0], _io_vcalloc_req_bits_WIRE_21 connect _io_vcalloc_req_bits_WIRE_1.`5`, _io_vcalloc_req_bits_WIRE_20 connect _io_vcalloc_req_bits_WIRE.vc_sel, _io_vcalloc_req_bits_WIRE_1 node _io_vcalloc_req_bits_T_73 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_74 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_75 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_76 = or(_io_vcalloc_req_bits_T_73, _io_vcalloc_req_bits_T_74) node _io_vcalloc_req_bits_T_77 = or(_io_vcalloc_req_bits_T_76, _io_vcalloc_req_bits_T_75) wire _io_vcalloc_req_bits_WIRE_22 : UInt<2> connect _io_vcalloc_req_bits_WIRE_22, _io_vcalloc_req_bits_T_77 connect _io_vcalloc_req_bits_WIRE.in_vc, _io_vcalloc_req_bits_WIRE_22 wire _io_vcalloc_req_bits_WIRE_23 : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>} node _io_vcalloc_req_bits_T_78 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_79 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_80 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_81 = or(_io_vcalloc_req_bits_T_78, _io_vcalloc_req_bits_T_79) node _io_vcalloc_req_bits_T_82 = or(_io_vcalloc_req_bits_T_81, _io_vcalloc_req_bits_T_80) wire _io_vcalloc_req_bits_WIRE_24 : UInt<2> connect _io_vcalloc_req_bits_WIRE_24, _io_vcalloc_req_bits_T_82 connect _io_vcalloc_req_bits_WIRE_23.egress_node_id, _io_vcalloc_req_bits_WIRE_24 node _io_vcalloc_req_bits_T_83 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_84 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_85 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_86 = or(_io_vcalloc_req_bits_T_83, _io_vcalloc_req_bits_T_84) node _io_vcalloc_req_bits_T_87 = or(_io_vcalloc_req_bits_T_86, _io_vcalloc_req_bits_T_85) wire _io_vcalloc_req_bits_WIRE_25 : UInt<4> connect _io_vcalloc_req_bits_WIRE_25, _io_vcalloc_req_bits_T_87 connect _io_vcalloc_req_bits_WIRE_23.egress_node, _io_vcalloc_req_bits_WIRE_25 node _io_vcalloc_req_bits_T_88 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_89 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_90 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_91 = or(_io_vcalloc_req_bits_T_88, _io_vcalloc_req_bits_T_89) node _io_vcalloc_req_bits_T_92 = or(_io_vcalloc_req_bits_T_91, _io_vcalloc_req_bits_T_90) wire _io_vcalloc_req_bits_WIRE_26 : UInt<3> connect _io_vcalloc_req_bits_WIRE_26, _io_vcalloc_req_bits_T_92 connect _io_vcalloc_req_bits_WIRE_23.ingress_node_id, _io_vcalloc_req_bits_WIRE_26 node _io_vcalloc_req_bits_T_93 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_94 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_95 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_96 = or(_io_vcalloc_req_bits_T_93, _io_vcalloc_req_bits_T_94) node _io_vcalloc_req_bits_T_97 = or(_io_vcalloc_req_bits_T_96, _io_vcalloc_req_bits_T_95) wire _io_vcalloc_req_bits_WIRE_27 : UInt<4> connect _io_vcalloc_req_bits_WIRE_27, _io_vcalloc_req_bits_T_97 connect _io_vcalloc_req_bits_WIRE_23.ingress_node, _io_vcalloc_req_bits_WIRE_27 node _io_vcalloc_req_bits_T_98 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_99 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_100 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_101 = or(_io_vcalloc_req_bits_T_98, _io_vcalloc_req_bits_T_99) node _io_vcalloc_req_bits_T_102 = or(_io_vcalloc_req_bits_T_101, _io_vcalloc_req_bits_T_100) wire _io_vcalloc_req_bits_WIRE_28 : UInt<2> connect _io_vcalloc_req_bits_WIRE_28, _io_vcalloc_req_bits_T_102 connect _io_vcalloc_req_bits_WIRE_23.vnet_id, _io_vcalloc_req_bits_WIRE_28 connect _io_vcalloc_req_bits_WIRE.flow, _io_vcalloc_req_bits_WIRE_23 connect io.vcalloc_req.bits, _io_vcalloc_req_bits_WIRE connect vcalloc_vals[0], UInt<1>(0h0) invalidate vcalloc_reqs[0].vc_sel.`0`[0] invalidate vcalloc_reqs[0].vc_sel.`0`[1] invalidate vcalloc_reqs[0].vc_sel.`0`[2] invalidate vcalloc_reqs[0].vc_sel.`1`[0] invalidate vcalloc_reqs[0].vc_sel.`1`[1] invalidate vcalloc_reqs[0].vc_sel.`1`[2] invalidate vcalloc_reqs[0].vc_sel.`2`[0] invalidate vcalloc_reqs[0].vc_sel.`2`[1] invalidate vcalloc_reqs[0].vc_sel.`2`[2] invalidate vcalloc_reqs[0].vc_sel.`3`[0] invalidate vcalloc_reqs[0].vc_sel.`3`[1] invalidate vcalloc_reqs[0].vc_sel.`3`[2] invalidate vcalloc_reqs[0].vc_sel.`4`[0] invalidate vcalloc_reqs[0].vc_sel.`5`[0] invalidate vcalloc_reqs[0].in_vc invalidate vcalloc_reqs[0].flow.egress_node_id invalidate vcalloc_reqs[0].flow.egress_node invalidate vcalloc_reqs[0].flow.ingress_node_id invalidate vcalloc_reqs[0].flow.ingress_node invalidate vcalloc_reqs[0].flow.vnet_id node _vcalloc_vals_1_T = eq(states[1].g, UInt<3>(0h2)) node _vcalloc_vals_1_T_1 = eq(states[1].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_1_T_2 = and(_vcalloc_vals_1_T, _vcalloc_vals_1_T_1) connect vcalloc_vals[1], _vcalloc_vals_1_T_2 connect vcalloc_reqs[1].in_vc, UInt<1>(0h1) connect vcalloc_reqs[1].vc_sel.`0`, states[1].vc_sel.`0` connect vcalloc_reqs[1].vc_sel.`1`, states[1].vc_sel.`1` connect vcalloc_reqs[1].vc_sel.`2`, states[1].vc_sel.`2` connect vcalloc_reqs[1].vc_sel.`3`, states[1].vc_sel.`3` connect vcalloc_reqs[1].vc_sel.`4`, states[1].vc_sel.`4` connect vcalloc_reqs[1].vc_sel.`5`, states[1].vc_sel.`5` connect vcalloc_reqs[1].flow, states[1].flow node _T_24 = bits(vcalloc_sel, 1, 1) node _T_25 = and(vcalloc_vals[1], _T_24) node _T_26 = and(_T_25, io.vcalloc_req.ready) when _T_26 : connect states[1].g, UInt<3>(0h3) node _T_27 = and(route_arbiter.io.in[1].ready, route_arbiter.io.in[1].valid) when _T_27 : connect vcalloc_vals[1], UInt<1>(0h1) connect vcalloc_reqs[1].vc_sel.`0`, io.router_resp.vc_sel.`0` connect vcalloc_reqs[1].vc_sel.`1`, io.router_resp.vc_sel.`1` connect vcalloc_reqs[1].vc_sel.`2`, io.router_resp.vc_sel.`2` connect vcalloc_reqs[1].vc_sel.`3`, io.router_resp.vc_sel.`3` connect vcalloc_reqs[1].vc_sel.`4`, io.router_resp.vc_sel.`4` connect vcalloc_reqs[1].vc_sel.`5`, io.router_resp.vc_sel.`5` node _vcalloc_vals_2_T = eq(states[2].g, UInt<3>(0h2)) node _vcalloc_vals_2_T_1 = eq(states[2].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_2_T_2 = and(_vcalloc_vals_2_T, _vcalloc_vals_2_T_1) connect vcalloc_vals[2], _vcalloc_vals_2_T_2 connect vcalloc_reqs[2].in_vc, UInt<2>(0h2) connect vcalloc_reqs[2].vc_sel.`0`, states[2].vc_sel.`0` connect vcalloc_reqs[2].vc_sel.`1`, states[2].vc_sel.`1` connect vcalloc_reqs[2].vc_sel.`2`, states[2].vc_sel.`2` connect vcalloc_reqs[2].vc_sel.`3`, states[2].vc_sel.`3` connect vcalloc_reqs[2].vc_sel.`4`, states[2].vc_sel.`4` connect vcalloc_reqs[2].vc_sel.`5`, states[2].vc_sel.`5` connect vcalloc_reqs[2].flow, states[2].flow node _T_28 = bits(vcalloc_sel, 2, 2) node _T_29 = and(vcalloc_vals[2], _T_28) node _T_30 = and(_T_29, io.vcalloc_req.ready) when _T_30 : connect states[2].g, UInt<3>(0h3) node _T_31 = and(route_arbiter.io.in[2].ready, route_arbiter.io.in[2].valid) when _T_31 : connect vcalloc_vals[2], UInt<1>(0h1) connect vcalloc_reqs[2].vc_sel.`0`, io.router_resp.vc_sel.`0` connect vcalloc_reqs[2].vc_sel.`1`, io.router_resp.vc_sel.`1` connect vcalloc_reqs[2].vc_sel.`2`, io.router_resp.vc_sel.`2` connect vcalloc_reqs[2].vc_sel.`3`, io.router_resp.vc_sel.`3` connect vcalloc_reqs[2].vc_sel.`4`, io.router_resp.vc_sel.`4` connect vcalloc_reqs[2].vc_sel.`5`, io.router_resp.vc_sel.`5` node _io_debug_va_stall_T = add(vcalloc_vals[1], vcalloc_vals[2]) node _io_debug_va_stall_T_1 = bits(_io_debug_va_stall_T, 1, 0) node _io_debug_va_stall_T_2 = add(vcalloc_vals[0], _io_debug_va_stall_T_1) node _io_debug_va_stall_T_3 = bits(_io_debug_va_stall_T_2, 1, 0) node _io_debug_va_stall_T_4 = sub(_io_debug_va_stall_T_3, io.vcalloc_req.ready) node _io_debug_va_stall_T_5 = tail(_io_debug_va_stall_T_4, 1) connect io.debug.va_stall, _io_debug_va_stall_T_5 node _T_32 = and(io.vcalloc_req.ready, io.vcalloc_req.valid) when _T_32 : node _T_33 = bits(vcalloc_sel, 0, 0) when _T_33 : connect states[0].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[0].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[0].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[0].vc_sel.`4`, io.vcalloc_resp.vc_sel.`4` connect states[0].vc_sel.`5`, io.vcalloc_resp.vc_sel.`5` connect states[0].g, UInt<3>(0h3) node _T_34 = bits(vcalloc_sel, 1, 1) when _T_34 : connect states[1].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[1].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[1].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[1].vc_sel.`4`, io.vcalloc_resp.vc_sel.`4` connect states[1].vc_sel.`5`, io.vcalloc_resp.vc_sel.`5` connect states[1].g, UInt<3>(0h3) node _T_35 = bits(vcalloc_sel, 2, 2) when _T_35 : connect states[2].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[2].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[2].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[2].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[2].vc_sel.`4`, io.vcalloc_resp.vc_sel.`4` connect states[2].vc_sel.`5`, io.vcalloc_resp.vc_sel.`5` connect states[2].g, UInt<3>(0h3) inst salloc_arb of SwitchArbiter_81 connect salloc_arb.clock, clock connect salloc_arb.reset, reset connect salloc_arb.io.in[0].valid, UInt<1>(0h0) invalidate salloc_arb.io.in[0].bits.tail invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[0] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[1] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[2] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[0] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[1] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[2] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[0] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[1] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[2] invalidate salloc_arb.io.in[0].bits.vc_sel.`3`[0] invalidate salloc_arb.io.in[0].bits.vc_sel.`3`[1] invalidate salloc_arb.io.in[0].bits.vc_sel.`3`[2] invalidate salloc_arb.io.in[0].bits.vc_sel.`4`[0] invalidate salloc_arb.io.in[0].bits.vc_sel.`5`[0] node credit_available_hi = cat(states[1].vc_sel.`0`[2], states[1].vc_sel.`0`[1]) node _credit_available_T = cat(credit_available_hi, states[1].vc_sel.`0`[0]) node credit_available_hi_1 = cat(states[1].vc_sel.`1`[2], states[1].vc_sel.`1`[1]) node _credit_available_T_1 = cat(credit_available_hi_1, states[1].vc_sel.`1`[0]) node credit_available_hi_2 = cat(states[1].vc_sel.`2`[2], states[1].vc_sel.`2`[1]) node _credit_available_T_2 = cat(credit_available_hi_2, states[1].vc_sel.`2`[0]) node credit_available_hi_3 = cat(states[1].vc_sel.`3`[2], states[1].vc_sel.`3`[1]) node _credit_available_T_3 = cat(credit_available_hi_3, states[1].vc_sel.`3`[0]) node credit_available_lo_hi = cat(_credit_available_T_2, _credit_available_T_1) node credit_available_lo = cat(credit_available_lo_hi, _credit_available_T) node credit_available_hi_hi = cat(states[1].vc_sel.`5`[0], states[1].vc_sel.`4`[0]) node credit_available_hi_4 = cat(credit_available_hi_hi, _credit_available_T_3) node _credit_available_T_4 = cat(credit_available_hi_4, credit_available_lo) node credit_available_hi_5 = cat(io.out_credit_available.`0`[2], io.out_credit_available.`0`[1]) node _credit_available_T_5 = cat(credit_available_hi_5, io.out_credit_available.`0`[0]) node credit_available_hi_6 = cat(io.out_credit_available.`1`[2], io.out_credit_available.`1`[1]) node _credit_available_T_6 = cat(credit_available_hi_6, io.out_credit_available.`1`[0]) node credit_available_hi_7 = cat(io.out_credit_available.`2`[2], io.out_credit_available.`2`[1]) node _credit_available_T_7 = cat(credit_available_hi_7, io.out_credit_available.`2`[0]) node credit_available_hi_8 = cat(io.out_credit_available.`3`[2], io.out_credit_available.`3`[1]) node _credit_available_T_8 = cat(credit_available_hi_8, io.out_credit_available.`3`[0]) node credit_available_lo_hi_1 = cat(_credit_available_T_7, _credit_available_T_6) node credit_available_lo_1 = cat(credit_available_lo_hi_1, _credit_available_T_5) node credit_available_hi_hi_1 = cat(io.out_credit_available.`5`[0], io.out_credit_available.`4`[0]) node credit_available_hi_9 = cat(credit_available_hi_hi_1, _credit_available_T_8) node _credit_available_T_9 = cat(credit_available_hi_9, credit_available_lo_1) node _credit_available_T_10 = and(_credit_available_T_4, _credit_available_T_9) node credit_available = neq(_credit_available_T_10, UInt<1>(0h0)) node _salloc_arb_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h3)) node _salloc_arb_io_in_1_valid_T_1 = and(_salloc_arb_io_in_1_valid_T, credit_available) node _salloc_arb_io_in_1_valid_T_2 = and(_salloc_arb_io_in_1_valid_T_1, input_buffer.io.deq[1].valid) connect salloc_arb.io.in[1].valid, _salloc_arb_io_in_1_valid_T_2 connect salloc_arb.io.in[1].bits.vc_sel.`0`[0], states[1].vc_sel.`0`[0] connect salloc_arb.io.in[1].bits.vc_sel.`0`[1], states[1].vc_sel.`0`[1] connect salloc_arb.io.in[1].bits.vc_sel.`0`[2], states[1].vc_sel.`0`[2] connect salloc_arb.io.in[1].bits.vc_sel.`1`[0], states[1].vc_sel.`1`[0] connect salloc_arb.io.in[1].bits.vc_sel.`1`[1], states[1].vc_sel.`1`[1] connect salloc_arb.io.in[1].bits.vc_sel.`1`[2], states[1].vc_sel.`1`[2] connect salloc_arb.io.in[1].bits.vc_sel.`2`[0], states[1].vc_sel.`2`[0] connect salloc_arb.io.in[1].bits.vc_sel.`2`[1], states[1].vc_sel.`2`[1] connect salloc_arb.io.in[1].bits.vc_sel.`2`[2], states[1].vc_sel.`2`[2] connect salloc_arb.io.in[1].bits.vc_sel.`3`[0], states[1].vc_sel.`3`[0] connect salloc_arb.io.in[1].bits.vc_sel.`3`[1], states[1].vc_sel.`3`[1] connect salloc_arb.io.in[1].bits.vc_sel.`3`[2], states[1].vc_sel.`3`[2] connect salloc_arb.io.in[1].bits.vc_sel.`4`[0], states[1].vc_sel.`4`[0] connect salloc_arb.io.in[1].bits.vc_sel.`5`[0], states[1].vc_sel.`5`[0] connect salloc_arb.io.in[1].bits.tail, input_buffer.io.deq[1].bits.tail node _T_36 = and(salloc_arb.io.in[1].ready, salloc_arb.io.in[1].valid) node _T_37 = and(_T_36, input_buffer.io.deq[1].bits.tail) when _T_37 : connect states[1].g, UInt<3>(0h0) connect input_buffer.io.deq[1].ready, salloc_arb.io.in[1].ready node credit_available_hi_10 = cat(states[2].vc_sel.`0`[2], states[2].vc_sel.`0`[1]) node _credit_available_T_11 = cat(credit_available_hi_10, states[2].vc_sel.`0`[0]) node credit_available_hi_11 = cat(states[2].vc_sel.`1`[2], states[2].vc_sel.`1`[1]) node _credit_available_T_12 = cat(credit_available_hi_11, states[2].vc_sel.`1`[0]) node credit_available_hi_12 = cat(states[2].vc_sel.`2`[2], states[2].vc_sel.`2`[1]) node _credit_available_T_13 = cat(credit_available_hi_12, states[2].vc_sel.`2`[0]) node credit_available_hi_13 = cat(states[2].vc_sel.`3`[2], states[2].vc_sel.`3`[1]) node _credit_available_T_14 = cat(credit_available_hi_13, states[2].vc_sel.`3`[0]) node credit_available_lo_hi_2 = cat(_credit_available_T_13, _credit_available_T_12) node credit_available_lo_2 = cat(credit_available_lo_hi_2, _credit_available_T_11) node credit_available_hi_hi_2 = cat(states[2].vc_sel.`5`[0], states[2].vc_sel.`4`[0]) node credit_available_hi_14 = cat(credit_available_hi_hi_2, _credit_available_T_14) node _credit_available_T_15 = cat(credit_available_hi_14, credit_available_lo_2) node credit_available_hi_15 = cat(io.out_credit_available.`0`[2], io.out_credit_available.`0`[1]) node _credit_available_T_16 = cat(credit_available_hi_15, io.out_credit_available.`0`[0]) node credit_available_hi_16 = cat(io.out_credit_available.`1`[2], io.out_credit_available.`1`[1]) node _credit_available_T_17 = cat(credit_available_hi_16, io.out_credit_available.`1`[0]) node credit_available_hi_17 = cat(io.out_credit_available.`2`[2], io.out_credit_available.`2`[1]) node _credit_available_T_18 = cat(credit_available_hi_17, io.out_credit_available.`2`[0]) node credit_available_hi_18 = cat(io.out_credit_available.`3`[2], io.out_credit_available.`3`[1]) node _credit_available_T_19 = cat(credit_available_hi_18, io.out_credit_available.`3`[0]) node credit_available_lo_hi_3 = cat(_credit_available_T_18, _credit_available_T_17) node credit_available_lo_3 = cat(credit_available_lo_hi_3, _credit_available_T_16) node credit_available_hi_hi_3 = cat(io.out_credit_available.`5`[0], io.out_credit_available.`4`[0]) node credit_available_hi_19 = cat(credit_available_hi_hi_3, _credit_available_T_19) node _credit_available_T_20 = cat(credit_available_hi_19, credit_available_lo_3) node _credit_available_T_21 = and(_credit_available_T_15, _credit_available_T_20) node credit_available_1 = neq(_credit_available_T_21, UInt<1>(0h0)) node _salloc_arb_io_in_2_valid_T = eq(states[2].g, UInt<3>(0h3)) node _salloc_arb_io_in_2_valid_T_1 = and(_salloc_arb_io_in_2_valid_T, credit_available_1) node _salloc_arb_io_in_2_valid_T_2 = and(_salloc_arb_io_in_2_valid_T_1, input_buffer.io.deq[2].valid) connect salloc_arb.io.in[2].valid, _salloc_arb_io_in_2_valid_T_2 connect salloc_arb.io.in[2].bits.vc_sel.`0`[0], states[2].vc_sel.`0`[0] connect salloc_arb.io.in[2].bits.vc_sel.`0`[1], states[2].vc_sel.`0`[1] connect salloc_arb.io.in[2].bits.vc_sel.`0`[2], states[2].vc_sel.`0`[2] connect salloc_arb.io.in[2].bits.vc_sel.`1`[0], states[2].vc_sel.`1`[0] connect salloc_arb.io.in[2].bits.vc_sel.`1`[1], states[2].vc_sel.`1`[1] connect salloc_arb.io.in[2].bits.vc_sel.`1`[2], states[2].vc_sel.`1`[2] connect salloc_arb.io.in[2].bits.vc_sel.`2`[0], states[2].vc_sel.`2`[0] connect salloc_arb.io.in[2].bits.vc_sel.`2`[1], states[2].vc_sel.`2`[1] connect salloc_arb.io.in[2].bits.vc_sel.`2`[2], states[2].vc_sel.`2`[2] connect salloc_arb.io.in[2].bits.vc_sel.`3`[0], states[2].vc_sel.`3`[0] connect salloc_arb.io.in[2].bits.vc_sel.`3`[1], states[2].vc_sel.`3`[1] connect salloc_arb.io.in[2].bits.vc_sel.`3`[2], states[2].vc_sel.`3`[2] connect salloc_arb.io.in[2].bits.vc_sel.`4`[0], states[2].vc_sel.`4`[0] connect salloc_arb.io.in[2].bits.vc_sel.`5`[0], states[2].vc_sel.`5`[0] connect salloc_arb.io.in[2].bits.tail, input_buffer.io.deq[2].bits.tail node _T_38 = and(salloc_arb.io.in[2].ready, salloc_arb.io.in[2].valid) node _T_39 = and(_T_38, input_buffer.io.deq[2].bits.tail) when _T_39 : connect states[2].g, UInt<3>(0h0) connect input_buffer.io.deq[2].ready, salloc_arb.io.in[2].ready node _io_debug_sa_stall_T = eq(salloc_arb.io.in[0].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_1 = and(salloc_arb.io.in[0].valid, _io_debug_sa_stall_T) node _io_debug_sa_stall_T_2 = eq(salloc_arb.io.in[1].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_3 = and(salloc_arb.io.in[1].valid, _io_debug_sa_stall_T_2) node _io_debug_sa_stall_T_4 = eq(salloc_arb.io.in[2].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_5 = and(salloc_arb.io.in[2].valid, _io_debug_sa_stall_T_4) node _io_debug_sa_stall_T_6 = add(_io_debug_sa_stall_T_3, _io_debug_sa_stall_T_5) node _io_debug_sa_stall_T_7 = bits(_io_debug_sa_stall_T_6, 1, 0) node _io_debug_sa_stall_T_8 = add(_io_debug_sa_stall_T_1, _io_debug_sa_stall_T_7) node _io_debug_sa_stall_T_9 = bits(_io_debug_sa_stall_T_8, 1, 0) connect io.debug.sa_stall, _io_debug_sa_stall_T_9 connect io.salloc_req[0].bits, salloc_arb.io.out[0].bits connect io.salloc_req[0].valid, salloc_arb.io.out[0].valid connect salloc_arb.io.out[0].ready, io.salloc_req[0].ready when io.block : connect salloc_arb.io.out[0].ready, UInt<1>(0h0) connect io.salloc_req[0].valid, UInt<1>(0h0) wire salloc_outs : { valid : UInt<1>, vid : UInt<2>, out_vid : UInt<2>, flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1] node _io_in_credit_return_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_credit_return_T_1 = mux(_io_in_credit_return_T, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.credit_return, _io_in_credit_return_T_1 node _io_in_vc_free_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_vc_free_T_1 = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _io_in_vc_free_T_2 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _io_in_vc_free_T_3 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _io_in_vc_free_T_4 = mux(_io_in_vc_free_T_1, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_5 = mux(_io_in_vc_free_T_2, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_6 = mux(_io_in_vc_free_T_3, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_7 = or(_io_in_vc_free_T_4, _io_in_vc_free_T_5) node _io_in_vc_free_T_8 = or(_io_in_vc_free_T_7, _io_in_vc_free_T_6) wire _io_in_vc_free_WIRE : UInt<1> connect _io_in_vc_free_WIRE, _io_in_vc_free_T_8 node _io_in_vc_free_T_9 = and(_io_in_vc_free_T, _io_in_vc_free_WIRE) node _io_in_vc_free_T_10 = mux(_io_in_vc_free_T_9, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.vc_free, _io_in_vc_free_T_10 node _salloc_outs_0_valid_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) connect salloc_outs[0].valid, _salloc_outs_0_valid_T node salloc_outs_0_vid_hi = bits(salloc_arb.io.chosen_oh[0], 2, 2) node salloc_outs_0_vid_lo = bits(salloc_arb.io.chosen_oh[0], 1, 0) node _salloc_outs_0_vid_T = orr(salloc_outs_0_vid_hi) node _salloc_outs_0_vid_T_1 = or(salloc_outs_0_vid_hi, salloc_outs_0_vid_lo) node _salloc_outs_0_vid_T_2 = bits(_salloc_outs_0_vid_T_1, 1, 1) node _salloc_outs_0_vid_T_3 = cat(_salloc_outs_0_vid_T, _salloc_outs_0_vid_T_2) connect salloc_outs[0].vid, _salloc_outs_0_vid_T_3 node _vc_sel_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _vc_sel_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _vc_sel_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) wire vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[3], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]} wire _vc_sel_WIRE : UInt<1>[3] node _vc_sel_T_3 = mux(_vc_sel_T, states[0].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_4 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_5 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_6 = or(_vc_sel_T_3, _vc_sel_T_4) node _vc_sel_T_7 = or(_vc_sel_T_6, _vc_sel_T_5) wire _vc_sel_WIRE_1 : UInt<1> connect _vc_sel_WIRE_1, _vc_sel_T_7 connect _vc_sel_WIRE[0], _vc_sel_WIRE_1 node _vc_sel_T_8 = mux(_vc_sel_T, states[0].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_9 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_10 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_11 = or(_vc_sel_T_8, _vc_sel_T_9) node _vc_sel_T_12 = or(_vc_sel_T_11, _vc_sel_T_10) wire _vc_sel_WIRE_2 : UInt<1> connect _vc_sel_WIRE_2, _vc_sel_T_12 connect _vc_sel_WIRE[1], _vc_sel_WIRE_2 node _vc_sel_T_13 = mux(_vc_sel_T, states[0].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_14 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_15 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_16 = or(_vc_sel_T_13, _vc_sel_T_14) node _vc_sel_T_17 = or(_vc_sel_T_16, _vc_sel_T_15) wire _vc_sel_WIRE_3 : UInt<1> connect _vc_sel_WIRE_3, _vc_sel_T_17 connect _vc_sel_WIRE[2], _vc_sel_WIRE_3 connect vc_sel.`0`, _vc_sel_WIRE wire _vc_sel_WIRE_4 : UInt<1>[3] node _vc_sel_T_18 = mux(_vc_sel_T, states[0].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_19 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_20 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_21 = or(_vc_sel_T_18, _vc_sel_T_19) node _vc_sel_T_22 = or(_vc_sel_T_21, _vc_sel_T_20) wire _vc_sel_WIRE_5 : UInt<1> connect _vc_sel_WIRE_5, _vc_sel_T_22 connect _vc_sel_WIRE_4[0], _vc_sel_WIRE_5 node _vc_sel_T_23 = mux(_vc_sel_T, states[0].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_24 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_25 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_26 = or(_vc_sel_T_23, _vc_sel_T_24) node _vc_sel_T_27 = or(_vc_sel_T_26, _vc_sel_T_25) wire _vc_sel_WIRE_6 : UInt<1> connect _vc_sel_WIRE_6, _vc_sel_T_27 connect _vc_sel_WIRE_4[1], _vc_sel_WIRE_6 node _vc_sel_T_28 = mux(_vc_sel_T, states[0].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_29 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_30 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_31 = or(_vc_sel_T_28, _vc_sel_T_29) node _vc_sel_T_32 = or(_vc_sel_T_31, _vc_sel_T_30) wire _vc_sel_WIRE_7 : UInt<1> connect _vc_sel_WIRE_7, _vc_sel_T_32 connect _vc_sel_WIRE_4[2], _vc_sel_WIRE_7 connect vc_sel.`1`, _vc_sel_WIRE_4 wire _vc_sel_WIRE_8 : UInt<1>[3] node _vc_sel_T_33 = mux(_vc_sel_T, states[0].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_34 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_35 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_36 = or(_vc_sel_T_33, _vc_sel_T_34) node _vc_sel_T_37 = or(_vc_sel_T_36, _vc_sel_T_35) wire _vc_sel_WIRE_9 : UInt<1> connect _vc_sel_WIRE_9, _vc_sel_T_37 connect _vc_sel_WIRE_8[0], _vc_sel_WIRE_9 node _vc_sel_T_38 = mux(_vc_sel_T, states[0].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_39 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_40 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_41 = or(_vc_sel_T_38, _vc_sel_T_39) node _vc_sel_T_42 = or(_vc_sel_T_41, _vc_sel_T_40) wire _vc_sel_WIRE_10 : UInt<1> connect _vc_sel_WIRE_10, _vc_sel_T_42 connect _vc_sel_WIRE_8[1], _vc_sel_WIRE_10 node _vc_sel_T_43 = mux(_vc_sel_T, states[0].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_44 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_45 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_46 = or(_vc_sel_T_43, _vc_sel_T_44) node _vc_sel_T_47 = or(_vc_sel_T_46, _vc_sel_T_45) wire _vc_sel_WIRE_11 : UInt<1> connect _vc_sel_WIRE_11, _vc_sel_T_47 connect _vc_sel_WIRE_8[2], _vc_sel_WIRE_11 connect vc_sel.`2`, _vc_sel_WIRE_8 wire _vc_sel_WIRE_12 : UInt<1>[3] node _vc_sel_T_48 = mux(_vc_sel_T, states[0].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_49 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_50 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_51 = or(_vc_sel_T_48, _vc_sel_T_49) node _vc_sel_T_52 = or(_vc_sel_T_51, _vc_sel_T_50) wire _vc_sel_WIRE_13 : UInt<1> connect _vc_sel_WIRE_13, _vc_sel_T_52 connect _vc_sel_WIRE_12[0], _vc_sel_WIRE_13 node _vc_sel_T_53 = mux(_vc_sel_T, states[0].vc_sel.`3`[1], UInt<1>(0h0)) node _vc_sel_T_54 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[1], UInt<1>(0h0)) node _vc_sel_T_55 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[1], UInt<1>(0h0)) node _vc_sel_T_56 = or(_vc_sel_T_53, _vc_sel_T_54) node _vc_sel_T_57 = or(_vc_sel_T_56, _vc_sel_T_55) wire _vc_sel_WIRE_14 : UInt<1> connect _vc_sel_WIRE_14, _vc_sel_T_57 connect _vc_sel_WIRE_12[1], _vc_sel_WIRE_14 node _vc_sel_T_58 = mux(_vc_sel_T, states[0].vc_sel.`3`[2], UInt<1>(0h0)) node _vc_sel_T_59 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[2], UInt<1>(0h0)) node _vc_sel_T_60 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[2], UInt<1>(0h0)) node _vc_sel_T_61 = or(_vc_sel_T_58, _vc_sel_T_59) node _vc_sel_T_62 = or(_vc_sel_T_61, _vc_sel_T_60) wire _vc_sel_WIRE_15 : UInt<1> connect _vc_sel_WIRE_15, _vc_sel_T_62 connect _vc_sel_WIRE_12[2], _vc_sel_WIRE_15 connect vc_sel.`3`, _vc_sel_WIRE_12 wire _vc_sel_WIRE_16 : UInt<1>[1] node _vc_sel_T_63 = mux(_vc_sel_T, states[0].vc_sel.`4`[0], UInt<1>(0h0)) node _vc_sel_T_64 = mux(_vc_sel_T_1, states[1].vc_sel.`4`[0], UInt<1>(0h0)) node _vc_sel_T_65 = mux(_vc_sel_T_2, states[2].vc_sel.`4`[0], UInt<1>(0h0)) node _vc_sel_T_66 = or(_vc_sel_T_63, _vc_sel_T_64) node _vc_sel_T_67 = or(_vc_sel_T_66, _vc_sel_T_65) wire _vc_sel_WIRE_17 : UInt<1> connect _vc_sel_WIRE_17, _vc_sel_T_67 connect _vc_sel_WIRE_16[0], _vc_sel_WIRE_17 connect vc_sel.`4`, _vc_sel_WIRE_16 wire _vc_sel_WIRE_18 : UInt<1>[1] node _vc_sel_T_68 = mux(_vc_sel_T, states[0].vc_sel.`5`[0], UInt<1>(0h0)) node _vc_sel_T_69 = mux(_vc_sel_T_1, states[1].vc_sel.`5`[0], UInt<1>(0h0)) node _vc_sel_T_70 = mux(_vc_sel_T_2, states[2].vc_sel.`5`[0], UInt<1>(0h0)) node _vc_sel_T_71 = or(_vc_sel_T_68, _vc_sel_T_69) node _vc_sel_T_72 = or(_vc_sel_T_71, _vc_sel_T_70) wire _vc_sel_WIRE_19 : UInt<1> connect _vc_sel_WIRE_19, _vc_sel_T_72 connect _vc_sel_WIRE_18[0], _vc_sel_WIRE_19 connect vc_sel.`5`, _vc_sel_WIRE_18 node _channel_oh_T = or(vc_sel.`0`[0], vc_sel.`0`[1]) node channel_oh_0 = or(_channel_oh_T, vc_sel.`0`[2]) node _channel_oh_T_1 = or(vc_sel.`1`[0], vc_sel.`1`[1]) node channel_oh_1 = or(_channel_oh_T_1, vc_sel.`1`[2]) node _channel_oh_T_2 = or(vc_sel.`2`[0], vc_sel.`2`[1]) node channel_oh_2 = or(_channel_oh_T_2, vc_sel.`2`[2]) node _channel_oh_T_3 = or(vc_sel.`3`[0], vc_sel.`3`[1]) node channel_oh_3 = or(_channel_oh_T_3, vc_sel.`3`[2]) node virt_channel_hi = cat(vc_sel.`0`[2], vc_sel.`0`[1]) node _virt_channel_T = cat(virt_channel_hi, vc_sel.`0`[0]) node virt_channel_hi_1 = bits(_virt_channel_T, 2, 2) node virt_channel_lo = bits(_virt_channel_T, 1, 0) node _virt_channel_T_1 = orr(virt_channel_hi_1) node _virt_channel_T_2 = or(virt_channel_hi_1, virt_channel_lo) node _virt_channel_T_3 = bits(_virt_channel_T_2, 1, 1) node _virt_channel_T_4 = cat(_virt_channel_T_1, _virt_channel_T_3) node virt_channel_hi_2 = cat(vc_sel.`1`[2], vc_sel.`1`[1]) node _virt_channel_T_5 = cat(virt_channel_hi_2, vc_sel.`1`[0]) node virt_channel_hi_3 = bits(_virt_channel_T_5, 2, 2) node virt_channel_lo_1 = bits(_virt_channel_T_5, 1, 0) node _virt_channel_T_6 = orr(virt_channel_hi_3) node _virt_channel_T_7 = or(virt_channel_hi_3, virt_channel_lo_1) node _virt_channel_T_8 = bits(_virt_channel_T_7, 1, 1) node _virt_channel_T_9 = cat(_virt_channel_T_6, _virt_channel_T_8) node virt_channel_hi_4 = cat(vc_sel.`2`[2], vc_sel.`2`[1]) node _virt_channel_T_10 = cat(virt_channel_hi_4, vc_sel.`2`[0]) node virt_channel_hi_5 = bits(_virt_channel_T_10, 2, 2) node virt_channel_lo_2 = bits(_virt_channel_T_10, 1, 0) node _virt_channel_T_11 = orr(virt_channel_hi_5) node _virt_channel_T_12 = or(virt_channel_hi_5, virt_channel_lo_2) node _virt_channel_T_13 = bits(_virt_channel_T_12, 1, 1) node _virt_channel_T_14 = cat(_virt_channel_T_11, _virt_channel_T_13) node virt_channel_hi_6 = cat(vc_sel.`3`[2], vc_sel.`3`[1]) node _virt_channel_T_15 = cat(virt_channel_hi_6, vc_sel.`3`[0]) node virt_channel_hi_7 = bits(_virt_channel_T_15, 2, 2) node virt_channel_lo_3 = bits(_virt_channel_T_15, 1, 0) node _virt_channel_T_16 = orr(virt_channel_hi_7) node _virt_channel_T_17 = or(virt_channel_hi_7, virt_channel_lo_3) node _virt_channel_T_18 = bits(_virt_channel_T_17, 1, 1) node _virt_channel_T_19 = cat(_virt_channel_T_16, _virt_channel_T_18) node _virt_channel_T_20 = mux(channel_oh_0, _virt_channel_T_4, UInt<1>(0h0)) node _virt_channel_T_21 = mux(channel_oh_1, _virt_channel_T_9, UInt<1>(0h0)) node _virt_channel_T_22 = mux(channel_oh_2, _virt_channel_T_14, UInt<1>(0h0)) node _virt_channel_T_23 = mux(channel_oh_3, _virt_channel_T_19, UInt<1>(0h0)) node _virt_channel_T_24 = mux(vc_sel.`4`[0], UInt<1>(0h0), UInt<1>(0h0)) node _virt_channel_T_25 = mux(vc_sel.`5`[0], UInt<1>(0h0), UInt<1>(0h0)) node _virt_channel_T_26 = or(_virt_channel_T_20, _virt_channel_T_21) node _virt_channel_T_27 = or(_virt_channel_T_26, _virt_channel_T_22) node _virt_channel_T_28 = or(_virt_channel_T_27, _virt_channel_T_23) node _virt_channel_T_29 = or(_virt_channel_T_28, _virt_channel_T_24) node _virt_channel_T_30 = or(_virt_channel_T_29, _virt_channel_T_25) wire virt_channel : UInt<2> connect virt_channel, _virt_channel_T_30 node _T_40 = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) when _T_40 : connect salloc_outs[0].out_vid, virt_channel node _salloc_outs_0_flit_payload_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_payload_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_payload_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_payload_T_3 = mux(_salloc_outs_0_flit_payload_T, input_buffer.io.deq[0].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_4 = mux(_salloc_outs_0_flit_payload_T_1, input_buffer.io.deq[1].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_5 = mux(_salloc_outs_0_flit_payload_T_2, input_buffer.io.deq[2].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_6 = or(_salloc_outs_0_flit_payload_T_3, _salloc_outs_0_flit_payload_T_4) node _salloc_outs_0_flit_payload_T_7 = or(_salloc_outs_0_flit_payload_T_6, _salloc_outs_0_flit_payload_T_5) wire _salloc_outs_0_flit_payload_WIRE : UInt<145> connect _salloc_outs_0_flit_payload_WIRE, _salloc_outs_0_flit_payload_T_7 connect salloc_outs[0].flit.payload, _salloc_outs_0_flit_payload_WIRE node _salloc_outs_0_flit_head_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_head_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_head_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_head_T_3 = mux(_salloc_outs_0_flit_head_T, input_buffer.io.deq[0].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_4 = mux(_salloc_outs_0_flit_head_T_1, input_buffer.io.deq[1].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_5 = mux(_salloc_outs_0_flit_head_T_2, input_buffer.io.deq[2].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_6 = or(_salloc_outs_0_flit_head_T_3, _salloc_outs_0_flit_head_T_4) node _salloc_outs_0_flit_head_T_7 = or(_salloc_outs_0_flit_head_T_6, _salloc_outs_0_flit_head_T_5) wire _salloc_outs_0_flit_head_WIRE : UInt<1> connect _salloc_outs_0_flit_head_WIRE, _salloc_outs_0_flit_head_T_7 connect salloc_outs[0].flit.head, _salloc_outs_0_flit_head_WIRE node _salloc_outs_0_flit_tail_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_tail_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_tail_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_tail_T_3 = mux(_salloc_outs_0_flit_tail_T, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_4 = mux(_salloc_outs_0_flit_tail_T_1, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_5 = mux(_salloc_outs_0_flit_tail_T_2, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_6 = or(_salloc_outs_0_flit_tail_T_3, _salloc_outs_0_flit_tail_T_4) node _salloc_outs_0_flit_tail_T_7 = or(_salloc_outs_0_flit_tail_T_6, _salloc_outs_0_flit_tail_T_5) wire _salloc_outs_0_flit_tail_WIRE : UInt<1> connect _salloc_outs_0_flit_tail_WIRE, _salloc_outs_0_flit_tail_T_7 connect salloc_outs[0].flit.tail, _salloc_outs_0_flit_tail_WIRE node _salloc_outs_0_flit_flow_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_flow_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_flow_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) wire _salloc_outs_0_flit_flow_WIRE : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>} node _salloc_outs_0_flit_flow_T_3 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_4 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_5 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_6 = or(_salloc_outs_0_flit_flow_T_3, _salloc_outs_0_flit_flow_T_4) node _salloc_outs_0_flit_flow_T_7 = or(_salloc_outs_0_flit_flow_T_6, _salloc_outs_0_flit_flow_T_5) wire _salloc_outs_0_flit_flow_WIRE_1 : UInt<2> connect _salloc_outs_0_flit_flow_WIRE_1, _salloc_outs_0_flit_flow_T_7 connect _salloc_outs_0_flit_flow_WIRE.egress_node_id, _salloc_outs_0_flit_flow_WIRE_1 node _salloc_outs_0_flit_flow_T_8 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_9 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_10 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_11 = or(_salloc_outs_0_flit_flow_T_8, _salloc_outs_0_flit_flow_T_9) node _salloc_outs_0_flit_flow_T_12 = or(_salloc_outs_0_flit_flow_T_11, _salloc_outs_0_flit_flow_T_10) wire _salloc_outs_0_flit_flow_WIRE_2 : UInt<4> connect _salloc_outs_0_flit_flow_WIRE_2, _salloc_outs_0_flit_flow_T_12 connect _salloc_outs_0_flit_flow_WIRE.egress_node, _salloc_outs_0_flit_flow_WIRE_2 node _salloc_outs_0_flit_flow_T_13 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_14 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_15 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_16 = or(_salloc_outs_0_flit_flow_T_13, _salloc_outs_0_flit_flow_T_14) node _salloc_outs_0_flit_flow_T_17 = or(_salloc_outs_0_flit_flow_T_16, _salloc_outs_0_flit_flow_T_15) wire _salloc_outs_0_flit_flow_WIRE_3 : UInt<3> connect _salloc_outs_0_flit_flow_WIRE_3, _salloc_outs_0_flit_flow_T_17 connect _salloc_outs_0_flit_flow_WIRE.ingress_node_id, _salloc_outs_0_flit_flow_WIRE_3 node _salloc_outs_0_flit_flow_T_18 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_19 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_20 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_21 = or(_salloc_outs_0_flit_flow_T_18, _salloc_outs_0_flit_flow_T_19) node _salloc_outs_0_flit_flow_T_22 = or(_salloc_outs_0_flit_flow_T_21, _salloc_outs_0_flit_flow_T_20) wire _salloc_outs_0_flit_flow_WIRE_4 : UInt<4> connect _salloc_outs_0_flit_flow_WIRE_4, _salloc_outs_0_flit_flow_T_22 connect _salloc_outs_0_flit_flow_WIRE.ingress_node, _salloc_outs_0_flit_flow_WIRE_4 node _salloc_outs_0_flit_flow_T_23 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_24 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_25 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_26 = or(_salloc_outs_0_flit_flow_T_23, _salloc_outs_0_flit_flow_T_24) node _salloc_outs_0_flit_flow_T_27 = or(_salloc_outs_0_flit_flow_T_26, _salloc_outs_0_flit_flow_T_25) wire _salloc_outs_0_flit_flow_WIRE_5 : UInt<2> connect _salloc_outs_0_flit_flow_WIRE_5, _salloc_outs_0_flit_flow_T_27 connect _salloc_outs_0_flit_flow_WIRE.vnet_id, _salloc_outs_0_flit_flow_WIRE_5 connect salloc_outs[0].flit.flow, _salloc_outs_0_flit_flow_WIRE else : invalidate salloc_outs[0].out_vid invalidate salloc_outs[0].flit.virt_channel_id invalidate salloc_outs[0].flit.flow.egress_node_id invalidate salloc_outs[0].flit.flow.egress_node invalidate salloc_outs[0].flit.flow.ingress_node_id invalidate salloc_outs[0].flit.flow.ingress_node invalidate salloc_outs[0].flit.flow.vnet_id invalidate salloc_outs[0].flit.payload invalidate salloc_outs[0].flit.tail invalidate salloc_outs[0].flit.head invalidate salloc_outs[0].flit.virt_channel_id connect io.out[0].valid, salloc_outs[0].valid connect io.out[0].bits.flit, salloc_outs[0].flit connect io.out[0].bits.out_virt_channel, salloc_outs[0].out_vid invalidate states[0].fifo_deps invalidate states[0].flow.egress_node_id invalidate states[0].flow.egress_node invalidate states[0].flow.ingress_node_id invalidate states[0].flow.ingress_node invalidate states[0].flow.vnet_id invalidate states[0].vc_sel.`0`[0] invalidate states[0].vc_sel.`0`[1] invalidate states[0].vc_sel.`0`[2] invalidate states[0].vc_sel.`1`[0] invalidate states[0].vc_sel.`1`[1] invalidate states[0].vc_sel.`1`[2] invalidate states[0].vc_sel.`2`[0] invalidate states[0].vc_sel.`2`[1] invalidate states[0].vc_sel.`2`[2] invalidate states[0].vc_sel.`3`[0] invalidate states[0].vc_sel.`3`[1] invalidate states[0].vc_sel.`3`[2] invalidate states[0].vc_sel.`4`[0] invalidate states[0].vc_sel.`5`[0] invalidate states[0].g connect states[1].vc_sel.`0`[0], UInt<1>(0h0) connect states[1].vc_sel.`0`[2], UInt<1>(0h0) connect states[1].vc_sel.`1`[0], UInt<1>(0h0) connect states[1].vc_sel.`1`[1], UInt<1>(0h0) connect states[1].vc_sel.`1`[2], UInt<1>(0h0) connect states[1].vc_sel.`2`[0], UInt<1>(0h0) connect states[1].vc_sel.`2`[1], UInt<1>(0h0) connect states[1].vc_sel.`2`[2], UInt<1>(0h0) connect states[1].vc_sel.`3`[0], UInt<1>(0h0) connect states[1].vc_sel.`3`[1], UInt<1>(0h0) connect states[1].vc_sel.`3`[2], UInt<1>(0h0) connect states[2].vc_sel.`0`[0], UInt<1>(0h0) connect states[2].vc_sel.`0`[1], UInt<1>(0h0) connect states[2].vc_sel.`1`[0], UInt<1>(0h0) connect states[2].vc_sel.`1`[1], UInt<1>(0h0) connect states[2].vc_sel.`1`[2], UInt<1>(0h0) connect states[2].vc_sel.`2`[0], UInt<1>(0h0) connect states[2].vc_sel.`2`[1], UInt<1>(0h0) connect states[2].vc_sel.`2`[2], UInt<1>(0h0) connect states[2].vc_sel.`3`[0], UInt<1>(0h0) connect states[2].vc_sel.`3`[1], UInt<1>(0h0) connect states[2].vc_sel.`3`[2], UInt<1>(0h0) node _T_41 = asUInt(reset) when _T_41 : connect states[0].g, UInt<3>(0h0) connect states[1].g, UInt<3>(0h0) connect states[2].g, UInt<3>(0h0)	module InputUnit_34( // @[InputUnit.scala:158:7] input clock, // @[InputUnit.scala:158:7] input reset, // @[InputUnit.scala:158:7] output [1:0] io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14] output [3:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14] output [2:0] io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [3:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_3_0, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_3_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_3_2, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_0, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_2, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_0, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_2, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_0, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_2, // @[InputUnit.scala:170:14] input io_vcalloc_req_ready, // @[InputUnit.scala:170:14] output io_vcalloc_req_valid, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_5_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_4_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_3_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_3_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_3_2, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_2, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_2, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_2, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_5_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_4_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_1, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_2, // @[InputUnit.scala:170:14] input io_out_credit_available_5_0, // @[InputUnit.scala:170:14] input io_out_credit_available_4_0, // @[InputUnit.scala:170:14] input io_out_credit_available_3_0, // @[InputUnit.scala:170:14] input io_out_credit_available_2_0, // @[InputUnit.scala:170:14] input io_out_credit_available_1_0, // @[InputUnit.scala:170:14] input io_out_credit_available_1_1, // @[InputUnit.scala:170:14] input io_out_credit_available_1_2, // @[InputUnit.scala:170:14] input io_out_credit_available_0_0, // @[InputUnit.scala:170:14] input io_out_credit_available_0_1, // @[InputUnit.scala:170:14] input io_out_credit_available_0_2, // @[InputUnit.scala:170:14] input io_salloc_req_0_ready, // @[InputUnit.scala:170:14] output io_salloc_req_0_valid, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_5_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_4_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14] output io_out_0_valid, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14] output [144:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14] output [1:0] io_debug_va_stall, // @[InputUnit.scala:170:14] output [1:0] io_debug_sa_stall, // @[InputUnit.scala:170:14] input io_in_flit_0_valid, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14] input [144:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14] output [2:0] io_in_credit_return, // @[InputUnit.scala:170:14] output [2:0] io_in_vc_free // @[InputUnit.scala:170:14] ); wire _GEN; // @[MixedVec.scala:116:9] wire _GEN_0; // @[MixedVec.scala:116:9] wire vcalloc_reqs_2_vc_sel_0_2; // @[MixedVec.scala:116:9] wire vcalloc_vals_2; // @[InputUnit.scala:266:25, :272:46, :273:29] wire _GEN_1; // @[MixedVec.scala:116:9] wire _GEN_2; // @[MixedVec.scala:116:9] wire vcalloc_reqs_1_vc_sel_0_1; // @[MixedVec.scala:116:9] wire vcalloc_vals_1; // @[InputUnit.scala:266:25, :272:46, :273:29] wire _salloc_arb_io_in_1_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_2_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26] wire [2:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26] wire _route_arbiter_io_in_1_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_2_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29] wire [1:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29] wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28] wire [144:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28] wire [144:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28] wire [144:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28] reg [2:0] states_1_g; // @[InputUnit.scala:192:19] reg states_1_vc_sel_5_0; // @[InputUnit.scala:192:19] reg states_1_vc_sel_4_0; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_1; // @[InputUnit.scala:192:19] reg [1:0] states_1_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_1_flow_ingress_node; // @[InputUnit.scala:192:19] reg [2:0] states_1_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_1_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_1_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_2_g; // @[InputUnit.scala:192:19] reg states_2_vc_sel_5_0; // @[InputUnit.scala:192:19] reg states_2_vc_sel_4_0; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_2; // @[InputUnit.scala:192:19] reg [1:0] states_2_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_2_flow_ingress_node; // @[InputUnit.scala:192:19] reg [2:0] states_2_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_2_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_2_flow_egress_node_id; // @[InputUnit.scala:192:19] wire _GEN_3 = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30] wire route_arbiter_io_in_1_valid = states_1_g == 3'h1; // @[InputUnit.scala:158:7, :192:19, :229:22] wire _GEN_4 = _route_arbiter_io_in_1_ready & route_arbiter_io_in_1_valid; // @[Decoupled.scala:51:35] wire route_arbiter_io_in_2_valid = states_2_g == 3'h1; // @[InputUnit.scala:158:7, :192:19, :229:22] wire _GEN_5 = _route_arbiter_io_in_2_ready & route_arbiter_io_in_2_valid; // @[Decoupled.scala:51:35]
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_59 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_87 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0	module AsyncResetSynchronizerShiftReg_w1_d3_i0_59( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] output io_q // @[ShiftReg.scala:36:14] ); wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_87 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_176 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_176( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w4_d3_i0_30 : input clock : Clock input reset : Reset output io : { flip d : UInt<4>, q : UInt<4>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_278 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q node _output_T_2 = asAsyncReset(reset) node _output_T_3 = bits(io.d, 1, 1) inst output_chain_1 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_279 connect output_chain_1.clock, clock connect output_chain_1.reset, _output_T_2 connect output_chain_1.io.d, _output_T_3 wire output_1 : UInt<1> connect output_1, output_chain_1.io.q node _output_T_4 = asAsyncReset(reset) node _output_T_5 = bits(io.d, 2, 2) inst output_chain_2 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_280 connect output_chain_2.clock, clock connect output_chain_2.reset, _output_T_4 connect output_chain_2.io.d, _output_T_5 wire output_2 : UInt<1> connect output_2, output_chain_2.io.q node _output_T_6 = asAsyncReset(reset) node _output_T_7 = bits(io.d, 3, 3) inst output_chain_3 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_281 connect output_chain_3.clock, clock connect output_chain_3.reset, _output_T_6 connect output_chain_3.io.d, _output_T_7 wire output_3 : UInt<1> connect output_3, output_chain_3.io.q node io_q_lo = cat(output_1, output_0) node io_q_hi = cat(output_3, output_2) node _io_q_T = cat(io_q_hi, io_q_lo) connect io.q, _io_q_T	module AsyncResetSynchronizerShiftReg_w4_d3_i0_30( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input [3:0] io_d, // @[ShiftReg.scala:36:14] output [3:0] io_q // @[ShiftReg.scala:36:14] ); wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21] wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14] wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7] wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_1; // @[ShiftReg.scala:48:24] wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_2; // @[ShiftReg.scala:48:24] wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_3; // @[ShiftReg.scala:48:24] wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14] wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14] assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14] assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_278 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_279 output_chain_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_2), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_3), // @[SynchronizerReg.scala:87:41] .io_q (output_1) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_280 output_chain_2 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_4), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_5), // @[SynchronizerReg.scala:87:41] .io_q (output_2) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_281 output_chain_3 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_6), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_7), // @[SynchronizerReg.scala:87:41] .io_q (output_3) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_218 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x	module OptimizationBarrier_TLBEntryData_218( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to this FIRRTL code module OutputUnit_1 : input clock : Clock input reset : Reset output io : { flip in : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], credit_available : UInt<1>[8], channel_status : { occupied : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}[8], flip allocs : { alloc : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}[8], flip credit_alloc : { alloc : UInt<1>, tail : UInt<1>}[8], out : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}} reg states : { `7` : { occupied : UInt<1>, c : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}, `6` : { occupied : UInt<1>, c : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}, `5` : { occupied : UInt<1>, c : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}, `4` : { occupied : UInt<1>, c : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}, `3` : { occupied : UInt<1>, c : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}, `2` : { occupied : UInt<1>, c : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}, `1` : { occupied : UInt<1>, c : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}, `0` : { occupied : UInt<1>, c : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}}, clock connect io.channel_status[0].occupied, states.`0`.occupied connect io.channel_status[0].flow, states.`0`.flow connect io.channel_status[1].occupied, states.`1`.occupied connect io.channel_status[1].flow, states.`1`.flow connect io.channel_status[2].occupied, states.`2`.occupied connect io.channel_status[2].flow, states.`2`.flow connect io.channel_status[3].occupied, states.`3`.occupied connect io.channel_status[3].flow, states.`3`.flow connect io.channel_status[4].occupied, states.`4`.occupied connect io.channel_status[4].flow, states.`4`.flow connect io.channel_status[5].occupied, states.`5`.occupied connect io.channel_status[5].flow, states.`5`.flow connect io.channel_status[6].occupied, states.`6`.occupied connect io.channel_status[6].flow, states.`6`.flow connect io.channel_status[7].occupied, states.`7`.occupied connect io.channel_status[7].flow, states.`7`.flow connect io.out.flit, io.in node _T = bits(io.out.vc_free, 0, 0) when _T : node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(states.`0`.occupied, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed\n at OutputUnit.scala:75 assert(s.occupied)\n") : printf assert(clock, states.`0`.occupied, UInt<1>(0h1), "") : assert connect states.`0`.occupied, UInt<1>(0h0) node _T_4 = bits(io.out.vc_free, 1, 1) when _T_4 : node _T_5 = asUInt(reset) node _T_6 = eq(_T_5, UInt<1>(0h0)) when _T_6 : node _T_7 = eq(states.`1`.occupied, UInt<1>(0h0)) when _T_7 : printf(clock, UInt<1>(0h1), "Assertion failed\n at OutputUnit.scala:75 assert(s.occupied)\n") : printf_1 assert(clock, states.`1`.occupied, UInt<1>(0h1), "") : assert_1 connect states.`1`.occupied, UInt<1>(0h0) node _T_8 = bits(io.out.vc_free, 2, 2) when _T_8 : node _T_9 = asUInt(reset) node _T_10 = eq(_T_9, UInt<1>(0h0)) when _T_10 : node _T_11 = eq(states.`2`.occupied, UInt<1>(0h0)) when _T_11 : printf(clock, UInt<1>(0h1), "Assertion failed\n at OutputUnit.scala:75 assert(s.occupied)\n") : printf_2 assert(clock, states.`2`.occupied, UInt<1>(0h1), "") : assert_2 connect states.`2`.occupied, UInt<1>(0h0) node _T_12 = bits(io.out.vc_free, 3, 3) when _T_12 : node _T_13 = asUInt(reset) node _T_14 = eq(_T_13, UInt<1>(0h0)) when _T_14 : node _T_15 = eq(states.`3`.occupied, UInt<1>(0h0)) when _T_15 : printf(clock, UInt<1>(0h1), "Assertion failed\n at OutputUnit.scala:75 assert(s.occupied)\n") : printf_3 assert(clock, states.`3`.occupied, UInt<1>(0h1), "") : assert_3 connect states.`3`.occupied, UInt<1>(0h0) node _T_16 = bits(io.out.vc_free, 4, 4) when _T_16 : node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(states.`4`.occupied, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed\n at OutputUnit.scala:75 assert(s.occupied)\n") : printf_4 assert(clock, states.`4`.occupied, UInt<1>(0h1), "") : assert_4 connect states.`4`.occupied, UInt<1>(0h0) node _T_20 = bits(io.out.vc_free, 5, 5) when _T_20 : node _T_21 = asUInt(reset) node _T_22 = eq(_T_21, UInt<1>(0h0)) when _T_22 : node _T_23 = eq(states.`5`.occupied, UInt<1>(0h0)) when _T_23 : printf(clock, UInt<1>(0h1), "Assertion failed\n at OutputUnit.scala:75 assert(s.occupied)\n") : printf_5 assert(clock, states.`5`.occupied, UInt<1>(0h1), "") : assert_5 connect states.`5`.occupied, UInt<1>(0h0) node _T_24 = bits(io.out.vc_free, 6, 6) when _T_24 : node _T_25 = asUInt(reset) node _T_26 = eq(_T_25, UInt<1>(0h0)) when _T_26 : node _T_27 = eq(states.`6`.occupied, UInt<1>(0h0)) when _T_27 : printf(clock, UInt<1>(0h1), "Assertion failed\n at OutputUnit.scala:75 assert(s.occupied)\n") : printf_6 assert(clock, states.`6`.occupied, UInt<1>(0h1), "") : assert_6 connect states.`6`.occupied, UInt<1>(0h0) node _T_28 = bits(io.out.vc_free, 7, 7) when _T_28 : node _T_29 = asUInt(reset) node _T_30 = eq(_T_29, UInt<1>(0h0)) when _T_30 : node _T_31 = eq(states.`7`.occupied, UInt<1>(0h0)) when _T_31 : printf(clock, UInt<1>(0h1), "Assertion failed\n at OutputUnit.scala:75 assert(s.occupied)\n") : printf_7 assert(clock, states.`7`.occupied, UInt<1>(0h1), "") : assert_7 connect states.`7`.occupied, UInt<1>(0h0) when io.allocs[0].alloc : connect states.`0`.occupied, UInt<1>(0h1) connect states.`0`.flow, io.allocs[0].flow when io.allocs[1].alloc : connect states.`1`.occupied, UInt<1>(0h1) connect states.`1`.flow, io.allocs[1].flow when io.allocs[2].alloc : connect states.`2`.occupied, UInt<1>(0h1) connect states.`2`.flow, io.allocs[2].flow when io.allocs[3].alloc : connect states.`3`.occupied, UInt<1>(0h1) connect states.`3`.flow, io.allocs[3].flow when io.allocs[4].alloc : connect states.`4`.occupied, UInt<1>(0h1) connect states.`4`.flow, io.allocs[4].flow when io.allocs[5].alloc : connect states.`5`.occupied, UInt<1>(0h1) connect states.`5`.flow, io.allocs[5].flow when io.allocs[6].alloc : connect states.`6`.occupied, UInt<1>(0h1) connect states.`6`.flow, io.allocs[6].flow when io.allocs[7].alloc : connect states.`7`.occupied, UInt<1>(0h1) connect states.`7`.flow, io.allocs[7].flow node _io_credit_available_0_T = neq(states.`0`.c, UInt<1>(0h0)) connect io.credit_available[0], _io_credit_available_0_T node _io_credit_available_1_T = neq(states.`1`.c, UInt<1>(0h0)) connect io.credit_available[1], _io_credit_available_1_T node _io_credit_available_2_T = neq(states.`2`.c, UInt<1>(0h0)) connect io.credit_available[2], _io_credit_available_2_T node _io_credit_available_3_T = neq(states.`3`.c, UInt<1>(0h0)) connect io.credit_available[3], _io_credit_available_3_T node _io_credit_available_4_T = neq(states.`4`.c, UInt<1>(0h0)) connect io.credit_available[4], _io_credit_available_4_T node _io_credit_available_5_T = neq(states.`5`.c, UInt<1>(0h0)) connect io.credit_available[5], _io_credit_available_5_T node _io_credit_available_6_T = neq(states.`6`.c, UInt<1>(0h0)) connect io.credit_available[6], _io_credit_available_6_T node _io_credit_available_7_T = neq(states.`7`.c, UInt<1>(0h0)) connect io.credit_available[7], _io_credit_available_7_T node free = bits(io.out.credit_return, 0, 0) node _states_0_c_T = add(states.`0`.c, free) node _states_0_c_T_1 = sub(_states_0_c_T, io.credit_alloc[0].alloc) node _states_0_c_T_2 = tail(_states_0_c_T_1, 1) connect states.`0`.c, _states_0_c_T_2 node free_1 = bits(io.out.credit_return, 1, 1) node _states_1_c_T = add(states.`1`.c, free_1) node _states_1_c_T_1 = sub(_states_1_c_T, io.credit_alloc[1].alloc) node _states_1_c_T_2 = tail(_states_1_c_T_1, 1) connect states.`1`.c, _states_1_c_T_2 node free_2 = bits(io.out.credit_return, 2, 2) node _states_2_c_T = add(states.`2`.c, free_2) node _states_2_c_T_1 = sub(_states_2_c_T, io.credit_alloc[2].alloc) node _states_2_c_T_2 = tail(_states_2_c_T_1, 1) connect states.`2`.c, _states_2_c_T_2 node free_3 = bits(io.out.credit_return, 3, 3) node _states_3_c_T = add(states.`3`.c, free_3) node _states_3_c_T_1 = sub(_states_3_c_T, io.credit_alloc[3].alloc) node _states_3_c_T_2 = tail(_states_3_c_T_1, 1) connect states.`3`.c, _states_3_c_T_2 node free_4 = bits(io.out.credit_return, 4, 4) node _states_4_c_T = add(states.`4`.c, free_4) node _states_4_c_T_1 = sub(_states_4_c_T, io.credit_alloc[4].alloc) node _states_4_c_T_2 = tail(_states_4_c_T_1, 1) connect states.`4`.c, _states_4_c_T_2 node free_5 = bits(io.out.credit_return, 5, 5) node _states_5_c_T = add(states.`5`.c, free_5) node _states_5_c_T_1 = sub(_states_5_c_T, io.credit_alloc[5].alloc) node _states_5_c_T_2 = tail(_states_5_c_T_1, 1) connect states.`5`.c, _states_5_c_T_2 node free_6 = bits(io.out.credit_return, 6, 6) node _states_6_c_T = add(states.`6`.c, free_6) node _states_6_c_T_1 = sub(_states_6_c_T, io.credit_alloc[6].alloc) node _states_6_c_T_2 = tail(_states_6_c_T_1, 1) connect states.`6`.c, _states_6_c_T_2 node free_7 = bits(io.out.credit_return, 7, 7) node _states_7_c_T = add(states.`7`.c, free_7) node _states_7_c_T_1 = sub(_states_7_c_T, io.credit_alloc[7].alloc) node _states_7_c_T_2 = tail(_states_7_c_T_1, 1) connect states.`7`.c, _states_7_c_T_2 node _T_32 = asUInt(reset) when _T_32 : connect states.`0`.occupied, UInt<1>(0h0) connect states.`1`.occupied, UInt<1>(0h0) connect states.`2`.occupied, UInt<1>(0h0) connect states.`3`.occupied, UInt<1>(0h0) connect states.`4`.occupied, UInt<1>(0h0) connect states.`5`.occupied, UInt<1>(0h0) connect states.`6`.occupied, UInt<1>(0h0) connect states.`7`.occupied, UInt<1>(0h0) connect states.`0`.c, UInt<3>(0h4) connect states.`1`.c, UInt<3>(0h4) connect states.`2`.c, UInt<3>(0h4) connect states.`3`.c, UInt<3>(0h4) connect states.`4`.c, UInt<3>(0h4) connect states.`5`.c, UInt<3>(0h4) connect states.`6`.c, UInt<3>(0h4) connect states.`7`.c, UInt<3>(0h4)	module OutputUnit_1( // @[OutputUnit.scala:52:7] input clock, // @[OutputUnit.scala:52:7] input reset, // @[OutputUnit.scala:52:7] input io_in_0_valid, // @[OutputUnit.scala:58:14] input io_in_0_bits_head, // @[OutputUnit.scala:58:14] input io_in_0_bits_tail, // @[OutputUnit.scala:58:14] input [72:0] io_in_0_bits_payload, // @[OutputUnit.scala:58:14] input [2:0] io_in_0_bits_flow_vnet_id, // @[OutputUnit.scala:58:14] input [4:0] io_in_0_bits_flow_ingress_node, // @[OutputUnit.scala:58:14] input [1:0] io_in_0_bits_flow_ingress_node_id, // @[OutputUnit.scala:58:14] input [4:0] io_in_0_bits_flow_egress_node, // @[OutputUnit.scala:58:14] input [1:0] io_in_0_bits_flow_egress_node_id, // @[OutputUnit.scala:58:14] input [2:0] io_in_0_bits_virt_channel_id, // @[OutputUnit.scala:58:14] output io_credit_available_0, // @[OutputUnit.scala:58:14] output io_credit_available_1, // @[OutputUnit.scala:58:14] output io_credit_available_2, // @[OutputUnit.scala:58:14] output io_credit_available_3, // @[OutputUnit.scala:58:14] output io_credit_available_4, // @[OutputUnit.scala:58:14] output io_credit_available_5, // @[OutputUnit.scala:58:14] output io_credit_available_6, // @[OutputUnit.scala:58:14] output io_credit_available_7, // @[OutputUnit.scala:58:14] output io_channel_status_0_occupied, // @[OutputUnit.scala:58:14] output io_channel_status_1_occupied, // @[OutputUnit.scala:58:14] output io_channel_status_2_occupied, // @[OutputUnit.scala:58:14] output io_channel_status_3_occupied, // @[OutputUnit.scala:58:14] output io_channel_status_4_occupied, // @[OutputUnit.scala:58:14] output io_channel_status_5_occupied, // @[OutputUnit.scala:58:14] output io_channel_status_6_occupied, // @[OutputUnit.scala:58:14] output io_channel_status_7_occupied, // @[OutputUnit.scala:58:14] input io_allocs_0_alloc, // @[OutputUnit.scala:58:14] input io_allocs_1_alloc, // @[OutputUnit.scala:58:14] input io_allocs_2_alloc, // @[OutputUnit.scala:58:14] input io_allocs_3_alloc, // @[OutputUnit.scala:58:14] input io_allocs_4_alloc, // @[OutputUnit.scala:58:14] input io_allocs_5_alloc, // @[OutputUnit.scala:58:14] input io_allocs_6_alloc, // @[OutputUnit.scala:58:14] input io_allocs_7_alloc, // @[OutputUnit.scala:58:14] input io_credit_alloc_0_alloc, // @[OutputUnit.scala:58:14] input io_credit_alloc_1_alloc, // @[OutputUnit.scala:58:14] input io_credit_alloc_2_alloc, // @[OutputUnit.scala:58:14] input io_credit_alloc_3_alloc, // @[OutputUnit.scala:58:14] input io_credit_alloc_4_alloc, // @[OutputUnit.scala:58:14] input io_credit_alloc_5_alloc, // @[OutputUnit.scala:58:14] input io_credit_alloc_6_alloc, // @[OutputUnit.scala:58:14] input io_credit_alloc_7_alloc, // @[OutputUnit.scala:58:14] output io_out_flit_0_valid, // @[OutputUnit.scala:58:14] output io_out_flit_0_bits_head, // @[OutputUnit.scala:58:14] output io_out_flit_0_bits_tail, // @[OutputUnit.scala:58:14] output [72:0] io_out_flit_0_bits_payload, // @[OutputUnit.scala:58:14] output [2:0] io_out_flit_0_bits_flow_vnet_id, // @[OutputUnit.scala:58:14] output [4:0] io_out_flit_0_bits_flow_ingress_node, // @[OutputUnit.scala:58:14] output [1:0] io_out_flit_0_bits_flow_ingress_node_id, // @[OutputUnit.scala:58:14] output [4:0] io_out_flit_0_bits_flow_egress_node, // @[OutputUnit.scala:58:14] output [1:0] io_out_flit_0_bits_flow_egress_node_id, // @[OutputUnit.scala:58:14] output [2:0] io_out_flit_0_bits_virt_channel_id, // @[OutputUnit.scala:58:14] input [7:0] io_out_credit_return, // @[OutputUnit.scala:58:14] input [7:0] io_out_vc_free // @[OutputUnit.scala:58:14] ); reg states_7_occupied; // @[OutputUnit.scala:66:19] reg [2:0] states_7_c; // @[OutputUnit.scala:66:19] reg states_6_occupied; // @[OutputUnit.scala:66:19] reg [2:0] states_6_c; // @[OutputUnit.scala:66:19] reg states_5_occupied; // @[OutputUnit.scala:66:19] reg [2:0] states_5_c; // @[OutputUnit.scala:66:19] reg states_4_occupied; // @[OutputUnit.scala:66:19] reg [2:0] states_4_c; // @[OutputUnit.scala:66:19] reg states_3_occupied; // @[OutputUnit.scala:66:19] reg [2:0] states_3_c; // @[OutputUnit.scala:66:19] reg states_2_occupied; // @[OutputUnit.scala:66:19] reg [2:0] states_2_c; // @[OutputUnit.scala:66:19] reg states_1_occupied; // @[OutputUnit.scala:66:19] reg [2:0] states_1_c; // @[OutputUnit.scala:66:19] reg states_0_occupied; // @[OutputUnit.scala:66:19] reg [2:0] states_0_c; // @[OutputUnit.scala:66:19]
Generate the Verilog code corresponding to this FIRRTL code module Tile_41 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_297 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a	module Tile_41( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0, // @[Tile.scala:17:14] output io_bad_dataflow // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] wire io_bad_dataflow_0; // @[Tile.scala:16:7] PE_297 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0), .io_bad_dataflow (io_bad_dataflow_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module SystemBus : output auto : { flip coupler_from_spike_tile_tl_master_clock_xing_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, coupler_to_bus_named_coh_widget_anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, flip coupler_from_bus_named_fbus_bus_xing_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, coupler_to_bus_named_cbus_bus_xing_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, fixedClockNode_anon_out_2 : { clock : Clock, reset : Reset}, fixedClockNode_anon_out_1 : { clock : Clock, reset : Reset}, fixedClockNode_anon_out_0 : { clock : Clock, reset : Reset}, flip sbus_clock_groups_in : { member : { sbus_1 : { clock : Clock, reset : Reset}, sbus_0 : { clock : Clock, reset : Reset}}}, sbus_clock_groups_out : { member : { coh_0 : { clock : Clock, reset : Reset}}}} output clock : Clock output reset : Reset wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset inst sbus_clock_groups of ClockGroupAggregator_sbus inst clockGroup of ClockGroup inst fixedClockNode of FixedClockBroadcast_4 inst broadcast of BundleBridgeNexus_NoOutput inst system_bus_xbar of TLXbar_sbus_i2_o2_a32d64s6k3z4c connect system_bus_xbar.clock, childClock connect system_bus_xbar.reset, childReset inst fixer of TLFIFOFixer connect fixer.clock, childClock connect fixer.reset, childReset inst coupler_to_bus_named_cbus of TLInterconnectCoupler_sbus_to_bus_named_cbus connect coupler_to_bus_named_cbus.clock, childClock connect coupler_to_bus_named_cbus.reset, childReset inst coupler_from_bus_named_fbus of TLInterconnectCoupler_sbus_from_bus_named_fbus connect coupler_from_bus_named_fbus.clock, childClock connect coupler_from_bus_named_fbus.reset, childReset inst coupler_to_bus_named_coh of TLInterconnectCoupler_sbus_to_bus_named_coh connect coupler_to_bus_named_coh.clock, childClock connect coupler_to_bus_named_coh.reset, childReset inst coupler_from_spike_tile of TLInterconnectCoupler_sbus_from_spike_tile connect coupler_from_spike_tile.clock, childClock connect coupler_from_spike_tile.reset, childReset wire clockSinkNodeIn : { clock : Clock, reset : Reset} invalidate clockSinkNodeIn.reset invalidate clockSinkNodeIn.clock connect clockGroup.auto.in, sbus_clock_groups.auto.out_0 connect fixedClockNode.auto.anon_in, clockGroup.auto.out connect clockSinkNodeIn, fixedClockNode.auto.anon_out_0 connect coupler_to_bus_named_cbus.auto.widget_anon_in, system_bus_xbar.auto.anon_out_0 connect coupler_to_bus_named_coh.auto.widget_anon_in, system_bus_xbar.auto.anon_out_1 connect system_bus_xbar.auto.anon_in_0, fixer.auto.anon_out_0 connect system_bus_xbar.auto.anon_in_1, fixer.auto.anon_out_1 connect fixer.auto.anon_in_0, coupler_from_bus_named_fbus.auto.widget_anon_out connect fixer.auto.anon_in_1, coupler_from_spike_tile.auto.tl_out connect auto.sbus_clock_groups_out, sbus_clock_groups.auto.out_1 connect sbus_clock_groups.auto.in, auto.sbus_clock_groups_in connect auto.fixedClockNode_anon_out_0, fixedClockNode.auto.anon_out_1 connect auto.fixedClockNode_anon_out_1, fixedClockNode.auto.anon_out_2 connect auto.fixedClockNode_anon_out_2, fixedClockNode.auto.anon_out_3 connect coupler_to_bus_named_cbus.auto.bus_xing_out.d, auto.coupler_to_bus_named_cbus_bus_xing_out.d connect auto.coupler_to_bus_named_cbus_bus_xing_out.a.bits, coupler_to_bus_named_cbus.auto.bus_xing_out.a.bits connect auto.coupler_to_bus_named_cbus_bus_xing_out.a.valid, coupler_to_bus_named_cbus.auto.bus_xing_out.a.valid connect coupler_to_bus_named_cbus.auto.bus_xing_out.a.ready, auto.coupler_to_bus_named_cbus_bus_xing_out.a.ready connect coupler_from_bus_named_fbus.auto.bus_xing_in, auto.coupler_from_bus_named_fbus_bus_xing_in connect auto.coupler_to_bus_named_coh_widget_anon_out.e.bits, coupler_to_bus_named_coh.auto.widget_anon_out.e.bits connect auto.coupler_to_bus_named_coh_widget_anon_out.e.valid, coupler_to_bus_named_coh.auto.widget_anon_out.e.valid connect coupler_to_bus_named_coh.auto.widget_anon_out.e.ready, auto.coupler_to_bus_named_coh_widget_anon_out.e.ready connect coupler_to_bus_named_coh.auto.widget_anon_out.d, auto.coupler_to_bus_named_coh_widget_anon_out.d connect auto.coupler_to_bus_named_coh_widget_anon_out.c.bits, coupler_to_bus_named_coh.auto.widget_anon_out.c.bits connect auto.coupler_to_bus_named_coh_widget_anon_out.c.valid, coupler_to_bus_named_coh.auto.widget_anon_out.c.valid connect coupler_to_bus_named_coh.auto.widget_anon_out.c.ready, auto.coupler_to_bus_named_coh_widget_anon_out.c.ready connect coupler_to_bus_named_coh.auto.widget_anon_out.b, auto.coupler_to_bus_named_coh_widget_anon_out.b connect auto.coupler_to_bus_named_coh_widget_anon_out.a.bits, coupler_to_bus_named_coh.auto.widget_anon_out.a.bits connect auto.coupler_to_bus_named_coh_widget_anon_out.a.valid, coupler_to_bus_named_coh.auto.widget_anon_out.a.valid connect coupler_to_bus_named_coh.auto.widget_anon_out.a.ready, auto.coupler_to_bus_named_coh_widget_anon_out.a.ready connect coupler_from_spike_tile.auto.tl_master_clock_xing_in, auto.coupler_from_spike_tile_tl_master_clock_xing_in connect childClock, clockSinkNodeIn.clock connect childReset, clockSinkNodeIn.reset connect clock, clockSinkNodeIn.clock connect reset, clockSinkNodeIn.reset	module SystemBus( // @[ClockDomain.scala:14:9] output auto_coupler_from_spike_tile_tl_master_clock_xing_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_spike_tile_tl_master_clock_xing_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_from_spike_tile_tl_master_clock_xing_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_from_spike_tile_tl_master_clock_xing_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_coupler_from_spike_tile_tl_master_clock_xing_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_from_spike_tile_tl_master_clock_xing_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_coupler_from_spike_tile_tl_master_clock_xing_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_coupler_from_spike_tile_tl_master_clock_xing_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_from_spike_tile_tl_master_clock_xing_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_spike_tile_tl_master_clock_xing_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_spike_tile_tl_master_clock_xing_in_b_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_spike_tile_tl_master_clock_xing_in_b_valid, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_from_spike_tile_tl_master_clock_xing_in_b_bits_param, // @[LazyModuleImp.scala:107:25] output [31:0] auto_coupler_from_spike_tile_tl_master_clock_xing_in_b_bits_address, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_spike_tile_tl_master_clock_xing_in_c_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_spike_tile_tl_master_clock_xing_in_c_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_from_spike_tile_tl_master_clock_xing_in_c_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_from_spike_tile_tl_master_clock_xing_in_c_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_coupler_from_spike_tile_tl_master_clock_xing_in_c_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_from_spike_tile_tl_master_clock_xing_in_c_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_coupler_from_spike_tile_tl_master_clock_xing_in_c_bits_address, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_from_spike_tile_tl_master_clock_xing_in_c_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_spike_tile_tl_master_clock_xing_in_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_spike_tile_tl_master_clock_xing_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_spike_tile_tl_master_clock_xing_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_from_spike_tile_tl_master_clock_xing_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_from_spike_tile_tl_master_clock_xing_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_from_spike_tile_tl_master_clock_xing_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_from_spike_tile_tl_master_clock_xing_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_from_spike_tile_tl_master_clock_xing_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_spike_tile_tl_master_clock_xing_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_from_spike_tile_tl_master_clock_xing_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_spike_tile_tl_master_clock_xing_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_spike_tile_tl_master_clock_xing_in_e_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_from_spike_tile_tl_master_clock_xing_in_e_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_coh_widget_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_coh_widget_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_coh_widget_anon_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_coh_widget_anon_out_b_valid, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_bus_named_coh_widget_anon_out_b_bits_param, // @[LazyModuleImp.scala:107:25] input [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_b_bits_address, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_coh_widget_anon_out_c_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_coh_widget_anon_out_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_address, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_coh_widget_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_coh_widget_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_coh_widget_anon_out_e_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_e_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_bus_named_fbus_bus_xing_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_bus_named_fbus_bus_xing_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_bus_named_fbus_bus_xing_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_bus_named_fbus_bus_xing_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_cbus_bus_xing_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_cbus_bus_xing_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [28:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_cbus_bus_xing_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_cbus_bus_xing_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_2_clock, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_2_reset, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_1_clock, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_1_reset, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_0_clock, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_0_reset, // @[LazyModuleImp.scala:107:25] input auto_sbus_clock_groups_in_member_sbus_1_clock, // @[LazyModuleImp.scala:107:25] input auto_sbus_clock_groups_in_member_sbus_1_reset, // @[LazyModuleImp.scala:107:25] input auto_sbus_clock_groups_in_member_sbus_0_clock, // @[LazyModuleImp.scala:107:25] input auto_sbus_clock_groups_in_member_sbus_0_reset, // @[LazyModuleImp.scala:107:25] output auto_sbus_clock_groups_out_member_coh_0_clock, // @[LazyModuleImp.scala:107:25] output auto_sbus_clock_groups_out_member_coh_0_reset // @[LazyModuleImp.scala:107:25] ); wire coupler_to_bus_named_coh_auto_widget_anon_in_e_valid; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_e_bits_sink; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_d_ready; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_c_valid; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_c_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire [63:0] coupler_to_bus_named_coh_auto_widget_anon_in_c_bits_data; // @[LazyModuleImp.scala:138:7] wire [31:0] coupler_to_bus_named_coh_auto_widget_anon_in_c_bits_address; // @[LazyModuleImp.scala:138:7] wire [5:0] coupler_to_bus_named_coh_auto_widget_anon_in_c_bits_source; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_c_bits_size; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_c_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_c_bits_opcode; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_b_ready; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_a_valid; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire [63:0] coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_data; // @[LazyModuleImp.scala:138:7] wire [7:0] coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_mask; // @[LazyModuleImp.scala:138:7] wire [31:0] coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_address; // @[LazyModuleImp.scala:138:7] wire [5:0] coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_source; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_size; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_opcode; // @[LazyModuleImp.scala:138:7] wire coupler_from_bus_named_fbus_widget_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9] wire coupler_from_bus_named_fbus_widget_auto_anon_in_d_ready; // @[WidthWidget.scala:27:9] wire coupler_from_bus_named_fbus_widget_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire [63:0] coupler_from_bus_named_fbus_widget_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9] wire coupler_from_bus_named_fbus_widget_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9] wire [2:0] coupler_from_bus_named_fbus_widget_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:27:9] wire [4:0] coupler_from_bus_named_fbus_widget_auto_anon_in_d_bits_source; // @[WidthWidget.scala:27:9] wire [3:0] coupler_from_bus_named_fbus_widget_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9] wire [1:0] coupler_from_bus_named_fbus_widget_auto_anon_in_d_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_from_bus_named_fbus_widget_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9] wire coupler_from_bus_named_fbus_widget_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9] wire coupler_from_bus_named_fbus_widget_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9] wire coupler_from_bus_named_fbus_widget_auto_anon_in_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire [63:0] coupler_from_bus_named_fbus_widget_auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9] wire [7:0] coupler_from_bus_named_fbus_widget_auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9] wire [31:0] coupler_from_bus_named_fbus_widget_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9] wire [4:0] coupler_from_bus_named_fbus_widget_auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9] wire [3:0] coupler_from_bus_named_fbus_widget_auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9] wire [2:0] coupler_from_bus_named_fbus_widget_auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_from_bus_named_fbus_widget_auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_cbus_widget_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_cbus_widget_auto_anon_out_d_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_cbus_widget_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire [63:0] coupler_to_bus_named_cbus_widget_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_cbus_widget_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_cbus_widget_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_cbus_widget_auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9] wire [3:0] coupler_to_bus_named_cbus_widget_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_cbus_widget_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_cbus_widget_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_cbus_widget_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_cbus_widget_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_cbus_widget_auto_anon_out_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire [63:0] coupler_to_bus_named_cbus_widget_auto_anon_out_a_bits_data; // @[WidthWidget.scala:27:9] wire [7:0] coupler_to_bus_named_cbus_widget_auto_anon_out_a_bits_mask; // @[WidthWidget.scala:27:9] wire [28:0] coupler_to_bus_named_cbus_widget_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_cbus_widget_auto_anon_out_a_bits_source; // @[WidthWidget.scala:27:9] wire [3:0] coupler_to_bus_named_cbus_widget_auto_anon_out_a_bits_size; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_cbus_widget_auto_anon_out_a_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_cbus_widget_auto_anon_out_a_bits_opcode; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_cbus_auto_widget_anon_in_d_ready; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_cbus_auto_widget_anon_in_a_valid; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_cbus_auto_widget_anon_in_a_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire [63:0] coupler_to_bus_named_cbus_auto_widget_anon_in_a_bits_data; // @[LazyModuleImp.scala:138:7] wire [7:0] coupler_to_bus_named_cbus_auto_widget_anon_in_a_bits_mask; // @[LazyModuleImp.scala:138:7] wire [28:0] coupler_to_bus_named_cbus_auto_widget_anon_in_a_bits_address; // @[LazyModuleImp.scala:138:7] wire [5:0] coupler_to_bus_named_cbus_auto_widget_anon_in_a_bits_source; // @[LazyModuleImp.scala:138:7] wire [3:0] coupler_to_bus_named_cbus_auto_widget_anon_in_a_bits_size; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_cbus_auto_widget_anon_in_a_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_cbus_auto_widget_anon_in_a_bits_opcode; // @[LazyModuleImp.scala:138:7] wire fixer_auto_anon_out_0_d_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_0_d_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_out_0_d_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_0_d_bits_denied; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_0_d_bits_sink; // @[FIFOFixer.scala:50:9] wire [4:0] fixer_auto_anon_out_0_d_bits_source; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_out_0_d_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_out_0_d_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_0_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_0_a_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_1_d_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_1_d_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_out_1_d_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_1_d_bits_denied; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_1_d_bits_sink; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_out_1_d_bits_source; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_out_1_d_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_out_1_d_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_1_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_1_c_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_1_b_valid; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_auto_anon_out_1_b_bits_address; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_out_1_b_bits_param; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_1_a_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_0_d_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_0_d_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_0_d_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_in_0_d_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_0_d_bits_denied; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_0_d_bits_sink; // @[FIFOFixer.scala:50:9] wire [4:0] fixer_auto_anon_in_0_d_bits_source; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_in_0_d_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_in_0_d_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_0_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_0_a_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_0_a_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_0_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_in_0_a_bits_data; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_auto_anon_in_0_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_auto_anon_in_0_a_bits_address; // @[FIFOFixer.scala:50:9] wire [4:0] fixer_auto_anon_in_0_a_bits_source; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_in_0_a_bits_size; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_0_a_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_0_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_1_e_valid; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_1_e_bits_sink; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_1_d_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_1_d_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_1_d_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_in_1_d_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_1_d_bits_denied; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_1_d_bits_sink; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_in_1_d_bits_source; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_in_1_d_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_in_1_d_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_1_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_1_c_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_1_c_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_1_c_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_in_1_c_bits_data; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_auto_anon_in_1_c_bits_address; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_in_1_c_bits_source; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_in_1_c_bits_size; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_1_c_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_1_c_bits_opcode; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_1_b_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_1_b_ready; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_auto_anon_in_1_b_bits_address; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_in_1_b_bits_param; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_1_a_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_1_a_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_1_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_in_1_a_bits_data; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_auto_anon_in_1_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_auto_anon_in_1_a_bits_address; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_in_1_a_bits_source; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_in_1_a_bits_size; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_1_a_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_1_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire sbus_clock_groups_auto_out_0_member_sbus_0_reset; // @[ClockGroup.scala:53:9] wire sbus_clock_groups_auto_out_0_member_sbus_0_clock; // @[ClockGroup.scala:53:9] wire auto_coupler_from_spike_tile_tl_master_clock_xing_in_a_valid_0 = auto_coupler_from_spike_tile_tl_master_clock_xing_in_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_spike_tile_tl_master_clock_xing_in_a_bits_opcode_0 = auto_coupler_from_spike_tile_tl_master_clock_xing_in_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_spike_tile_tl_master_clock_xing_in_a_bits_param_0 = auto_coupler_from_spike_tile_tl_master_clock_xing_in_a_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_from_spike_tile_tl_master_clock_xing_in_a_bits_size_0 = auto_coupler_from_spike_tile_tl_master_clock_xing_in_a_bits_size; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_from_spike_tile_tl_master_clock_xing_in_a_bits_source_0 = auto_coupler_from_spike_tile_tl_master_clock_xing_in_a_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] auto_coupler_from_spike_tile_tl_master_clock_xing_in_a_bits_address_0 = auto_coupler_from_spike_tile_tl_master_clock_xing_in_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] auto_coupler_from_spike_tile_tl_master_clock_xing_in_a_bits_mask_0 = auto_coupler_from_spike_tile_tl_master_clock_xing_in_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_from_spike_tile_tl_master_clock_xing_in_a_bits_data_0 = auto_coupler_from_spike_tile_tl_master_clock_xing_in_a_bits_data; // @[ClockDomain.scala:14:9] wire auto_coupler_from_spike_tile_tl_master_clock_xing_in_a_bits_corrupt_0 = auto_coupler_from_spike_tile_tl_master_clock_xing_in_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_coupler_from_spike_tile_tl_master_clock_xing_in_b_ready_0 = auto_coupler_from_spike_tile_tl_master_clock_xing_in_b_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_from_spike_tile_tl_master_clock_xing_in_c_valid_0 = auto_coupler_from_spike_tile_tl_master_clock_xing_in_c_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_spike_tile_tl_master_clock_xing_in_c_bits_opcode_0 = auto_coupler_from_spike_tile_tl_master_clock_xing_in_c_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_spike_tile_tl_master_clock_xing_in_c_bits_param_0 = auto_coupler_from_spike_tile_tl_master_clock_xing_in_c_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_from_spike_tile_tl_master_clock_xing_in_c_bits_size_0 = auto_coupler_from_spike_tile_tl_master_clock_xing_in_c_bits_size; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_from_spike_tile_tl_master_clock_xing_in_c_bits_source_0 = auto_coupler_from_spike_tile_tl_master_clock_xing_in_c_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] auto_coupler_from_spike_tile_tl_master_clock_xing_in_c_bits_address_0 = auto_coupler_from_spike_tile_tl_master_clock_xing_in_c_bits_address; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_from_spike_tile_tl_master_clock_xing_in_c_bits_data_0 = auto_coupler_from_spike_tile_tl_master_clock_xing_in_c_bits_data; // @[ClockDomain.scala:14:9] wire auto_coupler_from_spike_tile_tl_master_clock_xing_in_c_bits_corrupt_0 = auto_coupler_from_spike_tile_tl_master_clock_xing_in_c_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_coupler_from_spike_tile_tl_master_clock_xing_in_d_ready_0 = auto_coupler_from_spike_tile_tl_master_clock_xing_in_d_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_from_spike_tile_tl_master_clock_xing_in_e_valid_0 = auto_coupler_from_spike_tile_tl_master_clock_xing_in_e_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_spike_tile_tl_master_clock_xing_in_e_bits_sink_0 = auto_coupler_from_spike_tile_tl_master_clock_xing_in_e_bits_sink; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_a_ready_0 = auto_coupler_to_bus_named_coh_widget_anon_out_a_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_b_valid_0 = auto_coupler_to_bus_named_coh_widget_anon_out_b_valid; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_bus_named_coh_widget_anon_out_b_bits_param_0 = auto_coupler_to_bus_named_coh_widget_anon_out_b_bits_param; // @[ClockDomain.scala:14:9] wire [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_b_bits_address_0 = auto_coupler_to_bus_named_coh_widget_anon_out_b_bits_address; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_c_ready_0 = auto_coupler_to_bus_named_coh_widget_anon_out_c_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_d_valid_0 = auto_coupler_to_bus_named_coh_widget_anon_out_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_opcode_0 = auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_param_0 = auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_param; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_size_0 = auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_size; // @[ClockDomain.scala:14:9] wire [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_source_0 = auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_source; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_sink_0 = auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_sink; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_denied_0 = auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_denied; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_data_0 = auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_data; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_corrupt_0 = auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_coupler_from_bus_named_fbus_bus_xing_in_a_valid_0 = auto_coupler_from_bus_named_fbus_bus_xing_in_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_opcode_0 = auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_param_0 = auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_size_0 = auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_size; // @[ClockDomain.scala:14:9] wire [4:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_source_0 = auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_address_0 = auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_mask_0 = auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_data_0 = auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_data; // @[ClockDomain.scala:14:9] wire auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_corrupt_0 = auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_coupler_from_bus_named_fbus_bus_xing_in_d_ready_0 = auto_coupler_from_bus_named_fbus_bus_xing_in_d_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_cbus_bus_xing_out_a_ready_0 = auto_coupler_to_bus_named_cbus_bus_xing_out_a_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_cbus_bus_xing_out_d_valid_0 = auto_coupler_to_bus_named_cbus_bus_xing_out_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_opcode_0 = auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_param_0 = auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_size_0 = auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_size; // @[ClockDomain.scala:14:9] wire [5:0] auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_source_0 = auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_source; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_sink_0 = auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_sink; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_denied_0 = auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_denied; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_data_0 = auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_data; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_corrupt_0 = auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_sbus_clock_groups_in_member_sbus_1_clock_0 = auto_sbus_clock_groups_in_member_sbus_1_clock; // @[ClockDomain.scala:14:9] wire auto_sbus_clock_groups_in_member_sbus_1_reset_0 = auto_sbus_clock_groups_in_member_sbus_1_reset; // @[ClockDomain.scala:14:9] wire auto_sbus_clock_groups_in_member_sbus_0_clock_0 = auto_sbus_clock_groups_in_member_sbus_0_clock; // @[ClockDomain.scala:14:9] wire auto_sbus_clock_groups_in_member_sbus_0_reset_0 = auto_sbus_clock_groups_in_member_sbus_0_reset; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_spike_tile_tl_master_clock_xing_in_b_bits_opcode = 3'h6; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_b_bits_opcode = 3'h6; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_b_bits_size = 3'h6; // @[ClockDomain.scala:14:9] wire [2:0] fixer_auto_anon_in_1_b_bits_opcode = 3'h6; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_1_b_bits_opcode = 3'h6; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_x1_anonOut_b_bits_opcode = 3'h6; // @[MixedNode.scala:542:17] wire [2:0] fixer_x1_anonIn_b_bits_opcode = 3'h6; // @[MixedNode.scala:551:17] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_b_bits_opcode = 3'h6; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_b_bits_size = 3'h6; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_b_bits_opcode = 3'h6; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_b_bits_size = 3'h6; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_b_bits_opcode = 3'h6; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_b_bits_size = 3'h6; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_b_bits_opcode = 3'h6; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_b_bits_size = 3'h6; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_anonOut_b_bits_opcode = 3'h6; // @[MixedNode.scala:542:17] wire [2:0] coupler_to_bus_named_coh_widget_anonOut_b_bits_size = 3'h6; // @[MixedNode.scala:542:17] wire [2:0] coupler_to_bus_named_coh_widget_anonIn_b_bits_opcode = 3'h6; // @[MixedNode.scala:551:17] wire [2:0] coupler_to_bus_named_coh_widget_anonIn_b_bits_size = 3'h6; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_spike_tile_auto_tl_master_clock_xing_in_b_bits_opcode = 3'h6; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_from_spike_tile_auto_tl_out_b_bits_opcode = 3'h6; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_from_spike_tile_tlOut_b_bits_opcode = 3'h6; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_spike_tile_tlIn_b_bits_opcode = 3'h6; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_spike_tile_no_bufferOut_b_bits_opcode = 3'h6; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_spike_tile_no_bufferIn_b_bits_opcode = 3'h6; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_spike_tile_tlMasterClockXingOut_b_bits_opcode = 3'h6; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_spike_tile_tlMasterClockXingIn_b_bits_opcode = 3'h6; // @[MixedNode.scala:551:17] wire [3:0] auto_coupler_from_spike_tile_tl_master_clock_xing_in_b_bits_size = 4'h6; // @[ClockDomain.scala:14:9] wire [3:0] fixer_auto_anon_in_1_b_bits_size = 4'h6; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_out_1_b_bits_size = 4'h6; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_x1_anonOut_b_bits_size = 4'h6; // @[MixedNode.scala:542:17] wire [3:0] fixer_x1_anonIn_b_bits_size = 4'h6; // @[MixedNode.scala:551:17] wire [3:0] coupler_from_spike_tile_auto_tl_master_clock_xing_in_b_bits_size = 4'h6; // @[LazyModuleImp.scala:138:7] wire [3:0] coupler_from_spike_tile_auto_tl_out_b_bits_size = 4'h6; // @[LazyModuleImp.scala:138:7] wire [3:0] coupler_from_spike_tile_tlOut_b_bits_size = 4'h6; // @[MixedNode.scala:542:17] wire [3:0] coupler_from_spike_tile_tlIn_b_bits_size = 4'h6; // @[MixedNode.scala:551:17] wire [3:0] coupler_from_spike_tile_no_bufferOut_b_bits_size = 4'h6; // @[MixedNode.scala:542:17] wire [3:0] coupler_from_spike_tile_no_bufferIn_b_bits_size = 4'h6; // @[MixedNode.scala:551:17] wire [3:0] coupler_from_spike_tile_tlMasterClockXingOut_b_bits_size = 4'h6; // @[MixedNode.scala:542:17] wire [3:0] coupler_from_spike_tile_tlMasterClockXingIn_b_bits_size = 4'h6; // @[MixedNode.scala:551:17] wire [1:0] auto_coupler_from_spike_tile_tl_master_clock_xing_in_b_bits_source = 2'h1; // @[ClockDomain.scala:14:9] wire [1:0] fixer_auto_anon_in_1_b_bits_source = 2'h1; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_out_1_b_bits_source = 2'h1; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_x1_anonOut_b_bits_source = 2'h1; // @[MixedNode.scala:542:17] wire [1:0] fixer_x1_anonIn_b_bits_source = 2'h1; // @[MixedNode.scala:551:17] wire [1:0] coupler_from_spike_tile_auto_tl_master_clock_xing_in_b_bits_source = 2'h1; // @[LazyModuleImp.scala:138:7] wire [1:0] coupler_from_spike_tile_auto_tl_out_b_bits_source = 2'h1; // @[LazyModuleImp.scala:138:7] wire [1:0] coupler_from_spike_tile_tlOut_b_bits_source = 2'h1; // @[MixedNode.scala:542:17] wire [1:0] coupler_from_spike_tile_tlIn_b_bits_source = 2'h1; // @[MixedNode.scala:551:17] wire [1:0] coupler_from_spike_tile_no_bufferOut_b_bits_source = 2'h1; // @[MixedNode.scala:542:17] wire [1:0] coupler_from_spike_tile_no_bufferIn_b_bits_source = 2'h1; // @[MixedNode.scala:551:17] wire [1:0] coupler_from_spike_tile_tlMasterClockXingOut_b_bits_source = 2'h1; // @[MixedNode.scala:542:17] wire [1:0] coupler_from_spike_tile_tlMasterClockXingIn_b_bits_source = 2'h1; // @[MixedNode.scala:551:17] wire [7:0] auto_coupler_from_spike_tile_tl_master_clock_xing_in_b_bits_mask = 8'hFF; // @[ClockDomain.scala:14:9] wire [7:0] auto_coupler_to_bus_named_coh_widget_anon_out_b_bits_mask = 8'hFF; // @[ClockDomain.scala:14:9] wire [7:0] fixer_auto_anon_in_1_b_bits_mask = 8'hFF; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_auto_anon_out_1_b_bits_mask = 8'hFF; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_x1_anonOut_b_bits_mask = 8'hFF; // @[MixedNode.scala:542:17] wire [7:0] fixer_x1_anonIn_b_bits_mask = 8'hFF; // @[MixedNode.scala:551:17] wire [7:0] coupler_to_bus_named_coh_auto_widget_anon_in_b_bits_mask = 8'hFF; // @[LazyModuleImp.scala:138:7] wire [7:0] coupler_to_bus_named_coh_auto_widget_anon_out_b_bits_mask = 8'hFF; // @[LazyModuleImp.scala:138:7] wire [7:0] coupler_to_bus_named_coh_widget_auto_anon_in_b_bits_mask = 8'hFF; // @[WidthWidget.scala:27:9] wire [7:0] coupler_to_bus_named_coh_widget_auto_anon_out_b_bits_mask = 8'hFF; // @[WidthWidget.scala:27:9] wire [7:0] coupler_to_bus_named_coh_widget_anonOut_b_bits_mask = 8'hFF; // @[MixedNode.scala:542:17] wire [7:0] coupler_to_bus_named_coh_widget_anonIn_b_bits_mask = 8'hFF; // @[MixedNode.scala:551:17] wire [7:0] coupler_from_spike_tile_auto_tl_master_clock_xing_in_b_bits_mask = 8'hFF; // @[LazyModuleImp.scala:138:7] wire [7:0] coupler_from_spike_tile_auto_tl_out_b_bits_mask = 8'hFF; // @[LazyModuleImp.scala:138:7] wire [7:0] coupler_from_spike_tile_tlOut_b_bits_mask = 8'hFF; // @[MixedNode.scala:542:17] wire [7:0] coupler_from_spike_tile_tlIn_b_bits_mask = 8'hFF; // @[MixedNode.scala:551:17] wire [7:0] coupler_from_spike_tile_no_bufferOut_b_bits_mask = 8'hFF; // @[MixedNode.scala:542:17] wire [7:0] coupler_from_spike_tile_no_bufferIn_b_bits_mask = 8'hFF; // @[MixedNode.scala:551:17] wire [7:0] coupler_from_spike_tile_tlMasterClockXingOut_b_bits_mask = 8'hFF; // @[MixedNode.scala:542:17] wire [7:0] coupler_from_spike_tile_tlMasterClockXingIn_b_bits_mask = 8'hFF; // @[MixedNode.scala:551:17] wire [63:0] auto_coupler_from_spike_tile_tl_master_clock_xing_in_b_bits_data = 64'h0; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_bus_named_coh_widget_anon_out_b_bits_data = 64'h0; // @[ClockDomain.scala:14:9] wire [63:0] fixer_auto_anon_in_1_b_bits_data = 64'h0; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_out_1_b_bits_data = 64'h0; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_x1_anonOut_b_bits_data = 64'h0; // @[MixedNode.scala:542:17] wire [63:0] fixer_x1_anonIn_b_bits_data = 64'h0; // @[MixedNode.scala:551:17] wire [63:0] coupler_to_bus_named_coh_auto_widget_anon_in_b_bits_data = 64'h0; // @[LazyModuleImp.scala:138:7] wire [63:0] coupler_to_bus_named_coh_auto_widget_anon_out_b_bits_data = 64'h0; // @[LazyModuleImp.scala:138:7] wire [63:0] coupler_to_bus_named_coh_widget_auto_anon_in_b_bits_data = 64'h0; // @[WidthWidget.scala:27:9] wire [63:0] coupler_to_bus_named_coh_widget_auto_anon_out_b_bits_data = 64'h0; // @[WidthWidget.scala:27:9] wire [63:0] coupler_to_bus_named_coh_widget_anonOut_b_bits_data = 64'h0; // @[MixedNode.scala:542:17] wire [63:0] coupler_to_bus_named_coh_widget_anonIn_b_bits_data = 64'h0; // @[MixedNode.scala:551:17] wire [63:0] coupler_from_spike_tile_auto_tl_master_clock_xing_in_b_bits_data = 64'h0; // @[LazyModuleImp.scala:138:7] wire [63:0] coupler_from_spike_tile_auto_tl_out_b_bits_data = 64'h0; // @[LazyModuleImp.scala:138:7] wire [63:0] coupler_from_spike_tile_tlOut_b_bits_data = 64'h0; // @[MixedNode.scala:542:17] wire [63:0] coupler_from_spike_tile_tlIn_b_bits_data = 64'h0; // @[MixedNode.scala:551:17] wire [63:0] coupler_from_spike_tile_no_bufferOut_b_bits_data = 64'h0; // @[MixedNode.scala:542:17] wire [63:0] coupler_from_spike_tile_no_bufferIn_b_bits_data = 64'h0; // @[MixedNode.scala:551:17] wire [63:0] coupler_from_spike_tile_tlMasterClockXingOut_b_bits_data = 64'h0; // @[MixedNode.scala:542:17] wire [63:0] coupler_from_spike_tile_tlMasterClockXingIn_b_bits_data = 64'h0; // @[MixedNode.scala:551:17] wire auto_coupler_from_spike_tile_tl_master_clock_xing_in_b_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_b_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire sbus_clock_groups_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire sbus_clock_groups_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire sbus_clock_groups__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire clockGroup_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire clockGroup_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire clockGroup__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire broadcast_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire broadcast_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire broadcast__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire fixer_auto_anon_in_1_b_bits_corrupt = 1'h0; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_1_b_bits_corrupt = 1'h0; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonOut_b_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire fixer_x1_anonIn_b_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire fixer__a_notFIFO_T_28 = 1'h0; // @[Mux.scala:30:73] wire fixer_a_noDomain = 1'h0; // @[FIFOFixer.scala:63:29] wire fixer__flight_WIRE_0 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_1 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_2 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_3 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_4 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_5 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_6 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_7 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_8 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_9 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_10 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_11 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_12 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_13 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_14 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_15 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_16 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__a_notFIFO_T_59 = 1'h0; // @[Mux.scala:30:73] wire fixer_a_noDomain_1 = 1'h0; // @[FIFOFixer.scala:63:29] wire fixer__flight_WIRE_1_0 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_1_1 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_1_2 = 1'h0; // @[FIFOFixer.scala:79:35] wire coupler_to_bus_named_coh_auto_widget_anon_in_b_bits_corrupt = 1'h0; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_out_b_bits_corrupt = 1'h0; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_widget_auto_anon_in_b_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_b_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_anonOut_b_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire coupler_to_bus_named_coh_widget_anonIn_b_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire coupler_from_spike_tile_auto_tl_master_clock_xing_in_b_bits_corrupt = 1'h0; // @[LazyModuleImp.scala:138:7] wire coupler_from_spike_tile_auto_tl_out_b_bits_corrupt = 1'h0; // @[LazyModuleImp.scala:138:7] wire coupler_from_spike_tile_tlOut_b_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire coupler_from_spike_tile_tlIn_b_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire coupler_from_spike_tile_no_bufferOut_b_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire coupler_from_spike_tile_no_bufferIn_b_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire coupler_from_spike_tile_tlMasterClockXingOut_b_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire coupler_from_spike_tile_tlMasterClockXingIn_b_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire auto_coupler_from_spike_tile_tl_master_clock_xing_in_e_ready = 1'h1; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_e_ready = 1'h1; // @[ClockDomain.scala:14:9] wire fixer_auto_anon_in_1_e_ready = 1'h1; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_1_e_ready = 1'h1; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonOut_e_ready = 1'h1; // @[MixedNode.scala:542:17] wire fixer_x1_anonIn_e_ready = 1'h1; // @[MixedNode.scala:551:17] wire fixer__a_id_T_4 = 1'h1; // @[Parameters.scala:137:59] wire fixer__anonOut_a_valid_T = 1'h1; // @[FIFOFixer.scala:95:50] wire fixer__anonOut_a_valid_T_1 = 1'h1; // @[FIFOFixer.scala:95:47] wire fixer__anonIn_a_ready_T = 1'h1; // @[FIFOFixer.scala:96:50] wire fixer__anonIn_a_ready_T_1 = 1'h1; // @[FIFOFixer.scala:96:47] wire fixer__a_id_T_9 = 1'h1; // @[Parameters.scala:137:59] wire fixer__anonOut_a_valid_T_3 = 1'h1; // @[FIFOFixer.scala:95:50] wire fixer__anonOut_a_valid_T_4 = 1'h1; // @[FIFOFixer.scala:95:47] wire fixer__anonIn_a_ready_T_3 = 1'h1; // @[FIFOFixer.scala:96:50] wire fixer__anonIn_a_ready_T_4 = 1'h1; // @[FIFOFixer.scala:96:47] wire coupler_to_bus_named_coh_auto_widget_anon_in_e_ready = 1'h1; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_out_e_ready = 1'h1; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_widget_auto_anon_in_e_ready = 1'h1; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_e_ready = 1'h1; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_anonOut_e_ready = 1'h1; // @[MixedNode.scala:542:17] wire coupler_to_bus_named_coh_widget_anonIn_e_ready = 1'h1; // @[MixedNode.scala:551:17] wire coupler_from_spike_tile_auto_tl_master_clock_xing_in_e_ready = 1'h1; // @[LazyModuleImp.scala:138:7] wire coupler_from_spike_tile_auto_tl_out_e_ready = 1'h1; // @[LazyModuleImp.scala:138:7] wire coupler_from_spike_tile_tlOut_e_ready = 1'h1; // @[MixedNode.scala:542:17] wire coupler_from_spike_tile_tlIn_e_ready = 1'h1; // @[MixedNode.scala:551:17] wire coupler_from_spike_tile_no_bufferOut_e_ready = 1'h1; // @[MixedNode.scala:542:17] wire coupler_from_spike_tile_no_bufferIn_e_ready = 1'h1; // @[MixedNode.scala:551:17] wire coupler_from_spike_tile_tlMasterClockXingOut_e_ready = 1'h1; // @[MixedNode.scala:542:17] wire coupler_from_spike_tile_tlMasterClockXingIn_e_ready = 1'h1; // @[MixedNode.scala:551:17] wire [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_b_bits_source = 6'h21; // @[ClockDomain.scala:14:9] wire [5:0] coupler_to_bus_named_coh_auto_widget_anon_in_b_bits_source = 6'h21; // @[LazyModuleImp.scala:138:7] wire [5:0] coupler_to_bus_named_coh_auto_widget_anon_out_b_bits_source = 6'h21; // @[LazyModuleImp.scala:138:7] wire [5:0] coupler_to_bus_named_coh_widget_auto_anon_in_b_bits_source = 6'h21; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_auto_anon_out_b_bits_source = 6'h21; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_anonOut_b_bits_source = 6'h21; // @[MixedNode.scala:542:17] wire [5:0] coupler_to_bus_named_coh_widget_anonIn_b_bits_source = 6'h21; // @[MixedNode.scala:551:17] wire [2:0] fixer__allIDs_FIFOed_T_1 = 3'h7; // @[FIFOFixer.scala:127:48] wire [16:0] fixer__allIDs_FIFOed_T = 17'h1FFFF; // @[FIFOFixer.scala:127:48] wire [32:0] fixer__a_id_T_2 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] fixer__a_id_T_3 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] fixer__a_id_T_7 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] fixer__a_id_T_8 = 33'h0; // @[Parameters.scala:137:46] wire coupler_from_spike_tile_auto_tl_master_clock_xing_in_a_ready; // @[LazyModuleImp.scala:138:7] wire coupler_from_spike_tile_auto_tl_master_clock_xing_in_a_valid = auto_coupler_from_spike_tile_tl_master_clock_xing_in_a_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] coupler_from_spike_tile_auto_tl_master_clock_xing_in_a_bits_opcode = auto_coupler_from_spike_tile_tl_master_clock_xing_in_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] coupler_from_spike_tile_auto_tl_master_clock_xing_in_a_bits_param = auto_coupler_from_spike_tile_tl_master_clock_xing_in_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] coupler_from_spike_tile_auto_tl_master_clock_xing_in_a_bits_size = auto_coupler_from_spike_tile_tl_master_clock_xing_in_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [1:0] coupler_from_spike_tile_auto_tl_master_clock_xing_in_a_bits_source = auto_coupler_from_spike_tile_tl_master_clock_xing_in_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] coupler_from_spike_tile_auto_tl_master_clock_xing_in_a_bits_address = auto_coupler_from_spike_tile_tl_master_clock_xing_in_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] coupler_from_spike_tile_auto_tl_master_clock_xing_in_a_bits_mask = auto_coupler_from_spike_tile_tl_master_clock_xing_in_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] coupler_from_spike_tile_auto_tl_master_clock_xing_in_a_bits_data = auto_coupler_from_spike_tile_tl_master_clock_xing_in_a_bits_data_0; // @[ClockDomain.scala:14:9] wire coupler_from_spike_tile_auto_tl_master_clock_xing_in_a_bits_corrupt = auto_coupler_from_spike_tile_tl_master_clock_xing_in_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire coupler_from_spike_tile_auto_tl_master_clock_xing_in_b_ready = auto_coupler_from_spike_tile_tl_master_clock_xing_in_b_ready_0; // @[ClockDomain.scala:14:9] wire coupler_from_spike_tile_auto_tl_master_clock_xing_in_b_valid; // @[LazyModuleImp.scala:138:7] wire [1:0] coupler_from_spike_tile_auto_tl_master_clock_xing_in_b_bits_param; // @[LazyModuleImp.scala:138:7] wire [31:0] coupler_from_spike_tile_auto_tl_master_clock_xing_in_b_bits_address; // @[LazyModuleImp.scala:138:7] wire coupler_from_spike_tile_auto_tl_master_clock_xing_in_c_ready; // @[LazyModuleImp.scala:138:7] wire coupler_from_spike_tile_auto_tl_master_clock_xing_in_c_valid = auto_coupler_from_spike_tile_tl_master_clock_xing_in_c_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] coupler_from_spike_tile_auto_tl_master_clock_xing_in_c_bits_opcode = auto_coupler_from_spike_tile_tl_master_clock_xing_in_c_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] coupler_from_spike_tile_auto_tl_master_clock_xing_in_c_bits_param = auto_coupler_from_spike_tile_tl_master_clock_xing_in_c_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] coupler_from_spike_tile_auto_tl_master_clock_xing_in_c_bits_size = auto_coupler_from_spike_tile_tl_master_clock_xing_in_c_bits_size_0; // @[ClockDomain.scala:14:9] wire [1:0] coupler_from_spike_tile_auto_tl_master_clock_xing_in_c_bits_source = auto_coupler_from_spike_tile_tl_master_clock_xing_in_c_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] coupler_from_spike_tile_auto_tl_master_clock_xing_in_c_bits_address = auto_coupler_from_spike_tile_tl_master_clock_xing_in_c_bits_address_0; // @[ClockDomain.scala:14:9] wire [63:0] coupler_from_spike_tile_auto_tl_master_clock_xing_in_c_bits_data = auto_coupler_from_spike_tile_tl_master_clock_xing_in_c_bits_data_0; // @[ClockDomain.scala:14:9] wire coupler_from_spike_tile_auto_tl_master_clock_xing_in_c_bits_corrupt = auto_coupler_from_spike_tile_tl_master_clock_xing_in_c_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire coupler_from_spike_tile_auto_tl_master_clock_xing_in_d_ready = auto_coupler_from_spike_tile_tl_master_clock_xing_in_d_ready_0; // @[ClockDomain.scala:14:9] wire coupler_from_spike_tile_auto_tl_master_clock_xing_in_d_valid; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_from_spike_tile_auto_tl_master_clock_xing_in_d_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [1:0] coupler_from_spike_tile_auto_tl_master_clock_xing_in_d_bits_param; // @[LazyModuleImp.scala:138:7] wire [3:0] coupler_from_spike_tile_auto_tl_master_clock_xing_in_d_bits_size; // @[LazyModuleImp.scala:138:7] wire [1:0] coupler_from_spike_tile_auto_tl_master_clock_xing_in_d_bits_source; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_from_spike_tile_auto_tl_master_clock_xing_in_d_bits_sink; // @[LazyModuleImp.scala:138:7] wire coupler_from_spike_tile_auto_tl_master_clock_xing_in_d_bits_denied; // @[LazyModuleImp.scala:138:7] wire [63:0] coupler_from_spike_tile_auto_tl_master_clock_xing_in_d_bits_data; // @[LazyModuleImp.scala:138:7] wire coupler_from_spike_tile_auto_tl_master_clock_xing_in_d_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire coupler_from_spike_tile_auto_tl_master_clock_xing_in_e_valid = auto_coupler_from_spike_tile_tl_master_clock_xing_in_e_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] coupler_from_spike_tile_auto_tl_master_clock_xing_in_e_bits_sink = auto_coupler_from_spike_tile_tl_master_clock_xing_in_e_bits_sink_0; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_auto_widget_anon_out_a_ready = auto_coupler_to_bus_named_coh_widget_anon_out_a_ready_0; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_auto_widget_anon_out_a_valid; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_size; // @[LazyModuleImp.scala:138:7] wire [5:0] coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_source; // @[LazyModuleImp.scala:138:7] wire [31:0] coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_address; // @[LazyModuleImp.scala:138:7] wire [7:0] coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_mask; // @[LazyModuleImp.scala:138:7] wire [63:0] coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_data; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_out_b_ready; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_out_b_valid = auto_coupler_to_bus_named_coh_widget_anon_out_b_valid_0; // @[ClockDomain.scala:14:9] wire [1:0] coupler_to_bus_named_coh_auto_widget_anon_out_b_bits_param = auto_coupler_to_bus_named_coh_widget_anon_out_b_bits_param_0; // @[ClockDomain.scala:14:9] wire [31:0] coupler_to_bus_named_coh_auto_widget_anon_out_b_bits_address = auto_coupler_to_bus_named_coh_widget_anon_out_b_bits_address_0; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_auto_widget_anon_out_c_ready = auto_coupler_to_bus_named_coh_widget_anon_out_c_ready_0; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_auto_widget_anon_out_c_valid; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_c_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_c_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_c_bits_size; // @[LazyModuleImp.scala:138:7] wire [5:0] coupler_to_bus_named_coh_auto_widget_anon_out_c_bits_source; // @[LazyModuleImp.scala:138:7] wire [31:0] coupler_to_bus_named_coh_auto_widget_anon_out_c_bits_address; // @[LazyModuleImp.scala:138:7] wire [63:0] coupler_to_bus_named_coh_auto_widget_anon_out_c_bits_data; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_out_c_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_out_d_ready; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_out_d_valid = auto_coupler_to_bus_named_coh_widget_anon_out_d_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_d_bits_opcode = auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] coupler_to_bus_named_coh_auto_widget_anon_out_d_bits_param = auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_param_0; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_d_bits_size = auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [5:0] coupler_to_bus_named_coh_auto_widget_anon_out_d_bits_source = auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_source_0; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_d_bits_sink = auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_sink_0; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_auto_widget_anon_out_d_bits_denied = auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_denied_0; // @[ClockDomain.scala:14:9] wire [63:0] coupler_to_bus_named_coh_auto_widget_anon_out_d_bits_data = auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_data_0; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_auto_widget_anon_out_d_bits_corrupt = auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_auto_widget_anon_out_e_valid; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_out_e_bits_sink; // @[LazyModuleImp.scala:138:7] wire coupler_from_bus_named_fbus_auto_bus_xing_in_a_ready; // @[LazyModuleImp.scala:138:7] wire coupler_from_bus_named_fbus_auto_bus_xing_in_a_valid = auto_coupler_from_bus_named_fbus_bus_xing_in_a_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] coupler_from_bus_named_fbus_auto_bus_xing_in_a_bits_opcode = auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] coupler_from_bus_named_fbus_auto_bus_xing_in_a_bits_param = auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] coupler_from_bus_named_fbus_auto_bus_xing_in_a_bits_size = auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [4:0] coupler_from_bus_named_fbus_auto_bus_xing_in_a_bits_source = auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] coupler_from_bus_named_fbus_auto_bus_xing_in_a_bits_address = auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] coupler_from_bus_named_fbus_auto_bus_xing_in_a_bits_mask = auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] coupler_from_bus_named_fbus_auto_bus_xing_in_a_bits_data = auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_data_0; // @[ClockDomain.scala:14:9] wire coupler_from_bus_named_fbus_auto_bus_xing_in_a_bits_corrupt = auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire coupler_from_bus_named_fbus_auto_bus_xing_in_d_ready = auto_coupler_from_bus_named_fbus_bus_xing_in_d_ready_0; // @[ClockDomain.scala:14:9] wire coupler_from_bus_named_fbus_auto_bus_xing_in_d_valid; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_from_bus_named_fbus_auto_bus_xing_in_d_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [1:0] coupler_from_bus_named_fbus_auto_bus_xing_in_d_bits_param; // @[LazyModuleImp.scala:138:7] wire [3:0] coupler_from_bus_named_fbus_auto_bus_xing_in_d_bits_size; // @[LazyModuleImp.scala:138:7] wire [4:0] coupler_from_bus_named_fbus_auto_bus_xing_in_d_bits_source; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_from_bus_named_fbus_auto_bus_xing_in_d_bits_sink; // @[LazyModuleImp.scala:138:7] wire coupler_from_bus_named_fbus_auto_bus_xing_in_d_bits_denied; // @[LazyModuleImp.scala:138:7] wire [63:0] coupler_from_bus_named_fbus_auto_bus_xing_in_d_bits_data; // @[LazyModuleImp.scala:138:7] wire coupler_from_bus_named_fbus_auto_bus_xing_in_d_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_cbus_auto_bus_xing_out_a_ready = auto_coupler_to_bus_named_cbus_bus_xing_out_a_ready_0; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_cbus_auto_bus_xing_out_a_valid; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_cbus_auto_bus_xing_out_a_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_cbus_auto_bus_xing_out_a_bits_param; // @[LazyModuleImp.scala:138:7] wire [3:0] coupler_to_bus_named_cbus_auto_bus_xing_out_a_bits_size; // @[LazyModuleImp.scala:138:7] wire [5:0] coupler_to_bus_named_cbus_auto_bus_xing_out_a_bits_source; // @[LazyModuleImp.scala:138:7] wire [28:0] coupler_to_bus_named_cbus_auto_bus_xing_out_a_bits_address; // @[LazyModuleImp.scala:138:7] wire [7:0] coupler_to_bus_named_cbus_auto_bus_xing_out_a_bits_mask; // @[LazyModuleImp.scala:138:7] wire [63:0] coupler_to_bus_named_cbus_auto_bus_xing_out_a_bits_data; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_cbus_auto_bus_xing_out_a_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_cbus_auto_bus_xing_out_d_ready; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_cbus_auto_bus_xing_out_d_valid = auto_coupler_to_bus_named_cbus_bus_xing_out_d_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_cbus_auto_bus_xing_out_d_bits_opcode = auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] coupler_to_bus_named_cbus_auto_bus_xing_out_d_bits_param = auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] coupler_to_bus_named_cbus_auto_bus_xing_out_d_bits_size = auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [5:0] coupler_to_bus_named_cbus_auto_bus_xing_out_d_bits_source = auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_source_0; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_cbus_auto_bus_xing_out_d_bits_sink = auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_sink_0; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_cbus_auto_bus_xing_out_d_bits_denied = auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_denied_0; // @[ClockDomain.scala:14:9] wire [63:0] coupler_to_bus_named_cbus_auto_bus_xing_out_d_bits_data = auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_data_0; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_cbus_auto_bus_xing_out_d_bits_corrupt = auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire sbus_clock_groups_auto_in_member_sbus_1_clock = auto_sbus_clock_groups_in_member_sbus_1_clock_0; // @[ClockGroup.scala:53:9] wire sbus_clock_groups_auto_in_member_sbus_1_reset = auto_sbus_clock_groups_in_member_sbus_1_reset_0; // @[ClockGroup.scala:53:9] wire sbus_clock_groups_auto_in_member_sbus_0_clock = auto_sbus_clock_groups_in_member_sbus_0_clock_0; // @[ClockGroup.scala:53:9] wire sbus_clock_groups_auto_in_member_sbus_0_reset = auto_sbus_clock_groups_in_member_sbus_0_reset_0; // @[ClockGroup.scala:53:9] wire sbus_clock_groups_auto_out_1_member_coh_0_clock; // @[ClockGroup.scala:53:9] wire sbus_clock_groups_auto_out_1_member_coh_0_reset; // @[ClockGroup.scala:53:9] wire auto_coupler_from_spike_tile_tl_master_clock_xing_in_a_ready_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_from_spike_tile_tl_master_clock_xing_in_b_bits_param_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_coupler_from_spike_tile_tl_master_clock_xing_in_b_bits_address_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_spike_tile_tl_master_clock_xing_in_b_valid_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_spike_tile_tl_master_clock_xing_in_c_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_spike_tile_tl_master_clock_xing_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_from_spike_tile_tl_master_clock_xing_in_d_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_from_spike_tile_tl_master_clock_xing_in_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_from_spike_tile_tl_master_clock_xing_in_d_bits_source_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_spike_tile_tl_master_clock_xing_in_d_bits_sink_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_spike_tile_tl_master_clock_xing_in_d_bits_denied_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_from_spike_tile_tl_master_clock_xing_in_d_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_spike_tile_tl_master_clock_xing_in_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_spike_tile_tl_master_clock_xing_in_d_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_a_valid_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_b_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_param_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_size_0; // @[ClockDomain.scala:14:9] wire [5:0] auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_address_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_c_valid_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_d_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_e_bits_sink_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_coh_widget_anon_out_e_valid_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_bus_named_fbus_bus_xing_in_a_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [4:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_source_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_sink_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_denied_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_bus_named_fbus_bus_xing_in_d_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [5:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [28:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_cbus_bus_xing_out_a_valid_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_cbus_bus_xing_out_d_ready_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_2_clock_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_2_reset_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_1_clock_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_1_reset_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_0_clock_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_0_reset_0; // @[ClockDomain.scala:14:9] wire auto_sbus_clock_groups_out_member_coh_0_clock_0; // @[ClockDomain.scala:14:9] wire auto_sbus_clock_groups_out_member_coh_0_reset_0; // @[ClockDomain.scala:14:9] wire clockSinkNodeIn_clock; // @[MixedNode.scala:551:17] wire clockSinkNodeIn_reset; // @[MixedNode.scala:551:17] wire childClock; // @[LazyModuleImp.scala:155:31] wire childReset; // @[LazyModuleImp.scala:158:31] wire sbus_clock_groups_nodeIn_member_sbus_1_clock = sbus_clock_groups_auto_in_member_sbus_1_clock; // @[ClockGroup.scala:53:9] wire sbus_clock_groups_nodeIn_member_sbus_1_reset = sbus_clock_groups_auto_in_member_sbus_1_reset; // @[ClockGroup.scala:53:9] wire sbus_clock_groups_nodeIn_member_sbus_0_clock = sbus_clock_groups_auto_in_member_sbus_0_clock; // @[ClockGroup.scala:53:9] wire sbus_clock_groups_nodeIn_member_sbus_0_reset = sbus_clock_groups_auto_in_member_sbus_0_reset; // @[ClockGroup.scala:53:9] wire sbus_clock_groups_x1_nodeOut_member_coh_0_clock; // @[MixedNode.scala:542:17] assign auto_sbus_clock_groups_out_member_coh_0_clock_0 = sbus_clock_groups_auto_out_1_member_coh_0_clock; // @[ClockGroup.scala:53:9] wire sbus_clock_groups_x1_nodeOut_member_coh_0_reset; // @[MixedNode.scala:542:17] assign auto_sbus_clock_groups_out_member_coh_0_reset_0 = sbus_clock_groups_auto_out_1_member_coh_0_reset; // @[ClockGroup.scala:53:9] wire sbus_clock_groups_nodeOut_member_sbus_0_clock; // @[MixedNode.scala:542:17] wire sbus_clock_groups_nodeOut_member_sbus_0_reset; // @[MixedNode.scala:542:17] wire clockGroup_auto_in_member_sbus_0_clock = sbus_clock_groups_auto_out_0_member_sbus_0_clock; // @[ClockGroup.scala:24:9, :53:9] wire clockGroup_auto_in_member_sbus_0_reset = sbus_clock_groups_auto_out_0_member_sbus_0_reset; // @[ClockGroup.scala:24:9, :53:9] assign sbus_clock_groups_x1_nodeOut_member_coh_0_clock = sbus_clock_groups_nodeIn_member_sbus_1_clock; // @[MixedNode.scala:542:17, :551:17] assign sbus_clock_groups_x1_nodeOut_member_coh_0_reset = sbus_clock_groups_nodeIn_member_sbus_1_reset; // @[MixedNode.scala:542:17, :551:17] assign sbus_clock_groups_nodeOut_member_sbus_0_clock = sbus_clock_groups_nodeIn_member_sbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign sbus_clock_groups_nodeOut_member_sbus_0_reset = sbus_clock_groups_nodeIn_member_sbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign sbus_clock_groups_auto_out_0_member_sbus_0_clock = sbus_clock_groups_nodeOut_member_sbus_0_clock; // @[ClockGroup.scala:53:9] assign sbus_clock_groups_auto_out_0_member_sbus_0_reset = sbus_clock_groups_nodeOut_member_sbus_0_reset; // @[ClockGroup.scala:53:9] assign sbus_clock_groups_auto_out_1_member_coh_0_clock = sbus_clock_groups_x1_nodeOut_member_coh_0_clock; // @[ClockGroup.scala:53:9] assign sbus_clock_groups_auto_out_1_member_coh_0_reset = sbus_clock_groups_x1_nodeOut_member_coh_0_reset; // @[ClockGroup.scala:53:9] wire clockGroup_nodeIn_member_sbus_0_clock = clockGroup_auto_in_member_sbus_0_clock; // @[ClockGroup.scala:24:9] wire clockGroup_nodeOut_clock; // @[MixedNode.scala:542:17] wire clockGroup_nodeIn_member_sbus_0_reset = clockGroup_auto_in_member_sbus_0_reset; // @[ClockGroup.scala:24:9] wire clockGroup_nodeOut_reset; // @[MixedNode.scala:542:17] wire clockGroup_auto_out_clock; // @[ClockGroup.scala:24:9] wire clockGroup_auto_out_reset; // @[ClockGroup.scala:24:9] assign clockGroup_auto_out_clock = clockGroup_nodeOut_clock; // @[ClockGroup.scala:24:9] assign clockGroup_auto_out_reset = clockGroup_nodeOut_reset; // @[ClockGroup.scala:24:9] assign clockGroup_nodeOut_clock = clockGroup_nodeIn_member_sbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign clockGroup_nodeOut_reset = clockGroup_nodeIn_member_sbus_0_reset; // @[MixedNode.scala:542:17, :551:17] wire fixer_x1_anonIn_a_ready; // @[MixedNode.scala:551:17] wire coupler_from_spike_tile_auto_tl_out_a_ready = fixer_auto_anon_in_1_a_ready; // @[FIFOFixer.scala:50:9] wire coupler_from_spike_tile_auto_tl_out_a_valid; // @[LazyModuleImp.scala:138:7] wire fixer_x1_anonIn_a_valid = fixer_auto_anon_in_1_a_valid; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_spike_tile_auto_tl_out_a_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [2:0] fixer_x1_anonIn_a_bits_opcode = fixer_auto_anon_in_1_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_spike_tile_auto_tl_out_a_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] fixer_x1_anonIn_a_bits_param = fixer_auto_anon_in_1_a_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] coupler_from_spike_tile_auto_tl_out_a_bits_size; // @[LazyModuleImp.scala:138:7] wire [3:0] fixer_x1_anonIn_a_bits_size = fixer_auto_anon_in_1_a_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] coupler_from_spike_tile_auto_tl_out_a_bits_source; // @[LazyModuleImp.scala:138:7] wire [1:0] fixer_x1_anonIn_a_bits_source = fixer_auto_anon_in_1_a_bits_source; // @[FIFOFixer.scala:50:9] wire [31:0] coupler_from_spike_tile_auto_tl_out_a_bits_address; // @[LazyModuleImp.scala:138:7] wire [31:0] fixer_x1_anonIn_a_bits_address = fixer_auto_anon_in_1_a_bits_address; // @[FIFOFixer.scala:50:9] wire [7:0] coupler_from_spike_tile_auto_tl_out_a_bits_mask; // @[LazyModuleImp.scala:138:7] wire [7:0] fixer_x1_anonIn_a_bits_mask = fixer_auto_anon_in_1_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [63:0] coupler_from_spike_tile_auto_tl_out_a_bits_data; // @[LazyModuleImp.scala:138:7] wire [63:0] fixer_x1_anonIn_a_bits_data = fixer_auto_anon_in_1_a_bits_data; // @[FIFOFixer.scala:50:9] wire coupler_from_spike_tile_auto_tl_out_a_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire fixer_x1_anonIn_a_bits_corrupt = fixer_auto_anon_in_1_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire coupler_from_spike_tile_auto_tl_out_b_ready; // @[LazyModuleImp.scala:138:7] wire fixer_x1_anonIn_b_ready = fixer_auto_anon_in_1_b_ready; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonIn_b_valid; // @[MixedNode.scala:551:17] wire coupler_from_spike_tile_auto_tl_out_b_valid = fixer_auto_anon_in_1_b_valid; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_x1_anonIn_b_bits_param; // @[MixedNode.scala:551:17] wire [1:0] coupler_from_spike_tile_auto_tl_out_b_bits_param = fixer_auto_anon_in_1_b_bits_param; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_x1_anonIn_b_bits_address; // @[MixedNode.scala:551:17] wire [31:0] coupler_from_spike_tile_auto_tl_out_b_bits_address = fixer_auto_anon_in_1_b_bits_address; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonIn_c_ready; // @[MixedNode.scala:551:17] wire coupler_from_spike_tile_auto_tl_out_c_ready = fixer_auto_anon_in_1_c_ready; // @[FIFOFixer.scala:50:9] wire coupler_from_spike_tile_auto_tl_out_c_valid; // @[LazyModuleImp.scala:138:7] wire fixer_x1_anonIn_c_valid = fixer_auto_anon_in_1_c_valid; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_spike_tile_auto_tl_out_c_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [2:0] fixer_x1_anonIn_c_bits_opcode = fixer_auto_anon_in_1_c_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_spike_tile_auto_tl_out_c_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] fixer_x1_anonIn_c_bits_param = fixer_auto_anon_in_1_c_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] coupler_from_spike_tile_auto_tl_out_c_bits_size; // @[LazyModuleImp.scala:138:7] wire [3:0] fixer_x1_anonIn_c_bits_size = fixer_auto_anon_in_1_c_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] coupler_from_spike_tile_auto_tl_out_c_bits_source; // @[LazyModuleImp.scala:138:7] wire [1:0] fixer_x1_anonIn_c_bits_source = fixer_auto_anon_in_1_c_bits_source; // @[FIFOFixer.scala:50:9] wire [31:0] coupler_from_spike_tile_auto_tl_out_c_bits_address; // @[LazyModuleImp.scala:138:7] wire [31:0] fixer_x1_anonIn_c_bits_address = fixer_auto_anon_in_1_c_bits_address; // @[FIFOFixer.scala:50:9] wire [63:0] coupler_from_spike_tile_auto_tl_out_c_bits_data; // @[LazyModuleImp.scala:138:7] wire [63:0] fixer_x1_anonIn_c_bits_data = fixer_auto_anon_in_1_c_bits_data; // @[FIFOFixer.scala:50:9] wire coupler_from_spike_tile_auto_tl_out_c_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire fixer_x1_anonIn_c_bits_corrupt = fixer_auto_anon_in_1_c_bits_corrupt; // @[FIFOFixer.scala:50:9] wire coupler_from_spike_tile_auto_tl_out_d_ready; // @[LazyModuleImp.scala:138:7] wire fixer_x1_anonIn_d_ready = fixer_auto_anon_in_1_d_ready; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] fixer_x1_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire coupler_from_spike_tile_auto_tl_out_d_valid = fixer_auto_anon_in_1_d_valid; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_x1_anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_spike_tile_auto_tl_out_d_bits_opcode = fixer_auto_anon_in_1_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_x1_anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] coupler_from_spike_tile_auto_tl_out_d_bits_param = fixer_auto_anon_in_1_d_bits_param; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_x1_anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] coupler_from_spike_tile_auto_tl_out_d_bits_size = fixer_auto_anon_in_1_d_bits_size; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_x1_anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire [1:0] coupler_from_spike_tile_auto_tl_out_d_bits_source = fixer_auto_anon_in_1_d_bits_source; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_spike_tile_auto_tl_out_d_bits_sink = fixer_auto_anon_in_1_d_bits_sink; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_x1_anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire coupler_from_spike_tile_auto_tl_out_d_bits_denied = fixer_auto_anon_in_1_d_bits_denied; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] coupler_from_spike_tile_auto_tl_out_d_bits_data = fixer_auto_anon_in_1_d_bits_data; // @[FIFOFixer.scala:50:9] wire coupler_from_spike_tile_auto_tl_out_d_bits_corrupt = fixer_auto_anon_in_1_d_bits_corrupt; // @[FIFOFixer.scala:50:9] wire coupler_from_spike_tile_auto_tl_out_e_valid; // @[LazyModuleImp.scala:138:7] wire fixer_x1_anonIn_e_valid = fixer_auto_anon_in_1_e_valid; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_spike_tile_auto_tl_out_e_bits_sink; // @[LazyModuleImp.scala:138:7] wire fixer_anonIn_a_ready; // @[MixedNode.scala:551:17] wire [2:0] fixer_x1_anonIn_e_bits_sink = fixer_auto_anon_in_1_e_bits_sink; // @[FIFOFixer.scala:50:9] wire coupler_from_bus_named_fbus_auto_widget_anon_out_a_ready = fixer_auto_anon_in_0_a_ready; // @[FIFOFixer.scala:50:9] wire coupler_from_bus_named_fbus_auto_widget_anon_out_a_valid; // @[LazyModuleImp.scala:138:7] wire fixer_anonIn_a_valid = fixer_auto_anon_in_0_a_valid; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_bus_named_fbus_auto_widget_anon_out_a_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [2:0] fixer_anonIn_a_bits_opcode = fixer_auto_anon_in_0_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_bus_named_fbus_auto_widget_anon_out_a_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] fixer_anonIn_a_bits_param = fixer_auto_anon_in_0_a_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] coupler_from_bus_named_fbus_auto_widget_anon_out_a_bits_size; // @[LazyModuleImp.scala:138:7] wire [3:0] fixer_anonIn_a_bits_size = fixer_auto_anon_in_0_a_bits_size; // @[FIFOFixer.scala:50:9] wire [4:0] coupler_from_bus_named_fbus_auto_widget_anon_out_a_bits_source; // @[LazyModuleImp.scala:138:7] wire [4:0] fixer_anonIn_a_bits_source = fixer_auto_anon_in_0_a_bits_source; // @[FIFOFixer.scala:50:9] wire [31:0] coupler_from_bus_named_fbus_auto_widget_anon_out_a_bits_address; // @[LazyModuleImp.scala:138:7] wire [31:0] fixer_anonIn_a_bits_address = fixer_auto_anon_in_0_a_bits_address; // @[FIFOFixer.scala:50:9] wire [7:0] coupler_from_bus_named_fbus_auto_widget_anon_out_a_bits_mask; // @[LazyModuleImp.scala:138:7] wire [7:0] fixer_anonIn_a_bits_mask = fixer_auto_anon_in_0_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [63:0] coupler_from_bus_named_fbus_auto_widget_anon_out_a_bits_data; // @[LazyModuleImp.scala:138:7] wire [63:0] fixer_anonIn_a_bits_data = fixer_auto_anon_in_0_a_bits_data; // @[FIFOFixer.scala:50:9] wire coupler_from_bus_named_fbus_auto_widget_anon_out_a_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire fixer_anonIn_a_bits_corrupt = fixer_auto_anon_in_0_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire coupler_from_bus_named_fbus_auto_widget_anon_out_d_ready; // @[LazyModuleImp.scala:138:7] wire fixer_anonIn_d_ready = fixer_auto_anon_in_0_d_ready; // @[FIFOFixer.scala:50:9] wire fixer_anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] fixer_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire coupler_from_bus_named_fbus_auto_widget_anon_out_d_valid = fixer_auto_anon_in_0_d_valid; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_bus_named_fbus_auto_widget_anon_out_d_bits_opcode = fixer_auto_anon_in_0_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] coupler_from_bus_named_fbus_auto_widget_anon_out_d_bits_param = fixer_auto_anon_in_0_d_bits_param; // @[FIFOFixer.scala:50:9] wire [4:0] fixer_anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] coupler_from_bus_named_fbus_auto_widget_anon_out_d_bits_size = fixer_auto_anon_in_0_d_bits_size; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire [4:0] coupler_from_bus_named_fbus_auto_widget_anon_out_d_bits_source = fixer_auto_anon_in_0_d_bits_source; // @[FIFOFixer.scala:50:9] wire fixer_anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_bus_named_fbus_auto_widget_anon_out_d_bits_sink = fixer_auto_anon_in_0_d_bits_sink; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire coupler_from_bus_named_fbus_auto_widget_anon_out_d_bits_denied = fixer_auto_anon_in_0_d_bits_denied; // @[FIFOFixer.scala:50:9] wire fixer_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] coupler_from_bus_named_fbus_auto_widget_anon_out_d_bits_data = fixer_auto_anon_in_0_d_bits_data; // @[FIFOFixer.scala:50:9] wire coupler_from_bus_named_fbus_auto_widget_anon_out_d_bits_corrupt = fixer_auto_anon_in_0_d_bits_corrupt; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonOut_a_ready = fixer_auto_anon_out_1_a_ready; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] fixer_x1_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] fixer_x1_anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] fixer_x1_anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [1:0] fixer_x1_anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] fixer_x1_anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] fixer_x1_anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] fixer_x1_anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire fixer_x1_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire fixer_x1_anonOut_b_ready; // @[MixedNode.scala:542:17] wire fixer_x1_anonOut_b_valid = fixer_auto_anon_out_1_b_valid; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_x1_anonOut_b_bits_param = fixer_auto_anon_out_1_b_bits_param; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_x1_anonOut_b_bits_address = fixer_auto_anon_out_1_b_bits_address; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonOut_c_ready = fixer_auto_anon_out_1_c_ready; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonOut_c_valid; // @[MixedNode.scala:542:17] wire [2:0] fixer_x1_anonOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] fixer_x1_anonOut_c_bits_param; // @[MixedNode.scala:542:17] wire [3:0] fixer_x1_anonOut_c_bits_size; // @[MixedNode.scala:542:17] wire [1:0] fixer_x1_anonOut_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] fixer_x1_anonOut_c_bits_address; // @[MixedNode.scala:542:17] wire [63:0] fixer_x1_anonOut_c_bits_data; // @[MixedNode.scala:542:17] wire fixer_x1_anonOut_c_bits_corrupt; // @[MixedNode.scala:542:17] wire fixer_x1_anonOut_d_ready; // @[MixedNode.scala:542:17] wire fixer_x1_anonOut_d_valid = fixer_auto_anon_out_1_d_valid; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_x1_anonOut_d_bits_opcode = fixer_auto_anon_out_1_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_x1_anonOut_d_bits_param = fixer_auto_anon_out_1_d_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_x1_anonOut_d_bits_size = fixer_auto_anon_out_1_d_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_x1_anonOut_d_bits_source = fixer_auto_anon_out_1_d_bits_source; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_x1_anonOut_d_bits_sink = fixer_auto_anon_out_1_d_bits_sink; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonOut_d_bits_denied = fixer_auto_anon_out_1_d_bits_denied; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_x1_anonOut_d_bits_data = fixer_auto_anon_out_1_d_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonOut_d_bits_corrupt = fixer_auto_anon_out_1_d_bits_corrupt; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonOut_e_valid; // @[MixedNode.scala:542:17] wire [2:0] fixer_x1_anonOut_e_bits_sink; // @[MixedNode.scala:542:17] wire fixer_anonOut_a_ready = fixer_auto_anon_out_0_a_ready; // @[FIFOFixer.scala:50:9] wire fixer_anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] fixer_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] fixer_anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] fixer_anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [4:0] fixer_anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] fixer_anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] fixer_anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] fixer_anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire fixer_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire fixer_anonOut_d_ready; // @[MixedNode.scala:542:17] wire fixer_anonOut_d_valid = fixer_auto_anon_out_0_d_valid; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_anonOut_d_bits_opcode = fixer_auto_anon_out_0_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_anonOut_d_bits_param = fixer_auto_anon_out_0_d_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_anonOut_d_bits_size = fixer_auto_anon_out_0_d_bits_size; // @[FIFOFixer.scala:50:9] wire [4:0] fixer_anonOut_d_bits_source = fixer_auto_anon_out_0_d_bits_source; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_anonOut_d_bits_sink = fixer_auto_anon_out_0_d_bits_sink; // @[FIFOFixer.scala:50:9] wire fixer_anonOut_d_bits_denied = fixer_auto_anon_out_0_d_bits_denied; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_anonOut_d_bits_data = fixer_auto_anon_out_0_d_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_anonOut_d_bits_corrupt = fixer_auto_anon_out_0_d_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_1_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_1_a_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_out_1_a_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_out_1_a_bits_source; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_auto_anon_out_1_a_bits_address; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_auto_anon_out_1_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_out_1_a_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_1_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_1_a_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_1_b_ready; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_1_c_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_1_c_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_out_1_c_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_out_1_c_bits_source; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_auto_anon_out_1_c_bits_address; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_out_1_c_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_1_c_bits_corrupt; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_1_c_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_1_d_ready; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_1_e_bits_sink; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_1_e_valid; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_0_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_0_a_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_out_0_a_bits_size; // @[FIFOFixer.scala:50:9] wire [4:0] fixer_auto_anon_out_0_a_bits_source; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_auto_anon_out_0_a_bits_address; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_auto_anon_out_0_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_out_0_a_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_0_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_0_a_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_0_d_ready; // @[FIFOFixer.scala:50:9] wire fixer__anonOut_a_valid_T_2; // @[FIFOFixer.scala:95:33] wire fixer__anonIn_a_ready_T_2 = fixer_anonOut_a_ready; // @[FIFOFixer.scala:96:33] assign fixer_auto_anon_out_0_a_valid = fixer_anonOut_a_valid; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_0_a_bits_opcode = fixer_anonOut_a_bits_opcode; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_0_a_bits_param = fixer_anonOut_a_bits_param; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_0_a_bits_size = fixer_anonOut_a_bits_size; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_0_a_bits_source = fixer_anonOut_a_bits_source; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_0_a_bits_address = fixer_anonOut_a_bits_address; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_0_a_bits_mask = fixer_anonOut_a_bits_mask; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_0_a_bits_data = fixer_anonOut_a_bits_data; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_0_a_bits_corrupt = fixer_anonOut_a_bits_corrupt; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_0_d_ready = fixer_anonOut_d_ready; // @[FIFOFixer.scala:50:9] assign fixer_anonIn_d_valid = fixer_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_opcode = fixer_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_param = fixer_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_size = fixer_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_source = fixer_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_sink = fixer_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_denied = fixer_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_data = fixer_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_corrupt = fixer_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire fixer__anonOut_a_valid_T_5; // @[FIFOFixer.scala:95:33] wire fixer__anonIn_a_ready_T_5 = fixer_x1_anonOut_a_ready; // @[FIFOFixer.scala:96:33] assign fixer_auto_anon_out_1_a_valid = fixer_x1_anonOut_a_valid; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_1_a_bits_opcode = fixer_x1_anonOut_a_bits_opcode; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_1_a_bits_param = fixer_x1_anonOut_a_bits_param; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_1_a_bits_size = fixer_x1_anonOut_a_bits_size; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_1_a_bits_source = fixer_x1_anonOut_a_bits_source; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_1_a_bits_address = fixer_x1_anonOut_a_bits_address; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_1_a_bits_mask = fixer_x1_anonOut_a_bits_mask; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_1_a_bits_data = fixer_x1_anonOut_a_bits_data; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_1_a_bits_corrupt = fixer_x1_anonOut_a_bits_corrupt; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_1_b_ready = fixer_x1_anonOut_b_ready; // @[FIFOFixer.scala:50:9] assign fixer_x1_anonIn_b_valid = fixer_x1_anonOut_b_valid; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_b_bits_param = fixer_x1_anonOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_b_bits_address = fixer_x1_anonOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_c_ready = fixer_x1_anonOut_c_ready; // @[MixedNode.scala:542:17, :551:17] assign fixer_auto_anon_out_1_c_valid = fixer_x1_anonOut_c_valid; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_1_c_bits_opcode = fixer_x1_anonOut_c_bits_opcode; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_1_c_bits_param = fixer_x1_anonOut_c_bits_param; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_1_c_bits_size = fixer_x1_anonOut_c_bits_size; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_1_c_bits_source = fixer_x1_anonOut_c_bits_source; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_1_c_bits_address = fixer_x1_anonOut_c_bits_address; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_1_c_bits_data = fixer_x1_anonOut_c_bits_data; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_1_c_bits_corrupt = fixer_x1_anonOut_c_bits_corrupt; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_1_d_ready = fixer_x1_anonOut_d_ready; // @[FIFOFixer.scala:50:9] assign fixer_x1_anonIn_d_valid = fixer_x1_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_d_bits_opcode = fixer_x1_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_d_bits_param = fixer_x1_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_d_bits_size = fixer_x1_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_d_bits_source = fixer_x1_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_d_bits_sink = fixer_x1_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_d_bits_denied = fixer_x1_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_d_bits_data = fixer_x1_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_d_bits_corrupt = fixer_x1_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign fixer_auto_anon_out_1_e_valid = fixer_x1_anonOut_e_valid; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_1_e_bits_sink = fixer_x1_anonOut_e_bits_sink; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_0_a_ready = fixer_anonIn_a_ready; // @[FIFOFixer.scala:50:9] assign fixer__anonOut_a_valid_T_2 = fixer_anonIn_a_valid; // @[FIFOFixer.scala:95:33] assign fixer_anonOut_a_bits_opcode = fixer_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_param = fixer_anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_size = fixer_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_source = fixer_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_address = fixer_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [31:0] fixer__a_notFIFO_T = fixer_anonIn_a_bits_address; // @[Parameters.scala:137:31] wire [31:0] fixer__a_id_T = fixer_anonIn_a_bits_address; // @[Parameters.scala:137:31] assign fixer_anonOut_a_bits_mask = fixer_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_data = fixer_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_corrupt = fixer_anonIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_d_ready = fixer_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign fixer_auto_anon_in_0_d_valid = fixer_anonIn_d_valid; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_0_d_bits_opcode = fixer_anonIn_d_bits_opcode; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_0_d_bits_param = fixer_anonIn_d_bits_param; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_0_d_bits_size = fixer_anonIn_d_bits_size; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_0_d_bits_source = fixer_anonIn_d_bits_source; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_0_d_bits_sink = fixer_anonIn_d_bits_sink; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_0_d_bits_denied = fixer_anonIn_d_bits_denied; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_0_d_bits_data = fixer_anonIn_d_bits_data; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_0_d_bits_corrupt = fixer_anonIn_d_bits_corrupt; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_1_a_ready = fixer_x1_anonIn_a_ready; // @[FIFOFixer.scala:50:9] assign fixer__anonOut_a_valid_T_5 = fixer_x1_anonIn_a_valid; // @[FIFOFixer.scala:95:33] assign fixer_x1_anonOut_a_bits_opcode = fixer_x1_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_a_bits_param = fixer_x1_anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_a_bits_size = fixer_x1_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_a_bits_source = fixer_x1_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_a_bits_address = fixer_x1_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [31:0] fixer__a_notFIFO_T_31 = fixer_x1_anonIn_a_bits_address; // @[Parameters.scala:137:31] wire [31:0] fixer__a_id_T_5 = fixer_x1_anonIn_a_bits_address; // @[Parameters.scala:137:31] assign fixer_x1_anonOut_a_bits_mask = fixer_x1_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_a_bits_data = fixer_x1_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_a_bits_corrupt = fixer_x1_anonIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_b_ready = fixer_x1_anonIn_b_ready; // @[MixedNode.scala:542:17, :551:17] assign fixer_auto_anon_in_1_b_valid = fixer_x1_anonIn_b_valid; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_1_b_bits_param = fixer_x1_anonIn_b_bits_param; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_1_b_bits_address = fixer_x1_anonIn_b_bits_address; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_1_c_ready = fixer_x1_anonIn_c_ready; // @[FIFOFixer.scala:50:9] assign fixer_x1_anonOut_c_valid = fixer_x1_anonIn_c_valid; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_c_bits_opcode = fixer_x1_anonIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_c_bits_param = fixer_x1_anonIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_c_bits_size = fixer_x1_anonIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_c_bits_source = fixer_x1_anonIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_c_bits_address = fixer_x1_anonIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_c_bits_data = fixer_x1_anonIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_c_bits_corrupt = fixer_x1_anonIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_d_ready = fixer_x1_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign fixer_auto_anon_in_1_d_valid = fixer_x1_anonIn_d_valid; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_1_d_bits_opcode = fixer_x1_anonIn_d_bits_opcode; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_1_d_bits_param = fixer_x1_anonIn_d_bits_param; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_1_d_bits_size = fixer_x1_anonIn_d_bits_size; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_1_d_bits_source = fixer_x1_anonIn_d_bits_source; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_1_d_bits_sink = fixer_x1_anonIn_d_bits_sink; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_1_d_bits_denied = fixer_x1_anonIn_d_bits_denied; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_1_d_bits_data = fixer_x1_anonIn_d_bits_data; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_1_d_bits_corrupt = fixer_x1_anonIn_d_bits_corrupt; // @[FIFOFixer.scala:50:9] assign fixer_x1_anonOut_e_valid = fixer_x1_anonIn_e_valid; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_e_bits_sink = fixer_x1_anonIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire [32:0] fixer__a_notFIFO_T_1 = {1'h0, fixer__a_notFIFO_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] fixer__a_notFIFO_T_2 = fixer__a_notFIFO_T_1 & 33'h8C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] fixer__a_notFIFO_T_3 = fixer__a_notFIFO_T_2; // @[Parameters.scala:137:46] wire fixer__a_notFIFO_T_4 = fixer__a_notFIFO_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] fixer__a_notFIFO_T_5 = {fixer_anonIn_a_bits_address[31:17], fixer_anonIn_a_bits_address[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31] wire [32:0] fixer__a_notFIFO_T_6 = {1'h0, fixer__a_notFIFO_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] fixer__a_notFIFO_T_7 = fixer__a_notFIFO_T_6 & 33'h8C011000; // @[Parameters.scala:137:{41,46}] wire [32:0] fixer__a_notFIFO_T_8 = fixer__a_notFIFO_T_7; // @[Parameters.scala:137:46] wire fixer__a_notFIFO_T_9 = fixer__a_notFIFO_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] fixer__a_notFIFO_T_10 = {fixer_anonIn_a_bits_address[31:28], fixer_anonIn_a_bits_address[27:0] ^ 28'hC000000}; // @[Parameters.scala:137:31] wire [32:0] fixer__a_notFIFO_T_11 = {1'h0, fixer__a_notFIFO_T_10}; // @[Parameters.scala:137:{31,41}] wire [32:0] fixer__a_notFIFO_T_12 = fixer__a_notFIFO_T_11 & 33'h8C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] fixer__a_notFIFO_T_13 = fixer__a_notFIFO_T_12; // @[Parameters.scala:137:46] wire fixer__a_notFIFO_T_14 = fixer__a_notFIFO_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}] wire fixer__a_notFIFO_T_15 = fixer__a_notFIFO_T_4 \| fixer__a_notFIFO_T_9; // @[Parameters.scala:629:89] wire fixer__a_notFIFO_T_16 = fixer__a_notFIFO_T_15 \| fixer__a_notFIFO_T_14; // @[Parameters.scala:629:89] wire [31:0] fixer__a_notFIFO_T_17 = {fixer_anonIn_a_bits_address[31:28], fixer_anonIn_a_bits_address[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31] wire [32:0] fixer__a_notFIFO_T_18 = {1'h0, fixer__a_notFIFO_T_17}; // @[Parameters.scala:137:{31,41}] wire [32:0] fixer__a_notFIFO_T_19 = fixer__a_notFIFO_T_18 & 33'h8C010000; // @[Parameters.scala:137:{41,46}] wire [32:0] fixer__a_notFIFO_T_20 = fixer__a_notFIFO_T_19; // @[Parameters.scala:137:46] wire fixer__a_notFIFO_T_21 = fixer__a_notFIFO_T_20 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] fixer__a_notFIFO_T_22 = fixer_anonIn_a_bits_address ^ 32'h80000000; // @[Parameters.scala:137:31] wire [32:0] fixer__a_notFIFO_T_23 = {1'h0, fixer__a_notFIFO_T_22}; // @[Parameters.scala:137:{31,41}] wire [32:0] fixer__a_notFIFO_T_24 = fixer__a_notFIFO_T_23 & 33'h80000000; // @[Parameters.scala:137:{41,46}] wire [32:0] fixer__a_notFIFO_T_25 = fixer__a_notFIFO_T_24; // @[Parameters.scala:137:46] wire fixer__a_notFIFO_T_26 = fixer__a_notFIFO_T_25 == 33'h0; // @[Parameters.scala:137:{46,59}] wire fixer__a_notFIFO_T_27 = fixer__a_notFIFO_T_21 \| fixer__a_notFIFO_T_26; // @[Parameters.scala:629:89] wire fixer__a_notFIFO_T_29 = fixer__a_notFIFO_T_27; // @[Mux.scala:30:73] wire fixer__a_notFIFO_T_30 = fixer__a_notFIFO_T_29; // @[Mux.scala:30:73] wire fixer_a_notFIFO = fixer__a_notFIFO_T_30; // @[Mux.scala:30:73] wire [32:0] fixer__a_id_T_1 = {1'h0, fixer__a_id_T}; // @[Parameters.scala:137:{31,41}] wire fixer__a_first_T = fixer_anonIn_a_ready & fixer_anonIn_a_valid; // @[Decoupled.scala:51:35] wire [26:0] fixer__a_first_beats1_decode_T = 27'hFFF << fixer_anonIn_a_bits_size; // @[package.scala:243:71] wire [11:0] fixer__a_first_beats1_decode_T_1 = fixer__a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] fixer__a_first_beats1_decode_T_2 = ~fixer__a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] fixer_a_first_beats1_decode = fixer__a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire fixer__a_first_beats1_opdata_T = fixer_anonIn_a_bits_opcode[2]; // @[Edges.scala:92:37] wire fixer_a_first_beats1_opdata = ~fixer__a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] fixer_a_first_beats1 = fixer_a_first_beats1_opdata ? fixer_a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] fixer_a_first_counter; // @[Edges.scala:229:27] wire [9:0] fixer__a_first_counter1_T = {1'h0, fixer_a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] fixer_a_first_counter1 = fixer__a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire fixer_a_first = fixer_a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire fixer__a_first_last_T = fixer_a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire fixer__a_first_last_T_1 = fixer_a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire fixer_a_first_last = fixer__a_first_last_T \| fixer__a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire fixer_a_first_done = fixer_a_first_last & fixer__a_first_T; // @[Decoupled.scala:51:35] wire [8:0] fixer__a_first_count_T = ~fixer_a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] fixer_a_first_count = fixer_a_first_beats1 & fixer__a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] fixer__a_first_counter_T = fixer_a_first ? fixer_a_first_beats1 : fixer_a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire fixer__d_first_T = fixer_anonOut_d_ready & fixer_anonOut_d_valid; // @[Decoupled.scala:51:35] wire [26:0] fixer__d_first_beats1_decode_T = 27'hFFF << fixer_anonOut_d_bits_size; // @[package.scala:243:71] wire [11:0] fixer__d_first_beats1_decode_T_1 = fixer__d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] fixer__d_first_beats1_decode_T_2 = ~fixer__d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] fixer_d_first_beats1_decode = fixer__d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire fixer_d_first_beats1_opdata = fixer_anonOut_d_bits_opcode[0]; // @[Edges.scala:106:36] wire [8:0] fixer_d_first_beats1 = fixer_d_first_beats1_opdata ? fixer_d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] fixer_d_first_counter; // @[Edges.scala:229:27] wire [9:0] fixer__d_first_counter1_T = {1'h0, fixer_d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] fixer_d_first_counter1 = fixer__d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire fixer_d_first_first = fixer_d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire fixer__d_first_last_T = fixer_d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire fixer__d_first_last_T_1 = fixer_d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire fixer_d_first_last = fixer__d_first_last_T \| fixer__d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire fixer_d_first_done = fixer_d_first_last & fixer__d_first_T; // @[Decoupled.scala:51:35] wire [8:0] fixer__d_first_count_T = ~fixer_d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] fixer_d_first_count = fixer_d_first_beats1 & fixer__d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] fixer__d_first_counter_T = fixer_d_first_first ? fixer_d_first_beats1 : fixer_d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire fixer__d_first_T_1 = fixer_anonOut_d_bits_opcode != 3'h6; // @[FIFOFixer.scala:75:63] wire fixer_d_first = fixer_d_first_first & fixer__d_first_T_1; // @[FIFOFixer.scala:75:{42,63}] reg fixer_flight_0; // @[FIFOFixer.scala:79:27] reg fixer_flight_1; // @[FIFOFixer.scala:79:27] reg fixer_flight_2; // @[FIFOFixer.scala:79:27] reg fixer_flight_3; // @[FIFOFixer.scala:79:27] reg fixer_flight_4; // @[FIFOFixer.scala:79:27] reg fixer_flight_5; // @[FIFOFixer.scala:79:27] reg fixer_flight_6; // @[FIFOFixer.scala:79:27] reg fixer_flight_7; // @[FIFOFixer.scala:79:27] reg fixer_flight_8; // @[FIFOFixer.scala:79:27] reg fixer_flight_9; // @[FIFOFixer.scala:79:27] reg fixer_flight_10; // @[FIFOFixer.scala:79:27] reg fixer_flight_11; // @[FIFOFixer.scala:79:27] reg fixer_flight_12; // @[FIFOFixer.scala:79:27] reg fixer_flight_13; // @[FIFOFixer.scala:79:27] reg fixer_flight_14; // @[FIFOFixer.scala:79:27] reg fixer_flight_15; // @[FIFOFixer.scala:79:27] reg fixer_flight_16; // @[FIFOFixer.scala:79:27] wire fixer__flight_T = ~fixer_a_notFIFO; // @[Mux.scala:30:73] wire fixer__T_2 = fixer_anonIn_d_ready & fixer_anonIn_d_valid; // @[Decoupled.scala:51:35] assign fixer_anonOut_a_valid = fixer__anonOut_a_valid_T_2; // @[FIFOFixer.scala:95:33] assign fixer_anonIn_a_ready = fixer__anonIn_a_ready_T_2; // @[FIFOFixer.scala:96:33] reg [16:0] fixer_SourceIdFIFOed; // @[FIFOFixer.scala:115:35] wire [16:0] fixer_SourceIdSet; // @[FIFOFixer.scala:116:36] wire [16:0] fixer_SourceIdClear; // @[FIFOFixer.scala:117:38] wire [31:0] fixer__SourceIdSet_T = 32'h1 << fixer_anonIn_a_bits_source; // @[OneHot.scala:58:35] assign fixer_SourceIdSet = fixer_a_first & fixer__a_first_T & ~fixer_a_notFIFO ? fixer__SourceIdSet_T[16:0] : 17'h0; // @[OneHot.scala:58:35] wire [31:0] fixer__SourceIdClear_T = 32'h1 << fixer_anonIn_d_bits_source; // @[OneHot.scala:58:35] assign fixer_SourceIdClear = fixer_d_first & fixer__T_2 ? fixer__SourceIdClear_T[16:0] : 17'h0; // @[OneHot.scala:58:35] wire [16:0] fixer__SourceIdFIFOed_T = fixer_SourceIdFIFOed \| fixer_SourceIdSet; // @[FIFOFixer.scala:115:35, :116:36, :126:40] wire fixer_allIDs_FIFOed = &fixer_SourceIdFIFOed; // @[FIFOFixer.scala:115:35, :127:41] wire [32:0] fixer__a_notFIFO_T_32 = {1'h0, fixer__a_notFIFO_T_31}; // @[Parameters.scala:137:{31,41}] wire [32:0] fixer__a_notFIFO_T_33 = fixer__a_notFIFO_T_32 & 33'h8C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] fixer__a_notFIFO_T_34 = fixer__a_notFIFO_T_33; // @[Parameters.scala:137:46] wire fixer__a_notFIFO_T_35 = fixer__a_notFIFO_T_34 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] fixer__a_notFIFO_T_36 = {fixer_x1_anonIn_a_bits_address[31:17], fixer_x1_anonIn_a_bits_address[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31] wire [32:0] fixer__a_notFIFO_T_37 = {1'h0, fixer__a_notFIFO_T_36}; // @[Parameters.scala:137:{31,41}] wire [32:0] fixer__a_notFIFO_T_38 = fixer__a_notFIFO_T_37 & 33'h8C011000; // @[Parameters.scala:137:{41,46}] wire [32:0] fixer__a_notFIFO_T_39 = fixer__a_notFIFO_T_38; // @[Parameters.scala:137:46] wire fixer__a_notFIFO_T_40 = fixer__a_notFIFO_T_39 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] fixer__a_notFIFO_T_41 = {fixer_x1_anonIn_a_bits_address[31:28], fixer_x1_anonIn_a_bits_address[27:0] ^ 28'hC000000}; // @[Parameters.scala:137:31] wire [32:0] fixer__a_notFIFO_T_42 = {1'h0, fixer__a_notFIFO_T_41}; // @[Parameters.scala:137:{31,41}] wire [32:0] fixer__a_notFIFO_T_43 = fixer__a_notFIFO_T_42 & 33'h8C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] fixer__a_notFIFO_T_44 = fixer__a_notFIFO_T_43; // @[Parameters.scala:137:46] wire fixer__a_notFIFO_T_45 = fixer__a_notFIFO_T_44 == 33'h0; // @[Parameters.scala:137:{46,59}] wire fixer__a_notFIFO_T_46 = fixer__a_notFIFO_T_35 \| fixer__a_notFIFO_T_40; // @[Parameters.scala:629:89] wire fixer__a_notFIFO_T_47 = fixer__a_notFIFO_T_46 \| fixer__a_notFIFO_T_45; // @[Parameters.scala:629:89] wire [31:0] fixer__a_notFIFO_T_48 = {fixer_x1_anonIn_a_bits_address[31:28], fixer_x1_anonIn_a_bits_address[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31] wire [32:0] fixer__a_notFIFO_T_49 = {1'h0, fixer__a_notFIFO_T_48}; // @[Parameters.scala:137:{31,41}] wire [32:0] fixer__a_notFIFO_T_50 = fixer__a_notFIFO_T_49 & 33'h8C010000; // @[Parameters.scala:137:{41,46}] wire [32:0] fixer__a_notFIFO_T_51 = fixer__a_notFIFO_T_50; // @[Parameters.scala:137:46] wire fixer__a_notFIFO_T_52 = fixer__a_notFIFO_T_51 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] fixer__a_notFIFO_T_53 = fixer_x1_anonIn_a_bits_address ^ 32'h80000000; // @[Parameters.scala:137:31] wire [32:0] fixer__a_notFIFO_T_54 = {1'h0, fixer__a_notFIFO_T_53}; // @[Parameters.scala:137:{31,41}] wire [32:0] fixer__a_notFIFO_T_55 = fixer__a_notFIFO_T_54 & 33'h80000000; // @[Parameters.scala:137:{41,46}] wire [32:0] fixer__a_notFIFO_T_56 = fixer__a_notFIFO_T_55; // @[Parameters.scala:137:46] wire fixer__a_notFIFO_T_57 = fixer__a_notFIFO_T_56 == 33'h0; // @[Parameters.scala:137:{46,59}] wire fixer__a_notFIFO_T_58 = fixer__a_notFIFO_T_52 \| fixer__a_notFIFO_T_57; // @[Parameters.scala:629:89] wire fixer__a_notFIFO_T_60 = fixer__a_notFIFO_T_58; // @[Mux.scala:30:73] wire fixer__a_notFIFO_T_61 = fixer__a_notFIFO_T_60; // @[Mux.scala:30:73] wire fixer_a_notFIFO_1 = fixer__a_notFIFO_T_61; // @[Mux.scala:30:73] wire [32:0] fixer__a_id_T_6 = {1'h0, fixer__a_id_T_5}; // @[Parameters.scala:137:{31,41}] wire fixer__a_first_T_1 = fixer_x1_anonIn_a_ready & fixer_x1_anonIn_a_valid; // @[Decoupled.scala:51:35] wire [26:0] fixer__a_first_beats1_decode_T_3 = 27'hFFF << fixer_x1_anonIn_a_bits_size; // @[package.scala:243:71] wire [11:0] fixer__a_first_beats1_decode_T_4 = fixer__a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] fixer__a_first_beats1_decode_T_5 = ~fixer__a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] fixer_a_first_beats1_decode_1 = fixer__a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire fixer__a_first_beats1_opdata_T_1 = fixer_x1_anonIn_a_bits_opcode[2]; // @[Edges.scala:92:37] wire fixer_a_first_beats1_opdata_1 = ~fixer__a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] fixer_a_first_beats1_1 = fixer_a_first_beats1_opdata_1 ? fixer_a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] fixer_a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] fixer__a_first_counter1_T_1 = {1'h0, fixer_a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] fixer_a_first_counter1_1 = fixer__a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire fixer_a_first_1 = fixer_a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire fixer__a_first_last_T_2 = fixer_a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire fixer__a_first_last_T_3 = fixer_a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire fixer_a_first_last_1 = fixer__a_first_last_T_2 \| fixer__a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire fixer_a_first_done_1 = fixer_a_first_last_1 & fixer__a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] fixer__a_first_count_T_1 = ~fixer_a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] fixer_a_first_count_1 = fixer_a_first_beats1_1 & fixer__a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] fixer__a_first_counter_T_1 = fixer_a_first_1 ? fixer_a_first_beats1_1 : fixer_a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire fixer__d_first_T_2 = fixer_x1_anonOut_d_ready & fixer_x1_anonOut_d_valid; // @[Decoupled.scala:51:35] wire [26:0] fixer__d_first_beats1_decode_T_3 = 27'hFFF << fixer_x1_anonOut_d_bits_size; // @[package.scala:243:71] wire [11:0] fixer__d_first_beats1_decode_T_4 = fixer__d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] fixer__d_first_beats1_decode_T_5 = ~fixer__d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] fixer_d_first_beats1_decode_1 = fixer__d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire fixer_d_first_beats1_opdata_1 = fixer_x1_anonOut_d_bits_opcode[0]; // @[Edges.scala:106:36] wire [8:0] fixer_d_first_beats1_1 = fixer_d_first_beats1_opdata_1 ? fixer_d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] fixer_d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] fixer__d_first_counter1_T_1 = {1'h0, fixer_d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] fixer_d_first_counter1_1 = fixer__d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire fixer_d_first_first_1 = fixer_d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire fixer__d_first_last_T_2 = fixer_d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire fixer__d_first_last_T_3 = fixer_d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire fixer_d_first_last_1 = fixer__d_first_last_T_2 \| fixer__d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire fixer_d_first_done_1 = fixer_d_first_last_1 & fixer__d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] fixer__d_first_count_T_1 = ~fixer_d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] fixer_d_first_count_1 = fixer_d_first_beats1_1 & fixer__d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] fixer__d_first_counter_T_1 = fixer_d_first_first_1 ? fixer_d_first_beats1_1 : fixer_d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire fixer__d_first_T_3 = fixer_x1_anonOut_d_bits_opcode != 3'h6; // @[FIFOFixer.scala:75:63] wire fixer_d_first_1 = fixer_d_first_first_1 & fixer__d_first_T_3; // @[FIFOFixer.scala:75:{42,63}] reg fixer_flight_1_0; // @[FIFOFixer.scala:79:27] reg fixer_flight_1_1; // @[FIFOFixer.scala:79:27] reg fixer_flight_1_2; // @[FIFOFixer.scala:79:27] wire fixer__flight_T_1 = ~fixer_a_notFIFO_1; // @[Mux.scala:30:73] wire fixer__T_32 = fixer_x1_anonIn_d_ready & fixer_x1_anonIn_d_valid; // @[Decoupled.scala:51:35] assign fixer_x1_anonOut_a_valid = fixer__anonOut_a_valid_T_5; // @[FIFOFixer.scala:95:33] assign fixer_x1_anonIn_a_ready = fixer__anonIn_a_ready_T_5; // @[FIFOFixer.scala:96:33] reg [2:0] fixer_SourceIdFIFOed_1; // @[FIFOFixer.scala:115:35] wire [2:0] fixer_SourceIdSet_1; // @[FIFOFixer.scala:116:36] wire [2:0] fixer_SourceIdClear_1; // @[FIFOFixer.scala:117:38] wire [3:0] fixer__SourceIdSet_T_1 = 4'h1 << fixer_x1_anonIn_a_bits_source; // @[OneHot.scala:58:35] assign fixer_SourceIdSet_1 = fixer_a_first_1 & fixer__a_first_T_1 & ~fixer_a_notFIFO_1 ? fixer__SourceIdSet_T_1[2:0] : 3'h0; // @[OneHot.scala:58:35] wire [3:0] fixer__SourceIdClear_T_1 = 4'h1 << fixer_x1_anonIn_d_bits_source; // @[OneHot.scala:58:35] assign fixer_SourceIdClear_1 = fixer_d_first_1 & fixer__T_32 ? fixer__SourceIdClear_T_1[2:0] : 3'h0; // @[OneHot.scala:58:35] wire [2:0] fixer__SourceIdFIFOed_T_1 = fixer_SourceIdFIFOed_1 \| fixer_SourceIdSet_1; // @[FIFOFixer.scala:115:35, :116:36, :126:40] wire fixer_allIDs_FIFOed_1 = &fixer_SourceIdFIFOed_1; // @[FIFOFixer.scala:115:35, :127:41] wire coupler_to_bus_named_cbus_widget_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_cbus_widget_auto_anon_in_a_valid = coupler_to_bus_named_cbus_auto_widget_anon_in_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_cbus_widget_auto_anon_in_a_bits_opcode = coupler_to_bus_named_cbus_auto_widget_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_cbus_widget_auto_anon_in_a_bits_param = coupler_to_bus_named_cbus_auto_widget_anon_in_a_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] coupler_to_bus_named_cbus_widget_auto_anon_in_a_bits_size = coupler_to_bus_named_cbus_auto_widget_anon_in_a_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_cbus_widget_auto_anon_in_a_bits_source = coupler_to_bus_named_cbus_auto_widget_anon_in_a_bits_source; // @[WidthWidget.scala:27:9] wire [28:0] coupler_to_bus_named_cbus_widget_auto_anon_in_a_bits_address = coupler_to_bus_named_cbus_auto_widget_anon_in_a_bits_address; // @[WidthWidget.scala:27:9] wire [7:0] coupler_to_bus_named_cbus_widget_auto_anon_in_a_bits_mask = coupler_to_bus_named_cbus_auto_widget_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9] wire [63:0] coupler_to_bus_named_cbus_widget_auto_anon_in_a_bits_data = coupler_to_bus_named_cbus_auto_widget_anon_in_a_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_cbus_widget_auto_anon_in_a_bits_corrupt = coupler_to_bus_named_cbus_auto_widget_anon_in_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_cbus_widget_auto_anon_in_d_ready = coupler_to_bus_named_cbus_auto_widget_anon_in_d_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_cbus_widget_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_cbus_widget_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_cbus_widget_auto_anon_in_d_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] coupler_to_bus_named_cbus_widget_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_cbus_widget_auto_anon_in_d_bits_source; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_cbus_widget_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_cbus_widget_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9] wire [63:0] coupler_to_bus_named_cbus_widget_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_cbus_widget_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_cbus_bus_xingOut_a_ready = coupler_to_bus_named_cbus_auto_bus_xing_out_a_ready; // @[MixedNode.scala:542:17] wire coupler_to_bus_named_cbus_bus_xingOut_a_valid; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_cbus_bus_xing_out_a_valid_0 = coupler_to_bus_named_cbus_auto_bus_xing_out_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_cbus_bus_xingOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_opcode_0 = coupler_to_bus_named_cbus_auto_bus_xing_out_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_cbus_bus_xingOut_a_bits_param; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_param_0 = coupler_to_bus_named_cbus_auto_bus_xing_out_a_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] coupler_to_bus_named_cbus_bus_xingOut_a_bits_size; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_size_0 = coupler_to_bus_named_cbus_auto_bus_xing_out_a_bits_size; // @[ClockDomain.scala:14:9] wire [5:0] coupler_to_bus_named_cbus_bus_xingOut_a_bits_source; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_source_0 = coupler_to_bus_named_cbus_auto_bus_xing_out_a_bits_source; // @[ClockDomain.scala:14:9] wire [28:0] coupler_to_bus_named_cbus_bus_xingOut_a_bits_address; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_address_0 = coupler_to_bus_named_cbus_auto_bus_xing_out_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] coupler_to_bus_named_cbus_bus_xingOut_a_bits_mask; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_mask_0 = coupler_to_bus_named_cbus_auto_bus_xing_out_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] coupler_to_bus_named_cbus_bus_xingOut_a_bits_data; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_data_0 = coupler_to_bus_named_cbus_auto_bus_xing_out_a_bits_data; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_cbus_bus_xingOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_corrupt_0 = coupler_to_bus_named_cbus_auto_bus_xing_out_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_cbus_bus_xingOut_d_ready; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_cbus_bus_xing_out_d_ready_0 = coupler_to_bus_named_cbus_auto_bus_xing_out_d_ready; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_cbus_bus_xingOut_d_valid = coupler_to_bus_named_cbus_auto_bus_xing_out_d_valid; // @[MixedNode.scala:542:17] wire [2:0] coupler_to_bus_named_cbus_bus_xingOut_d_bits_opcode = coupler_to_bus_named_cbus_auto_bus_xing_out_d_bits_opcode; // @[MixedNode.scala:542:17] wire [1:0] coupler_to_bus_named_cbus_bus_xingOut_d_bits_param = coupler_to_bus_named_cbus_auto_bus_xing_out_d_bits_param; // @[MixedNode.scala:542:17] wire [3:0] coupler_to_bus_named_cbus_bus_xingOut_d_bits_size = coupler_to_bus_named_cbus_auto_bus_xing_out_d_bits_size; // @[MixedNode.scala:542:17] wire [5:0] coupler_to_bus_named_cbus_bus_xingOut_d_bits_source = coupler_to_bus_named_cbus_auto_bus_xing_out_d_bits_source; // @[MixedNode.scala:542:17] wire coupler_to_bus_named_cbus_bus_xingOut_d_bits_sink = coupler_to_bus_named_cbus_auto_bus_xing_out_d_bits_sink; // @[MixedNode.scala:542:17] wire coupler_to_bus_named_cbus_bus_xingOut_d_bits_denied = coupler_to_bus_named_cbus_auto_bus_xing_out_d_bits_denied; // @[MixedNode.scala:542:17] wire [63:0] coupler_to_bus_named_cbus_bus_xingOut_d_bits_data = coupler_to_bus_named_cbus_auto_bus_xing_out_d_bits_data; // @[MixedNode.scala:542:17] wire coupler_to_bus_named_cbus_bus_xingOut_d_bits_corrupt = coupler_to_bus_named_cbus_auto_bus_xing_out_d_bits_corrupt; // @[MixedNode.scala:542:17] wire coupler_to_bus_named_cbus_auto_widget_anon_in_a_ready; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [1:0] coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_param; // @[LazyModuleImp.scala:138:7] wire [3:0] coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_size; // @[LazyModuleImp.scala:138:7] wire [5:0] coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_source; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_sink; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_denied; // @[LazyModuleImp.scala:138:7] wire [63:0] coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_data; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_cbus_auto_widget_anon_in_d_valid; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_cbus_widget_anonIn_a_ready; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_cbus_auto_widget_anon_in_a_ready = coupler_to_bus_named_cbus_widget_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_cbus_widget_anonIn_a_valid = coupler_to_bus_named_cbus_widget_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_cbus_widget_anonIn_a_bits_opcode = coupler_to_bus_named_cbus_widget_auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_cbus_widget_anonIn_a_bits_param = coupler_to_bus_named_cbus_widget_auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] coupler_to_bus_named_cbus_widget_anonIn_a_bits_size = coupler_to_bus_named_cbus_widget_auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_cbus_widget_anonIn_a_bits_source = coupler_to_bus_named_cbus_widget_auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9] wire [28:0] coupler_to_bus_named_cbus_widget_anonIn_a_bits_address = coupler_to_bus_named_cbus_widget_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9] wire [7:0] coupler_to_bus_named_cbus_widget_anonIn_a_bits_mask = coupler_to_bus_named_cbus_widget_auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9] wire [63:0] coupler_to_bus_named_cbus_widget_anonIn_a_bits_data = coupler_to_bus_named_cbus_widget_auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_cbus_widget_anonIn_a_bits_corrupt = coupler_to_bus_named_cbus_widget_auto_anon_in_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_cbus_widget_anonIn_d_ready = coupler_to_bus_named_cbus_widget_auto_anon_in_d_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_cbus_widget_anonIn_d_valid; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_cbus_auto_widget_anon_in_d_valid = coupler_to_bus_named_cbus_widget_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_cbus_widget_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_opcode = coupler_to_bus_named_cbus_widget_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_cbus_widget_anonIn_d_bits_param; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_param = coupler_to_bus_named_cbus_widget_auto_anon_in_d_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] coupler_to_bus_named_cbus_widget_anonIn_d_bits_size; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_size = coupler_to_bus_named_cbus_widget_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_cbus_widget_anonIn_d_bits_source; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_source = coupler_to_bus_named_cbus_widget_auto_anon_in_d_bits_source; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_cbus_widget_anonIn_d_bits_sink; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_sink = coupler_to_bus_named_cbus_widget_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_cbus_widget_anonIn_d_bits_denied; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_denied = coupler_to_bus_named_cbus_widget_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9] wire [63:0] coupler_to_bus_named_cbus_widget_anonIn_d_bits_data; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_data = coupler_to_bus_named_cbus_widget_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_cbus_widget_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_corrupt = coupler_to_bus_named_cbus_widget_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_cbus_bus_xingIn_a_ready; // @[MixedNode.scala:551:17] wire coupler_to_bus_named_cbus_widget_anonOut_a_ready = coupler_to_bus_named_cbus_widget_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_cbus_widget_anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] coupler_to_bus_named_cbus_widget_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire coupler_to_bus_named_cbus_bus_xingIn_a_valid = coupler_to_bus_named_cbus_widget_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_cbus_widget_anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] coupler_to_bus_named_cbus_bus_xingIn_a_bits_opcode = coupler_to_bus_named_cbus_widget_auto_anon_out_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [3:0] coupler_to_bus_named_cbus_widget_anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [2:0] coupler_to_bus_named_cbus_bus_xingIn_a_bits_param = coupler_to_bus_named_cbus_widget_auto_anon_out_a_bits_param; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_cbus_widget_anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [3:0] coupler_to_bus_named_cbus_bus_xingIn_a_bits_size = coupler_to_bus_named_cbus_widget_auto_anon_out_a_bits_size; // @[WidthWidget.scala:27:9] wire [28:0] coupler_to_bus_named_cbus_widget_anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [5:0] coupler_to_bus_named_cbus_bus_xingIn_a_bits_source = coupler_to_bus_named_cbus_widget_auto_anon_out_a_bits_source; // @[WidthWidget.scala:27:9] wire [7:0] coupler_to_bus_named_cbus_widget_anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [28:0] coupler_to_bus_named_cbus_bus_xingIn_a_bits_address = coupler_to_bus_named_cbus_widget_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9] wire [63:0] coupler_to_bus_named_cbus_widget_anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire [7:0] coupler_to_bus_named_cbus_bus_xingIn_a_bits_mask = coupler_to_bus_named_cbus_widget_auto_anon_out_a_bits_mask; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_cbus_widget_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire [63:0] coupler_to_bus_named_cbus_bus_xingIn_a_bits_data = coupler_to_bus_named_cbus_widget_auto_anon_out_a_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_cbus_widget_anonOut_d_ready; // @[MixedNode.scala:542:17] wire coupler_to_bus_named_cbus_bus_xingIn_a_bits_corrupt = coupler_to_bus_named_cbus_widget_auto_anon_out_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_cbus_bus_xingIn_d_ready = coupler_to_bus_named_cbus_widget_auto_anon_out_d_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_cbus_bus_xingIn_d_valid; // @[MixedNode.scala:551:17] wire coupler_to_bus_named_cbus_widget_anonOut_d_valid = coupler_to_bus_named_cbus_widget_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_cbus_bus_xingIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] coupler_to_bus_named_cbus_widget_anonOut_d_bits_opcode = coupler_to_bus_named_cbus_widget_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_cbus_bus_xingIn_d_bits_param; // @[MixedNode.scala:551:17] wire [1:0] coupler_to_bus_named_cbus_widget_anonOut_d_bits_param = coupler_to_bus_named_cbus_widget_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] coupler_to_bus_named_cbus_bus_xingIn_d_bits_size; // @[MixedNode.scala:551:17] wire [3:0] coupler_to_bus_named_cbus_widget_anonOut_d_bits_size = coupler_to_bus_named_cbus_widget_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_cbus_bus_xingIn_d_bits_source; // @[MixedNode.scala:551:17] wire [5:0] coupler_to_bus_named_cbus_widget_anonOut_d_bits_source = coupler_to_bus_named_cbus_widget_auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_cbus_bus_xingIn_d_bits_sink; // @[MixedNode.scala:551:17] wire coupler_to_bus_named_cbus_widget_anonOut_d_bits_sink = coupler_to_bus_named_cbus_widget_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_cbus_bus_xingIn_d_bits_denied; // @[MixedNode.scala:551:17] wire coupler_to_bus_named_cbus_widget_anonOut_d_bits_denied = coupler_to_bus_named_cbus_widget_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9] wire [63:0] coupler_to_bus_named_cbus_bus_xingIn_d_bits_data; // @[MixedNode.scala:551:17] wire [63:0] coupler_to_bus_named_cbus_widget_anonOut_d_bits_data = coupler_to_bus_named_cbus_widget_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_cbus_bus_xingIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire coupler_to_bus_named_cbus_widget_anonOut_d_bits_corrupt = coupler_to_bus_named_cbus_widget_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_cbus_widget_anonIn_a_ready = coupler_to_bus_named_cbus_widget_anonOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_cbus_widget_auto_anon_out_a_valid = coupler_to_bus_named_cbus_widget_anonOut_a_valid; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_cbus_widget_auto_anon_out_a_bits_opcode = coupler_to_bus_named_cbus_widget_anonOut_a_bits_opcode; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_cbus_widget_auto_anon_out_a_bits_param = coupler_to_bus_named_cbus_widget_anonOut_a_bits_param; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_cbus_widget_auto_anon_out_a_bits_size = coupler_to_bus_named_cbus_widget_anonOut_a_bits_size; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_cbus_widget_auto_anon_out_a_bits_source = coupler_to_bus_named_cbus_widget_anonOut_a_bits_source; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_cbus_widget_auto_anon_out_a_bits_address = coupler_to_bus_named_cbus_widget_anonOut_a_bits_address; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_cbus_widget_auto_anon_out_a_bits_mask = coupler_to_bus_named_cbus_widget_anonOut_a_bits_mask; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_cbus_widget_auto_anon_out_a_bits_data = coupler_to_bus_named_cbus_widget_anonOut_a_bits_data; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_cbus_widget_auto_anon_out_a_bits_corrupt = coupler_to_bus_named_cbus_widget_anonOut_a_bits_corrupt; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_cbus_widget_auto_anon_out_d_ready = coupler_to_bus_named_cbus_widget_anonOut_d_ready; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_cbus_widget_anonIn_d_valid = coupler_to_bus_named_cbus_widget_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_cbus_widget_anonIn_d_bits_opcode = coupler_to_bus_named_cbus_widget_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_cbus_widget_anonIn_d_bits_param = coupler_to_bus_named_cbus_widget_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_cbus_widget_anonIn_d_bits_size = coupler_to_bus_named_cbus_widget_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_cbus_widget_anonIn_d_bits_source = coupler_to_bus_named_cbus_widget_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_cbus_widget_anonIn_d_bits_sink = coupler_to_bus_named_cbus_widget_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_cbus_widget_anonIn_d_bits_denied = coupler_to_bus_named_cbus_widget_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_cbus_widget_anonIn_d_bits_data = coupler_to_bus_named_cbus_widget_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_cbus_widget_anonIn_d_bits_corrupt = coupler_to_bus_named_cbus_widget_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_cbus_widget_auto_anon_in_a_ready = coupler_to_bus_named_cbus_widget_anonIn_a_ready; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_cbus_widget_anonOut_a_valid = coupler_to_bus_named_cbus_widget_anonIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_cbus_widget_anonOut_a_bits_opcode = coupler_to_bus_named_cbus_widget_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_cbus_widget_anonOut_a_bits_param = coupler_to_bus_named_cbus_widget_anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_cbus_widget_anonOut_a_bits_size = coupler_to_bus_named_cbus_widget_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_cbus_widget_anonOut_a_bits_source = coupler_to_bus_named_cbus_widget_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_cbus_widget_anonOut_a_bits_address = coupler_to_bus_named_cbus_widget_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_cbus_widget_anonOut_a_bits_mask = coupler_to_bus_named_cbus_widget_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_cbus_widget_anonOut_a_bits_data = coupler_to_bus_named_cbus_widget_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_cbus_widget_anonOut_a_bits_corrupt = coupler_to_bus_named_cbus_widget_anonIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_cbus_widget_anonOut_d_ready = coupler_to_bus_named_cbus_widget_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_cbus_widget_auto_anon_in_d_valid = coupler_to_bus_named_cbus_widget_anonIn_d_valid; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_cbus_widget_auto_anon_in_d_bits_opcode = coupler_to_bus_named_cbus_widget_anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_cbus_widget_auto_anon_in_d_bits_param = coupler_to_bus_named_cbus_widget_anonIn_d_bits_param; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_cbus_widget_auto_anon_in_d_bits_size = coupler_to_bus_named_cbus_widget_anonIn_d_bits_size; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_cbus_widget_auto_anon_in_d_bits_source = coupler_to_bus_named_cbus_widget_anonIn_d_bits_source; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_cbus_widget_auto_anon_in_d_bits_sink = coupler_to_bus_named_cbus_widget_anonIn_d_bits_sink; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_cbus_widget_auto_anon_in_d_bits_denied = coupler_to_bus_named_cbus_widget_anonIn_d_bits_denied; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_cbus_widget_auto_anon_in_d_bits_data = coupler_to_bus_named_cbus_widget_anonIn_d_bits_data; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_cbus_widget_auto_anon_in_d_bits_corrupt = coupler_to_bus_named_cbus_widget_anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_cbus_bus_xingIn_a_ready = coupler_to_bus_named_cbus_bus_xingOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_cbus_auto_bus_xing_out_a_valid = coupler_to_bus_named_cbus_bus_xingOut_a_valid; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_cbus_auto_bus_xing_out_a_bits_opcode = coupler_to_bus_named_cbus_bus_xingOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_cbus_auto_bus_xing_out_a_bits_param = coupler_to_bus_named_cbus_bus_xingOut_a_bits_param; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_cbus_auto_bus_xing_out_a_bits_size = coupler_to_bus_named_cbus_bus_xingOut_a_bits_size; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_cbus_auto_bus_xing_out_a_bits_source = coupler_to_bus_named_cbus_bus_xingOut_a_bits_source; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_cbus_auto_bus_xing_out_a_bits_address = coupler_to_bus_named_cbus_bus_xingOut_a_bits_address; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_cbus_auto_bus_xing_out_a_bits_mask = coupler_to_bus_named_cbus_bus_xingOut_a_bits_mask; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_cbus_auto_bus_xing_out_a_bits_data = coupler_to_bus_named_cbus_bus_xingOut_a_bits_data; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_cbus_auto_bus_xing_out_a_bits_corrupt = coupler_to_bus_named_cbus_bus_xingOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_cbus_auto_bus_xing_out_d_ready = coupler_to_bus_named_cbus_bus_xingOut_d_ready; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_cbus_bus_xingIn_d_valid = coupler_to_bus_named_cbus_bus_xingOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_cbus_bus_xingIn_d_bits_opcode = coupler_to_bus_named_cbus_bus_xingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_cbus_bus_xingIn_d_bits_param = coupler_to_bus_named_cbus_bus_xingOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_cbus_bus_xingIn_d_bits_size = coupler_to_bus_named_cbus_bus_xingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_cbus_bus_xingIn_d_bits_source = coupler_to_bus_named_cbus_bus_xingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_cbus_bus_xingIn_d_bits_sink = coupler_to_bus_named_cbus_bus_xingOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_cbus_bus_xingIn_d_bits_denied = coupler_to_bus_named_cbus_bus_xingOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_cbus_bus_xingIn_d_bits_data = coupler_to_bus_named_cbus_bus_xingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_cbus_bus_xingIn_d_bits_corrupt = coupler_to_bus_named_cbus_bus_xingOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_cbus_widget_auto_anon_out_a_ready = coupler_to_bus_named_cbus_bus_xingIn_a_ready; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_cbus_bus_xingOut_a_valid = coupler_to_bus_named_cbus_bus_xingIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_cbus_bus_xingOut_a_bits_opcode = coupler_to_bus_named_cbus_bus_xingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_cbus_bus_xingOut_a_bits_param = coupler_to_bus_named_cbus_bus_xingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_cbus_bus_xingOut_a_bits_size = coupler_to_bus_named_cbus_bus_xingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_cbus_bus_xingOut_a_bits_source = coupler_to_bus_named_cbus_bus_xingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_cbus_bus_xingOut_a_bits_address = coupler_to_bus_named_cbus_bus_xingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_cbus_bus_xingOut_a_bits_mask = coupler_to_bus_named_cbus_bus_xingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_cbus_bus_xingOut_a_bits_data = coupler_to_bus_named_cbus_bus_xingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_cbus_bus_xingOut_a_bits_corrupt = coupler_to_bus_named_cbus_bus_xingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_cbus_bus_xingOut_d_ready = coupler_to_bus_named_cbus_bus_xingIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_cbus_widget_auto_anon_out_d_valid = coupler_to_bus_named_cbus_bus_xingIn_d_valid; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_cbus_widget_auto_anon_out_d_bits_opcode = coupler_to_bus_named_cbus_bus_xingIn_d_bits_opcode; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_cbus_widget_auto_anon_out_d_bits_param = coupler_to_bus_named_cbus_bus_xingIn_d_bits_param; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_cbus_widget_auto_anon_out_d_bits_size = coupler_to_bus_named_cbus_bus_xingIn_d_bits_size; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_cbus_widget_auto_anon_out_d_bits_source = coupler_to_bus_named_cbus_bus_xingIn_d_bits_source; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_cbus_widget_auto_anon_out_d_bits_sink = coupler_to_bus_named_cbus_bus_xingIn_d_bits_sink; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_cbus_widget_auto_anon_out_d_bits_denied = coupler_to_bus_named_cbus_bus_xingIn_d_bits_denied; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_cbus_widget_auto_anon_out_d_bits_data = coupler_to_bus_named_cbus_bus_xingIn_d_bits_data; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_cbus_widget_auto_anon_out_d_bits_corrupt = coupler_to_bus_named_cbus_bus_xingIn_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_from_bus_named_fbus_widget_auto_anon_out_a_ready = coupler_from_bus_named_fbus_auto_widget_anon_out_a_ready; // @[WidthWidget.scala:27:9] wire coupler_from_bus_named_fbus_widget_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9] assign fixer_auto_anon_in_0_a_valid = coupler_from_bus_named_fbus_auto_widget_anon_out_a_valid; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_bus_named_fbus_widget_auto_anon_out_a_bits_opcode; // @[WidthWidget.scala:27:9] assign fixer_auto_anon_in_0_a_bits_opcode = coupler_from_bus_named_fbus_auto_widget_anon_out_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_bus_named_fbus_widget_auto_anon_out_a_bits_param; // @[WidthWidget.scala:27:9] assign fixer_auto_anon_in_0_a_bits_param = coupler_from_bus_named_fbus_auto_widget_anon_out_a_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] coupler_from_bus_named_fbus_widget_auto_anon_out_a_bits_size; // @[WidthWidget.scala:27:9] assign fixer_auto_anon_in_0_a_bits_size = coupler_from_bus_named_fbus_auto_widget_anon_out_a_bits_size; // @[FIFOFixer.scala:50:9] wire [4:0] coupler_from_bus_named_fbus_widget_auto_anon_out_a_bits_source; // @[WidthWidget.scala:27:9] assign fixer_auto_anon_in_0_a_bits_source = coupler_from_bus_named_fbus_auto_widget_anon_out_a_bits_source; // @[FIFOFixer.scala:50:9] wire [31:0] coupler_from_bus_named_fbus_widget_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9] assign fixer_auto_anon_in_0_a_bits_address = coupler_from_bus_named_fbus_auto_widget_anon_out_a_bits_address; // @[FIFOFixer.scala:50:9] wire [7:0] coupler_from_bus_named_fbus_widget_auto_anon_out_a_bits_mask; // @[WidthWidget.scala:27:9] assign fixer_auto_anon_in_0_a_bits_mask = coupler_from_bus_named_fbus_auto_widget_anon_out_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [63:0] coupler_from_bus_named_fbus_widget_auto_anon_out_a_bits_data; // @[WidthWidget.scala:27:9] assign fixer_auto_anon_in_0_a_bits_data = coupler_from_bus_named_fbus_auto_widget_anon_out_a_bits_data; // @[FIFOFixer.scala:50:9] wire coupler_from_bus_named_fbus_widget_auto_anon_out_a_bits_corrupt; // @[WidthWidget.scala:27:9] assign fixer_auto_anon_in_0_a_bits_corrupt = coupler_from_bus_named_fbus_auto_widget_anon_out_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire coupler_from_bus_named_fbus_widget_auto_anon_out_d_ready; // @[WidthWidget.scala:27:9] assign fixer_auto_anon_in_0_d_ready = coupler_from_bus_named_fbus_auto_widget_anon_out_d_ready; // @[FIFOFixer.scala:50:9] wire coupler_from_bus_named_fbus_widget_auto_anon_out_d_valid = coupler_from_bus_named_fbus_auto_widget_anon_out_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_from_bus_named_fbus_widget_auto_anon_out_d_bits_opcode = coupler_from_bus_named_fbus_auto_widget_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] coupler_from_bus_named_fbus_widget_auto_anon_out_d_bits_param = coupler_from_bus_named_fbus_auto_widget_anon_out_d_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] coupler_from_bus_named_fbus_widget_auto_anon_out_d_bits_size = coupler_from_bus_named_fbus_auto_widget_anon_out_d_bits_size; // @[WidthWidget.scala:27:9] wire [4:0] coupler_from_bus_named_fbus_widget_auto_anon_out_d_bits_source = coupler_from_bus_named_fbus_auto_widget_anon_out_d_bits_source; // @[WidthWidget.scala:27:9] wire [2:0] coupler_from_bus_named_fbus_widget_auto_anon_out_d_bits_sink = coupler_from_bus_named_fbus_auto_widget_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9] wire coupler_from_bus_named_fbus_widget_auto_anon_out_d_bits_denied = coupler_from_bus_named_fbus_auto_widget_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9] wire [63:0] coupler_from_bus_named_fbus_widget_auto_anon_out_d_bits_data = coupler_from_bus_named_fbus_auto_widget_anon_out_d_bits_data; // @[WidthWidget.scala:27:9] wire coupler_from_bus_named_fbus_widget_auto_anon_out_d_bits_corrupt = coupler_from_bus_named_fbus_auto_widget_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_from_bus_named_fbus_bus_xingIn_a_ready; // @[MixedNode.scala:551:17] assign auto_coupler_from_bus_named_fbus_bus_xing_in_a_ready_0 = coupler_from_bus_named_fbus_auto_bus_xing_in_a_ready; // @[ClockDomain.scala:14:9] wire coupler_from_bus_named_fbus_bus_xingIn_a_valid = coupler_from_bus_named_fbus_auto_bus_xing_in_a_valid; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_bus_named_fbus_bus_xingIn_a_bits_opcode = coupler_from_bus_named_fbus_auto_bus_xing_in_a_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_bus_named_fbus_bus_xingIn_a_bits_param = coupler_from_bus_named_fbus_auto_bus_xing_in_a_bits_param; // @[MixedNode.scala:551:17] wire [3:0] coupler_from_bus_named_fbus_bus_xingIn_a_bits_size = coupler_from_bus_named_fbus_auto_bus_xing_in_a_bits_size; // @[MixedNode.scala:551:17] wire [4:0] coupler_from_bus_named_fbus_bus_xingIn_a_bits_source = coupler_from_bus_named_fbus_auto_bus_xing_in_a_bits_source; // @[MixedNode.scala:551:17] wire [31:0] coupler_from_bus_named_fbus_bus_xingIn_a_bits_address = coupler_from_bus_named_fbus_auto_bus_xing_in_a_bits_address; // @[MixedNode.scala:551:17] wire [7:0] coupler_from_bus_named_fbus_bus_xingIn_a_bits_mask = coupler_from_bus_named_fbus_auto_bus_xing_in_a_bits_mask; // @[MixedNode.scala:551:17] wire [63:0] coupler_from_bus_named_fbus_bus_xingIn_a_bits_data = coupler_from_bus_named_fbus_auto_bus_xing_in_a_bits_data; // @[MixedNode.scala:551:17] wire coupler_from_bus_named_fbus_bus_xingIn_a_bits_corrupt = coupler_from_bus_named_fbus_auto_bus_xing_in_a_bits_corrupt; // @[MixedNode.scala:551:17] wire coupler_from_bus_named_fbus_bus_xingIn_d_ready = coupler_from_bus_named_fbus_auto_bus_xing_in_d_ready; // @[MixedNode.scala:551:17] wire coupler_from_bus_named_fbus_bus_xingIn_d_valid; // @[MixedNode.scala:551:17] assign auto_coupler_from_bus_named_fbus_bus_xing_in_d_valid_0 = coupler_from_bus_named_fbus_auto_bus_xing_in_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] coupler_from_bus_named_fbus_bus_xingIn_d_bits_opcode; // @[MixedNode.scala:551:17] assign auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_opcode_0 = coupler_from_bus_named_fbus_auto_bus_xing_in_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] coupler_from_bus_named_fbus_bus_xingIn_d_bits_param; // @[MixedNode.scala:551:17] assign auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_param_0 = coupler_from_bus_named_fbus_auto_bus_xing_in_d_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] coupler_from_bus_named_fbus_bus_xingIn_d_bits_size; // @[MixedNode.scala:551:17] assign auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_size_0 = coupler_from_bus_named_fbus_auto_bus_xing_in_d_bits_size; // @[ClockDomain.scala:14:9] wire [4:0] coupler_from_bus_named_fbus_bus_xingIn_d_bits_source; // @[MixedNode.scala:551:17] assign auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_source_0 = coupler_from_bus_named_fbus_auto_bus_xing_in_d_bits_source; // @[ClockDomain.scala:14:9] wire [2:0] coupler_from_bus_named_fbus_bus_xingIn_d_bits_sink; // @[MixedNode.scala:551:17] assign auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_sink_0 = coupler_from_bus_named_fbus_auto_bus_xing_in_d_bits_sink; // @[ClockDomain.scala:14:9] wire coupler_from_bus_named_fbus_bus_xingIn_d_bits_denied; // @[MixedNode.scala:551:17] assign auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_denied_0 = coupler_from_bus_named_fbus_auto_bus_xing_in_d_bits_denied; // @[ClockDomain.scala:14:9] wire [63:0] coupler_from_bus_named_fbus_bus_xingIn_d_bits_data; // @[MixedNode.scala:551:17] assign auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_data_0 = coupler_from_bus_named_fbus_auto_bus_xing_in_d_bits_data; // @[ClockDomain.scala:14:9] wire coupler_from_bus_named_fbus_bus_xingIn_d_bits_corrupt; // @[MixedNode.scala:551:17] assign auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_corrupt_0 = coupler_from_bus_named_fbus_auto_bus_xing_in_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire coupler_from_bus_named_fbus_widget_anonIn_a_ready; // @[MixedNode.scala:551:17] wire coupler_from_bus_named_fbus_bus_xingOut_a_ready = coupler_from_bus_named_fbus_widget_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9] wire coupler_from_bus_named_fbus_bus_xingOut_a_valid; // @[MixedNode.scala:542:17] wire coupler_from_bus_named_fbus_widget_anonIn_a_valid = coupler_from_bus_named_fbus_widget_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_from_bus_named_fbus_bus_xingOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_bus_named_fbus_widget_anonIn_a_bits_opcode = coupler_from_bus_named_fbus_widget_auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] coupler_from_bus_named_fbus_bus_xingOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_bus_named_fbus_widget_anonIn_a_bits_param = coupler_from_bus_named_fbus_widget_auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] coupler_from_bus_named_fbus_bus_xingOut_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] coupler_from_bus_named_fbus_widget_anonIn_a_bits_size = coupler_from_bus_named_fbus_widget_auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9] wire [4:0] coupler_from_bus_named_fbus_bus_xingOut_a_bits_source; // @[MixedNode.scala:542:17] wire [4:0] coupler_from_bus_named_fbus_widget_anonIn_a_bits_source = coupler_from_bus_named_fbus_widget_auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] coupler_from_bus_named_fbus_bus_xingOut_a_bits_address; // @[MixedNode.scala:542:17] wire [31:0] coupler_from_bus_named_fbus_widget_anonIn_a_bits_address = coupler_from_bus_named_fbus_widget_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9] wire [7:0] coupler_from_bus_named_fbus_bus_xingOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [7:0] coupler_from_bus_named_fbus_widget_anonIn_a_bits_mask = coupler_from_bus_named_fbus_widget_auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9] wire [63:0] coupler_from_bus_named_fbus_bus_xingOut_a_bits_data; // @[MixedNode.scala:542:17] wire [63:0] coupler_from_bus_named_fbus_widget_anonIn_a_bits_data = coupler_from_bus_named_fbus_widget_auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9] wire coupler_from_bus_named_fbus_bus_xingOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire coupler_from_bus_named_fbus_widget_anonIn_a_bits_corrupt = coupler_from_bus_named_fbus_widget_auto_anon_in_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_from_bus_named_fbus_bus_xingOut_d_ready; // @[MixedNode.scala:542:17] wire coupler_from_bus_named_fbus_widget_anonIn_d_ready = coupler_from_bus_named_fbus_widget_auto_anon_in_d_ready; // @[WidthWidget.scala:27:9] wire coupler_from_bus_named_fbus_widget_anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_bus_named_fbus_widget_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire coupler_from_bus_named_fbus_bus_xingOut_d_valid = coupler_from_bus_named_fbus_widget_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9] wire [1:0] coupler_from_bus_named_fbus_widget_anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_bus_named_fbus_bus_xingOut_d_bits_opcode = coupler_from_bus_named_fbus_widget_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [3:0] coupler_from_bus_named_fbus_widget_anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] coupler_from_bus_named_fbus_bus_xingOut_d_bits_param = coupler_from_bus_named_fbus_widget_auto_anon_in_d_bits_param; // @[WidthWidget.scala:27:9] wire [4:0] coupler_from_bus_named_fbus_widget_anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] coupler_from_bus_named_fbus_bus_xingOut_d_bits_size = coupler_from_bus_named_fbus_widget_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9] wire [2:0] coupler_from_bus_named_fbus_widget_anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire [4:0] coupler_from_bus_named_fbus_bus_xingOut_d_bits_source = coupler_from_bus_named_fbus_widget_auto_anon_in_d_bits_source; // @[WidthWidget.scala:27:9] wire coupler_from_bus_named_fbus_widget_anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_bus_named_fbus_bus_xingOut_d_bits_sink = coupler_from_bus_named_fbus_widget_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:27:9] wire [63:0] coupler_from_bus_named_fbus_widget_anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire coupler_from_bus_named_fbus_bus_xingOut_d_bits_denied = coupler_from_bus_named_fbus_widget_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9] wire coupler_from_bus_named_fbus_widget_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] coupler_from_bus_named_fbus_bus_xingOut_d_bits_data = coupler_from_bus_named_fbus_widget_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9] wire coupler_from_bus_named_fbus_bus_xingOut_d_bits_corrupt = coupler_from_bus_named_fbus_widget_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_from_bus_named_fbus_widget_anonOut_a_ready = coupler_from_bus_named_fbus_widget_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9] wire coupler_from_bus_named_fbus_widget_anonOut_a_valid; // @[MixedNode.scala:542:17] assign coupler_from_bus_named_fbus_auto_widget_anon_out_a_valid = coupler_from_bus_named_fbus_widget_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_from_bus_named_fbus_widget_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign coupler_from_bus_named_fbus_auto_widget_anon_out_a_bits_opcode = coupler_from_bus_named_fbus_widget_auto_anon_out_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] coupler_from_bus_named_fbus_widget_anonOut_a_bits_param; // @[MixedNode.scala:542:17] assign coupler_from_bus_named_fbus_auto_widget_anon_out_a_bits_param = coupler_from_bus_named_fbus_widget_auto_anon_out_a_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] coupler_from_bus_named_fbus_widget_anonOut_a_bits_size; // @[MixedNode.scala:542:17] assign coupler_from_bus_named_fbus_auto_widget_anon_out_a_bits_size = coupler_from_bus_named_fbus_widget_auto_anon_out_a_bits_size; // @[WidthWidget.scala:27:9] wire [4:0] coupler_from_bus_named_fbus_widget_anonOut_a_bits_source; // @[MixedNode.scala:542:17] assign coupler_from_bus_named_fbus_auto_widget_anon_out_a_bits_source = coupler_from_bus_named_fbus_widget_auto_anon_out_a_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] coupler_from_bus_named_fbus_widget_anonOut_a_bits_address; // @[MixedNode.scala:542:17] assign coupler_from_bus_named_fbus_auto_widget_anon_out_a_bits_address = coupler_from_bus_named_fbus_widget_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9] wire [7:0] coupler_from_bus_named_fbus_widget_anonOut_a_bits_mask; // @[MixedNode.scala:542:17] assign coupler_from_bus_named_fbus_auto_widget_anon_out_a_bits_mask = coupler_from_bus_named_fbus_widget_auto_anon_out_a_bits_mask; // @[WidthWidget.scala:27:9] wire [63:0] coupler_from_bus_named_fbus_widget_anonOut_a_bits_data; // @[MixedNode.scala:542:17] assign coupler_from_bus_named_fbus_auto_widget_anon_out_a_bits_data = coupler_from_bus_named_fbus_widget_auto_anon_out_a_bits_data; // @[WidthWidget.scala:27:9] wire coupler_from_bus_named_fbus_widget_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign coupler_from_bus_named_fbus_auto_widget_anon_out_a_bits_corrupt = coupler_from_bus_named_fbus_widget_auto_anon_out_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_from_bus_named_fbus_widget_anonOut_d_ready; // @[MixedNode.scala:542:17] assign coupler_from_bus_named_fbus_auto_widget_anon_out_d_ready = coupler_from_bus_named_fbus_widget_auto_anon_out_d_ready; // @[WidthWidget.scala:27:9] wire coupler_from_bus_named_fbus_widget_anonOut_d_valid = coupler_from_bus_named_fbus_widget_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_from_bus_named_fbus_widget_anonOut_d_bits_opcode = coupler_from_bus_named_fbus_widget_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] coupler_from_bus_named_fbus_widget_anonOut_d_bits_param = coupler_from_bus_named_fbus_widget_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] coupler_from_bus_named_fbus_widget_anonOut_d_bits_size = coupler_from_bus_named_fbus_widget_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9] wire [4:0] coupler_from_bus_named_fbus_widget_anonOut_d_bits_source = coupler_from_bus_named_fbus_widget_auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9] wire [2:0] coupler_from_bus_named_fbus_widget_anonOut_d_bits_sink = coupler_from_bus_named_fbus_widget_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9] wire coupler_from_bus_named_fbus_widget_anonOut_d_bits_denied = coupler_from_bus_named_fbus_widget_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9] wire [63:0] coupler_from_bus_named_fbus_widget_anonOut_d_bits_data = coupler_from_bus_named_fbus_widget_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9] wire coupler_from_bus_named_fbus_widget_anonOut_d_bits_corrupt = coupler_from_bus_named_fbus_widget_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9] assign coupler_from_bus_named_fbus_widget_anonIn_a_ready = coupler_from_bus_named_fbus_widget_anonOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_bus_named_fbus_widget_auto_anon_out_a_valid = coupler_from_bus_named_fbus_widget_anonOut_a_valid; // @[WidthWidget.scala:27:9] assign coupler_from_bus_named_fbus_widget_auto_anon_out_a_bits_opcode = coupler_from_bus_named_fbus_widget_anonOut_a_bits_opcode; // @[WidthWidget.scala:27:9] assign coupler_from_bus_named_fbus_widget_auto_anon_out_a_bits_param = coupler_from_bus_named_fbus_widget_anonOut_a_bits_param; // @[WidthWidget.scala:27:9] assign coupler_from_bus_named_fbus_widget_auto_anon_out_a_bits_size = coupler_from_bus_named_fbus_widget_anonOut_a_bits_size; // @[WidthWidget.scala:27:9] assign coupler_from_bus_named_fbus_widget_auto_anon_out_a_bits_source = coupler_from_bus_named_fbus_widget_anonOut_a_bits_source; // @[WidthWidget.scala:27:9] assign coupler_from_bus_named_fbus_widget_auto_anon_out_a_bits_address = coupler_from_bus_named_fbus_widget_anonOut_a_bits_address; // @[WidthWidget.scala:27:9] assign coupler_from_bus_named_fbus_widget_auto_anon_out_a_bits_mask = coupler_from_bus_named_fbus_widget_anonOut_a_bits_mask; // @[WidthWidget.scala:27:9] assign coupler_from_bus_named_fbus_widget_auto_anon_out_a_bits_data = coupler_from_bus_named_fbus_widget_anonOut_a_bits_data; // @[WidthWidget.scala:27:9] assign coupler_from_bus_named_fbus_widget_auto_anon_out_a_bits_corrupt = coupler_from_bus_named_fbus_widget_anonOut_a_bits_corrupt; // @[WidthWidget.scala:27:9] assign coupler_from_bus_named_fbus_widget_auto_anon_out_d_ready = coupler_from_bus_named_fbus_widget_anonOut_d_ready; // @[WidthWidget.scala:27:9] assign coupler_from_bus_named_fbus_widget_anonIn_d_valid = coupler_from_bus_named_fbus_widget_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_bus_named_fbus_widget_anonIn_d_bits_opcode = coupler_from_bus_named_fbus_widget_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_bus_named_fbus_widget_anonIn_d_bits_param = coupler_from_bus_named_fbus_widget_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_bus_named_fbus_widget_anonIn_d_bits_size = coupler_from_bus_named_fbus_widget_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_bus_named_fbus_widget_anonIn_d_bits_source = coupler_from_bus_named_fbus_widget_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_bus_named_fbus_widget_anonIn_d_bits_sink = coupler_from_bus_named_fbus_widget_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_bus_named_fbus_widget_anonIn_d_bits_denied = coupler_from_bus_named_fbus_widget_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_bus_named_fbus_widget_anonIn_d_bits_data = coupler_from_bus_named_fbus_widget_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_bus_named_fbus_widget_anonIn_d_bits_corrupt = coupler_from_bus_named_fbus_widget_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_bus_named_fbus_widget_auto_anon_in_a_ready = coupler_from_bus_named_fbus_widget_anonIn_a_ready; // @[WidthWidget.scala:27:9] assign coupler_from_bus_named_fbus_widget_anonOut_a_valid = coupler_from_bus_named_fbus_widget_anonIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_bus_named_fbus_widget_anonOut_a_bits_opcode = coupler_from_bus_named_fbus_widget_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_bus_named_fbus_widget_anonOut_a_bits_param = coupler_from_bus_named_fbus_widget_anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_bus_named_fbus_widget_anonOut_a_bits_size = coupler_from_bus_named_fbus_widget_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_bus_named_fbus_widget_anonOut_a_bits_source = coupler_from_bus_named_fbus_widget_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_bus_named_fbus_widget_anonOut_a_bits_address = coupler_from_bus_named_fbus_widget_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_bus_named_fbus_widget_anonOut_a_bits_mask = coupler_from_bus_named_fbus_widget_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_bus_named_fbus_widget_anonOut_a_bits_data = coupler_from_bus_named_fbus_widget_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_bus_named_fbus_widget_anonOut_a_bits_corrupt = coupler_from_bus_named_fbus_widget_anonIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_bus_named_fbus_widget_anonOut_d_ready = coupler_from_bus_named_fbus_widget_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_bus_named_fbus_widget_auto_anon_in_d_valid = coupler_from_bus_named_fbus_widget_anonIn_d_valid; // @[WidthWidget.scala:27:9] assign coupler_from_bus_named_fbus_widget_auto_anon_in_d_bits_opcode = coupler_from_bus_named_fbus_widget_anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9] assign coupler_from_bus_named_fbus_widget_auto_anon_in_d_bits_param = coupler_from_bus_named_fbus_widget_anonIn_d_bits_param; // @[WidthWidget.scala:27:9] assign coupler_from_bus_named_fbus_widget_auto_anon_in_d_bits_size = coupler_from_bus_named_fbus_widget_anonIn_d_bits_size; // @[WidthWidget.scala:27:9] assign coupler_from_bus_named_fbus_widget_auto_anon_in_d_bits_source = coupler_from_bus_named_fbus_widget_anonIn_d_bits_source; // @[WidthWidget.scala:27:9] assign coupler_from_bus_named_fbus_widget_auto_anon_in_d_bits_sink = coupler_from_bus_named_fbus_widget_anonIn_d_bits_sink; // @[WidthWidget.scala:27:9] assign coupler_from_bus_named_fbus_widget_auto_anon_in_d_bits_denied = coupler_from_bus_named_fbus_widget_anonIn_d_bits_denied; // @[WidthWidget.scala:27:9] assign coupler_from_bus_named_fbus_widget_auto_anon_in_d_bits_data = coupler_from_bus_named_fbus_widget_anonIn_d_bits_data; // @[WidthWidget.scala:27:9] assign coupler_from_bus_named_fbus_widget_auto_anon_in_d_bits_corrupt = coupler_from_bus_named_fbus_widget_anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9] assign coupler_from_bus_named_fbus_bus_xingIn_a_ready = coupler_from_bus_named_fbus_bus_xingOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_bus_named_fbus_widget_auto_anon_in_a_valid = coupler_from_bus_named_fbus_bus_xingOut_a_valid; // @[WidthWidget.scala:27:9] assign coupler_from_bus_named_fbus_widget_auto_anon_in_a_bits_opcode = coupler_from_bus_named_fbus_bus_xingOut_a_bits_opcode; // @[WidthWidget.scala:27:9] assign coupler_from_bus_named_fbus_widget_auto_anon_in_a_bits_param = coupler_from_bus_named_fbus_bus_xingOut_a_bits_param; // @[WidthWidget.scala:27:9] assign coupler_from_bus_named_fbus_widget_auto_anon_in_a_bits_size = coupler_from_bus_named_fbus_bus_xingOut_a_bits_size; // @[WidthWidget.scala:27:9] assign coupler_from_bus_named_fbus_widget_auto_anon_in_a_bits_source = coupler_from_bus_named_fbus_bus_xingOut_a_bits_source; // @[WidthWidget.scala:27:9] assign coupler_from_bus_named_fbus_widget_auto_anon_in_a_bits_address = coupler_from_bus_named_fbus_bus_xingOut_a_bits_address; // @[WidthWidget.scala:27:9] assign coupler_from_bus_named_fbus_widget_auto_anon_in_a_bits_mask = coupler_from_bus_named_fbus_bus_xingOut_a_bits_mask; // @[WidthWidget.scala:27:9] assign coupler_from_bus_named_fbus_widget_auto_anon_in_a_bits_data = coupler_from_bus_named_fbus_bus_xingOut_a_bits_data; // @[WidthWidget.scala:27:9] assign coupler_from_bus_named_fbus_widget_auto_anon_in_a_bits_corrupt = coupler_from_bus_named_fbus_bus_xingOut_a_bits_corrupt; // @[WidthWidget.scala:27:9] assign coupler_from_bus_named_fbus_widget_auto_anon_in_d_ready = coupler_from_bus_named_fbus_bus_xingOut_d_ready; // @[WidthWidget.scala:27:9] assign coupler_from_bus_named_fbus_bus_xingIn_d_valid = coupler_from_bus_named_fbus_bus_xingOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_bus_named_fbus_bus_xingIn_d_bits_opcode = coupler_from_bus_named_fbus_bus_xingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_bus_named_fbus_bus_xingIn_d_bits_param = coupler_from_bus_named_fbus_bus_xingOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_bus_named_fbus_bus_xingIn_d_bits_size = coupler_from_bus_named_fbus_bus_xingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_bus_named_fbus_bus_xingIn_d_bits_source = coupler_from_bus_named_fbus_bus_xingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_bus_named_fbus_bus_xingIn_d_bits_sink = coupler_from_bus_named_fbus_bus_xingOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_bus_named_fbus_bus_xingIn_d_bits_denied = coupler_from_bus_named_fbus_bus_xingOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_bus_named_fbus_bus_xingIn_d_bits_data = coupler_from_bus_named_fbus_bus_xingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_bus_named_fbus_bus_xingIn_d_bits_corrupt = coupler_from_bus_named_fbus_bus_xingOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_bus_named_fbus_auto_bus_xing_in_a_ready = coupler_from_bus_named_fbus_bus_xingIn_a_ready; // @[MixedNode.scala:551:17] assign coupler_from_bus_named_fbus_bus_xingOut_a_valid = coupler_from_bus_named_fbus_bus_xingIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_bus_named_fbus_bus_xingOut_a_bits_opcode = coupler_from_bus_named_fbus_bus_xingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_bus_named_fbus_bus_xingOut_a_bits_param = coupler_from_bus_named_fbus_bus_xingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_bus_named_fbus_bus_xingOut_a_bits_size = coupler_from_bus_named_fbus_bus_xingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_bus_named_fbus_bus_xingOut_a_bits_source = coupler_from_bus_named_fbus_bus_xingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_bus_named_fbus_bus_xingOut_a_bits_address = coupler_from_bus_named_fbus_bus_xingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_bus_named_fbus_bus_xingOut_a_bits_mask = coupler_from_bus_named_fbus_bus_xingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_bus_named_fbus_bus_xingOut_a_bits_data = coupler_from_bus_named_fbus_bus_xingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_bus_named_fbus_bus_xingOut_a_bits_corrupt = coupler_from_bus_named_fbus_bus_xingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_bus_named_fbus_bus_xingOut_d_ready = coupler_from_bus_named_fbus_bus_xingIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_bus_named_fbus_auto_bus_xing_in_d_valid = coupler_from_bus_named_fbus_bus_xingIn_d_valid; // @[MixedNode.scala:551:17] assign coupler_from_bus_named_fbus_auto_bus_xing_in_d_bits_opcode = coupler_from_bus_named_fbus_bus_xingIn_d_bits_opcode; // @[MixedNode.scala:551:17] assign coupler_from_bus_named_fbus_auto_bus_xing_in_d_bits_param = coupler_from_bus_named_fbus_bus_xingIn_d_bits_param; // @[MixedNode.scala:551:17] assign coupler_from_bus_named_fbus_auto_bus_xing_in_d_bits_size = coupler_from_bus_named_fbus_bus_xingIn_d_bits_size; // @[MixedNode.scala:551:17] assign coupler_from_bus_named_fbus_auto_bus_xing_in_d_bits_source = coupler_from_bus_named_fbus_bus_xingIn_d_bits_source; // @[MixedNode.scala:551:17] assign coupler_from_bus_named_fbus_auto_bus_xing_in_d_bits_sink = coupler_from_bus_named_fbus_bus_xingIn_d_bits_sink; // @[MixedNode.scala:551:17] assign coupler_from_bus_named_fbus_auto_bus_xing_in_d_bits_denied = coupler_from_bus_named_fbus_bus_xingIn_d_bits_denied; // @[MixedNode.scala:551:17] assign coupler_from_bus_named_fbus_auto_bus_xing_in_d_bits_data = coupler_from_bus_named_fbus_bus_xingIn_d_bits_data; // @[MixedNode.scala:551:17] assign coupler_from_bus_named_fbus_auto_bus_xing_in_d_bits_corrupt = coupler_from_bus_named_fbus_bus_xingIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire coupler_to_bus_named_coh_widget_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_a_valid = coupler_to_bus_named_coh_auto_widget_anon_in_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_a_bits_opcode = coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_a_bits_param = coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_a_bits_size = coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_auto_anon_in_a_bits_source = coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_auto_anon_in_a_bits_address = coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_address; // @[WidthWidget.scala:27:9] wire [7:0] coupler_to_bus_named_coh_widget_auto_anon_in_a_bits_mask = coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9] wire [63:0] coupler_to_bus_named_coh_widget_auto_anon_in_a_bits_data = coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_a_bits_corrupt = coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_b_ready = coupler_to_bus_named_coh_auto_widget_anon_in_b_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_b_valid; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_coh_widget_auto_anon_in_b_bits_param; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_auto_anon_in_b_bits_address; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_c_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_c_valid = coupler_to_bus_named_coh_auto_widget_anon_in_c_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_c_bits_opcode = coupler_to_bus_named_coh_auto_widget_anon_in_c_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_c_bits_param = coupler_to_bus_named_coh_auto_widget_anon_in_c_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_c_bits_size = coupler_to_bus_named_coh_auto_widget_anon_in_c_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_auto_anon_in_c_bits_source = coupler_to_bus_named_coh_auto_widget_anon_in_c_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_auto_anon_in_c_bits_address = coupler_to_bus_named_coh_auto_widget_anon_in_c_bits_address; // @[WidthWidget.scala:27:9] wire [63:0] coupler_to_bus_named_coh_widget_auto_anon_in_c_bits_data = coupler_to_bus_named_coh_auto_widget_anon_in_c_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_c_bits_corrupt = coupler_to_bus_named_coh_auto_widget_anon_in_c_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_d_ready = coupler_to_bus_named_coh_auto_widget_anon_in_d_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_source; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9] wire [63:0] coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_in_e_valid = coupler_to_bus_named_coh_auto_widget_anon_in_e_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_in_e_bits_sink = coupler_to_bus_named_coh_auto_widget_anon_in_e_bits_sink; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_a_ready = coupler_to_bus_named_coh_auto_widget_anon_out_a_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_a_valid_0 = coupler_to_bus_named_coh_auto_widget_anon_out_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_opcode; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_opcode_0 = coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_param; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_param_0 = coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_param; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_size; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_size_0 = coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_size; // @[ClockDomain.scala:14:9] wire [5:0] coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_source; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_source_0 = coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_address_0 = coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_mask; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_mask_0 = coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_data; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_data_0 = coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_data; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_corrupt; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_corrupt_0 = coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_b_ready; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_b_ready_0 = coupler_to_bus_named_coh_auto_widget_anon_out_b_ready; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_b_valid = coupler_to_bus_named_coh_auto_widget_anon_out_b_valid; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_coh_widget_auto_anon_out_b_bits_param = coupler_to_bus_named_coh_auto_widget_anon_out_b_bits_param; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_auto_anon_out_b_bits_address = coupler_to_bus_named_coh_auto_widget_anon_out_b_bits_address; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_c_ready = coupler_to_bus_named_coh_auto_widget_anon_out_c_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_c_valid; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_c_valid_0 = coupler_to_bus_named_coh_auto_widget_anon_out_c_valid; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_c_bits_opcode; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_opcode_0 = coupler_to_bus_named_coh_auto_widget_anon_out_c_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_c_bits_param; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_param_0 = coupler_to_bus_named_coh_auto_widget_anon_out_c_bits_param; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_c_bits_size; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_size_0 = coupler_to_bus_named_coh_auto_widget_anon_out_c_bits_size; // @[ClockDomain.scala:14:9] wire [5:0] coupler_to_bus_named_coh_widget_auto_anon_out_c_bits_source; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_source_0 = coupler_to_bus_named_coh_auto_widget_anon_out_c_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] coupler_to_bus_named_coh_widget_auto_anon_out_c_bits_address; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_address_0 = coupler_to_bus_named_coh_auto_widget_anon_out_c_bits_address; // @[ClockDomain.scala:14:9] wire [63:0] coupler_to_bus_named_coh_widget_auto_anon_out_c_bits_data; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_data_0 = coupler_to_bus_named_coh_auto_widget_anon_out_c_bits_data; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_c_bits_corrupt; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_corrupt_0 = coupler_to_bus_named_coh_auto_widget_anon_out_c_bits_corrupt; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_d_ready; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_d_ready_0 = coupler_to_bus_named_coh_auto_widget_anon_out_d_ready; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_d_valid = coupler_to_bus_named_coh_auto_widget_anon_out_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_d_bits_opcode = coupler_to_bus_named_coh_auto_widget_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_coh_widget_auto_anon_out_d_bits_param = coupler_to_bus_named_coh_auto_widget_anon_out_d_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_d_bits_size = coupler_to_bus_named_coh_auto_widget_anon_out_d_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_auto_anon_out_d_bits_source = coupler_to_bus_named_coh_auto_widget_anon_out_d_bits_source; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_d_bits_sink = coupler_to_bus_named_coh_auto_widget_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_d_bits_denied = coupler_to_bus_named_coh_auto_widget_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9] wire [63:0] coupler_to_bus_named_coh_widget_auto_anon_out_d_bits_data = coupler_to_bus_named_coh_auto_widget_anon_out_d_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_d_bits_corrupt = coupler_to_bus_named_coh_auto_widget_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_auto_anon_out_e_valid; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_e_valid_0 = coupler_to_bus_named_coh_auto_widget_anon_out_e_valid; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_coh_widget_auto_anon_out_e_bits_sink; // @[WidthWidget.scala:27:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_e_bits_sink_0 = coupler_to_bus_named_coh_auto_widget_anon_out_e_bits_sink; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_coh_auto_widget_anon_in_a_ready; // @[LazyModuleImp.scala:138:7] wire [1:0] coupler_to_bus_named_coh_auto_widget_anon_in_b_bits_param; // @[LazyModuleImp.scala:138:7] wire [31:0] coupler_to_bus_named_coh_auto_widget_anon_in_b_bits_address; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_b_valid; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_c_ready; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [1:0] coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_size; // @[LazyModuleImp.scala:138:7] wire [5:0] coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_source; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_sink; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_denied; // @[LazyModuleImp.scala:138:7] wire [63:0] coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_data; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_auto_widget_anon_in_d_valid; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_coh_widget_anonIn_a_ready; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_a_ready = coupler_to_bus_named_coh_widget_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_anonIn_a_valid = coupler_to_bus_named_coh_widget_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_anonIn_a_bits_opcode = coupler_to_bus_named_coh_widget_auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_anonIn_a_bits_param = coupler_to_bus_named_coh_widget_auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_anonIn_a_bits_size = coupler_to_bus_named_coh_widget_auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_anonIn_a_bits_source = coupler_to_bus_named_coh_widget_auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_anonIn_a_bits_address = coupler_to_bus_named_coh_widget_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9] wire [7:0] coupler_to_bus_named_coh_widget_anonIn_a_bits_mask = coupler_to_bus_named_coh_widget_auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9] wire [63:0] coupler_to_bus_named_coh_widget_anonIn_a_bits_data = coupler_to_bus_named_coh_widget_auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_anonIn_a_bits_corrupt = coupler_to_bus_named_coh_widget_auto_anon_in_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_anonIn_b_ready = coupler_to_bus_named_coh_widget_auto_anon_in_b_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_anonIn_b_valid; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_b_valid = coupler_to_bus_named_coh_widget_auto_anon_in_b_valid; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_coh_widget_anonIn_b_bits_param; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_b_bits_param = coupler_to_bus_named_coh_widget_auto_anon_in_b_bits_param; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_anonIn_b_bits_address; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_b_bits_address = coupler_to_bus_named_coh_widget_auto_anon_in_b_bits_address; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_anonIn_c_ready; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_c_ready = coupler_to_bus_named_coh_widget_auto_anon_in_c_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_anonIn_c_valid = coupler_to_bus_named_coh_widget_auto_anon_in_c_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_anonIn_c_bits_opcode = coupler_to_bus_named_coh_widget_auto_anon_in_c_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_anonIn_c_bits_param = coupler_to_bus_named_coh_widget_auto_anon_in_c_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_anonIn_c_bits_size = coupler_to_bus_named_coh_widget_auto_anon_in_c_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_anonIn_c_bits_source = coupler_to_bus_named_coh_widget_auto_anon_in_c_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_anonIn_c_bits_address = coupler_to_bus_named_coh_widget_auto_anon_in_c_bits_address; // @[WidthWidget.scala:27:9] wire [63:0] coupler_to_bus_named_coh_widget_anonIn_c_bits_data = coupler_to_bus_named_coh_widget_auto_anon_in_c_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_anonIn_c_bits_corrupt = coupler_to_bus_named_coh_widget_auto_anon_in_c_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_anonIn_d_ready = coupler_to_bus_named_coh_widget_auto_anon_in_d_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_anonIn_d_valid; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_d_valid = coupler_to_bus_named_coh_widget_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_opcode = coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_coh_widget_anonIn_d_bits_param; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_param = coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_anonIn_d_bits_size; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_size = coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_anonIn_d_bits_source; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_source = coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_source; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_anonIn_d_bits_sink; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_sink = coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_anonIn_d_bits_denied; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_denied = coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9] wire [63:0] coupler_to_bus_named_coh_widget_anonIn_d_bits_data; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_data = coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_corrupt = coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_anonIn_e_valid = coupler_to_bus_named_coh_widget_auto_anon_in_e_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_anonIn_e_bits_sink = coupler_to_bus_named_coh_widget_auto_anon_in_e_bits_sink; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_anonOut_a_ready = coupler_to_bus_named_coh_widget_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_anonOut_a_valid; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_a_valid = coupler_to_bus_named_coh_widget_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_opcode = coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_anonOut_a_bits_param; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_param = coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_anonOut_a_bits_size; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_size = coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_anonOut_a_bits_source; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_source = coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_anonOut_a_bits_address; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_address = coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9] wire [7:0] coupler_to_bus_named_coh_widget_anonOut_a_bits_mask; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_mask = coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_mask; // @[WidthWidget.scala:27:9] wire [63:0] coupler_to_bus_named_coh_widget_anonOut_a_bits_data; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_data = coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_a_bits_corrupt = coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_anonOut_b_ready; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_b_ready = coupler_to_bus_named_coh_widget_auto_anon_out_b_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_anonOut_b_valid = coupler_to_bus_named_coh_widget_auto_anon_out_b_valid; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_coh_widget_anonOut_b_bits_param = coupler_to_bus_named_coh_widget_auto_anon_out_b_bits_param; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_anonOut_b_bits_address = coupler_to_bus_named_coh_widget_auto_anon_out_b_bits_address; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_anonOut_c_ready = coupler_to_bus_named_coh_widget_auto_anon_out_c_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_anonOut_c_valid; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_c_valid = coupler_to_bus_named_coh_widget_auto_anon_out_c_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_anonOut_c_bits_opcode; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_c_bits_opcode = coupler_to_bus_named_coh_widget_auto_anon_out_c_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_anonOut_c_bits_param; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_c_bits_param = coupler_to_bus_named_coh_widget_auto_anon_out_c_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_anonOut_c_bits_size; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_c_bits_size = coupler_to_bus_named_coh_widget_auto_anon_out_c_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_anonOut_c_bits_source; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_c_bits_source = coupler_to_bus_named_coh_widget_auto_anon_out_c_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_coh_widget_anonOut_c_bits_address; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_c_bits_address = coupler_to_bus_named_coh_widget_auto_anon_out_c_bits_address; // @[WidthWidget.scala:27:9] wire [63:0] coupler_to_bus_named_coh_widget_anonOut_c_bits_data; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_c_bits_data = coupler_to_bus_named_coh_widget_auto_anon_out_c_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_anonOut_c_bits_corrupt; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_c_bits_corrupt = coupler_to_bus_named_coh_widget_auto_anon_out_c_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_anonOut_d_ready; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_d_ready = coupler_to_bus_named_coh_widget_auto_anon_out_d_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_anonOut_d_valid = coupler_to_bus_named_coh_widget_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_anonOut_d_bits_opcode = coupler_to_bus_named_coh_widget_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_coh_widget_anonOut_d_bits_param = coupler_to_bus_named_coh_widget_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_anonOut_d_bits_size = coupler_to_bus_named_coh_widget_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9] wire [5:0] coupler_to_bus_named_coh_widget_anonOut_d_bits_source = coupler_to_bus_named_coh_widget_auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_anonOut_d_bits_sink = coupler_to_bus_named_coh_widget_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_anonOut_d_bits_denied = coupler_to_bus_named_coh_widget_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9] wire [63:0] coupler_to_bus_named_coh_widget_anonOut_d_bits_data = coupler_to_bus_named_coh_widget_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_anonOut_d_bits_corrupt = coupler_to_bus_named_coh_widget_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_coh_widget_anonOut_e_valid; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_e_valid = coupler_to_bus_named_coh_widget_auto_anon_out_e_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_coh_widget_anonOut_e_bits_sink; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_coh_auto_widget_anon_out_e_bits_sink = coupler_to_bus_named_coh_widget_auto_anon_out_e_bits_sink; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_anonIn_a_ready = coupler_to_bus_named_coh_widget_anonOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_auto_anon_out_a_valid = coupler_to_bus_named_coh_widget_anonOut_a_valid; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_opcode = coupler_to_bus_named_coh_widget_anonOut_a_bits_opcode; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_param = coupler_to_bus_named_coh_widget_anonOut_a_bits_param; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_size = coupler_to_bus_named_coh_widget_anonOut_a_bits_size; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_source = coupler_to_bus_named_coh_widget_anonOut_a_bits_source; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_address = coupler_to_bus_named_coh_widget_anonOut_a_bits_address; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_mask = coupler_to_bus_named_coh_widget_anonOut_a_bits_mask; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_data = coupler_to_bus_named_coh_widget_anonOut_a_bits_data; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_a_bits_corrupt = coupler_to_bus_named_coh_widget_anonOut_a_bits_corrupt; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_b_ready = coupler_to_bus_named_coh_widget_anonOut_b_ready; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_anonIn_b_valid = coupler_to_bus_named_coh_widget_anonOut_b_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_anonIn_b_bits_param = coupler_to_bus_named_coh_widget_anonOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_anonIn_b_bits_address = coupler_to_bus_named_coh_widget_anonOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_anonIn_c_ready = coupler_to_bus_named_coh_widget_anonOut_c_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_auto_anon_out_c_valid = coupler_to_bus_named_coh_widget_anonOut_c_valid; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_c_bits_opcode = coupler_to_bus_named_coh_widget_anonOut_c_bits_opcode; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_c_bits_param = coupler_to_bus_named_coh_widget_anonOut_c_bits_param; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_c_bits_size = coupler_to_bus_named_coh_widget_anonOut_c_bits_size; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_c_bits_source = coupler_to_bus_named_coh_widget_anonOut_c_bits_source; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_c_bits_address = coupler_to_bus_named_coh_widget_anonOut_c_bits_address; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_c_bits_data = coupler_to_bus_named_coh_widget_anonOut_c_bits_data; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_c_bits_corrupt = coupler_to_bus_named_coh_widget_anonOut_c_bits_corrupt; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_d_ready = coupler_to_bus_named_coh_widget_anonOut_d_ready; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_anonIn_d_valid = coupler_to_bus_named_coh_widget_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_anonIn_d_bits_opcode = coupler_to_bus_named_coh_widget_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_anonIn_d_bits_param = coupler_to_bus_named_coh_widget_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_anonIn_d_bits_size = coupler_to_bus_named_coh_widget_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_anonIn_d_bits_source = coupler_to_bus_named_coh_widget_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_anonIn_d_bits_sink = coupler_to_bus_named_coh_widget_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_anonIn_d_bits_denied = coupler_to_bus_named_coh_widget_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_anonIn_d_bits_data = coupler_to_bus_named_coh_widget_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_anonIn_d_bits_corrupt = coupler_to_bus_named_coh_widget_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_auto_anon_out_e_valid = coupler_to_bus_named_coh_widget_anonOut_e_valid; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_out_e_bits_sink = coupler_to_bus_named_coh_widget_anonOut_e_bits_sink; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_a_ready = coupler_to_bus_named_coh_widget_anonIn_a_ready; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_anonOut_a_valid = coupler_to_bus_named_coh_widget_anonIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_anonOut_a_bits_opcode = coupler_to_bus_named_coh_widget_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_anonOut_a_bits_param = coupler_to_bus_named_coh_widget_anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_anonOut_a_bits_size = coupler_to_bus_named_coh_widget_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_anonOut_a_bits_source = coupler_to_bus_named_coh_widget_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_anonOut_a_bits_address = coupler_to_bus_named_coh_widget_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_anonOut_a_bits_mask = coupler_to_bus_named_coh_widget_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_anonOut_a_bits_data = coupler_to_bus_named_coh_widget_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_anonOut_a_bits_corrupt = coupler_to_bus_named_coh_widget_anonIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_anonOut_b_ready = coupler_to_bus_named_coh_widget_anonIn_b_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_auto_anon_in_b_valid = coupler_to_bus_named_coh_widget_anonIn_b_valid; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_b_bits_param = coupler_to_bus_named_coh_widget_anonIn_b_bits_param; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_b_bits_address = coupler_to_bus_named_coh_widget_anonIn_b_bits_address; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_c_ready = coupler_to_bus_named_coh_widget_anonIn_c_ready; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_anonOut_c_valid = coupler_to_bus_named_coh_widget_anonIn_c_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_anonOut_c_bits_opcode = coupler_to_bus_named_coh_widget_anonIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_anonOut_c_bits_param = coupler_to_bus_named_coh_widget_anonIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_anonOut_c_bits_size = coupler_to_bus_named_coh_widget_anonIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_anonOut_c_bits_source = coupler_to_bus_named_coh_widget_anonIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_anonOut_c_bits_address = coupler_to_bus_named_coh_widget_anonIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_anonOut_c_bits_data = coupler_to_bus_named_coh_widget_anonIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_anonOut_c_bits_corrupt = coupler_to_bus_named_coh_widget_anonIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_anonOut_d_ready = coupler_to_bus_named_coh_widget_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_auto_anon_in_d_valid = coupler_to_bus_named_coh_widget_anonIn_d_valid; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_opcode = coupler_to_bus_named_coh_widget_anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_param = coupler_to_bus_named_coh_widget_anonIn_d_bits_param; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_size = coupler_to_bus_named_coh_widget_anonIn_d_bits_size; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_source = coupler_to_bus_named_coh_widget_anonIn_d_bits_source; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_sink = coupler_to_bus_named_coh_widget_anonIn_d_bits_sink; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_denied = coupler_to_bus_named_coh_widget_anonIn_d_bits_denied; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_data = coupler_to_bus_named_coh_widget_anonIn_d_bits_data; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_auto_anon_in_d_bits_corrupt = coupler_to_bus_named_coh_widget_anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_coh_widget_anonOut_e_valid = coupler_to_bus_named_coh_widget_anonIn_e_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_coh_widget_anonOut_e_bits_sink = coupler_to_bus_named_coh_widget_anonIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_spike_tile_tlMasterClockXingIn_a_ready; // @[MixedNode.scala:551:17] assign auto_coupler_from_spike_tile_tl_master_clock_xing_in_a_ready_0 = coupler_from_spike_tile_auto_tl_master_clock_xing_in_a_ready; // @[ClockDomain.scala:14:9] wire coupler_from_spike_tile_tlMasterClockXingIn_a_valid = coupler_from_spike_tile_auto_tl_master_clock_xing_in_a_valid; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_spike_tile_tlMasterClockXingIn_a_bits_opcode = coupler_from_spike_tile_auto_tl_master_clock_xing_in_a_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_spike_tile_tlMasterClockXingIn_a_bits_param = coupler_from_spike_tile_auto_tl_master_clock_xing_in_a_bits_param; // @[MixedNode.scala:551:17] wire [3:0] coupler_from_spike_tile_tlMasterClockXingIn_a_bits_size = coupler_from_spike_tile_auto_tl_master_clock_xing_in_a_bits_size; // @[MixedNode.scala:551:17] wire [1:0] coupler_from_spike_tile_tlMasterClockXingIn_a_bits_source = coupler_from_spike_tile_auto_tl_master_clock_xing_in_a_bits_source; // @[MixedNode.scala:551:17] wire [31:0] coupler_from_spike_tile_tlMasterClockXingIn_a_bits_address = coupler_from_spike_tile_auto_tl_master_clock_xing_in_a_bits_address; // @[MixedNode.scala:551:17] wire [7:0] coupler_from_spike_tile_tlMasterClockXingIn_a_bits_mask = coupler_from_spike_tile_auto_tl_master_clock_xing_in_a_bits_mask; // @[MixedNode.scala:551:17] wire [63:0] coupler_from_spike_tile_tlMasterClockXingIn_a_bits_data = coupler_from_spike_tile_auto_tl_master_clock_xing_in_a_bits_data; // @[MixedNode.scala:551:17] wire coupler_from_spike_tile_tlMasterClockXingIn_a_bits_corrupt = coupler_from_spike_tile_auto_tl_master_clock_xing_in_a_bits_corrupt; // @[MixedNode.scala:551:17] wire coupler_from_spike_tile_tlMasterClockXingIn_b_ready = coupler_from_spike_tile_auto_tl_master_clock_xing_in_b_ready; // @[MixedNode.scala:551:17] wire coupler_from_spike_tile_tlMasterClockXingIn_b_valid; // @[MixedNode.scala:551:17] assign auto_coupler_from_spike_tile_tl_master_clock_xing_in_b_valid_0 = coupler_from_spike_tile_auto_tl_master_clock_xing_in_b_valid; // @[ClockDomain.scala:14:9] wire [1:0] coupler_from_spike_tile_tlMasterClockXingIn_b_bits_param; // @[MixedNode.scala:551:17] assign auto_coupler_from_spike_tile_tl_master_clock_xing_in_b_bits_param_0 = coupler_from_spike_tile_auto_tl_master_clock_xing_in_b_bits_param; // @[ClockDomain.scala:14:9] wire [31:0] coupler_from_spike_tile_tlMasterClockXingIn_b_bits_address; // @[MixedNode.scala:551:17] assign auto_coupler_from_spike_tile_tl_master_clock_xing_in_b_bits_address_0 = coupler_from_spike_tile_auto_tl_master_clock_xing_in_b_bits_address; // @[ClockDomain.scala:14:9] wire coupler_from_spike_tile_tlMasterClockXingIn_c_ready; // @[MixedNode.scala:551:17] assign auto_coupler_from_spike_tile_tl_master_clock_xing_in_c_ready_0 = coupler_from_spike_tile_auto_tl_master_clock_xing_in_c_ready; // @[ClockDomain.scala:14:9] wire coupler_from_spike_tile_tlMasterClockXingIn_c_valid = coupler_from_spike_tile_auto_tl_master_clock_xing_in_c_valid; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_spike_tile_tlMasterClockXingIn_c_bits_opcode = coupler_from_spike_tile_auto_tl_master_clock_xing_in_c_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_spike_tile_tlMasterClockXingIn_c_bits_param = coupler_from_spike_tile_auto_tl_master_clock_xing_in_c_bits_param; // @[MixedNode.scala:551:17] wire [3:0] coupler_from_spike_tile_tlMasterClockXingIn_c_bits_size = coupler_from_spike_tile_auto_tl_master_clock_xing_in_c_bits_size; // @[MixedNode.scala:551:17] wire [1:0] coupler_from_spike_tile_tlMasterClockXingIn_c_bits_source = coupler_from_spike_tile_auto_tl_master_clock_xing_in_c_bits_source; // @[MixedNode.scala:551:17] wire [31:0] coupler_from_spike_tile_tlMasterClockXingIn_c_bits_address = coupler_from_spike_tile_auto_tl_master_clock_xing_in_c_bits_address; // @[MixedNode.scala:551:17] wire [63:0] coupler_from_spike_tile_tlMasterClockXingIn_c_bits_data = coupler_from_spike_tile_auto_tl_master_clock_xing_in_c_bits_data; // @[MixedNode.scala:551:17] wire coupler_from_spike_tile_tlMasterClockXingIn_c_bits_corrupt = coupler_from_spike_tile_auto_tl_master_clock_xing_in_c_bits_corrupt; // @[MixedNode.scala:551:17] wire coupler_from_spike_tile_tlMasterClockXingIn_d_ready = coupler_from_spike_tile_auto_tl_master_clock_xing_in_d_ready; // @[MixedNode.scala:551:17] wire coupler_from_spike_tile_tlMasterClockXingIn_d_valid; // @[MixedNode.scala:551:17] assign auto_coupler_from_spike_tile_tl_master_clock_xing_in_d_valid_0 = coupler_from_spike_tile_auto_tl_master_clock_xing_in_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] coupler_from_spike_tile_tlMasterClockXingIn_d_bits_opcode; // @[MixedNode.scala:551:17] assign auto_coupler_from_spike_tile_tl_master_clock_xing_in_d_bits_opcode_0 = coupler_from_spike_tile_auto_tl_master_clock_xing_in_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] coupler_from_spike_tile_tlMasterClockXingIn_d_bits_param; // @[MixedNode.scala:551:17] assign auto_coupler_from_spike_tile_tl_master_clock_xing_in_d_bits_param_0 = coupler_from_spike_tile_auto_tl_master_clock_xing_in_d_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] coupler_from_spike_tile_tlMasterClockXingIn_d_bits_size; // @[MixedNode.scala:551:17] assign auto_coupler_from_spike_tile_tl_master_clock_xing_in_d_bits_size_0 = coupler_from_spike_tile_auto_tl_master_clock_xing_in_d_bits_size; // @[ClockDomain.scala:14:9] wire [1:0] coupler_from_spike_tile_tlMasterClockXingIn_d_bits_source; // @[MixedNode.scala:551:17] assign auto_coupler_from_spike_tile_tl_master_clock_xing_in_d_bits_source_0 = coupler_from_spike_tile_auto_tl_master_clock_xing_in_d_bits_source; // @[ClockDomain.scala:14:9] wire [2:0] coupler_from_spike_tile_tlMasterClockXingIn_d_bits_sink; // @[MixedNode.scala:551:17] assign auto_coupler_from_spike_tile_tl_master_clock_xing_in_d_bits_sink_0 = coupler_from_spike_tile_auto_tl_master_clock_xing_in_d_bits_sink; // @[ClockDomain.scala:14:9] wire coupler_from_spike_tile_tlMasterClockXingIn_d_bits_denied; // @[MixedNode.scala:551:17] assign auto_coupler_from_spike_tile_tl_master_clock_xing_in_d_bits_denied_0 = coupler_from_spike_tile_auto_tl_master_clock_xing_in_d_bits_denied; // @[ClockDomain.scala:14:9] wire [63:0] coupler_from_spike_tile_tlMasterClockXingIn_d_bits_data; // @[MixedNode.scala:551:17] assign auto_coupler_from_spike_tile_tl_master_clock_xing_in_d_bits_data_0 = coupler_from_spike_tile_auto_tl_master_clock_xing_in_d_bits_data; // @[ClockDomain.scala:14:9] wire coupler_from_spike_tile_tlMasterClockXingIn_d_bits_corrupt; // @[MixedNode.scala:551:17] assign auto_coupler_from_spike_tile_tl_master_clock_xing_in_d_bits_corrupt_0 = coupler_from_spike_tile_auto_tl_master_clock_xing_in_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire coupler_from_spike_tile_tlMasterClockXingIn_e_valid = coupler_from_spike_tile_auto_tl_master_clock_xing_in_e_valid; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_spike_tile_tlMasterClockXingIn_e_bits_sink = coupler_from_spike_tile_auto_tl_master_clock_xing_in_e_bits_sink; // @[MixedNode.scala:551:17] wire coupler_from_spike_tile_tlOut_a_ready = coupler_from_spike_tile_auto_tl_out_a_ready; // @[MixedNode.scala:542:17] wire coupler_from_spike_tile_tlOut_a_valid; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_1_a_valid = coupler_from_spike_tile_auto_tl_out_a_valid; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_spike_tile_tlOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_1_a_bits_opcode = coupler_from_spike_tile_auto_tl_out_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_spike_tile_tlOut_a_bits_param; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_1_a_bits_param = coupler_from_spike_tile_auto_tl_out_a_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] coupler_from_spike_tile_tlOut_a_bits_size; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_1_a_bits_size = coupler_from_spike_tile_auto_tl_out_a_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] coupler_from_spike_tile_tlOut_a_bits_source; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_1_a_bits_source = coupler_from_spike_tile_auto_tl_out_a_bits_source; // @[FIFOFixer.scala:50:9] wire [31:0] coupler_from_spike_tile_tlOut_a_bits_address; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_1_a_bits_address = coupler_from_spike_tile_auto_tl_out_a_bits_address; // @[FIFOFixer.scala:50:9] wire [7:0] coupler_from_spike_tile_tlOut_a_bits_mask; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_1_a_bits_mask = coupler_from_spike_tile_auto_tl_out_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [63:0] coupler_from_spike_tile_tlOut_a_bits_data; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_1_a_bits_data = coupler_from_spike_tile_auto_tl_out_a_bits_data; // @[FIFOFixer.scala:50:9] wire coupler_from_spike_tile_tlOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_1_a_bits_corrupt = coupler_from_spike_tile_auto_tl_out_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire coupler_from_spike_tile_tlOut_b_ready; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_1_b_ready = coupler_from_spike_tile_auto_tl_out_b_ready; // @[FIFOFixer.scala:50:9] wire coupler_from_spike_tile_tlOut_b_valid = coupler_from_spike_tile_auto_tl_out_b_valid; // @[MixedNode.scala:542:17] wire [1:0] coupler_from_spike_tile_tlOut_b_bits_param = coupler_from_spike_tile_auto_tl_out_b_bits_param; // @[MixedNode.scala:542:17] wire [31:0] coupler_from_spike_tile_tlOut_b_bits_address = coupler_from_spike_tile_auto_tl_out_b_bits_address; // @[MixedNode.scala:542:17] wire coupler_from_spike_tile_tlOut_c_ready = coupler_from_spike_tile_auto_tl_out_c_ready; // @[MixedNode.scala:542:17] wire coupler_from_spike_tile_tlOut_c_valid; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_1_c_valid = coupler_from_spike_tile_auto_tl_out_c_valid; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_spike_tile_tlOut_c_bits_opcode; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_1_c_bits_opcode = coupler_from_spike_tile_auto_tl_out_c_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_spike_tile_tlOut_c_bits_param; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_1_c_bits_param = coupler_from_spike_tile_auto_tl_out_c_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] coupler_from_spike_tile_tlOut_c_bits_size; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_1_c_bits_size = coupler_from_spike_tile_auto_tl_out_c_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] coupler_from_spike_tile_tlOut_c_bits_source; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_1_c_bits_source = coupler_from_spike_tile_auto_tl_out_c_bits_source; // @[FIFOFixer.scala:50:9] wire [31:0] coupler_from_spike_tile_tlOut_c_bits_address; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_1_c_bits_address = coupler_from_spike_tile_auto_tl_out_c_bits_address; // @[FIFOFixer.scala:50:9] wire [63:0] coupler_from_spike_tile_tlOut_c_bits_data; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_1_c_bits_data = coupler_from_spike_tile_auto_tl_out_c_bits_data; // @[FIFOFixer.scala:50:9] wire coupler_from_spike_tile_tlOut_c_bits_corrupt; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_1_c_bits_corrupt = coupler_from_spike_tile_auto_tl_out_c_bits_corrupt; // @[FIFOFixer.scala:50:9] wire coupler_from_spike_tile_tlOut_d_ready; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_1_d_ready = coupler_from_spike_tile_auto_tl_out_d_ready; // @[FIFOFixer.scala:50:9] wire coupler_from_spike_tile_tlOut_d_valid = coupler_from_spike_tile_auto_tl_out_d_valid; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_spike_tile_tlOut_d_bits_opcode = coupler_from_spike_tile_auto_tl_out_d_bits_opcode; // @[MixedNode.scala:542:17] wire [1:0] coupler_from_spike_tile_tlOut_d_bits_param = coupler_from_spike_tile_auto_tl_out_d_bits_param; // @[MixedNode.scala:542:17] wire [3:0] coupler_from_spike_tile_tlOut_d_bits_size = coupler_from_spike_tile_auto_tl_out_d_bits_size; // @[MixedNode.scala:542:17] wire [1:0] coupler_from_spike_tile_tlOut_d_bits_source = coupler_from_spike_tile_auto_tl_out_d_bits_source; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_spike_tile_tlOut_d_bits_sink = coupler_from_spike_tile_auto_tl_out_d_bits_sink; // @[MixedNode.scala:542:17] wire coupler_from_spike_tile_tlOut_d_bits_denied = coupler_from_spike_tile_auto_tl_out_d_bits_denied; // @[MixedNode.scala:542:17] wire [63:0] coupler_from_spike_tile_tlOut_d_bits_data = coupler_from_spike_tile_auto_tl_out_d_bits_data; // @[MixedNode.scala:542:17] wire coupler_from_spike_tile_tlOut_d_bits_corrupt = coupler_from_spike_tile_auto_tl_out_d_bits_corrupt; // @[MixedNode.scala:542:17] wire coupler_from_spike_tile_tlOut_e_valid; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_1_e_valid = coupler_from_spike_tile_auto_tl_out_e_valid; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_spike_tile_tlOut_e_bits_sink; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_1_e_bits_sink = coupler_from_spike_tile_auto_tl_out_e_bits_sink; // @[FIFOFixer.scala:50:9] wire coupler_from_spike_tile_tlIn_a_ready = coupler_from_spike_tile_tlOut_a_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_spike_tile_tlIn_a_valid; // @[MixedNode.scala:551:17] assign coupler_from_spike_tile_auto_tl_out_a_valid = coupler_from_spike_tile_tlOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_spike_tile_tlIn_a_bits_opcode; // @[MixedNode.scala:551:17] assign coupler_from_spike_tile_auto_tl_out_a_bits_opcode = coupler_from_spike_tile_tlOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_spike_tile_tlIn_a_bits_param; // @[MixedNode.scala:551:17] assign coupler_from_spike_tile_auto_tl_out_a_bits_param = coupler_from_spike_tile_tlOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] coupler_from_spike_tile_tlIn_a_bits_size; // @[MixedNode.scala:551:17] assign coupler_from_spike_tile_auto_tl_out_a_bits_size = coupler_from_spike_tile_tlOut_a_bits_size; // @[MixedNode.scala:542:17] wire [1:0] coupler_from_spike_tile_tlIn_a_bits_source; // @[MixedNode.scala:551:17] assign coupler_from_spike_tile_auto_tl_out_a_bits_source = coupler_from_spike_tile_tlOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] coupler_from_spike_tile_tlIn_a_bits_address; // @[MixedNode.scala:551:17] assign coupler_from_spike_tile_auto_tl_out_a_bits_address = coupler_from_spike_tile_tlOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] coupler_from_spike_tile_tlIn_a_bits_mask; // @[MixedNode.scala:551:17] assign coupler_from_spike_tile_auto_tl_out_a_bits_mask = coupler_from_spike_tile_tlOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] coupler_from_spike_tile_tlIn_a_bits_data; // @[MixedNode.scala:551:17] assign coupler_from_spike_tile_auto_tl_out_a_bits_data = coupler_from_spike_tile_tlOut_a_bits_data; // @[MixedNode.scala:542:17] wire coupler_from_spike_tile_tlIn_a_bits_corrupt; // @[MixedNode.scala:551:17] assign coupler_from_spike_tile_auto_tl_out_a_bits_corrupt = coupler_from_spike_tile_tlOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire coupler_from_spike_tile_tlIn_b_ready; // @[MixedNode.scala:551:17] assign coupler_from_spike_tile_auto_tl_out_b_ready = coupler_from_spike_tile_tlOut_b_ready; // @[MixedNode.scala:542:17] wire coupler_from_spike_tile_tlIn_b_valid = coupler_from_spike_tile_tlOut_b_valid; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_spike_tile_tlIn_b_bits_param = coupler_from_spike_tile_tlOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_spike_tile_tlIn_b_bits_address = coupler_from_spike_tile_tlOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_spike_tile_tlIn_c_ready = coupler_from_spike_tile_tlOut_c_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_spike_tile_tlIn_c_valid; // @[MixedNode.scala:551:17] assign coupler_from_spike_tile_auto_tl_out_c_valid = coupler_from_spike_tile_tlOut_c_valid; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_spike_tile_tlIn_c_bits_opcode; // @[MixedNode.scala:551:17] assign coupler_from_spike_tile_auto_tl_out_c_bits_opcode = coupler_from_spike_tile_tlOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_spike_tile_tlIn_c_bits_param; // @[MixedNode.scala:551:17] assign coupler_from_spike_tile_auto_tl_out_c_bits_param = coupler_from_spike_tile_tlOut_c_bits_param; // @[MixedNode.scala:542:17] wire [3:0] coupler_from_spike_tile_tlIn_c_bits_size; // @[MixedNode.scala:551:17] assign coupler_from_spike_tile_auto_tl_out_c_bits_size = coupler_from_spike_tile_tlOut_c_bits_size; // @[MixedNode.scala:542:17] wire [1:0] coupler_from_spike_tile_tlIn_c_bits_source; // @[MixedNode.scala:551:17] assign coupler_from_spike_tile_auto_tl_out_c_bits_source = coupler_from_spike_tile_tlOut_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] coupler_from_spike_tile_tlIn_c_bits_address; // @[MixedNode.scala:551:17] assign coupler_from_spike_tile_auto_tl_out_c_bits_address = coupler_from_spike_tile_tlOut_c_bits_address; // @[MixedNode.scala:542:17] wire [63:0] coupler_from_spike_tile_tlIn_c_bits_data; // @[MixedNode.scala:551:17] assign coupler_from_spike_tile_auto_tl_out_c_bits_data = coupler_from_spike_tile_tlOut_c_bits_data; // @[MixedNode.scala:542:17] wire coupler_from_spike_tile_tlIn_c_bits_corrupt; // @[MixedNode.scala:551:17] assign coupler_from_spike_tile_auto_tl_out_c_bits_corrupt = coupler_from_spike_tile_tlOut_c_bits_corrupt; // @[MixedNode.scala:542:17] wire coupler_from_spike_tile_tlIn_d_ready; // @[MixedNode.scala:551:17] assign coupler_from_spike_tile_auto_tl_out_d_ready = coupler_from_spike_tile_tlOut_d_ready; // @[MixedNode.scala:542:17] wire coupler_from_spike_tile_tlIn_d_valid = coupler_from_spike_tile_tlOut_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_spike_tile_tlIn_d_bits_opcode = coupler_from_spike_tile_tlOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_spike_tile_tlIn_d_bits_param = coupler_from_spike_tile_tlOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_spike_tile_tlIn_d_bits_size = coupler_from_spike_tile_tlOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_spike_tile_tlIn_d_bits_source = coupler_from_spike_tile_tlOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_spike_tile_tlIn_d_bits_sink = coupler_from_spike_tile_tlOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_spike_tile_tlIn_d_bits_denied = coupler_from_spike_tile_tlOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_spike_tile_tlIn_d_bits_data = coupler_from_spike_tile_tlOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_spike_tile_tlIn_d_bits_corrupt = coupler_from_spike_tile_tlOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_spike_tile_tlIn_e_valid; // @[MixedNode.scala:551:17] assign coupler_from_spike_tile_auto_tl_out_e_valid = coupler_from_spike_tile_tlOut_e_valid; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_spike_tile_tlIn_e_bits_sink; // @[MixedNode.scala:551:17] assign coupler_from_spike_tile_auto_tl_out_e_bits_sink = coupler_from_spike_tile_tlOut_e_bits_sink; // @[MixedNode.scala:542:17] wire coupler_from_spike_tile_no_bufferOut_a_ready = coupler_from_spike_tile_tlIn_a_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_spike_tile_no_bufferOut_a_valid; // @[MixedNode.scala:542:17] assign coupler_from_spike_tile_tlOut_a_valid = coupler_from_spike_tile_tlIn_a_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_spike_tile_no_bufferOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign coupler_from_spike_tile_tlOut_a_bits_opcode = coupler_from_spike_tile_tlIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_spike_tile_no_bufferOut_a_bits_param; // @[MixedNode.scala:542:17] assign coupler_from_spike_tile_tlOut_a_bits_param = coupler_from_spike_tile_tlIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_spike_tile_no_bufferOut_a_bits_size; // @[MixedNode.scala:542:17] assign coupler_from_spike_tile_tlOut_a_bits_size = coupler_from_spike_tile_tlIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_spike_tile_no_bufferOut_a_bits_source; // @[MixedNode.scala:542:17] assign coupler_from_spike_tile_tlOut_a_bits_source = coupler_from_spike_tile_tlIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_spike_tile_no_bufferOut_a_bits_address; // @[MixedNode.scala:542:17] assign coupler_from_spike_tile_tlOut_a_bits_address = coupler_from_spike_tile_tlIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [7:0] coupler_from_spike_tile_no_bufferOut_a_bits_mask; // @[MixedNode.scala:542:17] assign coupler_from_spike_tile_tlOut_a_bits_mask = coupler_from_spike_tile_tlIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_spike_tile_no_bufferOut_a_bits_data; // @[MixedNode.scala:542:17] assign coupler_from_spike_tile_tlOut_a_bits_data = coupler_from_spike_tile_tlIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_spike_tile_no_bufferOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign coupler_from_spike_tile_tlOut_a_bits_corrupt = coupler_from_spike_tile_tlIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_spike_tile_no_bufferOut_b_ready; // @[MixedNode.scala:542:17] assign coupler_from_spike_tile_tlOut_b_ready = coupler_from_spike_tile_tlIn_b_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_spike_tile_no_bufferOut_b_valid = coupler_from_spike_tile_tlIn_b_valid; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_spike_tile_no_bufferOut_b_bits_param = coupler_from_spike_tile_tlIn_b_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_spike_tile_no_bufferOut_b_bits_address = coupler_from_spike_tile_tlIn_b_bits_address; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_spike_tile_no_bufferOut_c_ready = coupler_from_spike_tile_tlIn_c_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_spike_tile_no_bufferOut_c_valid; // @[MixedNode.scala:542:17] assign coupler_from_spike_tile_tlOut_c_valid = coupler_from_spike_tile_tlIn_c_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_spike_tile_no_bufferOut_c_bits_opcode; // @[MixedNode.scala:542:17] assign coupler_from_spike_tile_tlOut_c_bits_opcode = coupler_from_spike_tile_tlIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_spike_tile_no_bufferOut_c_bits_param; // @[MixedNode.scala:542:17] assign coupler_from_spike_tile_tlOut_c_bits_param = coupler_from_spike_tile_tlIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_spike_tile_no_bufferOut_c_bits_size; // @[MixedNode.scala:542:17] assign coupler_from_spike_tile_tlOut_c_bits_size = coupler_from_spike_tile_tlIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_spike_tile_no_bufferOut_c_bits_source; // @[MixedNode.scala:542:17] assign coupler_from_spike_tile_tlOut_c_bits_source = coupler_from_spike_tile_tlIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_spike_tile_no_bufferOut_c_bits_address; // @[MixedNode.scala:542:17] assign coupler_from_spike_tile_tlOut_c_bits_address = coupler_from_spike_tile_tlIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_spike_tile_no_bufferOut_c_bits_data; // @[MixedNode.scala:542:17] assign coupler_from_spike_tile_tlOut_c_bits_data = coupler_from_spike_tile_tlIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_spike_tile_no_bufferOut_c_bits_corrupt; // @[MixedNode.scala:542:17] assign coupler_from_spike_tile_tlOut_c_bits_corrupt = coupler_from_spike_tile_tlIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_spike_tile_no_bufferOut_d_ready; // @[MixedNode.scala:542:17] assign coupler_from_spike_tile_tlOut_d_ready = coupler_from_spike_tile_tlIn_d_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_spike_tile_no_bufferOut_d_valid = coupler_from_spike_tile_tlIn_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_spike_tile_no_bufferOut_d_bits_opcode = coupler_from_spike_tile_tlIn_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_spike_tile_no_bufferOut_d_bits_param = coupler_from_spike_tile_tlIn_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_spike_tile_no_bufferOut_d_bits_size = coupler_from_spike_tile_tlIn_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_spike_tile_no_bufferOut_d_bits_source = coupler_from_spike_tile_tlIn_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_spike_tile_no_bufferOut_d_bits_sink = coupler_from_spike_tile_tlIn_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_spike_tile_no_bufferOut_d_bits_denied = coupler_from_spike_tile_tlIn_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_spike_tile_no_bufferOut_d_bits_data = coupler_from_spike_tile_tlIn_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_spike_tile_no_bufferOut_d_bits_corrupt = coupler_from_spike_tile_tlIn_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_spike_tile_no_bufferOut_e_valid; // @[MixedNode.scala:542:17] assign coupler_from_spike_tile_tlOut_e_valid = coupler_from_spike_tile_tlIn_e_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_spike_tile_no_bufferOut_e_bits_sink; // @[MixedNode.scala:542:17] assign coupler_from_spike_tile_tlOut_e_bits_sink = coupler_from_spike_tile_tlIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_spike_tile_no_bufferIn_a_ready = coupler_from_spike_tile_no_bufferOut_a_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_spike_tile_no_bufferIn_a_valid; // @[MixedNode.scala:551:17] assign coupler_from_spike_tile_tlIn_a_valid = coupler_from_spike_tile_no_bufferOut_a_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_spike_tile_no_bufferIn_a_bits_opcode; // @[MixedNode.scala:551:17] assign coupler_from_spike_tile_tlIn_a_bits_opcode = coupler_from_spike_tile_no_bufferOut_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_spike_tile_no_bufferIn_a_bits_param; // @[MixedNode.scala:551:17] assign coupler_from_spike_tile_tlIn_a_bits_param = coupler_from_spike_tile_no_bufferOut_a_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_spike_tile_no_bufferIn_a_bits_size; // @[MixedNode.scala:551:17] assign coupler_from_spike_tile_tlIn_a_bits_size = coupler_from_spike_tile_no_bufferOut_a_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_spike_tile_no_bufferIn_a_bits_source; // @[MixedNode.scala:551:17] assign coupler_from_spike_tile_tlIn_a_bits_source = coupler_from_spike_tile_no_bufferOut_a_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_spike_tile_no_bufferIn_a_bits_address; // @[MixedNode.scala:551:17] assign coupler_from_spike_tile_tlIn_a_bits_address = coupler_from_spike_tile_no_bufferOut_a_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [7:0] coupler_from_spike_tile_no_bufferIn_a_bits_mask; // @[MixedNode.scala:551:17] assign coupler_from_spike_tile_tlIn_a_bits_mask = coupler_from_spike_tile_no_bufferOut_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_spike_tile_no_bufferIn_a_bits_data; // @[MixedNode.scala:551:17] assign coupler_from_spike_tile_tlIn_a_bits_data = coupler_from_spike_tile_no_bufferOut_a_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_spike_tile_no_bufferIn_a_bits_corrupt; // @[MixedNode.scala:551:17] assign coupler_from_spike_tile_tlIn_a_bits_corrupt = coupler_from_spike_tile_no_bufferOut_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_spike_tile_no_bufferIn_b_ready; // @[MixedNode.scala:551:17] assign coupler_from_spike_tile_tlIn_b_ready = coupler_from_spike_tile_no_bufferOut_b_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_spike_tile_no_bufferIn_b_valid = coupler_from_spike_tile_no_bufferOut_b_valid; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_spike_tile_no_bufferIn_b_bits_param = coupler_from_spike_tile_no_bufferOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_spike_tile_no_bufferIn_b_bits_address = coupler_from_spike_tile_no_bufferOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_spike_tile_no_bufferIn_c_ready = coupler_from_spike_tile_no_bufferOut_c_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_spike_tile_no_bufferIn_c_valid; // @[MixedNode.scala:551:17] assign coupler_from_spike_tile_tlIn_c_valid = coupler_from_spike_tile_no_bufferOut_c_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_spike_tile_no_bufferIn_c_bits_opcode; // @[MixedNode.scala:551:17] assign coupler_from_spike_tile_tlIn_c_bits_opcode = coupler_from_spike_tile_no_bufferOut_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_spike_tile_no_bufferIn_c_bits_param; // @[MixedNode.scala:551:17] assign coupler_from_spike_tile_tlIn_c_bits_param = coupler_from_spike_tile_no_bufferOut_c_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_spike_tile_no_bufferIn_c_bits_size; // @[MixedNode.scala:551:17] assign coupler_from_spike_tile_tlIn_c_bits_size = coupler_from_spike_tile_no_bufferOut_c_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_spike_tile_no_bufferIn_c_bits_source; // @[MixedNode.scala:551:17] assign coupler_from_spike_tile_tlIn_c_bits_source = coupler_from_spike_tile_no_bufferOut_c_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_spike_tile_no_bufferIn_c_bits_address; // @[MixedNode.scala:551:17] assign coupler_from_spike_tile_tlIn_c_bits_address = coupler_from_spike_tile_no_bufferOut_c_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_spike_tile_no_bufferIn_c_bits_data; // @[MixedNode.scala:551:17] assign coupler_from_spike_tile_tlIn_c_bits_data = coupler_from_spike_tile_no_bufferOut_c_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_spike_tile_no_bufferIn_c_bits_corrupt; // @[MixedNode.scala:551:17] assign coupler_from_spike_tile_tlIn_c_bits_corrupt = coupler_from_spike_tile_no_bufferOut_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_spike_tile_no_bufferIn_d_ready; // @[MixedNode.scala:551:17] assign coupler_from_spike_tile_tlIn_d_ready = coupler_from_spike_tile_no_bufferOut_d_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_spike_tile_no_bufferIn_d_valid = coupler_from_spike_tile_no_bufferOut_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_spike_tile_no_bufferIn_d_bits_opcode = coupler_from_spike_tile_no_bufferOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_spike_tile_no_bufferIn_d_bits_param = coupler_from_spike_tile_no_bufferOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_spike_tile_no_bufferIn_d_bits_size = coupler_from_spike_tile_no_bufferOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_spike_tile_no_bufferIn_d_bits_source = coupler_from_spike_tile_no_bufferOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_spike_tile_no_bufferIn_d_bits_sink = coupler_from_spike_tile_no_bufferOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_spike_tile_no_bufferIn_d_bits_denied = coupler_from_spike_tile_no_bufferOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_spike_tile_no_bufferIn_d_bits_data = coupler_from_spike_tile_no_bufferOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_spike_tile_no_bufferIn_d_bits_corrupt = coupler_from_spike_tile_no_bufferOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_spike_tile_no_bufferIn_e_valid; // @[MixedNode.scala:551:17] assign coupler_from_spike_tile_tlIn_e_valid = coupler_from_spike_tile_no_bufferOut_e_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_spike_tile_no_bufferIn_e_bits_sink; // @[MixedNode.scala:551:17] assign coupler_from_spike_tile_tlIn_e_bits_sink = coupler_from_spike_tile_no_bufferOut_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_spike_tile_tlMasterClockXingOut_a_ready = coupler_from_spike_tile_no_bufferIn_a_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_spike_tile_tlMasterClockXingOut_a_valid; // @[MixedNode.scala:542:17] assign coupler_from_spike_tile_no_bufferOut_a_valid = coupler_from_spike_tile_no_bufferIn_a_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_spike_tile_tlMasterClockXingOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign coupler_from_spike_tile_no_bufferOut_a_bits_opcode = coupler_from_spike_tile_no_bufferIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_spike_tile_tlMasterClockXingOut_a_bits_param; // @[MixedNode.scala:542:17] assign coupler_from_spike_tile_no_bufferOut_a_bits_param = coupler_from_spike_tile_no_bufferIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_spike_tile_tlMasterClockXingOut_a_bits_size; // @[MixedNode.scala:542:17] assign coupler_from_spike_tile_no_bufferOut_a_bits_size = coupler_from_spike_tile_no_bufferIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_spike_tile_tlMasterClockXingOut_a_bits_source; // @[MixedNode.scala:542:17] assign coupler_from_spike_tile_no_bufferOut_a_bits_source = coupler_from_spike_tile_no_bufferIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_spike_tile_tlMasterClockXingOut_a_bits_address; // @[MixedNode.scala:542:17] assign coupler_from_spike_tile_no_bufferOut_a_bits_address = coupler_from_spike_tile_no_bufferIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [7:0] coupler_from_spike_tile_tlMasterClockXingOut_a_bits_mask; // @[MixedNode.scala:542:17] assign coupler_from_spike_tile_no_bufferOut_a_bits_mask = coupler_from_spike_tile_no_bufferIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_spike_tile_tlMasterClockXingOut_a_bits_data; // @[MixedNode.scala:542:17] assign coupler_from_spike_tile_no_bufferOut_a_bits_data = coupler_from_spike_tile_no_bufferIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_spike_tile_tlMasterClockXingOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign coupler_from_spike_tile_no_bufferOut_a_bits_corrupt = coupler_from_spike_tile_no_bufferIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_spike_tile_tlMasterClockXingOut_b_ready; // @[MixedNode.scala:542:17] assign coupler_from_spike_tile_no_bufferOut_b_ready = coupler_from_spike_tile_no_bufferIn_b_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_spike_tile_tlMasterClockXingOut_b_valid = coupler_from_spike_tile_no_bufferIn_b_valid; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_spike_tile_tlMasterClockXingOut_b_bits_param = coupler_from_spike_tile_no_bufferIn_b_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_spike_tile_tlMasterClockXingOut_b_bits_address = coupler_from_spike_tile_no_bufferIn_b_bits_address; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_spike_tile_tlMasterClockXingOut_c_ready = coupler_from_spike_tile_no_bufferIn_c_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_spike_tile_tlMasterClockXingOut_c_valid; // @[MixedNode.scala:542:17] assign coupler_from_spike_tile_no_bufferOut_c_valid = coupler_from_spike_tile_no_bufferIn_c_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_spike_tile_tlMasterClockXingOut_c_bits_opcode; // @[MixedNode.scala:542:17] assign coupler_from_spike_tile_no_bufferOut_c_bits_opcode = coupler_from_spike_tile_no_bufferIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_spike_tile_tlMasterClockXingOut_c_bits_param; // @[MixedNode.scala:542:17] assign coupler_from_spike_tile_no_bufferOut_c_bits_param = coupler_from_spike_tile_no_bufferIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_spike_tile_tlMasterClockXingOut_c_bits_size; // @[MixedNode.scala:542:17] assign coupler_from_spike_tile_no_bufferOut_c_bits_size = coupler_from_spike_tile_no_bufferIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_spike_tile_tlMasterClockXingOut_c_bits_source; // @[MixedNode.scala:542:17] assign coupler_from_spike_tile_no_bufferOut_c_bits_source = coupler_from_spike_tile_no_bufferIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_spike_tile_tlMasterClockXingOut_c_bits_address; // @[MixedNode.scala:542:17] assign coupler_from_spike_tile_no_bufferOut_c_bits_address = coupler_from_spike_tile_no_bufferIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_spike_tile_tlMasterClockXingOut_c_bits_data; // @[MixedNode.scala:542:17] assign coupler_from_spike_tile_no_bufferOut_c_bits_data = coupler_from_spike_tile_no_bufferIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_spike_tile_tlMasterClockXingOut_c_bits_corrupt; // @[MixedNode.scala:542:17] assign coupler_from_spike_tile_no_bufferOut_c_bits_corrupt = coupler_from_spike_tile_no_bufferIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_spike_tile_tlMasterClockXingOut_d_ready; // @[MixedNode.scala:542:17] assign coupler_from_spike_tile_no_bufferOut_d_ready = coupler_from_spike_tile_no_bufferIn_d_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_spike_tile_tlMasterClockXingOut_d_valid = coupler_from_spike_tile_no_bufferIn_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_spike_tile_tlMasterClockXingOut_d_bits_opcode = coupler_from_spike_tile_no_bufferIn_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_spike_tile_tlMasterClockXingOut_d_bits_param = coupler_from_spike_tile_no_bufferIn_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_spike_tile_tlMasterClockXingOut_d_bits_size = coupler_from_spike_tile_no_bufferIn_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_spike_tile_tlMasterClockXingOut_d_bits_source = coupler_from_spike_tile_no_bufferIn_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_spike_tile_tlMasterClockXingOut_d_bits_sink = coupler_from_spike_tile_no_bufferIn_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_spike_tile_tlMasterClockXingOut_d_bits_denied = coupler_from_spike_tile_no_bufferIn_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_spike_tile_tlMasterClockXingOut_d_bits_data = coupler_from_spike_tile_no_bufferIn_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_spike_tile_tlMasterClockXingOut_d_bits_corrupt = coupler_from_spike_tile_no_bufferIn_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_spike_tile_tlMasterClockXingOut_e_valid; // @[MixedNode.scala:542:17] assign coupler_from_spike_tile_no_bufferOut_e_valid = coupler_from_spike_tile_no_bufferIn_e_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_spike_tile_tlMasterClockXingOut_e_bits_sink; // @[MixedNode.scala:542:17] assign coupler_from_spike_tile_no_bufferOut_e_bits_sink = coupler_from_spike_tile_no_bufferIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_spike_tile_tlMasterClockXingIn_a_ready = coupler_from_spike_tile_tlMasterClockXingOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_spike_tile_no_bufferIn_a_valid = coupler_from_spike_tile_tlMasterClockXingOut_a_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_spike_tile_no_bufferIn_a_bits_opcode = coupler_from_spike_tile_tlMasterClockXingOut_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_spike_tile_no_bufferIn_a_bits_param = coupler_from_spike_tile_tlMasterClockXingOut_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_spike_tile_no_bufferIn_a_bits_size = coupler_from_spike_tile_tlMasterClockXingOut_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_spike_tile_no_bufferIn_a_bits_source = coupler_from_spike_tile_tlMasterClockXingOut_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_spike_tile_no_bufferIn_a_bits_address = coupler_from_spike_tile_tlMasterClockXingOut_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_spike_tile_no_bufferIn_a_bits_mask = coupler_from_spike_tile_tlMasterClockXingOut_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_spike_tile_no_bufferIn_a_bits_data = coupler_from_spike_tile_tlMasterClockXingOut_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_spike_tile_no_bufferIn_a_bits_corrupt = coupler_from_spike_tile_tlMasterClockXingOut_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_spike_tile_no_bufferIn_b_ready = coupler_from_spike_tile_tlMasterClockXingOut_b_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_spike_tile_tlMasterClockXingIn_b_valid = coupler_from_spike_tile_tlMasterClockXingOut_b_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_spike_tile_tlMasterClockXingIn_b_bits_param = coupler_from_spike_tile_tlMasterClockXingOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_spike_tile_tlMasterClockXingIn_b_bits_address = coupler_from_spike_tile_tlMasterClockXingOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_spike_tile_tlMasterClockXingIn_c_ready = coupler_from_spike_tile_tlMasterClockXingOut_c_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_spike_tile_no_bufferIn_c_valid = coupler_from_spike_tile_tlMasterClockXingOut_c_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_spike_tile_no_bufferIn_c_bits_opcode = coupler_from_spike_tile_tlMasterClockXingOut_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_spike_tile_no_bufferIn_c_bits_param = coupler_from_spike_tile_tlMasterClockXingOut_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_spike_tile_no_bufferIn_c_bits_size = coupler_from_spike_tile_tlMasterClockXingOut_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_spike_tile_no_bufferIn_c_bits_source = coupler_from_spike_tile_tlMasterClockXingOut_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_spike_tile_no_bufferIn_c_bits_address = coupler_from_spike_tile_tlMasterClockXingOut_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_spike_tile_no_bufferIn_c_bits_data = coupler_from_spike_tile_tlMasterClockXingOut_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_spike_tile_no_bufferIn_c_bits_corrupt = coupler_from_spike_tile_tlMasterClockXingOut_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_spike_tile_no_bufferIn_d_ready = coupler_from_spike_tile_tlMasterClockXingOut_d_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_spike_tile_tlMasterClockXingIn_d_valid = coupler_from_spike_tile_tlMasterClockXingOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_spike_tile_tlMasterClockXingIn_d_bits_opcode = coupler_from_spike_tile_tlMasterClockXingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_spike_tile_tlMasterClockXingIn_d_bits_param = coupler_from_spike_tile_tlMasterClockXingOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_spike_tile_tlMasterClockXingIn_d_bits_size = coupler_from_spike_tile_tlMasterClockXingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_spike_tile_tlMasterClockXingIn_d_bits_source = coupler_from_spike_tile_tlMasterClockXingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_spike_tile_tlMasterClockXingIn_d_bits_sink = coupler_from_spike_tile_tlMasterClockXingOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_spike_tile_tlMasterClockXingIn_d_bits_denied = coupler_from_spike_tile_tlMasterClockXingOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_spike_tile_tlMasterClockXingIn_d_bits_data = coupler_from_spike_tile_tlMasterClockXingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_spike_tile_tlMasterClockXingIn_d_bits_corrupt = coupler_from_spike_tile_tlMasterClockXingOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_spike_tile_no_bufferIn_e_valid = coupler_from_spike_tile_tlMasterClockXingOut_e_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_spike_tile_no_bufferIn_e_bits_sink = coupler_from_spike_tile_tlMasterClockXingOut_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_spike_tile_auto_tl_master_clock_xing_in_a_ready = coupler_from_spike_tile_tlMasterClockXingIn_a_ready; // @[MixedNode.scala:551:17] assign coupler_from_spike_tile_tlMasterClockXingOut_a_valid = coupler_from_spike_tile_tlMasterClockXingIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_spike_tile_tlMasterClockXingOut_a_bits_opcode = coupler_from_spike_tile_tlMasterClockXingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_spike_tile_tlMasterClockXingOut_a_bits_param = coupler_from_spike_tile_tlMasterClockXingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_spike_tile_tlMasterClockXingOut_a_bits_size = coupler_from_spike_tile_tlMasterClockXingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_spike_tile_tlMasterClockXingOut_a_bits_source = coupler_from_spike_tile_tlMasterClockXingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_spike_tile_tlMasterClockXingOut_a_bits_address = coupler_from_spike_tile_tlMasterClockXingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_spike_tile_tlMasterClockXingOut_a_bits_mask = coupler_from_spike_tile_tlMasterClockXingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_spike_tile_tlMasterClockXingOut_a_bits_data = coupler_from_spike_tile_tlMasterClockXingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_spike_tile_tlMasterClockXingOut_a_bits_corrupt = coupler_from_spike_tile_tlMasterClockXingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_spike_tile_tlMasterClockXingOut_b_ready = coupler_from_spike_tile_tlMasterClockXingIn_b_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_spike_tile_auto_tl_master_clock_xing_in_b_valid = coupler_from_spike_tile_tlMasterClockXingIn_b_valid; // @[MixedNode.scala:551:17] assign coupler_from_spike_tile_auto_tl_master_clock_xing_in_b_bits_param = coupler_from_spike_tile_tlMasterClockXingIn_b_bits_param; // @[MixedNode.scala:551:17] assign coupler_from_spike_tile_auto_tl_master_clock_xing_in_b_bits_address = coupler_from_spike_tile_tlMasterClockXingIn_b_bits_address; // @[MixedNode.scala:551:17] assign coupler_from_spike_tile_auto_tl_master_clock_xing_in_c_ready = coupler_from_spike_tile_tlMasterClockXingIn_c_ready; // @[MixedNode.scala:551:17] assign coupler_from_spike_tile_tlMasterClockXingOut_c_valid = coupler_from_spike_tile_tlMasterClockXingIn_c_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_spike_tile_tlMasterClockXingOut_c_bits_opcode = coupler_from_spike_tile_tlMasterClockXingIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_spike_tile_tlMasterClockXingOut_c_bits_param = coupler_from_spike_tile_tlMasterClockXingIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_spike_tile_tlMasterClockXingOut_c_bits_size = coupler_from_spike_tile_tlMasterClockXingIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_spike_tile_tlMasterClockXingOut_c_bits_source = coupler_from_spike_tile_tlMasterClockXingIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_spike_tile_tlMasterClockXingOut_c_bits_address = coupler_from_spike_tile_tlMasterClockXingIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_spike_tile_tlMasterClockXingOut_c_bits_data = coupler_from_spike_tile_tlMasterClockXingIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_spike_tile_tlMasterClockXingOut_c_bits_corrupt = coupler_from_spike_tile_tlMasterClockXingIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_spike_tile_tlMasterClockXingOut_d_ready = coupler_from_spike_tile_tlMasterClockXingIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_spike_tile_auto_tl_master_clock_xing_in_d_valid = coupler_from_spike_tile_tlMasterClockXingIn_d_valid; // @[MixedNode.scala:551:17] assign coupler_from_spike_tile_auto_tl_master_clock_xing_in_d_bits_opcode = coupler_from_spike_tile_tlMasterClockXingIn_d_bits_opcode; // @[MixedNode.scala:551:17] assign coupler_from_spike_tile_auto_tl_master_clock_xing_in_d_bits_param = coupler_from_spike_tile_tlMasterClockXingIn_d_bits_param; // @[MixedNode.scala:551:17] assign coupler_from_spike_tile_auto_tl_master_clock_xing_in_d_bits_size = coupler_from_spike_tile_tlMasterClockXingIn_d_bits_size; // @[MixedNode.scala:551:17] assign coupler_from_spike_tile_auto_tl_master_clock_xing_in_d_bits_source = coupler_from_spike_tile_tlMasterClockXingIn_d_bits_source; // @[MixedNode.scala:551:17] assign coupler_from_spike_tile_auto_tl_master_clock_xing_in_d_bits_sink = coupler_from_spike_tile_tlMasterClockXingIn_d_bits_sink; // @[MixedNode.scala:551:17] assign coupler_from_spike_tile_auto_tl_master_clock_xing_in_d_bits_denied = coupler_from_spike_tile_tlMasterClockXingIn_d_bits_denied; // @[MixedNode.scala:551:17] assign coupler_from_spike_tile_auto_tl_master_clock_xing_in_d_bits_data = coupler_from_spike_tile_tlMasterClockXingIn_d_bits_data; // @[MixedNode.scala:551:17] assign coupler_from_spike_tile_auto_tl_master_clock_xing_in_d_bits_corrupt = coupler_from_spike_tile_tlMasterClockXingIn_d_bits_corrupt; // @[MixedNode.scala:551:17] assign coupler_from_spike_tile_tlMasterClockXingOut_e_valid = coupler_from_spike_tile_tlMasterClockXingIn_e_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_spike_tile_tlMasterClockXingOut_e_bits_sink = coupler_from_spike_tile_tlMasterClockXingIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign childClock = clockSinkNodeIn_clock; // @[MixedNode.scala:551:17] assign childReset = clockSinkNodeIn_reset; // @[MixedNode.scala:551:17] wire fixer__T_1 = fixer_a_first & fixer__a_first_T; // @[Decoupled.scala:51:35] wire fixer__T_3 = fixer_d_first & fixer__T_2; // @[Decoupled.scala:51:35] wire fixer__T_31 = fixer_a_first_1 & fixer__a_first_T_1; // @[Decoupled.scala:51:35] wire fixer__T_33 = fixer_d_first_1 & fixer__T_32; // @[Decoupled.scala:51:35] always @(posedge childClock) begin // @[LazyModuleImp.scala:155:31] if (childReset) begin // @[LazyModuleImp.scala:155:31, :158:31] fixer_a_first_counter <= 9'h0; // @[Edges.scala:229:27] fixer_d_first_counter <= 9'h0; // @[Edges.scala:229:27] fixer_flight_0 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_1 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_2 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_3 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_4 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_5 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_6 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_7 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_8 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_9 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_10 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_11 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_12 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_13 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_14 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_15 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_16 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_SourceIdFIFOed <= 17'h0; // @[FIFOFixer.scala:115:35] fixer_a_first_counter_1 <= 9'h0; // @[Edges.scala:229:27] fixer_d_first_counter_1 <= 9'h0; // @[Edges.scala:229:27] fixer_flight_1_0 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_1_1 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_1_2 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_SourceIdFIFOed_1 <= 3'h0; // @[FIFOFixer.scala:115:35] end else begin // @[LazyModuleImp.scala:155:31] if (fixer__a_first_T) // @[Decoupled.scala:51:35] fixer_a_first_counter <= fixer__a_first_counter_T; // @[Edges.scala:229:27, :236:21] if (fixer__d_first_T) // @[Decoupled.scala:51:35] fixer_d_first_counter <= fixer__d_first_counter_T; // @[Edges.scala:229:27, :236:21] fixer_flight_0 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h0) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h0 ? fixer__flight_T : fixer_flight_0); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] fixer_flight_1 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h1) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h1 ? fixer__flight_T : fixer_flight_1); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] fixer_flight_2 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h2) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h2 ? fixer__flight_T : fixer_flight_2); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] fixer_flight_3 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h3) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h3 ? fixer__flight_T : fixer_flight_3); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] fixer_flight_4 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h4) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h4 ? fixer__flight_T : fixer_flight_4); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] fixer_flight_5 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h5) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h5 ? fixer__flight_T : fixer_flight_5); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] fixer_flight_6 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h6) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h6 ? fixer__flight_T : fixer_flight_6); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] fixer_flight_7 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h7) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h7 ? fixer__flight_T : fixer_flight_7); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] fixer_flight_8 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h8) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h8 ? fixer__flight_T : fixer_flight_8); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] fixer_flight_9 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h9) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h9 ? fixer__flight_T : fixer_flight_9); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] fixer_flight_10 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'hA) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'hA ? fixer__flight_T : fixer_flight_10); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] fixer_flight_11 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'hB) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'hB ? fixer__flight_T : fixer_flight_11); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] fixer_flight_12 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'hC) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'hC ? fixer__flight_T : fixer_flight_12); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] fixer_flight_13 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'hD) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'hD ? fixer__flight_T : fixer_flight_13); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] fixer_flight_14 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'hE) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'hE ? fixer__flight_T : fixer_flight_14); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] fixer_flight_15 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'hF) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'hF ? fixer__flight_T : fixer_flight_15); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] fixer_flight_16 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 5'h10) & (fixer__T_1 & fixer_anonIn_a_bits_source == 5'h10 ? fixer__flight_T : fixer_flight_16); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] fixer_SourceIdFIFOed <= fixer__SourceIdFIFOed_T; // @[FIFOFixer.scala:115:35, :126:40] if (fixer__a_first_T_1) // @[Decoupled.scala:51:35] fixer_a_first_counter_1 <= fixer__a_first_counter_T_1; // @[Edges.scala:229:27, :236:21] if (fixer__d_first_T_2) // @[Decoupled.scala:51:35] fixer_d_first_counter_1 <= fixer__d_first_counter_T_1; // @[Edges.scala:229:27, :236:21] fixer_flight_1_0 <= ~(fixer__T_33 & fixer_x1_anonIn_d_bits_source == 2'h0) & (fixer__T_31 & fixer_x1_anonIn_a_bits_source == 2'h0 ? fixer__flight_T_1 : fixer_flight_1_0); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] fixer_flight_1_1 <= ~(fixer__T_33 & fixer_x1_anonIn_d_bits_source == 2'h1) & (fixer__T_31 & fixer_x1_anonIn_a_bits_source == 2'h1 ? fixer__flight_T_1 : fixer_flight_1_1); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] fixer_flight_1_2 <= ~(fixer__T_33 & fixer_x1_anonIn_d_bits_source == 2'h2) & (fixer__T_31 & fixer_x1_anonIn_a_bits_source == 2'h2 ? fixer__flight_T_1 : fixer_flight_1_2); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] fixer_SourceIdFIFOed_1 <= fixer__SourceIdFIFOed_T_1; // @[FIFOFixer.scala:115:35, :126:40] end always @(posedge) FixedClockBroadcast_4 fixedClockNode ( // @[ClockGroup.scala:115:114] .auto_anon_in_clock (clockGroup_auto_out_clock), // @[ClockGroup.scala:24:9] .auto_anon_in_reset (clockGroup_auto_out_reset), // @[ClockGroup.scala:24:9] .auto_anon_out_3_clock (auto_fixedClockNode_anon_out_2_clock_0), .auto_anon_out_3_reset (auto_fixedClockNode_anon_out_2_reset_0), .auto_anon_out_2_clock (auto_fixedClockNode_anon_out_1_clock_0), .auto_anon_out_2_reset (auto_fixedClockNode_anon_out_1_reset_0), .auto_anon_out_1_clock (auto_fixedClockNode_anon_out_0_clock_0), .auto_anon_out_1_reset (auto_fixedClockNode_anon_out_0_reset_0), .auto_anon_out_0_clock (clockSinkNodeIn_clock), .auto_anon_out_0_reset (clockSinkNodeIn_reset) ); // @[ClockGroup.scala:115:114] TLXbar_sbus_i2_o2_a32d64s6k3z4c system_bus_xbar ( // @[SystemBus.scala:47:43] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_anon_in_1_a_ready (fixer_auto_anon_out_1_a_ready), .auto_anon_in_1_a_valid (fixer_auto_anon_out_1_a_valid), // @[FIFOFixer.scala:50:9] .auto_anon_in_1_a_bits_opcode (fixer_auto_anon_out_1_a_bits_opcode), // @[FIFOFixer.scala:50:9] .auto_anon_in_1_a_bits_param (fixer_auto_anon_out_1_a_bits_param), // @[FIFOFixer.scala:50:9] .auto_anon_in_1_a_bits_size (fixer_auto_anon_out_1_a_bits_size), // @[FIFOFixer.scala:50:9] .auto_anon_in_1_a_bits_source (fixer_auto_anon_out_1_a_bits_source), // @[FIFOFixer.scala:50:9] .auto_anon_in_1_a_bits_address (fixer_auto_anon_out_1_a_bits_address), // @[FIFOFixer.scala:50:9] .auto_anon_in_1_a_bits_mask (fixer_auto_anon_out_1_a_bits_mask), // @[FIFOFixer.scala:50:9] .auto_anon_in_1_a_bits_data (fixer_auto_anon_out_1_a_bits_data), // @[FIFOFixer.scala:50:9] .auto_anon_in_1_a_bits_corrupt (fixer_auto_anon_out_1_a_bits_corrupt), // @[FIFOFixer.scala:50:9] .auto_anon_in_1_b_ready (fixer_auto_anon_out_1_b_ready), // @[FIFOFixer.scala:50:9] .auto_anon_in_1_b_valid (fixer_auto_anon_out_1_b_valid), .auto_anon_in_1_b_bits_param (fixer_auto_anon_out_1_b_bits_param), .auto_anon_in_1_b_bits_address (fixer_auto_anon_out_1_b_bits_address), .auto_anon_in_1_c_ready (fixer_auto_anon_out_1_c_ready), .auto_anon_in_1_c_valid (fixer_auto_anon_out_1_c_valid), // @[FIFOFixer.scala:50:9] .auto_anon_in_1_c_bits_opcode (fixer_auto_anon_out_1_c_bits_opcode), // @[FIFOFixer.scala:50:9] .auto_anon_in_1_c_bits_param (fixer_auto_anon_out_1_c_bits_param), // @[FIFOFixer.scala:50:9] .auto_anon_in_1_c_bits_size (fixer_auto_anon_out_1_c_bits_size), // @[FIFOFixer.scala:50:9] .auto_anon_in_1_c_bits_source (fixer_auto_anon_out_1_c_bits_source), // @[FIFOFixer.scala:50:9] .auto_anon_in_1_c_bits_address (fixer_auto_anon_out_1_c_bits_address), // @[FIFOFixer.scala:50:9] .auto_anon_in_1_c_bits_data (fixer_auto_anon_out_1_c_bits_data), // @[FIFOFixer.scala:50:9] .auto_anon_in_1_c_bits_corrupt (fixer_auto_anon_out_1_c_bits_corrupt), // @[FIFOFixer.scala:50:9] .auto_anon_in_1_d_ready (fixer_auto_anon_out_1_d_ready), // @[FIFOFixer.scala:50:9] .auto_anon_in_1_d_valid (fixer_auto_anon_out_1_d_valid), .auto_anon_in_1_d_bits_opcode (fixer_auto_anon_out_1_d_bits_opcode), .auto_anon_in_1_d_bits_param (fixer_auto_anon_out_1_d_bits_param), .auto_anon_in_1_d_bits_size (fixer_auto_anon_out_1_d_bits_size), .auto_anon_in_1_d_bits_source (fixer_auto_anon_out_1_d_bits_source), .auto_anon_in_1_d_bits_sink (fixer_auto_anon_out_1_d_bits_sink), .auto_anon_in_1_d_bits_denied (fixer_auto_anon_out_1_d_bits_denied), .auto_anon_in_1_d_bits_data (fixer_auto_anon_out_1_d_bits_data), .auto_anon_in_1_d_bits_corrupt (fixer_auto_anon_out_1_d_bits_corrupt), .auto_anon_in_1_e_valid (fixer_auto_anon_out_1_e_valid), // @[FIFOFixer.scala:50:9] .auto_anon_in_1_e_bits_sink (fixer_auto_anon_out_1_e_bits_sink), // @[FIFOFixer.scala:50:9] .auto_anon_in_0_a_ready (fixer_auto_anon_out_0_a_ready), .auto_anon_in_0_a_valid (fixer_auto_anon_out_0_a_valid), // @[FIFOFixer.scala:50:9] .auto_anon_in_0_a_bits_opcode (fixer_auto_anon_out_0_a_bits_opcode), // @[FIFOFixer.scala:50:9] .auto_anon_in_0_a_bits_param (fixer_auto_anon_out_0_a_bits_param), // @[FIFOFixer.scala:50:9] .auto_anon_in_0_a_bits_size (fixer_auto_anon_out_0_a_bits_size), // @[FIFOFixer.scala:50:9] .auto_anon_in_0_a_bits_source (fixer_auto_anon_out_0_a_bits_source), // @[FIFOFixer.scala:50:9] .auto_anon_in_0_a_bits_address (fixer_auto_anon_out_0_a_bits_address), // @[FIFOFixer.scala:50:9] .auto_anon_in_0_a_bits_mask (fixer_auto_anon_out_0_a_bits_mask), // @[FIFOFixer.scala:50:9] .auto_anon_in_0_a_bits_data (fixer_auto_anon_out_0_a_bits_data), // @[FIFOFixer.scala:50:9] .auto_anon_in_0_a_bits_corrupt (fixer_auto_anon_out_0_a_bits_corrupt), // @[FIFOFixer.scala:50:9] .auto_anon_in_0_d_ready (fixer_auto_anon_out_0_d_ready), // @[FIFOFixer.scala:50:9] .auto_anon_in_0_d_valid (fixer_auto_anon_out_0_d_valid), .auto_anon_in_0_d_bits_opcode (fixer_auto_anon_out_0_d_bits_opcode), .auto_anon_in_0_d_bits_param (fixer_auto_anon_out_0_d_bits_param), .auto_anon_in_0_d_bits_size (fixer_auto_anon_out_0_d_bits_size), .auto_anon_in_0_d_bits_source (fixer_auto_anon_out_0_d_bits_source), .auto_anon_in_0_d_bits_sink (fixer_auto_anon_out_0_d_bits_sink), .auto_anon_in_0_d_bits_denied (fixer_auto_anon_out_0_d_bits_denied), .auto_anon_in_0_d_bits_data (fixer_auto_anon_out_0_d_bits_data), .auto_anon_in_0_d_bits_corrupt (fixer_auto_anon_out_0_d_bits_corrupt), .auto_anon_out_1_a_ready (coupler_to_bus_named_coh_auto_widget_anon_in_a_ready), // @[LazyModuleImp.scala:138:7] .auto_anon_out_1_a_valid (coupler_to_bus_named_coh_auto_widget_anon_in_a_valid), .auto_anon_out_1_a_bits_opcode (coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_opcode), .auto_anon_out_1_a_bits_param (coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_param), .auto_anon_out_1_a_bits_size (coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_size), .auto_anon_out_1_a_bits_source (coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_source), .auto_anon_out_1_a_bits_address (coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_address), .auto_anon_out_1_a_bits_mask (coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_mask), .auto_anon_out_1_a_bits_data (coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_data), .auto_anon_out_1_a_bits_corrupt (coupler_to_bus_named_coh_auto_widget_anon_in_a_bits_corrupt), .auto_anon_out_1_b_ready (coupler_to_bus_named_coh_auto_widget_anon_in_b_ready), .auto_anon_out_1_b_valid (coupler_to_bus_named_coh_auto_widget_anon_in_b_valid), // @[LazyModuleImp.scala:138:7] .auto_anon_out_1_b_bits_param (coupler_to_bus_named_coh_auto_widget_anon_in_b_bits_param), // @[LazyModuleImp.scala:138:7] .auto_anon_out_1_b_bits_address (coupler_to_bus_named_coh_auto_widget_anon_in_b_bits_address), // @[LazyModuleImp.scala:138:7] .auto_anon_out_1_c_ready (coupler_to_bus_named_coh_auto_widget_anon_in_c_ready), // @[LazyModuleImp.scala:138:7] .auto_anon_out_1_c_valid (coupler_to_bus_named_coh_auto_widget_anon_in_c_valid), .auto_anon_out_1_c_bits_opcode (coupler_to_bus_named_coh_auto_widget_anon_in_c_bits_opcode), .auto_anon_out_1_c_bits_param (coupler_to_bus_named_coh_auto_widget_anon_in_c_bits_param), .auto_anon_out_1_c_bits_size (coupler_to_bus_named_coh_auto_widget_anon_in_c_bits_size), .auto_anon_out_1_c_bits_source (coupler_to_bus_named_coh_auto_widget_anon_in_c_bits_source), .auto_anon_out_1_c_bits_address (coupler_to_bus_named_coh_auto_widget_anon_in_c_bits_address), .auto_anon_out_1_c_bits_data (coupler_to_bus_named_coh_auto_widget_anon_in_c_bits_data), .auto_anon_out_1_c_bits_corrupt (coupler_to_bus_named_coh_auto_widget_anon_in_c_bits_corrupt), .auto_anon_out_1_d_ready (coupler_to_bus_named_coh_auto_widget_anon_in_d_ready), .auto_anon_out_1_d_valid (coupler_to_bus_named_coh_auto_widget_anon_in_d_valid), // @[LazyModuleImp.scala:138:7] .auto_anon_out_1_d_bits_opcode (coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_opcode), // @[LazyModuleImp.scala:138:7] .auto_anon_out_1_d_bits_param (coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_param), // @[LazyModuleImp.scala:138:7] .auto_anon_out_1_d_bits_size (coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_size), // @[LazyModuleImp.scala:138:7] .auto_anon_out_1_d_bits_source (coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_source), // @[LazyModuleImp.scala:138:7] .auto_anon_out_1_d_bits_sink (coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_sink), // @[LazyModuleImp.scala:138:7] .auto_anon_out_1_d_bits_denied (coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_denied), // @[LazyModuleImp.scala:138:7] .auto_anon_out_1_d_bits_data (coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_data), // @[LazyModuleImp.scala:138:7] .auto_anon_out_1_d_bits_corrupt (coupler_to_bus_named_coh_auto_widget_anon_in_d_bits_corrupt), // @[LazyModuleImp.scala:138:7] .auto_anon_out_1_e_valid (coupler_to_bus_named_coh_auto_widget_anon_in_e_valid), .auto_anon_out_1_e_bits_sink (coupler_to_bus_named_coh_auto_widget_anon_in_e_bits_sink), .auto_anon_out_0_a_ready (coupler_to_bus_named_cbus_auto_widget_anon_in_a_ready), // @[LazyModuleImp.scala:138:7] .auto_anon_out_0_a_valid (coupler_to_bus_named_cbus_auto_widget_anon_in_a_valid), .auto_anon_out_0_a_bits_opcode (coupler_to_bus_named_cbus_auto_widget_anon_in_a_bits_opcode), .auto_anon_out_0_a_bits_param (coupler_to_bus_named_cbus_auto_widget_anon_in_a_bits_param), .auto_anon_out_0_a_bits_size (coupler_to_bus_named_cbus_auto_widget_anon_in_a_bits_size), .auto_anon_out_0_a_bits_source (coupler_to_bus_named_cbus_auto_widget_anon_in_a_bits_source), .auto_anon_out_0_a_bits_address (coupler_to_bus_named_cbus_auto_widget_anon_in_a_bits_address), .auto_anon_out_0_a_bits_mask (coupler_to_bus_named_cbus_auto_widget_anon_in_a_bits_mask), .auto_anon_out_0_a_bits_data (coupler_to_bus_named_cbus_auto_widget_anon_in_a_bits_data), .auto_anon_out_0_a_bits_corrupt (coupler_to_bus_named_cbus_auto_widget_anon_in_a_bits_corrupt), .auto_anon_out_0_d_ready (coupler_to_bus_named_cbus_auto_widget_anon_in_d_ready), .auto_anon_out_0_d_valid (coupler_to_bus_named_cbus_auto_widget_anon_in_d_valid), // @[LazyModuleImp.scala:138:7] .auto_anon_out_0_d_bits_opcode (coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_opcode), // @[LazyModuleImp.scala:138:7] .auto_anon_out_0_d_bits_param (coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_param), // @[LazyModuleImp.scala:138:7] .auto_anon_out_0_d_bits_size (coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_size), // @[LazyModuleImp.scala:138:7] .auto_anon_out_0_d_bits_source (coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_source), // @[LazyModuleImp.scala:138:7] .auto_anon_out_0_d_bits_sink (coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_sink), // @[LazyModuleImp.scala:138:7] .auto_anon_out_0_d_bits_denied (coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_denied), // @[LazyModuleImp.scala:138:7] .auto_anon_out_0_d_bits_data (coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_data), // @[LazyModuleImp.scala:138:7] .auto_anon_out_0_d_bits_corrupt (coupler_to_bus_named_cbus_auto_widget_anon_in_d_bits_corrupt) // @[LazyModuleImp.scala:138:7] ); // @[SystemBus.scala:47:43] assign auto_coupler_from_spike_tile_tl_master_clock_xing_in_a_ready = auto_coupler_from_spike_tile_tl_master_clock_xing_in_a_ready_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_spike_tile_tl_master_clock_xing_in_b_valid = auto_coupler_from_spike_tile_tl_master_clock_xing_in_b_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_spike_tile_tl_master_clock_xing_in_b_bits_param = auto_coupler_from_spike_tile_tl_master_clock_xing_in_b_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_spike_tile_tl_master_clock_xing_in_b_bits_address = auto_coupler_from_spike_tile_tl_master_clock_xing_in_b_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_spike_tile_tl_master_clock_xing_in_c_ready = auto_coupler_from_spike_tile_tl_master_clock_xing_in_c_ready_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_spike_tile_tl_master_clock_xing_in_d_valid = auto_coupler_from_spike_tile_tl_master_clock_xing_in_d_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_spike_tile_tl_master_clock_xing_in_d_bits_opcode = auto_coupler_from_spike_tile_tl_master_clock_xing_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_spike_tile_tl_master_clock_xing_in_d_bits_param = auto_coupler_from_spike_tile_tl_master_clock_xing_in_d_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_spike_tile_tl_master_clock_xing_in_d_bits_size = auto_coupler_from_spike_tile_tl_master_clock_xing_in_d_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_spike_tile_tl_master_clock_xing_in_d_bits_source = auto_coupler_from_spike_tile_tl_master_clock_xing_in_d_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_spike_tile_tl_master_clock_xing_in_d_bits_sink = auto_coupler_from_spike_tile_tl_master_clock_xing_in_d_bits_sink_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_spike_tile_tl_master_clock_xing_in_d_bits_denied = auto_coupler_from_spike_tile_tl_master_clock_xing_in_d_bits_denied_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_spike_tile_tl_master_clock_xing_in_d_bits_data = auto_coupler_from_spike_tile_tl_master_clock_xing_in_d_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_spike_tile_tl_master_clock_xing_in_d_bits_corrupt = auto_coupler_from_spike_tile_tl_master_clock_xing_in_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_a_valid = auto_coupler_to_bus_named_coh_widget_anon_out_a_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_opcode = auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_param = auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_size = auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_source = auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_address = auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_mask = auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_data = auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_corrupt = auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_b_ready = auto_coupler_to_bus_named_coh_widget_anon_out_b_ready_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_c_valid = auto_coupler_to_bus_named_coh_widget_anon_out_c_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_opcode = auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_param = auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_size = auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_source = auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_address = auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_data = auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_corrupt = auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_d_ready = auto_coupler_to_bus_named_coh_widget_anon_out_d_ready_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_e_valid = auto_coupler_to_bus_named_coh_widget_anon_out_e_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_coh_widget_anon_out_e_bits_sink = auto_coupler_to_bus_named_coh_widget_anon_out_e_bits_sink_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_bus_named_fbus_bus_xing_in_a_ready = auto_coupler_from_bus_named_fbus_bus_xing_in_a_ready_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_bus_named_fbus_bus_xing_in_d_valid = auto_coupler_from_bus_named_fbus_bus_xing_in_d_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_opcode = auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_param = auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_size = auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_source = auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_sink = auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_sink_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_denied = auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_denied_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_data = auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_corrupt = auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_cbus_bus_xing_out_a_valid = auto_coupler_to_bus_named_cbus_bus_xing_out_a_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_opcode = auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_param = auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_size = auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_source = auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_address = auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_mask = auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_data = auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_corrupt = auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_cbus_bus_xing_out_d_ready = auto_coupler_to_bus_named_cbus_bus_xing_out_d_ready_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_2_clock = auto_fixedClockNode_anon_out_2_clock_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_2_reset = auto_fixedClockNode_anon_out_2_reset_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_1_clock = auto_fixedClockNode_anon_out_1_clock_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_1_reset = auto_fixedClockNode_anon_out_1_reset_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_0_clock = auto_fixedClockNode_anon_out_0_clock_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_0_reset = auto_fixedClockNode_anon_out_0_reset_0; // @[ClockDomain.scala:14:9] assign auto_sbus_clock_groups_out_member_coh_0_clock = auto_sbus_clock_groups_out_member_coh_0_clock_0; // @[ClockDomain.scala:14:9] assign auto_sbus_clock_groups_out_member_coh_0_reset = auto_sbus_clock_groups_out_member_coh_0_reset_0; // @[ClockDomain.scala:14:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_41 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, b : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _source_ok_T_29 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _source_ok_T_30 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _source_ok_T_31 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_32 = eq(io.in.a.bits.source, UInt<6>(0h22)) wire _source_ok_WIRE : UInt<1>[13] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 connect _source_ok_WIRE[8], _source_ok_T_28 connect _source_ok_WIRE[9], _source_ok_T_29 connect _source_ok_WIRE[10], _source_ok_T_30 connect _source_ok_WIRE[11], _source_ok_T_31 connect _source_ok_WIRE[12], _source_ok_T_32 node _source_ok_T_33 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_34 = or(_source_ok_T_33, _source_ok_WIRE[2]) node _source_ok_T_35 = or(_source_ok_T_34, _source_ok_WIRE[3]) node _source_ok_T_36 = or(_source_ok_T_35, _source_ok_WIRE[4]) node _source_ok_T_37 = or(_source_ok_T_36, _source_ok_WIRE[5]) node _source_ok_T_38 = or(_source_ok_T_37, _source_ok_WIRE[6]) node _source_ok_T_39 = or(_source_ok_T_38, _source_ok_WIRE[7]) node _source_ok_T_40 = or(_source_ok_T_39, _source_ok_WIRE[8]) node _source_ok_T_41 = or(_source_ok_T_40, _source_ok_WIRE[9]) node _source_ok_T_42 = or(_source_ok_T_41, _source_ok_WIRE[10]) node _source_ok_T_43 = or(_source_ok_T_42, _source_ok_WIRE[11]) node source_ok = or(_source_ok_T_43, _source_ok_WIRE[12]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _T_88 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_89 = eq(_T_88, UInt<1>(0h0)) node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_89, _T_94) node _T_96 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_99 = cvt(_T_98) node _T_100 = and(_T_99, asSInt(UInt<1>(0h0))) node _T_101 = asSInt(_T_100) node _T_102 = eq(_T_101, asSInt(UInt<1>(0h0))) node _T_103 = or(_T_97, _T_102) node _T_104 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_105 = eq(_T_104, UInt<1>(0h0)) node _T_106 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_107 = cvt(_T_106) node _T_108 = and(_T_107, asSInt(UInt<1>(0h0))) node _T_109 = asSInt(_T_108) node _T_110 = eq(_T_109, asSInt(UInt<1>(0h0))) node _T_111 = or(_T_105, _T_110) node _T_112 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_113 = eq(_T_112, UInt<1>(0h0)) node _T_114 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_115 = cvt(_T_114) node _T_116 = and(_T_115, asSInt(UInt<1>(0h0))) node _T_117 = asSInt(_T_116) node _T_118 = eq(_T_117, asSInt(UInt<1>(0h0))) node _T_119 = or(_T_113, _T_118) node _T_120 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_121 = eq(_T_120, UInt<1>(0h0)) node _T_122 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_123 = cvt(_T_122) node _T_124 = and(_T_123, asSInt(UInt<1>(0h0))) node _T_125 = asSInt(_T_124) node _T_126 = eq(_T_125, asSInt(UInt<1>(0h0))) node _T_127 = or(_T_121, _T_126) node _T_128 = and(_T_11, _T_24) node _T_129 = and(_T_128, _T_37) node _T_130 = and(_T_129, _T_50) node _T_131 = and(_T_130, _T_63) node _T_132 = and(_T_131, _T_71) node _T_133 = and(_T_132, _T_79) node _T_134 = and(_T_133, _T_87) node _T_135 = and(_T_134, _T_95) node _T_136 = and(_T_135, _T_103) node _T_137 = and(_T_136, _T_111) node _T_138 = and(_T_137, _T_119) node _T_139 = and(_T_138, _T_127) node _T_140 = asUInt(reset) node _T_141 = eq(_T_140, UInt<1>(0h0)) when _T_141 : node _T_142 = eq(_T_139, UInt<1>(0h0)) when _T_142 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_139, UInt<1>(0h1), "") : assert_1 node _T_143 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_143 : node _T_144 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_145 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_146 = and(_T_144, _T_145) node _T_147 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_148 = shr(io.in.a.bits.source, 2) node _T_149 = eq(_T_148, UInt<1>(0h0)) node _T_150 = leq(UInt<1>(0h0), uncommonBits_4) node _T_151 = and(_T_149, _T_150) node _T_152 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_153 = and(_T_151, _T_152) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_154 = shr(io.in.a.bits.source, 2) node _T_155 = eq(_T_154, UInt<1>(0h1)) node _T_156 = leq(UInt<1>(0h0), uncommonBits_5) node _T_157 = and(_T_155, _T_156) node _T_158 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_159 = and(_T_157, _T_158) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_160 = shr(io.in.a.bits.source, 2) node _T_161 = eq(_T_160, UInt<2>(0h2)) node _T_162 = leq(UInt<1>(0h0), uncommonBits_6) node _T_163 = and(_T_161, _T_162) node _T_164 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_165 = and(_T_163, _T_164) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_166 = shr(io.in.a.bits.source, 2) node _T_167 = eq(_T_166, UInt<2>(0h3)) node _T_168 = leq(UInt<1>(0h0), uncommonBits_7) node _T_169 = and(_T_167, _T_168) node _T_170 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_171 = and(_T_169, _T_170) node _T_172 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_173 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_174 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_175 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_176 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_177 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_178 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_179 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_180 = or(_T_147, _T_153) node _T_181 = or(_T_180, _T_159) node _T_182 = or(_T_181, _T_165) node _T_183 = or(_T_182, _T_171) node _T_184 = or(_T_183, _T_172) node _T_185 = or(_T_184, _T_173) node _T_186 = or(_T_185, _T_174) node _T_187 = or(_T_186, _T_175) node _T_188 = or(_T_187, _T_176) node _T_189 = or(_T_188, _T_177) node _T_190 = or(_T_189, _T_178) node _T_191 = or(_T_190, _T_179) node _T_192 = and(_T_146, _T_191) node _T_193 = or(UInt<1>(0h0), _T_192) node _T_194 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_195 = or(UInt<1>(0h0), _T_194) node _T_196 = xor(io.in.a.bits.address, UInt<28>(0h8000040)) node _T_197 = cvt(_T_196) node _T_198 = and(_T_197, asSInt(UInt<17>(0h100c0))) node _T_199 = asSInt(_T_198) node _T_200 = eq(_T_199, asSInt(UInt<1>(0h0))) node _T_201 = xor(io.in.a.bits.address, UInt<32>(0h80000040)) node _T_202 = cvt(_T_201) node _T_203 = and(_T_202, asSInt(UInt<29>(0h100000c0))) node _T_204 = asSInt(_T_203) node _T_205 = eq(_T_204, asSInt(UInt<1>(0h0))) node _T_206 = or(_T_200, _T_205) node _T_207 = and(_T_195, _T_206) node _T_208 = or(UInt<1>(0h0), _T_207) node _T_209 = and(_T_193, _T_208) node _T_210 = asUInt(reset) node _T_211 = eq(_T_210, UInt<1>(0h0)) when _T_211 : node _T_212 = eq(_T_209, UInt<1>(0h0)) when _T_212 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_209, UInt<1>(0h1), "") : assert_2 node _T_213 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_214 = shr(io.in.a.bits.source, 2) node _T_215 = eq(_T_214, UInt<1>(0h0)) node _T_216 = leq(UInt<1>(0h0), uncommonBits_8) node _T_217 = and(_T_215, _T_216) node _T_218 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_219 = and(_T_217, _T_218) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_220 = shr(io.in.a.bits.source, 2) node _T_221 = eq(_T_220, UInt<1>(0h1)) node _T_222 = leq(UInt<1>(0h0), uncommonBits_9) node _T_223 = and(_T_221, _T_222) node _T_224 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_225 = and(_T_223, _T_224) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_226 = shr(io.in.a.bits.source, 2) node _T_227 = eq(_T_226, UInt<2>(0h2)) node _T_228 = leq(UInt<1>(0h0), uncommonBits_10) node _T_229 = and(_T_227, _T_228) node _T_230 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_231 = and(_T_229, _T_230) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_232 = shr(io.in.a.bits.source, 2) node _T_233 = eq(_T_232, UInt<2>(0h3)) node _T_234 = leq(UInt<1>(0h0), uncommonBits_11) node _T_235 = and(_T_233, _T_234) node _T_236 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_237 = and(_T_235, _T_236) node _T_238 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_239 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_240 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_241 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_242 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_243 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_244 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_245 = eq(io.in.a.bits.source, UInt<6>(0h22)) wire _WIRE : UInt<1>[13] connect _WIRE[0], _T_213 connect _WIRE[1], _T_219 connect _WIRE[2], _T_225 connect _WIRE[3], _T_231 connect _WIRE[4], _T_237 connect _WIRE[5], _T_238 connect _WIRE[6], _T_239 connect _WIRE[7], _T_240 connect _WIRE[8], _T_241 connect _WIRE[9], _T_242 connect _WIRE[10], _T_243 connect _WIRE[11], _T_244 connect _WIRE[12], _T_245 node _T_246 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_247 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_248 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_249 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_250 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_251 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_252 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_253 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_254 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_255 = mux(_WIRE[5], _T_246, UInt<1>(0h0)) node _T_256 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_257 = mux(_WIRE[7], _T_247, UInt<1>(0h0)) node _T_258 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_259 = mux(_WIRE[9], _T_248, UInt<1>(0h0)) node _T_260 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_261 = mux(_WIRE[11], _T_249, UInt<1>(0h0)) node _T_262 = mux(_WIRE[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_263 = or(_T_250, _T_251) node _T_264 = or(_T_263, _T_252) node _T_265 = or(_T_264, _T_253) node _T_266 = or(_T_265, _T_254) node _T_267 = or(_T_266, _T_255) node _T_268 = or(_T_267, _T_256) node _T_269 = or(_T_268, _T_257) node _T_270 = or(_T_269, _T_258) node _T_271 = or(_T_270, _T_259) node _T_272 = or(_T_271, _T_260) node _T_273 = or(_T_272, _T_261) node _T_274 = or(_T_273, _T_262) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_274 node _T_275 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_276 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_277 = and(_T_275, _T_276) node _T_278 = or(UInt<1>(0h0), _T_277) node _T_279 = xor(io.in.a.bits.address, UInt<28>(0h8000040)) node _T_280 = cvt(_T_279) node _T_281 = and(_T_280, asSInt(UInt<17>(0h100c0))) node _T_282 = asSInt(_T_281) node _T_283 = eq(_T_282, asSInt(UInt<1>(0h0))) node _T_284 = xor(io.in.a.bits.address, UInt<32>(0h80000040)) node _T_285 = cvt(_T_284) node _T_286 = and(_T_285, asSInt(UInt<29>(0h100000c0))) node _T_287 = asSInt(_T_286) node _T_288 = eq(_T_287, asSInt(UInt<1>(0h0))) node _T_289 = or(_T_283, _T_288) node _T_290 = and(_T_278, _T_289) node _T_291 = or(UInt<1>(0h0), _T_290) node _T_292 = and(_WIRE_1, _T_291) node _T_293 = asUInt(reset) node _T_294 = eq(_T_293, UInt<1>(0h0)) when _T_294 : node _T_295 = eq(_T_292, UInt<1>(0h0)) when _T_295 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_292, UInt<1>(0h1), "") : assert_3 node _T_296 = asUInt(reset) node _T_297 = eq(_T_296, UInt<1>(0h0)) when _T_297 : node _T_298 = eq(source_ok, UInt<1>(0h0)) when _T_298 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_299 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_T_299, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_299, UInt<1>(0h1), "") : assert_5 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(is_aligned, UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_306 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_307 = asUInt(reset) node _T_308 = eq(_T_307, UInt<1>(0h0)) when _T_308 : node _T_309 = eq(_T_306, UInt<1>(0h0)) when _T_309 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_306, UInt<1>(0h1), "") : assert_7 node _T_310 = not(io.in.a.bits.mask) node _T_311 = eq(_T_310, UInt<1>(0h0)) node _T_312 = asUInt(reset) node _T_313 = eq(_T_312, UInt<1>(0h0)) when _T_313 : node _T_314 = eq(_T_311, UInt<1>(0h0)) when _T_314 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_311, UInt<1>(0h1), "") : assert_8 node _T_315 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_316 = asUInt(reset) node _T_317 = eq(_T_316, UInt<1>(0h0)) when _T_317 : node _T_318 = eq(_T_315, UInt<1>(0h0)) when _T_318 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_315, UInt<1>(0h1), "") : assert_9 node _T_319 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_319 : node _T_320 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_321 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_322 = and(_T_320, _T_321) node _T_323 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_324 = shr(io.in.a.bits.source, 2) node _T_325 = eq(_T_324, UInt<1>(0h0)) node _T_326 = leq(UInt<1>(0h0), uncommonBits_12) node _T_327 = and(_T_325, _T_326) node _T_328 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_329 = and(_T_327, _T_328) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_330 = shr(io.in.a.bits.source, 2) node _T_331 = eq(_T_330, UInt<1>(0h1)) node _T_332 = leq(UInt<1>(0h0), uncommonBits_13) node _T_333 = and(_T_331, _T_332) node _T_334 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_335 = and(_T_333, _T_334) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_336 = shr(io.in.a.bits.source, 2) node _T_337 = eq(_T_336, UInt<2>(0h2)) node _T_338 = leq(UInt<1>(0h0), uncommonBits_14) node _T_339 = and(_T_337, _T_338) node _T_340 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_341 = and(_T_339, _T_340) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_342 = shr(io.in.a.bits.source, 2) node _T_343 = eq(_T_342, UInt<2>(0h3)) node _T_344 = leq(UInt<1>(0h0), uncommonBits_15) node _T_345 = and(_T_343, _T_344) node _T_346 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_347 = and(_T_345, _T_346) node _T_348 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_349 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_350 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_351 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_352 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_353 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_354 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_355 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_356 = or(_T_323, _T_329) node _T_357 = or(_T_356, _T_335) node _T_358 = or(_T_357, _T_341) node _T_359 = or(_T_358, _T_347) node _T_360 = or(_T_359, _T_348) node _T_361 = or(_T_360, _T_349) node _T_362 = or(_T_361, _T_350) node _T_363 = or(_T_362, _T_351) node _T_364 = or(_T_363, _T_352) node _T_365 = or(_T_364, _T_353) node _T_366 = or(_T_365, _T_354) node _T_367 = or(_T_366, _T_355) node _T_368 = and(_T_322, _T_367) node _T_369 = or(UInt<1>(0h0), _T_368) node _T_370 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_371 = or(UInt<1>(0h0), _T_370) node _T_372 = xor(io.in.a.bits.address, UInt<28>(0h8000040)) node _T_373 = cvt(_T_372) node _T_374 = and(_T_373, asSInt(UInt<17>(0h100c0))) node _T_375 = asSInt(_T_374) node _T_376 = eq(_T_375, asSInt(UInt<1>(0h0))) node _T_377 = xor(io.in.a.bits.address, UInt<32>(0h80000040)) node _T_378 = cvt(_T_377) node _T_379 = and(_T_378, asSInt(UInt<29>(0h100000c0))) node _T_380 = asSInt(_T_379) node _T_381 = eq(_T_380, asSInt(UInt<1>(0h0))) node _T_382 = or(_T_376, _T_381) node _T_383 = and(_T_371, _T_382) node _T_384 = or(UInt<1>(0h0), _T_383) node _T_385 = and(_T_369, _T_384) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_385, UInt<1>(0h1), "") : assert_10 node _T_389 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_390 = shr(io.in.a.bits.source, 2) node _T_391 = eq(_T_390, UInt<1>(0h0)) node _T_392 = leq(UInt<1>(0h0), uncommonBits_16) node _T_393 = and(_T_391, _T_392) node _T_394 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_395 = and(_T_393, _T_394) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_396 = shr(io.in.a.bits.source, 2) node _T_397 = eq(_T_396, UInt<1>(0h1)) node _T_398 = leq(UInt<1>(0h0), uncommonBits_17) node _T_399 = and(_T_397, _T_398) node _T_400 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_401 = and(_T_399, _T_400) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_402 = shr(io.in.a.bits.source, 2) node _T_403 = eq(_T_402, UInt<2>(0h2)) node _T_404 = leq(UInt<1>(0h0), uncommonBits_18) node _T_405 = and(_T_403, _T_404) node _T_406 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_407 = and(_T_405, _T_406) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_408 = shr(io.in.a.bits.source, 2) node _T_409 = eq(_T_408, UInt<2>(0h3)) node _T_410 = leq(UInt<1>(0h0), uncommonBits_19) node _T_411 = and(_T_409, _T_410) node _T_412 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_413 = and(_T_411, _T_412) node _T_414 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_415 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_416 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_417 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_418 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_419 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_420 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_421 = eq(io.in.a.bits.source, UInt<6>(0h22)) wire _WIRE_2 : UInt<1>[13] connect _WIRE_2[0], _T_389 connect _WIRE_2[1], _T_395 connect _WIRE_2[2], _T_401 connect _WIRE_2[3], _T_407 connect _WIRE_2[4], _T_413 connect _WIRE_2[5], _T_414 connect _WIRE_2[6], _T_415 connect _WIRE_2[7], _T_416 connect _WIRE_2[8], _T_417 connect _WIRE_2[9], _T_418 connect _WIRE_2[10], _T_419 connect _WIRE_2[11], _T_420 connect _WIRE_2[12], _T_421 node _T_422 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_423 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_424 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_425 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_426 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_427 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_428 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_429 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_430 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_431 = mux(_WIRE_2[5], _T_422, UInt<1>(0h0)) node _T_432 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_433 = mux(_WIRE_2[7], _T_423, UInt<1>(0h0)) node _T_434 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_435 = mux(_WIRE_2[9], _T_424, UInt<1>(0h0)) node _T_436 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_437 = mux(_WIRE_2[11], _T_425, UInt<1>(0h0)) node _T_438 = mux(_WIRE_2[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_439 = or(_T_426, _T_427) node _T_440 = or(_T_439, _T_428) node _T_441 = or(_T_440, _T_429) node _T_442 = or(_T_441, _T_430) node _T_443 = or(_T_442, _T_431) node _T_444 = or(_T_443, _T_432) node _T_445 = or(_T_444, _T_433) node _T_446 = or(_T_445, _T_434) node _T_447 = or(_T_446, _T_435) node _T_448 = or(_T_447, _T_436) node _T_449 = or(_T_448, _T_437) node _T_450 = or(_T_449, _T_438) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_450 node _T_451 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_452 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_453 = and(_T_451, _T_452) node _T_454 = or(UInt<1>(0h0), _T_453) node _T_455 = xor(io.in.a.bits.address, UInt<28>(0h8000040)) node _T_456 = cvt(_T_455) node _T_457 = and(_T_456, asSInt(UInt<17>(0h100c0))) node _T_458 = asSInt(_T_457) node _T_459 = eq(_T_458, asSInt(UInt<1>(0h0))) node _T_460 = xor(io.in.a.bits.address, UInt<32>(0h80000040)) node _T_461 = cvt(_T_460) node _T_462 = and(_T_461, asSInt(UInt<29>(0h100000c0))) node _T_463 = asSInt(_T_462) node _T_464 = eq(_T_463, asSInt(UInt<1>(0h0))) node _T_465 = or(_T_459, _T_464) node _T_466 = and(_T_454, _T_465) node _T_467 = or(UInt<1>(0h0), _T_466) node _T_468 = and(_WIRE_3, _T_467) node _T_469 = asUInt(reset) node _T_470 = eq(_T_469, UInt<1>(0h0)) when _T_470 : node _T_471 = eq(_T_468, UInt<1>(0h0)) when _T_471 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_468, UInt<1>(0h1), "") : assert_11 node _T_472 = asUInt(reset) node _T_473 = eq(_T_472, UInt<1>(0h0)) when _T_473 : node _T_474 = eq(source_ok, UInt<1>(0h0)) when _T_474 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_475 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_476 = asUInt(reset) node _T_477 = eq(_T_476, UInt<1>(0h0)) when _T_477 : node _T_478 = eq(_T_475, UInt<1>(0h0)) when _T_478 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_475, UInt<1>(0h1), "") : assert_13 node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(is_aligned, UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_482 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_482, UInt<1>(0h1), "") : assert_15 node _T_486 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_486, UInt<1>(0h1), "") : assert_16 node _T_490 = not(io.in.a.bits.mask) node _T_491 = eq(_T_490, UInt<1>(0h0)) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_491, UInt<1>(0h1), "") : assert_17 node _T_495 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_T_495, UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_495, UInt<1>(0h1), "") : assert_18 node _T_499 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_499 : node _T_500 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_501 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_502 = and(_T_500, _T_501) node _T_503 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_504 = shr(io.in.a.bits.source, 2) node _T_505 = eq(_T_504, UInt<1>(0h0)) node _T_506 = leq(UInt<1>(0h0), uncommonBits_20) node _T_507 = and(_T_505, _T_506) node _T_508 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_509 = and(_T_507, _T_508) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_510 = shr(io.in.a.bits.source, 2) node _T_511 = eq(_T_510, UInt<1>(0h1)) node _T_512 = leq(UInt<1>(0h0), uncommonBits_21) node _T_513 = and(_T_511, _T_512) node _T_514 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_515 = and(_T_513, _T_514) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_516 = shr(io.in.a.bits.source, 2) node _T_517 = eq(_T_516, UInt<2>(0h2)) node _T_518 = leq(UInt<1>(0h0), uncommonBits_22) node _T_519 = and(_T_517, _T_518) node _T_520 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_521 = and(_T_519, _T_520) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_522 = shr(io.in.a.bits.source, 2) node _T_523 = eq(_T_522, UInt<2>(0h3)) node _T_524 = leq(UInt<1>(0h0), uncommonBits_23) node _T_525 = and(_T_523, _T_524) node _T_526 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_527 = and(_T_525, _T_526) node _T_528 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_529 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_530 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_531 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_532 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_533 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_534 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_535 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_536 = or(_T_503, _T_509) node _T_537 = or(_T_536, _T_515) node _T_538 = or(_T_537, _T_521) node _T_539 = or(_T_538, _T_527) node _T_540 = or(_T_539, _T_528) node _T_541 = or(_T_540, _T_529) node _T_542 = or(_T_541, _T_530) node _T_543 = or(_T_542, _T_531) node _T_544 = or(_T_543, _T_532) node _T_545 = or(_T_544, _T_533) node _T_546 = or(_T_545, _T_534) node _T_547 = or(_T_546, _T_535) node _T_548 = and(_T_502, _T_547) node _T_549 = or(UInt<1>(0h0), _T_548) node _T_550 = asUInt(reset) node _T_551 = eq(_T_550, UInt<1>(0h0)) when _T_551 : node _T_552 = eq(_T_549, UInt<1>(0h0)) when _T_552 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_549, UInt<1>(0h1), "") : assert_19 node _T_553 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_554 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_555 = and(_T_553, _T_554) node _T_556 = or(UInt<1>(0h0), _T_555) node _T_557 = xor(io.in.a.bits.address, UInt<28>(0h8000040)) node _T_558 = cvt(_T_557) node _T_559 = and(_T_558, asSInt(UInt<17>(0h100c0))) node _T_560 = asSInt(_T_559) node _T_561 = eq(_T_560, asSInt(UInt<1>(0h0))) node _T_562 = xor(io.in.a.bits.address, UInt<32>(0h80000040)) node _T_563 = cvt(_T_562) node _T_564 = and(_T_563, asSInt(UInt<29>(0h100000c0))) node _T_565 = asSInt(_T_564) node _T_566 = eq(_T_565, asSInt(UInt<1>(0h0))) node _T_567 = or(_T_561, _T_566) node _T_568 = and(_T_556, _T_567) node _T_569 = or(UInt<1>(0h0), _T_568) node _T_570 = asUInt(reset) node _T_571 = eq(_T_570, UInt<1>(0h0)) when _T_571 : node _T_572 = eq(_T_569, UInt<1>(0h0)) when _T_572 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_569, UInt<1>(0h1), "") : assert_20 node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(source_ok, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_576 = asUInt(reset) node _T_577 = eq(_T_576, UInt<1>(0h0)) when _T_577 : node _T_578 = eq(is_aligned, UInt<1>(0h0)) when _T_578 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_579 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_580 = asUInt(reset) node _T_581 = eq(_T_580, UInt<1>(0h0)) when _T_581 : node _T_582 = eq(_T_579, UInt<1>(0h0)) when _T_582 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_579, UInt<1>(0h1), "") : assert_23 node _T_583 = eq(io.in.a.bits.mask, mask) node _T_584 = asUInt(reset) node _T_585 = eq(_T_584, UInt<1>(0h0)) when _T_585 : node _T_586 = eq(_T_583, UInt<1>(0h0)) when _T_586 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_583, UInt<1>(0h1), "") : assert_24 node _T_587 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_588 = asUInt(reset) node _T_589 = eq(_T_588, UInt<1>(0h0)) when _T_589 : node _T_590 = eq(_T_587, UInt<1>(0h0)) when _T_590 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_587, UInt<1>(0h1), "") : assert_25 node _T_591 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_591 : node _T_592 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_593 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_594 = and(_T_592, _T_593) node _T_595 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_596 = shr(io.in.a.bits.source, 2) node _T_597 = eq(_T_596, UInt<1>(0h0)) node _T_598 = leq(UInt<1>(0h0), uncommonBits_24) node _T_599 = and(_T_597, _T_598) node _T_600 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_601 = and(_T_599, _T_600) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_602 = shr(io.in.a.bits.source, 2) node _T_603 = eq(_T_602, UInt<1>(0h1)) node _T_604 = leq(UInt<1>(0h0), uncommonBits_25) node _T_605 = and(_T_603, _T_604) node _T_606 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_607 = and(_T_605, _T_606) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_608 = shr(io.in.a.bits.source, 2) node _T_609 = eq(_T_608, UInt<2>(0h2)) node _T_610 = leq(UInt<1>(0h0), uncommonBits_26) node _T_611 = and(_T_609, _T_610) node _T_612 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_613 = and(_T_611, _T_612) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_614 = shr(io.in.a.bits.source, 2) node _T_615 = eq(_T_614, UInt<2>(0h3)) node _T_616 = leq(UInt<1>(0h0), uncommonBits_27) node _T_617 = and(_T_615, _T_616) node _T_618 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_619 = and(_T_617, _T_618) node _T_620 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_621 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_622 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_623 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_624 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_625 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_626 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_627 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_628 = or(_T_595, _T_601) node _T_629 = or(_T_628, _T_607) node _T_630 = or(_T_629, _T_613) node _T_631 = or(_T_630, _T_619) node _T_632 = or(_T_631, _T_620) node _T_633 = or(_T_632, _T_621) node _T_634 = or(_T_633, _T_622) node _T_635 = or(_T_634, _T_623) node _T_636 = or(_T_635, _T_624) node _T_637 = or(_T_636, _T_625) node _T_638 = or(_T_637, _T_626) node _T_639 = or(_T_638, _T_627) node _T_640 = and(_T_594, _T_639) node _T_641 = or(UInt<1>(0h0), _T_640) node _T_642 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_643 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_644 = and(_T_642, _T_643) node _T_645 = or(UInt<1>(0h0), _T_644) node _T_646 = xor(io.in.a.bits.address, UInt<28>(0h8000040)) node _T_647 = cvt(_T_646) node _T_648 = and(_T_647, asSInt(UInt<17>(0h100c0))) node _T_649 = asSInt(_T_648) node _T_650 = eq(_T_649, asSInt(UInt<1>(0h0))) node _T_651 = xor(io.in.a.bits.address, UInt<32>(0h80000040)) node _T_652 = cvt(_T_651) node _T_653 = and(_T_652, asSInt(UInt<29>(0h100000c0))) node _T_654 = asSInt(_T_653) node _T_655 = eq(_T_654, asSInt(UInt<1>(0h0))) node _T_656 = or(_T_650, _T_655) node _T_657 = and(_T_645, _T_656) node _T_658 = or(UInt<1>(0h0), _T_657) node _T_659 = and(_T_641, _T_658) node _T_660 = asUInt(reset) node _T_661 = eq(_T_660, UInt<1>(0h0)) when _T_661 : node _T_662 = eq(_T_659, UInt<1>(0h0)) when _T_662 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_659, UInt<1>(0h1), "") : assert_26 node _T_663 = asUInt(reset) node _T_664 = eq(_T_663, UInt<1>(0h0)) when _T_664 : node _T_665 = eq(source_ok, UInt<1>(0h0)) when _T_665 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_666 = asUInt(reset) node _T_667 = eq(_T_666, UInt<1>(0h0)) when _T_667 : node _T_668 = eq(is_aligned, UInt<1>(0h0)) when _T_668 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_669 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_670 = asUInt(reset) node _T_671 = eq(_T_670, UInt<1>(0h0)) when _T_671 : node _T_672 = eq(_T_669, UInt<1>(0h0)) when _T_672 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_669, UInt<1>(0h1), "") : assert_29 node _T_673 = eq(io.in.a.bits.mask, mask) node _T_674 = asUInt(reset) node _T_675 = eq(_T_674, UInt<1>(0h0)) when _T_675 : node _T_676 = eq(_T_673, UInt<1>(0h0)) when _T_676 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_673, UInt<1>(0h1), "") : assert_30 node _T_677 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_677 : node _T_678 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_679 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_680 = and(_T_678, _T_679) node _T_681 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_682 = shr(io.in.a.bits.source, 2) node _T_683 = eq(_T_682, UInt<1>(0h0)) node _T_684 = leq(UInt<1>(0h0), uncommonBits_28) node _T_685 = and(_T_683, _T_684) node _T_686 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_687 = and(_T_685, _T_686) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_688 = shr(io.in.a.bits.source, 2) node _T_689 = eq(_T_688, UInt<1>(0h1)) node _T_690 = leq(UInt<1>(0h0), uncommonBits_29) node _T_691 = and(_T_689, _T_690) node _T_692 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_693 = and(_T_691, _T_692) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_694 = shr(io.in.a.bits.source, 2) node _T_695 = eq(_T_694, UInt<2>(0h2)) node _T_696 = leq(UInt<1>(0h0), uncommonBits_30) node _T_697 = and(_T_695, _T_696) node _T_698 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_699 = and(_T_697, _T_698) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_700 = shr(io.in.a.bits.source, 2) node _T_701 = eq(_T_700, UInt<2>(0h3)) node _T_702 = leq(UInt<1>(0h0), uncommonBits_31) node _T_703 = and(_T_701, _T_702) node _T_704 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_705 = and(_T_703, _T_704) node _T_706 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_707 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_708 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_709 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_710 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_711 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_712 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_713 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_714 = or(_T_681, _T_687) node _T_715 = or(_T_714, _T_693) node _T_716 = or(_T_715, _T_699) node _T_717 = or(_T_716, _T_705) node _T_718 = or(_T_717, _T_706) node _T_719 = or(_T_718, _T_707) node _T_720 = or(_T_719, _T_708) node _T_721 = or(_T_720, _T_709) node _T_722 = or(_T_721, _T_710) node _T_723 = or(_T_722, _T_711) node _T_724 = or(_T_723, _T_712) node _T_725 = or(_T_724, _T_713) node _T_726 = and(_T_680, _T_725) node _T_727 = or(UInt<1>(0h0), _T_726) node _T_728 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_729 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_730 = and(_T_728, _T_729) node _T_731 = or(UInt<1>(0h0), _T_730) node _T_732 = xor(io.in.a.bits.address, UInt<28>(0h8000040)) node _T_733 = cvt(_T_732) node _T_734 = and(_T_733, asSInt(UInt<17>(0h100c0))) node _T_735 = asSInt(_T_734) node _T_736 = eq(_T_735, asSInt(UInt<1>(0h0))) node _T_737 = xor(io.in.a.bits.address, UInt<32>(0h80000040)) node _T_738 = cvt(_T_737) node _T_739 = and(_T_738, asSInt(UInt<29>(0h100000c0))) node _T_740 = asSInt(_T_739) node _T_741 = eq(_T_740, asSInt(UInt<1>(0h0))) node _T_742 = or(_T_736, _T_741) node _T_743 = and(_T_731, _T_742) node _T_744 = or(UInt<1>(0h0), _T_743) node _T_745 = and(_T_727, _T_744) node _T_746 = asUInt(reset) node _T_747 = eq(_T_746, UInt<1>(0h0)) when _T_747 : node _T_748 = eq(_T_745, UInt<1>(0h0)) when _T_748 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_745, UInt<1>(0h1), "") : assert_31 node _T_749 = asUInt(reset) node _T_750 = eq(_T_749, UInt<1>(0h0)) when _T_750 : node _T_751 = eq(source_ok, UInt<1>(0h0)) when _T_751 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_752 = asUInt(reset) node _T_753 = eq(_T_752, UInt<1>(0h0)) when _T_753 : node _T_754 = eq(is_aligned, UInt<1>(0h0)) when _T_754 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_755 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_756 = asUInt(reset) node _T_757 = eq(_T_756, UInt<1>(0h0)) when _T_757 : node _T_758 = eq(_T_755, UInt<1>(0h0)) when _T_758 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_755, UInt<1>(0h1), "") : assert_34 node _T_759 = not(mask) node _T_760 = and(io.in.a.bits.mask, _T_759) node _T_761 = eq(_T_760, UInt<1>(0h0)) node _T_762 = asUInt(reset) node _T_763 = eq(_T_762, UInt<1>(0h0)) when _T_763 : node _T_764 = eq(_T_761, UInt<1>(0h0)) when _T_764 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_761, UInt<1>(0h1), "") : assert_35 node _T_765 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_765 : node _T_766 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_767 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_768 = and(_T_766, _T_767) node _T_769 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_770 = shr(io.in.a.bits.source, 2) node _T_771 = eq(_T_770, UInt<1>(0h0)) node _T_772 = leq(UInt<1>(0h0), uncommonBits_32) node _T_773 = and(_T_771, _T_772) node _T_774 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_775 = and(_T_773, _T_774) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_776 = shr(io.in.a.bits.source, 2) node _T_777 = eq(_T_776, UInt<1>(0h1)) node _T_778 = leq(UInt<1>(0h0), uncommonBits_33) node _T_779 = and(_T_777, _T_778) node _T_780 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_781 = and(_T_779, _T_780) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_782 = shr(io.in.a.bits.source, 2) node _T_783 = eq(_T_782, UInt<2>(0h2)) node _T_784 = leq(UInt<1>(0h0), uncommonBits_34) node _T_785 = and(_T_783, _T_784) node _T_786 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_787 = and(_T_785, _T_786) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_788 = shr(io.in.a.bits.source, 2) node _T_789 = eq(_T_788, UInt<2>(0h3)) node _T_790 = leq(UInt<1>(0h0), uncommonBits_35) node _T_791 = and(_T_789, _T_790) node _T_792 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_793 = and(_T_791, _T_792) node _T_794 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_795 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_796 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_797 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_798 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_799 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_800 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_801 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_802 = or(_T_769, _T_775) node _T_803 = or(_T_802, _T_781) node _T_804 = or(_T_803, _T_787) node _T_805 = or(_T_804, _T_793) node _T_806 = or(_T_805, _T_794) node _T_807 = or(_T_806, _T_795) node _T_808 = or(_T_807, _T_796) node _T_809 = or(_T_808, _T_797) node _T_810 = or(_T_809, _T_798) node _T_811 = or(_T_810, _T_799) node _T_812 = or(_T_811, _T_800) node _T_813 = or(_T_812, _T_801) node _T_814 = and(_T_768, _T_813) node _T_815 = or(UInt<1>(0h0), _T_814) node _T_816 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_817 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_818 = and(_T_816, _T_817) node _T_819 = or(UInt<1>(0h0), _T_818) node _T_820 = xor(io.in.a.bits.address, UInt<28>(0h8000040)) node _T_821 = cvt(_T_820) node _T_822 = and(_T_821, asSInt(UInt<17>(0h100c0))) node _T_823 = asSInt(_T_822) node _T_824 = eq(_T_823, asSInt(UInt<1>(0h0))) node _T_825 = xor(io.in.a.bits.address, UInt<32>(0h80000040)) node _T_826 = cvt(_T_825) node _T_827 = and(_T_826, asSInt(UInt<29>(0h100000c0))) node _T_828 = asSInt(_T_827) node _T_829 = eq(_T_828, asSInt(UInt<1>(0h0))) node _T_830 = or(_T_824, _T_829) node _T_831 = and(_T_819, _T_830) node _T_832 = or(UInt<1>(0h0), _T_831) node _T_833 = and(_T_815, _T_832) node _T_834 = asUInt(reset) node _T_835 = eq(_T_834, UInt<1>(0h0)) when _T_835 : node _T_836 = eq(_T_833, UInt<1>(0h0)) when _T_836 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_833, UInt<1>(0h1), "") : assert_36 node _T_837 = asUInt(reset) node _T_838 = eq(_T_837, UInt<1>(0h0)) when _T_838 : node _T_839 = eq(source_ok, UInt<1>(0h0)) when _T_839 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_840 = asUInt(reset) node _T_841 = eq(_T_840, UInt<1>(0h0)) when _T_841 : node _T_842 = eq(is_aligned, UInt<1>(0h0)) when _T_842 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_843 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_844 = asUInt(reset) node _T_845 = eq(_T_844, UInt<1>(0h0)) when _T_845 : node _T_846 = eq(_T_843, UInt<1>(0h0)) when _T_846 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_843, UInt<1>(0h1), "") : assert_39 node _T_847 = eq(io.in.a.bits.mask, mask) node _T_848 = asUInt(reset) node _T_849 = eq(_T_848, UInt<1>(0h0)) when _T_849 : node _T_850 = eq(_T_847, UInt<1>(0h0)) when _T_850 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_847, UInt<1>(0h1), "") : assert_40 node _T_851 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_851 : node _T_852 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_853 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_854 = and(_T_852, _T_853) node _T_855 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_856 = shr(io.in.a.bits.source, 2) node _T_857 = eq(_T_856, UInt<1>(0h0)) node _T_858 = leq(UInt<1>(0h0), uncommonBits_36) node _T_859 = and(_T_857, _T_858) node _T_860 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_861 = and(_T_859, _T_860) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_862 = shr(io.in.a.bits.source, 2) node _T_863 = eq(_T_862, UInt<1>(0h1)) node _T_864 = leq(UInt<1>(0h0), uncommonBits_37) node _T_865 = and(_T_863, _T_864) node _T_866 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_867 = and(_T_865, _T_866) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_868 = shr(io.in.a.bits.source, 2) node _T_869 = eq(_T_868, UInt<2>(0h2)) node _T_870 = leq(UInt<1>(0h0), uncommonBits_38) node _T_871 = and(_T_869, _T_870) node _T_872 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_873 = and(_T_871, _T_872) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_874 = shr(io.in.a.bits.source, 2) node _T_875 = eq(_T_874, UInt<2>(0h3)) node _T_876 = leq(UInt<1>(0h0), uncommonBits_39) node _T_877 = and(_T_875, _T_876) node _T_878 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_879 = and(_T_877, _T_878) node _T_880 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_881 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_882 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_883 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_884 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_885 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_886 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_887 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_888 = or(_T_855, _T_861) node _T_889 = or(_T_888, _T_867) node _T_890 = or(_T_889, _T_873) node _T_891 = or(_T_890, _T_879) node _T_892 = or(_T_891, _T_880) node _T_893 = or(_T_892, _T_881) node _T_894 = or(_T_893, _T_882) node _T_895 = or(_T_894, _T_883) node _T_896 = or(_T_895, _T_884) node _T_897 = or(_T_896, _T_885) node _T_898 = or(_T_897, _T_886) node _T_899 = or(_T_898, _T_887) node _T_900 = and(_T_854, _T_899) node _T_901 = or(UInt<1>(0h0), _T_900) node _T_902 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_903 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_904 = and(_T_902, _T_903) node _T_905 = or(UInt<1>(0h0), _T_904) node _T_906 = xor(io.in.a.bits.address, UInt<28>(0h8000040)) node _T_907 = cvt(_T_906) node _T_908 = and(_T_907, asSInt(UInt<17>(0h100c0))) node _T_909 = asSInt(_T_908) node _T_910 = eq(_T_909, asSInt(UInt<1>(0h0))) node _T_911 = xor(io.in.a.bits.address, UInt<32>(0h80000040)) node _T_912 = cvt(_T_911) node _T_913 = and(_T_912, asSInt(UInt<29>(0h100000c0))) node _T_914 = asSInt(_T_913) node _T_915 = eq(_T_914, asSInt(UInt<1>(0h0))) node _T_916 = or(_T_910, _T_915) node _T_917 = and(_T_905, _T_916) node _T_918 = or(UInt<1>(0h0), _T_917) node _T_919 = and(_T_901, _T_918) node _T_920 = asUInt(reset) node _T_921 = eq(_T_920, UInt<1>(0h0)) when _T_921 : node _T_922 = eq(_T_919, UInt<1>(0h0)) when _T_922 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_919, UInt<1>(0h1), "") : assert_41 node _T_923 = asUInt(reset) node _T_924 = eq(_T_923, UInt<1>(0h0)) when _T_924 : node _T_925 = eq(source_ok, UInt<1>(0h0)) when _T_925 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_926 = asUInt(reset) node _T_927 = eq(_T_926, UInt<1>(0h0)) when _T_927 : node _T_928 = eq(is_aligned, UInt<1>(0h0)) when _T_928 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_929 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_930 = asUInt(reset) node _T_931 = eq(_T_930, UInt<1>(0h0)) when _T_931 : node _T_932 = eq(_T_929, UInt<1>(0h0)) when _T_932 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_929, UInt<1>(0h1), "") : assert_44 node _T_933 = eq(io.in.a.bits.mask, mask) node _T_934 = asUInt(reset) node _T_935 = eq(_T_934, UInt<1>(0h0)) when _T_935 : node _T_936 = eq(_T_933, UInt<1>(0h0)) when _T_936 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_933, UInt<1>(0h1), "") : assert_45 node _T_937 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_937 : node _T_938 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_939 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_940 = and(_T_938, _T_939) node _T_941 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_942 = shr(io.in.a.bits.source, 2) node _T_943 = eq(_T_942, UInt<1>(0h0)) node _T_944 = leq(UInt<1>(0h0), uncommonBits_40) node _T_945 = and(_T_943, _T_944) node _T_946 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_947 = and(_T_945, _T_946) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_948 = shr(io.in.a.bits.source, 2) node _T_949 = eq(_T_948, UInt<1>(0h1)) node _T_950 = leq(UInt<1>(0h0), uncommonBits_41) node _T_951 = and(_T_949, _T_950) node _T_952 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_953 = and(_T_951, _T_952) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_954 = shr(io.in.a.bits.source, 2) node _T_955 = eq(_T_954, UInt<2>(0h2)) node _T_956 = leq(UInt<1>(0h0), uncommonBits_42) node _T_957 = and(_T_955, _T_956) node _T_958 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_959 = and(_T_957, _T_958) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_960 = shr(io.in.a.bits.source, 2) node _T_961 = eq(_T_960, UInt<2>(0h3)) node _T_962 = leq(UInt<1>(0h0), uncommonBits_43) node _T_963 = and(_T_961, _T_962) node _T_964 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_965 = and(_T_963, _T_964) node _T_966 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_967 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_968 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_969 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_970 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_971 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_972 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_973 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_974 = or(_T_941, _T_947) node _T_975 = or(_T_974, _T_953) node _T_976 = or(_T_975, _T_959) node _T_977 = or(_T_976, _T_965) node _T_978 = or(_T_977, _T_966) node _T_979 = or(_T_978, _T_967) node _T_980 = or(_T_979, _T_968) node _T_981 = or(_T_980, _T_969) node _T_982 = or(_T_981, _T_970) node _T_983 = or(_T_982, _T_971) node _T_984 = or(_T_983, _T_972) node _T_985 = or(_T_984, _T_973) node _T_986 = and(_T_940, _T_985) node _T_987 = or(UInt<1>(0h0), _T_986) node _T_988 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_989 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_990 = and(_T_988, _T_989) node _T_991 = or(UInt<1>(0h0), _T_990) node _T_992 = xor(io.in.a.bits.address, UInt<28>(0h8000040)) node _T_993 = cvt(_T_992) node _T_994 = and(_T_993, asSInt(UInt<17>(0h100c0))) node _T_995 = asSInt(_T_994) node _T_996 = eq(_T_995, asSInt(UInt<1>(0h0))) node _T_997 = xor(io.in.a.bits.address, UInt<32>(0h80000040)) node _T_998 = cvt(_T_997) node _T_999 = and(_T_998, asSInt(UInt<29>(0h100000c0))) node _T_1000 = asSInt(_T_999) node _T_1001 = eq(_T_1000, asSInt(UInt<1>(0h0))) node _T_1002 = or(_T_996, _T_1001) node _T_1003 = and(_T_991, _T_1002) node _T_1004 = or(UInt<1>(0h0), _T_1003) node _T_1005 = and(_T_987, _T_1004) node _T_1006 = asUInt(reset) node _T_1007 = eq(_T_1006, UInt<1>(0h0)) when _T_1007 : node _T_1008 = eq(_T_1005, UInt<1>(0h0)) when _T_1008 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1005, UInt<1>(0h1), "") : assert_46 node _T_1009 = asUInt(reset) node _T_1010 = eq(_T_1009, UInt<1>(0h0)) when _T_1010 : node _T_1011 = eq(source_ok, UInt<1>(0h0)) when _T_1011 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1012 = asUInt(reset) node _T_1013 = eq(_T_1012, UInt<1>(0h0)) when _T_1013 : node _T_1014 = eq(is_aligned, UInt<1>(0h0)) when _T_1014 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1015 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1016 = asUInt(reset) node _T_1017 = eq(_T_1016, UInt<1>(0h0)) when _T_1017 : node _T_1018 = eq(_T_1015, UInt<1>(0h0)) when _T_1018 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1015, UInt<1>(0h1), "") : assert_49 node _T_1019 = eq(io.in.a.bits.mask, mask) node _T_1020 = asUInt(reset) node _T_1021 = eq(_T_1020, UInt<1>(0h0)) when _T_1021 : node _T_1022 = eq(_T_1019, UInt<1>(0h0)) when _T_1022 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1019, UInt<1>(0h1), "") : assert_50 node _T_1023 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1024 = asUInt(reset) node _T_1025 = eq(_T_1024, UInt<1>(0h0)) when _T_1025 : node _T_1026 = eq(_T_1023, UInt<1>(0h0)) when _T_1026 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1023, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1027 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1028 = asUInt(reset) node _T_1029 = eq(_T_1028, UInt<1>(0h0)) when _T_1029 : node _T_1030 = eq(_T_1027, UInt<1>(0h0)) when _T_1030 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1027, UInt<1>(0h1), "") : assert_52 node _source_ok_T_44 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_45 = shr(io.in.d.bits.source, 2) node _source_ok_T_46 = eq(_source_ok_T_45, UInt<1>(0h0)) node _source_ok_T_47 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_48 = and(_source_ok_T_46, _source_ok_T_47) node _source_ok_T_49 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_50 = and(_source_ok_T_48, _source_ok_T_49) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_51 = shr(io.in.d.bits.source, 2) node _source_ok_T_52 = eq(_source_ok_T_51, UInt<1>(0h1)) node _source_ok_T_53 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53) node _source_ok_T_55 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_56 = and(_source_ok_T_54, _source_ok_T_55) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_57 = shr(io.in.d.bits.source, 2) node _source_ok_T_58 = eq(_source_ok_T_57, UInt<2>(0h2)) node _source_ok_T_59 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_60 = and(_source_ok_T_58, _source_ok_T_59) node _source_ok_T_61 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_62 = and(_source_ok_T_60, _source_ok_T_61) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_63 = shr(io.in.d.bits.source, 2) node _source_ok_T_64 = eq(_source_ok_T_63, UInt<2>(0h3)) node _source_ok_T_65 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_66 = and(_source_ok_T_64, _source_ok_T_65) node _source_ok_T_67 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_68 = and(_source_ok_T_66, _source_ok_T_67) node _source_ok_T_69 = eq(io.in.d.bits.source, UInt<6>(0h2c)) node _source_ok_T_70 = eq(io.in.d.bits.source, UInt<6>(0h2e)) node _source_ok_T_71 = eq(io.in.d.bits.source, UInt<6>(0h28)) node _source_ok_T_72 = eq(io.in.d.bits.source, UInt<6>(0h2a)) node _source_ok_T_73 = eq(io.in.d.bits.source, UInt<6>(0h24)) node _source_ok_T_74 = eq(io.in.d.bits.source, UInt<6>(0h26)) node _source_ok_T_75 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_76 = eq(io.in.d.bits.source, UInt<6>(0h22)) wire _source_ok_WIRE_1 : UInt<1>[13] connect _source_ok_WIRE_1[0], _source_ok_T_44 connect _source_ok_WIRE_1[1], _source_ok_T_50 connect _source_ok_WIRE_1[2], _source_ok_T_56 connect _source_ok_WIRE_1[3], _source_ok_T_62 connect _source_ok_WIRE_1[4], _source_ok_T_68 connect _source_ok_WIRE_1[5], _source_ok_T_69 connect _source_ok_WIRE_1[6], _source_ok_T_70 connect _source_ok_WIRE_1[7], _source_ok_T_71 connect _source_ok_WIRE_1[8], _source_ok_T_72 connect _source_ok_WIRE_1[9], _source_ok_T_73 connect _source_ok_WIRE_1[10], _source_ok_T_74 connect _source_ok_WIRE_1[11], _source_ok_T_75 connect _source_ok_WIRE_1[12], _source_ok_T_76 node _source_ok_T_77 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_78 = or(_source_ok_T_77, _source_ok_WIRE_1[2]) node _source_ok_T_79 = or(_source_ok_T_78, _source_ok_WIRE_1[3]) node _source_ok_T_80 = or(_source_ok_T_79, _source_ok_WIRE_1[4]) node _source_ok_T_81 = or(_source_ok_T_80, _source_ok_WIRE_1[5]) node _source_ok_T_82 = or(_source_ok_T_81, _source_ok_WIRE_1[6]) node _source_ok_T_83 = or(_source_ok_T_82, _source_ok_WIRE_1[7]) node _source_ok_T_84 = or(_source_ok_T_83, _source_ok_WIRE_1[8]) node _source_ok_T_85 = or(_source_ok_T_84, _source_ok_WIRE_1[9]) node _source_ok_T_86 = or(_source_ok_T_85, _source_ok_WIRE_1[10]) node _source_ok_T_87 = or(_source_ok_T_86, _source_ok_WIRE_1[11]) node source_ok_1 = or(_source_ok_T_87, _source_ok_WIRE_1[12]) node sink_ok = lt(io.in.d.bits.sink, UInt<3>(0h7)) node _T_1031 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1031 : node _T_1032 = asUInt(reset) node _T_1033 = eq(_T_1032, UInt<1>(0h0)) when _T_1033 : node _T_1034 = eq(source_ok_1, UInt<1>(0h0)) when _T_1034 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1035 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1036 = asUInt(reset) node _T_1037 = eq(_T_1036, UInt<1>(0h0)) when _T_1037 : node _T_1038 = eq(_T_1035, UInt<1>(0h0)) when _T_1038 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1035, UInt<1>(0h1), "") : assert_54 node _T_1039 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1040 = asUInt(reset) node _T_1041 = eq(_T_1040, UInt<1>(0h0)) when _T_1041 : node _T_1042 = eq(_T_1039, UInt<1>(0h0)) when _T_1042 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1039, UInt<1>(0h1), "") : assert_55 node _T_1043 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1044 = asUInt(reset) node _T_1045 = eq(_T_1044, UInt<1>(0h0)) when _T_1045 : node _T_1046 = eq(_T_1043, UInt<1>(0h0)) when _T_1046 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1043, UInt<1>(0h1), "") : assert_56 node _T_1047 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1048 = asUInt(reset) node _T_1049 = eq(_T_1048, UInt<1>(0h0)) when _T_1049 : node _T_1050 = eq(_T_1047, UInt<1>(0h0)) when _T_1050 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1047, UInt<1>(0h1), "") : assert_57 node _T_1051 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1051 : node _T_1052 = asUInt(reset) node _T_1053 = eq(_T_1052, UInt<1>(0h0)) when _T_1053 : node _T_1054 = eq(source_ok_1, UInt<1>(0h0)) when _T_1054 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1055 = asUInt(reset) node _T_1056 = eq(_T_1055, UInt<1>(0h0)) when _T_1056 : node _T_1057 = eq(sink_ok, UInt<1>(0h0)) when _T_1057 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1058 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1059 = asUInt(reset) node _T_1060 = eq(_T_1059, UInt<1>(0h0)) when _T_1060 : node _T_1061 = eq(_T_1058, UInt<1>(0h0)) when _T_1061 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1058, UInt<1>(0h1), "") : assert_60 node _T_1062 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1063 = asUInt(reset) node _T_1064 = eq(_T_1063, UInt<1>(0h0)) when _T_1064 : node _T_1065 = eq(_T_1062, UInt<1>(0h0)) when _T_1065 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1062, UInt<1>(0h1), "") : assert_61 node _T_1066 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1067 = asUInt(reset) node _T_1068 = eq(_T_1067, UInt<1>(0h0)) when _T_1068 : node _T_1069 = eq(_T_1066, UInt<1>(0h0)) when _T_1069 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1066, UInt<1>(0h1), "") : assert_62 node _T_1070 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1071 = asUInt(reset) node _T_1072 = eq(_T_1071, UInt<1>(0h0)) when _T_1072 : node _T_1073 = eq(_T_1070, UInt<1>(0h0)) when _T_1073 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1070, UInt<1>(0h1), "") : assert_63 node _T_1074 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1075 = or(UInt<1>(0h1), _T_1074) node _T_1076 = asUInt(reset) node _T_1077 = eq(_T_1076, UInt<1>(0h0)) when _T_1077 : node _T_1078 = eq(_T_1075, UInt<1>(0h0)) when _T_1078 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1075, UInt<1>(0h1), "") : assert_64 node _T_1079 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1079 : node _T_1080 = asUInt(reset) node _T_1081 = eq(_T_1080, UInt<1>(0h0)) when _T_1081 : node _T_1082 = eq(source_ok_1, UInt<1>(0h0)) when _T_1082 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1083 = asUInt(reset) node _T_1084 = eq(_T_1083, UInt<1>(0h0)) when _T_1084 : node _T_1085 = eq(sink_ok, UInt<1>(0h0)) when _T_1085 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1086 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1087 = asUInt(reset) node _T_1088 = eq(_T_1087, UInt<1>(0h0)) when _T_1088 : node _T_1089 = eq(_T_1086, UInt<1>(0h0)) when _T_1089 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1086, UInt<1>(0h1), "") : assert_67 node _T_1090 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1091 = asUInt(reset) node _T_1092 = eq(_T_1091, UInt<1>(0h0)) when _T_1092 : node _T_1093 = eq(_T_1090, UInt<1>(0h0)) when _T_1093 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1090, UInt<1>(0h1), "") : assert_68 node _T_1094 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1095 = asUInt(reset) node _T_1096 = eq(_T_1095, UInt<1>(0h0)) when _T_1096 : node _T_1097 = eq(_T_1094, UInt<1>(0h0)) when _T_1097 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1094, UInt<1>(0h1), "") : assert_69 node _T_1098 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1099 = or(_T_1098, io.in.d.bits.corrupt) node _T_1100 = asUInt(reset) node _T_1101 = eq(_T_1100, UInt<1>(0h0)) when _T_1101 : node _T_1102 = eq(_T_1099, UInt<1>(0h0)) when _T_1102 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1099, UInt<1>(0h1), "") : assert_70 node _T_1103 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1104 = or(UInt<1>(0h1), _T_1103) node _T_1105 = asUInt(reset) node _T_1106 = eq(_T_1105, UInt<1>(0h0)) when _T_1106 : node _T_1107 = eq(_T_1104, UInt<1>(0h0)) when _T_1107 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1104, UInt<1>(0h1), "") : assert_71 node _T_1108 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1108 : node _T_1109 = asUInt(reset) node _T_1110 = eq(_T_1109, UInt<1>(0h0)) when _T_1110 : node _T_1111 = eq(source_ok_1, UInt<1>(0h0)) when _T_1111 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1112 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1113 = asUInt(reset) node _T_1114 = eq(_T_1113, UInt<1>(0h0)) when _T_1114 : node _T_1115 = eq(_T_1112, UInt<1>(0h0)) when _T_1115 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1112, UInt<1>(0h1), "") : assert_73 node _T_1116 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1117 = asUInt(reset) node _T_1118 = eq(_T_1117, UInt<1>(0h0)) when _T_1118 : node _T_1119 = eq(_T_1116, UInt<1>(0h0)) when _T_1119 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1116, UInt<1>(0h1), "") : assert_74 node _T_1120 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1121 = or(UInt<1>(0h1), _T_1120) node _T_1122 = asUInt(reset) node _T_1123 = eq(_T_1122, UInt<1>(0h0)) when _T_1123 : node _T_1124 = eq(_T_1121, UInt<1>(0h0)) when _T_1124 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1121, UInt<1>(0h1), "") : assert_75 node _T_1125 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1125 : node _T_1126 = asUInt(reset) node _T_1127 = eq(_T_1126, UInt<1>(0h0)) when _T_1127 : node _T_1128 = eq(source_ok_1, UInt<1>(0h0)) when _T_1128 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1129 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1130 = asUInt(reset) node _T_1131 = eq(_T_1130, UInt<1>(0h0)) when _T_1131 : node _T_1132 = eq(_T_1129, UInt<1>(0h0)) when _T_1132 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1129, UInt<1>(0h1), "") : assert_77 node _T_1133 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1134 = or(_T_1133, io.in.d.bits.corrupt) node _T_1135 = asUInt(reset) node _T_1136 = eq(_T_1135, UInt<1>(0h0)) when _T_1136 : node _T_1137 = eq(_T_1134, UInt<1>(0h0)) when _T_1137 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1134, UInt<1>(0h1), "") : assert_78 node _T_1138 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1139 = or(UInt<1>(0h1), _T_1138) node _T_1140 = asUInt(reset) node _T_1141 = eq(_T_1140, UInt<1>(0h0)) when _T_1141 : node _T_1142 = eq(_T_1139, UInt<1>(0h0)) when _T_1142 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1139, UInt<1>(0h1), "") : assert_79 node _T_1143 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1143 : node _T_1144 = asUInt(reset) node _T_1145 = eq(_T_1144, UInt<1>(0h0)) when _T_1145 : node _T_1146 = eq(source_ok_1, UInt<1>(0h0)) when _T_1146 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1147 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1148 = asUInt(reset) node _T_1149 = eq(_T_1148, UInt<1>(0h0)) when _T_1149 : node _T_1150 = eq(_T_1147, UInt<1>(0h0)) when _T_1150 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1147, UInt<1>(0h1), "") : assert_81 node _T_1151 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1152 = asUInt(reset) node _T_1153 = eq(_T_1152, UInt<1>(0h0)) when _T_1153 : node _T_1154 = eq(_T_1151, UInt<1>(0h0)) when _T_1154 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1151, UInt<1>(0h1), "") : assert_82 node _T_1155 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1156 = or(UInt<1>(0h1), _T_1155) node _T_1157 = asUInt(reset) node _T_1158 = eq(_T_1157, UInt<1>(0h0)) when _T_1158 : node _T_1159 = eq(_T_1156, UInt<1>(0h0)) when _T_1159 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1156, UInt<1>(0h1), "") : assert_83 when io.in.b.valid : node _T_1160 = leq(io.in.b.bits.opcode, UInt<3>(0h6)) node _T_1161 = asUInt(reset) node _T_1162 = eq(_T_1161, UInt<1>(0h0)) when _T_1162 : node _T_1163 = eq(_T_1160, UInt<1>(0h0)) when _T_1163 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1160, UInt<1>(0h1), "") : assert_84 node _T_1164 = eq(io.in.b.bits.source, UInt<5>(0h10)) node _T_1165 = eq(_T_1164, UInt<1>(0h0)) node _T_1166 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1167 = cvt(_T_1166) node _T_1168 = and(_T_1167, asSInt(UInt<1>(0h0))) node _T_1169 = asSInt(_T_1168) node _T_1170 = eq(_T_1169, asSInt(UInt<1>(0h0))) node _T_1171 = or(_T_1165, _T_1170) node _uncommonBits_T_44 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_44 = bits(_uncommonBits_T_44, 1, 0) node _T_1172 = shr(io.in.b.bits.source, 2) node _T_1173 = eq(_T_1172, UInt<1>(0h0)) node _T_1174 = leq(UInt<1>(0h0), uncommonBits_44) node _T_1175 = and(_T_1173, _T_1174) node _T_1176 = leq(uncommonBits_44, UInt<2>(0h3)) node _T_1177 = and(_T_1175, _T_1176) node _T_1178 = eq(_T_1177, UInt<1>(0h0)) node _T_1179 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1180 = cvt(_T_1179) node _T_1181 = and(_T_1180, asSInt(UInt<1>(0h0))) node _T_1182 = asSInt(_T_1181) node _T_1183 = eq(_T_1182, asSInt(UInt<1>(0h0))) node _T_1184 = or(_T_1178, _T_1183) node _uncommonBits_T_45 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0) node _T_1185 = shr(io.in.b.bits.source, 2) node _T_1186 = eq(_T_1185, UInt<1>(0h1)) node _T_1187 = leq(UInt<1>(0h0), uncommonBits_45) node _T_1188 = and(_T_1186, _T_1187) node _T_1189 = leq(uncommonBits_45, UInt<2>(0h3)) node _T_1190 = and(_T_1188, _T_1189) node _T_1191 = eq(_T_1190, UInt<1>(0h0)) node _T_1192 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1193 = cvt(_T_1192) node _T_1194 = and(_T_1193, asSInt(UInt<1>(0h0))) node _T_1195 = asSInt(_T_1194) node _T_1196 = eq(_T_1195, asSInt(UInt<1>(0h0))) node _T_1197 = or(_T_1191, _T_1196) node _uncommonBits_T_46 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_46 = bits(_uncommonBits_T_46, 1, 0) node _T_1198 = shr(io.in.b.bits.source, 2) node _T_1199 = eq(_T_1198, UInt<2>(0h2)) node _T_1200 = leq(UInt<1>(0h0), uncommonBits_46) node _T_1201 = and(_T_1199, _T_1200) node _T_1202 = leq(uncommonBits_46, UInt<2>(0h3)) node _T_1203 = and(_T_1201, _T_1202) node _T_1204 = eq(_T_1203, UInt<1>(0h0)) node _T_1205 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1206 = cvt(_T_1205) node _T_1207 = and(_T_1206, asSInt(UInt<1>(0h0))) node _T_1208 = asSInt(_T_1207) node _T_1209 = eq(_T_1208, asSInt(UInt<1>(0h0))) node _T_1210 = or(_T_1204, _T_1209) node _uncommonBits_T_47 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_47 = bits(_uncommonBits_T_47, 1, 0) node _T_1211 = shr(io.in.b.bits.source, 2) node _T_1212 = eq(_T_1211, UInt<2>(0h3)) node _T_1213 = leq(UInt<1>(0h0), uncommonBits_47) node _T_1214 = and(_T_1212, _T_1213) node _T_1215 = leq(uncommonBits_47, UInt<2>(0h3)) node _T_1216 = and(_T_1214, _T_1215) node _T_1217 = eq(_T_1216, UInt<1>(0h0)) node _T_1218 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1219 = cvt(_T_1218) node _T_1220 = and(_T_1219, asSInt(UInt<1>(0h0))) node _T_1221 = asSInt(_T_1220) node _T_1222 = eq(_T_1221, asSInt(UInt<1>(0h0))) node _T_1223 = or(_T_1217, _T_1222) node _T_1224 = eq(io.in.b.bits.source, UInt<6>(0h2c)) node _T_1225 = eq(_T_1224, UInt<1>(0h0)) node _T_1226 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1227 = cvt(_T_1226) node _T_1228 = and(_T_1227, asSInt(UInt<1>(0h0))) node _T_1229 = asSInt(_T_1228) node _T_1230 = eq(_T_1229, asSInt(UInt<1>(0h0))) node _T_1231 = or(_T_1225, _T_1230) node _T_1232 = eq(io.in.b.bits.source, UInt<6>(0h2e)) node _T_1233 = eq(_T_1232, UInt<1>(0h0)) node _T_1234 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1235 = cvt(_T_1234) node _T_1236 = and(_T_1235, asSInt(UInt<1>(0h0))) node _T_1237 = asSInt(_T_1236) node _T_1238 = eq(_T_1237, asSInt(UInt<1>(0h0))) node _T_1239 = or(_T_1233, _T_1238) node _T_1240 = eq(io.in.b.bits.source, UInt<6>(0h28)) node _T_1241 = eq(_T_1240, UInt<1>(0h0)) node _T_1242 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1243 = cvt(_T_1242) node _T_1244 = and(_T_1243, asSInt(UInt<1>(0h0))) node _T_1245 = asSInt(_T_1244) node _T_1246 = eq(_T_1245, asSInt(UInt<1>(0h0))) node _T_1247 = or(_T_1241, _T_1246) node _T_1248 = eq(io.in.b.bits.source, UInt<6>(0h2a)) node _T_1249 = eq(_T_1248, UInt<1>(0h0)) node _T_1250 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1251 = cvt(_T_1250) node _T_1252 = and(_T_1251, asSInt(UInt<1>(0h0))) node _T_1253 = asSInt(_T_1252) node _T_1254 = eq(_T_1253, asSInt(UInt<1>(0h0))) node _T_1255 = or(_T_1249, _T_1254) node _T_1256 = eq(io.in.b.bits.source, UInt<6>(0h24)) node _T_1257 = eq(_T_1256, UInt<1>(0h0)) node _T_1258 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1259 = cvt(_T_1258) node _T_1260 = and(_T_1259, asSInt(UInt<1>(0h0))) node _T_1261 = asSInt(_T_1260) node _T_1262 = eq(_T_1261, asSInt(UInt<1>(0h0))) node _T_1263 = or(_T_1257, _T_1262) node _T_1264 = eq(io.in.b.bits.source, UInt<6>(0h26)) node _T_1265 = eq(_T_1264, UInt<1>(0h0)) node _T_1266 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1267 = cvt(_T_1266) node _T_1268 = and(_T_1267, asSInt(UInt<1>(0h0))) node _T_1269 = asSInt(_T_1268) node _T_1270 = eq(_T_1269, asSInt(UInt<1>(0h0))) node _T_1271 = or(_T_1265, _T_1270) node _T_1272 = eq(io.in.b.bits.source, UInt<6>(0h20)) node _T_1273 = eq(_T_1272, UInt<1>(0h0)) node _T_1274 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1275 = cvt(_T_1274) node _T_1276 = and(_T_1275, asSInt(UInt<1>(0h0))) node _T_1277 = asSInt(_T_1276) node _T_1278 = eq(_T_1277, asSInt(UInt<1>(0h0))) node _T_1279 = or(_T_1273, _T_1278) node _T_1280 = eq(io.in.b.bits.source, UInt<6>(0h22)) node _T_1281 = eq(_T_1280, UInt<1>(0h0)) node _T_1282 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1283 = cvt(_T_1282) node _T_1284 = and(_T_1283, asSInt(UInt<1>(0h0))) node _T_1285 = asSInt(_T_1284) node _T_1286 = eq(_T_1285, asSInt(UInt<1>(0h0))) node _T_1287 = or(_T_1281, _T_1286) node _T_1288 = and(_T_1171, _T_1184) node _T_1289 = and(_T_1288, _T_1197) node _T_1290 = and(_T_1289, _T_1210) node _T_1291 = and(_T_1290, _T_1223) node _T_1292 = and(_T_1291, _T_1231) node _T_1293 = and(_T_1292, _T_1239) node _T_1294 = and(_T_1293, _T_1247) node _T_1295 = and(_T_1294, _T_1255) node _T_1296 = and(_T_1295, _T_1263) node _T_1297 = and(_T_1296, _T_1271) node _T_1298 = and(_T_1297, _T_1279) node _T_1299 = and(_T_1298, _T_1287) node _T_1300 = asUInt(reset) node _T_1301 = eq(_T_1300, UInt<1>(0h0)) when _T_1301 : node _T_1302 = eq(_T_1299, UInt<1>(0h0)) when _T_1302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1299, UInt<1>(0h1), "") : assert_85 node _address_ok_T = xor(io.in.b.bits.address, UInt<28>(0h8000040)) node _address_ok_T_1 = cvt(_address_ok_T) node _address_ok_T_2 = and(_address_ok_T_1, asSInt(UInt<17>(0h100c0))) node _address_ok_T_3 = asSInt(_address_ok_T_2) node _address_ok_T_4 = eq(_address_ok_T_3, asSInt(UInt<1>(0h0))) node _address_ok_T_5 = xor(io.in.b.bits.address, UInt<32>(0h80000040)) node _address_ok_T_6 = cvt(_address_ok_T_5) node _address_ok_T_7 = and(_address_ok_T_6, asSInt(UInt<29>(0h100000c0))) node _address_ok_T_8 = asSInt(_address_ok_T_7) node _address_ok_T_9 = eq(_address_ok_T_8, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE : UInt<1>[2] connect _address_ok_WIRE[0], _address_ok_T_4 connect _address_ok_WIRE[1], _address_ok_T_9 node address_ok = or(_address_ok_WIRE[0], _address_ok_WIRE[1]) node _is_aligned_mask_T_2 = dshl(UInt<6>(0h3f), io.in.b.bits.size) node _is_aligned_mask_T_3 = bits(_is_aligned_mask_T_2, 5, 0) node is_aligned_mask_1 = not(_is_aligned_mask_T_3) node _is_aligned_T_1 = and(io.in.b.bits.address, is_aligned_mask_1) node is_aligned_1 = eq(_is_aligned_T_1, UInt<1>(0h0)) node _mask_sizeOH_T_3 = or(io.in.b.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount_1 = bits(_mask_sizeOH_T_3, 1, 0) node _mask_sizeOH_T_4 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount_1) node _mask_sizeOH_T_5 = bits(_mask_sizeOH_T_4, 2, 0) node mask_sizeOH_1 = or(_mask_sizeOH_T_5, UInt<1>(0h1)) node mask_sub_sub_sub_0_1_1 = geq(io.in.b.bits.size, UInt<2>(0h3)) node mask_sub_sub_size_1 = bits(mask_sizeOH_1, 2, 2) node mask_sub_sub_bit_1 = bits(io.in.b.bits.address, 2, 2) node mask_sub_sub_nbit_1 = eq(mask_sub_sub_bit_1, UInt<1>(0h0)) node mask_sub_sub_0_2_1 = and(UInt<1>(0h1), mask_sub_sub_nbit_1) node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size_1, mask_sub_sub_0_2_1) node mask_sub_sub_0_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_2) node mask_sub_sub_1_2_1 = and(UInt<1>(0h1), mask_sub_sub_bit_1) node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size_1, mask_sub_sub_1_2_1) node mask_sub_sub_1_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_3) node mask_sub_size_1 = bits(mask_sizeOH_1, 1, 1) node mask_sub_bit_1 = bits(io.in.b.bits.address, 1, 1) node mask_sub_nbit_1 = eq(mask_sub_bit_1, UInt<1>(0h0)) node mask_sub_0_2_1 = and(mask_sub_sub_0_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_4 = and(mask_sub_size_1, mask_sub_0_2_1) node mask_sub_0_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_4) node mask_sub_1_2_1 = and(mask_sub_sub_0_2_1, mask_sub_bit_1) node _mask_sub_acc_T_5 = and(mask_sub_size_1, mask_sub_1_2_1) node mask_sub_1_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_5) node mask_sub_2_2_1 = and(mask_sub_sub_1_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_6 = and(mask_sub_size_1, mask_sub_2_2_1) node mask_sub_2_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_6) node mask_sub_3_2_1 = and(mask_sub_sub_1_2_1, mask_sub_bit_1) node _mask_sub_acc_T_7 = and(mask_sub_size_1, mask_sub_3_2_1) node mask_sub_3_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_7) node mask_size_1 = bits(mask_sizeOH_1, 0, 0) node mask_bit_1 = bits(io.in.b.bits.address, 0, 0) node mask_nbit_1 = eq(mask_bit_1, UInt<1>(0h0)) node mask_eq_8 = and(mask_sub_0_2_1, mask_nbit_1) node _mask_acc_T_8 = and(mask_size_1, mask_eq_8) node mask_acc_8 = or(mask_sub_0_1_1, _mask_acc_T_8) node mask_eq_9 = and(mask_sub_0_2_1, mask_bit_1) node _mask_acc_T_9 = and(mask_size_1, mask_eq_9) node mask_acc_9 = or(mask_sub_0_1_1, _mask_acc_T_9) node mask_eq_10 = and(mask_sub_1_2_1, mask_nbit_1) node _mask_acc_T_10 = and(mask_size_1, mask_eq_10) node mask_acc_10 = or(mask_sub_1_1_1, _mask_acc_T_10) node mask_eq_11 = and(mask_sub_1_2_1, mask_bit_1) node _mask_acc_T_11 = and(mask_size_1, mask_eq_11) node mask_acc_11 = or(mask_sub_1_1_1, _mask_acc_T_11) node mask_eq_12 = and(mask_sub_2_2_1, mask_nbit_1) node _mask_acc_T_12 = and(mask_size_1, mask_eq_12) node mask_acc_12 = or(mask_sub_2_1_1, _mask_acc_T_12) node mask_eq_13 = and(mask_sub_2_2_1, mask_bit_1) node _mask_acc_T_13 = and(mask_size_1, mask_eq_13) node mask_acc_13 = or(mask_sub_2_1_1, _mask_acc_T_13) node mask_eq_14 = and(mask_sub_3_2_1, mask_nbit_1) node _mask_acc_T_14 = and(mask_size_1, mask_eq_14) node mask_acc_14 = or(mask_sub_3_1_1, _mask_acc_T_14) node mask_eq_15 = and(mask_sub_3_2_1, mask_bit_1) node _mask_acc_T_15 = and(mask_size_1, mask_eq_15) node mask_acc_15 = or(mask_sub_3_1_1, _mask_acc_T_15) node mask_lo_lo_1 = cat(mask_acc_9, mask_acc_8) node mask_lo_hi_1 = cat(mask_acc_11, mask_acc_10) node mask_lo_1 = cat(mask_lo_hi_1, mask_lo_lo_1) node mask_hi_lo_1 = cat(mask_acc_13, mask_acc_12) node mask_hi_hi_1 = cat(mask_acc_15, mask_acc_14) node mask_hi_1 = cat(mask_hi_hi_1, mask_hi_lo_1) node mask_1 = cat(mask_hi_1, mask_lo_1) node _legal_source_T = eq(io.in.b.bits.source, UInt<5>(0h10)) node _legal_source_uncommonBits_T = or(io.in.b.bits.source, UInt<2>(0h0)) node legal_source_uncommonBits = bits(_legal_source_uncommonBits_T, 1, 0) node _legal_source_T_1 = shr(io.in.b.bits.source, 2) node _legal_source_T_2 = eq(_legal_source_T_1, UInt<1>(0h0)) node _legal_source_T_3 = leq(UInt<1>(0h0), legal_source_uncommonBits) node _legal_source_T_4 = and(_legal_source_T_2, _legal_source_T_3) node _legal_source_T_5 = leq(legal_source_uncommonBits, UInt<2>(0h3)) node _legal_source_T_6 = and(_legal_source_T_4, _legal_source_T_5) node _legal_source_uncommonBits_T_1 = or(io.in.b.bits.source, UInt<2>(0h0)) node legal_source_uncommonBits_1 = bits(_legal_source_uncommonBits_T_1, 1, 0) node _legal_source_T_7 = shr(io.in.b.bits.source, 2) node _legal_source_T_8 = eq(_legal_source_T_7, UInt<1>(0h1)) node _legal_source_T_9 = leq(UInt<1>(0h0), legal_source_uncommonBits_1) node _legal_source_T_10 = and(_legal_source_T_8, _legal_source_T_9) node _legal_source_T_11 = leq(legal_source_uncommonBits_1, UInt<2>(0h3)) node _legal_source_T_12 = and(_legal_source_T_10, _legal_source_T_11) node _legal_source_uncommonBits_T_2 = or(io.in.b.bits.source, UInt<2>(0h0)) node legal_source_uncommonBits_2 = bits(_legal_source_uncommonBits_T_2, 1, 0) node _legal_source_T_13 = shr(io.in.b.bits.source, 2) node _legal_source_T_14 = eq(_legal_source_T_13, UInt<2>(0h2)) node _legal_source_T_15 = leq(UInt<1>(0h0), legal_source_uncommonBits_2) node _legal_source_T_16 = and(_legal_source_T_14, _legal_source_T_15) node _legal_source_T_17 = leq(legal_source_uncommonBits_2, UInt<2>(0h3)) node _legal_source_T_18 = and(_legal_source_T_16, _legal_source_T_17) node _legal_source_uncommonBits_T_3 = or(io.in.b.bits.source, UInt<2>(0h0)) node legal_source_uncommonBits_3 = bits(_legal_source_uncommonBits_T_3, 1, 0) node _legal_source_T_19 = shr(io.in.b.bits.source, 2) node _legal_source_T_20 = eq(_legal_source_T_19, UInt<2>(0h3)) node _legal_source_T_21 = leq(UInt<1>(0h0), legal_source_uncommonBits_3) node _legal_source_T_22 = and(_legal_source_T_20, _legal_source_T_21) node _legal_source_T_23 = leq(legal_source_uncommonBits_3, UInt<2>(0h3)) node _legal_source_T_24 = and(_legal_source_T_22, _legal_source_T_23) node _legal_source_T_25 = eq(io.in.b.bits.source, UInt<6>(0h2c)) node _legal_source_T_26 = eq(io.in.b.bits.source, UInt<6>(0h2e)) node _legal_source_T_27 = eq(io.in.b.bits.source, UInt<6>(0h28)) node _legal_source_T_28 = eq(io.in.b.bits.source, UInt<6>(0h2a)) node _legal_source_T_29 = eq(io.in.b.bits.source, UInt<6>(0h24)) node _legal_source_T_30 = eq(io.in.b.bits.source, UInt<6>(0h26)) node _legal_source_T_31 = eq(io.in.b.bits.source, UInt<6>(0h20)) node _legal_source_T_32 = eq(io.in.b.bits.source, UInt<6>(0h22)) wire _legal_source_WIRE : UInt<1>[13] connect _legal_source_WIRE[0], _legal_source_T connect _legal_source_WIRE[1], _legal_source_T_6 connect _legal_source_WIRE[2], _legal_source_T_12 connect _legal_source_WIRE[3], _legal_source_T_18 connect _legal_source_WIRE[4], _legal_source_T_24 connect _legal_source_WIRE[5], _legal_source_T_25 connect _legal_source_WIRE[6], _legal_source_T_26 connect _legal_source_WIRE[7], _legal_source_T_27 connect _legal_source_WIRE[8], _legal_source_T_28 connect _legal_source_WIRE[9], _legal_source_T_29 connect _legal_source_WIRE[10], _legal_source_T_30 connect _legal_source_WIRE[11], _legal_source_T_31 connect _legal_source_WIRE[12], _legal_source_T_32 node _legal_source_T_33 = mux(_legal_source_WIRE[0], UInt<5>(0h10), UInt<1>(0h0)) node _legal_source_T_34 = mux(_legal_source_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _legal_source_T_35 = mux(_legal_source_WIRE[2], UInt<3>(0h4), UInt<1>(0h0)) node _legal_source_T_36 = mux(_legal_source_WIRE[3], UInt<4>(0h8), UInt<1>(0h0)) node _legal_source_T_37 = mux(_legal_source_WIRE[4], UInt<4>(0hc), UInt<1>(0h0)) node _legal_source_T_38 = mux(_legal_source_WIRE[5], UInt<6>(0h2c), UInt<1>(0h0)) node _legal_source_T_39 = mux(_legal_source_WIRE[6], UInt<6>(0h2e), UInt<1>(0h0)) node _legal_source_T_40 = mux(_legal_source_WIRE[7], UInt<6>(0h28), UInt<1>(0h0)) node _legal_source_T_41 = mux(_legal_source_WIRE[8], UInt<6>(0h2a), UInt<1>(0h0)) node _legal_source_T_42 = mux(_legal_source_WIRE[9], UInt<6>(0h24), UInt<1>(0h0)) node _legal_source_T_43 = mux(_legal_source_WIRE[10], UInt<6>(0h26), UInt<1>(0h0)) node _legal_source_T_44 = mux(_legal_source_WIRE[11], UInt<6>(0h20), UInt<1>(0h0)) node _legal_source_T_45 = mux(_legal_source_WIRE[12], UInt<6>(0h22), UInt<1>(0h0)) node _legal_source_T_46 = or(_legal_source_T_33, _legal_source_T_34) node _legal_source_T_47 = or(_legal_source_T_46, _legal_source_T_35) node _legal_source_T_48 = or(_legal_source_T_47, _legal_source_T_36) node _legal_source_T_49 = or(_legal_source_T_48, _legal_source_T_37) node _legal_source_T_50 = or(_legal_source_T_49, _legal_source_T_38) node _legal_source_T_51 = or(_legal_source_T_50, _legal_source_T_39) node _legal_source_T_52 = or(_legal_source_T_51, _legal_source_T_40) node _legal_source_T_53 = or(_legal_source_T_52, _legal_source_T_41) node _legal_source_T_54 = or(_legal_source_T_53, _legal_source_T_42) node _legal_source_T_55 = or(_legal_source_T_54, _legal_source_T_43) node _legal_source_T_56 = or(_legal_source_T_55, _legal_source_T_44) node _legal_source_T_57 = or(_legal_source_T_56, _legal_source_T_45) wire _legal_source_WIRE_1 : UInt<6> connect _legal_source_WIRE_1, _legal_source_T_57 node legal_source = eq(_legal_source_WIRE_1, io.in.b.bits.source) node _T_1303 = eq(io.in.b.bits.opcode, UInt<3>(0h6)) when _T_1303 : node _T_1304 = eq(io.in.b.bits.source, UInt<5>(0h10)) node _uncommonBits_T_48 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0) node _T_1305 = shr(io.in.b.bits.source, 2) node _T_1306 = eq(_T_1305, UInt<1>(0h0)) node _T_1307 = leq(UInt<1>(0h0), uncommonBits_48) node _T_1308 = and(_T_1306, _T_1307) node _T_1309 = leq(uncommonBits_48, UInt<2>(0h3)) node _T_1310 = and(_T_1308, _T_1309) node _uncommonBits_T_49 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_49 = bits(_uncommonBits_T_49, 1, 0) node _T_1311 = shr(io.in.b.bits.source, 2) node _T_1312 = eq(_T_1311, UInt<1>(0h1)) node _T_1313 = leq(UInt<1>(0h0), uncommonBits_49) node _T_1314 = and(_T_1312, _T_1313) node _T_1315 = leq(uncommonBits_49, UInt<2>(0h3)) node _T_1316 = and(_T_1314, _T_1315) node _uncommonBits_T_50 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0) node _T_1317 = shr(io.in.b.bits.source, 2) node _T_1318 = eq(_T_1317, UInt<2>(0h2)) node _T_1319 = leq(UInt<1>(0h0), uncommonBits_50) node _T_1320 = and(_T_1318, _T_1319) node _T_1321 = leq(uncommonBits_50, UInt<2>(0h3)) node _T_1322 = and(_T_1320, _T_1321) node _uncommonBits_T_51 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0) node _T_1323 = shr(io.in.b.bits.source, 2) node _T_1324 = eq(_T_1323, UInt<2>(0h3)) node _T_1325 = leq(UInt<1>(0h0), uncommonBits_51) node _T_1326 = and(_T_1324, _T_1325) node _T_1327 = leq(uncommonBits_51, UInt<2>(0h3)) node _T_1328 = and(_T_1326, _T_1327) node _T_1329 = eq(io.in.b.bits.source, UInt<6>(0h2c)) node _T_1330 = eq(io.in.b.bits.source, UInt<6>(0h2e)) node _T_1331 = eq(io.in.b.bits.source, UInt<6>(0h28)) node _T_1332 = eq(io.in.b.bits.source, UInt<6>(0h2a)) node _T_1333 = eq(io.in.b.bits.source, UInt<6>(0h24)) node _T_1334 = eq(io.in.b.bits.source, UInt<6>(0h26)) node _T_1335 = eq(io.in.b.bits.source, UInt<6>(0h20)) node _T_1336 = eq(io.in.b.bits.source, UInt<6>(0h22)) wire _WIRE_4 : UInt<1>[13] connect _WIRE_4[0], _T_1304 connect _WIRE_4[1], _T_1310 connect _WIRE_4[2], _T_1316 connect _WIRE_4[3], _T_1322 connect _WIRE_4[4], _T_1328 connect _WIRE_4[5], _T_1329 connect _WIRE_4[6], _T_1330 connect _WIRE_4[7], _T_1331 connect _WIRE_4[8], _T_1332 connect _WIRE_4[9], _T_1333 connect _WIRE_4[10], _T_1334 connect _WIRE_4[11], _T_1335 connect _WIRE_4[12], _T_1336 node _T_1337 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1338 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1339 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1340 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1341 = mux(_WIRE_4[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_1342 = mux(_WIRE_4[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1343 = mux(_WIRE_4[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_1344 = mux(_WIRE_4[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_1345 = mux(_WIRE_4[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_1346 = mux(_WIRE_4[5], _T_1337, UInt<1>(0h0)) node _T_1347 = mux(_WIRE_4[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_1348 = mux(_WIRE_4[7], _T_1338, UInt<1>(0h0)) node _T_1349 = mux(_WIRE_4[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_1350 = mux(_WIRE_4[9], _T_1339, UInt<1>(0h0)) node _T_1351 = mux(_WIRE_4[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_1352 = mux(_WIRE_4[11], _T_1340, UInt<1>(0h0)) node _T_1353 = mux(_WIRE_4[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_1354 = or(_T_1341, _T_1342) node _T_1355 = or(_T_1354, _T_1343) node _T_1356 = or(_T_1355, _T_1344) node _T_1357 = or(_T_1356, _T_1345) node _T_1358 = or(_T_1357, _T_1346) node _T_1359 = or(_T_1358, _T_1347) node _T_1360 = or(_T_1359, _T_1348) node _T_1361 = or(_T_1360, _T_1349) node _T_1362 = or(_T_1361, _T_1350) node _T_1363 = or(_T_1362, _T_1351) node _T_1364 = or(_T_1363, _T_1352) node _T_1365 = or(_T_1364, _T_1353) wire _WIRE_5 : UInt<1> connect _WIRE_5, _T_1365 node _T_1366 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1367 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1368 = and(_T_1366, _T_1367) node _T_1369 = or(UInt<1>(0h0), _T_1368) node _T_1370 = xor(io.in.b.bits.address, UInt<28>(0h8000040)) node _T_1371 = cvt(_T_1370) node _T_1372 = and(_T_1371, asSInt(UInt<17>(0h100c0))) node _T_1373 = asSInt(_T_1372) node _T_1374 = eq(_T_1373, asSInt(UInt<1>(0h0))) node _T_1375 = xor(io.in.b.bits.address, UInt<32>(0h80000040)) node _T_1376 = cvt(_T_1375) node _T_1377 = and(_T_1376, asSInt(UInt<29>(0h100000c0))) node _T_1378 = asSInt(_T_1377) node _T_1379 = eq(_T_1378, asSInt(UInt<1>(0h0))) node _T_1380 = or(_T_1374, _T_1379) node _T_1381 = and(_T_1369, _T_1380) node _T_1382 = or(UInt<1>(0h0), _T_1381) node _T_1383 = and(_WIRE_5, _T_1382) node _T_1384 = asUInt(reset) node _T_1385 = eq(_T_1384, UInt<1>(0h0)) when _T_1385 : node _T_1386 = eq(_T_1383, UInt<1>(0h0)) when _T_1386 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_86 assert(clock, _T_1383, UInt<1>(0h1), "") : assert_86 node _T_1387 = asUInt(reset) node _T_1388 = eq(_T_1387, UInt<1>(0h0)) when _T_1388 : node _T_1389 = eq(address_ok, UInt<1>(0h0)) when _T_1389 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_87 assert(clock, address_ok, UInt<1>(0h1), "") : assert_87 node _T_1390 = asUInt(reset) node _T_1391 = eq(_T_1390, UInt<1>(0h0)) when _T_1391 : node _T_1392 = eq(legal_source, UInt<1>(0h0)) when _T_1392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_88 assert(clock, legal_source, UInt<1>(0h1), "") : assert_88 node _T_1393 = asUInt(reset) node _T_1394 = eq(_T_1393, UInt<1>(0h0)) when _T_1394 : node _T_1395 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1395 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_89 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_89 node _T_1396 = leq(io.in.b.bits.param, UInt<2>(0h2)) node _T_1397 = asUInt(reset) node _T_1398 = eq(_T_1397, UInt<1>(0h0)) when _T_1398 : node _T_1399 = eq(_T_1396, UInt<1>(0h0)) when _T_1399 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_90 assert(clock, _T_1396, UInt<1>(0h1), "") : assert_90 node _T_1400 = eq(io.in.b.bits.mask, mask_1) node _T_1401 = asUInt(reset) node _T_1402 = eq(_T_1401, UInt<1>(0h0)) when _T_1402 : node _T_1403 = eq(_T_1400, UInt<1>(0h0)) when _T_1403 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_91 assert(clock, _T_1400, UInt<1>(0h1), "") : assert_91 node _T_1404 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1405 = asUInt(reset) node _T_1406 = eq(_T_1405, UInt<1>(0h0)) when _T_1406 : node _T_1407 = eq(_T_1404, UInt<1>(0h0)) when _T_1407 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1404, UInt<1>(0h1), "") : assert_92 node _T_1408 = eq(io.in.b.bits.opcode, UInt<3>(0h4)) when _T_1408 : node _T_1409 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1410 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1411 = and(_T_1409, _T_1410) node _T_1412 = or(UInt<1>(0h0), _T_1411) node _T_1413 = xor(io.in.b.bits.address, UInt<28>(0h8000040)) node _T_1414 = cvt(_T_1413) node _T_1415 = and(_T_1414, asSInt(UInt<17>(0h100c0))) node _T_1416 = asSInt(_T_1415) node _T_1417 = eq(_T_1416, asSInt(UInt<1>(0h0))) node _T_1418 = xor(io.in.b.bits.address, UInt<32>(0h80000040)) node _T_1419 = cvt(_T_1418) node _T_1420 = and(_T_1419, asSInt(UInt<29>(0h100000c0))) node _T_1421 = asSInt(_T_1420) node _T_1422 = eq(_T_1421, asSInt(UInt<1>(0h0))) node _T_1423 = or(_T_1417, _T_1422) node _T_1424 = and(_T_1412, _T_1423) node _T_1425 = or(UInt<1>(0h0), _T_1424) node _T_1426 = and(UInt<1>(0h0), _T_1425) node _T_1427 = asUInt(reset) node _T_1428 = eq(_T_1427, UInt<1>(0h0)) when _T_1428 : node _T_1429 = eq(_T_1426, UInt<1>(0h0)) when _T_1429 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Get type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_93 assert(clock, _T_1426, UInt<1>(0h1), "") : assert_93 node _T_1430 = asUInt(reset) node _T_1431 = eq(_T_1430, UInt<1>(0h0)) when _T_1431 : node _T_1432 = eq(address_ok, UInt<1>(0h0)) when _T_1432 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_94 assert(clock, address_ok, UInt<1>(0h1), "") : assert_94 node _T_1433 = asUInt(reset) node _T_1434 = eq(_T_1433, UInt<1>(0h0)) when _T_1434 : node _T_1435 = eq(legal_source, UInt<1>(0h0)) when _T_1435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_95 assert(clock, legal_source, UInt<1>(0h1), "") : assert_95 node _T_1436 = asUInt(reset) node _T_1437 = eq(_T_1436, UInt<1>(0h0)) when _T_1437 : node _T_1438 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1438 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_96 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_96 node _T_1439 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1440 = asUInt(reset) node _T_1441 = eq(_T_1440, UInt<1>(0h0)) when _T_1441 : node _T_1442 = eq(_T_1439, UInt<1>(0h0)) when _T_1442 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_97 assert(clock, _T_1439, UInt<1>(0h1), "") : assert_97 node _T_1443 = eq(io.in.b.bits.mask, mask_1) node _T_1444 = asUInt(reset) node _T_1445 = eq(_T_1444, UInt<1>(0h0)) when _T_1445 : node _T_1446 = eq(_T_1443, UInt<1>(0h0)) when _T_1446 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1443, UInt<1>(0h1), "") : assert_98 node _T_1447 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1448 = asUInt(reset) node _T_1449 = eq(_T_1448, UInt<1>(0h0)) when _T_1449 : node _T_1450 = eq(_T_1447, UInt<1>(0h0)) when _T_1450 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_99 assert(clock, _T_1447, UInt<1>(0h1), "") : assert_99 node _T_1451 = eq(io.in.b.bits.opcode, UInt<1>(0h0)) when _T_1451 : node _T_1452 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1453 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1454 = and(_T_1452, _T_1453) node _T_1455 = or(UInt<1>(0h0), _T_1454) node _T_1456 = xor(io.in.b.bits.address, UInt<28>(0h8000040)) node _T_1457 = cvt(_T_1456) node _T_1458 = and(_T_1457, asSInt(UInt<17>(0h100c0))) node _T_1459 = asSInt(_T_1458) node _T_1460 = eq(_T_1459, asSInt(UInt<1>(0h0))) node _T_1461 = xor(io.in.b.bits.address, UInt<32>(0h80000040)) node _T_1462 = cvt(_T_1461) node _T_1463 = and(_T_1462, asSInt(UInt<29>(0h100000c0))) node _T_1464 = asSInt(_T_1463) node _T_1465 = eq(_T_1464, asSInt(UInt<1>(0h0))) node _T_1466 = or(_T_1460, _T_1465) node _T_1467 = and(_T_1455, _T_1466) node _T_1468 = or(UInt<1>(0h0), _T_1467) node _T_1469 = and(UInt<1>(0h0), _T_1468) node _T_1470 = asUInt(reset) node _T_1471 = eq(_T_1470, UInt<1>(0h0)) when _T_1471 : node _T_1472 = eq(_T_1469, UInt<1>(0h0)) when _T_1472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_100 assert(clock, _T_1469, UInt<1>(0h1), "") : assert_100 node _T_1473 = asUInt(reset) node _T_1474 = eq(_T_1473, UInt<1>(0h0)) when _T_1474 : node _T_1475 = eq(address_ok, UInt<1>(0h0)) when _T_1475 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_101 assert(clock, address_ok, UInt<1>(0h1), "") : assert_101 node _T_1476 = asUInt(reset) node _T_1477 = eq(_T_1476, UInt<1>(0h0)) when _T_1477 : node _T_1478 = eq(legal_source, UInt<1>(0h0)) when _T_1478 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_102 assert(clock, legal_source, UInt<1>(0h1), "") : assert_102 node _T_1479 = asUInt(reset) node _T_1480 = eq(_T_1479, UInt<1>(0h0)) when _T_1480 : node _T_1481 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_103 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_103 node _T_1482 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1483 = asUInt(reset) node _T_1484 = eq(_T_1483, UInt<1>(0h0)) when _T_1484 : node _T_1485 = eq(_T_1482, UInt<1>(0h0)) when _T_1485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_104 assert(clock, _T_1482, UInt<1>(0h1), "") : assert_104 node _T_1486 = eq(io.in.b.bits.mask, mask_1) node _T_1487 = asUInt(reset) node _T_1488 = eq(_T_1487, UInt<1>(0h0)) when _T_1488 : node _T_1489 = eq(_T_1486, UInt<1>(0h0)) when _T_1489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1486, UInt<1>(0h1), "") : assert_105 node _T_1490 = eq(io.in.b.bits.opcode, UInt<1>(0h1)) when _T_1490 : node _T_1491 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1492 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1493 = and(_T_1491, _T_1492) node _T_1494 = or(UInt<1>(0h0), _T_1493) node _T_1495 = xor(io.in.b.bits.address, UInt<28>(0h8000040)) node _T_1496 = cvt(_T_1495) node _T_1497 = and(_T_1496, asSInt(UInt<17>(0h100c0))) node _T_1498 = asSInt(_T_1497) node _T_1499 = eq(_T_1498, asSInt(UInt<1>(0h0))) node _T_1500 = xor(io.in.b.bits.address, UInt<32>(0h80000040)) node _T_1501 = cvt(_T_1500) node _T_1502 = and(_T_1501, asSInt(UInt<29>(0h100000c0))) node _T_1503 = asSInt(_T_1502) node _T_1504 = eq(_T_1503, asSInt(UInt<1>(0h0))) node _T_1505 = or(_T_1499, _T_1504) node _T_1506 = and(_T_1494, _T_1505) node _T_1507 = or(UInt<1>(0h0), _T_1506) node _T_1508 = and(UInt<1>(0h0), _T_1507) node _T_1509 = asUInt(reset) node _T_1510 = eq(_T_1509, UInt<1>(0h0)) when _T_1510 : node _T_1511 = eq(_T_1508, UInt<1>(0h0)) when _T_1511 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1508, UInt<1>(0h1), "") : assert_106 node _T_1512 = asUInt(reset) node _T_1513 = eq(_T_1512, UInt<1>(0h0)) when _T_1513 : node _T_1514 = eq(address_ok, UInt<1>(0h0)) when _T_1514 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, address_ok, UInt<1>(0h1), "") : assert_107 node _T_1515 = asUInt(reset) node _T_1516 = eq(_T_1515, UInt<1>(0h0)) when _T_1516 : node _T_1517 = eq(legal_source, UInt<1>(0h0)) when _T_1517 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_108 assert(clock, legal_source, UInt<1>(0h1), "") : assert_108 node _T_1518 = asUInt(reset) node _T_1519 = eq(_T_1518, UInt<1>(0h0)) when _T_1519 : node _T_1520 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_109 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_109 node _T_1521 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1522 = asUInt(reset) node _T_1523 = eq(_T_1522, UInt<1>(0h0)) when _T_1523 : node _T_1524 = eq(_T_1521, UInt<1>(0h0)) when _T_1524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_110 assert(clock, _T_1521, UInt<1>(0h1), "") : assert_110 node _T_1525 = not(mask_1) node _T_1526 = and(io.in.b.bits.mask, _T_1525) node _T_1527 = eq(_T_1526, UInt<1>(0h0)) node _T_1528 = asUInt(reset) node _T_1529 = eq(_T_1528, UInt<1>(0h0)) when _T_1529 : node _T_1530 = eq(_T_1527, UInt<1>(0h0)) when _T_1530 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1527, UInt<1>(0h1), "") : assert_111 node _T_1531 = eq(io.in.b.bits.opcode, UInt<2>(0h2)) when _T_1531 : node _T_1532 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1533 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1534 = and(_T_1532, _T_1533) node _T_1535 = or(UInt<1>(0h0), _T_1534) node _T_1536 = xor(io.in.b.bits.address, UInt<28>(0h8000040)) node _T_1537 = cvt(_T_1536) node _T_1538 = and(_T_1537, asSInt(UInt<17>(0h100c0))) node _T_1539 = asSInt(_T_1538) node _T_1540 = eq(_T_1539, asSInt(UInt<1>(0h0))) node _T_1541 = xor(io.in.b.bits.address, UInt<32>(0h80000040)) node _T_1542 = cvt(_T_1541) node _T_1543 = and(_T_1542, asSInt(UInt<29>(0h100000c0))) node _T_1544 = asSInt(_T_1543) node _T_1545 = eq(_T_1544, asSInt(UInt<1>(0h0))) node _T_1546 = or(_T_1540, _T_1545) node _T_1547 = and(_T_1535, _T_1546) node _T_1548 = or(UInt<1>(0h0), _T_1547) node _T_1549 = and(UInt<1>(0h0), _T_1548) node _T_1550 = asUInt(reset) node _T_1551 = eq(_T_1550, UInt<1>(0h0)) when _T_1551 : node _T_1552 = eq(_T_1549, UInt<1>(0h0)) when _T_1552 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by master (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_112 assert(clock, _T_1549, UInt<1>(0h1), "") : assert_112 node _T_1553 = asUInt(reset) node _T_1554 = eq(_T_1553, UInt<1>(0h0)) when _T_1554 : node _T_1555 = eq(address_ok, UInt<1>(0h0)) when _T_1555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, address_ok, UInt<1>(0h1), "") : assert_113 node _T_1556 = asUInt(reset) node _T_1557 = eq(_T_1556, UInt<1>(0h0)) when _T_1557 : node _T_1558 = eq(legal_source, UInt<1>(0h0)) when _T_1558 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_114 assert(clock, legal_source, UInt<1>(0h1), "") : assert_114 node _T_1559 = asUInt(reset) node _T_1560 = eq(_T_1559, UInt<1>(0h0)) when _T_1560 : node _T_1561 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1561 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_115 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_115 node _T_1562 = leq(io.in.b.bits.param, UInt<3>(0h4)) node _T_1563 = asUInt(reset) node _T_1564 = eq(_T_1563, UInt<1>(0h0)) when _T_1564 : node _T_1565 = eq(_T_1562, UInt<1>(0h0)) when _T_1565 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_116 assert(clock, _T_1562, UInt<1>(0h1), "") : assert_116 node _T_1566 = eq(io.in.b.bits.mask, mask_1) node _T_1567 = asUInt(reset) node _T_1568 = eq(_T_1567, UInt<1>(0h0)) when _T_1568 : node _T_1569 = eq(_T_1566, UInt<1>(0h0)) when _T_1569 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_117 assert(clock, _T_1566, UInt<1>(0h1), "") : assert_117 node _T_1570 = eq(io.in.b.bits.opcode, UInt<2>(0h3)) when _T_1570 : node _T_1571 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1572 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1573 = and(_T_1571, _T_1572) node _T_1574 = or(UInt<1>(0h0), _T_1573) node _T_1575 = xor(io.in.b.bits.address, UInt<28>(0h8000040)) node _T_1576 = cvt(_T_1575) node _T_1577 = and(_T_1576, asSInt(UInt<17>(0h100c0))) node _T_1578 = asSInt(_T_1577) node _T_1579 = eq(_T_1578, asSInt(UInt<1>(0h0))) node _T_1580 = xor(io.in.b.bits.address, UInt<32>(0h80000040)) node _T_1581 = cvt(_T_1580) node _T_1582 = and(_T_1581, asSInt(UInt<29>(0h100000c0))) node _T_1583 = asSInt(_T_1582) node _T_1584 = eq(_T_1583, asSInt(UInt<1>(0h0))) node _T_1585 = or(_T_1579, _T_1584) node _T_1586 = and(_T_1574, _T_1585) node _T_1587 = or(UInt<1>(0h0), _T_1586) node _T_1588 = and(UInt<1>(0h0), _T_1587) node _T_1589 = asUInt(reset) node _T_1590 = eq(_T_1589, UInt<1>(0h0)) when _T_1590 : node _T_1591 = eq(_T_1588, UInt<1>(0h0)) when _T_1591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_118 assert(clock, _T_1588, UInt<1>(0h1), "") : assert_118 node _T_1592 = asUInt(reset) node _T_1593 = eq(_T_1592, UInt<1>(0h0)) when _T_1593 : node _T_1594 = eq(address_ok, UInt<1>(0h0)) when _T_1594 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_119 assert(clock, address_ok, UInt<1>(0h1), "") : assert_119 node _T_1595 = asUInt(reset) node _T_1596 = eq(_T_1595, UInt<1>(0h0)) when _T_1596 : node _T_1597 = eq(legal_source, UInt<1>(0h0)) when _T_1597 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_120 assert(clock, legal_source, UInt<1>(0h1), "") : assert_120 node _T_1598 = asUInt(reset) node _T_1599 = eq(_T_1598, UInt<1>(0h0)) when _T_1599 : node _T_1600 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1600 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_121 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_121 node _T_1601 = leq(io.in.b.bits.param, UInt<3>(0h3)) node _T_1602 = asUInt(reset) node _T_1603 = eq(_T_1602, UInt<1>(0h0)) when _T_1603 : node _T_1604 = eq(_T_1601, UInt<1>(0h0)) when _T_1604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_122 assert(clock, _T_1601, UInt<1>(0h1), "") : assert_122 node _T_1605 = eq(io.in.b.bits.mask, mask_1) node _T_1606 = asUInt(reset) node _T_1607 = eq(_T_1606, UInt<1>(0h0)) when _T_1607 : node _T_1608 = eq(_T_1605, UInt<1>(0h0)) when _T_1608 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_123 assert(clock, _T_1605, UInt<1>(0h1), "") : assert_123 node _T_1609 = eq(io.in.b.bits.opcode, UInt<3>(0h5)) when _T_1609 : node _T_1610 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1611 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1612 = and(_T_1610, _T_1611) node _T_1613 = or(UInt<1>(0h0), _T_1612) node _T_1614 = xor(io.in.b.bits.address, UInt<28>(0h8000040)) node _T_1615 = cvt(_T_1614) node _T_1616 = and(_T_1615, asSInt(UInt<17>(0h100c0))) node _T_1617 = asSInt(_T_1616) node _T_1618 = eq(_T_1617, asSInt(UInt<1>(0h0))) node _T_1619 = xor(io.in.b.bits.address, UInt<32>(0h80000040)) node _T_1620 = cvt(_T_1619) node _T_1621 = and(_T_1620, asSInt(UInt<29>(0h100000c0))) node _T_1622 = asSInt(_T_1621) node _T_1623 = eq(_T_1622, asSInt(UInt<1>(0h0))) node _T_1624 = or(_T_1618, _T_1623) node _T_1625 = and(_T_1613, _T_1624) node _T_1626 = or(UInt<1>(0h0), _T_1625) node _T_1627 = and(UInt<1>(0h0), _T_1626) node _T_1628 = asUInt(reset) node _T_1629 = eq(_T_1628, UInt<1>(0h0)) when _T_1629 : node _T_1630 = eq(_T_1627, UInt<1>(0h0)) when _T_1630 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_124 assert(clock, _T_1627, UInt<1>(0h1), "") : assert_124 node _T_1631 = asUInt(reset) node _T_1632 = eq(_T_1631, UInt<1>(0h0)) when _T_1632 : node _T_1633 = eq(address_ok, UInt<1>(0h0)) when _T_1633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_125 assert(clock, address_ok, UInt<1>(0h1), "") : assert_125 node _T_1634 = asUInt(reset) node _T_1635 = eq(_T_1634, UInt<1>(0h0)) when _T_1635 : node _T_1636 = eq(legal_source, UInt<1>(0h0)) when _T_1636 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_126 assert(clock, legal_source, UInt<1>(0h1), "") : assert_126 node _T_1637 = asUInt(reset) node _T_1638 = eq(_T_1637, UInt<1>(0h0)) when _T_1638 : node _T_1639 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_127 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_127 node _T_1640 = eq(io.in.b.bits.mask, mask_1) node _T_1641 = asUInt(reset) node _T_1642 = eq(_T_1641, UInt<1>(0h0)) when _T_1642 : node _T_1643 = eq(_T_1640, UInt<1>(0h0)) when _T_1643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_128 assert(clock, _T_1640, UInt<1>(0h1), "") : assert_128 node _T_1644 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1645 = asUInt(reset) node _T_1646 = eq(_T_1645, UInt<1>(0h0)) when _T_1646 : node _T_1647 = eq(_T_1644, UInt<1>(0h0)) when _T_1647 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_129 assert(clock, _T_1644, UInt<1>(0h1), "") : assert_129 when io.in.c.valid : node _T_1648 = leq(io.in.c.bits.opcode, UInt<3>(0h7)) node _T_1649 = asUInt(reset) node _T_1650 = eq(_T_1649, UInt<1>(0h0)) when _T_1650 : node _T_1651 = eq(_T_1648, UInt<1>(0h0)) when _T_1651 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_130 assert(clock, _T_1648, UInt<1>(0h1), "") : assert_130 node _source_ok_T_88 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_8 = or(io.in.c.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0) node _source_ok_T_89 = shr(io.in.c.bits.source, 2) node _source_ok_T_90 = eq(_source_ok_T_89, UInt<1>(0h0)) node _source_ok_T_91 = leq(UInt<1>(0h0), source_ok_uncommonBits_8) node _source_ok_T_92 = and(_source_ok_T_90, _source_ok_T_91) node _source_ok_T_93 = leq(source_ok_uncommonBits_8, UInt<2>(0h3)) node _source_ok_T_94 = and(_source_ok_T_92, _source_ok_T_93) node _source_ok_uncommonBits_T_9 = or(io.in.c.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 1, 0) node _source_ok_T_95 = shr(io.in.c.bits.source, 2) node _source_ok_T_96 = eq(_source_ok_T_95, UInt<1>(0h1)) node _source_ok_T_97 = leq(UInt<1>(0h0), source_ok_uncommonBits_9) node _source_ok_T_98 = and(_source_ok_T_96, _source_ok_T_97) node _source_ok_T_99 = leq(source_ok_uncommonBits_9, UInt<2>(0h3)) node _source_ok_T_100 = and(_source_ok_T_98, _source_ok_T_99) node _source_ok_uncommonBits_T_10 = or(io.in.c.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 1, 0) node _source_ok_T_101 = shr(io.in.c.bits.source, 2) node _source_ok_T_102 = eq(_source_ok_T_101, UInt<2>(0h2)) node _source_ok_T_103 = leq(UInt<1>(0h0), source_ok_uncommonBits_10) node _source_ok_T_104 = and(_source_ok_T_102, _source_ok_T_103) node _source_ok_T_105 = leq(source_ok_uncommonBits_10, UInt<2>(0h3)) node _source_ok_T_106 = and(_source_ok_T_104, _source_ok_T_105) node _source_ok_uncommonBits_T_11 = or(io.in.c.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 1, 0) node _source_ok_T_107 = shr(io.in.c.bits.source, 2) node _source_ok_T_108 = eq(_source_ok_T_107, UInt<2>(0h3)) node _source_ok_T_109 = leq(UInt<1>(0h0), source_ok_uncommonBits_11) node _source_ok_T_110 = and(_source_ok_T_108, _source_ok_T_109) node _source_ok_T_111 = leq(source_ok_uncommonBits_11, UInt<2>(0h3)) node _source_ok_T_112 = and(_source_ok_T_110, _source_ok_T_111) node _source_ok_T_113 = eq(io.in.c.bits.source, UInt<6>(0h2c)) node _source_ok_T_114 = eq(io.in.c.bits.source, UInt<6>(0h2e)) node _source_ok_T_115 = eq(io.in.c.bits.source, UInt<6>(0h28)) node _source_ok_T_116 = eq(io.in.c.bits.source, UInt<6>(0h2a)) node _source_ok_T_117 = eq(io.in.c.bits.source, UInt<6>(0h24)) node _source_ok_T_118 = eq(io.in.c.bits.source, UInt<6>(0h26)) node _source_ok_T_119 = eq(io.in.c.bits.source, UInt<6>(0h20)) node _source_ok_T_120 = eq(io.in.c.bits.source, UInt<6>(0h22)) wire _source_ok_WIRE_2 : UInt<1>[13] connect _source_ok_WIRE_2[0], _source_ok_T_88 connect _source_ok_WIRE_2[1], _source_ok_T_94 connect _source_ok_WIRE_2[2], _source_ok_T_100 connect _source_ok_WIRE_2[3], _source_ok_T_106 connect _source_ok_WIRE_2[4], _source_ok_T_112 connect _source_ok_WIRE_2[5], _source_ok_T_113 connect _source_ok_WIRE_2[6], _source_ok_T_114 connect _source_ok_WIRE_2[7], _source_ok_T_115 connect _source_ok_WIRE_2[8], _source_ok_T_116 connect _source_ok_WIRE_2[9], _source_ok_T_117 connect _source_ok_WIRE_2[10], _source_ok_T_118 connect _source_ok_WIRE_2[11], _source_ok_T_119 connect _source_ok_WIRE_2[12], _source_ok_T_120 node _source_ok_T_121 = or(_source_ok_WIRE_2[0], _source_ok_WIRE_2[1]) node _source_ok_T_122 = or(_source_ok_T_121, _source_ok_WIRE_2[2]) node _source_ok_T_123 = or(_source_ok_T_122, _source_ok_WIRE_2[3]) node _source_ok_T_124 = or(_source_ok_T_123, _source_ok_WIRE_2[4]) node _source_ok_T_125 = or(_source_ok_T_124, _source_ok_WIRE_2[5]) node _source_ok_T_126 = or(_source_ok_T_125, _source_ok_WIRE_2[6]) node _source_ok_T_127 = or(_source_ok_T_126, _source_ok_WIRE_2[7]) node _source_ok_T_128 = or(_source_ok_T_127, _source_ok_WIRE_2[8]) node _source_ok_T_129 = or(_source_ok_T_128, _source_ok_WIRE_2[9]) node _source_ok_T_130 = or(_source_ok_T_129, _source_ok_WIRE_2[10]) node _source_ok_T_131 = or(_source_ok_T_130, _source_ok_WIRE_2[11]) node source_ok_2 = or(_source_ok_T_131, _source_ok_WIRE_2[12]) node _is_aligned_mask_T_4 = dshl(UInt<6>(0h3f), io.in.c.bits.size) node _is_aligned_mask_T_5 = bits(_is_aligned_mask_T_4, 5, 0) node is_aligned_mask_2 = not(_is_aligned_mask_T_5) node _is_aligned_T_2 = and(io.in.c.bits.address, is_aligned_mask_2) node is_aligned_2 = eq(_is_aligned_T_2, UInt<1>(0h0)) node _address_ok_T_10 = xor(io.in.c.bits.address, UInt<28>(0h8000040)) node _address_ok_T_11 = cvt(_address_ok_T_10) node _address_ok_T_12 = and(_address_ok_T_11, asSInt(UInt<17>(0h100c0))) node _address_ok_T_13 = asSInt(_address_ok_T_12) node _address_ok_T_14 = eq(_address_ok_T_13, asSInt(UInt<1>(0h0))) node _address_ok_T_15 = xor(io.in.c.bits.address, UInt<32>(0h80000040)) node _address_ok_T_16 = cvt(_address_ok_T_15) node _address_ok_T_17 = and(_address_ok_T_16, asSInt(UInt<29>(0h100000c0))) node _address_ok_T_18 = asSInt(_address_ok_T_17) node _address_ok_T_19 = eq(_address_ok_T_18, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE_1 : UInt<1>[2] connect _address_ok_WIRE_1[0], _address_ok_T_14 connect _address_ok_WIRE_1[1], _address_ok_T_19 node address_ok_1 = or(_address_ok_WIRE_1[0], _address_ok_WIRE_1[1]) node _T_1652 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _T_1653 = eq(_T_1652, UInt<1>(0h0)) node _T_1654 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1655 = cvt(_T_1654) node _T_1656 = and(_T_1655, asSInt(UInt<1>(0h0))) node _T_1657 = asSInt(_T_1656) node _T_1658 = eq(_T_1657, asSInt(UInt<1>(0h0))) node _T_1659 = or(_T_1653, _T_1658) node _uncommonBits_T_52 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_52 = bits(_uncommonBits_T_52, 1, 0) node _T_1660 = shr(io.in.c.bits.source, 2) node _T_1661 = eq(_T_1660, UInt<1>(0h0)) node _T_1662 = leq(UInt<1>(0h0), uncommonBits_52) node _T_1663 = and(_T_1661, _T_1662) node _T_1664 = leq(uncommonBits_52, UInt<2>(0h3)) node _T_1665 = and(_T_1663, _T_1664) node _T_1666 = eq(_T_1665, UInt<1>(0h0)) node _T_1667 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1668 = cvt(_T_1667) node _T_1669 = and(_T_1668, asSInt(UInt<1>(0h0))) node _T_1670 = asSInt(_T_1669) node _T_1671 = eq(_T_1670, asSInt(UInt<1>(0h0))) node _T_1672 = or(_T_1666, _T_1671) node _uncommonBits_T_53 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_53 = bits(_uncommonBits_T_53, 1, 0) node _T_1673 = shr(io.in.c.bits.source, 2) node _T_1674 = eq(_T_1673, UInt<1>(0h1)) node _T_1675 = leq(UInt<1>(0h0), uncommonBits_53) node _T_1676 = and(_T_1674, _T_1675) node _T_1677 = leq(uncommonBits_53, UInt<2>(0h3)) node _T_1678 = and(_T_1676, _T_1677) node _T_1679 = eq(_T_1678, UInt<1>(0h0)) node _T_1680 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1681 = cvt(_T_1680) node _T_1682 = and(_T_1681, asSInt(UInt<1>(0h0))) node _T_1683 = asSInt(_T_1682) node _T_1684 = eq(_T_1683, asSInt(UInt<1>(0h0))) node _T_1685 = or(_T_1679, _T_1684) node _uncommonBits_T_54 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_54 = bits(_uncommonBits_T_54, 1, 0) node _T_1686 = shr(io.in.c.bits.source, 2) node _T_1687 = eq(_T_1686, UInt<2>(0h2)) node _T_1688 = leq(UInt<1>(0h0), uncommonBits_54) node _T_1689 = and(_T_1687, _T_1688) node _T_1690 = leq(uncommonBits_54, UInt<2>(0h3)) node _T_1691 = and(_T_1689, _T_1690) node _T_1692 = eq(_T_1691, UInt<1>(0h0)) node _T_1693 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1694 = cvt(_T_1693) node _T_1695 = and(_T_1694, asSInt(UInt<1>(0h0))) node _T_1696 = asSInt(_T_1695) node _T_1697 = eq(_T_1696, asSInt(UInt<1>(0h0))) node _T_1698 = or(_T_1692, _T_1697) node _uncommonBits_T_55 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_55 = bits(_uncommonBits_T_55, 1, 0) node _T_1699 = shr(io.in.c.bits.source, 2) node _T_1700 = eq(_T_1699, UInt<2>(0h3)) node _T_1701 = leq(UInt<1>(0h0), uncommonBits_55) node _T_1702 = and(_T_1700, _T_1701) node _T_1703 = leq(uncommonBits_55, UInt<2>(0h3)) node _T_1704 = and(_T_1702, _T_1703) node _T_1705 = eq(_T_1704, UInt<1>(0h0)) node _T_1706 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1707 = cvt(_T_1706) node _T_1708 = and(_T_1707, asSInt(UInt<1>(0h0))) node _T_1709 = asSInt(_T_1708) node _T_1710 = eq(_T_1709, asSInt(UInt<1>(0h0))) node _T_1711 = or(_T_1705, _T_1710) node _T_1712 = eq(io.in.c.bits.source, UInt<6>(0h2c)) node _T_1713 = eq(_T_1712, UInt<1>(0h0)) node _T_1714 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1715 = cvt(_T_1714) node _T_1716 = and(_T_1715, asSInt(UInt<1>(0h0))) node _T_1717 = asSInt(_T_1716) node _T_1718 = eq(_T_1717, asSInt(UInt<1>(0h0))) node _T_1719 = or(_T_1713, _T_1718) node _T_1720 = eq(io.in.c.bits.source, UInt<6>(0h2e)) node _T_1721 = eq(_T_1720, UInt<1>(0h0)) node _T_1722 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1723 = cvt(_T_1722) node _T_1724 = and(_T_1723, asSInt(UInt<1>(0h0))) node _T_1725 = asSInt(_T_1724) node _T_1726 = eq(_T_1725, asSInt(UInt<1>(0h0))) node _T_1727 = or(_T_1721, _T_1726) node _T_1728 = eq(io.in.c.bits.source, UInt<6>(0h28)) node _T_1729 = eq(_T_1728, UInt<1>(0h0)) node _T_1730 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1731 = cvt(_T_1730) node _T_1732 = and(_T_1731, asSInt(UInt<1>(0h0))) node _T_1733 = asSInt(_T_1732) node _T_1734 = eq(_T_1733, asSInt(UInt<1>(0h0))) node _T_1735 = or(_T_1729, _T_1734) node _T_1736 = eq(io.in.c.bits.source, UInt<6>(0h2a)) node _T_1737 = eq(_T_1736, UInt<1>(0h0)) node _T_1738 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1739 = cvt(_T_1738) node _T_1740 = and(_T_1739, asSInt(UInt<1>(0h0))) node _T_1741 = asSInt(_T_1740) node _T_1742 = eq(_T_1741, asSInt(UInt<1>(0h0))) node _T_1743 = or(_T_1737, _T_1742) node _T_1744 = eq(io.in.c.bits.source, UInt<6>(0h24)) node _T_1745 = eq(_T_1744, UInt<1>(0h0)) node _T_1746 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1747 = cvt(_T_1746) node _T_1748 = and(_T_1747, asSInt(UInt<1>(0h0))) node _T_1749 = asSInt(_T_1748) node _T_1750 = eq(_T_1749, asSInt(UInt<1>(0h0))) node _T_1751 = or(_T_1745, _T_1750) node _T_1752 = eq(io.in.c.bits.source, UInt<6>(0h26)) node _T_1753 = eq(_T_1752, UInt<1>(0h0)) node _T_1754 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1755 = cvt(_T_1754) node _T_1756 = and(_T_1755, asSInt(UInt<1>(0h0))) node _T_1757 = asSInt(_T_1756) node _T_1758 = eq(_T_1757, asSInt(UInt<1>(0h0))) node _T_1759 = or(_T_1753, _T_1758) node _T_1760 = eq(io.in.c.bits.source, UInt<6>(0h20)) node _T_1761 = eq(_T_1760, UInt<1>(0h0)) node _T_1762 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1763 = cvt(_T_1762) node _T_1764 = and(_T_1763, asSInt(UInt<1>(0h0))) node _T_1765 = asSInt(_T_1764) node _T_1766 = eq(_T_1765, asSInt(UInt<1>(0h0))) node _T_1767 = or(_T_1761, _T_1766) node _T_1768 = eq(io.in.c.bits.source, UInt<6>(0h22)) node _T_1769 = eq(_T_1768, UInt<1>(0h0)) node _T_1770 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1771 = cvt(_T_1770) node _T_1772 = and(_T_1771, asSInt(UInt<1>(0h0))) node _T_1773 = asSInt(_T_1772) node _T_1774 = eq(_T_1773, asSInt(UInt<1>(0h0))) node _T_1775 = or(_T_1769, _T_1774) node _T_1776 = and(_T_1659, _T_1672) node _T_1777 = and(_T_1776, _T_1685) node _T_1778 = and(_T_1777, _T_1698) node _T_1779 = and(_T_1778, _T_1711) node _T_1780 = and(_T_1779, _T_1719) node _T_1781 = and(_T_1780, _T_1727) node _T_1782 = and(_T_1781, _T_1735) node _T_1783 = and(_T_1782, _T_1743) node _T_1784 = and(_T_1783, _T_1751) node _T_1785 = and(_T_1784, _T_1759) node _T_1786 = and(_T_1785, _T_1767) node _T_1787 = and(_T_1786, _T_1775) node _T_1788 = asUInt(reset) node _T_1789 = eq(_T_1788, UInt<1>(0h0)) when _T_1789 : node _T_1790 = eq(_T_1787, UInt<1>(0h0)) when _T_1790 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_131 assert(clock, _T_1787, UInt<1>(0h1), "") : assert_131 node _T_1791 = eq(io.in.c.bits.opcode, UInt<3>(0h4)) when _T_1791 : node _T_1792 = asUInt(reset) node _T_1793 = eq(_T_1792, UInt<1>(0h0)) when _T_1793 : node _T_1794 = eq(address_ok_1, UInt<1>(0h0)) when _T_1794 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_132 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_132 node _T_1795 = asUInt(reset) node _T_1796 = eq(_T_1795, UInt<1>(0h0)) when _T_1796 : node _T_1797 = eq(source_ok_2, UInt<1>(0h0)) when _T_1797 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_133 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_133 node _T_1798 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_1799 = asUInt(reset) node _T_1800 = eq(_T_1799, UInt<1>(0h0)) when _T_1800 : node _T_1801 = eq(_T_1798, UInt<1>(0h0)) when _T_1801 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_134 assert(clock, _T_1798, UInt<1>(0h1), "") : assert_134 node _T_1802 = asUInt(reset) node _T_1803 = eq(_T_1802, UInt<1>(0h0)) when _T_1803 : node _T_1804 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1804 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_135 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_135 node _T_1805 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1806 = asUInt(reset) node _T_1807 = eq(_T_1806, UInt<1>(0h0)) when _T_1807 : node _T_1808 = eq(_T_1805, UInt<1>(0h0)) when _T_1808 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_136 assert(clock, _T_1805, UInt<1>(0h1), "") : assert_136 node _T_1809 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1810 = asUInt(reset) node _T_1811 = eq(_T_1810, UInt<1>(0h0)) when _T_1811 : node _T_1812 = eq(_T_1809, UInt<1>(0h0)) when _T_1812 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_137 assert(clock, _T_1809, UInt<1>(0h1), "") : assert_137 node _T_1813 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) when _T_1813 : node _T_1814 = asUInt(reset) node _T_1815 = eq(_T_1814, UInt<1>(0h0)) when _T_1815 : node _T_1816 = eq(address_ok_1, UInt<1>(0h0)) when _T_1816 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_138 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_138 node _T_1817 = asUInt(reset) node _T_1818 = eq(_T_1817, UInt<1>(0h0)) when _T_1818 : node _T_1819 = eq(source_ok_2, UInt<1>(0h0)) when _T_1819 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_139 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_139 node _T_1820 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_1821 = asUInt(reset) node _T_1822 = eq(_T_1821, UInt<1>(0h0)) when _T_1822 : node _T_1823 = eq(_T_1820, UInt<1>(0h0)) when _T_1823 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_140 assert(clock, _T_1820, UInt<1>(0h1), "") : assert_140 node _T_1824 = asUInt(reset) node _T_1825 = eq(_T_1824, UInt<1>(0h0)) when _T_1825 : node _T_1826 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1826 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_141 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_141 node _T_1827 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1828 = asUInt(reset) node _T_1829 = eq(_T_1828, UInt<1>(0h0)) when _T_1829 : node _T_1830 = eq(_T_1827, UInt<1>(0h0)) when _T_1830 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_142 assert(clock, _T_1827, UInt<1>(0h1), "") : assert_142 node _T_1831 = eq(io.in.c.bits.opcode, UInt<3>(0h6)) when _T_1831 : node _T_1832 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1833 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1834 = and(_T_1832, _T_1833) node _T_1835 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _uncommonBits_T_56 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_56 = bits(_uncommonBits_T_56, 1, 0) node _T_1836 = shr(io.in.c.bits.source, 2) node _T_1837 = eq(_T_1836, UInt<1>(0h0)) node _T_1838 = leq(UInt<1>(0h0), uncommonBits_56) node _T_1839 = and(_T_1837, _T_1838) node _T_1840 = leq(uncommonBits_56, UInt<2>(0h3)) node _T_1841 = and(_T_1839, _T_1840) node _uncommonBits_T_57 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_57 = bits(_uncommonBits_T_57, 1, 0) node _T_1842 = shr(io.in.c.bits.source, 2) node _T_1843 = eq(_T_1842, UInt<1>(0h1)) node _T_1844 = leq(UInt<1>(0h0), uncommonBits_57) node _T_1845 = and(_T_1843, _T_1844) node _T_1846 = leq(uncommonBits_57, UInt<2>(0h3)) node _T_1847 = and(_T_1845, _T_1846) node _uncommonBits_T_58 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_58 = bits(_uncommonBits_T_58, 1, 0) node _T_1848 = shr(io.in.c.bits.source, 2) node _T_1849 = eq(_T_1848, UInt<2>(0h2)) node _T_1850 = leq(UInt<1>(0h0), uncommonBits_58) node _T_1851 = and(_T_1849, _T_1850) node _T_1852 = leq(uncommonBits_58, UInt<2>(0h3)) node _T_1853 = and(_T_1851, _T_1852) node _uncommonBits_T_59 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_59 = bits(_uncommonBits_T_59, 1, 0) node _T_1854 = shr(io.in.c.bits.source, 2) node _T_1855 = eq(_T_1854, UInt<2>(0h3)) node _T_1856 = leq(UInt<1>(0h0), uncommonBits_59) node _T_1857 = and(_T_1855, _T_1856) node _T_1858 = leq(uncommonBits_59, UInt<2>(0h3)) node _T_1859 = and(_T_1857, _T_1858) node _T_1860 = eq(io.in.c.bits.source, UInt<6>(0h2c)) node _T_1861 = eq(io.in.c.bits.source, UInt<6>(0h2e)) node _T_1862 = eq(io.in.c.bits.source, UInt<6>(0h28)) node _T_1863 = eq(io.in.c.bits.source, UInt<6>(0h2a)) node _T_1864 = eq(io.in.c.bits.source, UInt<6>(0h24)) node _T_1865 = eq(io.in.c.bits.source, UInt<6>(0h26)) node _T_1866 = eq(io.in.c.bits.source, UInt<6>(0h20)) node _T_1867 = eq(io.in.c.bits.source, UInt<6>(0h22)) node _T_1868 = or(_T_1835, _T_1841) node _T_1869 = or(_T_1868, _T_1847) node _T_1870 = or(_T_1869, _T_1853) node _T_1871 = or(_T_1870, _T_1859) node _T_1872 = or(_T_1871, _T_1860) node _T_1873 = or(_T_1872, _T_1861) node _T_1874 = or(_T_1873, _T_1862) node _T_1875 = or(_T_1874, _T_1863) node _T_1876 = or(_T_1875, _T_1864) node _T_1877 = or(_T_1876, _T_1865) node _T_1878 = or(_T_1877, _T_1866) node _T_1879 = or(_T_1878, _T_1867) node _T_1880 = and(_T_1834, _T_1879) node _T_1881 = or(UInt<1>(0h0), _T_1880) node _T_1882 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1883 = or(UInt<1>(0h0), _T_1882) node _T_1884 = xor(io.in.c.bits.address, UInt<28>(0h8000040)) node _T_1885 = cvt(_T_1884) node _T_1886 = and(_T_1885, asSInt(UInt<17>(0h100c0))) node _T_1887 = asSInt(_T_1886) node _T_1888 = eq(_T_1887, asSInt(UInt<1>(0h0))) node _T_1889 = xor(io.in.c.bits.address, UInt<32>(0h80000040)) node _T_1890 = cvt(_T_1889) node _T_1891 = and(_T_1890, asSInt(UInt<29>(0h100000c0))) node _T_1892 = asSInt(_T_1891) node _T_1893 = eq(_T_1892, asSInt(UInt<1>(0h0))) node _T_1894 = or(_T_1888, _T_1893) node _T_1895 = and(_T_1883, _T_1894) node _T_1896 = or(UInt<1>(0h0), _T_1895) node _T_1897 = and(_T_1881, _T_1896) node _T_1898 = asUInt(reset) node _T_1899 = eq(_T_1898, UInt<1>(0h0)) when _T_1899 : node _T_1900 = eq(_T_1897, UInt<1>(0h0)) when _T_1900 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_143 assert(clock, _T_1897, UInt<1>(0h1), "") : assert_143 node _T_1901 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _uncommonBits_T_60 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_60 = bits(_uncommonBits_T_60, 1, 0) node _T_1902 = shr(io.in.c.bits.source, 2) node _T_1903 = eq(_T_1902, UInt<1>(0h0)) node _T_1904 = leq(UInt<1>(0h0), uncommonBits_60) node _T_1905 = and(_T_1903, _T_1904) node _T_1906 = leq(uncommonBits_60, UInt<2>(0h3)) node _T_1907 = and(_T_1905, _T_1906) node _uncommonBits_T_61 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_61 = bits(_uncommonBits_T_61, 1, 0) node _T_1908 = shr(io.in.c.bits.source, 2) node _T_1909 = eq(_T_1908, UInt<1>(0h1)) node _T_1910 = leq(UInt<1>(0h0), uncommonBits_61) node _T_1911 = and(_T_1909, _T_1910) node _T_1912 = leq(uncommonBits_61, UInt<2>(0h3)) node _T_1913 = and(_T_1911, _T_1912) node _uncommonBits_T_62 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_62 = bits(_uncommonBits_T_62, 1, 0) node _T_1914 = shr(io.in.c.bits.source, 2) node _T_1915 = eq(_T_1914, UInt<2>(0h2)) node _T_1916 = leq(UInt<1>(0h0), uncommonBits_62) node _T_1917 = and(_T_1915, _T_1916) node _T_1918 = leq(uncommonBits_62, UInt<2>(0h3)) node _T_1919 = and(_T_1917, _T_1918) node _uncommonBits_T_63 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_63 = bits(_uncommonBits_T_63, 1, 0) node _T_1920 = shr(io.in.c.bits.source, 2) node _T_1921 = eq(_T_1920, UInt<2>(0h3)) node _T_1922 = leq(UInt<1>(0h0), uncommonBits_63) node _T_1923 = and(_T_1921, _T_1922) node _T_1924 = leq(uncommonBits_63, UInt<2>(0h3)) node _T_1925 = and(_T_1923, _T_1924) node _T_1926 = eq(io.in.c.bits.source, UInt<6>(0h2c)) node _T_1927 = eq(io.in.c.bits.source, UInt<6>(0h2e)) node _T_1928 = eq(io.in.c.bits.source, UInt<6>(0h28)) node _T_1929 = eq(io.in.c.bits.source, UInt<6>(0h2a)) node _T_1930 = eq(io.in.c.bits.source, UInt<6>(0h24)) node _T_1931 = eq(io.in.c.bits.source, UInt<6>(0h26)) node _T_1932 = eq(io.in.c.bits.source, UInt<6>(0h20)) node _T_1933 = eq(io.in.c.bits.source, UInt<6>(0h22)) wire _WIRE_6 : UInt<1>[13] connect _WIRE_6[0], _T_1901 connect _WIRE_6[1], _T_1907 connect _WIRE_6[2], _T_1913 connect _WIRE_6[3], _T_1919 connect _WIRE_6[4], _T_1925 connect _WIRE_6[5], _T_1926 connect _WIRE_6[6], _T_1927 connect _WIRE_6[7], _T_1928 connect _WIRE_6[8], _T_1929 connect _WIRE_6[9], _T_1930 connect _WIRE_6[10], _T_1931 connect _WIRE_6[11], _T_1932 connect _WIRE_6[12], _T_1933 node _T_1934 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1935 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1936 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1937 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1938 = mux(_WIRE_6[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_1939 = mux(_WIRE_6[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1940 = mux(_WIRE_6[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_1941 = mux(_WIRE_6[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_1942 = mux(_WIRE_6[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_1943 = mux(_WIRE_6[5], _T_1934, UInt<1>(0h0)) node _T_1944 = mux(_WIRE_6[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_1945 = mux(_WIRE_6[7], _T_1935, UInt<1>(0h0)) node _T_1946 = mux(_WIRE_6[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_1947 = mux(_WIRE_6[9], _T_1936, UInt<1>(0h0)) node _T_1948 = mux(_WIRE_6[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_1949 = mux(_WIRE_6[11], _T_1937, UInt<1>(0h0)) node _T_1950 = mux(_WIRE_6[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_1951 = or(_T_1938, _T_1939) node _T_1952 = or(_T_1951, _T_1940) node _T_1953 = or(_T_1952, _T_1941) node _T_1954 = or(_T_1953, _T_1942) node _T_1955 = or(_T_1954, _T_1943) node _T_1956 = or(_T_1955, _T_1944) node _T_1957 = or(_T_1956, _T_1945) node _T_1958 = or(_T_1957, _T_1946) node _T_1959 = or(_T_1958, _T_1947) node _T_1960 = or(_T_1959, _T_1948) node _T_1961 = or(_T_1960, _T_1949) node _T_1962 = or(_T_1961, _T_1950) wire _WIRE_7 : UInt<1> connect _WIRE_7, _T_1962 node _T_1963 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1964 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1965 = and(_T_1963, _T_1964) node _T_1966 = or(UInt<1>(0h0), _T_1965) node _T_1967 = xor(io.in.c.bits.address, UInt<28>(0h8000040)) node _T_1968 = cvt(_T_1967) node _T_1969 = and(_T_1968, asSInt(UInt<17>(0h100c0))) node _T_1970 = asSInt(_T_1969) node _T_1971 = eq(_T_1970, asSInt(UInt<1>(0h0))) node _T_1972 = xor(io.in.c.bits.address, UInt<32>(0h80000040)) node _T_1973 = cvt(_T_1972) node _T_1974 = and(_T_1973, asSInt(UInt<29>(0h100000c0))) node _T_1975 = asSInt(_T_1974) node _T_1976 = eq(_T_1975, asSInt(UInt<1>(0h0))) node _T_1977 = or(_T_1971, _T_1976) node _T_1978 = and(_T_1966, _T_1977) node _T_1979 = or(UInt<1>(0h0), _T_1978) node _T_1980 = and(_WIRE_7, _T_1979) node _T_1981 = asUInt(reset) node _T_1982 = eq(_T_1981, UInt<1>(0h0)) when _T_1982 : node _T_1983 = eq(_T_1980, UInt<1>(0h0)) when _T_1983 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_144 assert(clock, _T_1980, UInt<1>(0h1), "") : assert_144 node _T_1984 = asUInt(reset) node _T_1985 = eq(_T_1984, UInt<1>(0h0)) when _T_1985 : node _T_1986 = eq(source_ok_2, UInt<1>(0h0)) when _T_1986 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_145 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_145 node _T_1987 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_1988 = asUInt(reset) node _T_1989 = eq(_T_1988, UInt<1>(0h0)) when _T_1989 : node _T_1990 = eq(_T_1987, UInt<1>(0h0)) when _T_1990 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_146 assert(clock, _T_1987, UInt<1>(0h1), "") : assert_146 node _T_1991 = asUInt(reset) node _T_1992 = eq(_T_1991, UInt<1>(0h0)) when _T_1992 : node _T_1993 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1993 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_147 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_147 node _T_1994 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1995 = asUInt(reset) node _T_1996 = eq(_T_1995, UInt<1>(0h0)) when _T_1996 : node _T_1997 = eq(_T_1994, UInt<1>(0h0)) when _T_1997 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_148 assert(clock, _T_1994, UInt<1>(0h1), "") : assert_148 node _T_1998 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1999 = asUInt(reset) node _T_2000 = eq(_T_1999, UInt<1>(0h0)) when _T_2000 : node _T_2001 = eq(_T_1998, UInt<1>(0h0)) when _T_2001 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_149 assert(clock, _T_1998, UInt<1>(0h1), "") : assert_149 node _T_2002 = eq(io.in.c.bits.opcode, UInt<3>(0h7)) when _T_2002 : node _T_2003 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2004 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2005 = and(_T_2003, _T_2004) node _T_2006 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _uncommonBits_T_64 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_64 = bits(_uncommonBits_T_64, 1, 0) node _T_2007 = shr(io.in.c.bits.source, 2) node _T_2008 = eq(_T_2007, UInt<1>(0h0)) node _T_2009 = leq(UInt<1>(0h0), uncommonBits_64) node _T_2010 = and(_T_2008, _T_2009) node _T_2011 = leq(uncommonBits_64, UInt<2>(0h3)) node _T_2012 = and(_T_2010, _T_2011) node _uncommonBits_T_65 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_65 = bits(_uncommonBits_T_65, 1, 0) node _T_2013 = shr(io.in.c.bits.source, 2) node _T_2014 = eq(_T_2013, UInt<1>(0h1)) node _T_2015 = leq(UInt<1>(0h0), uncommonBits_65) node _T_2016 = and(_T_2014, _T_2015) node _T_2017 = leq(uncommonBits_65, UInt<2>(0h3)) node _T_2018 = and(_T_2016, _T_2017) node _uncommonBits_T_66 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_66 = bits(_uncommonBits_T_66, 1, 0) node _T_2019 = shr(io.in.c.bits.source, 2) node _T_2020 = eq(_T_2019, UInt<2>(0h2)) node _T_2021 = leq(UInt<1>(0h0), uncommonBits_66) node _T_2022 = and(_T_2020, _T_2021) node _T_2023 = leq(uncommonBits_66, UInt<2>(0h3)) node _T_2024 = and(_T_2022, _T_2023) node _uncommonBits_T_67 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_67 = bits(_uncommonBits_T_67, 1, 0) node _T_2025 = shr(io.in.c.bits.source, 2) node _T_2026 = eq(_T_2025, UInt<2>(0h3)) node _T_2027 = leq(UInt<1>(0h0), uncommonBits_67) node _T_2028 = and(_T_2026, _T_2027) node _T_2029 = leq(uncommonBits_67, UInt<2>(0h3)) node _T_2030 = and(_T_2028, _T_2029) node _T_2031 = eq(io.in.c.bits.source, UInt<6>(0h2c)) node _T_2032 = eq(io.in.c.bits.source, UInt<6>(0h2e)) node _T_2033 = eq(io.in.c.bits.source, UInt<6>(0h28)) node _T_2034 = eq(io.in.c.bits.source, UInt<6>(0h2a)) node _T_2035 = eq(io.in.c.bits.source, UInt<6>(0h24)) node _T_2036 = eq(io.in.c.bits.source, UInt<6>(0h26)) node _T_2037 = eq(io.in.c.bits.source, UInt<6>(0h20)) node _T_2038 = eq(io.in.c.bits.source, UInt<6>(0h22)) node _T_2039 = or(_T_2006, _T_2012) node _T_2040 = or(_T_2039, _T_2018) node _T_2041 = or(_T_2040, _T_2024) node _T_2042 = or(_T_2041, _T_2030) node _T_2043 = or(_T_2042, _T_2031) node _T_2044 = or(_T_2043, _T_2032) node _T_2045 = or(_T_2044, _T_2033) node _T_2046 = or(_T_2045, _T_2034) node _T_2047 = or(_T_2046, _T_2035) node _T_2048 = or(_T_2047, _T_2036) node _T_2049 = or(_T_2048, _T_2037) node _T_2050 = or(_T_2049, _T_2038) node _T_2051 = and(_T_2005, _T_2050) node _T_2052 = or(UInt<1>(0h0), _T_2051) node _T_2053 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2054 = or(UInt<1>(0h0), _T_2053) node _T_2055 = xor(io.in.c.bits.address, UInt<28>(0h8000040)) node _T_2056 = cvt(_T_2055) node _T_2057 = and(_T_2056, asSInt(UInt<17>(0h100c0))) node _T_2058 = asSInt(_T_2057) node _T_2059 = eq(_T_2058, asSInt(UInt<1>(0h0))) node _T_2060 = xor(io.in.c.bits.address, UInt<32>(0h80000040)) node _T_2061 = cvt(_T_2060) node _T_2062 = and(_T_2061, asSInt(UInt<29>(0h100000c0))) node _T_2063 = asSInt(_T_2062) node _T_2064 = eq(_T_2063, asSInt(UInt<1>(0h0))) node _T_2065 = or(_T_2059, _T_2064) node _T_2066 = and(_T_2054, _T_2065) node _T_2067 = or(UInt<1>(0h0), _T_2066) node _T_2068 = and(_T_2052, _T_2067) node _T_2069 = asUInt(reset) node _T_2070 = eq(_T_2069, UInt<1>(0h0)) when _T_2070 : node _T_2071 = eq(_T_2068, UInt<1>(0h0)) when _T_2071 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_150 assert(clock, _T_2068, UInt<1>(0h1), "") : assert_150 node _T_2072 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _uncommonBits_T_68 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_68 = bits(_uncommonBits_T_68, 1, 0) node _T_2073 = shr(io.in.c.bits.source, 2) node _T_2074 = eq(_T_2073, UInt<1>(0h0)) node _T_2075 = leq(UInt<1>(0h0), uncommonBits_68) node _T_2076 = and(_T_2074, _T_2075) node _T_2077 = leq(uncommonBits_68, UInt<2>(0h3)) node _T_2078 = and(_T_2076, _T_2077) node _uncommonBits_T_69 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_69 = bits(_uncommonBits_T_69, 1, 0) node _T_2079 = shr(io.in.c.bits.source, 2) node _T_2080 = eq(_T_2079, UInt<1>(0h1)) node _T_2081 = leq(UInt<1>(0h0), uncommonBits_69) node _T_2082 = and(_T_2080, _T_2081) node _T_2083 = leq(uncommonBits_69, UInt<2>(0h3)) node _T_2084 = and(_T_2082, _T_2083) node _uncommonBits_T_70 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_70 = bits(_uncommonBits_T_70, 1, 0) node _T_2085 = shr(io.in.c.bits.source, 2) node _T_2086 = eq(_T_2085, UInt<2>(0h2)) node _T_2087 = leq(UInt<1>(0h0), uncommonBits_70) node _T_2088 = and(_T_2086, _T_2087) node _T_2089 = leq(uncommonBits_70, UInt<2>(0h3)) node _T_2090 = and(_T_2088, _T_2089) node _uncommonBits_T_71 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_71 = bits(_uncommonBits_T_71, 1, 0) node _T_2091 = shr(io.in.c.bits.source, 2) node _T_2092 = eq(_T_2091, UInt<2>(0h3)) node _T_2093 = leq(UInt<1>(0h0), uncommonBits_71) node _T_2094 = and(_T_2092, _T_2093) node _T_2095 = leq(uncommonBits_71, UInt<2>(0h3)) node _T_2096 = and(_T_2094, _T_2095) node _T_2097 = eq(io.in.c.bits.source, UInt<6>(0h2c)) node _T_2098 = eq(io.in.c.bits.source, UInt<6>(0h2e)) node _T_2099 = eq(io.in.c.bits.source, UInt<6>(0h28)) node _T_2100 = eq(io.in.c.bits.source, UInt<6>(0h2a)) node _T_2101 = eq(io.in.c.bits.source, UInt<6>(0h24)) node _T_2102 = eq(io.in.c.bits.source, UInt<6>(0h26)) node _T_2103 = eq(io.in.c.bits.source, UInt<6>(0h20)) node _T_2104 = eq(io.in.c.bits.source, UInt<6>(0h22)) wire _WIRE_8 : UInt<1>[13] connect _WIRE_8[0], _T_2072 connect _WIRE_8[1], _T_2078 connect _WIRE_8[2], _T_2084 connect _WIRE_8[3], _T_2090 connect _WIRE_8[4], _T_2096 connect _WIRE_8[5], _T_2097 connect _WIRE_8[6], _T_2098 connect _WIRE_8[7], _T_2099 connect _WIRE_8[8], _T_2100 connect _WIRE_8[9], _T_2101 connect _WIRE_8[10], _T_2102 connect _WIRE_8[11], _T_2103 connect _WIRE_8[12], _T_2104 node _T_2105 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2106 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2107 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2108 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2109 = mux(_WIRE_8[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_2110 = mux(_WIRE_8[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_2111 = mux(_WIRE_8[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_2112 = mux(_WIRE_8[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_2113 = mux(_WIRE_8[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_2114 = mux(_WIRE_8[5], _T_2105, UInt<1>(0h0)) node _T_2115 = mux(_WIRE_8[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_2116 = mux(_WIRE_8[7], _T_2106, UInt<1>(0h0)) node _T_2117 = mux(_WIRE_8[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_2118 = mux(_WIRE_8[9], _T_2107, UInt<1>(0h0)) node _T_2119 = mux(_WIRE_8[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_2120 = mux(_WIRE_8[11], _T_2108, UInt<1>(0h0)) node _T_2121 = mux(_WIRE_8[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_2122 = or(_T_2109, _T_2110) node _T_2123 = or(_T_2122, _T_2111) node _T_2124 = or(_T_2123, _T_2112) node _T_2125 = or(_T_2124, _T_2113) node _T_2126 = or(_T_2125, _T_2114) node _T_2127 = or(_T_2126, _T_2115) node _T_2128 = or(_T_2127, _T_2116) node _T_2129 = or(_T_2128, _T_2117) node _T_2130 = or(_T_2129, _T_2118) node _T_2131 = or(_T_2130, _T_2119) node _T_2132 = or(_T_2131, _T_2120) node _T_2133 = or(_T_2132, _T_2121) wire _WIRE_9 : UInt<1> connect _WIRE_9, _T_2133 node _T_2134 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2135 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2136 = and(_T_2134, _T_2135) node _T_2137 = or(UInt<1>(0h0), _T_2136) node _T_2138 = xor(io.in.c.bits.address, UInt<28>(0h8000040)) node _T_2139 = cvt(_T_2138) node _T_2140 = and(_T_2139, asSInt(UInt<17>(0h100c0))) node _T_2141 = asSInt(_T_2140) node _T_2142 = eq(_T_2141, asSInt(UInt<1>(0h0))) node _T_2143 = xor(io.in.c.bits.address, UInt<32>(0h80000040)) node _T_2144 = cvt(_T_2143) node _T_2145 = and(_T_2144, asSInt(UInt<29>(0h100000c0))) node _T_2146 = asSInt(_T_2145) node _T_2147 = eq(_T_2146, asSInt(UInt<1>(0h0))) node _T_2148 = or(_T_2142, _T_2147) node _T_2149 = and(_T_2137, _T_2148) node _T_2150 = or(UInt<1>(0h0), _T_2149) node _T_2151 = and(_WIRE_9, _T_2150) node _T_2152 = asUInt(reset) node _T_2153 = eq(_T_2152, UInt<1>(0h0)) when _T_2153 : node _T_2154 = eq(_T_2151, UInt<1>(0h0)) when _T_2154 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_151 assert(clock, _T_2151, UInt<1>(0h1), "") : assert_151 node _T_2155 = asUInt(reset) node _T_2156 = eq(_T_2155, UInt<1>(0h0)) when _T_2156 : node _T_2157 = eq(source_ok_2, UInt<1>(0h0)) when _T_2157 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_152 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_152 node _T_2158 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_2159 = asUInt(reset) node _T_2160 = eq(_T_2159, UInt<1>(0h0)) when _T_2160 : node _T_2161 = eq(_T_2158, UInt<1>(0h0)) when _T_2161 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_153 assert(clock, _T_2158, UInt<1>(0h1), "") : assert_153 node _T_2162 = asUInt(reset) node _T_2163 = eq(_T_2162, UInt<1>(0h0)) when _T_2163 : node _T_2164 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2164 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_154 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_154 node _T_2165 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2166 = asUInt(reset) node _T_2167 = eq(_T_2166, UInt<1>(0h0)) when _T_2167 : node _T_2168 = eq(_T_2165, UInt<1>(0h0)) when _T_2168 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_155 assert(clock, _T_2165, UInt<1>(0h1), "") : assert_155 node _T_2169 = eq(io.in.c.bits.opcode, UInt<1>(0h0)) when _T_2169 : node _T_2170 = asUInt(reset) node _T_2171 = eq(_T_2170, UInt<1>(0h0)) when _T_2171 : node _T_2172 = eq(address_ok_1, UInt<1>(0h0)) when _T_2172 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_156 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_156 node _T_2173 = asUInt(reset) node _T_2174 = eq(_T_2173, UInt<1>(0h0)) when _T_2174 : node _T_2175 = eq(source_ok_2, UInt<1>(0h0)) when _T_2175 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_157 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_157 node _T_2176 = asUInt(reset) node _T_2177 = eq(_T_2176, UInt<1>(0h0)) when _T_2177 : node _T_2178 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2178 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_158 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_158 node _T_2179 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2180 = asUInt(reset) node _T_2181 = eq(_T_2180, UInt<1>(0h0)) when _T_2181 : node _T_2182 = eq(_T_2179, UInt<1>(0h0)) when _T_2182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_159 assert(clock, _T_2179, UInt<1>(0h1), "") : assert_159 node _T_2183 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2184 = asUInt(reset) node _T_2185 = eq(_T_2184, UInt<1>(0h0)) when _T_2185 : node _T_2186 = eq(_T_2183, UInt<1>(0h0)) when _T_2186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_160 assert(clock, _T_2183, UInt<1>(0h1), "") : assert_160 node _T_2187 = eq(io.in.c.bits.opcode, UInt<1>(0h1)) when _T_2187 : node _T_2188 = asUInt(reset) node _T_2189 = eq(_T_2188, UInt<1>(0h0)) when _T_2189 : node _T_2190 = eq(address_ok_1, UInt<1>(0h0)) when _T_2190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_161 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_161 node _T_2191 = asUInt(reset) node _T_2192 = eq(_T_2191, UInt<1>(0h0)) when _T_2192 : node _T_2193 = eq(source_ok_2, UInt<1>(0h0)) when _T_2193 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_162 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_162 node _T_2194 = asUInt(reset) node _T_2195 = eq(_T_2194, UInt<1>(0h0)) when _T_2195 : node _T_2196 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2196 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_163 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_163 node _T_2197 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2198 = asUInt(reset) node _T_2199 = eq(_T_2198, UInt<1>(0h0)) when _T_2199 : node _T_2200 = eq(_T_2197, UInt<1>(0h0)) when _T_2200 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_164 assert(clock, _T_2197, UInt<1>(0h1), "") : assert_164 node _T_2201 = eq(io.in.c.bits.opcode, UInt<2>(0h2)) when _T_2201 : node _T_2202 = asUInt(reset) node _T_2203 = eq(_T_2202, UInt<1>(0h0)) when _T_2203 : node _T_2204 = eq(address_ok_1, UInt<1>(0h0)) when _T_2204 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_165 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_165 node _T_2205 = asUInt(reset) node _T_2206 = eq(_T_2205, UInt<1>(0h0)) when _T_2206 : node _T_2207 = eq(source_ok_2, UInt<1>(0h0)) when _T_2207 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_166 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_166 node _T_2208 = asUInt(reset) node _T_2209 = eq(_T_2208, UInt<1>(0h0)) when _T_2209 : node _T_2210 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2210 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_167 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_167 node _T_2211 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2212 = asUInt(reset) node _T_2213 = eq(_T_2212, UInt<1>(0h0)) when _T_2213 : node _T_2214 = eq(_T_2211, UInt<1>(0h0)) when _T_2214 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_168 assert(clock, _T_2211, UInt<1>(0h1), "") : assert_168 node _T_2215 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2216 = asUInt(reset) node _T_2217 = eq(_T_2216, UInt<1>(0h0)) when _T_2217 : node _T_2218 = eq(_T_2215, UInt<1>(0h0)) when _T_2218 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_169 assert(clock, _T_2215, UInt<1>(0h1), "") : assert_169 when io.in.e.valid : node sink_ok_1 = lt(io.in.e.bits.sink, UInt<3>(0h7)) node _T_2219 = asUInt(reset) node _T_2220 = eq(_T_2219, UInt<1>(0h0)) when _T_2220 : node _T_2221 = eq(sink_ok_1, UInt<1>(0h0)) when _T_2221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channels carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_170 assert(clock, sink_ok_1, UInt<1>(0h1), "") : assert_170 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_2222 = eq(a_first, UInt<1>(0h0)) node _T_2223 = and(io.in.a.valid, _T_2222) when _T_2223 : node _T_2224 = eq(io.in.a.bits.opcode, opcode) node _T_2225 = asUInt(reset) node _T_2226 = eq(_T_2225, UInt<1>(0h0)) when _T_2226 : node _T_2227 = eq(_T_2224, UInt<1>(0h0)) when _T_2227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_171 assert(clock, _T_2224, UInt<1>(0h1), "") : assert_171 node _T_2228 = eq(io.in.a.bits.param, param) node _T_2229 = asUInt(reset) node _T_2230 = eq(_T_2229, UInt<1>(0h0)) when _T_2230 : node _T_2231 = eq(_T_2228, UInt<1>(0h0)) when _T_2231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_172 assert(clock, _T_2228, UInt<1>(0h1), "") : assert_172 node _T_2232 = eq(io.in.a.bits.size, size) node _T_2233 = asUInt(reset) node _T_2234 = eq(_T_2233, UInt<1>(0h0)) when _T_2234 : node _T_2235 = eq(_T_2232, UInt<1>(0h0)) when _T_2235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_173 assert(clock, _T_2232, UInt<1>(0h1), "") : assert_173 node _T_2236 = eq(io.in.a.bits.source, source) node _T_2237 = asUInt(reset) node _T_2238 = eq(_T_2237, UInt<1>(0h0)) when _T_2238 : node _T_2239 = eq(_T_2236, UInt<1>(0h0)) when _T_2239 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_174 assert(clock, _T_2236, UInt<1>(0h1), "") : assert_174 node _T_2240 = eq(io.in.a.bits.address, address) node _T_2241 = asUInt(reset) node _T_2242 = eq(_T_2241, UInt<1>(0h0)) when _T_2242 : node _T_2243 = eq(_T_2240, UInt<1>(0h0)) when _T_2243 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_175 assert(clock, _T_2240, UInt<1>(0h1), "") : assert_175 node _T_2244 = and(io.in.a.ready, io.in.a.valid) node _T_2245 = and(_T_2244, a_first) when _T_2245 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_2246 = eq(d_first, UInt<1>(0h0)) node _T_2247 = and(io.in.d.valid, _T_2246) when _T_2247 : node _T_2248 = eq(io.in.d.bits.opcode, opcode_1) node _T_2249 = asUInt(reset) node _T_2250 = eq(_T_2249, UInt<1>(0h0)) when _T_2250 : node _T_2251 = eq(_T_2248, UInt<1>(0h0)) when _T_2251 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_176 assert(clock, _T_2248, UInt<1>(0h1), "") : assert_176 node _T_2252 = eq(io.in.d.bits.param, param_1) node _T_2253 = asUInt(reset) node _T_2254 = eq(_T_2253, UInt<1>(0h0)) when _T_2254 : node _T_2255 = eq(_T_2252, UInt<1>(0h0)) when _T_2255 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_177 assert(clock, _T_2252, UInt<1>(0h1), "") : assert_177 node _T_2256 = eq(io.in.d.bits.size, size_1) node _T_2257 = asUInt(reset) node _T_2258 = eq(_T_2257, UInt<1>(0h0)) when _T_2258 : node _T_2259 = eq(_T_2256, UInt<1>(0h0)) when _T_2259 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_178 assert(clock, _T_2256, UInt<1>(0h1), "") : assert_178 node _T_2260 = eq(io.in.d.bits.source, source_1) node _T_2261 = asUInt(reset) node _T_2262 = eq(_T_2261, UInt<1>(0h0)) when _T_2262 : node _T_2263 = eq(_T_2260, UInt<1>(0h0)) when _T_2263 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_179 assert(clock, _T_2260, UInt<1>(0h1), "") : assert_179 node _T_2264 = eq(io.in.d.bits.sink, sink) node _T_2265 = asUInt(reset) node _T_2266 = eq(_T_2265, UInt<1>(0h0)) when _T_2266 : node _T_2267 = eq(_T_2264, UInt<1>(0h0)) when _T_2267 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_180 assert(clock, _T_2264, UInt<1>(0h1), "") : assert_180 node _T_2268 = eq(io.in.d.bits.denied, denied) node _T_2269 = asUInt(reset) node _T_2270 = eq(_T_2269, UInt<1>(0h0)) when _T_2270 : node _T_2271 = eq(_T_2268, UInt<1>(0h0)) when _T_2271 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_181 assert(clock, _T_2268, UInt<1>(0h1), "") : assert_181 node _T_2272 = and(io.in.d.ready, io.in.d.valid) node _T_2273 = and(_T_2272, d_first) when _T_2273 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied node _b_first_T = and(io.in.b.ready, io.in.b.valid) node _b_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.b.bits.size) node _b_first_beats1_decode_T_1 = bits(_b_first_beats1_decode_T, 5, 0) node _b_first_beats1_decode_T_2 = not(_b_first_beats1_decode_T_1) node b_first_beats1_decode = shr(_b_first_beats1_decode_T_2, 3) node _b_first_beats1_opdata_T = bits(io.in.b.bits.opcode, 2, 2) node b_first_beats1_opdata = eq(_b_first_beats1_opdata_T, UInt<1>(0h0)) node b_first_beats1 = mux(UInt<1>(0h0), b_first_beats1_decode, UInt<1>(0h0)) regreset b_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _b_first_counter1_T = sub(b_first_counter, UInt<1>(0h1)) node b_first_counter1 = tail(_b_first_counter1_T, 1) node b_first = eq(b_first_counter, UInt<1>(0h0)) node _b_first_last_T = eq(b_first_counter, UInt<1>(0h1)) node _b_first_last_T_1 = eq(b_first_beats1, UInt<1>(0h0)) node b_first_last = or(_b_first_last_T, _b_first_last_T_1) node b_first_done = and(b_first_last, _b_first_T) node _b_first_count_T = not(b_first_counter1) node b_first_count = and(b_first_beats1, _b_first_count_T) when _b_first_T : node _b_first_counter_T = mux(b_first, b_first_beats1, b_first_counter1) connect b_first_counter, _b_first_counter_T reg opcode_2 : UInt, clock reg param_2 : UInt, clock reg size_2 : UInt, clock reg source_2 : UInt, clock reg address_1 : UInt, clock node _T_2274 = eq(b_first, UInt<1>(0h0)) node _T_2275 = and(io.in.b.valid, _T_2274) when _T_2275 : node _T_2276 = eq(io.in.b.bits.opcode, opcode_2) node _T_2277 = asUInt(reset) node _T_2278 = eq(_T_2277, UInt<1>(0h0)) when _T_2278 : node _T_2279 = eq(_T_2276, UInt<1>(0h0)) when _T_2279 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_182 assert(clock, _T_2276, UInt<1>(0h1), "") : assert_182 node _T_2280 = eq(io.in.b.bits.param, param_2) node _T_2281 = asUInt(reset) node _T_2282 = eq(_T_2281, UInt<1>(0h0)) when _T_2282 : node _T_2283 = eq(_T_2280, UInt<1>(0h0)) when _T_2283 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_183 assert(clock, _T_2280, UInt<1>(0h1), "") : assert_183 node _T_2284 = eq(io.in.b.bits.size, size_2) node _T_2285 = asUInt(reset) node _T_2286 = eq(_T_2285, UInt<1>(0h0)) when _T_2286 : node _T_2287 = eq(_T_2284, UInt<1>(0h0)) when _T_2287 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_184 assert(clock, _T_2284, UInt<1>(0h1), "") : assert_184 node _T_2288 = eq(io.in.b.bits.source, source_2) node _T_2289 = asUInt(reset) node _T_2290 = eq(_T_2289, UInt<1>(0h0)) when _T_2290 : node _T_2291 = eq(_T_2288, UInt<1>(0h0)) when _T_2291 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_185 assert(clock, _T_2288, UInt<1>(0h1), "") : assert_185 node _T_2292 = eq(io.in.b.bits.address, address_1) node _T_2293 = asUInt(reset) node _T_2294 = eq(_T_2293, UInt<1>(0h0)) when _T_2294 : node _T_2295 = eq(_T_2292, UInt<1>(0h0)) when _T_2295 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_186 assert(clock, _T_2292, UInt<1>(0h1), "") : assert_186 node _T_2296 = and(io.in.b.ready, io.in.b.valid) node _T_2297 = and(_T_2296, b_first) when _T_2297 : connect opcode_2, io.in.b.bits.opcode connect param_2, io.in.b.bits.param connect size_2, io.in.b.bits.size connect source_2, io.in.b.bits.source connect address_1, io.in.b.bits.address node _c_first_T = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.c.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T reg opcode_3 : UInt, clock reg param_3 : UInt, clock reg size_3 : UInt, clock reg source_3 : UInt, clock reg address_2 : UInt, clock node _T_2298 = eq(c_first, UInt<1>(0h0)) node _T_2299 = and(io.in.c.valid, _T_2298) when _T_2299 : node _T_2300 = eq(io.in.c.bits.opcode, opcode_3) node _T_2301 = asUInt(reset) node _T_2302 = eq(_T_2301, UInt<1>(0h0)) when _T_2302 : node _T_2303 = eq(_T_2300, UInt<1>(0h0)) when _T_2303 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_187 assert(clock, _T_2300, UInt<1>(0h1), "") : assert_187 node _T_2304 = eq(io.in.c.bits.param, param_3) node _T_2305 = asUInt(reset) node _T_2306 = eq(_T_2305, UInt<1>(0h0)) when _T_2306 : node _T_2307 = eq(_T_2304, UInt<1>(0h0)) when _T_2307 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_188 assert(clock, _T_2304, UInt<1>(0h1), "") : assert_188 node _T_2308 = eq(io.in.c.bits.size, size_3) node _T_2309 = asUInt(reset) node _T_2310 = eq(_T_2309, UInt<1>(0h0)) when _T_2310 : node _T_2311 = eq(_T_2308, UInt<1>(0h0)) when _T_2311 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_189 assert(clock, _T_2308, UInt<1>(0h1), "") : assert_189 node _T_2312 = eq(io.in.c.bits.source, source_3) node _T_2313 = asUInt(reset) node _T_2314 = eq(_T_2313, UInt<1>(0h0)) when _T_2314 : node _T_2315 = eq(_T_2312, UInt<1>(0h0)) when _T_2315 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_190 assert(clock, _T_2312, UInt<1>(0h1), "") : assert_190 node _T_2316 = eq(io.in.c.bits.address, address_2) node _T_2317 = asUInt(reset) node _T_2318 = eq(_T_2317, UInt<1>(0h0)) when _T_2318 : node _T_2319 = eq(_T_2316, UInt<1>(0h0)) when _T_2319 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_191 assert(clock, _T_2316, UInt<1>(0h1), "") : assert_191 node _T_2320 = and(io.in.c.ready, io.in.c.valid) node _T_2321 = and(_T_2320, c_first) when _T_2321 : connect opcode_3, io.in.c.bits.opcode connect param_3, io.in.c.bits.param connect size_3, io.in.c.bits.size connect source_3, io.in.c.bits.source connect address_2, io.in.c.bits.address regreset inflight : UInt<47>, clock, reset, UInt<47>(0h0) regreset inflight_opcodes : UInt<188>, clock, reset, UInt<188>(0h0) regreset inflight_sizes : UInt<188>, clock, reset, UInt<188>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<47> connect a_set, UInt<47>(0h0) wire a_set_wo_ready : UInt<47> connect a_set_wo_ready, UInt<47>(0h0) wire a_opcodes_set : UInt<188> connect a_opcodes_set, UInt<188>(0h0) wire a_sizes_set : UInt<188> connect a_sizes_set, UInt<188>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_2322 = and(io.in.a.valid, a_first_1) node _T_2323 = and(_T_2322, UInt<1>(0h1)) when _T_2323 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_2324 = and(io.in.a.ready, io.in.a.valid) node _T_2325 = and(_T_2324, a_first_1) node _T_2326 = and(_T_2325, UInt<1>(0h1)) when _T_2326 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_2327 = dshr(inflight, io.in.a.bits.source) node _T_2328 = bits(_T_2327, 0, 0) node _T_2329 = eq(_T_2328, UInt<1>(0h0)) node _T_2330 = asUInt(reset) node _T_2331 = eq(_T_2330, UInt<1>(0h0)) when _T_2331 : node _T_2332 = eq(_T_2329, UInt<1>(0h0)) when _T_2332 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_192 assert(clock, _T_2329, UInt<1>(0h1), "") : assert_192 wire d_clr : UInt<47> connect d_clr, UInt<47>(0h0) wire d_clr_wo_ready : UInt<47> connect d_clr_wo_ready, UInt<47>(0h0) wire d_opcodes_clr : UInt<188> connect d_opcodes_clr, UInt<188>(0h0) wire d_sizes_clr : UInt<188> connect d_sizes_clr, UInt<188>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2333 = and(io.in.d.valid, d_first_1) node _T_2334 = and(_T_2333, UInt<1>(0h1)) node _T_2335 = eq(d_release_ack, UInt<1>(0h0)) node _T_2336 = and(_T_2334, _T_2335) when _T_2336 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_2337 = and(io.in.d.ready, io.in.d.valid) node _T_2338 = and(_T_2337, d_first_1) node _T_2339 = and(_T_2338, UInt<1>(0h1)) node _T_2340 = eq(d_release_ack, UInt<1>(0h0)) node _T_2341 = and(_T_2339, _T_2340) when _T_2341 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_2342 = and(io.in.d.valid, d_first_1) node _T_2343 = and(_T_2342, UInt<1>(0h1)) node _T_2344 = eq(d_release_ack, UInt<1>(0h0)) node _T_2345 = and(_T_2343, _T_2344) when _T_2345 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_2346 = dshr(inflight, io.in.d.bits.source) node _T_2347 = bits(_T_2346, 0, 0) node _T_2348 = or(_T_2347, same_cycle_resp) node _T_2349 = asUInt(reset) node _T_2350 = eq(_T_2349, UInt<1>(0h0)) when _T_2350 : node _T_2351 = eq(_T_2348, UInt<1>(0h0)) when _T_2351 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_193 assert(clock, _T_2348, UInt<1>(0h1), "") : assert_193 when same_cycle_resp : node _T_2352 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_2353 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_2354 = or(_T_2352, _T_2353) node _T_2355 = asUInt(reset) node _T_2356 = eq(_T_2355, UInt<1>(0h0)) when _T_2356 : node _T_2357 = eq(_T_2354, UInt<1>(0h0)) when _T_2357 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_194 assert(clock, _T_2354, UInt<1>(0h1), "") : assert_194 node _T_2358 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_2359 = asUInt(reset) node _T_2360 = eq(_T_2359, UInt<1>(0h0)) when _T_2360 : node _T_2361 = eq(_T_2358, UInt<1>(0h0)) when _T_2361 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_195 assert(clock, _T_2358, UInt<1>(0h1), "") : assert_195 else : node _T_2362 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_2363 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_2364 = or(_T_2362, _T_2363) node _T_2365 = asUInt(reset) node _T_2366 = eq(_T_2365, UInt<1>(0h0)) when _T_2366 : node _T_2367 = eq(_T_2364, UInt<1>(0h0)) when _T_2367 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_196 assert(clock, _T_2364, UInt<1>(0h1), "") : assert_196 node _T_2368 = eq(io.in.d.bits.size, a_size_lookup) node _T_2369 = asUInt(reset) node _T_2370 = eq(_T_2369, UInt<1>(0h0)) when _T_2370 : node _T_2371 = eq(_T_2368, UInt<1>(0h0)) when _T_2371 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_197 assert(clock, _T_2368, UInt<1>(0h1), "") : assert_197 node _T_2372 = and(io.in.d.valid, d_first_1) node _T_2373 = and(_T_2372, a_first_1) node _T_2374 = and(_T_2373, io.in.a.valid) node _T_2375 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_2376 = and(_T_2374, _T_2375) node _T_2377 = eq(d_release_ack, UInt<1>(0h0)) node _T_2378 = and(_T_2376, _T_2377) when _T_2378 : node _T_2379 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2380 = or(_T_2379, io.in.a.ready) node _T_2381 = asUInt(reset) node _T_2382 = eq(_T_2381, UInt<1>(0h0)) when _T_2382 : node _T_2383 = eq(_T_2380, UInt<1>(0h0)) when _T_2383 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_198 assert(clock, _T_2380, UInt<1>(0h1), "") : assert_198 node _T_2384 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_2385 = orr(a_set_wo_ready) node _T_2386 = eq(_T_2385, UInt<1>(0h0)) node _T_2387 = or(_T_2384, _T_2386) node _T_2388 = asUInt(reset) node _T_2389 = eq(_T_2388, UInt<1>(0h0)) when _T_2389 : node _T_2390 = eq(_T_2387, UInt<1>(0h0)) when _T_2390 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_199 assert(clock, _T_2387, UInt<1>(0h1), "") : assert_199 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_91 node _T_2391 = orr(inflight) node _T_2392 = eq(_T_2391, UInt<1>(0h0)) node _T_2393 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_2394 = or(_T_2392, _T_2393) node _T_2395 = lt(watchdog, plusarg_reader.out) node _T_2396 = or(_T_2394, _T_2395) node _T_2397 = asUInt(reset) node _T_2398 = eq(_T_2397, UInt<1>(0h0)) when _T_2398 : node _T_2399 = eq(_T_2396, UInt<1>(0h0)) when _T_2399 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_200 assert(clock, _T_2396, UInt<1>(0h1), "") : assert_200 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_2400 = and(io.in.a.ready, io.in.a.valid) node _T_2401 = and(io.in.d.ready, io.in.d.valid) node _T_2402 = or(_T_2400, _T_2401) when _T_2402 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<47>, clock, reset, UInt<47>(0h0) regreset inflight_opcodes_1 : UInt<188>, clock, reset, UInt<188>(0h0) regreset inflight_sizes_1 : UInt<188>, clock, reset, UInt<188>(0h0) node _c_first_T_1 = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.c.bits.size) node _c_first_beats1_decode_T_4 = bits(_c_first_beats1_decode_T_3, 5, 0) node _c_first_beats1_decode_T_5 = not(_c_first_beats1_decode_T_4) node c_first_beats1_decode_1 = shr(_c_first_beats1_decode_T_5, 3) node c_first_beats1_opdata_1 = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1_1 = mux(c_first_beats1_opdata_1, c_first_beats1_decode_1, UInt<1>(0h0)) regreset c_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T_1 = sub(c_first_counter_1, UInt<1>(0h1)) node c_first_counter1_1 = tail(_c_first_counter1_T_1, 1) node c_first_1 = eq(c_first_counter_1, UInt<1>(0h0)) node _c_first_last_T_2 = eq(c_first_counter_1, UInt<1>(0h1)) node _c_first_last_T_3 = eq(c_first_beats1_1, UInt<1>(0h0)) node c_first_last_1 = or(_c_first_last_T_2, _c_first_last_T_3) node c_first_done_1 = and(c_first_last_1, _c_first_T_1) node _c_first_count_T_1 = not(c_first_counter1_1) node c_first_count_1 = and(c_first_beats1_1, _c_first_count_T_1) when _c_first_T_1 : node _c_first_counter_T_1 = mux(c_first_1, c_first_beats1_1, c_first_counter1_1) connect c_first_counter_1, _c_first_counter_T_1 node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<47> connect c_set, UInt<47>(0h0) wire c_set_wo_ready : UInt<47> connect c_set_wo_ready, UInt<47>(0h0) wire c_opcodes_set : UInt<188> connect c_opcodes_set, UInt<188>(0h0) wire c_sizes_set : UInt<188> connect c_sizes_set, UInt<188>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) node _T_2403 = and(io.in.c.valid, c_first_1) node _T_2404 = bits(io.in.c.bits.opcode, 2, 2) node _T_2405 = bits(io.in.c.bits.opcode, 1, 1) node _T_2406 = and(_T_2404, _T_2405) node _T_2407 = and(_T_2403, _T_2406) when _T_2407 : node _c_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T node _T_2408 = and(io.in.c.ready, io.in.c.valid) node _T_2409 = and(_T_2408, c_first_1) node _T_2410 = bits(io.in.c.bits.opcode, 2, 2) node _T_2411 = bits(io.in.c.bits.opcode, 1, 1) node _T_2412 = and(_T_2410, _T_2411) node _T_2413 = and(_T_2409, _T_2412) when _T_2413 : node _c_set_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set, _c_set_T node _c_opcodes_set_interm_T = dshl(io.in.c.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 node _c_sizes_set_interm_T = dshl(io.in.c.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 node _c_opcodes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 node _c_sizes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 node _T_2414 = dshr(inflight_1, io.in.c.bits.source) node _T_2415 = bits(_T_2414, 0, 0) node _T_2416 = eq(_T_2415, UInt<1>(0h0)) node _T_2417 = asUInt(reset) node _T_2418 = eq(_T_2417, UInt<1>(0h0)) when _T_2418 : node _T_2419 = eq(_T_2416, UInt<1>(0h0)) when _T_2419 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_201 assert(clock, _T_2416, UInt<1>(0h1), "") : assert_201 node _c_probe_ack_T = eq(io.in.c.bits.opcode, UInt<3>(0h4)) node _c_probe_ack_T_1 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<47> connect d_clr_1, UInt<47>(0h0) wire d_clr_wo_ready_1 : UInt<47> connect d_clr_wo_ready_1, UInt<47>(0h0) wire d_opcodes_clr_1 : UInt<188> connect d_opcodes_clr_1, UInt<188>(0h0) wire d_sizes_clr_1 : UInt<188> connect d_sizes_clr_1, UInt<188>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2420 = and(io.in.d.valid, d_first_2) node _T_2421 = and(_T_2420, UInt<1>(0h1)) node _T_2422 = and(_T_2421, d_release_ack_1) when _T_2422 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_2423 = and(io.in.d.ready, io.in.d.valid) node _T_2424 = and(_T_2423, d_first_2) node _T_2425 = and(_T_2424, UInt<1>(0h1)) node _T_2426 = and(_T_2425, d_release_ack_1) when _T_2426 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_2427 = and(io.in.d.valid, d_first_2) node _T_2428 = and(_T_2427, UInt<1>(0h1)) node _T_2429 = and(_T_2428, d_release_ack_1) when _T_2429 : node _same_cycle_resp_T_3 = and(io.in.c.valid, c_first_1) node _same_cycle_resp_T_4 = bits(io.in.c.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(io.in.c.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) node _same_cycle_resp_T_8 = eq(io.in.c.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_2430 = dshr(inflight_1, io.in.d.bits.source) node _T_2431 = bits(_T_2430, 0, 0) node _T_2432 = or(_T_2431, same_cycle_resp_1) node _T_2433 = asUInt(reset) node _T_2434 = eq(_T_2433, UInt<1>(0h0)) when _T_2434 : node _T_2435 = eq(_T_2432, UInt<1>(0h0)) when _T_2435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_202 assert(clock, _T_2432, UInt<1>(0h1), "") : assert_202 when same_cycle_resp_1 : node _T_2436 = eq(io.in.d.bits.size, io.in.c.bits.size) node _T_2437 = asUInt(reset) node _T_2438 = eq(_T_2437, UInt<1>(0h0)) when _T_2438 : node _T_2439 = eq(_T_2436, UInt<1>(0h0)) when _T_2439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_203 assert(clock, _T_2436, UInt<1>(0h1), "") : assert_203 else : node _T_2440 = eq(io.in.d.bits.size, c_size_lookup) node _T_2441 = asUInt(reset) node _T_2442 = eq(_T_2441, UInt<1>(0h0)) when _T_2442 : node _T_2443 = eq(_T_2440, UInt<1>(0h0)) when _T_2443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_204 assert(clock, _T_2440, UInt<1>(0h1), "") : assert_204 node _T_2444 = and(io.in.d.valid, d_first_2) node _T_2445 = and(_T_2444, c_first_1) node _T_2446 = and(_T_2445, io.in.c.valid) node _T_2447 = eq(io.in.c.bits.source, io.in.d.bits.source) node _T_2448 = and(_T_2446, _T_2447) node _T_2449 = and(_T_2448, d_release_ack_1) node _T_2450 = eq(c_probe_ack, UInt<1>(0h0)) node _T_2451 = and(_T_2449, _T_2450) when _T_2451 : node _T_2452 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2453 = or(_T_2452, io.in.c.ready) node _T_2454 = asUInt(reset) node _T_2455 = eq(_T_2454, UInt<1>(0h0)) when _T_2455 : node _T_2456 = eq(_T_2453, UInt<1>(0h0)) when _T_2456 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_205 assert(clock, _T_2453, UInt<1>(0h1), "") : assert_205 node _T_2457 = orr(c_set_wo_ready) when _T_2457 : node _T_2458 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_2459 = asUInt(reset) node _T_2460 = eq(_T_2459, UInt<1>(0h0)) when _T_2460 : node _T_2461 = eq(_T_2458, UInt<1>(0h0)) when _T_2461 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_206 assert(clock, _T_2458, UInt<1>(0h1), "") : assert_206 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_92 node _T_2462 = orr(inflight_1) node _T_2463 = eq(_T_2462, UInt<1>(0h0)) node _T_2464 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_2465 = or(_T_2463, _T_2464) node _T_2466 = lt(watchdog_1, plusarg_reader_1.out) node _T_2467 = or(_T_2465, _T_2466) node _T_2468 = asUInt(reset) node _T_2469 = eq(_T_2468, UInt<1>(0h0)) when _T_2469 : node _T_2470 = eq(_T_2467, UInt<1>(0h0)) when _T_2470 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_207 assert(clock, _T_2467, UInt<1>(0h1), "") : assert_207 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 node _T_2471 = and(io.in.c.ready, io.in.c.valid) node _T_2472 = and(io.in.d.ready, io.in.d.valid) node _T_2473 = or(_T_2471, _T_2472) when _T_2473 : connect watchdog_1, UInt<1>(0h0) regreset inflight_2 : UInt<7>, clock, reset, UInt<7>(0h0) node _d_first_T_3 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_9 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_10 = bits(_d_first_beats1_decode_T_9, 5, 0) node _d_first_beats1_decode_T_11 = not(_d_first_beats1_decode_T_10) node d_first_beats1_decode_3 = shr(_d_first_beats1_decode_T_11, 3) node d_first_beats1_opdata_3 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_3 = mux(d_first_beats1_opdata_3, d_first_beats1_decode_3, UInt<1>(0h0)) regreset d_first_counter_3 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_3 = sub(d_first_counter_3, UInt<1>(0h1)) node d_first_counter1_3 = tail(_d_first_counter1_T_3, 1) node d_first_3 = eq(d_first_counter_3, UInt<1>(0h0)) node _d_first_last_T_6 = eq(d_first_counter_3, UInt<1>(0h1)) node _d_first_last_T_7 = eq(d_first_beats1_3, UInt<1>(0h0)) node d_first_last_3 = or(_d_first_last_T_6, _d_first_last_T_7) node d_first_done_3 = and(d_first_last_3, _d_first_T_3) node _d_first_count_T_3 = not(d_first_counter1_3) node d_first_count_3 = and(d_first_beats1_3, _d_first_count_T_3) when _d_first_T_3 : node _d_first_counter_T_3 = mux(d_first_3, d_first_beats1_3, d_first_counter1_3) connect d_first_counter_3, _d_first_counter_T_3 wire d_set : UInt<7> connect d_set, UInt<7>(0h0) node _T_2474 = and(io.in.d.ready, io.in.d.valid) node _T_2475 = and(_T_2474, d_first_3) node _T_2476 = bits(io.in.d.bits.opcode, 2, 2) node _T_2477 = bits(io.in.d.bits.opcode, 1, 1) node _T_2478 = eq(_T_2477, UInt<1>(0h0)) node _T_2479 = and(_T_2476, _T_2478) node _T_2480 = and(_T_2475, _T_2479) when _T_2480 : node _d_set_T = dshl(UInt<1>(0h1), io.in.d.bits.sink) connect d_set, _d_set_T node _T_2481 = dshr(inflight_2, io.in.d.bits.sink) node _T_2482 = bits(_T_2481, 0, 0) node _T_2483 = eq(_T_2482, UInt<1>(0h0)) node _T_2484 = asUInt(reset) node _T_2485 = eq(_T_2484, UInt<1>(0h0)) when _T_2485 : node _T_2486 = eq(_T_2483, UInt<1>(0h0)) when _T_2486 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel re-used a sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_208 assert(clock, _T_2483, UInt<1>(0h1), "") : assert_208 wire e_clr : UInt<7> connect e_clr, UInt<7>(0h0) node _T_2487 = and(io.in.e.ready, io.in.e.valid) node _T_2488 = and(_T_2487, UInt<1>(0h1)) node _T_2489 = and(_T_2488, UInt<1>(0h1)) when _T_2489 : node _e_clr_T = dshl(UInt<1>(0h1), io.in.e.bits.sink) connect e_clr, _e_clr_T node _T_2490 = or(d_set, inflight_2) node _T_2491 = dshr(_T_2490, io.in.e.bits.sink) node _T_2492 = bits(_T_2491, 0, 0) node _T_2493 = asUInt(reset) node _T_2494 = eq(_T_2493, UInt<1>(0h0)) when _T_2494 : node _T_2495 = eq(_T_2492, UInt<1>(0h0)) when _T_2495 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_209 assert(clock, _T_2492, UInt<1>(0h1), "") : assert_209 node _inflight_T_6 = or(inflight_2, d_set) node _inflight_T_7 = not(e_clr) node _inflight_T_8 = and(_inflight_T_6, _inflight_T_7) connect inflight_2, _inflight_T_8 extmodule plusarg_reader_93 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_94 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32	module TLMonitor_41( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_b_ready, // @[Monitor.scala:20:14] input io_in_b_valid, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14] input [5:0] io_in_b_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input io_in_c_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [2:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire [12:0] _GEN_0 = {10'h0, io_in_c_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [2:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [5:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _d_first_T_3 = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala:51:35] reg [2:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [5:0] source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [2:0] b_first_counter; // @[Edges.scala:229:27] reg [1:0] param_2; // @[Monitor.scala:411:22] reg [5:0] source_2; // @[Monitor.scala:413:22] reg [31:0] address_1; // @[Monitor.scala:414:22] wire _c_first_T_1 = io_in_c_ready & io_in_c_valid; // @[Decoupled.scala:51:35] reg [2:0] c_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [2:0] size_3; // @[Monitor.scala:517:22] reg [5:0] source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [46:0] inflight; // @[Monitor.scala:614:27] reg [187:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [187:0] inflight_sizes; // @[Monitor.scala:618:33] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire [63:0] _GEN_1 = {58'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35] wire _GEN_2 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_3 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] wire [63:0] _GEN_4 = {58'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [46:0] inflight_1; // @[Monitor.scala:726:35] reg [187:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [2:0] c_first_counter_1; // @[Edges.scala:229:27] wire c_first_1 = c_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _GEN_5 = io_in_c_bits_opcode[2] & io_in_c_bits_opcode[1]; // @[Edges.scala:68:{36,40,51}] wire [63:0] _GEN_6 = {58'h0, io_in_c_bits_source}; // @[OneHot.scala:58:35] wire _GEN_7 = _c_first_T_1 & c_first_1 & _GEN_5; // @[Decoupled.scala:51:35] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] reg [6:0] inflight_2; // @[Monitor.scala:828:27] reg [2:0] d_first_counter_3; // @[Edges.scala:229:27] wire d_first_3 = d_first_counter_3 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _GEN_8 = _d_first_T_3 & d_first_3 & io_in_d_bits_opcode[2] & ~(io_in_d_bits_opcode[1]); // @[Decoupled.scala:51:35] wire [7:0] _d_set_T = 8'h1 << io_in_d_bits_sink; // @[OneHot.scala:58:35] wire [6:0] d_set = _GEN_8 ? _d_set_T[6:0] : 7'h0; // @[OneHot.scala:58:35]
Generate the Verilog code corresponding to this FIRRTL code module ClockCrossingReg_w15 : input clock : Clock input reset : Reset output io : { flip d : UInt<15>, q : UInt<15>, flip en : UInt<1>} reg cdc_reg : UInt<15>, clock when io.en : connect cdc_reg, io.d connect io.q, cdc_reg	module ClockCrossingReg_w15( // @[SynchronizerReg.scala:191:7] input clock, // @[SynchronizerReg.scala:191:7] input reset, // @[SynchronizerReg.scala:191:7] input [14:0] io_d, // @[SynchronizerReg.scala:195:14] output [14:0] io_q, // @[SynchronizerReg.scala:195:14] input io_en // @[SynchronizerReg.scala:195:14] ); wire [14:0] io_d_0 = io_d; // @[SynchronizerReg.scala:191:7] wire io_en_0 = io_en; // @[SynchronizerReg.scala:191:7] wire [14:0] io_q_0; // @[SynchronizerReg.scala:191:7] reg [14:0] cdc_reg; // @[SynchronizerReg.scala:201:76] assign io_q_0 = cdc_reg; // @[SynchronizerReg.scala:191:7, :201:76] always @(posedge clock) begin // @[SynchronizerReg.scala:191:7] if (io_en_0) // @[SynchronizerReg.scala:191:7] cdc_reg <= io_d_0; // @[SynchronizerReg.scala:191:7, :201:76] always @(posedge) assign io_q = io_q_0; // @[SynchronizerReg.scala:191:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_44 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 10, 0) node _source_ok_T = shr(io.in.a.bits.source, 11) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<11>(0h40f)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits = bits(_uncommonBits_T, 10, 0) node _T_4 = shr(io.in.a.bits.source, 11) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<11>(0h40f)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 10, 0) node _T_24 = shr(io.in.a.bits.source, 11) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<11>(0h40f)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<17>(0h10000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 10, 0) node _T_86 = shr(io.in.a.bits.source, 11) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<11>(0h40f)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<17>(0h10000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<17>(0h10000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 10, 0) node _T_152 = shr(io.in.a.bits.source, 11) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<11>(0h40f)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<17>(0h10000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 10, 0) node _T_199 = shr(io.in.a.bits.source, 11) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<11>(0h40f)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_208 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_209 = and(_T_207, _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<17>(0h10000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = and(_T_210, _T_215) node _T_217 = or(UInt<1>(0h0), _T_216) node _T_218 = and(_T_206, _T_217) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_218, UInt<1>(0h1), "") : assert_26 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(is_aligned, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_228, UInt<1>(0h1), "") : assert_29 node _T_232 = eq(io.in.a.bits.mask, mask) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_236 : node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_239 = and(_T_237, _T_238) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 10, 0) node _T_240 = shr(io.in.a.bits.source, 11) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = leq(UInt<1>(0h0), uncommonBits_5) node _T_243 = and(_T_241, _T_242) node _T_244 = leq(uncommonBits_5, UInt<11>(0h40f)) node _T_245 = and(_T_243, _T_244) node _T_246 = and(_T_239, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_253 = cvt(_T_252) node _T_254 = and(_T_253, asSInt(UInt<17>(0h10000))) node _T_255 = asSInt(_T_254) node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) node _T_257 = and(_T_251, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = and(_T_247, _T_258) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_259, UInt<1>(0h1), "") : assert_31 node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(is_aligned, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_269, UInt<1>(0h1), "") : assert_34 node _T_273 = not(mask) node _T_274 = and(io.in.a.bits.mask, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_275, UInt<1>(0h1), "") : assert_35 node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_279 : node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_282 = and(_T_280, _T_281) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 10, 0) node _T_283 = shr(io.in.a.bits.source, 11) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = leq(UInt<1>(0h0), uncommonBits_6) node _T_286 = and(_T_284, _T_285) node _T_287 = leq(uncommonBits_6, UInt<11>(0h40f)) node _T_288 = and(_T_286, _T_287) node _T_289 = and(_T_282, _T_288) node _T_290 = or(UInt<1>(0h0), _T_289) node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_292 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<17>(0h10000))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = and(_T_291, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = and(_T_290, _T_298) node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_T_299, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_299, UInt<1>(0h1), "") : assert_36 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(is_aligned, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_309, UInt<1>(0h1), "") : assert_39 node _T_313 = eq(io.in.a.bits.mask, mask) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_313, UInt<1>(0h1), "") : assert_40 node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_317 : node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 10, 0) node _T_321 = shr(io.in.a.bits.source, 11) node _T_322 = eq(_T_321, UInt<1>(0h0)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_7) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_7, UInt<11>(0h40f)) node _T_326 = and(_T_324, _T_325) node _T_327 = and(_T_320, _T_326) node _T_328 = or(UInt<1>(0h0), _T_327) node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<17>(0h10000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = and(_T_329, _T_334) node _T_336 = or(UInt<1>(0h0), _T_335) node _T_337 = and(_T_328, _T_336) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_337, UInt<1>(0h1), "") : assert_41 node _T_341 = asUInt(reset) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(is_aligned, UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_347, UInt<1>(0h1), "") : assert_44 node _T_351 = eq(io.in.a.bits.mask, mask) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_351, UInt<1>(0h1), "") : assert_45 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 10, 0) node _T_359 = shr(io.in.a.bits.source, 11) node _T_360 = eq(_T_359, UInt<1>(0h0)) node _T_361 = leq(UInt<1>(0h0), uncommonBits_8) node _T_362 = and(_T_360, _T_361) node _T_363 = leq(uncommonBits_8, UInt<11>(0h40f)) node _T_364 = and(_T_362, _T_363) node _T_365 = and(_T_358, _T_364) node _T_366 = or(UInt<1>(0h0), _T_365) node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_369 = cvt(_T_368) node _T_370 = and(_T_369, asSInt(UInt<17>(0h10000))) node _T_371 = asSInt(_T_370) node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0))) node _T_373 = and(_T_367, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = and(_T_366, _T_374) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_375, UInt<1>(0h1), "") : assert_46 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(is_aligned, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_385, UInt<1>(0h1), "") : assert_49 node _T_389 = eq(io.in.a.bits.mask, mask) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_389, UInt<1>(0h1), "") : assert_50 node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_393, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_397, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<11>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 10, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 11) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<11>(0h40f)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_401 : node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_405, UInt<1>(0h1), "") : assert_54 node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_409, UInt<1>(0h1), "") : assert_55 node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_413, UInt<1>(0h1), "") : assert_56 node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(_T_417, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_417, UInt<1>(0h1), "") : assert_57 node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_421 : node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(sink_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_428, UInt<1>(0h1), "") : assert_60 node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_432, UInt<1>(0h1), "") : assert_61 node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_436, UInt<1>(0h1), "") : assert_62 node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(_T_440, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_440, UInt<1>(0h1), "") : assert_63 node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_445 = or(UInt<1>(0h0), _T_444) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_445, UInt<1>(0h1), "") : assert_64 node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_449 : node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(sink_ok, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_457 = asUInt(reset) node _T_458 = eq(_T_457, UInt<1>(0h0)) when _T_458 : node _T_459 = eq(_T_456, UInt<1>(0h0)) when _T_459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_456, UInt<1>(0h1), "") : assert_67 node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_T_460, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_460, UInt<1>(0h1), "") : assert_68 node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_464, UInt<1>(0h1), "") : assert_69 node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_469 = or(_T_468, io.in.d.bits.corrupt) node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_T_469, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_469, UInt<1>(0h1), "") : assert_70 node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_474 = or(UInt<1>(0h0), _T_473) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_474, UInt<1>(0h1), "") : assert_71 node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_478 : node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_482, UInt<1>(0h1), "") : assert_73 node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_486, UInt<1>(0h1), "") : assert_74 node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_491, UInt<1>(0h1), "") : assert_75 node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_495 : node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_499, UInt<1>(0h1), "") : assert_77 node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_504 = or(_T_503, io.in.d.bits.corrupt) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_504, UInt<1>(0h1), "") : assert_78 node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_509, UInt<1>(0h1), "") : assert_79 node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_513 : node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_517, UInt<1>(0h1), "") : assert_81 node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_521, UInt<1>(0h1), "") : assert_82 node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_526 = or(UInt<1>(0h0), _T_525) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_526, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<26>(0h0) connect _WIRE.bits.source, UInt<11>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_530, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<26>(0h0) connect _WIRE_2.bits.source, UInt<11>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_534, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_538, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_542 = eq(a_first, UInt<1>(0h0)) node _T_543 = and(io.in.a.valid, _T_542) when _T_543 : node _T_544 = eq(io.in.a.bits.opcode, opcode) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_544, UInt<1>(0h1), "") : assert_87 node _T_548 = eq(io.in.a.bits.param, param) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_548, UInt<1>(0h1), "") : assert_88 node _T_552 = eq(io.in.a.bits.size, size) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_552, UInt<1>(0h1), "") : assert_89 node _T_556 = eq(io.in.a.bits.source, source) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_556, UInt<1>(0h1), "") : assert_90 node _T_560 = eq(io.in.a.bits.address, address) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_560, UInt<1>(0h1), "") : assert_91 node _T_564 = and(io.in.a.ready, io.in.a.valid) node _T_565 = and(_T_564, a_first) when _T_565 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_566 = eq(d_first, UInt<1>(0h0)) node _T_567 = and(io.in.d.valid, _T_566) when _T_567 : node _T_568 = eq(io.in.d.bits.opcode, opcode_1) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_568, UInt<1>(0h1), "") : assert_92 node _T_572 = eq(io.in.d.bits.param, param_1) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_572, UInt<1>(0h1), "") : assert_93 node _T_576 = eq(io.in.d.bits.size, size_1) node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(_T_576, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_576, UInt<1>(0h1), "") : assert_94 node _T_580 = eq(io.in.d.bits.source, source_1) node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(_T_580, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_580, UInt<1>(0h1), "") : assert_95 node _T_584 = eq(io.in.d.bits.sink, sink) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_584, UInt<1>(0h1), "") : assert_96 node _T_588 = eq(io.in.d.bits.denied, denied) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_588, UInt<1>(0h1), "") : assert_97 node _T_592 = and(io.in.d.ready, io.in.d.valid) node _T_593 = and(_T_592, d_first) when _T_593 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<1040>, clock, reset, UInt<1040>(0h0) regreset inflight_opcodes : UInt<4160>, clock, reset, UInt<4160>(0h0) regreset inflight_sizes : UInt<4160>, clock, reset, UInt<4160>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1040> connect a_set, UInt<1040>(0h0) wire a_set_wo_ready : UInt<1040> connect a_set_wo_ready, UInt<1040>(0h0) wire a_opcodes_set : UInt<4160> connect a_opcodes_set, UInt<4160>(0h0) wire a_sizes_set : UInt<4160> connect a_sizes_set, UInt<4160>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_594 = and(io.in.a.valid, a_first_1) node _T_595 = and(_T_594, UInt<1>(0h1)) when _T_595 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_596 = and(io.in.a.ready, io.in.a.valid) node _T_597 = and(_T_596, a_first_1) node _T_598 = and(_T_597, UInt<1>(0h1)) when _T_598 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_599 = dshr(inflight, io.in.a.bits.source) node _T_600 = bits(_T_599, 0, 0) node _T_601 = eq(_T_600, UInt<1>(0h0)) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_601, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1040> connect d_clr, UInt<1040>(0h0) wire d_clr_wo_ready : UInt<1040> connect d_clr_wo_ready, UInt<1040>(0h0) wire d_opcodes_clr : UInt<4160> connect d_opcodes_clr, UInt<4160>(0h0) wire d_sizes_clr : UInt<4160> connect d_sizes_clr, UInt<4160>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_605 = and(io.in.d.valid, d_first_1) node _T_606 = and(_T_605, UInt<1>(0h1)) node _T_607 = eq(d_release_ack, UInt<1>(0h0)) node _T_608 = and(_T_606, _T_607) when _T_608 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_609 = and(io.in.d.ready, io.in.d.valid) node _T_610 = and(_T_609, d_first_1) node _T_611 = and(_T_610, UInt<1>(0h1)) node _T_612 = eq(d_release_ack, UInt<1>(0h0)) node _T_613 = and(_T_611, _T_612) when _T_613 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_614 = and(io.in.d.valid, d_first_1) node _T_615 = and(_T_614, UInt<1>(0h1)) node _T_616 = eq(d_release_ack, UInt<1>(0h0)) node _T_617 = and(_T_615, _T_616) when _T_617 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_618 = dshr(inflight, io.in.d.bits.source) node _T_619 = bits(_T_618, 0, 0) node _T_620 = or(_T_619, same_cycle_resp) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_620, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_626 = or(_T_624, _T_625) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_626, UInt<1>(0h1), "") : assert_100 node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_630, UInt<1>(0h1), "") : assert_101 else : node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_636 = or(_T_634, _T_635) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_636, UInt<1>(0h1), "") : assert_102 node _T_640 = eq(io.in.d.bits.size, a_size_lookup) node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(_T_640, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_640, UInt<1>(0h1), "") : assert_103 node _T_644 = and(io.in.d.valid, d_first_1) node _T_645 = and(_T_644, a_first_1) node _T_646 = and(_T_645, io.in.a.valid) node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_648 = and(_T_646, _T_647) node _T_649 = eq(d_release_ack, UInt<1>(0h0)) node _T_650 = and(_T_648, _T_649) when _T_650 : node _T_651 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_652 = or(_T_651, io.in.a.ready) node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(_T_652, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_652, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_89 node _T_656 = orr(inflight) node _T_657 = eq(_T_656, UInt<1>(0h0)) node _T_658 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_659 = or(_T_657, _T_658) node _T_660 = lt(watchdog, plusarg_reader.out) node _T_661 = or(_T_659, _T_660) node _T_662 = asUInt(reset) node _T_663 = eq(_T_662, UInt<1>(0h0)) when _T_663 : node _T_664 = eq(_T_661, UInt<1>(0h0)) when _T_664 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_661, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_665 = and(io.in.a.ready, io.in.a.valid) node _T_666 = and(io.in.d.ready, io.in.d.valid) node _T_667 = or(_T_665, _T_666) when _T_667 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<1040>, clock, reset, UInt<1040>(0h0) regreset inflight_opcodes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0) regreset inflight_sizes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<26>(0h0) connect _c_first_WIRE.bits.source, UInt<11>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<26>(0h0) connect _c_first_WIRE_2.bits.source, UInt<11>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1040> connect c_set, UInt<1040>(0h0) wire c_set_wo_ready : UInt<1040> connect c_set_wo_ready, UInt<1040>(0h0) wire c_opcodes_set : UInt<4160> connect c_opcodes_set, UInt<4160>(0h0) wire c_sizes_set : UInt<4160> connect c_sizes_set, UInt<4160>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<26>(0h0) connect _WIRE_6.bits.source, UInt<11>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_668 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<26>(0h0) connect _WIRE_8.bits.source, UInt<11>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_669 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_670 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_671 = and(_T_669, _T_670) node _T_672 = and(_T_668, _T_671) when _T_672 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<26>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<11>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<26>(0h0) connect _WIRE_10.bits.source, UInt<11>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_673 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_674 = and(_T_673, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<26>(0h0) connect _WIRE_12.bits.source, UInt<11>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_675 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_676 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_677 = and(_T_675, _T_676) node _T_678 = and(_T_674, _T_677) when _T_678 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<26>(0h0) connect _c_set_WIRE.bits.source, UInt<11>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<26>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<11>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<26>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<11>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<26>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<11>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<26>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<11>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<26>(0h0) connect _WIRE_14.bits.source, UInt<11>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_679 = dshr(inflight_1, _WIRE_15.bits.source) node _T_680 = bits(_T_679, 0, 0) node _T_681 = eq(_T_680, UInt<1>(0h0)) node _T_682 = asUInt(reset) node _T_683 = eq(_T_682, UInt<1>(0h0)) when _T_683 : node _T_684 = eq(_T_681, UInt<1>(0h0)) when _T_684 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_681, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<26>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<11>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<26>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<11>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1040> connect d_clr_1, UInt<1040>(0h0) wire d_clr_wo_ready_1 : UInt<1040> connect d_clr_wo_ready_1, UInt<1040>(0h0) wire d_opcodes_clr_1 : UInt<4160> connect d_opcodes_clr_1, UInt<4160>(0h0) wire d_sizes_clr_1 : UInt<4160> connect d_sizes_clr_1, UInt<4160>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_685 = and(io.in.d.valid, d_first_2) node _T_686 = and(_T_685, UInt<1>(0h1)) node _T_687 = and(_T_686, d_release_ack_1) when _T_687 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_688 = and(io.in.d.ready, io.in.d.valid) node _T_689 = and(_T_688, d_first_2) node _T_690 = and(_T_689, UInt<1>(0h1)) node _T_691 = and(_T_690, d_release_ack_1) when _T_691 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_692 = and(io.in.d.valid, d_first_2) node _T_693 = and(_T_692, UInt<1>(0h1)) node _T_694 = and(_T_693, d_release_ack_1) when _T_694 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<26>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<26>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<26>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_695 = dshr(inflight_1, io.in.d.bits.source) node _T_696 = bits(_T_695, 0, 0) node _T_697 = or(_T_696, same_cycle_resp_1) node _T_698 = asUInt(reset) node _T_699 = eq(_T_698, UInt<1>(0h0)) when _T_699 : node _T_700 = eq(_T_697, UInt<1>(0h0)) when _T_700 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_697, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<26>(0h0) connect _WIRE_16.bits.source, UInt<11>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_701 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_702 = asUInt(reset) node _T_703 = eq(_T_702, UInt<1>(0h0)) when _T_703 : node _T_704 = eq(_T_701, UInt<1>(0h0)) when _T_704 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_701, UInt<1>(0h1), "") : assert_108 else : node _T_705 = eq(io.in.d.bits.size, c_size_lookup) node _T_706 = asUInt(reset) node _T_707 = eq(_T_706, UInt<1>(0h0)) when _T_707 : node _T_708 = eq(_T_705, UInt<1>(0h0)) when _T_708 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_705, UInt<1>(0h1), "") : assert_109 node _T_709 = and(io.in.d.valid, d_first_2) node _T_710 = and(_T_709, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<26>(0h0) connect _WIRE_18.bits.source, UInt<11>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_711 = and(_T_710, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<26>(0h0) connect _WIRE_20.bits.source, UInt<11>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_712 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_713 = and(_T_711, _T_712) node _T_714 = and(_T_713, d_release_ack_1) node _T_715 = eq(c_probe_ack, UInt<1>(0h0)) node _T_716 = and(_T_714, _T_715) when _T_716 : node _T_717 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<26>(0h0) connect _WIRE_22.bits.source, UInt<11>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_718 = or(_T_717, _WIRE_23.ready) node _T_719 = asUInt(reset) node _T_720 = eq(_T_719, UInt<1>(0h0)) when _T_720 : node _T_721 = eq(_T_718, UInt<1>(0h0)) when _T_721 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_718, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_90 node _T_722 = orr(inflight_1) node _T_723 = eq(_T_722, UInt<1>(0h0)) node _T_724 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_725 = or(_T_723, _T_724) node _T_726 = lt(watchdog_1, plusarg_reader_1.out) node _T_727 = or(_T_725, _T_726) node _T_728 = asUInt(reset) node _T_729 = eq(_T_728, UInt<1>(0h0)) when _T_729 : node _T_730 = eq(_T_727, UInt<1>(0h0)) when _T_730 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:37)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_727, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<26>(0h0) connect _WIRE_24.bits.source, UInt<11>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_731 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_732 = and(io.in.d.ready, io.in.d.valid) node _T_733 = or(_T_731, _T_732) when _T_733 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_44( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [25:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [25:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [25:0] _c_first_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_first_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_first_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_first_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_set_wo_ready_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_set_wo_ready_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_opcodes_set_interm_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_opcodes_set_interm_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_sizes_set_interm_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_sizes_set_interm_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_opcodes_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_opcodes_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_sizes_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_sizes_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_probe_ack_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_probe_ack_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_probe_ack_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_probe_ack_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _same_cycle_resp_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _same_cycle_resp_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _same_cycle_resp_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _same_cycle_resp_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _same_cycle_resp_WIRE_4_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _same_cycle_resp_WIRE_5_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_wo_ready_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_wo_ready_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_4_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_5_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [16385:0] _c_sizes_set_T_1 = 16386'h0; // @[Monitor.scala:768:52] wire [13:0] _c_opcodes_set_T = 14'h0; // @[Monitor.scala:767:79] wire [13:0] _c_sizes_set_T = 14'h0; // @[Monitor.scala:768:77] wire [16386:0] _c_opcodes_set_T_1 = 16387'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [2047:0] _c_set_wo_ready_T = 2048'h1; // @[OneHot.scala:58:35] wire [2047:0] _c_set_T = 2048'h1; // @[OneHot.scala:58:35] wire [4159:0] c_opcodes_set = 4160'h0; // @[Monitor.scala:740:34] wire [4159:0] c_sizes_set = 4160'h0; // @[Monitor.scala:741:34] wire [1039:0] c_set = 1040'h0; // @[Monitor.scala:738:34] wire [1039:0] c_set_wo_ready = 1040'h0; // @[Monitor.scala:739:34] wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76] wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [10:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [25:0] _is_aligned_T = {23'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 26'h0; // @[Edges.scala:21:{16,24}] wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [10:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [10:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_665 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_665; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_665; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [10:0] source; // @[Monitor.scala:390:22] reg [25:0] address; // @[Monitor.scala:391:22] wire _T_733 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_733; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [10:0] source_1; // @[Monitor.scala:541:22] reg [1039:0] inflight; // @[Monitor.scala:614:27] reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [1039:0] a_set; // @[Monitor.scala:626:34] wire [1039:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [4159:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [4159:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [13:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [13:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [13:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [13:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [13:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [13:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [13:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [13:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [13:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [4159:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [4159:0] _a_opcode_lookup_T_6 = {4156'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [4159:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [4159:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [4159:0] _a_size_lookup_T_6 = {4156'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [4159:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[4159:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [2047:0] _GEN_2 = 2048'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [2047:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_665 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [13:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [13:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [13:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [16386:0] _a_opcodes_set_T_1 = {16383'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [16385:0] _a_sizes_set_T_1 = {16383'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [1039:0] d_clr; // @[Monitor.scala:664:34] wire [1039:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [4159:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [4159:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [2047:0] _GEN_5 = 2048'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_733 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [16398:0] _d_opcodes_clr_T_5 = 16399'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [16398:0] _d_sizes_clr_T_5 = 16399'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1039:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [1039:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1039:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [4159:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [4159:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [4159:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [4159:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [4159:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [4159:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1039:0] inflight_1; // @[Monitor.scala:726:35] wire [1039:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [4159:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [4159:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [4159:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [4159:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [4159:0] _c_opcode_lookup_T_6 = {4156'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [4159:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [4159:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [4159:0] _c_size_lookup_T_6 = {4156'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [4159:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[4159:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [1039:0] d_clr_1; // @[Monitor.scala:774:34] wire [1039:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [4159:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [4159:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_709 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_709 & d_release_ack_1 ? _d_clr_wo_ready_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_691 = _T_733 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_691 ? _d_clr_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [16398:0] _d_opcodes_clr_T_11 = 16399'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_691 ? _d_opcodes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [16398:0] _d_sizes_clr_T_11 = 16399'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_691 ? _d_sizes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 11'h0; // @[Monitor.scala:36:7, :795:113] wire [1039:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1039:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [4159:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [4159:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [4159:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [4159:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module LevelGateway : input clock : Clock input reset : Reset output io : { flip interrupt : UInt<1>, plic : { valid : UInt<1>, flip ready : UInt<1>, flip complete : UInt<1>}} regreset inFlight : UInt<1>, clock, reset, UInt<1>(0h0) node _T = and(io.interrupt, io.plic.ready) when _T : connect inFlight, UInt<1>(0h1) when io.plic.complete : connect inFlight, UInt<1>(0h0) node _io_plic_valid_T = eq(inFlight, UInt<1>(0h0)) node _io_plic_valid_T_1 = and(io.interrupt, _io_plic_valid_T) connect io.plic.valid, _io_plic_valid_T_1	module LevelGateway( // @[Plic.scala:31:7] input clock, // @[Plic.scala:31:7] input reset, // @[Plic.scala:31:7] input io_interrupt, // @[Plic.scala:32:14] output io_plic_valid, // @[Plic.scala:32:14] input io_plic_ready, // @[Plic.scala:32:14] input io_plic_complete // @[Plic.scala:32:14] ); reg inFlight; // @[Plic.scala:37:25] always @(posedge clock) begin // @[Plic.scala:31:7] if (reset) // @[Plic.scala:31:7] inFlight <= 1'h0; // @[Plic.scala:31:7, :37:25] else // @[Plic.scala:31:7] inFlight <= ~io_plic_complete & (io_interrupt & io_plic_ready \| inFlight); // @[Plic.scala:37:25, :38:{22,40,51}, :39:{27,38}] always @(posedge)
Generate the Verilog code corresponding to this FIRRTL code module PE_457 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_201 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<8>, clock reg c2 : SInt<8>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h0), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node _c1_T = bits(io.in_d, 7, 0) node _c1_T_1 = asSInt(_c1_T) connect c1, _c1_T_1 else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node _c2_T = bits(io.in_d, 7, 0) node _c2_T_1 = asSInt(_c2_T) connect c2, _c2_T_1 else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h0), _T_4) node _T_6 = or(UInt<1>(0h1), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c	module PE_457( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid // @[PE.scala:35:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7] wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60] wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [7:0] c1; // @[PE.scala:70:15] wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [7:0] c2; // @[PE.scala:71:15] wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = \|_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros \| io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = \|_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 \| io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}] wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16] wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8] c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15] if (~(~io_in_valid_0 \| io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8] c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15] if (io_in_valid_0) // @[PE.scala:31:7] last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] always @(posedge) MacUnit_201 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_b_0), // @[PE.scala:31:7] .io_out_d (io_out_b_0) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_43 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_sink_valid of AsyncResetSynchronizerShiftReg_w1_d3_i0_56 connect io_out_sink_valid.clock, clock connect io_out_sink_valid.reset, reset connect io_out_sink_valid.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_sink_valid.io.q connect io.out, _io_out_WIRE	module AsyncValidSync_43( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_56 io_out_sink_valid ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_101 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T node _is_aligned_mask_T = dshl(UInt<2>(0h3), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 1, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<2>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 0, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 1, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h2)) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(UInt<1>(0h1), mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(UInt<1>(0h1), mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_lo = cat(mask_acc_1, mask_acc) node mask_hi = cat(mask_acc_3, mask_acc_2) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_15 : node _T_16 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_17 = and(UInt<1>(0h0), _T_16) node _T_18 = or(UInt<1>(0h0), _T_17) node _T_19 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_20 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_21 = cvt(_T_20) node _T_22 = and(_T_21, asSInt(UInt<7>(0h40))) node _T_23 = asSInt(_T_22) node _T_24 = eq(_T_23, asSInt(UInt<1>(0h0))) node _T_25 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_26 = cvt(_T_25) node _T_27 = and(_T_26, asSInt(UInt<5>(0h14))) node _T_28 = asSInt(_T_27) node _T_29 = eq(_T_28, asSInt(UInt<1>(0h0))) node _T_30 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_31 = cvt(_T_30) node _T_32 = and(_T_31, asSInt(UInt<4>(0h8))) node _T_33 = asSInt(_T_32) node _T_34 = eq(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_36 = cvt(_T_35) node _T_37 = and(_T_36, asSInt(UInt<6>(0h20))) node _T_38 = asSInt(_T_37) node _T_39 = eq(_T_38, asSInt(UInt<1>(0h0))) node _T_40 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_41 = cvt(_T_40) node _T_42 = and(_T_41, asSInt(UInt<8>(0h80))) node _T_43 = asSInt(_T_42) node _T_44 = eq(_T_43, asSInt(UInt<1>(0h0))) node _T_45 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<9>(0h100))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_24, _T_29) node _T_51 = or(_T_50, _T_34) node _T_52 = or(_T_51, _T_39) node _T_53 = or(_T_52, _T_44) node _T_54 = or(_T_53, _T_49) node _T_55 = and(_T_19, _T_54) node _T_56 = or(UInt<1>(0h0), _T_55) node _T_57 = and(_T_18, _T_56) node _T_58 = asUInt(reset) node _T_59 = eq(_T_58, UInt<1>(0h0)) when _T_59 : node _T_60 = eq(_T_57, UInt<1>(0h0)) when _T_60 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_57, UInt<1>(0h1), "") : assert_2 node _T_61 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_62 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_63 = and(_T_61, _T_62) node _T_64 = or(UInt<1>(0h0), _T_63) node _T_65 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_66 = cvt(_T_65) node _T_67 = and(_T_66, asSInt(UInt<7>(0h40))) node _T_68 = asSInt(_T_67) node _T_69 = eq(_T_68, asSInt(UInt<1>(0h0))) node _T_70 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_71 = cvt(_T_70) node _T_72 = and(_T_71, asSInt(UInt<5>(0h14))) node _T_73 = asSInt(_T_72) node _T_74 = eq(_T_73, asSInt(UInt<1>(0h0))) node _T_75 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_76 = cvt(_T_75) node _T_77 = and(_T_76, asSInt(UInt<4>(0h8))) node _T_78 = asSInt(_T_77) node _T_79 = eq(_T_78, asSInt(UInt<1>(0h0))) node _T_80 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_81 = cvt(_T_80) node _T_82 = and(_T_81, asSInt(UInt<6>(0h20))) node _T_83 = asSInt(_T_82) node _T_84 = eq(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_86 = cvt(_T_85) node _T_87 = and(_T_86, asSInt(UInt<8>(0h80))) node _T_88 = asSInt(_T_87) node _T_89 = eq(_T_88, asSInt(UInt<1>(0h0))) node _T_90 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<9>(0h100))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_69, _T_74) node _T_96 = or(_T_95, _T_79) node _T_97 = or(_T_96, _T_84) node _T_98 = or(_T_97, _T_89) node _T_99 = or(_T_98, _T_94) node _T_100 = and(_T_64, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(UInt<1>(0h0), _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_102, UInt<1>(0h1), "") : assert_3 node _T_106 = asUInt(reset) node _T_107 = eq(_T_106, UInt<1>(0h0)) when _T_107 : node _T_108 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_108 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_109 = geq(io.in.a.bits.size, UInt<2>(0h2)) node _T_110 = asUInt(reset) node _T_111 = eq(_T_110, UInt<1>(0h0)) when _T_111 : node _T_112 = eq(_T_109, UInt<1>(0h0)) when _T_112 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_109, UInt<1>(0h1), "") : assert_5 node _T_113 = asUInt(reset) node _T_114 = eq(_T_113, UInt<1>(0h0)) when _T_114 : node _T_115 = eq(is_aligned, UInt<1>(0h0)) when _T_115 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_116 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_117 = asUInt(reset) node _T_118 = eq(_T_117, UInt<1>(0h0)) when _T_118 : node _T_119 = eq(_T_116, UInt<1>(0h0)) when _T_119 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_116, UInt<1>(0h1), "") : assert_7 node _T_120 = not(io.in.a.bits.mask) node _T_121 = eq(_T_120, UInt<1>(0h0)) node _T_122 = asUInt(reset) node _T_123 = eq(_T_122, UInt<1>(0h0)) when _T_123 : node _T_124 = eq(_T_121, UInt<1>(0h0)) when _T_124 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_121, UInt<1>(0h1), "") : assert_8 node _T_125 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_126 = asUInt(reset) node _T_127 = eq(_T_126, UInt<1>(0h0)) when _T_127 : node _T_128 = eq(_T_125, UInt<1>(0h0)) when _T_128 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_125, UInt<1>(0h1), "") : assert_9 node _T_129 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_129 : node _T_130 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_131 = and(UInt<1>(0h0), _T_130) node _T_132 = or(UInt<1>(0h0), _T_131) node _T_133 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_134 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_135 = cvt(_T_134) node _T_136 = and(_T_135, asSInt(UInt<7>(0h40))) node _T_137 = asSInt(_T_136) node _T_138 = eq(_T_137, asSInt(UInt<1>(0h0))) node _T_139 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_140 = cvt(_T_139) node _T_141 = and(_T_140, asSInt(UInt<5>(0h14))) node _T_142 = asSInt(_T_141) node _T_143 = eq(_T_142, asSInt(UInt<1>(0h0))) node _T_144 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_145 = cvt(_T_144) node _T_146 = and(_T_145, asSInt(UInt<4>(0h8))) node _T_147 = asSInt(_T_146) node _T_148 = eq(_T_147, asSInt(UInt<1>(0h0))) node _T_149 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_150 = cvt(_T_149) node _T_151 = and(_T_150, asSInt(UInt<6>(0h20))) node _T_152 = asSInt(_T_151) node _T_153 = eq(_T_152, asSInt(UInt<1>(0h0))) node _T_154 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_155 = cvt(_T_154) node _T_156 = and(_T_155, asSInt(UInt<8>(0h80))) node _T_157 = asSInt(_T_156) node _T_158 = eq(_T_157, asSInt(UInt<1>(0h0))) node _T_159 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_160 = cvt(_T_159) node _T_161 = and(_T_160, asSInt(UInt<9>(0h100))) node _T_162 = asSInt(_T_161) node _T_163 = eq(_T_162, asSInt(UInt<1>(0h0))) node _T_164 = or(_T_138, _T_143) node _T_165 = or(_T_164, _T_148) node _T_166 = or(_T_165, _T_153) node _T_167 = or(_T_166, _T_158) node _T_168 = or(_T_167, _T_163) node _T_169 = and(_T_133, _T_168) node _T_170 = or(UInt<1>(0h0), _T_169) node _T_171 = and(_T_132, _T_170) node _T_172 = asUInt(reset) node _T_173 = eq(_T_172, UInt<1>(0h0)) when _T_173 : node _T_174 = eq(_T_171, UInt<1>(0h0)) when _T_174 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_171, UInt<1>(0h1), "") : assert_10 node _T_175 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_176 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_177 = and(_T_175, _T_176) node _T_178 = or(UInt<1>(0h0), _T_177) node _T_179 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_180 = cvt(_T_179) node _T_181 = and(_T_180, asSInt(UInt<7>(0h40))) node _T_182 = asSInt(_T_181) node _T_183 = eq(_T_182, asSInt(UInt<1>(0h0))) node _T_184 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_185 = cvt(_T_184) node _T_186 = and(_T_185, asSInt(UInt<5>(0h14))) node _T_187 = asSInt(_T_186) node _T_188 = eq(_T_187, asSInt(UInt<1>(0h0))) node _T_189 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_190 = cvt(_T_189) node _T_191 = and(_T_190, asSInt(UInt<4>(0h8))) node _T_192 = asSInt(_T_191) node _T_193 = eq(_T_192, asSInt(UInt<1>(0h0))) node _T_194 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_195 = cvt(_T_194) node _T_196 = and(_T_195, asSInt(UInt<6>(0h20))) node _T_197 = asSInt(_T_196) node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0))) node _T_199 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_200 = cvt(_T_199) node _T_201 = and(_T_200, asSInt(UInt<8>(0h80))) node _T_202 = asSInt(_T_201) node _T_203 = eq(_T_202, asSInt(UInt<1>(0h0))) node _T_204 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_205 = cvt(_T_204) node _T_206 = and(_T_205, asSInt(UInt<9>(0h100))) node _T_207 = asSInt(_T_206) node _T_208 = eq(_T_207, asSInt(UInt<1>(0h0))) node _T_209 = or(_T_183, _T_188) node _T_210 = or(_T_209, _T_193) node _T_211 = or(_T_210, _T_198) node _T_212 = or(_T_211, _T_203) node _T_213 = or(_T_212, _T_208) node _T_214 = and(_T_178, _T_213) node _T_215 = or(UInt<1>(0h0), _T_214) node _T_216 = and(UInt<1>(0h0), _T_215) node _T_217 = asUInt(reset) node _T_218 = eq(_T_217, UInt<1>(0h0)) when _T_218 : node _T_219 = eq(_T_216, UInt<1>(0h0)) when _T_219 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_216, UInt<1>(0h1), "") : assert_11 node _T_220 = asUInt(reset) node _T_221 = eq(_T_220, UInt<1>(0h0)) when _T_221 : node _T_222 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_222 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_223 = geq(io.in.a.bits.size, UInt<2>(0h2)) node _T_224 = asUInt(reset) node _T_225 = eq(_T_224, UInt<1>(0h0)) when _T_225 : node _T_226 = eq(_T_223, UInt<1>(0h0)) when _T_226 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_223, UInt<1>(0h1), "") : assert_13 node _T_227 = asUInt(reset) node _T_228 = eq(_T_227, UInt<1>(0h0)) when _T_228 : node _T_229 = eq(is_aligned, UInt<1>(0h0)) when _T_229 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_230 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_231 = asUInt(reset) node _T_232 = eq(_T_231, UInt<1>(0h0)) when _T_232 : node _T_233 = eq(_T_230, UInt<1>(0h0)) when _T_233 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_230, UInt<1>(0h1), "") : assert_15 node _T_234 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_235 = asUInt(reset) node _T_236 = eq(_T_235, UInt<1>(0h0)) when _T_236 : node _T_237 = eq(_T_234, UInt<1>(0h0)) when _T_237 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_234, UInt<1>(0h1), "") : assert_16 node _T_238 = not(io.in.a.bits.mask) node _T_239 = eq(_T_238, UInt<1>(0h0)) node _T_240 = asUInt(reset) node _T_241 = eq(_T_240, UInt<1>(0h0)) when _T_241 : node _T_242 = eq(_T_239, UInt<1>(0h0)) when _T_242 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_239, UInt<1>(0h1), "") : assert_17 node _T_243 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_244 = asUInt(reset) node _T_245 = eq(_T_244, UInt<1>(0h0)) when _T_245 : node _T_246 = eq(_T_243, UInt<1>(0h0)) when _T_246 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_243, UInt<1>(0h1), "") : assert_18 node _T_247 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_247 : node _T_248 = eq(UInt<2>(0h2), io.in.a.bits.size) node _T_249 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = asUInt(reset) node _T_253 = eq(_T_252, UInt<1>(0h0)) when _T_253 : node _T_254 = eq(_T_251, UInt<1>(0h0)) when _T_254 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_251, UInt<1>(0h1), "") : assert_19 node _T_255 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_256 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_257 = and(_T_255, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_260 = cvt(_T_259) node _T_261 = and(_T_260, asSInt(UInt<7>(0h40))) node _T_262 = asSInt(_T_261) node _T_263 = eq(_T_262, asSInt(UInt<1>(0h0))) node _T_264 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_265 = cvt(_T_264) node _T_266 = and(_T_265, asSInt(UInt<5>(0h14))) node _T_267 = asSInt(_T_266) node _T_268 = eq(_T_267, asSInt(UInt<1>(0h0))) node _T_269 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_270 = cvt(_T_269) node _T_271 = and(_T_270, asSInt(UInt<4>(0h8))) node _T_272 = asSInt(_T_271) node _T_273 = eq(_T_272, asSInt(UInt<1>(0h0))) node _T_274 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_275 = cvt(_T_274) node _T_276 = and(_T_275, asSInt(UInt<6>(0h20))) node _T_277 = asSInt(_T_276) node _T_278 = eq(_T_277, asSInt(UInt<1>(0h0))) node _T_279 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_280 = cvt(_T_279) node _T_281 = and(_T_280, asSInt(UInt<8>(0h80))) node _T_282 = asSInt(_T_281) node _T_283 = eq(_T_282, asSInt(UInt<1>(0h0))) node _T_284 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_285 = cvt(_T_284) node _T_286 = and(_T_285, asSInt(UInt<9>(0h100))) node _T_287 = asSInt(_T_286) node _T_288 = eq(_T_287, asSInt(UInt<1>(0h0))) node _T_289 = or(_T_263, _T_268) node _T_290 = or(_T_289, _T_273) node _T_291 = or(_T_290, _T_278) node _T_292 = or(_T_291, _T_283) node _T_293 = or(_T_292, _T_288) node _T_294 = and(_T_258, _T_293) node _T_295 = or(UInt<1>(0h0), _T_294) node _T_296 = asUInt(reset) node _T_297 = eq(_T_296, UInt<1>(0h0)) when _T_297 : node _T_298 = eq(_T_295, UInt<1>(0h0)) when _T_298 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_295, UInt<1>(0h1), "") : assert_20 node _T_299 = asUInt(reset) node _T_300 = eq(_T_299, UInt<1>(0h0)) when _T_300 : node _T_301 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_301 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_302 = asUInt(reset) node _T_303 = eq(_T_302, UInt<1>(0h0)) when _T_303 : node _T_304 = eq(is_aligned, UInt<1>(0h0)) when _T_304 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_305 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(_T_305, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_305, UInt<1>(0h1), "") : assert_23 node _T_309 = eq(io.in.a.bits.mask, mask) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_309, UInt<1>(0h1), "") : assert_24 node _T_313 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_313, UInt<1>(0h1), "") : assert_25 node _T_317 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_317 : node _T_318 = eq(UInt<2>(0h2), io.in.a.bits.size) node _T_319 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_320 = and(_T_318, _T_319) node _T_321 = or(UInt<1>(0h0), _T_320) node _T_322 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_323 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_324 = and(_T_322, _T_323) node _T_325 = or(UInt<1>(0h0), _T_324) node _T_326 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_327 = cvt(_T_326) node _T_328 = and(_T_327, asSInt(UInt<7>(0h40))) node _T_329 = asSInt(_T_328) node _T_330 = eq(_T_329, asSInt(UInt<1>(0h0))) node _T_331 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_332 = cvt(_T_331) node _T_333 = and(_T_332, asSInt(UInt<5>(0h14))) node _T_334 = asSInt(_T_333) node _T_335 = eq(_T_334, asSInt(UInt<1>(0h0))) node _T_336 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_337 = cvt(_T_336) node _T_338 = and(_T_337, asSInt(UInt<4>(0h8))) node _T_339 = asSInt(_T_338) node _T_340 = eq(_T_339, asSInt(UInt<1>(0h0))) node _T_341 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_342 = cvt(_T_341) node _T_343 = and(_T_342, asSInt(UInt<6>(0h20))) node _T_344 = asSInt(_T_343) node _T_345 = eq(_T_344, asSInt(UInt<1>(0h0))) node _T_346 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_347 = cvt(_T_346) node _T_348 = and(_T_347, asSInt(UInt<8>(0h80))) node _T_349 = asSInt(_T_348) node _T_350 = eq(_T_349, asSInt(UInt<1>(0h0))) node _T_351 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_352 = cvt(_T_351) node _T_353 = and(_T_352, asSInt(UInt<9>(0h100))) node _T_354 = asSInt(_T_353) node _T_355 = eq(_T_354, asSInt(UInt<1>(0h0))) node _T_356 = or(_T_330, _T_335) node _T_357 = or(_T_356, _T_340) node _T_358 = or(_T_357, _T_345) node _T_359 = or(_T_358, _T_350) node _T_360 = or(_T_359, _T_355) node _T_361 = and(_T_325, _T_360) node _T_362 = or(UInt<1>(0h0), _T_361) node _T_363 = and(_T_321, _T_362) node _T_364 = asUInt(reset) node _T_365 = eq(_T_364, UInt<1>(0h0)) when _T_365 : node _T_366 = eq(_T_363, UInt<1>(0h0)) when _T_366 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_363, UInt<1>(0h1), "") : assert_26 node _T_367 = asUInt(reset) node _T_368 = eq(_T_367, UInt<1>(0h0)) when _T_368 : node _T_369 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_369 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_370 = asUInt(reset) node _T_371 = eq(_T_370, UInt<1>(0h0)) when _T_371 : node _T_372 = eq(is_aligned, UInt<1>(0h0)) when _T_372 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_373 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_374 = asUInt(reset) node _T_375 = eq(_T_374, UInt<1>(0h0)) when _T_375 : node _T_376 = eq(_T_373, UInt<1>(0h0)) when _T_376 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_373, UInt<1>(0h1), "") : assert_29 node _T_377 = eq(io.in.a.bits.mask, mask) node _T_378 = asUInt(reset) node _T_379 = eq(_T_378, UInt<1>(0h0)) when _T_379 : node _T_380 = eq(_T_377, UInt<1>(0h0)) when _T_380 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_377, UInt<1>(0h1), "") : assert_30 node _T_381 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_381 : node _T_382 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_383 = and(UInt<1>(0h0), _T_382) node _T_384 = or(UInt<1>(0h0), _T_383) node _T_385 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_386 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_387 = and(_T_385, _T_386) node _T_388 = or(UInt<1>(0h0), _T_387) node _T_389 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_390 = cvt(_T_389) node _T_391 = and(_T_390, asSInt(UInt<7>(0h40))) node _T_392 = asSInt(_T_391) node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0))) node _T_394 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_395 = cvt(_T_394) node _T_396 = and(_T_395, asSInt(UInt<5>(0h14))) node _T_397 = asSInt(_T_396) node _T_398 = eq(_T_397, asSInt(UInt<1>(0h0))) node _T_399 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_400 = cvt(_T_399) node _T_401 = and(_T_400, asSInt(UInt<4>(0h8))) node _T_402 = asSInt(_T_401) node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0))) node _T_404 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_405 = cvt(_T_404) node _T_406 = and(_T_405, asSInt(UInt<6>(0h20))) node _T_407 = asSInt(_T_406) node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0))) node _T_409 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_410 = cvt(_T_409) node _T_411 = and(_T_410, asSInt(UInt<8>(0h80))) node _T_412 = asSInt(_T_411) node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0))) node _T_414 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_415 = cvt(_T_414) node _T_416 = and(_T_415, asSInt(UInt<9>(0h100))) node _T_417 = asSInt(_T_416) node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0))) node _T_419 = or(_T_393, _T_398) node _T_420 = or(_T_419, _T_403) node _T_421 = or(_T_420, _T_408) node _T_422 = or(_T_421, _T_413) node _T_423 = or(_T_422, _T_418) node _T_424 = and(_T_388, _T_423) node _T_425 = or(UInt<1>(0h0), _T_424) node _T_426 = and(_T_384, _T_425) node _T_427 = asUInt(reset) node _T_428 = eq(_T_427, UInt<1>(0h0)) when _T_428 : node _T_429 = eq(_T_426, UInt<1>(0h0)) when _T_429 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_426, UInt<1>(0h1), "") : assert_31 node _T_430 = asUInt(reset) node _T_431 = eq(_T_430, UInt<1>(0h0)) when _T_431 : node _T_432 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_432 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(is_aligned, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_436 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_436, UInt<1>(0h1), "") : assert_34 node _T_440 = not(mask) node _T_441 = and(io.in.a.bits.mask, _T_440) node _T_442 = eq(_T_441, UInt<1>(0h0)) node _T_443 = asUInt(reset) node _T_444 = eq(_T_443, UInt<1>(0h0)) when _T_444 : node _T_445 = eq(_T_442, UInt<1>(0h0)) when _T_445 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_442, UInt<1>(0h1), "") : assert_35 node _T_446 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_446 : node _T_447 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_448 = and(UInt<1>(0h0), _T_447) node _T_449 = or(UInt<1>(0h0), _T_448) node _T_450 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_451 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_452 = cvt(_T_451) node _T_453 = and(_T_452, asSInt(UInt<7>(0h40))) node _T_454 = asSInt(_T_453) node _T_455 = eq(_T_454, asSInt(UInt<1>(0h0))) node _T_456 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_457 = cvt(_T_456) node _T_458 = and(_T_457, asSInt(UInt<5>(0h14))) node _T_459 = asSInt(_T_458) node _T_460 = eq(_T_459, asSInt(UInt<1>(0h0))) node _T_461 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_462 = cvt(_T_461) node _T_463 = and(_T_462, asSInt(UInt<4>(0h8))) node _T_464 = asSInt(_T_463) node _T_465 = eq(_T_464, asSInt(UInt<1>(0h0))) node _T_466 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_467 = cvt(_T_466) node _T_468 = and(_T_467, asSInt(UInt<6>(0h20))) node _T_469 = asSInt(_T_468) node _T_470 = eq(_T_469, asSInt(UInt<1>(0h0))) node _T_471 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_472 = cvt(_T_471) node _T_473 = and(_T_472, asSInt(UInt<8>(0h80))) node _T_474 = asSInt(_T_473) node _T_475 = eq(_T_474, asSInt(UInt<1>(0h0))) node _T_476 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_477 = cvt(_T_476) node _T_478 = and(_T_477, asSInt(UInt<9>(0h100))) node _T_479 = asSInt(_T_478) node _T_480 = eq(_T_479, asSInt(UInt<1>(0h0))) node _T_481 = or(_T_455, _T_460) node _T_482 = or(_T_481, _T_465) node _T_483 = or(_T_482, _T_470) node _T_484 = or(_T_483, _T_475) node _T_485 = or(_T_484, _T_480) node _T_486 = and(_T_450, _T_485) node _T_487 = or(UInt<1>(0h0), _T_486) node _T_488 = and(_T_449, _T_487) node _T_489 = asUInt(reset) node _T_490 = eq(_T_489, UInt<1>(0h0)) when _T_490 : node _T_491 = eq(_T_488, UInt<1>(0h0)) when _T_491 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_488, UInt<1>(0h1), "") : assert_36 node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_495 = asUInt(reset) node _T_496 = eq(_T_495, UInt<1>(0h0)) when _T_496 : node _T_497 = eq(is_aligned, UInt<1>(0h0)) when _T_497 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_498 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_499 = asUInt(reset) node _T_500 = eq(_T_499, UInt<1>(0h0)) when _T_500 : node _T_501 = eq(_T_498, UInt<1>(0h0)) when _T_501 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_498, UInt<1>(0h1), "") : assert_39 node _T_502 = eq(io.in.a.bits.mask, mask) node _T_503 = asUInt(reset) node _T_504 = eq(_T_503, UInt<1>(0h0)) when _T_504 : node _T_505 = eq(_T_502, UInt<1>(0h0)) when _T_505 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_502, UInt<1>(0h1), "") : assert_40 node _T_506 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_506 : node _T_507 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_508 = and(UInt<1>(0h0), _T_507) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_511 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_512 = cvt(_T_511) node _T_513 = and(_T_512, asSInt(UInt<7>(0h40))) node _T_514 = asSInt(_T_513) node _T_515 = eq(_T_514, asSInt(UInt<1>(0h0))) node _T_516 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_517 = cvt(_T_516) node _T_518 = and(_T_517, asSInt(UInt<5>(0h14))) node _T_519 = asSInt(_T_518) node _T_520 = eq(_T_519, asSInt(UInt<1>(0h0))) node _T_521 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_522 = cvt(_T_521) node _T_523 = and(_T_522, asSInt(UInt<4>(0h8))) node _T_524 = asSInt(_T_523) node _T_525 = eq(_T_524, asSInt(UInt<1>(0h0))) node _T_526 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_527 = cvt(_T_526) node _T_528 = and(_T_527, asSInt(UInt<6>(0h20))) node _T_529 = asSInt(_T_528) node _T_530 = eq(_T_529, asSInt(UInt<1>(0h0))) node _T_531 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_532 = cvt(_T_531) node _T_533 = and(_T_532, asSInt(UInt<8>(0h80))) node _T_534 = asSInt(_T_533) node _T_535 = eq(_T_534, asSInt(UInt<1>(0h0))) node _T_536 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_537 = cvt(_T_536) node _T_538 = and(_T_537, asSInt(UInt<9>(0h100))) node _T_539 = asSInt(_T_538) node _T_540 = eq(_T_539, asSInt(UInt<1>(0h0))) node _T_541 = or(_T_515, _T_520) node _T_542 = or(_T_541, _T_525) node _T_543 = or(_T_542, _T_530) node _T_544 = or(_T_543, _T_535) node _T_545 = or(_T_544, _T_540) node _T_546 = and(_T_510, _T_545) node _T_547 = or(UInt<1>(0h0), _T_546) node _T_548 = and(_T_509, _T_547) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_548, UInt<1>(0h1), "") : assert_41 node _T_552 = asUInt(reset) node _T_553 = eq(_T_552, UInt<1>(0h0)) when _T_553 : node _T_554 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_554 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_555 = asUInt(reset) node _T_556 = eq(_T_555, UInt<1>(0h0)) when _T_556 : node _T_557 = eq(is_aligned, UInt<1>(0h0)) when _T_557 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_558 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_559 = asUInt(reset) node _T_560 = eq(_T_559, UInt<1>(0h0)) when _T_560 : node _T_561 = eq(_T_558, UInt<1>(0h0)) when _T_561 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_558, UInt<1>(0h1), "") : assert_44 node _T_562 = eq(io.in.a.bits.mask, mask) node _T_563 = asUInt(reset) node _T_564 = eq(_T_563, UInt<1>(0h0)) when _T_564 : node _T_565 = eq(_T_562, UInt<1>(0h0)) when _T_565 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_562, UInt<1>(0h1), "") : assert_45 node _T_566 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_566 : node _T_567 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_568 = and(UInt<1>(0h0), _T_567) node _T_569 = or(UInt<1>(0h0), _T_568) node _T_570 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_571 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_572 = cvt(_T_571) node _T_573 = and(_T_572, asSInt(UInt<7>(0h40))) node _T_574 = asSInt(_T_573) node _T_575 = eq(_T_574, asSInt(UInt<1>(0h0))) node _T_576 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_577 = cvt(_T_576) node _T_578 = and(_T_577, asSInt(UInt<5>(0h14))) node _T_579 = asSInt(_T_578) node _T_580 = eq(_T_579, asSInt(UInt<1>(0h0))) node _T_581 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_582 = cvt(_T_581) node _T_583 = and(_T_582, asSInt(UInt<4>(0h8))) node _T_584 = asSInt(_T_583) node _T_585 = eq(_T_584, asSInt(UInt<1>(0h0))) node _T_586 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_587 = cvt(_T_586) node _T_588 = and(_T_587, asSInt(UInt<6>(0h20))) node _T_589 = asSInt(_T_588) node _T_590 = eq(_T_589, asSInt(UInt<1>(0h0))) node _T_591 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_592 = cvt(_T_591) node _T_593 = and(_T_592, asSInt(UInt<8>(0h80))) node _T_594 = asSInt(_T_593) node _T_595 = eq(_T_594, asSInt(UInt<1>(0h0))) node _T_596 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_597 = cvt(_T_596) node _T_598 = and(_T_597, asSInt(UInt<9>(0h100))) node _T_599 = asSInt(_T_598) node _T_600 = eq(_T_599, asSInt(UInt<1>(0h0))) node _T_601 = or(_T_575, _T_580) node _T_602 = or(_T_601, _T_585) node _T_603 = or(_T_602, _T_590) node _T_604 = or(_T_603, _T_595) node _T_605 = or(_T_604, _T_600) node _T_606 = and(_T_570, _T_605) node _T_607 = or(UInt<1>(0h0), _T_606) node _T_608 = and(_T_569, _T_607) node _T_609 = asUInt(reset) node _T_610 = eq(_T_609, UInt<1>(0h0)) when _T_610 : node _T_611 = eq(_T_608, UInt<1>(0h0)) when _T_611 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_608, UInt<1>(0h1), "") : assert_46 node _T_612 = asUInt(reset) node _T_613 = eq(_T_612, UInt<1>(0h0)) when _T_613 : node _T_614 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_614 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_615 = asUInt(reset) node _T_616 = eq(_T_615, UInt<1>(0h0)) when _T_616 : node _T_617 = eq(is_aligned, UInt<1>(0h0)) when _T_617 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_618 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_619 = asUInt(reset) node _T_620 = eq(_T_619, UInt<1>(0h0)) when _T_620 : node _T_621 = eq(_T_618, UInt<1>(0h0)) when _T_621 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_618, UInt<1>(0h1), "") : assert_49 node _T_622 = eq(io.in.a.bits.mask, mask) node _T_623 = asUInt(reset) node _T_624 = eq(_T_623, UInt<1>(0h0)) when _T_624 : node _T_625 = eq(_T_622, UInt<1>(0h0)) when _T_625 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_622, UInt<1>(0h1), "") : assert_50 node _T_626 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_626, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_630 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_630, UInt<1>(0h1), "") : assert_52 node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_1 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_634 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_634 : node _T_635 = asUInt(reset) node _T_636 = eq(_T_635, UInt<1>(0h0)) when _T_636 : node _T_637 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_637 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_638 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_639 = asUInt(reset) node _T_640 = eq(_T_639, UInt<1>(0h0)) when _T_640 : node _T_641 = eq(_T_638, UInt<1>(0h0)) when _T_641 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_638, UInt<1>(0h1), "") : assert_54 node _T_642 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_643 = asUInt(reset) node _T_644 = eq(_T_643, UInt<1>(0h0)) when _T_644 : node _T_645 = eq(_T_642, UInt<1>(0h0)) when _T_645 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_642, UInt<1>(0h1), "") : assert_55 node _T_646 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_647 = asUInt(reset) node _T_648 = eq(_T_647, UInt<1>(0h0)) when _T_648 : node _T_649 = eq(_T_646, UInt<1>(0h0)) when _T_649 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_646, UInt<1>(0h1), "") : assert_56 node _T_650 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_651 = asUInt(reset) node _T_652 = eq(_T_651, UInt<1>(0h0)) when _T_652 : node _T_653 = eq(_T_650, UInt<1>(0h0)) when _T_653 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_650, UInt<1>(0h1), "") : assert_57 node _T_654 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_654 : node _T_655 = asUInt(reset) node _T_656 = eq(_T_655, UInt<1>(0h0)) when _T_656 : node _T_657 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_657 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_658 = asUInt(reset) node _T_659 = eq(_T_658, UInt<1>(0h0)) when _T_659 : node _T_660 = eq(sink_ok, UInt<1>(0h0)) when _T_660 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_661 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_662 = asUInt(reset) node _T_663 = eq(_T_662, UInt<1>(0h0)) when _T_663 : node _T_664 = eq(_T_661, UInt<1>(0h0)) when _T_664 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_661, UInt<1>(0h1), "") : assert_60 node _T_665 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_666 = asUInt(reset) node _T_667 = eq(_T_666, UInt<1>(0h0)) when _T_667 : node _T_668 = eq(_T_665, UInt<1>(0h0)) when _T_668 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_665, UInt<1>(0h1), "") : assert_61 node _T_669 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_670 = asUInt(reset) node _T_671 = eq(_T_670, UInt<1>(0h0)) when _T_671 : node _T_672 = eq(_T_669, UInt<1>(0h0)) when _T_672 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_669, UInt<1>(0h1), "") : assert_62 node _T_673 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_674 = asUInt(reset) node _T_675 = eq(_T_674, UInt<1>(0h0)) when _T_675 : node _T_676 = eq(_T_673, UInt<1>(0h0)) when _T_676 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_673, UInt<1>(0h1), "") : assert_63 node _T_677 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_678 = or(UInt<1>(0h0), _T_677) node _T_679 = asUInt(reset) node _T_680 = eq(_T_679, UInt<1>(0h0)) when _T_680 : node _T_681 = eq(_T_678, UInt<1>(0h0)) when _T_681 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_678, UInt<1>(0h1), "") : assert_64 node _T_682 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_682 : node _T_683 = asUInt(reset) node _T_684 = eq(_T_683, UInt<1>(0h0)) when _T_684 : node _T_685 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_685 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_686 = asUInt(reset) node _T_687 = eq(_T_686, UInt<1>(0h0)) when _T_687 : node _T_688 = eq(sink_ok, UInt<1>(0h0)) when _T_688 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_689 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_690 = asUInt(reset) node _T_691 = eq(_T_690, UInt<1>(0h0)) when _T_691 : node _T_692 = eq(_T_689, UInt<1>(0h0)) when _T_692 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_689, UInt<1>(0h1), "") : assert_67 node _T_693 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_694 = asUInt(reset) node _T_695 = eq(_T_694, UInt<1>(0h0)) when _T_695 : node _T_696 = eq(_T_693, UInt<1>(0h0)) when _T_696 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_693, UInt<1>(0h1), "") : assert_68 node _T_697 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_698 = asUInt(reset) node _T_699 = eq(_T_698, UInt<1>(0h0)) when _T_699 : node _T_700 = eq(_T_697, UInt<1>(0h0)) when _T_700 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_697, UInt<1>(0h1), "") : assert_69 node _T_701 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_702 = or(_T_701, io.in.d.bits.corrupt) node _T_703 = asUInt(reset) node _T_704 = eq(_T_703, UInt<1>(0h0)) when _T_704 : node _T_705 = eq(_T_702, UInt<1>(0h0)) when _T_705 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_702, UInt<1>(0h1), "") : assert_70 node _T_706 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_707 = or(UInt<1>(0h0), _T_706) node _T_708 = asUInt(reset) node _T_709 = eq(_T_708, UInt<1>(0h0)) when _T_709 : node _T_710 = eq(_T_707, UInt<1>(0h0)) when _T_710 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_707, UInt<1>(0h1), "") : assert_71 node _T_711 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_711 : node _T_712 = asUInt(reset) node _T_713 = eq(_T_712, UInt<1>(0h0)) when _T_713 : node _T_714 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_714 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_715 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_716 = asUInt(reset) node _T_717 = eq(_T_716, UInt<1>(0h0)) when _T_717 : node _T_718 = eq(_T_715, UInt<1>(0h0)) when _T_718 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_715, UInt<1>(0h1), "") : assert_73 node _T_719 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_720 = asUInt(reset) node _T_721 = eq(_T_720, UInt<1>(0h0)) when _T_721 : node _T_722 = eq(_T_719, UInt<1>(0h0)) when _T_722 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_719, UInt<1>(0h1), "") : assert_74 node _T_723 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_724 = or(UInt<1>(0h0), _T_723) node _T_725 = asUInt(reset) node _T_726 = eq(_T_725, UInt<1>(0h0)) when _T_726 : node _T_727 = eq(_T_724, UInt<1>(0h0)) when _T_727 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_724, UInt<1>(0h1), "") : assert_75 node _T_728 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_728 : node _T_729 = asUInt(reset) node _T_730 = eq(_T_729, UInt<1>(0h0)) when _T_730 : node _T_731 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_731 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_732 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_733 = asUInt(reset) node _T_734 = eq(_T_733, UInt<1>(0h0)) when _T_734 : node _T_735 = eq(_T_732, UInt<1>(0h0)) when _T_735 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_732, UInt<1>(0h1), "") : assert_77 node _T_736 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_737 = or(_T_736, io.in.d.bits.corrupt) node _T_738 = asUInt(reset) node _T_739 = eq(_T_738, UInt<1>(0h0)) when _T_739 : node _T_740 = eq(_T_737, UInt<1>(0h0)) when _T_740 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_737, UInt<1>(0h1), "") : assert_78 node _T_741 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_742 = or(UInt<1>(0h0), _T_741) node _T_743 = asUInt(reset) node _T_744 = eq(_T_743, UInt<1>(0h0)) when _T_744 : node _T_745 = eq(_T_742, UInt<1>(0h0)) when _T_745 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_742, UInt<1>(0h1), "") : assert_79 node _T_746 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_746 : node _T_747 = asUInt(reset) node _T_748 = eq(_T_747, UInt<1>(0h0)) when _T_748 : node _T_749 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_749 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_750 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_751 = asUInt(reset) node _T_752 = eq(_T_751, UInt<1>(0h0)) when _T_752 : node _T_753 = eq(_T_750, UInt<1>(0h0)) when _T_753 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_750, UInt<1>(0h1), "") : assert_81 node _T_754 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_755 = asUInt(reset) node _T_756 = eq(_T_755, UInt<1>(0h0)) when _T_756 : node _T_757 = eq(_T_754, UInt<1>(0h0)) when _T_757 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_754, UInt<1>(0h1), "") : assert_82 node _T_758 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_759 = or(UInt<1>(0h0), _T_758) node _T_760 = asUInt(reset) node _T_761 = eq(_T_760, UInt<1>(0h0)) when _T_761 : node _T_762 = eq(_T_759, UInt<1>(0h0)) when _T_762 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_759, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<32>(0h0) connect _WIRE.bits.mask, UInt<4>(0h0) connect _WIRE.bits.address, UInt<9>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_763 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_764 = asUInt(reset) node _T_765 = eq(_T_764, UInt<1>(0h0)) when _T_765 : node _T_766 = eq(_T_763, UInt<1>(0h0)) when _T_766 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_763, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<32>(0h0) connect _WIRE_2.bits.address, UInt<9>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_767 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_768 = asUInt(reset) node _T_769 = eq(_T_768, UInt<1>(0h0)) when _T_769 : node _T_770 = eq(_T_767, UInt<1>(0h0)) when _T_770 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_767, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_771 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_772 = asUInt(reset) node _T_773 = eq(_T_772, UInt<1>(0h0)) when _T_773 : node _T_774 = eq(_T_771, UInt<1>(0h0)) when _T_774 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_771, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 1, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 2) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_775 = eq(a_first, UInt<1>(0h0)) node _T_776 = and(io.in.a.valid, _T_775) when _T_776 : node _T_777 = eq(io.in.a.bits.opcode, opcode) node _T_778 = asUInt(reset) node _T_779 = eq(_T_778, UInt<1>(0h0)) when _T_779 : node _T_780 = eq(_T_777, UInt<1>(0h0)) when _T_780 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_777, UInt<1>(0h1), "") : assert_87 node _T_781 = eq(io.in.a.bits.param, param) node _T_782 = asUInt(reset) node _T_783 = eq(_T_782, UInt<1>(0h0)) when _T_783 : node _T_784 = eq(_T_781, UInt<1>(0h0)) when _T_784 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_781, UInt<1>(0h1), "") : assert_88 node _T_785 = eq(io.in.a.bits.size, size) node _T_786 = asUInt(reset) node _T_787 = eq(_T_786, UInt<1>(0h0)) when _T_787 : node _T_788 = eq(_T_785, UInt<1>(0h0)) when _T_788 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_785, UInt<1>(0h1), "") : assert_89 node _T_789 = eq(io.in.a.bits.source, source) node _T_790 = asUInt(reset) node _T_791 = eq(_T_790, UInt<1>(0h0)) when _T_791 : node _T_792 = eq(_T_789, UInt<1>(0h0)) when _T_792 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_789, UInt<1>(0h1), "") : assert_90 node _T_793 = eq(io.in.a.bits.address, address) node _T_794 = asUInt(reset) node _T_795 = eq(_T_794, UInt<1>(0h0)) when _T_795 : node _T_796 = eq(_T_793, UInt<1>(0h0)) when _T_796 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_793, UInt<1>(0h1), "") : assert_91 node _T_797 = and(io.in.a.ready, io.in.a.valid) node _T_798 = and(_T_797, a_first) when _T_798 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 1, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 2) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_799 = eq(d_first, UInt<1>(0h0)) node _T_800 = and(io.in.d.valid, _T_799) when _T_800 : node _T_801 = eq(io.in.d.bits.opcode, opcode_1) node _T_802 = asUInt(reset) node _T_803 = eq(_T_802, UInt<1>(0h0)) when _T_803 : node _T_804 = eq(_T_801, UInt<1>(0h0)) when _T_804 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_801, UInt<1>(0h1), "") : assert_92 node _T_805 = eq(io.in.d.bits.param, param_1) node _T_806 = asUInt(reset) node _T_807 = eq(_T_806, UInt<1>(0h0)) when _T_807 : node _T_808 = eq(_T_805, UInt<1>(0h0)) when _T_808 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_805, UInt<1>(0h1), "") : assert_93 node _T_809 = eq(io.in.d.bits.size, size_1) node _T_810 = asUInt(reset) node _T_811 = eq(_T_810, UInt<1>(0h0)) when _T_811 : node _T_812 = eq(_T_809, UInt<1>(0h0)) when _T_812 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_809, UInt<1>(0h1), "") : assert_94 node _T_813 = eq(io.in.d.bits.source, source_1) node _T_814 = asUInt(reset) node _T_815 = eq(_T_814, UInt<1>(0h0)) when _T_815 : node _T_816 = eq(_T_813, UInt<1>(0h0)) when _T_816 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_813, UInt<1>(0h1), "") : assert_95 node _T_817 = eq(io.in.d.bits.sink, sink) node _T_818 = asUInt(reset) node _T_819 = eq(_T_818, UInt<1>(0h0)) when _T_819 : node _T_820 = eq(_T_817, UInt<1>(0h0)) when _T_820 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_817, UInt<1>(0h1), "") : assert_96 node _T_821 = eq(io.in.d.bits.denied, denied) node _T_822 = asUInt(reset) node _T_823 = eq(_T_822, UInt<1>(0h0)) when _T_823 : node _T_824 = eq(_T_821, UInt<1>(0h0)) when _T_824 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_821, UInt<1>(0h1), "") : assert_97 node _T_825 = and(io.in.d.ready, io.in.d.valid) node _T_826 = and(_T_825, d_first) when _T_826 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes : UInt<4>, clock, reset, UInt<4>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 1, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 2) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 1, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 2) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1> connect a_set, UInt<1>(0h0) wire a_set_wo_ready : UInt<1> connect a_set_wo_ready, UInt<1>(0h0) wire a_opcodes_set : UInt<4> connect a_opcodes_set, UInt<4>(0h0) wire a_sizes_set : UInt<4> connect a_sizes_set, UInt<4>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_827 = and(io.in.a.valid, a_first_1) node _T_828 = and(_T_827, UInt<1>(0h1)) when _T_828 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_829 = and(io.in.a.ready, io.in.a.valid) node _T_830 = and(_T_829, a_first_1) node _T_831 = and(_T_830, UInt<1>(0h1)) when _T_831 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_832 = dshr(inflight, io.in.a.bits.source) node _T_833 = bits(_T_832, 0, 0) node _T_834 = eq(_T_833, UInt<1>(0h0)) node _T_835 = asUInt(reset) node _T_836 = eq(_T_835, UInt<1>(0h0)) when _T_836 : node _T_837 = eq(_T_834, UInt<1>(0h0)) when _T_837 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_834, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1> connect d_clr, UInt<1>(0h0) wire d_clr_wo_ready : UInt<1> connect d_clr_wo_ready, UInt<1>(0h0) wire d_opcodes_clr : UInt<4> connect d_opcodes_clr, UInt<4>(0h0) wire d_sizes_clr : UInt<4> connect d_sizes_clr, UInt<4>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_838 = and(io.in.d.valid, d_first_1) node _T_839 = and(_T_838, UInt<1>(0h1)) node _T_840 = eq(d_release_ack, UInt<1>(0h0)) node _T_841 = and(_T_839, _T_840) when _T_841 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_842 = and(io.in.d.ready, io.in.d.valid) node _T_843 = and(_T_842, d_first_1) node _T_844 = and(_T_843, UInt<1>(0h1)) node _T_845 = eq(d_release_ack, UInt<1>(0h0)) node _T_846 = and(_T_844, _T_845) when _T_846 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_847 = and(io.in.d.valid, d_first_1) node _T_848 = and(_T_847, UInt<1>(0h1)) node _T_849 = eq(d_release_ack, UInt<1>(0h0)) node _T_850 = and(_T_848, _T_849) when _T_850 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_851 = dshr(inflight, io.in.d.bits.source) node _T_852 = bits(_T_851, 0, 0) node _T_853 = or(_T_852, same_cycle_resp) node _T_854 = asUInt(reset) node _T_855 = eq(_T_854, UInt<1>(0h0)) when _T_855 : node _T_856 = eq(_T_853, UInt<1>(0h0)) when _T_856 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_853, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_857 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_858 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_859 = or(_T_857, _T_858) node _T_860 = asUInt(reset) node _T_861 = eq(_T_860, UInt<1>(0h0)) when _T_861 : node _T_862 = eq(_T_859, UInt<1>(0h0)) when _T_862 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_859, UInt<1>(0h1), "") : assert_100 node _T_863 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_864 = asUInt(reset) node _T_865 = eq(_T_864, UInt<1>(0h0)) when _T_865 : node _T_866 = eq(_T_863, UInt<1>(0h0)) when _T_866 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_863, UInt<1>(0h1), "") : assert_101 else : node _T_867 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_868 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_869 = or(_T_867, _T_868) node _T_870 = asUInt(reset) node _T_871 = eq(_T_870, UInt<1>(0h0)) when _T_871 : node _T_872 = eq(_T_869, UInt<1>(0h0)) when _T_872 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_869, UInt<1>(0h1), "") : assert_102 node _T_873 = eq(io.in.d.bits.size, a_size_lookup) node _T_874 = asUInt(reset) node _T_875 = eq(_T_874, UInt<1>(0h0)) when _T_875 : node _T_876 = eq(_T_873, UInt<1>(0h0)) when _T_876 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_873, UInt<1>(0h1), "") : assert_103 node _T_877 = and(io.in.d.valid, d_first_1) node _T_878 = and(_T_877, a_first_1) node _T_879 = and(_T_878, io.in.a.valid) node _T_880 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_881 = and(_T_879, _T_880) node _T_882 = eq(d_release_ack, UInt<1>(0h0)) node _T_883 = and(_T_881, _T_882) when _T_883 : node _T_884 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_885 = or(_T_884, io.in.a.ready) node _T_886 = asUInt(reset) node _T_887 = eq(_T_886, UInt<1>(0h0)) when _T_887 : node _T_888 = eq(_T_885, UInt<1>(0h0)) when _T_888 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_885, UInt<1>(0h1), "") : assert_104 node _T_889 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_890 = orr(a_set_wo_ready) node _T_891 = eq(_T_890, UInt<1>(0h0)) node _T_892 = or(_T_889, _T_891) node _T_893 = asUInt(reset) node _T_894 = eq(_T_893, UInt<1>(0h0)) when _T_894 : node _T_895 = eq(_T_892, UInt<1>(0h0)) when _T_895 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_892, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_203 node _T_896 = orr(inflight) node _T_897 = eq(_T_896, UInt<1>(0h0)) node _T_898 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_899 = or(_T_897, _T_898) node _T_900 = lt(watchdog, plusarg_reader.out) node _T_901 = or(_T_899, _T_900) node _T_902 = asUInt(reset) node _T_903 = eq(_T_902, UInt<1>(0h0)) when _T_903 : node _T_904 = eq(_T_901, UInt<1>(0h0)) when _T_904 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_901, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_905 = and(io.in.a.ready, io.in.a.valid) node _T_906 = and(io.in.d.ready, io.in.d.valid) node _T_907 = or(_T_905, _T_906) when _T_907 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes_1 : UInt<4>, clock, reset, UInt<4>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<32>(0h0) connect _c_first_WIRE.bits.address, UInt<9>(0h0) connect _c_first_WIRE.bits.source, UInt<1>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<32>(0h0) connect _c_first_WIRE_2.bits.address, UInt<9>(0h0) connect _c_first_WIRE_2.bits.source, UInt<1>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<2>(0h3), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 1, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 2) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 1, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 2) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1> connect c_set, UInt<1>(0h0) wire c_set_wo_ready : UInt<1> connect c_set_wo_ready, UInt<1>(0h0) wire c_opcodes_set : UInt<4> connect c_opcodes_set, UInt<4>(0h0) wire c_sizes_set : UInt<4> connect c_sizes_set, UInt<4>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<32>(0h0) connect _WIRE_6.bits.address, UInt<9>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_908 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<32>(0h0) connect _WIRE_8.bits.address, UInt<9>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_909 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_910 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_911 = and(_T_909, _T_910) node _T_912 = and(_T_908, _T_911) when _T_912 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<9>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<32>(0h0) connect _WIRE_10.bits.address, UInt<9>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_913 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_914 = and(_T_913, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<32>(0h0) connect _WIRE_12.bits.address, UInt<9>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_915 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_916 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_917 = and(_T_915, _T_916) node _T_918 = and(_T_914, _T_917) when _T_918 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<32>(0h0) connect _c_set_WIRE.bits.address, UInt<9>(0h0) connect _c_set_WIRE.bits.source, UInt<1>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<9>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<9>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<9>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<9>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<32>(0h0) connect _WIRE_14.bits.address, UInt<9>(0h0) connect _WIRE_14.bits.source, UInt<1>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_919 = dshr(inflight_1, _WIRE_15.bits.source) node _T_920 = bits(_T_919, 0, 0) node _T_921 = eq(_T_920, UInt<1>(0h0)) node _T_922 = asUInt(reset) node _T_923 = eq(_T_922, UInt<1>(0h0)) when _T_923 : node _T_924 = eq(_T_921, UInt<1>(0h0)) when _T_924 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_921, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<9>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<9>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1> connect d_clr_1, UInt<1>(0h0) wire d_clr_wo_ready_1 : UInt<1> connect d_clr_wo_ready_1, UInt<1>(0h0) wire d_opcodes_clr_1 : UInt<4> connect d_opcodes_clr_1, UInt<4>(0h0) wire d_sizes_clr_1 : UInt<4> connect d_sizes_clr_1, UInt<4>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_925 = and(io.in.d.valid, d_first_2) node _T_926 = and(_T_925, UInt<1>(0h1)) node _T_927 = and(_T_926, d_release_ack_1) when _T_927 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_928 = and(io.in.d.ready, io.in.d.valid) node _T_929 = and(_T_928, d_first_2) node _T_930 = and(_T_929, UInt<1>(0h1)) node _T_931 = and(_T_930, d_release_ack_1) when _T_931 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_932 = and(io.in.d.valid, d_first_2) node _T_933 = and(_T_932, UInt<1>(0h1)) node _T_934 = and(_T_933, d_release_ack_1) when _T_934 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<9>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<9>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<9>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_935 = dshr(inflight_1, io.in.d.bits.source) node _T_936 = bits(_T_935, 0, 0) node _T_937 = or(_T_936, same_cycle_resp_1) node _T_938 = asUInt(reset) node _T_939 = eq(_T_938, UInt<1>(0h0)) when _T_939 : node _T_940 = eq(_T_937, UInt<1>(0h0)) when _T_940 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_937, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<32>(0h0) connect _WIRE_16.bits.address, UInt<9>(0h0) connect _WIRE_16.bits.source, UInt<1>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_941 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_942 = asUInt(reset) node _T_943 = eq(_T_942, UInt<1>(0h0)) when _T_943 : node _T_944 = eq(_T_941, UInt<1>(0h0)) when _T_944 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_941, UInt<1>(0h1), "") : assert_109 else : node _T_945 = eq(io.in.d.bits.size, c_size_lookup) node _T_946 = asUInt(reset) node _T_947 = eq(_T_946, UInt<1>(0h0)) when _T_947 : node _T_948 = eq(_T_945, UInt<1>(0h0)) when _T_948 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_945, UInt<1>(0h1), "") : assert_110 node _T_949 = and(io.in.d.valid, d_first_2) node _T_950 = and(_T_949, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<32>(0h0) connect _WIRE_18.bits.address, UInt<9>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_951 = and(_T_950, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<32>(0h0) connect _WIRE_20.bits.address, UInt<9>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_952 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_953 = and(_T_951, _T_952) node _T_954 = and(_T_953, d_release_ack_1) node _T_955 = eq(c_probe_ack, UInt<1>(0h0)) node _T_956 = and(_T_954, _T_955) when _T_956 : node _T_957 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<32>(0h0) connect _WIRE_22.bits.address, UInt<9>(0h0) connect _WIRE_22.bits.source, UInt<1>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_958 = or(_T_957, _WIRE_23.ready) node _T_959 = asUInt(reset) node _T_960 = eq(_T_959, UInt<1>(0h0)) when _T_960 : node _T_961 = eq(_T_958, UInt<1>(0h0)) when _T_961 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_958, UInt<1>(0h1), "") : assert_111 node _T_962 = orr(c_set_wo_ready) when _T_962 : node _T_963 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_964 = asUInt(reset) node _T_965 = eq(_T_964, UInt<1>(0h0)) when _T_965 : node _T_966 = eq(_T_963, UInt<1>(0h0)) when _T_966 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_963, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_204 node _T_967 = orr(inflight_1) node _T_968 = eq(_T_967, UInt<1>(0h0)) node _T_969 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_970 = or(_T_968, _T_969) node _T_971 = lt(watchdog_1, plusarg_reader_1.out) node _T_972 = or(_T_970, _T_971) node _T_973 = asUInt(reset) node _T_974 = eq(_T_973, UInt<1>(0h0)) when _T_974 : node _T_975 = eq(_T_972, UInt<1>(0h0)) when _T_975 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_972, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<32>(0h0) connect _WIRE_24.bits.address, UInt<9>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_976 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_977 = and(io.in.d.ready, io.in.d.valid) node _T_978 = or(_T_976, _T_977) when _T_978 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_101( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [8:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [31:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [8:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [31:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire mask_sizeOH_shiftAmount = 1'h0; // @[OneHot.scala:64:49] wire mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21] wire mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_size = 1'h1; // @[Misc.scala:209:26] wire mask_acc = 1'h1; // @[Misc.scala:215:29] wire mask_acc_1 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_2 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_3 = 1'h1; // @[Misc.scala:215:29] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] is_aligned_mask = 2'h3; // @[package.scala:243:46] wire [1:0] mask_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] _a_first_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46] wire [1:0] _a_first_beats1_decode_T_5 = 2'h3; // @[package.scala:243:46] wire [1:0] _c_first_beats1_decode_T_1 = 2'h3; // @[package.scala:243:76] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_a_bits_size = 2'h2; // @[Monitor.scala:36:7] wire [1:0] _mask_sizeOH_T = 2'h2; // @[Misc.scala:202:34] wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [3:0] io_in_a_bits_mask = 4'hF; // @[Monitor.scala:36:7] wire [3:0] mask = 4'hF; // @[Misc.scala:222:10] wire [31:0] _c_first_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [8:0] _c_first_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_first_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_first_WIRE_2_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_first_WIRE_3_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_set_wo_ready_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_set_wo_ready_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_set_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_set_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_opcodes_set_interm_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_opcodes_set_interm_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_sizes_set_interm_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_sizes_set_interm_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_opcodes_set_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_opcodes_set_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_sizes_set_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_sizes_set_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_probe_ack_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_probe_ack_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_probe_ack_WIRE_2_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_probe_ack_WIRE_3_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _same_cycle_resp_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _same_cycle_resp_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _same_cycle_resp_WIRE_2_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _same_cycle_resp_WIRE_3_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _same_cycle_resp_WIRE_4_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _same_cycle_resp_WIRE_5_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [1:0] _is_aligned_mask_T_1 = 2'h0; // @[package.scala:243:76] wire [1:0] _a_first_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76] wire [1:0] _a_first_beats1_decode_T_4 = 2'h0; // @[package.scala:243:76] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_beats1_decode_T_2 = 2'h0; // @[package.scala:243:46] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [17:0] _c_sizes_set_T_1 = 18'h0; // @[Monitor.scala:768:52] wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79] wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] c_sizes_set = 4'h0; // @[Monitor.scala:741:34] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [1:0] _mask_sizeOH_T_1 = 2'h1; // @[OneHot.scala:65:12] wire [1:0] _mask_sizeOH_T_2 = 2'h1; // @[OneHot.scala:65:27] wire [1:0] mask_sizeOH = 2'h1; // @[Misc.scala:202:81] wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [4:0] _c_first_beats1_decode_T = 5'h3; // @[package.scala:243:71] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] _a_sizes_set_interm_T_1 = 3'h5; // @[Monitor.scala:658:59] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] _a_sizes_set_interm_T = 3'h4; // @[Monitor.scala:658:51] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [4:0] _is_aligned_mask_T = 5'hC; // @[package.scala:243:71] wire [4:0] _a_first_beats1_decode_T = 5'hC; // @[package.scala:243:71] wire [4:0] _a_first_beats1_decode_T_3 = 5'hC; // @[package.scala:243:71] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [8:0] _is_aligned_T = {7'h0, io_in_a_bits_address_0[1:0]}; // @[Monitor.scala:36:7] wire is_aligned = _is_aligned_T == 9'h0; // @[Edges.scala:21:{16,24}] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_1_2 = mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_eq; // @[Misc.scala:214:27, :215:38] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_eq_1; // @[Misc.scala:214:27, :215:38] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_eq_2; // @[Misc.scala:214:27, :215:38] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_eq_3; // @[Misc.scala:214:27, :215:38] wire _source_ok_T_1 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_1; // @[Parameters.scala:1138:31] wire _T_905 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_905; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_905; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [8:0] address; // @[Monitor.scala:391:22] wire _T_978 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_978; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_978; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_978; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [4:0] _GEN = 5'h3 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN; // @[package.scala:243:71] wire [1:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [3:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [1:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [3:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [3:0] _GEN_0 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [3:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_0; // @[Monitor.scala:637:69] wire [3:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_0; // @[Monitor.scala:637:69, :641:65] wire [3:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_0; // @[Monitor.scala:637:69, :680:101] wire [3:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_0; // @[Monitor.scala:637:69, :681:99] wire [3:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_0; // @[Monitor.scala:637:69, :749:69] wire [3:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_0; // @[Monitor.scala:637:69, :750:67] wire [3:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_0; // @[Monitor.scala:637:69, :790:101] wire [3:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_0; // @[Monitor.scala:637:69, :791:99] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [3:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [15:0] _a_size_lookup_T_6 = {12'h0, _a_size_lookup_T_1}; // @[Monitor.scala:637:97, :641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _T_828 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26] assign a_set_wo_ready = _T_828; // @[Monitor.scala:627:34, :651:26] wire _same_cycle_resp_T; // @[Monitor.scala:684:44] assign _same_cycle_resp_T = _T_828; // @[Monitor.scala:651:26, :684:44] assign a_set = _T_905 & a_first_1; // @[Decoupled.scala:51:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = a_set ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:{28,61}] assign a_sizes_set_interm = a_set ? 3'h5 : 3'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:28] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[Monitor.scala:646:40, :659:54] assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}] wire [17:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[Monitor.scala:648:38, :659:54, :660:52] assign a_sizes_set = a_set ? _a_sizes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [3:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_1 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_1; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_1; // @[Monitor.scala:673:46, :783:46] wire _T_877 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [1:0] _GEN_2 = {1'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_3 = 2'h1 << _GEN_2; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_3; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_3; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_3; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_877 & ~d_release_ack & _d_clr_wo_ready_T[0]; // @[OneHot.scala:58:35] wire _T_846 = _T_978 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_846 & _d_clr_T[0]; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_5 = 31'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_846 ? _d_opcodes_clr_T_5[3:0] : 4'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [30:0] _d_sizes_clr_T_5 = 31'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_846 ? _d_sizes_clr_T_5[3:0] : 4'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1:0] _inflight_T = {inflight[1], inflight[0] \| a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [3:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [3:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [3:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [3:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [3:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [1:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:637:97, :749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [3:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [15:0] _c_size_lookup_T_6 = {12'h0, _c_size_lookup_T_1}; // @[Monitor.scala:637:97, :750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [3:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_949 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_949 & d_release_ack_1 & _d_clr_wo_ready_T_1[0]; // @[OneHot.scala:58:35] wire _T_931 = _T_978 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_931 & _d_clr_T_1[0]; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_11 = 31'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_931 ? _d_opcodes_clr_T_11[3:0] : 4'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [30:0] _d_sizes_clr_T_11 = 31'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_931 ? _d_sizes_clr_T_11[3:0] : 4'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [3:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [3:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_71 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x	module OptimizationBarrier_TLBEntryData_71( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_EntryData_23 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x	module OptimizationBarrier_EntryData_23( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_g, // @[package.scala:268:18] output io_y_ae, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c, // @[package.scala:268:18] output io_y_fragmented_superpage // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_0 = io_x_ae; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g_0 = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_0 = io_x_ae_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage_0 = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_g = io_y_g_0; // @[package.scala:267:30] assign io_y_ae = io_y_ae_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] assign io_y_fragmented_superpage = io_y_fragmented_superpage_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to this FIRRTL code module InclusiveCacheBankScheduler_7 : input clock : Clock input reset : Reset output io : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, flip ways : UInt<16>[8], flip divs : UInt<11>[8], flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { address : UInt<32>}}, resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { fail : UInt<1>}}} inst sourceA of SourceA_7 connect sourceA.clock, clock connect sourceA.reset, reset inst sourceB of SourceB_7 connect sourceB.clock, clock connect sourceB.reset, reset inst sourceC of SourceC_7 connect sourceC.clock, clock connect sourceC.reset, reset inst sourceD of SourceD_7 connect sourceD.clock, clock connect sourceD.reset, reset inst sourceE of SourceE_7 connect sourceE.clock, clock connect sourceE.reset, reset inst sourceX of SourceX_7 connect sourceX.clock, clock connect sourceX.reset, reset connect io.out.a.bits, sourceA.io.a.bits connect io.out.a.valid, sourceA.io.a.valid connect sourceA.io.a.ready, io.out.a.ready connect io.out.c.bits, sourceC.io.c.bits connect io.out.c.valid, sourceC.io.c.valid connect sourceC.io.c.ready, io.out.c.ready connect io.out.e.bits, sourceE.io.e.bits connect io.out.e.valid, sourceE.io.e.valid connect sourceE.io.e.ready, io.out.e.ready connect io.in.b.bits, sourceB.io.b.bits connect io.in.b.valid, sourceB.io.b.valid connect sourceB.io.b.ready, io.in.b.ready connect io.in.d.bits, sourceD.io.d.bits connect io.in.d.valid, sourceD.io.d.valid connect sourceD.io.d.ready, io.in.d.ready connect io.resp.bits, sourceX.io.x.bits connect io.resp.valid, sourceX.io.x.valid connect sourceX.io.x.ready, io.resp.ready inst sinkA of SinkA_7 connect sinkA.clock, clock connect sinkA.reset, reset inst sinkC of SinkC_7 connect sinkC.clock, clock connect sinkC.reset, reset inst sinkD of SinkD_7 connect sinkD.clock, clock connect sinkD.reset, reset inst sinkE of SinkE_7 connect sinkE.clock, clock connect sinkE.reset, reset inst sinkX of SinkX_7 connect sinkX.clock, clock connect sinkX.reset, reset connect sinkA.io.a, io.in.a connect sinkC.io.c, io.in.c connect sinkE.io.e, io.in.e connect sinkD.io.d, io.out.d connect sinkX.io.x, io.req connect io.out.b.ready, UInt<1>(0h1) inst directory of Directory_7 connect directory.clock, clock connect directory.reset, reset inst bankedStore of BankedStore_7 connect bankedStore.clock, clock connect bankedStore.reset, reset inst requests of ListBuffer_QueuedRequest_q36_e28_7 connect requests.clock, clock connect requests.reset, reset inst mshrs_0 of MSHR_84 connect mshrs_0.clock, clock connect mshrs_0.reset, reset inst mshrs_1 of MSHR_85 connect mshrs_1.clock, clock connect mshrs_1.reset, reset inst mshrs_2 of MSHR_86 connect mshrs_2.clock, clock connect mshrs_2.reset, reset inst mshrs_3 of MSHR_87 connect mshrs_3.clock, clock connect mshrs_3.reset, reset inst mshrs_4 of MSHR_88 connect mshrs_4.clock, clock connect mshrs_4.reset, reset inst mshrs_5 of MSHR_89 connect mshrs_5.clock, clock connect mshrs_5.reset, reset inst mshrs_6 of MSHR_90 connect mshrs_6.clock, clock connect mshrs_6.reset, reset inst mshrs_7 of MSHR_91 connect mshrs_7.clock, clock connect mshrs_7.reset, reset inst mshrs_8 of MSHR_92 connect mshrs_8.clock, clock connect mshrs_8.reset, reset inst mshrs_9 of MSHR_93 connect mshrs_9.clock, clock connect mshrs_9.reset, reset inst mshrs_10 of MSHR_94 connect mshrs_10.clock, clock connect mshrs_10.reset, reset inst mshrs_11 of MSHR_95 connect mshrs_11.clock, clock connect mshrs_11.reset, reset wire nestedwb : { set : UInt<11>, tag : UInt<9>, b_toN : UInt<1>, b_toB : UInt<1>, b_clr_dirty : UInt<1>, c_set_dirty : UInt<1>} node _mshrs_0_io_sinkc_valid_T = eq(sinkC.io.resp.bits.set, mshrs_0.io.status.bits.set) node _mshrs_0_io_sinkc_valid_T_1 = and(sinkC.io.resp.valid, _mshrs_0_io_sinkc_valid_T) connect mshrs_0.io.sinkc.valid, _mshrs_0_io_sinkc_valid_T_1 node _mshrs_0_io_sinkd_valid_T = eq(sinkD.io.resp.bits.source, UInt<1>(0h0)) node _mshrs_0_io_sinkd_valid_T_1 = and(sinkD.io.resp.valid, _mshrs_0_io_sinkd_valid_T) connect mshrs_0.io.sinkd.valid, _mshrs_0_io_sinkd_valid_T_1 node _mshrs_0_io_sinke_valid_T = eq(sinkE.io.resp.bits.sink, UInt<1>(0h0)) node _mshrs_0_io_sinke_valid_T_1 = and(sinkE.io.resp.valid, _mshrs_0_io_sinke_valid_T) connect mshrs_0.io.sinke.valid, _mshrs_0_io_sinke_valid_T_1 connect mshrs_0.io.sinkc.bits.data, sinkC.io.resp.bits.data connect mshrs_0.io.sinkc.bits.param, sinkC.io.resp.bits.param connect mshrs_0.io.sinkc.bits.source, sinkC.io.resp.bits.source connect mshrs_0.io.sinkc.bits.tag, sinkC.io.resp.bits.tag connect mshrs_0.io.sinkc.bits.set, sinkC.io.resp.bits.set connect mshrs_0.io.sinkc.bits.last, sinkC.io.resp.bits.last connect mshrs_0.io.sinkd.bits.denied, sinkD.io.resp.bits.denied connect mshrs_0.io.sinkd.bits.sink, sinkD.io.resp.bits.sink connect mshrs_0.io.sinkd.bits.source, sinkD.io.resp.bits.source connect mshrs_0.io.sinkd.bits.param, sinkD.io.resp.bits.param connect mshrs_0.io.sinkd.bits.opcode, sinkD.io.resp.bits.opcode connect mshrs_0.io.sinkd.bits.last, sinkD.io.resp.bits.last connect mshrs_0.io.sinke.bits.sink, sinkE.io.resp.bits.sink connect mshrs_0.io.nestedwb.c_set_dirty, nestedwb.c_set_dirty connect mshrs_0.io.nestedwb.b_clr_dirty, nestedwb.b_clr_dirty connect mshrs_0.io.nestedwb.b_toB, nestedwb.b_toB connect mshrs_0.io.nestedwb.b_toN, nestedwb.b_toN connect mshrs_0.io.nestedwb.tag, nestedwb.tag connect mshrs_0.io.nestedwb.set, nestedwb.set node _mshrs_1_io_sinkc_valid_T = eq(sinkC.io.resp.bits.set, mshrs_1.io.status.bits.set) node _mshrs_1_io_sinkc_valid_T_1 = and(sinkC.io.resp.valid, _mshrs_1_io_sinkc_valid_T) connect mshrs_1.io.sinkc.valid, _mshrs_1_io_sinkc_valid_T_1 node _mshrs_1_io_sinkd_valid_T = eq(sinkD.io.resp.bits.source, UInt<1>(0h1)) node _mshrs_1_io_sinkd_valid_T_1 = and(sinkD.io.resp.valid, _mshrs_1_io_sinkd_valid_T) connect mshrs_1.io.sinkd.valid, _mshrs_1_io_sinkd_valid_T_1 node _mshrs_1_io_sinke_valid_T = eq(sinkE.io.resp.bits.sink, UInt<1>(0h1)) node _mshrs_1_io_sinke_valid_T_1 = and(sinkE.io.resp.valid, _mshrs_1_io_sinke_valid_T) connect mshrs_1.io.sinke.valid, _mshrs_1_io_sinke_valid_T_1 connect mshrs_1.io.sinkc.bits.data, sinkC.io.resp.bits.data connect mshrs_1.io.sinkc.bits.param, sinkC.io.resp.bits.param connect mshrs_1.io.sinkc.bits.source, sinkC.io.resp.bits.source connect mshrs_1.io.sinkc.bits.tag, sinkC.io.resp.bits.tag connect mshrs_1.io.sinkc.bits.set, sinkC.io.resp.bits.set connect mshrs_1.io.sinkc.bits.last, sinkC.io.resp.bits.last connect mshrs_1.io.sinkd.bits.denied, sinkD.io.resp.bits.denied connect mshrs_1.io.sinkd.bits.sink, sinkD.io.resp.bits.sink connect mshrs_1.io.sinkd.bits.source, sinkD.io.resp.bits.source connect mshrs_1.io.sinkd.bits.param, sinkD.io.resp.bits.param connect mshrs_1.io.sinkd.bits.opcode, sinkD.io.resp.bits.opcode connect mshrs_1.io.sinkd.bits.last, sinkD.io.resp.bits.last connect mshrs_1.io.sinke.bits.sink, sinkE.io.resp.bits.sink connect mshrs_1.io.nestedwb.c_set_dirty, nestedwb.c_set_dirty connect mshrs_1.io.nestedwb.b_clr_dirty, nestedwb.b_clr_dirty connect mshrs_1.io.nestedwb.b_toB, nestedwb.b_toB connect mshrs_1.io.nestedwb.b_toN, nestedwb.b_toN connect mshrs_1.io.nestedwb.tag, nestedwb.tag connect mshrs_1.io.nestedwb.set, nestedwb.set node _mshrs_2_io_sinkc_valid_T = eq(sinkC.io.resp.bits.set, mshrs_2.io.status.bits.set) node _mshrs_2_io_sinkc_valid_T_1 = and(sinkC.io.resp.valid, _mshrs_2_io_sinkc_valid_T) connect mshrs_2.io.sinkc.valid, _mshrs_2_io_sinkc_valid_T_1 node _mshrs_2_io_sinkd_valid_T = eq(sinkD.io.resp.bits.source, UInt<2>(0h2)) node _mshrs_2_io_sinkd_valid_T_1 = and(sinkD.io.resp.valid, _mshrs_2_io_sinkd_valid_T) connect mshrs_2.io.sinkd.valid, _mshrs_2_io_sinkd_valid_T_1 node _mshrs_2_io_sinke_valid_T = eq(sinkE.io.resp.bits.sink, UInt<2>(0h2)) node _mshrs_2_io_sinke_valid_T_1 = and(sinkE.io.resp.valid, _mshrs_2_io_sinke_valid_T) connect mshrs_2.io.sinke.valid, _mshrs_2_io_sinke_valid_T_1 connect mshrs_2.io.sinkc.bits.data, sinkC.io.resp.bits.data connect mshrs_2.io.sinkc.bits.param, sinkC.io.resp.bits.param connect mshrs_2.io.sinkc.bits.source, sinkC.io.resp.bits.source connect mshrs_2.io.sinkc.bits.tag, sinkC.io.resp.bits.tag connect mshrs_2.io.sinkc.bits.set, sinkC.io.resp.bits.set connect mshrs_2.io.sinkc.bits.last, sinkC.io.resp.bits.last connect mshrs_2.io.sinkd.bits.denied, sinkD.io.resp.bits.denied connect mshrs_2.io.sinkd.bits.sink, sinkD.io.resp.bits.sink connect mshrs_2.io.sinkd.bits.source, sinkD.io.resp.bits.source connect mshrs_2.io.sinkd.bits.param, sinkD.io.resp.bits.param connect mshrs_2.io.sinkd.bits.opcode, sinkD.io.resp.bits.opcode connect mshrs_2.io.sinkd.bits.last, sinkD.io.resp.bits.last connect mshrs_2.io.sinke.bits.sink, sinkE.io.resp.bits.sink connect mshrs_2.io.nestedwb.c_set_dirty, nestedwb.c_set_dirty connect mshrs_2.io.nestedwb.b_clr_dirty, nestedwb.b_clr_dirty connect mshrs_2.io.nestedwb.b_toB, nestedwb.b_toB connect mshrs_2.io.nestedwb.b_toN, nestedwb.b_toN connect mshrs_2.io.nestedwb.tag, nestedwb.tag connect mshrs_2.io.nestedwb.set, nestedwb.set node _mshrs_3_io_sinkc_valid_T = eq(sinkC.io.resp.bits.set, mshrs_3.io.status.bits.set) node _mshrs_3_io_sinkc_valid_T_1 = and(sinkC.io.resp.valid, _mshrs_3_io_sinkc_valid_T) connect mshrs_3.io.sinkc.valid, _mshrs_3_io_sinkc_valid_T_1 node _mshrs_3_io_sinkd_valid_T = eq(sinkD.io.resp.bits.source, UInt<2>(0h3)) node _mshrs_3_io_sinkd_valid_T_1 = and(sinkD.io.resp.valid, _mshrs_3_io_sinkd_valid_T) connect mshrs_3.io.sinkd.valid, _mshrs_3_io_sinkd_valid_T_1 node _mshrs_3_io_sinke_valid_T = eq(sinkE.io.resp.bits.sink, UInt<2>(0h3)) node _mshrs_3_io_sinke_valid_T_1 = and(sinkE.io.resp.valid, _mshrs_3_io_sinke_valid_T) connect mshrs_3.io.sinke.valid, _mshrs_3_io_sinke_valid_T_1 connect mshrs_3.io.sinkc.bits.data, sinkC.io.resp.bits.data connect mshrs_3.io.sinkc.bits.param, sinkC.io.resp.bits.param connect mshrs_3.io.sinkc.bits.source, sinkC.io.resp.bits.source connect mshrs_3.io.sinkc.bits.tag, sinkC.io.resp.bits.tag connect mshrs_3.io.sinkc.bits.set, sinkC.io.resp.bits.set connect mshrs_3.io.sinkc.bits.last, sinkC.io.resp.bits.last connect mshrs_3.io.sinkd.bits.denied, sinkD.io.resp.bits.denied connect mshrs_3.io.sinkd.bits.sink, sinkD.io.resp.bits.sink connect mshrs_3.io.sinkd.bits.source, sinkD.io.resp.bits.source connect mshrs_3.io.sinkd.bits.param, sinkD.io.resp.bits.param connect mshrs_3.io.sinkd.bits.opcode, sinkD.io.resp.bits.opcode connect mshrs_3.io.sinkd.bits.last, sinkD.io.resp.bits.last connect mshrs_3.io.sinke.bits.sink, sinkE.io.resp.bits.sink connect mshrs_3.io.nestedwb.c_set_dirty, nestedwb.c_set_dirty connect mshrs_3.io.nestedwb.b_clr_dirty, nestedwb.b_clr_dirty connect mshrs_3.io.nestedwb.b_toB, nestedwb.b_toB connect mshrs_3.io.nestedwb.b_toN, nestedwb.b_toN connect mshrs_3.io.nestedwb.tag, nestedwb.tag connect mshrs_3.io.nestedwb.set, nestedwb.set node _mshrs_4_io_sinkc_valid_T = eq(sinkC.io.resp.bits.set, mshrs_4.io.status.bits.set) node _mshrs_4_io_sinkc_valid_T_1 = and(sinkC.io.resp.valid, _mshrs_4_io_sinkc_valid_T) connect mshrs_4.io.sinkc.valid, _mshrs_4_io_sinkc_valid_T_1 node _mshrs_4_io_sinkd_valid_T = eq(sinkD.io.resp.bits.source, UInt<3>(0h4)) node _mshrs_4_io_sinkd_valid_T_1 = and(sinkD.io.resp.valid, _mshrs_4_io_sinkd_valid_T) connect mshrs_4.io.sinkd.valid, _mshrs_4_io_sinkd_valid_T_1 node _mshrs_4_io_sinke_valid_T = eq(sinkE.io.resp.bits.sink, UInt<3>(0h4)) node _mshrs_4_io_sinke_valid_T_1 = and(sinkE.io.resp.valid, _mshrs_4_io_sinke_valid_T) connect mshrs_4.io.sinke.valid, _mshrs_4_io_sinke_valid_T_1 connect mshrs_4.io.sinkc.bits.data, sinkC.io.resp.bits.data connect mshrs_4.io.sinkc.bits.param, sinkC.io.resp.bits.param connect mshrs_4.io.sinkc.bits.source, sinkC.io.resp.bits.source connect mshrs_4.io.sinkc.bits.tag, sinkC.io.resp.bits.tag connect mshrs_4.io.sinkc.bits.set, sinkC.io.resp.bits.set connect mshrs_4.io.sinkc.bits.last, sinkC.io.resp.bits.last connect mshrs_4.io.sinkd.bits.denied, sinkD.io.resp.bits.denied connect mshrs_4.io.sinkd.bits.sink, sinkD.io.resp.bits.sink connect mshrs_4.io.sinkd.bits.source, sinkD.io.resp.bits.source connect mshrs_4.io.sinkd.bits.param, sinkD.io.resp.bits.param connect mshrs_4.io.sinkd.bits.opcode, sinkD.io.resp.bits.opcode connect mshrs_4.io.sinkd.bits.last, sinkD.io.resp.bits.last connect mshrs_4.io.sinke.bits.sink, sinkE.io.resp.bits.sink connect mshrs_4.io.nestedwb.c_set_dirty, nestedwb.c_set_dirty connect mshrs_4.io.nestedwb.b_clr_dirty, nestedwb.b_clr_dirty connect mshrs_4.io.nestedwb.b_toB, nestedwb.b_toB connect mshrs_4.io.nestedwb.b_toN, nestedwb.b_toN connect mshrs_4.io.nestedwb.tag, nestedwb.tag connect mshrs_4.io.nestedwb.set, nestedwb.set node _mshrs_5_io_sinkc_valid_T = eq(sinkC.io.resp.bits.set, mshrs_5.io.status.bits.set) node _mshrs_5_io_sinkc_valid_T_1 = and(sinkC.io.resp.valid, _mshrs_5_io_sinkc_valid_T) connect mshrs_5.io.sinkc.valid, _mshrs_5_io_sinkc_valid_T_1 node _mshrs_5_io_sinkd_valid_T = eq(sinkD.io.resp.bits.source, UInt<3>(0h5)) node _mshrs_5_io_sinkd_valid_T_1 = and(sinkD.io.resp.valid, _mshrs_5_io_sinkd_valid_T) connect mshrs_5.io.sinkd.valid, _mshrs_5_io_sinkd_valid_T_1 node _mshrs_5_io_sinke_valid_T = eq(sinkE.io.resp.bits.sink, UInt<3>(0h5)) node _mshrs_5_io_sinke_valid_T_1 = and(sinkE.io.resp.valid, _mshrs_5_io_sinke_valid_T) connect mshrs_5.io.sinke.valid, _mshrs_5_io_sinke_valid_T_1 connect mshrs_5.io.sinkc.bits.data, sinkC.io.resp.bits.data connect mshrs_5.io.sinkc.bits.param, sinkC.io.resp.bits.param connect mshrs_5.io.sinkc.bits.source, sinkC.io.resp.bits.source connect mshrs_5.io.sinkc.bits.tag, sinkC.io.resp.bits.tag connect mshrs_5.io.sinkc.bits.set, sinkC.io.resp.bits.set connect mshrs_5.io.sinkc.bits.last, sinkC.io.resp.bits.last connect mshrs_5.io.sinkd.bits.denied, sinkD.io.resp.bits.denied connect mshrs_5.io.sinkd.bits.sink, sinkD.io.resp.bits.sink connect mshrs_5.io.sinkd.bits.source, sinkD.io.resp.bits.source connect mshrs_5.io.sinkd.bits.param, sinkD.io.resp.bits.param connect mshrs_5.io.sinkd.bits.opcode, sinkD.io.resp.bits.opcode connect mshrs_5.io.sinkd.bits.last, sinkD.io.resp.bits.last connect mshrs_5.io.sinke.bits.sink, sinkE.io.resp.bits.sink connect mshrs_5.io.nestedwb.c_set_dirty, nestedwb.c_set_dirty connect mshrs_5.io.nestedwb.b_clr_dirty, nestedwb.b_clr_dirty connect mshrs_5.io.nestedwb.b_toB, nestedwb.b_toB connect mshrs_5.io.nestedwb.b_toN, nestedwb.b_toN connect mshrs_5.io.nestedwb.tag, nestedwb.tag connect mshrs_5.io.nestedwb.set, nestedwb.set node _mshrs_6_io_sinkc_valid_T = eq(sinkC.io.resp.bits.set, mshrs_6.io.status.bits.set) node _mshrs_6_io_sinkc_valid_T_1 = and(sinkC.io.resp.valid, _mshrs_6_io_sinkc_valid_T) connect mshrs_6.io.sinkc.valid, _mshrs_6_io_sinkc_valid_T_1 node _mshrs_6_io_sinkd_valid_T = eq(sinkD.io.resp.bits.source, UInt<3>(0h6)) node _mshrs_6_io_sinkd_valid_T_1 = and(sinkD.io.resp.valid, _mshrs_6_io_sinkd_valid_T) connect mshrs_6.io.sinkd.valid, _mshrs_6_io_sinkd_valid_T_1 node _mshrs_6_io_sinke_valid_T = eq(sinkE.io.resp.bits.sink, UInt<3>(0h6)) node _mshrs_6_io_sinke_valid_T_1 = and(sinkE.io.resp.valid, _mshrs_6_io_sinke_valid_T) connect mshrs_6.io.sinke.valid, _mshrs_6_io_sinke_valid_T_1 connect mshrs_6.io.sinkc.bits.data, sinkC.io.resp.bits.data connect mshrs_6.io.sinkc.bits.param, sinkC.io.resp.bits.param connect mshrs_6.io.sinkc.bits.source, sinkC.io.resp.bits.source connect mshrs_6.io.sinkc.bits.tag, sinkC.io.resp.bits.tag connect mshrs_6.io.sinkc.bits.set, sinkC.io.resp.bits.set connect mshrs_6.io.sinkc.bits.last, sinkC.io.resp.bits.last connect mshrs_6.io.sinkd.bits.denied, sinkD.io.resp.bits.denied connect mshrs_6.io.sinkd.bits.sink, sinkD.io.resp.bits.sink connect mshrs_6.io.sinkd.bits.source, sinkD.io.resp.bits.source connect mshrs_6.io.sinkd.bits.param, sinkD.io.resp.bits.param connect mshrs_6.io.sinkd.bits.opcode, sinkD.io.resp.bits.opcode connect mshrs_6.io.sinkd.bits.last, sinkD.io.resp.bits.last connect mshrs_6.io.sinke.bits.sink, sinkE.io.resp.bits.sink connect mshrs_6.io.nestedwb.c_set_dirty, nestedwb.c_set_dirty connect mshrs_6.io.nestedwb.b_clr_dirty, nestedwb.b_clr_dirty connect mshrs_6.io.nestedwb.b_toB, nestedwb.b_toB connect mshrs_6.io.nestedwb.b_toN, nestedwb.b_toN connect mshrs_6.io.nestedwb.tag, nestedwb.tag connect mshrs_6.io.nestedwb.set, nestedwb.set node _mshrs_7_io_sinkc_valid_T = eq(sinkC.io.resp.bits.set, mshrs_7.io.status.bits.set) node _mshrs_7_io_sinkc_valid_T_1 = and(sinkC.io.resp.valid, _mshrs_7_io_sinkc_valid_T) connect mshrs_7.io.sinkc.valid, _mshrs_7_io_sinkc_valid_T_1 node _mshrs_7_io_sinkd_valid_T = eq(sinkD.io.resp.bits.source, UInt<3>(0h7)) node _mshrs_7_io_sinkd_valid_T_1 = and(sinkD.io.resp.valid, _mshrs_7_io_sinkd_valid_T) connect mshrs_7.io.sinkd.valid, _mshrs_7_io_sinkd_valid_T_1 node _mshrs_7_io_sinke_valid_T = eq(sinkE.io.resp.bits.sink, UInt<3>(0h7)) node _mshrs_7_io_sinke_valid_T_1 = and(sinkE.io.resp.valid, _mshrs_7_io_sinke_valid_T) connect mshrs_7.io.sinke.valid, _mshrs_7_io_sinke_valid_T_1 connect mshrs_7.io.sinkc.bits.data, sinkC.io.resp.bits.data connect mshrs_7.io.sinkc.bits.param, sinkC.io.resp.bits.param connect mshrs_7.io.sinkc.bits.source, sinkC.io.resp.bits.source connect mshrs_7.io.sinkc.bits.tag, sinkC.io.resp.bits.tag connect mshrs_7.io.sinkc.bits.set, sinkC.io.resp.bits.set connect mshrs_7.io.sinkc.bits.last, sinkC.io.resp.bits.last connect mshrs_7.io.sinkd.bits.denied, sinkD.io.resp.bits.denied connect mshrs_7.io.sinkd.bits.sink, sinkD.io.resp.bits.sink connect mshrs_7.io.sinkd.bits.source, sinkD.io.resp.bits.source connect mshrs_7.io.sinkd.bits.param, sinkD.io.resp.bits.param connect mshrs_7.io.sinkd.bits.opcode, sinkD.io.resp.bits.opcode connect mshrs_7.io.sinkd.bits.last, sinkD.io.resp.bits.last connect mshrs_7.io.sinke.bits.sink, sinkE.io.resp.bits.sink connect mshrs_7.io.nestedwb.c_set_dirty, nestedwb.c_set_dirty connect mshrs_7.io.nestedwb.b_clr_dirty, nestedwb.b_clr_dirty connect mshrs_7.io.nestedwb.b_toB, nestedwb.b_toB connect mshrs_7.io.nestedwb.b_toN, nestedwb.b_toN connect mshrs_7.io.nestedwb.tag, nestedwb.tag connect mshrs_7.io.nestedwb.set, nestedwb.set node _mshrs_8_io_sinkc_valid_T = eq(sinkC.io.resp.bits.set, mshrs_8.io.status.bits.set) node _mshrs_8_io_sinkc_valid_T_1 = and(sinkC.io.resp.valid, _mshrs_8_io_sinkc_valid_T) connect mshrs_8.io.sinkc.valid, _mshrs_8_io_sinkc_valid_T_1 node _mshrs_8_io_sinkd_valid_T = eq(sinkD.io.resp.bits.source, UInt<4>(0h8)) node _mshrs_8_io_sinkd_valid_T_1 = and(sinkD.io.resp.valid, _mshrs_8_io_sinkd_valid_T) connect mshrs_8.io.sinkd.valid, _mshrs_8_io_sinkd_valid_T_1 node _mshrs_8_io_sinke_valid_T = eq(sinkE.io.resp.bits.sink, UInt<4>(0h8)) node _mshrs_8_io_sinke_valid_T_1 = and(sinkE.io.resp.valid, _mshrs_8_io_sinke_valid_T) connect mshrs_8.io.sinke.valid, _mshrs_8_io_sinke_valid_T_1 connect mshrs_8.io.sinkc.bits.data, sinkC.io.resp.bits.data connect mshrs_8.io.sinkc.bits.param, sinkC.io.resp.bits.param connect mshrs_8.io.sinkc.bits.source, sinkC.io.resp.bits.source connect mshrs_8.io.sinkc.bits.tag, sinkC.io.resp.bits.tag connect mshrs_8.io.sinkc.bits.set, sinkC.io.resp.bits.set connect mshrs_8.io.sinkc.bits.last, sinkC.io.resp.bits.last connect mshrs_8.io.sinkd.bits.denied, sinkD.io.resp.bits.denied connect mshrs_8.io.sinkd.bits.sink, sinkD.io.resp.bits.sink connect mshrs_8.io.sinkd.bits.source, sinkD.io.resp.bits.source connect mshrs_8.io.sinkd.bits.param, sinkD.io.resp.bits.param connect mshrs_8.io.sinkd.bits.opcode, sinkD.io.resp.bits.opcode connect mshrs_8.io.sinkd.bits.last, sinkD.io.resp.bits.last connect mshrs_8.io.sinke.bits.sink, sinkE.io.resp.bits.sink connect mshrs_8.io.nestedwb.c_set_dirty, nestedwb.c_set_dirty connect mshrs_8.io.nestedwb.b_clr_dirty, nestedwb.b_clr_dirty connect mshrs_8.io.nestedwb.b_toB, nestedwb.b_toB connect mshrs_8.io.nestedwb.b_toN, nestedwb.b_toN connect mshrs_8.io.nestedwb.tag, nestedwb.tag connect mshrs_8.io.nestedwb.set, nestedwb.set node _mshrs_9_io_sinkc_valid_T = eq(sinkC.io.resp.bits.set, mshrs_9.io.status.bits.set) node _mshrs_9_io_sinkc_valid_T_1 = and(sinkC.io.resp.valid, _mshrs_9_io_sinkc_valid_T) connect mshrs_9.io.sinkc.valid, _mshrs_9_io_sinkc_valid_T_1 node _mshrs_9_io_sinkd_valid_T = eq(sinkD.io.resp.bits.source, UInt<4>(0h9)) node _mshrs_9_io_sinkd_valid_T_1 = and(sinkD.io.resp.valid, _mshrs_9_io_sinkd_valid_T) connect mshrs_9.io.sinkd.valid, _mshrs_9_io_sinkd_valid_T_1 node _mshrs_9_io_sinke_valid_T = eq(sinkE.io.resp.bits.sink, UInt<4>(0h9)) node _mshrs_9_io_sinke_valid_T_1 = and(sinkE.io.resp.valid, _mshrs_9_io_sinke_valid_T) connect mshrs_9.io.sinke.valid, _mshrs_9_io_sinke_valid_T_1 connect mshrs_9.io.sinkc.bits.data, sinkC.io.resp.bits.data connect mshrs_9.io.sinkc.bits.param, sinkC.io.resp.bits.param connect mshrs_9.io.sinkc.bits.source, sinkC.io.resp.bits.source connect mshrs_9.io.sinkc.bits.tag, sinkC.io.resp.bits.tag connect mshrs_9.io.sinkc.bits.set, sinkC.io.resp.bits.set connect mshrs_9.io.sinkc.bits.last, sinkC.io.resp.bits.last connect mshrs_9.io.sinkd.bits.denied, sinkD.io.resp.bits.denied connect mshrs_9.io.sinkd.bits.sink, sinkD.io.resp.bits.sink connect mshrs_9.io.sinkd.bits.source, sinkD.io.resp.bits.source connect mshrs_9.io.sinkd.bits.param, sinkD.io.resp.bits.param connect mshrs_9.io.sinkd.bits.opcode, sinkD.io.resp.bits.opcode connect mshrs_9.io.sinkd.bits.last, sinkD.io.resp.bits.last connect mshrs_9.io.sinke.bits.sink, sinkE.io.resp.bits.sink connect mshrs_9.io.nestedwb.c_set_dirty, nestedwb.c_set_dirty connect mshrs_9.io.nestedwb.b_clr_dirty, nestedwb.b_clr_dirty connect mshrs_9.io.nestedwb.b_toB, nestedwb.b_toB connect mshrs_9.io.nestedwb.b_toN, nestedwb.b_toN connect mshrs_9.io.nestedwb.tag, nestedwb.tag connect mshrs_9.io.nestedwb.set, nestedwb.set node _mshrs_10_io_sinkc_valid_T = eq(sinkC.io.resp.bits.set, mshrs_10.io.status.bits.set) node _mshrs_10_io_sinkc_valid_T_1 = and(sinkC.io.resp.valid, _mshrs_10_io_sinkc_valid_T) connect mshrs_10.io.sinkc.valid, _mshrs_10_io_sinkc_valid_T_1 node _mshrs_10_io_sinkd_valid_T = eq(sinkD.io.resp.bits.source, UInt<4>(0ha)) node _mshrs_10_io_sinkd_valid_T_1 = and(sinkD.io.resp.valid, _mshrs_10_io_sinkd_valid_T) connect mshrs_10.io.sinkd.valid, _mshrs_10_io_sinkd_valid_T_1 node _mshrs_10_io_sinke_valid_T = eq(sinkE.io.resp.bits.sink, UInt<4>(0ha)) node _mshrs_10_io_sinke_valid_T_1 = and(sinkE.io.resp.valid, _mshrs_10_io_sinke_valid_T) connect mshrs_10.io.sinke.valid, _mshrs_10_io_sinke_valid_T_1 connect mshrs_10.io.sinkc.bits.data, sinkC.io.resp.bits.data connect mshrs_10.io.sinkc.bits.param, sinkC.io.resp.bits.param connect mshrs_10.io.sinkc.bits.source, sinkC.io.resp.bits.source connect mshrs_10.io.sinkc.bits.tag, sinkC.io.resp.bits.tag connect mshrs_10.io.sinkc.bits.set, sinkC.io.resp.bits.set connect mshrs_10.io.sinkc.bits.last, sinkC.io.resp.bits.last connect mshrs_10.io.sinkd.bits.denied, sinkD.io.resp.bits.denied connect mshrs_10.io.sinkd.bits.sink, sinkD.io.resp.bits.sink connect mshrs_10.io.sinkd.bits.source, sinkD.io.resp.bits.source connect mshrs_10.io.sinkd.bits.param, sinkD.io.resp.bits.param connect mshrs_10.io.sinkd.bits.opcode, sinkD.io.resp.bits.opcode connect mshrs_10.io.sinkd.bits.last, sinkD.io.resp.bits.last connect mshrs_10.io.sinke.bits.sink, sinkE.io.resp.bits.sink connect mshrs_10.io.nestedwb.c_set_dirty, nestedwb.c_set_dirty connect mshrs_10.io.nestedwb.b_clr_dirty, nestedwb.b_clr_dirty connect mshrs_10.io.nestedwb.b_toB, nestedwb.b_toB connect mshrs_10.io.nestedwb.b_toN, nestedwb.b_toN connect mshrs_10.io.nestedwb.tag, nestedwb.tag connect mshrs_10.io.nestedwb.set, nestedwb.set node _mshrs_11_io_sinkc_valid_T = eq(sinkC.io.resp.bits.set, mshrs_11.io.status.bits.set) node _mshrs_11_io_sinkc_valid_T_1 = and(sinkC.io.resp.valid, _mshrs_11_io_sinkc_valid_T) connect mshrs_11.io.sinkc.valid, _mshrs_11_io_sinkc_valid_T_1 node _mshrs_11_io_sinkd_valid_T = eq(sinkD.io.resp.bits.source, UInt<4>(0hb)) node _mshrs_11_io_sinkd_valid_T_1 = and(sinkD.io.resp.valid, _mshrs_11_io_sinkd_valid_T) connect mshrs_11.io.sinkd.valid, _mshrs_11_io_sinkd_valid_T_1 node _mshrs_11_io_sinke_valid_T = eq(sinkE.io.resp.bits.sink, UInt<4>(0hb)) node _mshrs_11_io_sinke_valid_T_1 = and(sinkE.io.resp.valid, _mshrs_11_io_sinke_valid_T) connect mshrs_11.io.sinke.valid, _mshrs_11_io_sinke_valid_T_1 connect mshrs_11.io.sinkc.bits.data, sinkC.io.resp.bits.data connect mshrs_11.io.sinkc.bits.param, sinkC.io.resp.bits.param connect mshrs_11.io.sinkc.bits.source, sinkC.io.resp.bits.source connect mshrs_11.io.sinkc.bits.tag, sinkC.io.resp.bits.tag connect mshrs_11.io.sinkc.bits.set, sinkC.io.resp.bits.set connect mshrs_11.io.sinkc.bits.last, sinkC.io.resp.bits.last connect mshrs_11.io.sinkd.bits.denied, sinkD.io.resp.bits.denied connect mshrs_11.io.sinkd.bits.sink, sinkD.io.resp.bits.sink connect mshrs_11.io.sinkd.bits.source, sinkD.io.resp.bits.source connect mshrs_11.io.sinkd.bits.param, sinkD.io.resp.bits.param connect mshrs_11.io.sinkd.bits.opcode, sinkD.io.resp.bits.opcode connect mshrs_11.io.sinkd.bits.last, sinkD.io.resp.bits.last connect mshrs_11.io.sinke.bits.sink, sinkE.io.resp.bits.sink connect mshrs_11.io.nestedwb.c_set_dirty, nestedwb.c_set_dirty connect mshrs_11.io.nestedwb.b_clr_dirty, nestedwb.b_clr_dirty connect mshrs_11.io.nestedwb.b_toB, nestedwb.b_toB connect mshrs_11.io.nestedwb.b_toN, nestedwb.b_toN connect mshrs_11.io.nestedwb.tag, nestedwb.tag connect mshrs_11.io.nestedwb.set, nestedwb.set node _mshr_stall_abc_T = eq(mshrs_0.io.status.bits.set, mshrs_10.io.status.bits.set) node _mshr_stall_abc_T_1 = and(mshrs_10.io.status.valid, _mshr_stall_abc_T) node _mshr_stall_abc_T_2 = eq(mshrs_0.io.status.bits.set, mshrs_11.io.status.bits.set) node _mshr_stall_abc_T_3 = and(mshrs_11.io.status.valid, _mshr_stall_abc_T_2) node mshr_stall_abc_0 = or(_mshr_stall_abc_T_1, _mshr_stall_abc_T_3) node _mshr_stall_abc_T_4 = eq(mshrs_1.io.status.bits.set, mshrs_10.io.status.bits.set) node _mshr_stall_abc_T_5 = and(mshrs_10.io.status.valid, _mshr_stall_abc_T_4) node _mshr_stall_abc_T_6 = eq(mshrs_1.io.status.bits.set, mshrs_11.io.status.bits.set) node _mshr_stall_abc_T_7 = and(mshrs_11.io.status.valid, _mshr_stall_abc_T_6) node mshr_stall_abc_1 = or(_mshr_stall_abc_T_5, _mshr_stall_abc_T_7) node _mshr_stall_abc_T_8 = eq(mshrs_2.io.status.bits.set, mshrs_10.io.status.bits.set) node _mshr_stall_abc_T_9 = and(mshrs_10.io.status.valid, _mshr_stall_abc_T_8) node _mshr_stall_abc_T_10 = eq(mshrs_2.io.status.bits.set, mshrs_11.io.status.bits.set) node _mshr_stall_abc_T_11 = and(mshrs_11.io.status.valid, _mshr_stall_abc_T_10) node mshr_stall_abc_2 = or(_mshr_stall_abc_T_9, _mshr_stall_abc_T_11) node _mshr_stall_abc_T_12 = eq(mshrs_3.io.status.bits.set, mshrs_10.io.status.bits.set) node _mshr_stall_abc_T_13 = and(mshrs_10.io.status.valid, _mshr_stall_abc_T_12) node _mshr_stall_abc_T_14 = eq(mshrs_3.io.status.bits.set, mshrs_11.io.status.bits.set) node _mshr_stall_abc_T_15 = and(mshrs_11.io.status.valid, _mshr_stall_abc_T_14) node mshr_stall_abc_3 = or(_mshr_stall_abc_T_13, _mshr_stall_abc_T_15) node _mshr_stall_abc_T_16 = eq(mshrs_4.io.status.bits.set, mshrs_10.io.status.bits.set) node _mshr_stall_abc_T_17 = and(mshrs_10.io.status.valid, _mshr_stall_abc_T_16) node _mshr_stall_abc_T_18 = eq(mshrs_4.io.status.bits.set, mshrs_11.io.status.bits.set) node _mshr_stall_abc_T_19 = and(mshrs_11.io.status.valid, _mshr_stall_abc_T_18) node mshr_stall_abc_4 = or(_mshr_stall_abc_T_17, _mshr_stall_abc_T_19) node _mshr_stall_abc_T_20 = eq(mshrs_5.io.status.bits.set, mshrs_10.io.status.bits.set) node _mshr_stall_abc_T_21 = and(mshrs_10.io.status.valid, _mshr_stall_abc_T_20) node _mshr_stall_abc_T_22 = eq(mshrs_5.io.status.bits.set, mshrs_11.io.status.bits.set) node _mshr_stall_abc_T_23 = and(mshrs_11.io.status.valid, _mshr_stall_abc_T_22) node mshr_stall_abc_5 = or(_mshr_stall_abc_T_21, _mshr_stall_abc_T_23) node _mshr_stall_abc_T_24 = eq(mshrs_6.io.status.bits.set, mshrs_10.io.status.bits.set) node _mshr_stall_abc_T_25 = and(mshrs_10.io.status.valid, _mshr_stall_abc_T_24) node _mshr_stall_abc_T_26 = eq(mshrs_6.io.status.bits.set, mshrs_11.io.status.bits.set) node _mshr_stall_abc_T_27 = and(mshrs_11.io.status.valid, _mshr_stall_abc_T_26) node mshr_stall_abc_6 = or(_mshr_stall_abc_T_25, _mshr_stall_abc_T_27) node _mshr_stall_abc_T_28 = eq(mshrs_7.io.status.bits.set, mshrs_10.io.status.bits.set) node _mshr_stall_abc_T_29 = and(mshrs_10.io.status.valid, _mshr_stall_abc_T_28) node _mshr_stall_abc_T_30 = eq(mshrs_7.io.status.bits.set, mshrs_11.io.status.bits.set) node _mshr_stall_abc_T_31 = and(mshrs_11.io.status.valid, _mshr_stall_abc_T_30) node mshr_stall_abc_7 = or(_mshr_stall_abc_T_29, _mshr_stall_abc_T_31) node _mshr_stall_abc_T_32 = eq(mshrs_8.io.status.bits.set, mshrs_10.io.status.bits.set) node _mshr_stall_abc_T_33 = and(mshrs_10.io.status.valid, _mshr_stall_abc_T_32) node _mshr_stall_abc_T_34 = eq(mshrs_8.io.status.bits.set, mshrs_11.io.status.bits.set) node _mshr_stall_abc_T_35 = and(mshrs_11.io.status.valid, _mshr_stall_abc_T_34) node mshr_stall_abc_8 = or(_mshr_stall_abc_T_33, _mshr_stall_abc_T_35) node _mshr_stall_abc_T_36 = eq(mshrs_9.io.status.bits.set, mshrs_10.io.status.bits.set) node _mshr_stall_abc_T_37 = and(mshrs_10.io.status.valid, _mshr_stall_abc_T_36) node _mshr_stall_abc_T_38 = eq(mshrs_9.io.status.bits.set, mshrs_11.io.status.bits.set) node _mshr_stall_abc_T_39 = and(mshrs_11.io.status.valid, _mshr_stall_abc_T_38) node mshr_stall_abc_9 = or(_mshr_stall_abc_T_37, _mshr_stall_abc_T_39) node _mshr_stall_bc_T = eq(mshrs_10.io.status.bits.set, mshrs_11.io.status.bits.set) node mshr_stall_bc = and(mshrs_11.io.status.valid, _mshr_stall_bc_T) node stall_abc_0 = and(mshr_stall_abc_0, mshrs_0.io.status.valid) node stall_abc_1 = and(mshr_stall_abc_1, mshrs_1.io.status.valid) node stall_abc_2 = and(mshr_stall_abc_2, mshrs_2.io.status.valid) node stall_abc_3 = and(mshr_stall_abc_3, mshrs_3.io.status.valid) node stall_abc_4 = and(mshr_stall_abc_4, mshrs_4.io.status.valid) node stall_abc_5 = and(mshr_stall_abc_5, mshrs_5.io.status.valid) node stall_abc_6 = and(mshr_stall_abc_6, mshrs_6.io.status.valid) node stall_abc_7 = and(mshr_stall_abc_7, mshrs_7.io.status.valid) node stall_abc_8 = and(mshr_stall_abc_8, mshrs_8.io.status.valid) node stall_abc_9 = and(mshr_stall_abc_9, mshrs_9.io.status.valid) node _T = or(stall_abc_0, stall_abc_1) node _T_1 = or(_T, stall_abc_2) node _T_2 = or(_T_1, stall_abc_3) node _T_3 = or(_T_2, stall_abc_4) node _T_4 = or(_T_3, stall_abc_5) node _T_5 = or(_T_4, stall_abc_6) node _T_6 = or(_T_5, stall_abc_7) node _T_7 = or(_T_6, stall_abc_8) node _T_8 = or(_T_7, stall_abc_9) node _mshr_request_T = eq(mshr_stall_abc_0, UInt<1>(0h0)) node _mshr_request_T_1 = and(mshrs_0.io.schedule.valid, _mshr_request_T) node _mshr_request_T_2 = eq(mshrs_0.io.schedule.bits.a.valid, UInt<1>(0h0)) node _mshr_request_T_3 = or(sourceA.io.req.ready, _mshr_request_T_2) node _mshr_request_T_4 = and(_mshr_request_T_1, _mshr_request_T_3) node _mshr_request_T_5 = eq(mshrs_0.io.schedule.bits.b.valid, UInt<1>(0h0)) node _mshr_request_T_6 = or(sourceB.io.req.ready, _mshr_request_T_5) node _mshr_request_T_7 = and(_mshr_request_T_4, _mshr_request_T_6) node _mshr_request_T_8 = eq(mshrs_0.io.schedule.bits.c.valid, UInt<1>(0h0)) node _mshr_request_T_9 = or(sourceC.io.req.ready, _mshr_request_T_8) node _mshr_request_T_10 = and(_mshr_request_T_7, _mshr_request_T_9) node _mshr_request_T_11 = eq(mshrs_0.io.schedule.bits.d.valid, UInt<1>(0h0)) node _mshr_request_T_12 = or(sourceD.io.req.ready, _mshr_request_T_11) node _mshr_request_T_13 = and(_mshr_request_T_10, _mshr_request_T_12) node _mshr_request_T_14 = eq(mshrs_0.io.schedule.bits.e.valid, UInt<1>(0h0)) node _mshr_request_T_15 = or(sourceE.io.req.ready, _mshr_request_T_14) node _mshr_request_T_16 = and(_mshr_request_T_13, _mshr_request_T_15) node _mshr_request_T_17 = eq(mshrs_0.io.schedule.bits.x.valid, UInt<1>(0h0)) node _mshr_request_T_18 = or(sourceX.io.req.ready, _mshr_request_T_17) node _mshr_request_T_19 = and(_mshr_request_T_16, _mshr_request_T_18) node _mshr_request_T_20 = eq(mshrs_0.io.schedule.bits.dir.valid, UInt<1>(0h0)) node _mshr_request_T_21 = or(directory.io.write.ready, _mshr_request_T_20) node _mshr_request_T_22 = and(_mshr_request_T_19, _mshr_request_T_21) node _mshr_request_T_23 = eq(mshr_stall_abc_1, UInt<1>(0h0)) node _mshr_request_T_24 = and(mshrs_1.io.schedule.valid, _mshr_request_T_23) node _mshr_request_T_25 = eq(mshrs_1.io.schedule.bits.a.valid, UInt<1>(0h0)) node _mshr_request_T_26 = or(sourceA.io.req.ready, _mshr_request_T_25) node _mshr_request_T_27 = and(_mshr_request_T_24, _mshr_request_T_26) node _mshr_request_T_28 = eq(mshrs_1.io.schedule.bits.b.valid, UInt<1>(0h0)) node _mshr_request_T_29 = or(sourceB.io.req.ready, _mshr_request_T_28) node _mshr_request_T_30 = and(_mshr_request_T_27, _mshr_request_T_29) node _mshr_request_T_31 = eq(mshrs_1.io.schedule.bits.c.valid, UInt<1>(0h0)) node _mshr_request_T_32 = or(sourceC.io.req.ready, _mshr_request_T_31) node _mshr_request_T_33 = and(_mshr_request_T_30, _mshr_request_T_32) node _mshr_request_T_34 = eq(mshrs_1.io.schedule.bits.d.valid, UInt<1>(0h0)) node _mshr_request_T_35 = or(sourceD.io.req.ready, _mshr_request_T_34) node _mshr_request_T_36 = and(_mshr_request_T_33, _mshr_request_T_35) node _mshr_request_T_37 = eq(mshrs_1.io.schedule.bits.e.valid, UInt<1>(0h0)) node _mshr_request_T_38 = or(sourceE.io.req.ready, _mshr_request_T_37) node _mshr_request_T_39 = and(_mshr_request_T_36, _mshr_request_T_38) node _mshr_request_T_40 = eq(mshrs_1.io.schedule.bits.x.valid, UInt<1>(0h0)) node _mshr_request_T_41 = or(sourceX.io.req.ready, _mshr_request_T_40) node _mshr_request_T_42 = and(_mshr_request_T_39, _mshr_request_T_41) node _mshr_request_T_43 = eq(mshrs_1.io.schedule.bits.dir.valid, UInt<1>(0h0)) node _mshr_request_T_44 = or(directory.io.write.ready, _mshr_request_T_43) node _mshr_request_T_45 = and(_mshr_request_T_42, _mshr_request_T_44) node _mshr_request_T_46 = eq(mshr_stall_abc_2, UInt<1>(0h0)) node _mshr_request_T_47 = and(mshrs_2.io.schedule.valid, _mshr_request_T_46) node _mshr_request_T_48 = eq(mshrs_2.io.schedule.bits.a.valid, UInt<1>(0h0)) node _mshr_request_T_49 = or(sourceA.io.req.ready, _mshr_request_T_48) node _mshr_request_T_50 = and(_mshr_request_T_47, _mshr_request_T_49) node _mshr_request_T_51 = eq(mshrs_2.io.schedule.bits.b.valid, UInt<1>(0h0)) node _mshr_request_T_52 = or(sourceB.io.req.ready, _mshr_request_T_51) node _mshr_request_T_53 = and(_mshr_request_T_50, _mshr_request_T_52) node _mshr_request_T_54 = eq(mshrs_2.io.schedule.bits.c.valid, UInt<1>(0h0)) node _mshr_request_T_55 = or(sourceC.io.req.ready, _mshr_request_T_54) node _mshr_request_T_56 = and(_mshr_request_T_53, _mshr_request_T_55) node _mshr_request_T_57 = eq(mshrs_2.io.schedule.bits.d.valid, UInt<1>(0h0)) node _mshr_request_T_58 = or(sourceD.io.req.ready, _mshr_request_T_57) node _mshr_request_T_59 = and(_mshr_request_T_56, _mshr_request_T_58) node _mshr_request_T_60 = eq(mshrs_2.io.schedule.bits.e.valid, UInt<1>(0h0)) node _mshr_request_T_61 = or(sourceE.io.req.ready, _mshr_request_T_60) node _mshr_request_T_62 = and(_mshr_request_T_59, _mshr_request_T_61) node _mshr_request_T_63 = eq(mshrs_2.io.schedule.bits.x.valid, UInt<1>(0h0)) node _mshr_request_T_64 = or(sourceX.io.req.ready, _mshr_request_T_63) node _mshr_request_T_65 = and(_mshr_request_T_62, _mshr_request_T_64) node _mshr_request_T_66 = eq(mshrs_2.io.schedule.bits.dir.valid, UInt<1>(0h0)) node _mshr_request_T_67 = or(directory.io.write.ready, _mshr_request_T_66) node _mshr_request_T_68 = and(_mshr_request_T_65, _mshr_request_T_67) node _mshr_request_T_69 = eq(mshr_stall_abc_3, UInt<1>(0h0)) node _mshr_request_T_70 = and(mshrs_3.io.schedule.valid, _mshr_request_T_69) node _mshr_request_T_71 = eq(mshrs_3.io.schedule.bits.a.valid, UInt<1>(0h0)) node _mshr_request_T_72 = or(sourceA.io.req.ready, _mshr_request_T_71) node _mshr_request_T_73 = and(_mshr_request_T_70, _mshr_request_T_72) node _mshr_request_T_74 = eq(mshrs_3.io.schedule.bits.b.valid, UInt<1>(0h0)) node _mshr_request_T_75 = or(sourceB.io.req.ready, _mshr_request_T_74) node _mshr_request_T_76 = and(_mshr_request_T_73, _mshr_request_T_75) node _mshr_request_T_77 = eq(mshrs_3.io.schedule.bits.c.valid, UInt<1>(0h0)) node _mshr_request_T_78 = or(sourceC.io.req.ready, _mshr_request_T_77) node _mshr_request_T_79 = and(_mshr_request_T_76, _mshr_request_T_78) node _mshr_request_T_80 = eq(mshrs_3.io.schedule.bits.d.valid, UInt<1>(0h0)) node _mshr_request_T_81 = or(sourceD.io.req.ready, _mshr_request_T_80) node _mshr_request_T_82 = and(_mshr_request_T_79, _mshr_request_T_81) node _mshr_request_T_83 = eq(mshrs_3.io.schedule.bits.e.valid, UInt<1>(0h0)) node _mshr_request_T_84 = or(sourceE.io.req.ready, _mshr_request_T_83) node _mshr_request_T_85 = and(_mshr_request_T_82, _mshr_request_T_84) node _mshr_request_T_86 = eq(mshrs_3.io.schedule.bits.x.valid, UInt<1>(0h0)) node _mshr_request_T_87 = or(sourceX.io.req.ready, _mshr_request_T_86) node _mshr_request_T_88 = and(_mshr_request_T_85, _mshr_request_T_87) node _mshr_request_T_89 = eq(mshrs_3.io.schedule.bits.dir.valid, UInt<1>(0h0)) node _mshr_request_T_90 = or(directory.io.write.ready, _mshr_request_T_89) node _mshr_request_T_91 = and(_mshr_request_T_88, _mshr_request_T_90) node _mshr_request_T_92 = eq(mshr_stall_abc_4, UInt<1>(0h0)) node _mshr_request_T_93 = and(mshrs_4.io.schedule.valid, _mshr_request_T_92) node _mshr_request_T_94 = eq(mshrs_4.io.schedule.bits.a.valid, UInt<1>(0h0)) node _mshr_request_T_95 = or(sourceA.io.req.ready, _mshr_request_T_94) node _mshr_request_T_96 = and(_mshr_request_T_93, _mshr_request_T_95) node _mshr_request_T_97 = eq(mshrs_4.io.schedule.bits.b.valid, UInt<1>(0h0)) node _mshr_request_T_98 = or(sourceB.io.req.ready, _mshr_request_T_97) node _mshr_request_T_99 = and(_mshr_request_T_96, _mshr_request_T_98) node _mshr_request_T_100 = eq(mshrs_4.io.schedule.bits.c.valid, UInt<1>(0h0)) node _mshr_request_T_101 = or(sourceC.io.req.ready, _mshr_request_T_100) node _mshr_request_T_102 = and(_mshr_request_T_99, _mshr_request_T_101) node _mshr_request_T_103 = eq(mshrs_4.io.schedule.bits.d.valid, UInt<1>(0h0)) node _mshr_request_T_104 = or(sourceD.io.req.ready, _mshr_request_T_103) node _mshr_request_T_105 = and(_mshr_request_T_102, _mshr_request_T_104) node _mshr_request_T_106 = eq(mshrs_4.io.schedule.bits.e.valid, UInt<1>(0h0)) node _mshr_request_T_107 = or(sourceE.io.req.ready, _mshr_request_T_106) node _mshr_request_T_108 = and(_mshr_request_T_105, _mshr_request_T_107) node _mshr_request_T_109 = eq(mshrs_4.io.schedule.bits.x.valid, UInt<1>(0h0)) node _mshr_request_T_110 = or(sourceX.io.req.ready, _mshr_request_T_109) node _mshr_request_T_111 = and(_mshr_request_T_108, _mshr_request_T_110) node _mshr_request_T_112 = eq(mshrs_4.io.schedule.bits.dir.valid, UInt<1>(0h0)) node _mshr_request_T_113 = or(directory.io.write.ready, _mshr_request_T_112) node _mshr_request_T_114 = and(_mshr_request_T_111, _mshr_request_T_113) node _mshr_request_T_115 = eq(mshr_stall_abc_5, UInt<1>(0h0)) node _mshr_request_T_116 = and(mshrs_5.io.schedule.valid, _mshr_request_T_115) node _mshr_request_T_117 = eq(mshrs_5.io.schedule.bits.a.valid, UInt<1>(0h0)) node _mshr_request_T_118 = or(sourceA.io.req.ready, _mshr_request_T_117) node _mshr_request_T_119 = and(_mshr_request_T_116, _mshr_request_T_118) node _mshr_request_T_120 = eq(mshrs_5.io.schedule.bits.b.valid, UInt<1>(0h0)) node _mshr_request_T_121 = or(sourceB.io.req.ready, _mshr_request_T_120) node _mshr_request_T_122 = and(_mshr_request_T_119, _mshr_request_T_121) node _mshr_request_T_123 = eq(mshrs_5.io.schedule.bits.c.valid, UInt<1>(0h0)) node _mshr_request_T_124 = or(sourceC.io.req.ready, _mshr_request_T_123) node _mshr_request_T_125 = and(_mshr_request_T_122, _mshr_request_T_124) node _mshr_request_T_126 = eq(mshrs_5.io.schedule.bits.d.valid, UInt<1>(0h0)) node _mshr_request_T_127 = or(sourceD.io.req.ready, _mshr_request_T_126) node _mshr_request_T_128 = and(_mshr_request_T_125, _mshr_request_T_127) node _mshr_request_T_129 = eq(mshrs_5.io.schedule.bits.e.valid, UInt<1>(0h0)) node _mshr_request_T_130 = or(sourceE.io.req.ready, _mshr_request_T_129) node _mshr_request_T_131 = and(_mshr_request_T_128, _mshr_request_T_130) node _mshr_request_T_132 = eq(mshrs_5.io.schedule.bits.x.valid, UInt<1>(0h0)) node _mshr_request_T_133 = or(sourceX.io.req.ready, _mshr_request_T_132) node _mshr_request_T_134 = and(_mshr_request_T_131, _mshr_request_T_133) node _mshr_request_T_135 = eq(mshrs_5.io.schedule.bits.dir.valid, UInt<1>(0h0)) node _mshr_request_T_136 = or(directory.io.write.ready, _mshr_request_T_135) node _mshr_request_T_137 = and(_mshr_request_T_134, _mshr_request_T_136) node _mshr_request_T_138 = eq(mshr_stall_abc_6, UInt<1>(0h0)) node _mshr_request_T_139 = and(mshrs_6.io.schedule.valid, _mshr_request_T_138) node _mshr_request_T_140 = eq(mshrs_6.io.schedule.bits.a.valid, UInt<1>(0h0)) node _mshr_request_T_141 = or(sourceA.io.req.ready, _mshr_request_T_140) node _mshr_request_T_142 = and(_mshr_request_T_139, _mshr_request_T_141) node _mshr_request_T_143 = eq(mshrs_6.io.schedule.bits.b.valid, UInt<1>(0h0)) node _mshr_request_T_144 = or(sourceB.io.req.ready, _mshr_request_T_143) node _mshr_request_T_145 = and(_mshr_request_T_142, _mshr_request_T_144) node _mshr_request_T_146 = eq(mshrs_6.io.schedule.bits.c.valid, UInt<1>(0h0)) node _mshr_request_T_147 = or(sourceC.io.req.ready, _mshr_request_T_146) node _mshr_request_T_148 = and(_mshr_request_T_145, _mshr_request_T_147) node _mshr_request_T_149 = eq(mshrs_6.io.schedule.bits.d.valid, UInt<1>(0h0)) node _mshr_request_T_150 = or(sourceD.io.req.ready, _mshr_request_T_149) node _mshr_request_T_151 = and(_mshr_request_T_148, _mshr_request_T_150) node _mshr_request_T_152 = eq(mshrs_6.io.schedule.bits.e.valid, UInt<1>(0h0)) node _mshr_request_T_153 = or(sourceE.io.req.ready, _mshr_request_T_152) node _mshr_request_T_154 = and(_mshr_request_T_151, _mshr_request_T_153) node _mshr_request_T_155 = eq(mshrs_6.io.schedule.bits.x.valid, UInt<1>(0h0)) node _mshr_request_T_156 = or(sourceX.io.req.ready, _mshr_request_T_155) node _mshr_request_T_157 = and(_mshr_request_T_154, _mshr_request_T_156) node _mshr_request_T_158 = eq(mshrs_6.io.schedule.bits.dir.valid, UInt<1>(0h0)) node _mshr_request_T_159 = or(directory.io.write.ready, _mshr_request_T_158) node _mshr_request_T_160 = and(_mshr_request_T_157, _mshr_request_T_159) node _mshr_request_T_161 = eq(mshr_stall_abc_7, UInt<1>(0h0)) node _mshr_request_T_162 = and(mshrs_7.io.schedule.valid, _mshr_request_T_161) node _mshr_request_T_163 = eq(mshrs_7.io.schedule.bits.a.valid, UInt<1>(0h0)) node _mshr_request_T_164 = or(sourceA.io.req.ready, _mshr_request_T_163) node _mshr_request_T_165 = and(_mshr_request_T_162, _mshr_request_T_164) node _mshr_request_T_166 = eq(mshrs_7.io.schedule.bits.b.valid, UInt<1>(0h0)) node _mshr_request_T_167 = or(sourceB.io.req.ready, _mshr_request_T_166) node _mshr_request_T_168 = and(_mshr_request_T_165, _mshr_request_T_167) node _mshr_request_T_169 = eq(mshrs_7.io.schedule.bits.c.valid, UInt<1>(0h0)) node _mshr_request_T_170 = or(sourceC.io.req.ready, _mshr_request_T_169) node _mshr_request_T_171 = and(_mshr_request_T_168, _mshr_request_T_170) node _mshr_request_T_172 = eq(mshrs_7.io.schedule.bits.d.valid, UInt<1>(0h0)) node _mshr_request_T_173 = or(sourceD.io.req.ready, _mshr_request_T_172) node _mshr_request_T_174 = and(_mshr_request_T_171, _mshr_request_T_173) node _mshr_request_T_175 = eq(mshrs_7.io.schedule.bits.e.valid, UInt<1>(0h0)) node _mshr_request_T_176 = or(sourceE.io.req.ready, _mshr_request_T_175) node _mshr_request_T_177 = and(_mshr_request_T_174, _mshr_request_T_176) node _mshr_request_T_178 = eq(mshrs_7.io.schedule.bits.x.valid, UInt<1>(0h0)) node _mshr_request_T_179 = or(sourceX.io.req.ready, _mshr_request_T_178) node _mshr_request_T_180 = and(_mshr_request_T_177, _mshr_request_T_179) node _mshr_request_T_181 = eq(mshrs_7.io.schedule.bits.dir.valid, UInt<1>(0h0)) node _mshr_request_T_182 = or(directory.io.write.ready, _mshr_request_T_181) node _mshr_request_T_183 = and(_mshr_request_T_180, _mshr_request_T_182) node _mshr_request_T_184 = eq(mshr_stall_abc_8, UInt<1>(0h0)) node _mshr_request_T_185 = and(mshrs_8.io.schedule.valid, _mshr_request_T_184) node _mshr_request_T_186 = eq(mshrs_8.io.schedule.bits.a.valid, UInt<1>(0h0)) node _mshr_request_T_187 = or(sourceA.io.req.ready, _mshr_request_T_186) node _mshr_request_T_188 = and(_mshr_request_T_185, _mshr_request_T_187) node _mshr_request_T_189 = eq(mshrs_8.io.schedule.bits.b.valid, UInt<1>(0h0)) node _mshr_request_T_190 = or(sourceB.io.req.ready, _mshr_request_T_189) node _mshr_request_T_191 = and(_mshr_request_T_188, _mshr_request_T_190) node _mshr_request_T_192 = eq(mshrs_8.io.schedule.bits.c.valid, UInt<1>(0h0)) node _mshr_request_T_193 = or(sourceC.io.req.ready, _mshr_request_T_192) node _mshr_request_T_194 = and(_mshr_request_T_191, _mshr_request_T_193) node _mshr_request_T_195 = eq(mshrs_8.io.schedule.bits.d.valid, UInt<1>(0h0)) node _mshr_request_T_196 = or(sourceD.io.req.ready, _mshr_request_T_195) node _mshr_request_T_197 = and(_mshr_request_T_194, _mshr_request_T_196) node _mshr_request_T_198 = eq(mshrs_8.io.schedule.bits.e.valid, UInt<1>(0h0)) node _mshr_request_T_199 = or(sourceE.io.req.ready, _mshr_request_T_198) node _mshr_request_T_200 = and(_mshr_request_T_197, _mshr_request_T_199) node _mshr_request_T_201 = eq(mshrs_8.io.schedule.bits.x.valid, UInt<1>(0h0)) node _mshr_request_T_202 = or(sourceX.io.req.ready, _mshr_request_T_201) node _mshr_request_T_203 = and(_mshr_request_T_200, _mshr_request_T_202) node _mshr_request_T_204 = eq(mshrs_8.io.schedule.bits.dir.valid, UInt<1>(0h0)) node _mshr_request_T_205 = or(directory.io.write.ready, _mshr_request_T_204) node _mshr_request_T_206 = and(_mshr_request_T_203, _mshr_request_T_205) node _mshr_request_T_207 = eq(mshr_stall_abc_9, UInt<1>(0h0)) node _mshr_request_T_208 = and(mshrs_9.io.schedule.valid, _mshr_request_T_207) node _mshr_request_T_209 = eq(mshrs_9.io.schedule.bits.a.valid, UInt<1>(0h0)) node _mshr_request_T_210 = or(sourceA.io.req.ready, _mshr_request_T_209) node _mshr_request_T_211 = and(_mshr_request_T_208, _mshr_request_T_210) node _mshr_request_T_212 = eq(mshrs_9.io.schedule.bits.b.valid, UInt<1>(0h0)) node _mshr_request_T_213 = or(sourceB.io.req.ready, _mshr_request_T_212) node _mshr_request_T_214 = and(_mshr_request_T_211, _mshr_request_T_213) node _mshr_request_T_215 = eq(mshrs_9.io.schedule.bits.c.valid, UInt<1>(0h0)) node _mshr_request_T_216 = or(sourceC.io.req.ready, _mshr_request_T_215) node _mshr_request_T_217 = and(_mshr_request_T_214, _mshr_request_T_216) node _mshr_request_T_218 = eq(mshrs_9.io.schedule.bits.d.valid, UInt<1>(0h0)) node _mshr_request_T_219 = or(sourceD.io.req.ready, _mshr_request_T_218) node _mshr_request_T_220 = and(_mshr_request_T_217, _mshr_request_T_219) node _mshr_request_T_221 = eq(mshrs_9.io.schedule.bits.e.valid, UInt<1>(0h0)) node _mshr_request_T_222 = or(sourceE.io.req.ready, _mshr_request_T_221) node _mshr_request_T_223 = and(_mshr_request_T_220, _mshr_request_T_222) node _mshr_request_T_224 = eq(mshrs_9.io.schedule.bits.x.valid, UInt<1>(0h0)) node _mshr_request_T_225 = or(sourceX.io.req.ready, _mshr_request_T_224) node _mshr_request_T_226 = and(_mshr_request_T_223, _mshr_request_T_225) node _mshr_request_T_227 = eq(mshrs_9.io.schedule.bits.dir.valid, UInt<1>(0h0)) node _mshr_request_T_228 = or(directory.io.write.ready, _mshr_request_T_227) node _mshr_request_T_229 = and(_mshr_request_T_226, _mshr_request_T_228) node _mshr_request_T_230 = eq(mshr_stall_bc, UInt<1>(0h0)) node _mshr_request_T_231 = and(mshrs_10.io.schedule.valid, _mshr_request_T_230) node _mshr_request_T_232 = eq(mshrs_10.io.schedule.bits.a.valid, UInt<1>(0h0)) node _mshr_request_T_233 = or(sourceA.io.req.ready, _mshr_request_T_232) node _mshr_request_T_234 = and(_mshr_request_T_231, _mshr_request_T_233) node _mshr_request_T_235 = eq(mshrs_10.io.schedule.bits.b.valid, UInt<1>(0h0)) node _mshr_request_T_236 = or(sourceB.io.req.ready, _mshr_request_T_235) node _mshr_request_T_237 = and(_mshr_request_T_234, _mshr_request_T_236) node _mshr_request_T_238 = eq(mshrs_10.io.schedule.bits.c.valid, UInt<1>(0h0)) node _mshr_request_T_239 = or(sourceC.io.req.ready, _mshr_request_T_238) node _mshr_request_T_240 = and(_mshr_request_T_237, _mshr_request_T_239) node _mshr_request_T_241 = eq(mshrs_10.io.schedule.bits.d.valid, UInt<1>(0h0)) node _mshr_request_T_242 = or(sourceD.io.req.ready, _mshr_request_T_241) node _mshr_request_T_243 = and(_mshr_request_T_240, _mshr_request_T_242) node _mshr_request_T_244 = eq(mshrs_10.io.schedule.bits.e.valid, UInt<1>(0h0)) node _mshr_request_T_245 = or(sourceE.io.req.ready, _mshr_request_T_244) node _mshr_request_T_246 = and(_mshr_request_T_243, _mshr_request_T_245) node _mshr_request_T_247 = eq(mshrs_10.io.schedule.bits.x.valid, UInt<1>(0h0)) node _mshr_request_T_248 = or(sourceX.io.req.ready, _mshr_request_T_247) node _mshr_request_T_249 = and(_mshr_request_T_246, _mshr_request_T_248) node _mshr_request_T_250 = eq(mshrs_10.io.schedule.bits.dir.valid, UInt<1>(0h0)) node _mshr_request_T_251 = or(directory.io.write.ready, _mshr_request_T_250) node _mshr_request_T_252 = and(_mshr_request_T_249, _mshr_request_T_251) node _mshr_request_T_253 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _mshr_request_T_254 = and(mshrs_11.io.schedule.valid, _mshr_request_T_253) node _mshr_request_T_255 = eq(mshrs_11.io.schedule.bits.a.valid, UInt<1>(0h0)) node _mshr_request_T_256 = or(sourceA.io.req.ready, _mshr_request_T_255) node _mshr_request_T_257 = and(_mshr_request_T_254, _mshr_request_T_256) node _mshr_request_T_258 = eq(mshrs_11.io.schedule.bits.b.valid, UInt<1>(0h0)) node _mshr_request_T_259 = or(sourceB.io.req.ready, _mshr_request_T_258) node _mshr_request_T_260 = and(_mshr_request_T_257, _mshr_request_T_259) node _mshr_request_T_261 = eq(mshrs_11.io.schedule.bits.c.valid, UInt<1>(0h0)) node _mshr_request_T_262 = or(sourceC.io.req.ready, _mshr_request_T_261) node _mshr_request_T_263 = and(_mshr_request_T_260, _mshr_request_T_262) node _mshr_request_T_264 = eq(mshrs_11.io.schedule.bits.d.valid, UInt<1>(0h0)) node _mshr_request_T_265 = or(sourceD.io.req.ready, _mshr_request_T_264) node _mshr_request_T_266 = and(_mshr_request_T_263, _mshr_request_T_265) node _mshr_request_T_267 = eq(mshrs_11.io.schedule.bits.e.valid, UInt<1>(0h0)) node _mshr_request_T_268 = or(sourceE.io.req.ready, _mshr_request_T_267) node _mshr_request_T_269 = and(_mshr_request_T_266, _mshr_request_T_268) node _mshr_request_T_270 = eq(mshrs_11.io.schedule.bits.x.valid, UInt<1>(0h0)) node _mshr_request_T_271 = or(sourceX.io.req.ready, _mshr_request_T_270) node _mshr_request_T_272 = and(_mshr_request_T_269, _mshr_request_T_271) node _mshr_request_T_273 = eq(mshrs_11.io.schedule.bits.dir.valid, UInt<1>(0h0)) node _mshr_request_T_274 = or(directory.io.write.ready, _mshr_request_T_273) node _mshr_request_T_275 = and(_mshr_request_T_272, _mshr_request_T_274) node mshr_request_lo_lo_hi = cat(_mshr_request_T_68, _mshr_request_T_45) node mshr_request_lo_lo = cat(mshr_request_lo_lo_hi, _mshr_request_T_22) node mshr_request_lo_hi_hi = cat(_mshr_request_T_137, _mshr_request_T_114) node mshr_request_lo_hi = cat(mshr_request_lo_hi_hi, _mshr_request_T_91) node mshr_request_lo = cat(mshr_request_lo_hi, mshr_request_lo_lo) node mshr_request_hi_lo_hi = cat(_mshr_request_T_206, _mshr_request_T_183) node mshr_request_hi_lo = cat(mshr_request_hi_lo_hi, _mshr_request_T_160) node mshr_request_hi_hi_hi = cat(_mshr_request_T_275, _mshr_request_T_252) node mshr_request_hi_hi = cat(mshr_request_hi_hi_hi, _mshr_request_T_229) node mshr_request_hi = cat(mshr_request_hi_hi, mshr_request_hi_lo) node mshr_request = cat(mshr_request_hi, mshr_request_lo) regreset robin_filter : UInt<12>, clock, reset, UInt<12>(0h0) node _robin_request_T = and(mshr_request, robin_filter) node robin_request = cat(mshr_request, _robin_request_T) node _mshr_selectOH2_T = shl(robin_request, 1) node _mshr_selectOH2_T_1 = bits(_mshr_selectOH2_T, 23, 0) node _mshr_selectOH2_T_2 = or(robin_request, _mshr_selectOH2_T_1) node _mshr_selectOH2_T_3 = shl(_mshr_selectOH2_T_2, 2) node _mshr_selectOH2_T_4 = bits(_mshr_selectOH2_T_3, 23, 0) node _mshr_selectOH2_T_5 = or(_mshr_selectOH2_T_2, _mshr_selectOH2_T_4) node _mshr_selectOH2_T_6 = shl(_mshr_selectOH2_T_5, 4) node _mshr_selectOH2_T_7 = bits(_mshr_selectOH2_T_6, 23, 0) node _mshr_selectOH2_T_8 = or(_mshr_selectOH2_T_5, _mshr_selectOH2_T_7) node _mshr_selectOH2_T_9 = shl(_mshr_selectOH2_T_8, 8) node _mshr_selectOH2_T_10 = bits(_mshr_selectOH2_T_9, 23, 0) node _mshr_selectOH2_T_11 = or(_mshr_selectOH2_T_8, _mshr_selectOH2_T_10) node _mshr_selectOH2_T_12 = shl(_mshr_selectOH2_T_11, 16) node _mshr_selectOH2_T_13 = bits(_mshr_selectOH2_T_12, 23, 0) node _mshr_selectOH2_T_14 = or(_mshr_selectOH2_T_11, _mshr_selectOH2_T_13) node _mshr_selectOH2_T_15 = bits(_mshr_selectOH2_T_14, 23, 0) node _mshr_selectOH2_T_16 = shl(_mshr_selectOH2_T_15, 1) node _mshr_selectOH2_T_17 = not(_mshr_selectOH2_T_16) node mshr_selectOH2 = and(_mshr_selectOH2_T_17, robin_request) node _mshr_selectOH_T = bits(mshr_selectOH2, 23, 12) node _mshr_selectOH_T_1 = bits(mshr_selectOH2, 11, 0) node mshr_selectOH = or(_mshr_selectOH_T, _mshr_selectOH_T_1) node mshr_select_hi = bits(mshr_selectOH, 11, 8) node mshr_select_lo = bits(mshr_selectOH, 7, 0) node _mshr_select_T = orr(mshr_select_hi) node _mshr_select_T_1 = or(mshr_select_hi, mshr_select_lo) node mshr_select_hi_1 = bits(_mshr_select_T_1, 7, 4) node mshr_select_lo_1 = bits(_mshr_select_T_1, 3, 0) node _mshr_select_T_2 = orr(mshr_select_hi_1) node _mshr_select_T_3 = or(mshr_select_hi_1, mshr_select_lo_1) node mshr_select_hi_2 = bits(_mshr_select_T_3, 3, 2) node mshr_select_lo_2 = bits(_mshr_select_T_3, 1, 0) node _mshr_select_T_4 = orr(mshr_select_hi_2) node _mshr_select_T_5 = or(mshr_select_hi_2, mshr_select_lo_2) node _mshr_select_T_6 = bits(_mshr_select_T_5, 1, 1) node _mshr_select_T_7 = cat(_mshr_select_T_4, _mshr_select_T_6) node _mshr_select_T_8 = cat(_mshr_select_T_2, _mshr_select_T_7) node mshr_select = cat(_mshr_select_T, _mshr_select_T_8) node _schedule_T = bits(mshr_selectOH, 0, 0) node _schedule_T_1 = bits(mshr_selectOH, 1, 1) node _schedule_T_2 = bits(mshr_selectOH, 2, 2) node _schedule_T_3 = bits(mshr_selectOH, 3, 3) node _schedule_T_4 = bits(mshr_selectOH, 4, 4) node _schedule_T_5 = bits(mshr_selectOH, 5, 5) node _schedule_T_6 = bits(mshr_selectOH, 6, 6) node _schedule_T_7 = bits(mshr_selectOH, 7, 7) node _schedule_T_8 = bits(mshr_selectOH, 8, 8) node _schedule_T_9 = bits(mshr_selectOH, 9, 9) node _schedule_T_10 = bits(mshr_selectOH, 10, 10) node _schedule_T_11 = bits(mshr_selectOH, 11, 11) wire schedule : { a : { valid : UInt<1>, bits : { tag : UInt<9>, set : UInt<11>, param : UInt<3>, source : UInt<4>, block : UInt<1>}}, b : { valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<9>, set : UInt<11>, clients : UInt<1>}}, c : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, source : UInt<4>, tag : UInt<9>, set : UInt<11>, way : UInt<4>, dirty : UInt<1>}}, d : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, sink : UInt<4>, way : UInt<4>, bad : UInt<1>}}, e : { valid : UInt<1>, bits : { sink : UInt<3>}}, x : { valid : UInt<1>, bits : { fail : UInt<1>}}, dir : { valid : UInt<1>, bits : { set : UInt<11>, way : UInt<4>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>}}}, reload : UInt<1>} node _schedule_T_12 = mux(_schedule_T, mshrs_0.io.schedule.bits.reload, UInt<1>(0h0)) node _schedule_T_13 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.reload, UInt<1>(0h0)) node _schedule_T_14 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.reload, UInt<1>(0h0)) node _schedule_T_15 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.reload, UInt<1>(0h0)) node _schedule_T_16 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.reload, UInt<1>(0h0)) node _schedule_T_17 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.reload, UInt<1>(0h0)) node _schedule_T_18 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.reload, UInt<1>(0h0)) node _schedule_T_19 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.reload, UInt<1>(0h0)) node _schedule_T_20 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.reload, UInt<1>(0h0)) node _schedule_T_21 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.reload, UInt<1>(0h0)) node _schedule_T_22 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.reload, UInt<1>(0h0)) node _schedule_T_23 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.reload, UInt<1>(0h0)) node _schedule_T_24 = or(_schedule_T_12, _schedule_T_13) node _schedule_T_25 = or(_schedule_T_24, _schedule_T_14) node _schedule_T_26 = or(_schedule_T_25, _schedule_T_15) node _schedule_T_27 = or(_schedule_T_26, _schedule_T_16) node _schedule_T_28 = or(_schedule_T_27, _schedule_T_17) node _schedule_T_29 = or(_schedule_T_28, _schedule_T_18) node _schedule_T_30 = or(_schedule_T_29, _schedule_T_19) node _schedule_T_31 = or(_schedule_T_30, _schedule_T_20) node _schedule_T_32 = or(_schedule_T_31, _schedule_T_21) node _schedule_T_33 = or(_schedule_T_32, _schedule_T_22) node _schedule_T_34 = or(_schedule_T_33, _schedule_T_23) wire _schedule_WIRE : UInt<1> connect _schedule_WIRE, _schedule_T_34 connect schedule.reload, _schedule_WIRE wire _schedule_WIRE_1 : { valid : UInt<1>, bits : { set : UInt<11>, way : UInt<4>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>}}} wire _schedule_WIRE_2 : { set : UInt<11>, way : UInt<4>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>}} wire _schedule_WIRE_3 : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} node _schedule_T_35 = mux(_schedule_T, mshrs_0.io.schedule.bits.dir.bits.data.tag, UInt<1>(0h0)) node _schedule_T_36 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.dir.bits.data.tag, UInt<1>(0h0)) node _schedule_T_37 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.dir.bits.data.tag, UInt<1>(0h0)) node _schedule_T_38 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.dir.bits.data.tag, UInt<1>(0h0)) node _schedule_T_39 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.dir.bits.data.tag, UInt<1>(0h0)) node _schedule_T_40 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.dir.bits.data.tag, UInt<1>(0h0)) node _schedule_T_41 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.dir.bits.data.tag, UInt<1>(0h0)) node _schedule_T_42 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.dir.bits.data.tag, UInt<1>(0h0)) node _schedule_T_43 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.dir.bits.data.tag, UInt<1>(0h0)) node _schedule_T_44 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.dir.bits.data.tag, UInt<1>(0h0)) node _schedule_T_45 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.dir.bits.data.tag, UInt<1>(0h0)) node _schedule_T_46 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.dir.bits.data.tag, UInt<1>(0h0)) node _schedule_T_47 = or(_schedule_T_35, _schedule_T_36) node _schedule_T_48 = or(_schedule_T_47, _schedule_T_37) node _schedule_T_49 = or(_schedule_T_48, _schedule_T_38) node _schedule_T_50 = or(_schedule_T_49, _schedule_T_39) node _schedule_T_51 = or(_schedule_T_50, _schedule_T_40) node _schedule_T_52 = or(_schedule_T_51, _schedule_T_41) node _schedule_T_53 = or(_schedule_T_52, _schedule_T_42) node _schedule_T_54 = or(_schedule_T_53, _schedule_T_43) node _schedule_T_55 = or(_schedule_T_54, _schedule_T_44) node _schedule_T_56 = or(_schedule_T_55, _schedule_T_45) node _schedule_T_57 = or(_schedule_T_56, _schedule_T_46) wire _schedule_WIRE_4 : UInt<9> connect _schedule_WIRE_4, _schedule_T_57 connect _schedule_WIRE_3.tag, _schedule_WIRE_4 node _schedule_T_58 = mux(_schedule_T, mshrs_0.io.schedule.bits.dir.bits.data.clients, UInt<1>(0h0)) node _schedule_T_59 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.dir.bits.data.clients, UInt<1>(0h0)) node _schedule_T_60 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.dir.bits.data.clients, UInt<1>(0h0)) node _schedule_T_61 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.dir.bits.data.clients, UInt<1>(0h0)) node _schedule_T_62 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.dir.bits.data.clients, UInt<1>(0h0)) node _schedule_T_63 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.dir.bits.data.clients, UInt<1>(0h0)) node _schedule_T_64 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.dir.bits.data.clients, UInt<1>(0h0)) node _schedule_T_65 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.dir.bits.data.clients, UInt<1>(0h0)) node _schedule_T_66 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.dir.bits.data.clients, UInt<1>(0h0)) node _schedule_T_67 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.dir.bits.data.clients, UInt<1>(0h0)) node _schedule_T_68 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.dir.bits.data.clients, UInt<1>(0h0)) node _schedule_T_69 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.dir.bits.data.clients, UInt<1>(0h0)) node _schedule_T_70 = or(_schedule_T_58, _schedule_T_59) node _schedule_T_71 = or(_schedule_T_70, _schedule_T_60) node _schedule_T_72 = or(_schedule_T_71, _schedule_T_61) node _schedule_T_73 = or(_schedule_T_72, _schedule_T_62) node _schedule_T_74 = or(_schedule_T_73, _schedule_T_63) node _schedule_T_75 = or(_schedule_T_74, _schedule_T_64) node _schedule_T_76 = or(_schedule_T_75, _schedule_T_65) node _schedule_T_77 = or(_schedule_T_76, _schedule_T_66) node _schedule_T_78 = or(_schedule_T_77, _schedule_T_67) node _schedule_T_79 = or(_schedule_T_78, _schedule_T_68) node _schedule_T_80 = or(_schedule_T_79, _schedule_T_69) wire _schedule_WIRE_5 : UInt<1> connect _schedule_WIRE_5, _schedule_T_80 connect _schedule_WIRE_3.clients, _schedule_WIRE_5 node _schedule_T_81 = mux(_schedule_T, mshrs_0.io.schedule.bits.dir.bits.data.state, UInt<1>(0h0)) node _schedule_T_82 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.dir.bits.data.state, UInt<1>(0h0)) node _schedule_T_83 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.dir.bits.data.state, UInt<1>(0h0)) node _schedule_T_84 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.dir.bits.data.state, UInt<1>(0h0)) node _schedule_T_85 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.dir.bits.data.state, UInt<1>(0h0)) node _schedule_T_86 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.dir.bits.data.state, UInt<1>(0h0)) node _schedule_T_87 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.dir.bits.data.state, UInt<1>(0h0)) node _schedule_T_88 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.dir.bits.data.state, UInt<1>(0h0)) node _schedule_T_89 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.dir.bits.data.state, UInt<1>(0h0)) node _schedule_T_90 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.dir.bits.data.state, UInt<1>(0h0)) node _schedule_T_91 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.dir.bits.data.state, UInt<1>(0h0)) node _schedule_T_92 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.dir.bits.data.state, UInt<1>(0h0)) node _schedule_T_93 = or(_schedule_T_81, _schedule_T_82) node _schedule_T_94 = or(_schedule_T_93, _schedule_T_83) node _schedule_T_95 = or(_schedule_T_94, _schedule_T_84) node _schedule_T_96 = or(_schedule_T_95, _schedule_T_85) node _schedule_T_97 = or(_schedule_T_96, _schedule_T_86) node _schedule_T_98 = or(_schedule_T_97, _schedule_T_87) node _schedule_T_99 = or(_schedule_T_98, _schedule_T_88) node _schedule_T_100 = or(_schedule_T_99, _schedule_T_89) node _schedule_T_101 = or(_schedule_T_100, _schedule_T_90) node _schedule_T_102 = or(_schedule_T_101, _schedule_T_91) node _schedule_T_103 = or(_schedule_T_102, _schedule_T_92) wire _schedule_WIRE_6 : UInt<2> connect _schedule_WIRE_6, _schedule_T_103 connect _schedule_WIRE_3.state, _schedule_WIRE_6 node _schedule_T_104 = mux(_schedule_T, mshrs_0.io.schedule.bits.dir.bits.data.dirty, UInt<1>(0h0)) node _schedule_T_105 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.dir.bits.data.dirty, UInt<1>(0h0)) node _schedule_T_106 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.dir.bits.data.dirty, UInt<1>(0h0)) node _schedule_T_107 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.dir.bits.data.dirty, UInt<1>(0h0)) node _schedule_T_108 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.dir.bits.data.dirty, UInt<1>(0h0)) node _schedule_T_109 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.dir.bits.data.dirty, UInt<1>(0h0)) node _schedule_T_110 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.dir.bits.data.dirty, UInt<1>(0h0)) node _schedule_T_111 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.dir.bits.data.dirty, UInt<1>(0h0)) node _schedule_T_112 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.dir.bits.data.dirty, UInt<1>(0h0)) node _schedule_T_113 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.dir.bits.data.dirty, UInt<1>(0h0)) node _schedule_T_114 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.dir.bits.data.dirty, UInt<1>(0h0)) node _schedule_T_115 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.dir.bits.data.dirty, UInt<1>(0h0)) node _schedule_T_116 = or(_schedule_T_104, _schedule_T_105) node _schedule_T_117 = or(_schedule_T_116, _schedule_T_106) node _schedule_T_118 = or(_schedule_T_117, _schedule_T_107) node _schedule_T_119 = or(_schedule_T_118, _schedule_T_108) node _schedule_T_120 = or(_schedule_T_119, _schedule_T_109) node _schedule_T_121 = or(_schedule_T_120, _schedule_T_110) node _schedule_T_122 = or(_schedule_T_121, _schedule_T_111) node _schedule_T_123 = or(_schedule_T_122, _schedule_T_112) node _schedule_T_124 = or(_schedule_T_123, _schedule_T_113) node _schedule_T_125 = or(_schedule_T_124, _schedule_T_114) node _schedule_T_126 = or(_schedule_T_125, _schedule_T_115) wire _schedule_WIRE_7 : UInt<1> connect _schedule_WIRE_7, _schedule_T_126 connect _schedule_WIRE_3.dirty, _schedule_WIRE_7 connect _schedule_WIRE_2.data, _schedule_WIRE_3 node _schedule_T_127 = mux(_schedule_T, mshrs_0.io.schedule.bits.dir.bits.way, UInt<1>(0h0)) node _schedule_T_128 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.dir.bits.way, UInt<1>(0h0)) node _schedule_T_129 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.dir.bits.way, UInt<1>(0h0)) node _schedule_T_130 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.dir.bits.way, UInt<1>(0h0)) node _schedule_T_131 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.dir.bits.way, UInt<1>(0h0)) node _schedule_T_132 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.dir.bits.way, UInt<1>(0h0)) node _schedule_T_133 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.dir.bits.way, UInt<1>(0h0)) node _schedule_T_134 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.dir.bits.way, UInt<1>(0h0)) node _schedule_T_135 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.dir.bits.way, UInt<1>(0h0)) node _schedule_T_136 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.dir.bits.way, UInt<1>(0h0)) node _schedule_T_137 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.dir.bits.way, UInt<1>(0h0)) node _schedule_T_138 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.dir.bits.way, UInt<1>(0h0)) node _schedule_T_139 = or(_schedule_T_127, _schedule_T_128) node _schedule_T_140 = or(_schedule_T_139, _schedule_T_129) node _schedule_T_141 = or(_schedule_T_140, _schedule_T_130) node _schedule_T_142 = or(_schedule_T_141, _schedule_T_131) node _schedule_T_143 = or(_schedule_T_142, _schedule_T_132) node _schedule_T_144 = or(_schedule_T_143, _schedule_T_133) node _schedule_T_145 = or(_schedule_T_144, _schedule_T_134) node _schedule_T_146 = or(_schedule_T_145, _schedule_T_135) node _schedule_T_147 = or(_schedule_T_146, _schedule_T_136) node _schedule_T_148 = or(_schedule_T_147, _schedule_T_137) node _schedule_T_149 = or(_schedule_T_148, _schedule_T_138) wire _schedule_WIRE_8 : UInt<4> connect _schedule_WIRE_8, _schedule_T_149 connect _schedule_WIRE_2.way, _schedule_WIRE_8 node _schedule_T_150 = mux(_schedule_T, mshrs_0.io.schedule.bits.dir.bits.set, UInt<1>(0h0)) node _schedule_T_151 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.dir.bits.set, UInt<1>(0h0)) node _schedule_T_152 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.dir.bits.set, UInt<1>(0h0)) node _schedule_T_153 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.dir.bits.set, UInt<1>(0h0)) node _schedule_T_154 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.dir.bits.set, UInt<1>(0h0)) node _schedule_T_155 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.dir.bits.set, UInt<1>(0h0)) node _schedule_T_156 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.dir.bits.set, UInt<1>(0h0)) node _schedule_T_157 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.dir.bits.set, UInt<1>(0h0)) node _schedule_T_158 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.dir.bits.set, UInt<1>(0h0)) node _schedule_T_159 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.dir.bits.set, UInt<1>(0h0)) node _schedule_T_160 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.dir.bits.set, UInt<1>(0h0)) node _schedule_T_161 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.dir.bits.set, UInt<1>(0h0)) node _schedule_T_162 = or(_schedule_T_150, _schedule_T_151) node _schedule_T_163 = or(_schedule_T_162, _schedule_T_152) node _schedule_T_164 = or(_schedule_T_163, _schedule_T_153) node _schedule_T_165 = or(_schedule_T_164, _schedule_T_154) node _schedule_T_166 = or(_schedule_T_165, _schedule_T_155) node _schedule_T_167 = or(_schedule_T_166, _schedule_T_156) node _schedule_T_168 = or(_schedule_T_167, _schedule_T_157) node _schedule_T_169 = or(_schedule_T_168, _schedule_T_158) node _schedule_T_170 = or(_schedule_T_169, _schedule_T_159) node _schedule_T_171 = or(_schedule_T_170, _schedule_T_160) node _schedule_T_172 = or(_schedule_T_171, _schedule_T_161) wire _schedule_WIRE_9 : UInt<11> connect _schedule_WIRE_9, _schedule_T_172 connect _schedule_WIRE_2.set, _schedule_WIRE_9 connect _schedule_WIRE_1.bits, _schedule_WIRE_2 node _schedule_T_173 = mux(_schedule_T, mshrs_0.io.schedule.bits.dir.valid, UInt<1>(0h0)) node _schedule_T_174 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.dir.valid, UInt<1>(0h0)) node _schedule_T_175 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.dir.valid, UInt<1>(0h0)) node _schedule_T_176 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.dir.valid, UInt<1>(0h0)) node _schedule_T_177 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.dir.valid, UInt<1>(0h0)) node _schedule_T_178 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.dir.valid, UInt<1>(0h0)) node _schedule_T_179 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.dir.valid, UInt<1>(0h0)) node _schedule_T_180 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.dir.valid, UInt<1>(0h0)) node _schedule_T_181 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.dir.valid, UInt<1>(0h0)) node _schedule_T_182 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.dir.valid, UInt<1>(0h0)) node _schedule_T_183 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.dir.valid, UInt<1>(0h0)) node _schedule_T_184 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.dir.valid, UInt<1>(0h0)) node _schedule_T_185 = or(_schedule_T_173, _schedule_T_174) node _schedule_T_186 = or(_schedule_T_185, _schedule_T_175) node _schedule_T_187 = or(_schedule_T_186, _schedule_T_176) node _schedule_T_188 = or(_schedule_T_187, _schedule_T_177) node _schedule_T_189 = or(_schedule_T_188, _schedule_T_178) node _schedule_T_190 = or(_schedule_T_189, _schedule_T_179) node _schedule_T_191 = or(_schedule_T_190, _schedule_T_180) node _schedule_T_192 = or(_schedule_T_191, _schedule_T_181) node _schedule_T_193 = or(_schedule_T_192, _schedule_T_182) node _schedule_T_194 = or(_schedule_T_193, _schedule_T_183) node _schedule_T_195 = or(_schedule_T_194, _schedule_T_184) wire _schedule_WIRE_10 : UInt<1> connect _schedule_WIRE_10, _schedule_T_195 connect _schedule_WIRE_1.valid, _schedule_WIRE_10 connect schedule.dir, _schedule_WIRE_1 wire _schedule_WIRE_11 : { valid : UInt<1>, bits : { fail : UInt<1>}} wire _schedule_WIRE_12 : { fail : UInt<1>} node _schedule_T_196 = mux(_schedule_T, mshrs_0.io.schedule.bits.x.bits.fail, UInt<1>(0h0)) node _schedule_T_197 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.x.bits.fail, UInt<1>(0h0)) node _schedule_T_198 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.x.bits.fail, UInt<1>(0h0)) node _schedule_T_199 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.x.bits.fail, UInt<1>(0h0)) node _schedule_T_200 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.x.bits.fail, UInt<1>(0h0)) node _schedule_T_201 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.x.bits.fail, UInt<1>(0h0)) node _schedule_T_202 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.x.bits.fail, UInt<1>(0h0)) node _schedule_T_203 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.x.bits.fail, UInt<1>(0h0)) node _schedule_T_204 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.x.bits.fail, UInt<1>(0h0)) node _schedule_T_205 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.x.bits.fail, UInt<1>(0h0)) node _schedule_T_206 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.x.bits.fail, UInt<1>(0h0)) node _schedule_T_207 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.x.bits.fail, UInt<1>(0h0)) node _schedule_T_208 = or(_schedule_T_196, _schedule_T_197) node _schedule_T_209 = or(_schedule_T_208, _schedule_T_198) node _schedule_T_210 = or(_schedule_T_209, _schedule_T_199) node _schedule_T_211 = or(_schedule_T_210, _schedule_T_200) node _schedule_T_212 = or(_schedule_T_211, _schedule_T_201) node _schedule_T_213 = or(_schedule_T_212, _schedule_T_202) node _schedule_T_214 = or(_schedule_T_213, _schedule_T_203) node _schedule_T_215 = or(_schedule_T_214, _schedule_T_204) node _schedule_T_216 = or(_schedule_T_215, _schedule_T_205) node _schedule_T_217 = or(_schedule_T_216, _schedule_T_206) node _schedule_T_218 = or(_schedule_T_217, _schedule_T_207) wire _schedule_WIRE_13 : UInt<1> connect _schedule_WIRE_13, _schedule_T_218 connect _schedule_WIRE_12.fail, _schedule_WIRE_13 connect _schedule_WIRE_11.bits, _schedule_WIRE_12 node _schedule_T_219 = mux(_schedule_T, mshrs_0.io.schedule.bits.x.valid, UInt<1>(0h0)) node _schedule_T_220 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.x.valid, UInt<1>(0h0)) node _schedule_T_221 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.x.valid, UInt<1>(0h0)) node _schedule_T_222 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.x.valid, UInt<1>(0h0)) node _schedule_T_223 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.x.valid, UInt<1>(0h0)) node _schedule_T_224 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.x.valid, UInt<1>(0h0)) node _schedule_T_225 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.x.valid, UInt<1>(0h0)) node _schedule_T_226 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.x.valid, UInt<1>(0h0)) node _schedule_T_227 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.x.valid, UInt<1>(0h0)) node _schedule_T_228 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.x.valid, UInt<1>(0h0)) node _schedule_T_229 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.x.valid, UInt<1>(0h0)) node _schedule_T_230 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.x.valid, UInt<1>(0h0)) node _schedule_T_231 = or(_schedule_T_219, _schedule_T_220) node _schedule_T_232 = or(_schedule_T_231, _schedule_T_221) node _schedule_T_233 = or(_schedule_T_232, _schedule_T_222) node _schedule_T_234 = or(_schedule_T_233, _schedule_T_223) node _schedule_T_235 = or(_schedule_T_234, _schedule_T_224) node _schedule_T_236 = or(_schedule_T_235, _schedule_T_225) node _schedule_T_237 = or(_schedule_T_236, _schedule_T_226) node _schedule_T_238 = or(_schedule_T_237, _schedule_T_227) node _schedule_T_239 = or(_schedule_T_238, _schedule_T_228) node _schedule_T_240 = or(_schedule_T_239, _schedule_T_229) node _schedule_T_241 = or(_schedule_T_240, _schedule_T_230) wire _schedule_WIRE_14 : UInt<1> connect _schedule_WIRE_14, _schedule_T_241 connect _schedule_WIRE_11.valid, _schedule_WIRE_14 connect schedule.x, _schedule_WIRE_11 wire _schedule_WIRE_15 : { valid : UInt<1>, bits : { sink : UInt<3>}} wire _schedule_WIRE_16 : { sink : UInt<3>} node _schedule_T_242 = mux(_schedule_T, mshrs_0.io.schedule.bits.e.bits.sink, UInt<1>(0h0)) node _schedule_T_243 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.e.bits.sink, UInt<1>(0h0)) node _schedule_T_244 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.e.bits.sink, UInt<1>(0h0)) node _schedule_T_245 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.e.bits.sink, UInt<1>(0h0)) node _schedule_T_246 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.e.bits.sink, UInt<1>(0h0)) node _schedule_T_247 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.e.bits.sink, UInt<1>(0h0)) node _schedule_T_248 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.e.bits.sink, UInt<1>(0h0)) node _schedule_T_249 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.e.bits.sink, UInt<1>(0h0)) node _schedule_T_250 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.e.bits.sink, UInt<1>(0h0)) node _schedule_T_251 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.e.bits.sink, UInt<1>(0h0)) node _schedule_T_252 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.e.bits.sink, UInt<1>(0h0)) node _schedule_T_253 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.e.bits.sink, UInt<1>(0h0)) node _schedule_T_254 = or(_schedule_T_242, _schedule_T_243) node _schedule_T_255 = or(_schedule_T_254, _schedule_T_244) node _schedule_T_256 = or(_schedule_T_255, _schedule_T_245) node _schedule_T_257 = or(_schedule_T_256, _schedule_T_246) node _schedule_T_258 = or(_schedule_T_257, _schedule_T_247) node _schedule_T_259 = or(_schedule_T_258, _schedule_T_248) node _schedule_T_260 = or(_schedule_T_259, _schedule_T_249) node _schedule_T_261 = or(_schedule_T_260, _schedule_T_250) node _schedule_T_262 = or(_schedule_T_261, _schedule_T_251) node _schedule_T_263 = or(_schedule_T_262, _schedule_T_252) node _schedule_T_264 = or(_schedule_T_263, _schedule_T_253) wire _schedule_WIRE_17 : UInt<3> connect _schedule_WIRE_17, _schedule_T_264 connect _schedule_WIRE_16.sink, _schedule_WIRE_17 connect _schedule_WIRE_15.bits, _schedule_WIRE_16 node _schedule_T_265 = mux(_schedule_T, mshrs_0.io.schedule.bits.e.valid, UInt<1>(0h0)) node _schedule_T_266 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.e.valid, UInt<1>(0h0)) node _schedule_T_267 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.e.valid, UInt<1>(0h0)) node _schedule_T_268 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.e.valid, UInt<1>(0h0)) node _schedule_T_269 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.e.valid, UInt<1>(0h0)) node _schedule_T_270 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.e.valid, UInt<1>(0h0)) node _schedule_T_271 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.e.valid, UInt<1>(0h0)) node _schedule_T_272 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.e.valid, UInt<1>(0h0)) node _schedule_T_273 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.e.valid, UInt<1>(0h0)) node _schedule_T_274 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.e.valid, UInt<1>(0h0)) node _schedule_T_275 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.e.valid, UInt<1>(0h0)) node _schedule_T_276 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.e.valid, UInt<1>(0h0)) node _schedule_T_277 = or(_schedule_T_265, _schedule_T_266) node _schedule_T_278 = or(_schedule_T_277, _schedule_T_267) node _schedule_T_279 = or(_schedule_T_278, _schedule_T_268) node _schedule_T_280 = or(_schedule_T_279, _schedule_T_269) node _schedule_T_281 = or(_schedule_T_280, _schedule_T_270) node _schedule_T_282 = or(_schedule_T_281, _schedule_T_271) node _schedule_T_283 = or(_schedule_T_282, _schedule_T_272) node _schedule_T_284 = or(_schedule_T_283, _schedule_T_273) node _schedule_T_285 = or(_schedule_T_284, _schedule_T_274) node _schedule_T_286 = or(_schedule_T_285, _schedule_T_275) node _schedule_T_287 = or(_schedule_T_286, _schedule_T_276) wire _schedule_WIRE_18 : UInt<1> connect _schedule_WIRE_18, _schedule_T_287 connect _schedule_WIRE_15.valid, _schedule_WIRE_18 connect schedule.e, _schedule_WIRE_15 wire _schedule_WIRE_19 : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, sink : UInt<4>, way : UInt<4>, bad : UInt<1>}} wire _schedule_WIRE_20 : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, sink : UInt<4>, way : UInt<4>, bad : UInt<1>} node _schedule_T_288 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.bad, UInt<1>(0h0)) node _schedule_T_289 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.bad, UInt<1>(0h0)) node _schedule_T_290 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.bad, UInt<1>(0h0)) node _schedule_T_291 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.bad, UInt<1>(0h0)) node _schedule_T_292 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.bad, UInt<1>(0h0)) node _schedule_T_293 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.bad, UInt<1>(0h0)) node _schedule_T_294 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.bad, UInt<1>(0h0)) node _schedule_T_295 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.bad, UInt<1>(0h0)) node _schedule_T_296 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.bad, UInt<1>(0h0)) node _schedule_T_297 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.bad, UInt<1>(0h0)) node _schedule_T_298 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.bad, UInt<1>(0h0)) node _schedule_T_299 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.bad, UInt<1>(0h0)) node _schedule_T_300 = or(_schedule_T_288, _schedule_T_289) node _schedule_T_301 = or(_schedule_T_300, _schedule_T_290) node _schedule_T_302 = or(_schedule_T_301, _schedule_T_291) node _schedule_T_303 = or(_schedule_T_302, _schedule_T_292) node _schedule_T_304 = or(_schedule_T_303, _schedule_T_293) node _schedule_T_305 = or(_schedule_T_304, _schedule_T_294) node _schedule_T_306 = or(_schedule_T_305, _schedule_T_295) node _schedule_T_307 = or(_schedule_T_306, _schedule_T_296) node _schedule_T_308 = or(_schedule_T_307, _schedule_T_297) node _schedule_T_309 = or(_schedule_T_308, _schedule_T_298) node _schedule_T_310 = or(_schedule_T_309, _schedule_T_299) wire _schedule_WIRE_21 : UInt<1> connect _schedule_WIRE_21, _schedule_T_310 connect _schedule_WIRE_20.bad, _schedule_WIRE_21 node _schedule_T_311 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.way, UInt<1>(0h0)) node _schedule_T_312 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.way, UInt<1>(0h0)) node _schedule_T_313 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.way, UInt<1>(0h0)) node _schedule_T_314 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.way, UInt<1>(0h0)) node _schedule_T_315 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.way, UInt<1>(0h0)) node _schedule_T_316 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.way, UInt<1>(0h0)) node _schedule_T_317 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.way, UInt<1>(0h0)) node _schedule_T_318 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.way, UInt<1>(0h0)) node _schedule_T_319 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.way, UInt<1>(0h0)) node _schedule_T_320 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.way, UInt<1>(0h0)) node _schedule_T_321 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.way, UInt<1>(0h0)) node _schedule_T_322 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.way, UInt<1>(0h0)) node _schedule_T_323 = or(_schedule_T_311, _schedule_T_312) node _schedule_T_324 = or(_schedule_T_323, _schedule_T_313) node _schedule_T_325 = or(_schedule_T_324, _schedule_T_314) node _schedule_T_326 = or(_schedule_T_325, _schedule_T_315) node _schedule_T_327 = or(_schedule_T_326, _schedule_T_316) node _schedule_T_328 = or(_schedule_T_327, _schedule_T_317) node _schedule_T_329 = or(_schedule_T_328, _schedule_T_318) node _schedule_T_330 = or(_schedule_T_329, _schedule_T_319) node _schedule_T_331 = or(_schedule_T_330, _schedule_T_320) node _schedule_T_332 = or(_schedule_T_331, _schedule_T_321) node _schedule_T_333 = or(_schedule_T_332, _schedule_T_322) wire _schedule_WIRE_22 : UInt<4> connect _schedule_WIRE_22, _schedule_T_333 connect _schedule_WIRE_20.way, _schedule_WIRE_22 node _schedule_T_334 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.sink, UInt<1>(0h0)) node _schedule_T_335 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.sink, UInt<1>(0h0)) node _schedule_T_336 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.sink, UInt<1>(0h0)) node _schedule_T_337 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.sink, UInt<1>(0h0)) node _schedule_T_338 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.sink, UInt<1>(0h0)) node _schedule_T_339 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.sink, UInt<1>(0h0)) node _schedule_T_340 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.sink, UInt<1>(0h0)) node _schedule_T_341 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.sink, UInt<1>(0h0)) node _schedule_T_342 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.sink, UInt<1>(0h0)) node _schedule_T_343 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.sink, UInt<1>(0h0)) node _schedule_T_344 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.sink, UInt<1>(0h0)) node _schedule_T_345 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.sink, UInt<1>(0h0)) node _schedule_T_346 = or(_schedule_T_334, _schedule_T_335) node _schedule_T_347 = or(_schedule_T_346, _schedule_T_336) node _schedule_T_348 = or(_schedule_T_347, _schedule_T_337) node _schedule_T_349 = or(_schedule_T_348, _schedule_T_338) node _schedule_T_350 = or(_schedule_T_349, _schedule_T_339) node _schedule_T_351 = or(_schedule_T_350, _schedule_T_340) node _schedule_T_352 = or(_schedule_T_351, _schedule_T_341) node _schedule_T_353 = or(_schedule_T_352, _schedule_T_342) node _schedule_T_354 = or(_schedule_T_353, _schedule_T_343) node _schedule_T_355 = or(_schedule_T_354, _schedule_T_344) node _schedule_T_356 = or(_schedule_T_355, _schedule_T_345) wire _schedule_WIRE_23 : UInt<4> connect _schedule_WIRE_23, _schedule_T_356 connect _schedule_WIRE_20.sink, _schedule_WIRE_23 node _schedule_T_357 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.set, UInt<1>(0h0)) node _schedule_T_358 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.set, UInt<1>(0h0)) node _schedule_T_359 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.set, UInt<1>(0h0)) node _schedule_T_360 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.set, UInt<1>(0h0)) node _schedule_T_361 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.set, UInt<1>(0h0)) node _schedule_T_362 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.set, UInt<1>(0h0)) node _schedule_T_363 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.set, UInt<1>(0h0)) node _schedule_T_364 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.set, UInt<1>(0h0)) node _schedule_T_365 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.set, UInt<1>(0h0)) node _schedule_T_366 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.set, UInt<1>(0h0)) node _schedule_T_367 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.set, UInt<1>(0h0)) node _schedule_T_368 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.set, UInt<1>(0h0)) node _schedule_T_369 = or(_schedule_T_357, _schedule_T_358) node _schedule_T_370 = or(_schedule_T_369, _schedule_T_359) node _schedule_T_371 = or(_schedule_T_370, _schedule_T_360) node _schedule_T_372 = or(_schedule_T_371, _schedule_T_361) node _schedule_T_373 = or(_schedule_T_372, _schedule_T_362) node _schedule_T_374 = or(_schedule_T_373, _schedule_T_363) node _schedule_T_375 = or(_schedule_T_374, _schedule_T_364) node _schedule_T_376 = or(_schedule_T_375, _schedule_T_365) node _schedule_T_377 = or(_schedule_T_376, _schedule_T_366) node _schedule_T_378 = or(_schedule_T_377, _schedule_T_367) node _schedule_T_379 = or(_schedule_T_378, _schedule_T_368) wire _schedule_WIRE_24 : UInt<11> connect _schedule_WIRE_24, _schedule_T_379 connect _schedule_WIRE_20.set, _schedule_WIRE_24 node _schedule_T_380 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.put, UInt<1>(0h0)) node _schedule_T_381 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.put, UInt<1>(0h0)) node _schedule_T_382 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.put, UInt<1>(0h0)) node _schedule_T_383 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.put, UInt<1>(0h0)) node _schedule_T_384 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.put, UInt<1>(0h0)) node _schedule_T_385 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.put, UInt<1>(0h0)) node _schedule_T_386 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.put, UInt<1>(0h0)) node _schedule_T_387 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.put, UInt<1>(0h0)) node _schedule_T_388 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.put, UInt<1>(0h0)) node _schedule_T_389 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.put, UInt<1>(0h0)) node _schedule_T_390 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.put, UInt<1>(0h0)) node _schedule_T_391 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.put, UInt<1>(0h0)) node _schedule_T_392 = or(_schedule_T_380, _schedule_T_381) node _schedule_T_393 = or(_schedule_T_392, _schedule_T_382) node _schedule_T_394 = or(_schedule_T_393, _schedule_T_383) node _schedule_T_395 = or(_schedule_T_394, _schedule_T_384) node _schedule_T_396 = or(_schedule_T_395, _schedule_T_385) node _schedule_T_397 = or(_schedule_T_396, _schedule_T_386) node _schedule_T_398 = or(_schedule_T_397, _schedule_T_387) node _schedule_T_399 = or(_schedule_T_398, _schedule_T_388) node _schedule_T_400 = or(_schedule_T_399, _schedule_T_389) node _schedule_T_401 = or(_schedule_T_400, _schedule_T_390) node _schedule_T_402 = or(_schedule_T_401, _schedule_T_391) wire _schedule_WIRE_25 : UInt<6> connect _schedule_WIRE_25, _schedule_T_402 connect _schedule_WIRE_20.put, _schedule_WIRE_25 node _schedule_T_403 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.offset, UInt<1>(0h0)) node _schedule_T_404 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.offset, UInt<1>(0h0)) node _schedule_T_405 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.offset, UInt<1>(0h0)) node _schedule_T_406 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.offset, UInt<1>(0h0)) node _schedule_T_407 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.offset, UInt<1>(0h0)) node _schedule_T_408 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.offset, UInt<1>(0h0)) node _schedule_T_409 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.offset, UInt<1>(0h0)) node _schedule_T_410 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.offset, UInt<1>(0h0)) node _schedule_T_411 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.offset, UInt<1>(0h0)) node _schedule_T_412 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.offset, UInt<1>(0h0)) node _schedule_T_413 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.offset, UInt<1>(0h0)) node _schedule_T_414 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.offset, UInt<1>(0h0)) node _schedule_T_415 = or(_schedule_T_403, _schedule_T_404) node _schedule_T_416 = or(_schedule_T_415, _schedule_T_405) node _schedule_T_417 = or(_schedule_T_416, _schedule_T_406) node _schedule_T_418 = or(_schedule_T_417, _schedule_T_407) node _schedule_T_419 = or(_schedule_T_418, _schedule_T_408) node _schedule_T_420 = or(_schedule_T_419, _schedule_T_409) node _schedule_T_421 = or(_schedule_T_420, _schedule_T_410) node _schedule_T_422 = or(_schedule_T_421, _schedule_T_411) node _schedule_T_423 = or(_schedule_T_422, _schedule_T_412) node _schedule_T_424 = or(_schedule_T_423, _schedule_T_413) node _schedule_T_425 = or(_schedule_T_424, _schedule_T_414) wire _schedule_WIRE_26 : UInt<6> connect _schedule_WIRE_26, _schedule_T_425 connect _schedule_WIRE_20.offset, _schedule_WIRE_26 node _schedule_T_426 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.tag, UInt<1>(0h0)) node _schedule_T_427 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.tag, UInt<1>(0h0)) node _schedule_T_428 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.tag, UInt<1>(0h0)) node _schedule_T_429 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.tag, UInt<1>(0h0)) node _schedule_T_430 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.tag, UInt<1>(0h0)) node _schedule_T_431 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.tag, UInt<1>(0h0)) node _schedule_T_432 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.tag, UInt<1>(0h0)) node _schedule_T_433 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.tag, UInt<1>(0h0)) node _schedule_T_434 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.tag, UInt<1>(0h0)) node _schedule_T_435 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.tag, UInt<1>(0h0)) node _schedule_T_436 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.tag, UInt<1>(0h0)) node _schedule_T_437 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.tag, UInt<1>(0h0)) node _schedule_T_438 = or(_schedule_T_426, _schedule_T_427) node _schedule_T_439 = or(_schedule_T_438, _schedule_T_428) node _schedule_T_440 = or(_schedule_T_439, _schedule_T_429) node _schedule_T_441 = or(_schedule_T_440, _schedule_T_430) node _schedule_T_442 = or(_schedule_T_441, _schedule_T_431) node _schedule_T_443 = or(_schedule_T_442, _schedule_T_432) node _schedule_T_444 = or(_schedule_T_443, _schedule_T_433) node _schedule_T_445 = or(_schedule_T_444, _schedule_T_434) node _schedule_T_446 = or(_schedule_T_445, _schedule_T_435) node _schedule_T_447 = or(_schedule_T_446, _schedule_T_436) node _schedule_T_448 = or(_schedule_T_447, _schedule_T_437) wire _schedule_WIRE_27 : UInt<9> connect _schedule_WIRE_27, _schedule_T_448 connect _schedule_WIRE_20.tag, _schedule_WIRE_27 node _schedule_T_449 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.source, UInt<1>(0h0)) node _schedule_T_450 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.source, UInt<1>(0h0)) node _schedule_T_451 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.source, UInt<1>(0h0)) node _schedule_T_452 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.source, UInt<1>(0h0)) node _schedule_T_453 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.source, UInt<1>(0h0)) node _schedule_T_454 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.source, UInt<1>(0h0)) node _schedule_T_455 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.source, UInt<1>(0h0)) node _schedule_T_456 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.source, UInt<1>(0h0)) node _schedule_T_457 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.source, UInt<1>(0h0)) node _schedule_T_458 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.source, UInt<1>(0h0)) node _schedule_T_459 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.source, UInt<1>(0h0)) node _schedule_T_460 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.source, UInt<1>(0h0)) node _schedule_T_461 = or(_schedule_T_449, _schedule_T_450) node _schedule_T_462 = or(_schedule_T_461, _schedule_T_451) node _schedule_T_463 = or(_schedule_T_462, _schedule_T_452) node _schedule_T_464 = or(_schedule_T_463, _schedule_T_453) node _schedule_T_465 = or(_schedule_T_464, _schedule_T_454) node _schedule_T_466 = or(_schedule_T_465, _schedule_T_455) node _schedule_T_467 = or(_schedule_T_466, _schedule_T_456) node _schedule_T_468 = or(_schedule_T_467, _schedule_T_457) node _schedule_T_469 = or(_schedule_T_468, _schedule_T_458) node _schedule_T_470 = or(_schedule_T_469, _schedule_T_459) node _schedule_T_471 = or(_schedule_T_470, _schedule_T_460) wire _schedule_WIRE_28 : UInt<6> connect _schedule_WIRE_28, _schedule_T_471 connect _schedule_WIRE_20.source, _schedule_WIRE_28 node _schedule_T_472 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.size, UInt<1>(0h0)) node _schedule_T_473 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.size, UInt<1>(0h0)) node _schedule_T_474 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.size, UInt<1>(0h0)) node _schedule_T_475 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.size, UInt<1>(0h0)) node _schedule_T_476 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.size, UInt<1>(0h0)) node _schedule_T_477 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.size, UInt<1>(0h0)) node _schedule_T_478 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.size, UInt<1>(0h0)) node _schedule_T_479 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.size, UInt<1>(0h0)) node _schedule_T_480 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.size, UInt<1>(0h0)) node _schedule_T_481 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.size, UInt<1>(0h0)) node _schedule_T_482 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.size, UInt<1>(0h0)) node _schedule_T_483 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.size, UInt<1>(0h0)) node _schedule_T_484 = or(_schedule_T_472, _schedule_T_473) node _schedule_T_485 = or(_schedule_T_484, _schedule_T_474) node _schedule_T_486 = or(_schedule_T_485, _schedule_T_475) node _schedule_T_487 = or(_schedule_T_486, _schedule_T_476) node _schedule_T_488 = or(_schedule_T_487, _schedule_T_477) node _schedule_T_489 = or(_schedule_T_488, _schedule_T_478) node _schedule_T_490 = or(_schedule_T_489, _schedule_T_479) node _schedule_T_491 = or(_schedule_T_490, _schedule_T_480) node _schedule_T_492 = or(_schedule_T_491, _schedule_T_481) node _schedule_T_493 = or(_schedule_T_492, _schedule_T_482) node _schedule_T_494 = or(_schedule_T_493, _schedule_T_483) wire _schedule_WIRE_29 : UInt<3> connect _schedule_WIRE_29, _schedule_T_494 connect _schedule_WIRE_20.size, _schedule_WIRE_29 node _schedule_T_495 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.param, UInt<1>(0h0)) node _schedule_T_496 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.param, UInt<1>(0h0)) node _schedule_T_497 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.param, UInt<1>(0h0)) node _schedule_T_498 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.param, UInt<1>(0h0)) node _schedule_T_499 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.param, UInt<1>(0h0)) node _schedule_T_500 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.param, UInt<1>(0h0)) node _schedule_T_501 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.param, UInt<1>(0h0)) node _schedule_T_502 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.param, UInt<1>(0h0)) node _schedule_T_503 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.param, UInt<1>(0h0)) node _schedule_T_504 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.param, UInt<1>(0h0)) node _schedule_T_505 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.param, UInt<1>(0h0)) node _schedule_T_506 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.param, UInt<1>(0h0)) node _schedule_T_507 = or(_schedule_T_495, _schedule_T_496) node _schedule_T_508 = or(_schedule_T_507, _schedule_T_497) node _schedule_T_509 = or(_schedule_T_508, _schedule_T_498) node _schedule_T_510 = or(_schedule_T_509, _schedule_T_499) node _schedule_T_511 = or(_schedule_T_510, _schedule_T_500) node _schedule_T_512 = or(_schedule_T_511, _schedule_T_501) node _schedule_T_513 = or(_schedule_T_512, _schedule_T_502) node _schedule_T_514 = or(_schedule_T_513, _schedule_T_503) node _schedule_T_515 = or(_schedule_T_514, _schedule_T_504) node _schedule_T_516 = or(_schedule_T_515, _schedule_T_505) node _schedule_T_517 = or(_schedule_T_516, _schedule_T_506) wire _schedule_WIRE_30 : UInt<3> connect _schedule_WIRE_30, _schedule_T_517 connect _schedule_WIRE_20.param, _schedule_WIRE_30 node _schedule_T_518 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.opcode, UInt<1>(0h0)) node _schedule_T_519 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.opcode, UInt<1>(0h0)) node _schedule_T_520 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.opcode, UInt<1>(0h0)) node _schedule_T_521 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.opcode, UInt<1>(0h0)) node _schedule_T_522 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.opcode, UInt<1>(0h0)) node _schedule_T_523 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.opcode, UInt<1>(0h0)) node _schedule_T_524 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.opcode, UInt<1>(0h0)) node _schedule_T_525 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.opcode, UInt<1>(0h0)) node _schedule_T_526 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.opcode, UInt<1>(0h0)) node _schedule_T_527 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.opcode, UInt<1>(0h0)) node _schedule_T_528 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.opcode, UInt<1>(0h0)) node _schedule_T_529 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.opcode, UInt<1>(0h0)) node _schedule_T_530 = or(_schedule_T_518, _schedule_T_519) node _schedule_T_531 = or(_schedule_T_530, _schedule_T_520) node _schedule_T_532 = or(_schedule_T_531, _schedule_T_521) node _schedule_T_533 = or(_schedule_T_532, _schedule_T_522) node _schedule_T_534 = or(_schedule_T_533, _schedule_T_523) node _schedule_T_535 = or(_schedule_T_534, _schedule_T_524) node _schedule_T_536 = or(_schedule_T_535, _schedule_T_525) node _schedule_T_537 = or(_schedule_T_536, _schedule_T_526) node _schedule_T_538 = or(_schedule_T_537, _schedule_T_527) node _schedule_T_539 = or(_schedule_T_538, _schedule_T_528) node _schedule_T_540 = or(_schedule_T_539, _schedule_T_529) wire _schedule_WIRE_31 : UInt<3> connect _schedule_WIRE_31, _schedule_T_540 connect _schedule_WIRE_20.opcode, _schedule_WIRE_31 node _schedule_T_541 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.control, UInt<1>(0h0)) node _schedule_T_542 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.control, UInt<1>(0h0)) node _schedule_T_543 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.control, UInt<1>(0h0)) node _schedule_T_544 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.control, UInt<1>(0h0)) node _schedule_T_545 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.control, UInt<1>(0h0)) node _schedule_T_546 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.control, UInt<1>(0h0)) node _schedule_T_547 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.control, UInt<1>(0h0)) node _schedule_T_548 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.control, UInt<1>(0h0)) node _schedule_T_549 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.control, UInt<1>(0h0)) node _schedule_T_550 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.control, UInt<1>(0h0)) node _schedule_T_551 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.control, UInt<1>(0h0)) node _schedule_T_552 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.control, UInt<1>(0h0)) node _schedule_T_553 = or(_schedule_T_541, _schedule_T_542) node _schedule_T_554 = or(_schedule_T_553, _schedule_T_543) node _schedule_T_555 = or(_schedule_T_554, _schedule_T_544) node _schedule_T_556 = or(_schedule_T_555, _schedule_T_545) node _schedule_T_557 = or(_schedule_T_556, _schedule_T_546) node _schedule_T_558 = or(_schedule_T_557, _schedule_T_547) node _schedule_T_559 = or(_schedule_T_558, _schedule_T_548) node _schedule_T_560 = or(_schedule_T_559, _schedule_T_549) node _schedule_T_561 = or(_schedule_T_560, _schedule_T_550) node _schedule_T_562 = or(_schedule_T_561, _schedule_T_551) node _schedule_T_563 = or(_schedule_T_562, _schedule_T_552) wire _schedule_WIRE_32 : UInt<1> connect _schedule_WIRE_32, _schedule_T_563 connect _schedule_WIRE_20.control, _schedule_WIRE_32 wire _schedule_WIRE_33 : UInt<1>[3] node _schedule_T_564 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.prio[0], UInt<1>(0h0)) node _schedule_T_565 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.prio[0], UInt<1>(0h0)) node _schedule_T_566 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.prio[0], UInt<1>(0h0)) node _schedule_T_567 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.prio[0], UInt<1>(0h0)) node _schedule_T_568 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.prio[0], UInt<1>(0h0)) node _schedule_T_569 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.prio[0], UInt<1>(0h0)) node _schedule_T_570 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.prio[0], UInt<1>(0h0)) node _schedule_T_571 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.prio[0], UInt<1>(0h0)) node _schedule_T_572 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.prio[0], UInt<1>(0h0)) node _schedule_T_573 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.prio[0], UInt<1>(0h0)) node _schedule_T_574 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.prio[0], UInt<1>(0h0)) node _schedule_T_575 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.prio[0], UInt<1>(0h0)) node _schedule_T_576 = or(_schedule_T_564, _schedule_T_565) node _schedule_T_577 = or(_schedule_T_576, _schedule_T_566) node _schedule_T_578 = or(_schedule_T_577, _schedule_T_567) node _schedule_T_579 = or(_schedule_T_578, _schedule_T_568) node _schedule_T_580 = or(_schedule_T_579, _schedule_T_569) node _schedule_T_581 = or(_schedule_T_580, _schedule_T_570) node _schedule_T_582 = or(_schedule_T_581, _schedule_T_571) node _schedule_T_583 = or(_schedule_T_582, _schedule_T_572) node _schedule_T_584 = or(_schedule_T_583, _schedule_T_573) node _schedule_T_585 = or(_schedule_T_584, _schedule_T_574) node _schedule_T_586 = or(_schedule_T_585, _schedule_T_575) wire _schedule_WIRE_34 : UInt<1> connect _schedule_WIRE_34, _schedule_T_586 connect _schedule_WIRE_33[0], _schedule_WIRE_34 node _schedule_T_587 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.prio[1], UInt<1>(0h0)) node _schedule_T_588 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.prio[1], UInt<1>(0h0)) node _schedule_T_589 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.prio[1], UInt<1>(0h0)) node _schedule_T_590 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.prio[1], UInt<1>(0h0)) node _schedule_T_591 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.prio[1], UInt<1>(0h0)) node _schedule_T_592 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.prio[1], UInt<1>(0h0)) node _schedule_T_593 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.prio[1], UInt<1>(0h0)) node _schedule_T_594 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.prio[1], UInt<1>(0h0)) node _schedule_T_595 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.prio[1], UInt<1>(0h0)) node _schedule_T_596 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.prio[1], UInt<1>(0h0)) node _schedule_T_597 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.prio[1], UInt<1>(0h0)) node _schedule_T_598 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.prio[1], UInt<1>(0h0)) node _schedule_T_599 = or(_schedule_T_587, _schedule_T_588) node _schedule_T_600 = or(_schedule_T_599, _schedule_T_589) node _schedule_T_601 = or(_schedule_T_600, _schedule_T_590) node _schedule_T_602 = or(_schedule_T_601, _schedule_T_591) node _schedule_T_603 = or(_schedule_T_602, _schedule_T_592) node _schedule_T_604 = or(_schedule_T_603, _schedule_T_593) node _schedule_T_605 = or(_schedule_T_604, _schedule_T_594) node _schedule_T_606 = or(_schedule_T_605, _schedule_T_595) node _schedule_T_607 = or(_schedule_T_606, _schedule_T_596) node _schedule_T_608 = or(_schedule_T_607, _schedule_T_597) node _schedule_T_609 = or(_schedule_T_608, _schedule_T_598) wire _schedule_WIRE_35 : UInt<1> connect _schedule_WIRE_35, _schedule_T_609 connect _schedule_WIRE_33[1], _schedule_WIRE_35 node _schedule_T_610 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.prio[2], UInt<1>(0h0)) node _schedule_T_611 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.prio[2], UInt<1>(0h0)) node _schedule_T_612 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.prio[2], UInt<1>(0h0)) node _schedule_T_613 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.prio[2], UInt<1>(0h0)) node _schedule_T_614 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.prio[2], UInt<1>(0h0)) node _schedule_T_615 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.prio[2], UInt<1>(0h0)) node _schedule_T_616 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.prio[2], UInt<1>(0h0)) node _schedule_T_617 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.prio[2], UInt<1>(0h0)) node _schedule_T_618 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.prio[2], UInt<1>(0h0)) node _schedule_T_619 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.prio[2], UInt<1>(0h0)) node _schedule_T_620 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.prio[2], UInt<1>(0h0)) node _schedule_T_621 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.prio[2], UInt<1>(0h0)) node _schedule_T_622 = or(_schedule_T_610, _schedule_T_611) node _schedule_T_623 = or(_schedule_T_622, _schedule_T_612) node _schedule_T_624 = or(_schedule_T_623, _schedule_T_613) node _schedule_T_625 = or(_schedule_T_624, _schedule_T_614) node _schedule_T_626 = or(_schedule_T_625, _schedule_T_615) node _schedule_T_627 = or(_schedule_T_626, _schedule_T_616) node _schedule_T_628 = or(_schedule_T_627, _schedule_T_617) node _schedule_T_629 = or(_schedule_T_628, _schedule_T_618) node _schedule_T_630 = or(_schedule_T_629, _schedule_T_619) node _schedule_T_631 = or(_schedule_T_630, _schedule_T_620) node _schedule_T_632 = or(_schedule_T_631, _schedule_T_621) wire _schedule_WIRE_36 : UInt<1> connect _schedule_WIRE_36, _schedule_T_632 connect _schedule_WIRE_33[2], _schedule_WIRE_36 connect _schedule_WIRE_20.prio, _schedule_WIRE_33 connect _schedule_WIRE_19.bits, _schedule_WIRE_20 node _schedule_T_633 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.valid, UInt<1>(0h0)) node _schedule_T_634 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.valid, UInt<1>(0h0)) node _schedule_T_635 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.valid, UInt<1>(0h0)) node _schedule_T_636 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.valid, UInt<1>(0h0)) node _schedule_T_637 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.valid, UInt<1>(0h0)) node _schedule_T_638 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.valid, UInt<1>(0h0)) node _schedule_T_639 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.valid, UInt<1>(0h0)) node _schedule_T_640 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.valid, UInt<1>(0h0)) node _schedule_T_641 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.valid, UInt<1>(0h0)) node _schedule_T_642 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.valid, UInt<1>(0h0)) node _schedule_T_643 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.valid, UInt<1>(0h0)) node _schedule_T_644 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.valid, UInt<1>(0h0)) node _schedule_T_645 = or(_schedule_T_633, _schedule_T_634) node _schedule_T_646 = or(_schedule_T_645, _schedule_T_635) node _schedule_T_647 = or(_schedule_T_646, _schedule_T_636) node _schedule_T_648 = or(_schedule_T_647, _schedule_T_637) node _schedule_T_649 = or(_schedule_T_648, _schedule_T_638) node _schedule_T_650 = or(_schedule_T_649, _schedule_T_639) node _schedule_T_651 = or(_schedule_T_650, _schedule_T_640) node _schedule_T_652 = or(_schedule_T_651, _schedule_T_641) node _schedule_T_653 = or(_schedule_T_652, _schedule_T_642) node _schedule_T_654 = or(_schedule_T_653, _schedule_T_643) node _schedule_T_655 = or(_schedule_T_654, _schedule_T_644) wire _schedule_WIRE_37 : UInt<1> connect _schedule_WIRE_37, _schedule_T_655 connect _schedule_WIRE_19.valid, _schedule_WIRE_37 connect schedule.d, _schedule_WIRE_19 wire _schedule_WIRE_38 : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, source : UInt<4>, tag : UInt<9>, set : UInt<11>, way : UInt<4>, dirty : UInt<1>}} wire _schedule_WIRE_39 : { opcode : UInt<3>, param : UInt<3>, source : UInt<4>, tag : UInt<9>, set : UInt<11>, way : UInt<4>, dirty : UInt<1>} node _schedule_T_656 = mux(_schedule_T, mshrs_0.io.schedule.bits.c.bits.dirty, UInt<1>(0h0)) node _schedule_T_657 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.c.bits.dirty, UInt<1>(0h0)) node _schedule_T_658 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.c.bits.dirty, UInt<1>(0h0)) node _schedule_T_659 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.c.bits.dirty, UInt<1>(0h0)) node _schedule_T_660 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.c.bits.dirty, UInt<1>(0h0)) node _schedule_T_661 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.c.bits.dirty, UInt<1>(0h0)) node _schedule_T_662 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.c.bits.dirty, UInt<1>(0h0)) node _schedule_T_663 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.c.bits.dirty, UInt<1>(0h0)) node _schedule_T_664 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.c.bits.dirty, UInt<1>(0h0)) node _schedule_T_665 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.c.bits.dirty, UInt<1>(0h0)) node _schedule_T_666 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.c.bits.dirty, UInt<1>(0h0)) node _schedule_T_667 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.c.bits.dirty, UInt<1>(0h0)) node _schedule_T_668 = or(_schedule_T_656, _schedule_T_657) node _schedule_T_669 = or(_schedule_T_668, _schedule_T_658) node _schedule_T_670 = or(_schedule_T_669, _schedule_T_659) node _schedule_T_671 = or(_schedule_T_670, _schedule_T_660) node _schedule_T_672 = or(_schedule_T_671, _schedule_T_661) node _schedule_T_673 = or(_schedule_T_672, _schedule_T_662) node _schedule_T_674 = or(_schedule_T_673, _schedule_T_663) node _schedule_T_675 = or(_schedule_T_674, _schedule_T_664) node _schedule_T_676 = or(_schedule_T_675, _schedule_T_665) node _schedule_T_677 = or(_schedule_T_676, _schedule_T_666) node _schedule_T_678 = or(_schedule_T_677, _schedule_T_667) wire _schedule_WIRE_40 : UInt<1> connect _schedule_WIRE_40, _schedule_T_678 connect _schedule_WIRE_39.dirty, _schedule_WIRE_40 node _schedule_T_679 = mux(_schedule_T, mshrs_0.io.schedule.bits.c.bits.way, UInt<1>(0h0)) node _schedule_T_680 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.c.bits.way, UInt<1>(0h0)) node _schedule_T_681 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.c.bits.way, UInt<1>(0h0)) node _schedule_T_682 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.c.bits.way, UInt<1>(0h0)) node _schedule_T_683 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.c.bits.way, UInt<1>(0h0)) node _schedule_T_684 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.c.bits.way, UInt<1>(0h0)) node _schedule_T_685 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.c.bits.way, UInt<1>(0h0)) node _schedule_T_686 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.c.bits.way, UInt<1>(0h0)) node _schedule_T_687 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.c.bits.way, UInt<1>(0h0)) node _schedule_T_688 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.c.bits.way, UInt<1>(0h0)) node _schedule_T_689 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.c.bits.way, UInt<1>(0h0)) node _schedule_T_690 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.c.bits.way, UInt<1>(0h0)) node _schedule_T_691 = or(_schedule_T_679, _schedule_T_680) node _schedule_T_692 = or(_schedule_T_691, _schedule_T_681) node _schedule_T_693 = or(_schedule_T_692, _schedule_T_682) node _schedule_T_694 = or(_schedule_T_693, _schedule_T_683) node _schedule_T_695 = or(_schedule_T_694, _schedule_T_684) node _schedule_T_696 = or(_schedule_T_695, _schedule_T_685) node _schedule_T_697 = or(_schedule_T_696, _schedule_T_686) node _schedule_T_698 = or(_schedule_T_697, _schedule_T_687) node _schedule_T_699 = or(_schedule_T_698, _schedule_T_688) node _schedule_T_700 = or(_schedule_T_699, _schedule_T_689) node _schedule_T_701 = or(_schedule_T_700, _schedule_T_690) wire _schedule_WIRE_41 : UInt<4> connect _schedule_WIRE_41, _schedule_T_701 connect _schedule_WIRE_39.way, _schedule_WIRE_41 node _schedule_T_702 = mux(_schedule_T, mshrs_0.io.schedule.bits.c.bits.set, UInt<1>(0h0)) node _schedule_T_703 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.c.bits.set, UInt<1>(0h0)) node _schedule_T_704 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.c.bits.set, UInt<1>(0h0)) node _schedule_T_705 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.c.bits.set, UInt<1>(0h0)) node _schedule_T_706 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.c.bits.set, UInt<1>(0h0)) node _schedule_T_707 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.c.bits.set, UInt<1>(0h0)) node _schedule_T_708 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.c.bits.set, UInt<1>(0h0)) node _schedule_T_709 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.c.bits.set, UInt<1>(0h0)) node _schedule_T_710 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.c.bits.set, UInt<1>(0h0)) node _schedule_T_711 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.c.bits.set, UInt<1>(0h0)) node _schedule_T_712 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.c.bits.set, UInt<1>(0h0)) node _schedule_T_713 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.c.bits.set, UInt<1>(0h0)) node _schedule_T_714 = or(_schedule_T_702, _schedule_T_703) node _schedule_T_715 = or(_schedule_T_714, _schedule_T_704) node _schedule_T_716 = or(_schedule_T_715, _schedule_T_705) node _schedule_T_717 = or(_schedule_T_716, _schedule_T_706) node _schedule_T_718 = or(_schedule_T_717, _schedule_T_707) node _schedule_T_719 = or(_schedule_T_718, _schedule_T_708) node _schedule_T_720 = or(_schedule_T_719, _schedule_T_709) node _schedule_T_721 = or(_schedule_T_720, _schedule_T_710) node _schedule_T_722 = or(_schedule_T_721, _schedule_T_711) node _schedule_T_723 = or(_schedule_T_722, _schedule_T_712) node _schedule_T_724 = or(_schedule_T_723, _schedule_T_713) wire _schedule_WIRE_42 : UInt<11> connect _schedule_WIRE_42, _schedule_T_724 connect _schedule_WIRE_39.set, _schedule_WIRE_42 node _schedule_T_725 = mux(_schedule_T, mshrs_0.io.schedule.bits.c.bits.tag, UInt<1>(0h0)) node _schedule_T_726 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.c.bits.tag, UInt<1>(0h0)) node _schedule_T_727 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.c.bits.tag, UInt<1>(0h0)) node _schedule_T_728 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.c.bits.tag, UInt<1>(0h0)) node _schedule_T_729 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.c.bits.tag, UInt<1>(0h0)) node _schedule_T_730 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.c.bits.tag, UInt<1>(0h0)) node _schedule_T_731 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.c.bits.tag, UInt<1>(0h0)) node _schedule_T_732 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.c.bits.tag, UInt<1>(0h0)) node _schedule_T_733 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.c.bits.tag, UInt<1>(0h0)) node _schedule_T_734 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.c.bits.tag, UInt<1>(0h0)) node _schedule_T_735 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.c.bits.tag, UInt<1>(0h0)) node _schedule_T_736 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.c.bits.tag, UInt<1>(0h0)) node _schedule_T_737 = or(_schedule_T_725, _schedule_T_726) node _schedule_T_738 = or(_schedule_T_737, _schedule_T_727) node _schedule_T_739 = or(_schedule_T_738, _schedule_T_728) node _schedule_T_740 = or(_schedule_T_739, _schedule_T_729) node _schedule_T_741 = or(_schedule_T_740, _schedule_T_730) node _schedule_T_742 = or(_schedule_T_741, _schedule_T_731) node _schedule_T_743 = or(_schedule_T_742, _schedule_T_732) node _schedule_T_744 = or(_schedule_T_743, _schedule_T_733) node _schedule_T_745 = or(_schedule_T_744, _schedule_T_734) node _schedule_T_746 = or(_schedule_T_745, _schedule_T_735) node _schedule_T_747 = or(_schedule_T_746, _schedule_T_736) wire _schedule_WIRE_43 : UInt<9> connect _schedule_WIRE_43, _schedule_T_747 connect _schedule_WIRE_39.tag, _schedule_WIRE_43 node _schedule_T_748 = mux(_schedule_T, mshrs_0.io.schedule.bits.c.bits.source, UInt<1>(0h0)) node _schedule_T_749 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.c.bits.source, UInt<1>(0h0)) node _schedule_T_750 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.c.bits.source, UInt<1>(0h0)) node _schedule_T_751 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.c.bits.source, UInt<1>(0h0)) node _schedule_T_752 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.c.bits.source, UInt<1>(0h0)) node _schedule_T_753 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.c.bits.source, UInt<1>(0h0)) node _schedule_T_754 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.c.bits.source, UInt<1>(0h0)) node _schedule_T_755 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.c.bits.source, UInt<1>(0h0)) node _schedule_T_756 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.c.bits.source, UInt<1>(0h0)) node _schedule_T_757 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.c.bits.source, UInt<1>(0h0)) node _schedule_T_758 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.c.bits.source, UInt<1>(0h0)) node _schedule_T_759 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.c.bits.source, UInt<1>(0h0)) node _schedule_T_760 = or(_schedule_T_748, _schedule_T_749) node _schedule_T_761 = or(_schedule_T_760, _schedule_T_750) node _schedule_T_762 = or(_schedule_T_761, _schedule_T_751) node _schedule_T_763 = or(_schedule_T_762, _schedule_T_752) node _schedule_T_764 = or(_schedule_T_763, _schedule_T_753) node _schedule_T_765 = or(_schedule_T_764, _schedule_T_754) node _schedule_T_766 = or(_schedule_T_765, _schedule_T_755) node _schedule_T_767 = or(_schedule_T_766, _schedule_T_756) node _schedule_T_768 = or(_schedule_T_767, _schedule_T_757) node _schedule_T_769 = or(_schedule_T_768, _schedule_T_758) node _schedule_T_770 = or(_schedule_T_769, _schedule_T_759) wire _schedule_WIRE_44 : UInt<4> connect _schedule_WIRE_44, _schedule_T_770 connect _schedule_WIRE_39.source, _schedule_WIRE_44 node _schedule_T_771 = mux(_schedule_T, mshrs_0.io.schedule.bits.c.bits.param, UInt<1>(0h0)) node _schedule_T_772 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.c.bits.param, UInt<1>(0h0)) node _schedule_T_773 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.c.bits.param, UInt<1>(0h0)) node _schedule_T_774 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.c.bits.param, UInt<1>(0h0)) node _schedule_T_775 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.c.bits.param, UInt<1>(0h0)) node _schedule_T_776 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.c.bits.param, UInt<1>(0h0)) node _schedule_T_777 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.c.bits.param, UInt<1>(0h0)) node _schedule_T_778 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.c.bits.param, UInt<1>(0h0)) node _schedule_T_779 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.c.bits.param, UInt<1>(0h0)) node _schedule_T_780 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.c.bits.param, UInt<1>(0h0)) node _schedule_T_781 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.c.bits.param, UInt<1>(0h0)) node _schedule_T_782 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.c.bits.param, UInt<1>(0h0)) node _schedule_T_783 = or(_schedule_T_771, _schedule_T_772) node _schedule_T_784 = or(_schedule_T_783, _schedule_T_773) node _schedule_T_785 = or(_schedule_T_784, _schedule_T_774) node _schedule_T_786 = or(_schedule_T_785, _schedule_T_775) node _schedule_T_787 = or(_schedule_T_786, _schedule_T_776) node _schedule_T_788 = or(_schedule_T_787, _schedule_T_777) node _schedule_T_789 = or(_schedule_T_788, _schedule_T_778) node _schedule_T_790 = or(_schedule_T_789, _schedule_T_779) node _schedule_T_791 = or(_schedule_T_790, _schedule_T_780) node _schedule_T_792 = or(_schedule_T_791, _schedule_T_781) node _schedule_T_793 = or(_schedule_T_792, _schedule_T_782) wire _schedule_WIRE_45 : UInt<3> connect _schedule_WIRE_45, _schedule_T_793 connect _schedule_WIRE_39.param, _schedule_WIRE_45 node _schedule_T_794 = mux(_schedule_T, mshrs_0.io.schedule.bits.c.bits.opcode, UInt<1>(0h0)) node _schedule_T_795 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.c.bits.opcode, UInt<1>(0h0)) node _schedule_T_796 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.c.bits.opcode, UInt<1>(0h0)) node _schedule_T_797 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.c.bits.opcode, UInt<1>(0h0)) node _schedule_T_798 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.c.bits.opcode, UInt<1>(0h0)) node _schedule_T_799 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.c.bits.opcode, UInt<1>(0h0)) node _schedule_T_800 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.c.bits.opcode, UInt<1>(0h0)) node _schedule_T_801 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.c.bits.opcode, UInt<1>(0h0)) node _schedule_T_802 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.c.bits.opcode, UInt<1>(0h0)) node _schedule_T_803 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.c.bits.opcode, UInt<1>(0h0)) node _schedule_T_804 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.c.bits.opcode, UInt<1>(0h0)) node _schedule_T_805 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.c.bits.opcode, UInt<1>(0h0)) node _schedule_T_806 = or(_schedule_T_794, _schedule_T_795) node _schedule_T_807 = or(_schedule_T_806, _schedule_T_796) node _schedule_T_808 = or(_schedule_T_807, _schedule_T_797) node _schedule_T_809 = or(_schedule_T_808, _schedule_T_798) node _schedule_T_810 = or(_schedule_T_809, _schedule_T_799) node _schedule_T_811 = or(_schedule_T_810, _schedule_T_800) node _schedule_T_812 = or(_schedule_T_811, _schedule_T_801) node _schedule_T_813 = or(_schedule_T_812, _schedule_T_802) node _schedule_T_814 = or(_schedule_T_813, _schedule_T_803) node _schedule_T_815 = or(_schedule_T_814, _schedule_T_804) node _schedule_T_816 = or(_schedule_T_815, _schedule_T_805) wire _schedule_WIRE_46 : UInt<3> connect _schedule_WIRE_46, _schedule_T_816 connect _schedule_WIRE_39.opcode, _schedule_WIRE_46 connect _schedule_WIRE_38.bits, _schedule_WIRE_39 node _schedule_T_817 = mux(_schedule_T, mshrs_0.io.schedule.bits.c.valid, UInt<1>(0h0)) node _schedule_T_818 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.c.valid, UInt<1>(0h0)) node _schedule_T_819 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.c.valid, UInt<1>(0h0)) node _schedule_T_820 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.c.valid, UInt<1>(0h0)) node _schedule_T_821 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.c.valid, UInt<1>(0h0)) node _schedule_T_822 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.c.valid, UInt<1>(0h0)) node _schedule_T_823 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.c.valid, UInt<1>(0h0)) node _schedule_T_824 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.c.valid, UInt<1>(0h0)) node _schedule_T_825 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.c.valid, UInt<1>(0h0)) node _schedule_T_826 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.c.valid, UInt<1>(0h0)) node _schedule_T_827 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.c.valid, UInt<1>(0h0)) node _schedule_T_828 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.c.valid, UInt<1>(0h0)) node _schedule_T_829 = or(_schedule_T_817, _schedule_T_818) node _schedule_T_830 = or(_schedule_T_829, _schedule_T_819) node _schedule_T_831 = or(_schedule_T_830, _schedule_T_820) node _schedule_T_832 = or(_schedule_T_831, _schedule_T_821) node _schedule_T_833 = or(_schedule_T_832, _schedule_T_822) node _schedule_T_834 = or(_schedule_T_833, _schedule_T_823) node _schedule_T_835 = or(_schedule_T_834, _schedule_T_824) node _schedule_T_836 = or(_schedule_T_835, _schedule_T_825) node _schedule_T_837 = or(_schedule_T_836, _schedule_T_826) node _schedule_T_838 = or(_schedule_T_837, _schedule_T_827) node _schedule_T_839 = or(_schedule_T_838, _schedule_T_828) wire _schedule_WIRE_47 : UInt<1> connect _schedule_WIRE_47, _schedule_T_839 connect _schedule_WIRE_38.valid, _schedule_WIRE_47 connect schedule.c, _schedule_WIRE_38 wire _schedule_WIRE_48 : { valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<9>, set : UInt<11>, clients : UInt<1>}} wire _schedule_WIRE_49 : { param : UInt<3>, tag : UInt<9>, set : UInt<11>, clients : UInt<1>} node _schedule_T_840 = mux(_schedule_T, mshrs_0.io.schedule.bits.b.bits.clients, UInt<1>(0h0)) node _schedule_T_841 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.b.bits.clients, UInt<1>(0h0)) node _schedule_T_842 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.b.bits.clients, UInt<1>(0h0)) node _schedule_T_843 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.b.bits.clients, UInt<1>(0h0)) node _schedule_T_844 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.b.bits.clients, UInt<1>(0h0)) node _schedule_T_845 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.b.bits.clients, UInt<1>(0h0)) node _schedule_T_846 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.b.bits.clients, UInt<1>(0h0)) node _schedule_T_847 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.b.bits.clients, UInt<1>(0h0)) node _schedule_T_848 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.b.bits.clients, UInt<1>(0h0)) node _schedule_T_849 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.b.bits.clients, UInt<1>(0h0)) node _schedule_T_850 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.b.bits.clients, UInt<1>(0h0)) node _schedule_T_851 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.b.bits.clients, UInt<1>(0h0)) node _schedule_T_852 = or(_schedule_T_840, _schedule_T_841) node _schedule_T_853 = or(_schedule_T_852, _schedule_T_842) node _schedule_T_854 = or(_schedule_T_853, _schedule_T_843) node _schedule_T_855 = or(_schedule_T_854, _schedule_T_844) node _schedule_T_856 = or(_schedule_T_855, _schedule_T_845) node _schedule_T_857 = or(_schedule_T_856, _schedule_T_846) node _schedule_T_858 = or(_schedule_T_857, _schedule_T_847) node _schedule_T_859 = or(_schedule_T_858, _schedule_T_848) node _schedule_T_860 = or(_schedule_T_859, _schedule_T_849) node _schedule_T_861 = or(_schedule_T_860, _schedule_T_850) node _schedule_T_862 = or(_schedule_T_861, _schedule_T_851) wire _schedule_WIRE_50 : UInt<1> connect _schedule_WIRE_50, _schedule_T_862 connect _schedule_WIRE_49.clients, _schedule_WIRE_50 node _schedule_T_863 = mux(_schedule_T, mshrs_0.io.schedule.bits.b.bits.set, UInt<1>(0h0)) node _schedule_T_864 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.b.bits.set, UInt<1>(0h0)) node _schedule_T_865 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.b.bits.set, UInt<1>(0h0)) node _schedule_T_866 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.b.bits.set, UInt<1>(0h0)) node _schedule_T_867 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.b.bits.set, UInt<1>(0h0)) node _schedule_T_868 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.b.bits.set, UInt<1>(0h0)) node _schedule_T_869 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.b.bits.set, UInt<1>(0h0)) node _schedule_T_870 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.b.bits.set, UInt<1>(0h0)) node _schedule_T_871 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.b.bits.set, UInt<1>(0h0)) node _schedule_T_872 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.b.bits.set, UInt<1>(0h0)) node _schedule_T_873 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.b.bits.set, UInt<1>(0h0)) node _schedule_T_874 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.b.bits.set, UInt<1>(0h0)) node _schedule_T_875 = or(_schedule_T_863, _schedule_T_864) node _schedule_T_876 = or(_schedule_T_875, _schedule_T_865) node _schedule_T_877 = or(_schedule_T_876, _schedule_T_866) node _schedule_T_878 = or(_schedule_T_877, _schedule_T_867) node _schedule_T_879 = or(_schedule_T_878, _schedule_T_868) node _schedule_T_880 = or(_schedule_T_879, _schedule_T_869) node _schedule_T_881 = or(_schedule_T_880, _schedule_T_870) node _schedule_T_882 = or(_schedule_T_881, _schedule_T_871) node _schedule_T_883 = or(_schedule_T_882, _schedule_T_872) node _schedule_T_884 = or(_schedule_T_883, _schedule_T_873) node _schedule_T_885 = or(_schedule_T_884, _schedule_T_874) wire _schedule_WIRE_51 : UInt<11> connect _schedule_WIRE_51, _schedule_T_885 connect _schedule_WIRE_49.set, _schedule_WIRE_51 node _schedule_T_886 = mux(_schedule_T, mshrs_0.io.schedule.bits.b.bits.tag, UInt<1>(0h0)) node _schedule_T_887 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.b.bits.tag, UInt<1>(0h0)) node _schedule_T_888 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.b.bits.tag, UInt<1>(0h0)) node _schedule_T_889 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.b.bits.tag, UInt<1>(0h0)) node _schedule_T_890 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.b.bits.tag, UInt<1>(0h0)) node _schedule_T_891 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.b.bits.tag, UInt<1>(0h0)) node _schedule_T_892 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.b.bits.tag, UInt<1>(0h0)) node _schedule_T_893 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.b.bits.tag, UInt<1>(0h0)) node _schedule_T_894 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.b.bits.tag, UInt<1>(0h0)) node _schedule_T_895 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.b.bits.tag, UInt<1>(0h0)) node _schedule_T_896 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.b.bits.tag, UInt<1>(0h0)) node _schedule_T_897 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.b.bits.tag, UInt<1>(0h0)) node _schedule_T_898 = or(_schedule_T_886, _schedule_T_887) node _schedule_T_899 = or(_schedule_T_898, _schedule_T_888) node _schedule_T_900 = or(_schedule_T_899, _schedule_T_889) node _schedule_T_901 = or(_schedule_T_900, _schedule_T_890) node _schedule_T_902 = or(_schedule_T_901, _schedule_T_891) node _schedule_T_903 = or(_schedule_T_902, _schedule_T_892) node _schedule_T_904 = or(_schedule_T_903, _schedule_T_893) node _schedule_T_905 = or(_schedule_T_904, _schedule_T_894) node _schedule_T_906 = or(_schedule_T_905, _schedule_T_895) node _schedule_T_907 = or(_schedule_T_906, _schedule_T_896) node _schedule_T_908 = or(_schedule_T_907, _schedule_T_897) wire _schedule_WIRE_52 : UInt<9> connect _schedule_WIRE_52, _schedule_T_908 connect _schedule_WIRE_49.tag, _schedule_WIRE_52 node _schedule_T_909 = mux(_schedule_T, mshrs_0.io.schedule.bits.b.bits.param, UInt<1>(0h0)) node _schedule_T_910 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.b.bits.param, UInt<1>(0h0)) node _schedule_T_911 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.b.bits.param, UInt<1>(0h0)) node _schedule_T_912 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.b.bits.param, UInt<1>(0h0)) node _schedule_T_913 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.b.bits.param, UInt<1>(0h0)) node _schedule_T_914 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.b.bits.param, UInt<1>(0h0)) node _schedule_T_915 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.b.bits.param, UInt<1>(0h0)) node _schedule_T_916 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.b.bits.param, UInt<1>(0h0)) node _schedule_T_917 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.b.bits.param, UInt<1>(0h0)) node _schedule_T_918 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.b.bits.param, UInt<1>(0h0)) node _schedule_T_919 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.b.bits.param, UInt<1>(0h0)) node _schedule_T_920 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.b.bits.param, UInt<1>(0h0)) node _schedule_T_921 = or(_schedule_T_909, _schedule_T_910) node _schedule_T_922 = or(_schedule_T_921, _schedule_T_911) node _schedule_T_923 = or(_schedule_T_922, _schedule_T_912) node _schedule_T_924 = or(_schedule_T_923, _schedule_T_913) node _schedule_T_925 = or(_schedule_T_924, _schedule_T_914) node _schedule_T_926 = or(_schedule_T_925, _schedule_T_915) node _schedule_T_927 = or(_schedule_T_926, _schedule_T_916) node _schedule_T_928 = or(_schedule_T_927, _schedule_T_917) node _schedule_T_929 = or(_schedule_T_928, _schedule_T_918) node _schedule_T_930 = or(_schedule_T_929, _schedule_T_919) node _schedule_T_931 = or(_schedule_T_930, _schedule_T_920) wire _schedule_WIRE_53 : UInt<3> connect _schedule_WIRE_53, _schedule_T_931 connect _schedule_WIRE_49.param, _schedule_WIRE_53 connect _schedule_WIRE_48.bits, _schedule_WIRE_49 node _schedule_T_932 = mux(_schedule_T, mshrs_0.io.schedule.bits.b.valid, UInt<1>(0h0)) node _schedule_T_933 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.b.valid, UInt<1>(0h0)) node _schedule_T_934 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.b.valid, UInt<1>(0h0)) node _schedule_T_935 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.b.valid, UInt<1>(0h0)) node _schedule_T_936 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.b.valid, UInt<1>(0h0)) node _schedule_T_937 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.b.valid, UInt<1>(0h0)) node _schedule_T_938 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.b.valid, UInt<1>(0h0)) node _schedule_T_939 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.b.valid, UInt<1>(0h0)) node _schedule_T_940 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.b.valid, UInt<1>(0h0)) node _schedule_T_941 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.b.valid, UInt<1>(0h0)) node _schedule_T_942 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.b.valid, UInt<1>(0h0)) node _schedule_T_943 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.b.valid, UInt<1>(0h0)) node _schedule_T_944 = or(_schedule_T_932, _schedule_T_933) node _schedule_T_945 = or(_schedule_T_944, _schedule_T_934) node _schedule_T_946 = or(_schedule_T_945, _schedule_T_935) node _schedule_T_947 = or(_schedule_T_946, _schedule_T_936) node _schedule_T_948 = or(_schedule_T_947, _schedule_T_937) node _schedule_T_949 = or(_schedule_T_948, _schedule_T_938) node _schedule_T_950 = or(_schedule_T_949, _schedule_T_939) node _schedule_T_951 = or(_schedule_T_950, _schedule_T_940) node _schedule_T_952 = or(_schedule_T_951, _schedule_T_941) node _schedule_T_953 = or(_schedule_T_952, _schedule_T_942) node _schedule_T_954 = or(_schedule_T_953, _schedule_T_943) wire _schedule_WIRE_54 : UInt<1> connect _schedule_WIRE_54, _schedule_T_954 connect _schedule_WIRE_48.valid, _schedule_WIRE_54 connect schedule.b, _schedule_WIRE_48 wire _schedule_WIRE_55 : { valid : UInt<1>, bits : { tag : UInt<9>, set : UInt<11>, param : UInt<3>, source : UInt<4>, block : UInt<1>}} wire _schedule_WIRE_56 : { tag : UInt<9>, set : UInt<11>, param : UInt<3>, source : UInt<4>, block : UInt<1>} node _schedule_T_955 = mux(_schedule_T, mshrs_0.io.schedule.bits.a.bits.block, UInt<1>(0h0)) node _schedule_T_956 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.a.bits.block, UInt<1>(0h0)) node _schedule_T_957 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.a.bits.block, UInt<1>(0h0)) node _schedule_T_958 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.a.bits.block, UInt<1>(0h0)) node _schedule_T_959 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.a.bits.block, UInt<1>(0h0)) node _schedule_T_960 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.a.bits.block, UInt<1>(0h0)) node _schedule_T_961 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.a.bits.block, UInt<1>(0h0)) node _schedule_T_962 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.a.bits.block, UInt<1>(0h0)) node _schedule_T_963 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.a.bits.block, UInt<1>(0h0)) node _schedule_T_964 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.a.bits.block, UInt<1>(0h0)) node _schedule_T_965 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.a.bits.block, UInt<1>(0h0)) node _schedule_T_966 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.a.bits.block, UInt<1>(0h0)) node _schedule_T_967 = or(_schedule_T_955, _schedule_T_956) node _schedule_T_968 = or(_schedule_T_967, _schedule_T_957) node _schedule_T_969 = or(_schedule_T_968, _schedule_T_958) node _schedule_T_970 = or(_schedule_T_969, _schedule_T_959) node _schedule_T_971 = or(_schedule_T_970, _schedule_T_960) node _schedule_T_972 = or(_schedule_T_971, _schedule_T_961) node _schedule_T_973 = or(_schedule_T_972, _schedule_T_962) node _schedule_T_974 = or(_schedule_T_973, _schedule_T_963) node _schedule_T_975 = or(_schedule_T_974, _schedule_T_964) node _schedule_T_976 = or(_schedule_T_975, _schedule_T_965) node _schedule_T_977 = or(_schedule_T_976, _schedule_T_966) wire _schedule_WIRE_57 : UInt<1> connect _schedule_WIRE_57, _schedule_T_977 connect _schedule_WIRE_56.block, _schedule_WIRE_57 node _schedule_T_978 = mux(_schedule_T, mshrs_0.io.schedule.bits.a.bits.source, UInt<1>(0h0)) node _schedule_T_979 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.a.bits.source, UInt<1>(0h0)) node _schedule_T_980 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.a.bits.source, UInt<1>(0h0)) node _schedule_T_981 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.a.bits.source, UInt<1>(0h0)) node _schedule_T_982 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.a.bits.source, UInt<1>(0h0)) node _schedule_T_983 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.a.bits.source, UInt<1>(0h0)) node _schedule_T_984 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.a.bits.source, UInt<1>(0h0)) node _schedule_T_985 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.a.bits.source, UInt<1>(0h0)) node _schedule_T_986 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.a.bits.source, UInt<1>(0h0)) node _schedule_T_987 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.a.bits.source, UInt<1>(0h0)) node _schedule_T_988 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.a.bits.source, UInt<1>(0h0)) node _schedule_T_989 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.a.bits.source, UInt<1>(0h0)) node _schedule_T_990 = or(_schedule_T_978, _schedule_T_979) node _schedule_T_991 = or(_schedule_T_990, _schedule_T_980) node _schedule_T_992 = or(_schedule_T_991, _schedule_T_981) node _schedule_T_993 = or(_schedule_T_992, _schedule_T_982) node _schedule_T_994 = or(_schedule_T_993, _schedule_T_983) node _schedule_T_995 = or(_schedule_T_994, _schedule_T_984) node _schedule_T_996 = or(_schedule_T_995, _schedule_T_985) node _schedule_T_997 = or(_schedule_T_996, _schedule_T_986) node _schedule_T_998 = or(_schedule_T_997, _schedule_T_987) node _schedule_T_999 = or(_schedule_T_998, _schedule_T_988) node _schedule_T_1000 = or(_schedule_T_999, _schedule_T_989) wire _schedule_WIRE_58 : UInt<4> connect _schedule_WIRE_58, _schedule_T_1000 connect _schedule_WIRE_56.source, _schedule_WIRE_58 node _schedule_T_1001 = mux(_schedule_T, mshrs_0.io.schedule.bits.a.bits.param, UInt<1>(0h0)) node _schedule_T_1002 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.a.bits.param, UInt<1>(0h0)) node _schedule_T_1003 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.a.bits.param, UInt<1>(0h0)) node _schedule_T_1004 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.a.bits.param, UInt<1>(0h0)) node _schedule_T_1005 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.a.bits.param, UInt<1>(0h0)) node _schedule_T_1006 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.a.bits.param, UInt<1>(0h0)) node _schedule_T_1007 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.a.bits.param, UInt<1>(0h0)) node _schedule_T_1008 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.a.bits.param, UInt<1>(0h0)) node _schedule_T_1009 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.a.bits.param, UInt<1>(0h0)) node _schedule_T_1010 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.a.bits.param, UInt<1>(0h0)) node _schedule_T_1011 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.a.bits.param, UInt<1>(0h0)) node _schedule_T_1012 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.a.bits.param, UInt<1>(0h0)) node _schedule_T_1013 = or(_schedule_T_1001, _schedule_T_1002) node _schedule_T_1014 = or(_schedule_T_1013, _schedule_T_1003) node _schedule_T_1015 = or(_schedule_T_1014, _schedule_T_1004) node _schedule_T_1016 = or(_schedule_T_1015, _schedule_T_1005) node _schedule_T_1017 = or(_schedule_T_1016, _schedule_T_1006) node _schedule_T_1018 = or(_schedule_T_1017, _schedule_T_1007) node _schedule_T_1019 = or(_schedule_T_1018, _schedule_T_1008) node _schedule_T_1020 = or(_schedule_T_1019, _schedule_T_1009) node _schedule_T_1021 = or(_schedule_T_1020, _schedule_T_1010) node _schedule_T_1022 = or(_schedule_T_1021, _schedule_T_1011) node _schedule_T_1023 = or(_schedule_T_1022, _schedule_T_1012) wire _schedule_WIRE_59 : UInt<3> connect _schedule_WIRE_59, _schedule_T_1023 connect _schedule_WIRE_56.param, _schedule_WIRE_59 node _schedule_T_1024 = mux(_schedule_T, mshrs_0.io.schedule.bits.a.bits.set, UInt<1>(0h0)) node _schedule_T_1025 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.a.bits.set, UInt<1>(0h0)) node _schedule_T_1026 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.a.bits.set, UInt<1>(0h0)) node _schedule_T_1027 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.a.bits.set, UInt<1>(0h0)) node _schedule_T_1028 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.a.bits.set, UInt<1>(0h0)) node _schedule_T_1029 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.a.bits.set, UInt<1>(0h0)) node _schedule_T_1030 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.a.bits.set, UInt<1>(0h0)) node _schedule_T_1031 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.a.bits.set, UInt<1>(0h0)) node _schedule_T_1032 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.a.bits.set, UInt<1>(0h0)) node _schedule_T_1033 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.a.bits.set, UInt<1>(0h0)) node _schedule_T_1034 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.a.bits.set, UInt<1>(0h0)) node _schedule_T_1035 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.a.bits.set, UInt<1>(0h0)) node _schedule_T_1036 = or(_schedule_T_1024, _schedule_T_1025) node _schedule_T_1037 = or(_schedule_T_1036, _schedule_T_1026) node _schedule_T_1038 = or(_schedule_T_1037, _schedule_T_1027) node _schedule_T_1039 = or(_schedule_T_1038, _schedule_T_1028) node _schedule_T_1040 = or(_schedule_T_1039, _schedule_T_1029) node _schedule_T_1041 = or(_schedule_T_1040, _schedule_T_1030) node _schedule_T_1042 = or(_schedule_T_1041, _schedule_T_1031) node _schedule_T_1043 = or(_schedule_T_1042, _schedule_T_1032) node _schedule_T_1044 = or(_schedule_T_1043, _schedule_T_1033) node _schedule_T_1045 = or(_schedule_T_1044, _schedule_T_1034) node _schedule_T_1046 = or(_schedule_T_1045, _schedule_T_1035) wire _schedule_WIRE_60 : UInt<11> connect _schedule_WIRE_60, _schedule_T_1046 connect _schedule_WIRE_56.set, _schedule_WIRE_60 node _schedule_T_1047 = mux(_schedule_T, mshrs_0.io.schedule.bits.a.bits.tag, UInt<1>(0h0)) node _schedule_T_1048 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.a.bits.tag, UInt<1>(0h0)) node _schedule_T_1049 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.a.bits.tag, UInt<1>(0h0)) node _schedule_T_1050 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.a.bits.tag, UInt<1>(0h0)) node _schedule_T_1051 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.a.bits.tag, UInt<1>(0h0)) node _schedule_T_1052 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.a.bits.tag, UInt<1>(0h0)) node _schedule_T_1053 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.a.bits.tag, UInt<1>(0h0)) node _schedule_T_1054 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.a.bits.tag, UInt<1>(0h0)) node _schedule_T_1055 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.a.bits.tag, UInt<1>(0h0)) node _schedule_T_1056 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.a.bits.tag, UInt<1>(0h0)) node _schedule_T_1057 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.a.bits.tag, UInt<1>(0h0)) node _schedule_T_1058 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.a.bits.tag, UInt<1>(0h0)) node _schedule_T_1059 = or(_schedule_T_1047, _schedule_T_1048) node _schedule_T_1060 = or(_schedule_T_1059, _schedule_T_1049) node _schedule_T_1061 = or(_schedule_T_1060, _schedule_T_1050) node _schedule_T_1062 = or(_schedule_T_1061, _schedule_T_1051) node _schedule_T_1063 = or(_schedule_T_1062, _schedule_T_1052) node _schedule_T_1064 = or(_schedule_T_1063, _schedule_T_1053) node _schedule_T_1065 = or(_schedule_T_1064, _schedule_T_1054) node _schedule_T_1066 = or(_schedule_T_1065, _schedule_T_1055) node _schedule_T_1067 = or(_schedule_T_1066, _schedule_T_1056) node _schedule_T_1068 = or(_schedule_T_1067, _schedule_T_1057) node _schedule_T_1069 = or(_schedule_T_1068, _schedule_T_1058) wire _schedule_WIRE_61 : UInt<9> connect _schedule_WIRE_61, _schedule_T_1069 connect _schedule_WIRE_56.tag, _schedule_WIRE_61 connect _schedule_WIRE_55.bits, _schedule_WIRE_56 node _schedule_T_1070 = mux(_schedule_T, mshrs_0.io.schedule.bits.a.valid, UInt<1>(0h0)) node _schedule_T_1071 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.a.valid, UInt<1>(0h0)) node _schedule_T_1072 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.a.valid, UInt<1>(0h0)) node _schedule_T_1073 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.a.valid, UInt<1>(0h0)) node _schedule_T_1074 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.a.valid, UInt<1>(0h0)) node _schedule_T_1075 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.a.valid, UInt<1>(0h0)) node _schedule_T_1076 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.a.valid, UInt<1>(0h0)) node _schedule_T_1077 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.a.valid, UInt<1>(0h0)) node _schedule_T_1078 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.a.valid, UInt<1>(0h0)) node _schedule_T_1079 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.a.valid, UInt<1>(0h0)) node _schedule_T_1080 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.a.valid, UInt<1>(0h0)) node _schedule_T_1081 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.a.valid, UInt<1>(0h0)) node _schedule_T_1082 = or(_schedule_T_1070, _schedule_T_1071) node _schedule_T_1083 = or(_schedule_T_1082, _schedule_T_1072) node _schedule_T_1084 = or(_schedule_T_1083, _schedule_T_1073) node _schedule_T_1085 = or(_schedule_T_1084, _schedule_T_1074) node _schedule_T_1086 = or(_schedule_T_1085, _schedule_T_1075) node _schedule_T_1087 = or(_schedule_T_1086, _schedule_T_1076) node _schedule_T_1088 = or(_schedule_T_1087, _schedule_T_1077) node _schedule_T_1089 = or(_schedule_T_1088, _schedule_T_1078) node _schedule_T_1090 = or(_schedule_T_1089, _schedule_T_1079) node _schedule_T_1091 = or(_schedule_T_1090, _schedule_T_1080) node _schedule_T_1092 = or(_schedule_T_1091, _schedule_T_1081) wire _schedule_WIRE_62 : UInt<1> connect _schedule_WIRE_62, _schedule_T_1092 connect _schedule_WIRE_55.valid, _schedule_WIRE_62 connect schedule.a, _schedule_WIRE_55 node _scheduleTag_T = bits(mshr_selectOH, 0, 0) node _scheduleTag_T_1 = bits(mshr_selectOH, 1, 1) node _scheduleTag_T_2 = bits(mshr_selectOH, 2, 2) node _scheduleTag_T_3 = bits(mshr_selectOH, 3, 3) node _scheduleTag_T_4 = bits(mshr_selectOH, 4, 4) node _scheduleTag_T_5 = bits(mshr_selectOH, 5, 5) node _scheduleTag_T_6 = bits(mshr_selectOH, 6, 6) node _scheduleTag_T_7 = bits(mshr_selectOH, 7, 7) node _scheduleTag_T_8 = bits(mshr_selectOH, 8, 8) node _scheduleTag_T_9 = bits(mshr_selectOH, 9, 9) node _scheduleTag_T_10 = bits(mshr_selectOH, 10, 10) node _scheduleTag_T_11 = bits(mshr_selectOH, 11, 11) node _scheduleTag_T_12 = mux(_scheduleTag_T, mshrs_0.io.status.bits.tag, UInt<1>(0h0)) node _scheduleTag_T_13 = mux(_scheduleTag_T_1, mshrs_1.io.status.bits.tag, UInt<1>(0h0)) node _scheduleTag_T_14 = mux(_scheduleTag_T_2, mshrs_2.io.status.bits.tag, UInt<1>(0h0)) node _scheduleTag_T_15 = mux(_scheduleTag_T_3, mshrs_3.io.status.bits.tag, UInt<1>(0h0)) node _scheduleTag_T_16 = mux(_scheduleTag_T_4, mshrs_4.io.status.bits.tag, UInt<1>(0h0)) node _scheduleTag_T_17 = mux(_scheduleTag_T_5, mshrs_5.io.status.bits.tag, UInt<1>(0h0)) node _scheduleTag_T_18 = mux(_scheduleTag_T_6, mshrs_6.io.status.bits.tag, UInt<1>(0h0)) node _scheduleTag_T_19 = mux(_scheduleTag_T_7, mshrs_7.io.status.bits.tag, UInt<1>(0h0)) node _scheduleTag_T_20 = mux(_scheduleTag_T_8, mshrs_8.io.status.bits.tag, UInt<1>(0h0)) node _scheduleTag_T_21 = mux(_scheduleTag_T_9, mshrs_9.io.status.bits.tag, UInt<1>(0h0)) node _scheduleTag_T_22 = mux(_scheduleTag_T_10, mshrs_10.io.status.bits.tag, UInt<1>(0h0)) node _scheduleTag_T_23 = mux(_scheduleTag_T_11, mshrs_11.io.status.bits.tag, UInt<1>(0h0)) node _scheduleTag_T_24 = or(_scheduleTag_T_12, _scheduleTag_T_13) node _scheduleTag_T_25 = or(_scheduleTag_T_24, _scheduleTag_T_14) node _scheduleTag_T_26 = or(_scheduleTag_T_25, _scheduleTag_T_15) node _scheduleTag_T_27 = or(_scheduleTag_T_26, _scheduleTag_T_16) node _scheduleTag_T_28 = or(_scheduleTag_T_27, _scheduleTag_T_17) node _scheduleTag_T_29 = or(_scheduleTag_T_28, _scheduleTag_T_18) node _scheduleTag_T_30 = or(_scheduleTag_T_29, _scheduleTag_T_19) node _scheduleTag_T_31 = or(_scheduleTag_T_30, _scheduleTag_T_20) node _scheduleTag_T_32 = or(_scheduleTag_T_31, _scheduleTag_T_21) node _scheduleTag_T_33 = or(_scheduleTag_T_32, _scheduleTag_T_22) node _scheduleTag_T_34 = or(_scheduleTag_T_33, _scheduleTag_T_23) wire scheduleTag : UInt<9> connect scheduleTag, _scheduleTag_T_34 node _scheduleSet_T = bits(mshr_selectOH, 0, 0) node _scheduleSet_T_1 = bits(mshr_selectOH, 1, 1) node _scheduleSet_T_2 = bits(mshr_selectOH, 2, 2) node _scheduleSet_T_3 = bits(mshr_selectOH, 3, 3) node _scheduleSet_T_4 = bits(mshr_selectOH, 4, 4) node _scheduleSet_T_5 = bits(mshr_selectOH, 5, 5) node _scheduleSet_T_6 = bits(mshr_selectOH, 6, 6) node _scheduleSet_T_7 = bits(mshr_selectOH, 7, 7) node _scheduleSet_T_8 = bits(mshr_selectOH, 8, 8) node _scheduleSet_T_9 = bits(mshr_selectOH, 9, 9) node _scheduleSet_T_10 = bits(mshr_selectOH, 10, 10) node _scheduleSet_T_11 = bits(mshr_selectOH, 11, 11) node _scheduleSet_T_12 = mux(_scheduleSet_T, mshrs_0.io.status.bits.set, UInt<1>(0h0)) node _scheduleSet_T_13 = mux(_scheduleSet_T_1, mshrs_1.io.status.bits.set, UInt<1>(0h0)) node _scheduleSet_T_14 = mux(_scheduleSet_T_2, mshrs_2.io.status.bits.set, UInt<1>(0h0)) node _scheduleSet_T_15 = mux(_scheduleSet_T_3, mshrs_3.io.status.bits.set, UInt<1>(0h0)) node _scheduleSet_T_16 = mux(_scheduleSet_T_4, mshrs_4.io.status.bits.set, UInt<1>(0h0)) node _scheduleSet_T_17 = mux(_scheduleSet_T_5, mshrs_5.io.status.bits.set, UInt<1>(0h0)) node _scheduleSet_T_18 = mux(_scheduleSet_T_6, mshrs_6.io.status.bits.set, UInt<1>(0h0)) node _scheduleSet_T_19 = mux(_scheduleSet_T_7, mshrs_7.io.status.bits.set, UInt<1>(0h0)) node _scheduleSet_T_20 = mux(_scheduleSet_T_8, mshrs_8.io.status.bits.set, UInt<1>(0h0)) node _scheduleSet_T_21 = mux(_scheduleSet_T_9, mshrs_9.io.status.bits.set, UInt<1>(0h0)) node _scheduleSet_T_22 = mux(_scheduleSet_T_10, mshrs_10.io.status.bits.set, UInt<1>(0h0)) node _scheduleSet_T_23 = mux(_scheduleSet_T_11, mshrs_11.io.status.bits.set, UInt<1>(0h0)) node _scheduleSet_T_24 = or(_scheduleSet_T_12, _scheduleSet_T_13) node _scheduleSet_T_25 = or(_scheduleSet_T_24, _scheduleSet_T_14) node _scheduleSet_T_26 = or(_scheduleSet_T_25, _scheduleSet_T_15) node _scheduleSet_T_27 = or(_scheduleSet_T_26, _scheduleSet_T_16) node _scheduleSet_T_28 = or(_scheduleSet_T_27, _scheduleSet_T_17) node _scheduleSet_T_29 = or(_scheduleSet_T_28, _scheduleSet_T_18) node _scheduleSet_T_30 = or(_scheduleSet_T_29, _scheduleSet_T_19) node _scheduleSet_T_31 = or(_scheduleSet_T_30, _scheduleSet_T_20) node _scheduleSet_T_32 = or(_scheduleSet_T_31, _scheduleSet_T_21) node _scheduleSet_T_33 = or(_scheduleSet_T_32, _scheduleSet_T_22) node _scheduleSet_T_34 = or(_scheduleSet_T_33, _scheduleSet_T_23) wire scheduleSet : UInt<11> connect scheduleSet, _scheduleSet_T_34 node _T_9 = orr(mshr_request) when _T_9 : node _robin_filter_T = shr(mshr_selectOH, 1) node _robin_filter_T_1 = or(mshr_selectOH, _robin_filter_T) node _robin_filter_T_2 = shr(_robin_filter_T_1, 2) node _robin_filter_T_3 = or(_robin_filter_T_1, _robin_filter_T_2) node _robin_filter_T_4 = shr(_robin_filter_T_3, 4) node _robin_filter_T_5 = or(_robin_filter_T_3, _robin_filter_T_4) node _robin_filter_T_6 = shr(_robin_filter_T_5, 8) node _robin_filter_T_7 = or(_robin_filter_T_5, _robin_filter_T_6) node _robin_filter_T_8 = bits(_robin_filter_T_7, 11, 0) node _robin_filter_T_9 = not(_robin_filter_T_8) connect robin_filter, _robin_filter_T_9 connect schedule.a.bits.source, mshr_select node _schedule_c_bits_source_T = bits(schedule.c.bits.opcode, 1, 1) node _schedule_c_bits_source_T_1 = mux(_schedule_c_bits_source_T, mshr_select, UInt<1>(0h0)) connect schedule.c.bits.source, _schedule_c_bits_source_T_1 connect schedule.d.bits.sink, mshr_select connect sourceA.io.req.valid, schedule.a.valid connect sourceB.io.req.valid, schedule.b.valid connect sourceC.io.req.valid, schedule.c.valid connect sourceD.io.req.valid, schedule.d.valid connect sourceE.io.req.valid, schedule.e.valid connect sourceX.io.req.valid, schedule.x.valid connect sourceA.io.req.bits.block, schedule.a.bits.block connect sourceA.io.req.bits.source, schedule.a.bits.source connect sourceA.io.req.bits.param, schedule.a.bits.param connect sourceA.io.req.bits.set, schedule.a.bits.set connect sourceA.io.req.bits.tag, schedule.a.bits.tag connect sourceB.io.req.bits.clients, schedule.b.bits.clients connect sourceB.io.req.bits.set, schedule.b.bits.set connect sourceB.io.req.bits.tag, schedule.b.bits.tag connect sourceB.io.req.bits.param, schedule.b.bits.param connect sourceC.io.req.bits.dirty, schedule.c.bits.dirty connect sourceC.io.req.bits.way, schedule.c.bits.way connect sourceC.io.req.bits.set, schedule.c.bits.set connect sourceC.io.req.bits.tag, schedule.c.bits.tag connect sourceC.io.req.bits.source, schedule.c.bits.source connect sourceC.io.req.bits.param, schedule.c.bits.param connect sourceC.io.req.bits.opcode, schedule.c.bits.opcode connect sourceD.io.req.bits.bad, schedule.d.bits.bad connect sourceD.io.req.bits.way, schedule.d.bits.way connect sourceD.io.req.bits.sink, schedule.d.bits.sink connect sourceD.io.req.bits.set, schedule.d.bits.set connect sourceD.io.req.bits.put, schedule.d.bits.put connect sourceD.io.req.bits.offset, schedule.d.bits.offset connect sourceD.io.req.bits.tag, schedule.d.bits.tag connect sourceD.io.req.bits.source, schedule.d.bits.source connect sourceD.io.req.bits.size, schedule.d.bits.size connect sourceD.io.req.bits.param, schedule.d.bits.param connect sourceD.io.req.bits.opcode, schedule.d.bits.opcode connect sourceD.io.req.bits.control, schedule.d.bits.control connect sourceD.io.req.bits.prio[0], schedule.d.bits.prio[0] connect sourceD.io.req.bits.prio[1], schedule.d.bits.prio[1] connect sourceD.io.req.bits.prio[2], schedule.d.bits.prio[2] connect sourceE.io.req.bits.sink, schedule.e.bits.sink connect sourceX.io.req.bits.fail, schedule.x.bits.fail connect directory.io.write.valid, schedule.dir.valid connect directory.io.write.bits.data.tag, schedule.dir.bits.data.tag connect directory.io.write.bits.data.clients, schedule.dir.bits.data.clients connect directory.io.write.bits.data.state, schedule.dir.bits.data.state connect directory.io.write.bits.data.dirty, schedule.dir.bits.data.dirty connect directory.io.write.bits.way, schedule.dir.bits.way connect directory.io.write.bits.set, schedule.dir.bits.set node select_c = bits(mshr_selectOH, 11, 11) node select_bc = bits(mshr_selectOH, 10, 10) node _nestedwb_set_T = mux(select_c, mshrs_11.io.status.bits.set, mshrs_10.io.status.bits.set) connect nestedwb.set, _nestedwb_set_T node _nestedwb_tag_T = mux(select_c, mshrs_11.io.status.bits.tag, mshrs_10.io.status.bits.tag) connect nestedwb.tag, _nestedwb_tag_T node _nestedwb_b_toN_T = and(select_bc, mshrs_10.io.schedule.bits.dir.valid) node _nestedwb_b_toN_T_1 = eq(mshrs_10.io.schedule.bits.dir.bits.data.state, UInt<2>(0h0)) node _nestedwb_b_toN_T_2 = and(_nestedwb_b_toN_T, _nestedwb_b_toN_T_1) connect nestedwb.b_toN, _nestedwb_b_toN_T_2 node _nestedwb_b_toB_T = and(select_bc, mshrs_10.io.schedule.bits.dir.valid) node _nestedwb_b_toB_T_1 = eq(mshrs_10.io.schedule.bits.dir.bits.data.state, UInt<2>(0h1)) node _nestedwb_b_toB_T_2 = and(_nestedwb_b_toB_T, _nestedwb_b_toB_T_1) connect nestedwb.b_toB, _nestedwb_b_toB_T_2 node _nestedwb_b_clr_dirty_T = and(select_bc, mshrs_10.io.schedule.bits.dir.valid) connect nestedwb.b_clr_dirty, _nestedwb_b_clr_dirty_T node _nestedwb_c_set_dirty_T = and(select_c, mshrs_11.io.schedule.bits.dir.valid) node _nestedwb_c_set_dirty_T_1 = and(_nestedwb_c_set_dirty_T, mshrs_11.io.schedule.bits.dir.bits.data.dirty) connect nestedwb.c_set_dirty, _nestedwb_c_set_dirty_T_1 wire request : { flip ready : UInt<1>, valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>}} node _request_valid_T = or(sinkA.io.req.valid, sinkX.io.req.valid) node _request_valid_T_1 = or(_request_valid_T, sinkC.io.req.valid) node _request_valid_T_2 = and(directory.io.ready, _request_valid_T_1) connect request.valid, _request_valid_T_2 node _request_bits_T = mux(sinkX.io.req.valid, sinkX.io.req.bits, sinkA.io.req.bits) node _request_bits_T_1 = mux(sinkC.io.req.valid, sinkC.io.req.bits, _request_bits_T) connect request.bits, _request_bits_T_1 node _sinkC_io_req_ready_T = and(directory.io.ready, request.ready) connect sinkC.io.req.ready, _sinkC_io_req_ready_T node _sinkX_io_req_ready_T = and(directory.io.ready, request.ready) node _sinkX_io_req_ready_T_1 = eq(sinkC.io.req.valid, UInt<1>(0h0)) node _sinkX_io_req_ready_T_2 = and(_sinkX_io_req_ready_T, _sinkX_io_req_ready_T_1) connect sinkX.io.req.ready, _sinkX_io_req_ready_T_2 node _sinkA_io_req_ready_T = and(directory.io.ready, request.ready) node _sinkA_io_req_ready_T_1 = eq(sinkC.io.req.valid, UInt<1>(0h0)) node _sinkA_io_req_ready_T_2 = and(_sinkA_io_req_ready_T, _sinkA_io_req_ready_T_1) node _sinkA_io_req_ready_T_3 = eq(sinkX.io.req.valid, UInt<1>(0h0)) node _sinkA_io_req_ready_T_4 = and(_sinkA_io_req_ready_T_2, _sinkA_io_req_ready_T_3) connect sinkA.io.req.ready, _sinkA_io_req_ready_T_4 node _setMatches_T = eq(mshrs_0.io.status.bits.set, request.bits.set) node _setMatches_T_1 = and(mshrs_0.io.status.valid, _setMatches_T) node _setMatches_T_2 = eq(mshrs_1.io.status.bits.set, request.bits.set) node _setMatches_T_3 = and(mshrs_1.io.status.valid, _setMatches_T_2) node _setMatches_T_4 = eq(mshrs_2.io.status.bits.set, request.bits.set) node _setMatches_T_5 = and(mshrs_2.io.status.valid, _setMatches_T_4) node _setMatches_T_6 = eq(mshrs_3.io.status.bits.set, request.bits.set) node _setMatches_T_7 = and(mshrs_3.io.status.valid, _setMatches_T_6) node _setMatches_T_8 = eq(mshrs_4.io.status.bits.set, request.bits.set) node _setMatches_T_9 = and(mshrs_4.io.status.valid, _setMatches_T_8) node _setMatches_T_10 = eq(mshrs_5.io.status.bits.set, request.bits.set) node _setMatches_T_11 = and(mshrs_5.io.status.valid, _setMatches_T_10) node _setMatches_T_12 = eq(mshrs_6.io.status.bits.set, request.bits.set) node _setMatches_T_13 = and(mshrs_6.io.status.valid, _setMatches_T_12) node _setMatches_T_14 = eq(mshrs_7.io.status.bits.set, request.bits.set) node _setMatches_T_15 = and(mshrs_7.io.status.valid, _setMatches_T_14) node _setMatches_T_16 = eq(mshrs_8.io.status.bits.set, request.bits.set) node _setMatches_T_17 = and(mshrs_8.io.status.valid, _setMatches_T_16) node _setMatches_T_18 = eq(mshrs_9.io.status.bits.set, request.bits.set) node _setMatches_T_19 = and(mshrs_9.io.status.valid, _setMatches_T_18) node _setMatches_T_20 = eq(mshrs_10.io.status.bits.set, request.bits.set) node _setMatches_T_21 = and(mshrs_10.io.status.valid, _setMatches_T_20) node _setMatches_T_22 = eq(mshrs_11.io.status.bits.set, request.bits.set) node _setMatches_T_23 = and(mshrs_11.io.status.valid, _setMatches_T_22) node setMatches_lo_lo_hi = cat(_setMatches_T_5, _setMatches_T_3) node setMatches_lo_lo = cat(setMatches_lo_lo_hi, _setMatches_T_1) node setMatches_lo_hi_hi = cat(_setMatches_T_11, _setMatches_T_9) node setMatches_lo_hi = cat(setMatches_lo_hi_hi, _setMatches_T_7) node setMatches_lo = cat(setMatches_lo_hi, setMatches_lo_lo) node setMatches_hi_lo_hi = cat(_setMatches_T_17, _setMatches_T_15) node setMatches_hi_lo = cat(setMatches_hi_lo_hi, _setMatches_T_13) node setMatches_hi_hi_hi = cat(_setMatches_T_23, _setMatches_T_21) node setMatches_hi_hi = cat(setMatches_hi_hi_hi, _setMatches_T_19) node setMatches_hi = cat(setMatches_hi_hi, setMatches_hi_lo) node setMatches = cat(setMatches_hi, setMatches_lo) node _alloc_T = orr(setMatches) node alloc = eq(_alloc_T, UInt<1>(0h0)) node _blockB_T = bits(setMatches, 0, 0) node _blockB_T_1 = bits(setMatches, 1, 1) node _blockB_T_2 = bits(setMatches, 2, 2) node _blockB_T_3 = bits(setMatches, 3, 3) node _blockB_T_4 = bits(setMatches, 4, 4) node _blockB_T_5 = bits(setMatches, 5, 5) node _blockB_T_6 = bits(setMatches, 6, 6) node _blockB_T_7 = bits(setMatches, 7, 7) node _blockB_T_8 = bits(setMatches, 8, 8) node _blockB_T_9 = bits(setMatches, 9, 9) node _blockB_T_10 = bits(setMatches, 10, 10) node _blockB_T_11 = bits(setMatches, 11, 11) node _blockB_T_12 = mux(_blockB_T, mshrs_0.io.status.bits.blockB, UInt<1>(0h0)) node _blockB_T_13 = mux(_blockB_T_1, mshrs_1.io.status.bits.blockB, UInt<1>(0h0)) node _blockB_T_14 = mux(_blockB_T_2, mshrs_2.io.status.bits.blockB, UInt<1>(0h0)) node _blockB_T_15 = mux(_blockB_T_3, mshrs_3.io.status.bits.blockB, UInt<1>(0h0)) node _blockB_T_16 = mux(_blockB_T_4, mshrs_4.io.status.bits.blockB, UInt<1>(0h0)) node _blockB_T_17 = mux(_blockB_T_5, mshrs_5.io.status.bits.blockB, UInt<1>(0h0)) node _blockB_T_18 = mux(_blockB_T_6, mshrs_6.io.status.bits.blockB, UInt<1>(0h0)) node _blockB_T_19 = mux(_blockB_T_7, mshrs_7.io.status.bits.blockB, UInt<1>(0h0)) node _blockB_T_20 = mux(_blockB_T_8, mshrs_8.io.status.bits.blockB, UInt<1>(0h0)) node _blockB_T_21 = mux(_blockB_T_9, mshrs_9.io.status.bits.blockB, UInt<1>(0h0)) node _blockB_T_22 = mux(_blockB_T_10, mshrs_10.io.status.bits.blockB, UInt<1>(0h0)) node _blockB_T_23 = mux(_blockB_T_11, mshrs_11.io.status.bits.blockB, UInt<1>(0h0)) node _blockB_T_24 = or(_blockB_T_12, _blockB_T_13) node _blockB_T_25 = or(_blockB_T_24, _blockB_T_14) node _blockB_T_26 = or(_blockB_T_25, _blockB_T_15) node _blockB_T_27 = or(_blockB_T_26, _blockB_T_16) node _blockB_T_28 = or(_blockB_T_27, _blockB_T_17) node _blockB_T_29 = or(_blockB_T_28, _blockB_T_18) node _blockB_T_30 = or(_blockB_T_29, _blockB_T_19) node _blockB_T_31 = or(_blockB_T_30, _blockB_T_20) node _blockB_T_32 = or(_blockB_T_31, _blockB_T_21) node _blockB_T_33 = or(_blockB_T_32, _blockB_T_22) node _blockB_T_34 = or(_blockB_T_33, _blockB_T_23) wire _blockB_WIRE : UInt<1> connect _blockB_WIRE, _blockB_T_34 node blockB = and(_blockB_WIRE, request.bits.prio[1]) node _blockC_T = bits(setMatches, 0, 0) node _blockC_T_1 = bits(setMatches, 1, 1) node _blockC_T_2 = bits(setMatches, 2, 2) node _blockC_T_3 = bits(setMatches, 3, 3) node _blockC_T_4 = bits(setMatches, 4, 4) node _blockC_T_5 = bits(setMatches, 5, 5) node _blockC_T_6 = bits(setMatches, 6, 6) node _blockC_T_7 = bits(setMatches, 7, 7) node _blockC_T_8 = bits(setMatches, 8, 8) node _blockC_T_9 = bits(setMatches, 9, 9) node _blockC_T_10 = bits(setMatches, 10, 10) node _blockC_T_11 = bits(setMatches, 11, 11) node _blockC_T_12 = mux(_blockC_T, mshrs_0.io.status.bits.blockC, UInt<1>(0h0)) node _blockC_T_13 = mux(_blockC_T_1, mshrs_1.io.status.bits.blockC, UInt<1>(0h0)) node _blockC_T_14 = mux(_blockC_T_2, mshrs_2.io.status.bits.blockC, UInt<1>(0h0)) node _blockC_T_15 = mux(_blockC_T_3, mshrs_3.io.status.bits.blockC, UInt<1>(0h0)) node _blockC_T_16 = mux(_blockC_T_4, mshrs_4.io.status.bits.blockC, UInt<1>(0h0)) node _blockC_T_17 = mux(_blockC_T_5, mshrs_5.io.status.bits.blockC, UInt<1>(0h0)) node _blockC_T_18 = mux(_blockC_T_6, mshrs_6.io.status.bits.blockC, UInt<1>(0h0)) node _blockC_T_19 = mux(_blockC_T_7, mshrs_7.io.status.bits.blockC, UInt<1>(0h0)) node _blockC_T_20 = mux(_blockC_T_8, mshrs_8.io.status.bits.blockC, UInt<1>(0h0)) node _blockC_T_21 = mux(_blockC_T_9, mshrs_9.io.status.bits.blockC, UInt<1>(0h0)) node _blockC_T_22 = mux(_blockC_T_10, mshrs_10.io.status.bits.blockC, UInt<1>(0h0)) node _blockC_T_23 = mux(_blockC_T_11, mshrs_11.io.status.bits.blockC, UInt<1>(0h0)) node _blockC_T_24 = or(_blockC_T_12, _blockC_T_13) node _blockC_T_25 = or(_blockC_T_24, _blockC_T_14) node _blockC_T_26 = or(_blockC_T_25, _blockC_T_15) node _blockC_T_27 = or(_blockC_T_26, _blockC_T_16) node _blockC_T_28 = or(_blockC_T_27, _blockC_T_17) node _blockC_T_29 = or(_blockC_T_28, _blockC_T_18) node _blockC_T_30 = or(_blockC_T_29, _blockC_T_19) node _blockC_T_31 = or(_blockC_T_30, _blockC_T_20) node _blockC_T_32 = or(_blockC_T_31, _blockC_T_21) node _blockC_T_33 = or(_blockC_T_32, _blockC_T_22) node _blockC_T_34 = or(_blockC_T_33, _blockC_T_23) wire _blockC_WIRE : UInt<1> connect _blockC_WIRE, _blockC_T_34 node blockC = and(_blockC_WIRE, request.bits.prio[2]) node _nestB_T = bits(setMatches, 0, 0) node _nestB_T_1 = bits(setMatches, 1, 1) node _nestB_T_2 = bits(setMatches, 2, 2) node _nestB_T_3 = bits(setMatches, 3, 3) node _nestB_T_4 = bits(setMatches, 4, 4) node _nestB_T_5 = bits(setMatches, 5, 5) node _nestB_T_6 = bits(setMatches, 6, 6) node _nestB_T_7 = bits(setMatches, 7, 7) node _nestB_T_8 = bits(setMatches, 8, 8) node _nestB_T_9 = bits(setMatches, 9, 9) node _nestB_T_10 = bits(setMatches, 10, 10) node _nestB_T_11 = bits(setMatches, 11, 11) node _nestB_T_12 = mux(_nestB_T, mshrs_0.io.status.bits.nestB, UInt<1>(0h0)) node _nestB_T_13 = mux(_nestB_T_1, mshrs_1.io.status.bits.nestB, UInt<1>(0h0)) node _nestB_T_14 = mux(_nestB_T_2, mshrs_2.io.status.bits.nestB, UInt<1>(0h0)) node _nestB_T_15 = mux(_nestB_T_3, mshrs_3.io.status.bits.nestB, UInt<1>(0h0)) node _nestB_T_16 = mux(_nestB_T_4, mshrs_4.io.status.bits.nestB, UInt<1>(0h0)) node _nestB_T_17 = mux(_nestB_T_5, mshrs_5.io.status.bits.nestB, UInt<1>(0h0)) node _nestB_T_18 = mux(_nestB_T_6, mshrs_6.io.status.bits.nestB, UInt<1>(0h0)) node _nestB_T_19 = mux(_nestB_T_7, mshrs_7.io.status.bits.nestB, UInt<1>(0h0)) node _nestB_T_20 = mux(_nestB_T_8, mshrs_8.io.status.bits.nestB, UInt<1>(0h0)) node _nestB_T_21 = mux(_nestB_T_9, mshrs_9.io.status.bits.nestB, UInt<1>(0h0)) node _nestB_T_22 = mux(_nestB_T_10, mshrs_10.io.status.bits.nestB, UInt<1>(0h0)) node _nestB_T_23 = mux(_nestB_T_11, mshrs_11.io.status.bits.nestB, UInt<1>(0h0)) node _nestB_T_24 = or(_nestB_T_12, _nestB_T_13) node _nestB_T_25 = or(_nestB_T_24, _nestB_T_14) node _nestB_T_26 = or(_nestB_T_25, _nestB_T_15) node _nestB_T_27 = or(_nestB_T_26, _nestB_T_16) node _nestB_T_28 = or(_nestB_T_27, _nestB_T_17) node _nestB_T_29 = or(_nestB_T_28, _nestB_T_18) node _nestB_T_30 = or(_nestB_T_29, _nestB_T_19) node _nestB_T_31 = or(_nestB_T_30, _nestB_T_20) node _nestB_T_32 = or(_nestB_T_31, _nestB_T_21) node _nestB_T_33 = or(_nestB_T_32, _nestB_T_22) node _nestB_T_34 = or(_nestB_T_33, _nestB_T_23) wire _nestB_WIRE : UInt<1> connect _nestB_WIRE, _nestB_T_34 node nestB = and(_nestB_WIRE, request.bits.prio[1]) node _nestC_T = bits(setMatches, 0, 0) node _nestC_T_1 = bits(setMatches, 1, 1) node _nestC_T_2 = bits(setMatches, 2, 2) node _nestC_T_3 = bits(setMatches, 3, 3) node _nestC_T_4 = bits(setMatches, 4, 4) node _nestC_T_5 = bits(setMatches, 5, 5) node _nestC_T_6 = bits(setMatches, 6, 6) node _nestC_T_7 = bits(setMatches, 7, 7) node _nestC_T_8 = bits(setMatches, 8, 8) node _nestC_T_9 = bits(setMatches, 9, 9) node _nestC_T_10 = bits(setMatches, 10, 10) node _nestC_T_11 = bits(setMatches, 11, 11) node _nestC_T_12 = mux(_nestC_T, mshrs_0.io.status.bits.nestC, UInt<1>(0h0)) node _nestC_T_13 = mux(_nestC_T_1, mshrs_1.io.status.bits.nestC, UInt<1>(0h0)) node _nestC_T_14 = mux(_nestC_T_2, mshrs_2.io.status.bits.nestC, UInt<1>(0h0)) node _nestC_T_15 = mux(_nestC_T_3, mshrs_3.io.status.bits.nestC, UInt<1>(0h0)) node _nestC_T_16 = mux(_nestC_T_4, mshrs_4.io.status.bits.nestC, UInt<1>(0h0)) node _nestC_T_17 = mux(_nestC_T_5, mshrs_5.io.status.bits.nestC, UInt<1>(0h0)) node _nestC_T_18 = mux(_nestC_T_6, mshrs_6.io.status.bits.nestC, UInt<1>(0h0)) node _nestC_T_19 = mux(_nestC_T_7, mshrs_7.io.status.bits.nestC, UInt<1>(0h0)) node _nestC_T_20 = mux(_nestC_T_8, mshrs_8.io.status.bits.nestC, UInt<1>(0h0)) node _nestC_T_21 = mux(_nestC_T_9, mshrs_9.io.status.bits.nestC, UInt<1>(0h0)) node _nestC_T_22 = mux(_nestC_T_10, mshrs_10.io.status.bits.nestC, UInt<1>(0h0)) node _nestC_T_23 = mux(_nestC_T_11, mshrs_11.io.status.bits.nestC, UInt<1>(0h0)) node _nestC_T_24 = or(_nestC_T_12, _nestC_T_13) node _nestC_T_25 = or(_nestC_T_24, _nestC_T_14) node _nestC_T_26 = or(_nestC_T_25, _nestC_T_15) node _nestC_T_27 = or(_nestC_T_26, _nestC_T_16) node _nestC_T_28 = or(_nestC_T_27, _nestC_T_17) node _nestC_T_29 = or(_nestC_T_28, _nestC_T_18) node _nestC_T_30 = or(_nestC_T_29, _nestC_T_19) node _nestC_T_31 = or(_nestC_T_30, _nestC_T_20) node _nestC_T_32 = or(_nestC_T_31, _nestC_T_21) node _nestC_T_33 = or(_nestC_T_32, _nestC_T_22) node _nestC_T_34 = or(_nestC_T_33, _nestC_T_23) wire _nestC_WIRE : UInt<1> connect _nestC_WIRE, _nestC_T_34 node nestC = and(_nestC_WIRE, request.bits.prio[2]) node _prioFilter_T = eq(request.bits.prio[0], UInt<1>(0h0)) node _prioFilter_T_1 = not(UInt<10>(0h0)) node prioFilter_hi = cat(request.bits.prio[2], _prioFilter_T) node prioFilter = cat(prioFilter_hi, _prioFilter_T_1) node lowerMatches = and(setMatches, prioFilter) node _queue_T = orr(lowerMatches) node _queue_T_1 = eq(nestB, UInt<1>(0h0)) node _queue_T_2 = and(_queue_T, _queue_T_1) node _queue_T_3 = eq(nestC, UInt<1>(0h0)) node _queue_T_4 = and(_queue_T_2, _queue_T_3) node _queue_T_5 = eq(blockB, UInt<1>(0h0)) node _queue_T_6 = and(_queue_T_4, _queue_T_5) node _queue_T_7 = eq(blockC, UInt<1>(0h0)) node queue = and(_queue_T_6, _queue_T_7) node _T_10 = and(request.valid, blockC) node _T_11 = and(request.valid, nestC) node _T_12 = and(request.valid, queue) node _lowerMatches1_T = bits(lowerMatches, 11, 11) node _lowerMatches1_T_1 = shl(UInt<1>(0h1), 11) node _lowerMatches1_T_2 = bits(lowerMatches, 10, 10) node _lowerMatches1_T_3 = shl(UInt<1>(0h1), 10) node _lowerMatches1_T_4 = mux(_lowerMatches1_T_2, _lowerMatches1_T_3, lowerMatches) node lowerMatches1 = mux(_lowerMatches1_T, _lowerMatches1_T_1, _lowerMatches1_T_4) node selected_requests_hi = cat(mshr_selectOH, mshr_selectOH) node _selected_requests_T = cat(selected_requests_hi, mshr_selectOH) node selected_requests = and(_selected_requests_T, requests.io.valid) node _a_pop_T = bits(selected_requests, 11, 0) node a_pop = orr(_a_pop_T) node _b_pop_T = bits(selected_requests, 23, 12) node b_pop = orr(_b_pop_T) node _c_pop_T = bits(selected_requests, 35, 24) node c_pop = orr(_c_pop_T) node _bypassMatches_T = and(mshr_selectOH, lowerMatches1) node _bypassMatches_T_1 = orr(_bypassMatches_T) node _bypassMatches_T_2 = or(c_pop, request.bits.prio[2]) node _bypassMatches_T_3 = eq(c_pop, UInt<1>(0h0)) node _bypassMatches_T_4 = or(b_pop, request.bits.prio[1]) node _bypassMatches_T_5 = eq(b_pop, UInt<1>(0h0)) node _bypassMatches_T_6 = eq(a_pop, UInt<1>(0h0)) node _bypassMatches_T_7 = mux(_bypassMatches_T_4, _bypassMatches_T_5, _bypassMatches_T_6) node _bypassMatches_T_8 = mux(_bypassMatches_T_2, _bypassMatches_T_3, _bypassMatches_T_7) node bypassMatches = and(_bypassMatches_T_1, _bypassMatches_T_8) node _may_pop_T = or(a_pop, b_pop) node may_pop = or(_may_pop_T, c_pop) node _bypass_T = and(request.valid, queue) node bypass = and(_bypass_T, bypassMatches) node _will_reload_T = or(may_pop, bypass) node will_reload = and(schedule.reload, _will_reload_T) node _will_pop_T = and(schedule.reload, may_pop) node _will_pop_T_1 = eq(bypass, UInt<1>(0h0)) node will_pop = and(_will_pop_T, _will_pop_T_1) node _T_13 = orr(mshr_selectOH) node _T_14 = and(_T_13, bypass) node _T_15 = orr(mshr_selectOH) node _T_16 = and(_T_15, will_reload) node _T_17 = orr(mshr_selectOH) node _T_18 = and(_T_17, will_pop) node sel = bits(mshr_selectOH, 0, 0) connect mshrs_0.io.schedule.ready, sel node a_pop_1 = bits(requests.io.valid, 0, 0) node b_pop_1 = bits(requests.io.valid, 12, 12) node c_pop_1 = bits(requests.io.valid, 24, 24) node _bypassMatches_T_9 = bits(lowerMatches1, 0, 0) node _bypassMatches_T_10 = or(c_pop_1, request.bits.prio[2]) node _bypassMatches_T_11 = eq(c_pop_1, UInt<1>(0h0)) node _bypassMatches_T_12 = or(b_pop_1, request.bits.prio[1]) node _bypassMatches_T_13 = eq(b_pop_1, UInt<1>(0h0)) node _bypassMatches_T_14 = eq(a_pop_1, UInt<1>(0h0)) node _bypassMatches_T_15 = mux(_bypassMatches_T_12, _bypassMatches_T_13, _bypassMatches_T_14) node _bypassMatches_T_16 = mux(_bypassMatches_T_10, _bypassMatches_T_11, _bypassMatches_T_15) node bypassMatches_1 = and(_bypassMatches_T_9, _bypassMatches_T_16) node _may_pop_T_1 = or(a_pop_1, b_pop_1) node may_pop_1 = or(_may_pop_T_1, c_pop_1) node _bypass_T_1 = and(request.valid, queue) node bypass_1 = and(_bypass_T_1, bypassMatches_1) node _will_reload_T_1 = or(may_pop_1, bypass_1) node will_reload_1 = and(mshrs_0.io.schedule.bits.reload, _will_reload_T_1) wire _view__WIRE : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>} connect _view__WIRE.put, request.bits.put connect _view__WIRE.offset, request.bits.offset connect _view__WIRE.tag, request.bits.tag connect _view__WIRE.source, request.bits.source connect _view__WIRE.size, request.bits.size connect _view__WIRE.param, request.bits.param connect _view__WIRE.opcode, request.bits.opcode connect _view__WIRE.control, request.bits.control connect _view__WIRE.prio, request.bits.prio node _view__T = mux(bypass_1, _view__WIRE, requests.io.data) connect mshrs_0.io.allocate.bits.put, _view__T.put connect mshrs_0.io.allocate.bits.offset, _view__T.offset connect mshrs_0.io.allocate.bits.tag, _view__T.tag connect mshrs_0.io.allocate.bits.source, _view__T.source connect mshrs_0.io.allocate.bits.size, _view__T.size connect mshrs_0.io.allocate.bits.param, _view__T.param connect mshrs_0.io.allocate.bits.opcode, _view__T.opcode connect mshrs_0.io.allocate.bits.control, _view__T.control connect mshrs_0.io.allocate.bits.prio[0], _view__T.prio[0] connect mshrs_0.io.allocate.bits.prio[1], _view__T.prio[1] connect mshrs_0.io.allocate.bits.prio[2], _view__T.prio[2] connect mshrs_0.io.allocate.bits.set, mshrs_0.io.status.bits.set node _mshrs_0_io_allocate_bits_repeat_T = eq(mshrs_0.io.allocate.bits.tag, mshrs_0.io.status.bits.tag) connect mshrs_0.io.allocate.bits.repeat, _mshrs_0_io_allocate_bits_repeat_T node _mshrs_0_io_allocate_valid_T = and(sel, will_reload_1) connect mshrs_0.io.allocate.valid, _mshrs_0_io_allocate_valid_T node sel_1 = bits(mshr_selectOH, 1, 1) connect mshrs_1.io.schedule.ready, sel_1 node a_pop_2 = bits(requests.io.valid, 1, 1) node b_pop_2 = bits(requests.io.valid, 13, 13) node c_pop_2 = bits(requests.io.valid, 25, 25) node _bypassMatches_T_17 = bits(lowerMatches1, 1, 1) node _bypassMatches_T_18 = or(c_pop_2, request.bits.prio[2]) node _bypassMatches_T_19 = eq(c_pop_2, UInt<1>(0h0)) node _bypassMatches_T_20 = or(b_pop_2, request.bits.prio[1]) node _bypassMatches_T_21 = eq(b_pop_2, UInt<1>(0h0)) node _bypassMatches_T_22 = eq(a_pop_2, UInt<1>(0h0)) node _bypassMatches_T_23 = mux(_bypassMatches_T_20, _bypassMatches_T_21, _bypassMatches_T_22) node _bypassMatches_T_24 = mux(_bypassMatches_T_18, _bypassMatches_T_19, _bypassMatches_T_23) node bypassMatches_2 = and(_bypassMatches_T_17, _bypassMatches_T_24) node _may_pop_T_2 = or(a_pop_2, b_pop_2) node may_pop_2 = or(_may_pop_T_2, c_pop_2) node _bypass_T_2 = and(request.valid, queue) node bypass_2 = and(_bypass_T_2, bypassMatches_2) node _will_reload_T_2 = or(may_pop_2, bypass_2) node will_reload_2 = and(mshrs_1.io.schedule.bits.reload, _will_reload_T_2) wire _view__WIRE_1 : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>} connect _view__WIRE_1.put, request.bits.put connect _view__WIRE_1.offset, request.bits.offset connect _view__WIRE_1.tag, request.bits.tag connect _view__WIRE_1.source, request.bits.source connect _view__WIRE_1.size, request.bits.size connect _view__WIRE_1.param, request.bits.param connect _view__WIRE_1.opcode, request.bits.opcode connect _view__WIRE_1.control, request.bits.control connect _view__WIRE_1.prio, request.bits.prio node _view__T_1 = mux(bypass_2, _view__WIRE_1, requests.io.data) connect mshrs_1.io.allocate.bits.put, _view__T_1.put connect mshrs_1.io.allocate.bits.offset, _view__T_1.offset connect mshrs_1.io.allocate.bits.tag, _view__T_1.tag connect mshrs_1.io.allocate.bits.source, _view__T_1.source connect mshrs_1.io.allocate.bits.size, _view__T_1.size connect mshrs_1.io.allocate.bits.param, _view__T_1.param connect mshrs_1.io.allocate.bits.opcode, _view__T_1.opcode connect mshrs_1.io.allocate.bits.control, _view__T_1.control connect mshrs_1.io.allocate.bits.prio[0], _view__T_1.prio[0] connect mshrs_1.io.allocate.bits.prio[1], _view__T_1.prio[1] connect mshrs_1.io.allocate.bits.prio[2], _view__T_1.prio[2] connect mshrs_1.io.allocate.bits.set, mshrs_1.io.status.bits.set node _mshrs_1_io_allocate_bits_repeat_T = eq(mshrs_1.io.allocate.bits.tag, mshrs_1.io.status.bits.tag) connect mshrs_1.io.allocate.bits.repeat, _mshrs_1_io_allocate_bits_repeat_T node _mshrs_1_io_allocate_valid_T = and(sel_1, will_reload_2) connect mshrs_1.io.allocate.valid, _mshrs_1_io_allocate_valid_T node sel_2 = bits(mshr_selectOH, 2, 2) connect mshrs_2.io.schedule.ready, sel_2 node a_pop_3 = bits(requests.io.valid, 2, 2) node b_pop_3 = bits(requests.io.valid, 14, 14) node c_pop_3 = bits(requests.io.valid, 26, 26) node _bypassMatches_T_25 = bits(lowerMatches1, 2, 2) node _bypassMatches_T_26 = or(c_pop_3, request.bits.prio[2]) node _bypassMatches_T_27 = eq(c_pop_3, UInt<1>(0h0)) node _bypassMatches_T_28 = or(b_pop_3, request.bits.prio[1]) node _bypassMatches_T_29 = eq(b_pop_3, UInt<1>(0h0)) node _bypassMatches_T_30 = eq(a_pop_3, UInt<1>(0h0)) node _bypassMatches_T_31 = mux(_bypassMatches_T_28, _bypassMatches_T_29, _bypassMatches_T_30) node _bypassMatches_T_32 = mux(_bypassMatches_T_26, _bypassMatches_T_27, _bypassMatches_T_31) node bypassMatches_3 = and(_bypassMatches_T_25, _bypassMatches_T_32) node _may_pop_T_3 = or(a_pop_3, b_pop_3) node may_pop_3 = or(_may_pop_T_3, c_pop_3) node _bypass_T_3 = and(request.valid, queue) node bypass_3 = and(_bypass_T_3, bypassMatches_3) node _will_reload_T_3 = or(may_pop_3, bypass_3) node will_reload_3 = and(mshrs_2.io.schedule.bits.reload, _will_reload_T_3) wire _view__WIRE_2 : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>} connect _view__WIRE_2.put, request.bits.put connect _view__WIRE_2.offset, request.bits.offset connect _view__WIRE_2.tag, request.bits.tag connect _view__WIRE_2.source, request.bits.source connect _view__WIRE_2.size, request.bits.size connect _view__WIRE_2.param, request.bits.param connect _view__WIRE_2.opcode, request.bits.opcode connect _view__WIRE_2.control, request.bits.control connect _view__WIRE_2.prio, request.bits.prio node _view__T_2 = mux(bypass_3, _view__WIRE_2, requests.io.data) connect mshrs_2.io.allocate.bits.put, _view__T_2.put connect mshrs_2.io.allocate.bits.offset, _view__T_2.offset connect mshrs_2.io.allocate.bits.tag, _view__T_2.tag connect mshrs_2.io.allocate.bits.source, _view__T_2.source connect mshrs_2.io.allocate.bits.size, _view__T_2.size connect mshrs_2.io.allocate.bits.param, _view__T_2.param connect mshrs_2.io.allocate.bits.opcode, _view__T_2.opcode connect mshrs_2.io.allocate.bits.control, _view__T_2.control connect mshrs_2.io.allocate.bits.prio[0], _view__T_2.prio[0] connect mshrs_2.io.allocate.bits.prio[1], _view__T_2.prio[1] connect mshrs_2.io.allocate.bits.prio[2], _view__T_2.prio[2] connect mshrs_2.io.allocate.bits.set, mshrs_2.io.status.bits.set node _mshrs_2_io_allocate_bits_repeat_T = eq(mshrs_2.io.allocate.bits.tag, mshrs_2.io.status.bits.tag) connect mshrs_2.io.allocate.bits.repeat, _mshrs_2_io_allocate_bits_repeat_T node _mshrs_2_io_allocate_valid_T = and(sel_2, will_reload_3) connect mshrs_2.io.allocate.valid, _mshrs_2_io_allocate_valid_T node sel_3 = bits(mshr_selectOH, 3, 3) connect mshrs_3.io.schedule.ready, sel_3 node a_pop_4 = bits(requests.io.valid, 3, 3) node b_pop_4 = bits(requests.io.valid, 15, 15) node c_pop_4 = bits(requests.io.valid, 27, 27) node _bypassMatches_T_33 = bits(lowerMatches1, 3, 3) node _bypassMatches_T_34 = or(c_pop_4, request.bits.prio[2]) node _bypassMatches_T_35 = eq(c_pop_4, UInt<1>(0h0)) node _bypassMatches_T_36 = or(b_pop_4, request.bits.prio[1]) node _bypassMatches_T_37 = eq(b_pop_4, UInt<1>(0h0)) node _bypassMatches_T_38 = eq(a_pop_4, UInt<1>(0h0)) node _bypassMatches_T_39 = mux(_bypassMatches_T_36, _bypassMatches_T_37, _bypassMatches_T_38) node _bypassMatches_T_40 = mux(_bypassMatches_T_34, _bypassMatches_T_35, _bypassMatches_T_39) node bypassMatches_4 = and(_bypassMatches_T_33, _bypassMatches_T_40) node _may_pop_T_4 = or(a_pop_4, b_pop_4) node may_pop_4 = or(_may_pop_T_4, c_pop_4) node _bypass_T_4 = and(request.valid, queue) node bypass_4 = and(_bypass_T_4, bypassMatches_4) node _will_reload_T_4 = or(may_pop_4, bypass_4) node will_reload_4 = and(mshrs_3.io.schedule.bits.reload, _will_reload_T_4) wire _view__WIRE_3 : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>} connect _view__WIRE_3.put, request.bits.put connect _view__WIRE_3.offset, request.bits.offset connect _view__WIRE_3.tag, request.bits.tag connect _view__WIRE_3.source, request.bits.source connect _view__WIRE_3.size, request.bits.size connect _view__WIRE_3.param, request.bits.param connect _view__WIRE_3.opcode, request.bits.opcode connect _view__WIRE_3.control, request.bits.control connect _view__WIRE_3.prio, request.bits.prio node _view__T_3 = mux(bypass_4, _view__WIRE_3, requests.io.data) connect mshrs_3.io.allocate.bits.put, _view__T_3.put connect mshrs_3.io.allocate.bits.offset, _view__T_3.offset connect mshrs_3.io.allocate.bits.tag, _view__T_3.tag connect mshrs_3.io.allocate.bits.source, _view__T_3.source connect mshrs_3.io.allocate.bits.size, _view__T_3.size connect mshrs_3.io.allocate.bits.param, _view__T_3.param connect mshrs_3.io.allocate.bits.opcode, _view__T_3.opcode connect mshrs_3.io.allocate.bits.control, _view__T_3.control connect mshrs_3.io.allocate.bits.prio[0], _view__T_3.prio[0] connect mshrs_3.io.allocate.bits.prio[1], _view__T_3.prio[1] connect mshrs_3.io.allocate.bits.prio[2], _view__T_3.prio[2] connect mshrs_3.io.allocate.bits.set, mshrs_3.io.status.bits.set node _mshrs_3_io_allocate_bits_repeat_T = eq(mshrs_3.io.allocate.bits.tag, mshrs_3.io.status.bits.tag) connect mshrs_3.io.allocate.bits.repeat, _mshrs_3_io_allocate_bits_repeat_T node _mshrs_3_io_allocate_valid_T = and(sel_3, will_reload_4) connect mshrs_3.io.allocate.valid, _mshrs_3_io_allocate_valid_T node sel_4 = bits(mshr_selectOH, 4, 4) connect mshrs_4.io.schedule.ready, sel_4 node a_pop_5 = bits(requests.io.valid, 4, 4) node b_pop_5 = bits(requests.io.valid, 16, 16) node c_pop_5 = bits(requests.io.valid, 28, 28) node _bypassMatches_T_41 = bits(lowerMatches1, 4, 4) node _bypassMatches_T_42 = or(c_pop_5, request.bits.prio[2]) node _bypassMatches_T_43 = eq(c_pop_5, UInt<1>(0h0)) node _bypassMatches_T_44 = or(b_pop_5, request.bits.prio[1]) node _bypassMatches_T_45 = eq(b_pop_5, UInt<1>(0h0)) node _bypassMatches_T_46 = eq(a_pop_5, UInt<1>(0h0)) node _bypassMatches_T_47 = mux(_bypassMatches_T_44, _bypassMatches_T_45, _bypassMatches_T_46) node _bypassMatches_T_48 = mux(_bypassMatches_T_42, _bypassMatches_T_43, _bypassMatches_T_47) node bypassMatches_5 = and(_bypassMatches_T_41, _bypassMatches_T_48) node _may_pop_T_5 = or(a_pop_5, b_pop_5) node may_pop_5 = or(_may_pop_T_5, c_pop_5) node _bypass_T_5 = and(request.valid, queue) node bypass_5 = and(_bypass_T_5, bypassMatches_5) node _will_reload_T_5 = or(may_pop_5, bypass_5) node will_reload_5 = and(mshrs_4.io.schedule.bits.reload, _will_reload_T_5) wire _view__WIRE_4 : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>} connect _view__WIRE_4.put, request.bits.put connect _view__WIRE_4.offset, request.bits.offset connect _view__WIRE_4.tag, request.bits.tag connect _view__WIRE_4.source, request.bits.source connect _view__WIRE_4.size, request.bits.size connect _view__WIRE_4.param, request.bits.param connect _view__WIRE_4.opcode, request.bits.opcode connect _view__WIRE_4.control, request.bits.control connect _view__WIRE_4.prio, request.bits.prio node _view__T_4 = mux(bypass_5, _view__WIRE_4, requests.io.data) connect mshrs_4.io.allocate.bits.put, _view__T_4.put connect mshrs_4.io.allocate.bits.offset, _view__T_4.offset connect mshrs_4.io.allocate.bits.tag, _view__T_4.tag connect mshrs_4.io.allocate.bits.source, _view__T_4.source connect mshrs_4.io.allocate.bits.size, _view__T_4.size connect mshrs_4.io.allocate.bits.param, _view__T_4.param connect mshrs_4.io.allocate.bits.opcode, _view__T_4.opcode connect mshrs_4.io.allocate.bits.control, _view__T_4.control connect mshrs_4.io.allocate.bits.prio[0], _view__T_4.prio[0] connect mshrs_4.io.allocate.bits.prio[1], _view__T_4.prio[1] connect mshrs_4.io.allocate.bits.prio[2], _view__T_4.prio[2] connect mshrs_4.io.allocate.bits.set, mshrs_4.io.status.bits.set node _mshrs_4_io_allocate_bits_repeat_T = eq(mshrs_4.io.allocate.bits.tag, mshrs_4.io.status.bits.tag) connect mshrs_4.io.allocate.bits.repeat, _mshrs_4_io_allocate_bits_repeat_T node _mshrs_4_io_allocate_valid_T = and(sel_4, will_reload_5) connect mshrs_4.io.allocate.valid, _mshrs_4_io_allocate_valid_T node sel_5 = bits(mshr_selectOH, 5, 5) connect mshrs_5.io.schedule.ready, sel_5 node a_pop_6 = bits(requests.io.valid, 5, 5) node b_pop_6 = bits(requests.io.valid, 17, 17) node c_pop_6 = bits(requests.io.valid, 29, 29) node _bypassMatches_T_49 = bits(lowerMatches1, 5, 5) node _bypassMatches_T_50 = or(c_pop_6, request.bits.prio[2]) node _bypassMatches_T_51 = eq(c_pop_6, UInt<1>(0h0)) node _bypassMatches_T_52 = or(b_pop_6, request.bits.prio[1]) node _bypassMatches_T_53 = eq(b_pop_6, UInt<1>(0h0)) node _bypassMatches_T_54 = eq(a_pop_6, UInt<1>(0h0)) node _bypassMatches_T_55 = mux(_bypassMatches_T_52, _bypassMatches_T_53, _bypassMatches_T_54) node _bypassMatches_T_56 = mux(_bypassMatches_T_50, _bypassMatches_T_51, _bypassMatches_T_55) node bypassMatches_6 = and(_bypassMatches_T_49, _bypassMatches_T_56) node _may_pop_T_6 = or(a_pop_6, b_pop_6) node may_pop_6 = or(_may_pop_T_6, c_pop_6) node _bypass_T_6 = and(request.valid, queue) node bypass_6 = and(_bypass_T_6, bypassMatches_6) node _will_reload_T_6 = or(may_pop_6, bypass_6) node will_reload_6 = and(mshrs_5.io.schedule.bits.reload, _will_reload_T_6) wire _view__WIRE_5 : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>} connect _view__WIRE_5.put, request.bits.put connect _view__WIRE_5.offset, request.bits.offset connect _view__WIRE_5.tag, request.bits.tag connect _view__WIRE_5.source, request.bits.source connect _view__WIRE_5.size, request.bits.size connect _view__WIRE_5.param, request.bits.param connect _view__WIRE_5.opcode, request.bits.opcode connect _view__WIRE_5.control, request.bits.control connect _view__WIRE_5.prio, request.bits.prio node _view__T_5 = mux(bypass_6, _view__WIRE_5, requests.io.data) connect mshrs_5.io.allocate.bits.put, _view__T_5.put connect mshrs_5.io.allocate.bits.offset, _view__T_5.offset connect mshrs_5.io.allocate.bits.tag, _view__T_5.tag connect mshrs_5.io.allocate.bits.source, _view__T_5.source connect mshrs_5.io.allocate.bits.size, _view__T_5.size connect mshrs_5.io.allocate.bits.param, _view__T_5.param connect mshrs_5.io.allocate.bits.opcode, _view__T_5.opcode connect mshrs_5.io.allocate.bits.control, _view__T_5.control connect mshrs_5.io.allocate.bits.prio[0], _view__T_5.prio[0] connect mshrs_5.io.allocate.bits.prio[1], _view__T_5.prio[1] connect mshrs_5.io.allocate.bits.prio[2], _view__T_5.prio[2] connect mshrs_5.io.allocate.bits.set, mshrs_5.io.status.bits.set node _mshrs_5_io_allocate_bits_repeat_T = eq(mshrs_5.io.allocate.bits.tag, mshrs_5.io.status.bits.tag) connect mshrs_5.io.allocate.bits.repeat, _mshrs_5_io_allocate_bits_repeat_T node _mshrs_5_io_allocate_valid_T = and(sel_5, will_reload_6) connect mshrs_5.io.allocate.valid, _mshrs_5_io_allocate_valid_T node sel_6 = bits(mshr_selectOH, 6, 6) connect mshrs_6.io.schedule.ready, sel_6 node a_pop_7 = bits(requests.io.valid, 6, 6) node b_pop_7 = bits(requests.io.valid, 18, 18) node c_pop_7 = bits(requests.io.valid, 30, 30) node _bypassMatches_T_57 = bits(lowerMatches1, 6, 6) node _bypassMatches_T_58 = or(c_pop_7, request.bits.prio[2]) node _bypassMatches_T_59 = eq(c_pop_7, UInt<1>(0h0)) node _bypassMatches_T_60 = or(b_pop_7, request.bits.prio[1]) node _bypassMatches_T_61 = eq(b_pop_7, UInt<1>(0h0)) node _bypassMatches_T_62 = eq(a_pop_7, UInt<1>(0h0)) node _bypassMatches_T_63 = mux(_bypassMatches_T_60, _bypassMatches_T_61, _bypassMatches_T_62) node _bypassMatches_T_64 = mux(_bypassMatches_T_58, _bypassMatches_T_59, _bypassMatches_T_63) node bypassMatches_7 = and(_bypassMatches_T_57, _bypassMatches_T_64) node _may_pop_T_7 = or(a_pop_7, b_pop_7) node may_pop_7 = or(_may_pop_T_7, c_pop_7) node _bypass_T_7 = and(request.valid, queue) node bypass_7 = and(_bypass_T_7, bypassMatches_7) node _will_reload_T_7 = or(may_pop_7, bypass_7) node will_reload_7 = and(mshrs_6.io.schedule.bits.reload, _will_reload_T_7) wire _view__WIRE_6 : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>} connect _view__WIRE_6.put, request.bits.put connect _view__WIRE_6.offset, request.bits.offset connect _view__WIRE_6.tag, request.bits.tag connect _view__WIRE_6.source, request.bits.source connect _view__WIRE_6.size, request.bits.size connect _view__WIRE_6.param, request.bits.param connect _view__WIRE_6.opcode, request.bits.opcode connect _view__WIRE_6.control, request.bits.control connect _view__WIRE_6.prio, request.bits.prio node _view__T_6 = mux(bypass_7, _view__WIRE_6, requests.io.data) connect mshrs_6.io.allocate.bits.put, _view__T_6.put connect mshrs_6.io.allocate.bits.offset, _view__T_6.offset connect mshrs_6.io.allocate.bits.tag, _view__T_6.tag connect mshrs_6.io.allocate.bits.source, _view__T_6.source connect mshrs_6.io.allocate.bits.size, _view__T_6.size connect mshrs_6.io.allocate.bits.param, _view__T_6.param connect mshrs_6.io.allocate.bits.opcode, _view__T_6.opcode connect mshrs_6.io.allocate.bits.control, _view__T_6.control connect mshrs_6.io.allocate.bits.prio[0], _view__T_6.prio[0] connect mshrs_6.io.allocate.bits.prio[1], _view__T_6.prio[1] connect mshrs_6.io.allocate.bits.prio[2], _view__T_6.prio[2] connect mshrs_6.io.allocate.bits.set, mshrs_6.io.status.bits.set node _mshrs_6_io_allocate_bits_repeat_T = eq(mshrs_6.io.allocate.bits.tag, mshrs_6.io.status.bits.tag) connect mshrs_6.io.allocate.bits.repeat, _mshrs_6_io_allocate_bits_repeat_T node _mshrs_6_io_allocate_valid_T = and(sel_6, will_reload_7) connect mshrs_6.io.allocate.valid, _mshrs_6_io_allocate_valid_T node sel_7 = bits(mshr_selectOH, 7, 7) connect mshrs_7.io.schedule.ready, sel_7 node a_pop_8 = bits(requests.io.valid, 7, 7) node b_pop_8 = bits(requests.io.valid, 19, 19) node c_pop_8 = bits(requests.io.valid, 31, 31) node _bypassMatches_T_65 = bits(lowerMatches1, 7, 7) node _bypassMatches_T_66 = or(c_pop_8, request.bits.prio[2]) node _bypassMatches_T_67 = eq(c_pop_8, UInt<1>(0h0)) node _bypassMatches_T_68 = or(b_pop_8, request.bits.prio[1]) node _bypassMatches_T_69 = eq(b_pop_8, UInt<1>(0h0)) node _bypassMatches_T_70 = eq(a_pop_8, UInt<1>(0h0)) node _bypassMatches_T_71 = mux(_bypassMatches_T_68, _bypassMatches_T_69, _bypassMatches_T_70) node _bypassMatches_T_72 = mux(_bypassMatches_T_66, _bypassMatches_T_67, _bypassMatches_T_71) node bypassMatches_8 = and(_bypassMatches_T_65, _bypassMatches_T_72) node _may_pop_T_8 = or(a_pop_8, b_pop_8) node may_pop_8 = or(_may_pop_T_8, c_pop_8) node _bypass_T_8 = and(request.valid, queue) node bypass_8 = and(_bypass_T_8, bypassMatches_8) node _will_reload_T_8 = or(may_pop_8, bypass_8) node will_reload_8 = and(mshrs_7.io.schedule.bits.reload, _will_reload_T_8) wire _view__WIRE_7 : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>} connect _view__WIRE_7.put, request.bits.put connect _view__WIRE_7.offset, request.bits.offset connect _view__WIRE_7.tag, request.bits.tag connect _view__WIRE_7.source, request.bits.source connect _view__WIRE_7.size, request.bits.size connect _view__WIRE_7.param, request.bits.param connect _view__WIRE_7.opcode, request.bits.opcode connect _view__WIRE_7.control, request.bits.control connect _view__WIRE_7.prio, request.bits.prio node _view__T_7 = mux(bypass_8, _view__WIRE_7, requests.io.data) connect mshrs_7.io.allocate.bits.put, _view__T_7.put connect mshrs_7.io.allocate.bits.offset, _view__T_7.offset connect mshrs_7.io.allocate.bits.tag, _view__T_7.tag connect mshrs_7.io.allocate.bits.source, _view__T_7.source connect mshrs_7.io.allocate.bits.size, _view__T_7.size connect mshrs_7.io.allocate.bits.param, _view__T_7.param connect mshrs_7.io.allocate.bits.opcode, _view__T_7.opcode connect mshrs_7.io.allocate.bits.control, _view__T_7.control connect mshrs_7.io.allocate.bits.prio[0], _view__T_7.prio[0] connect mshrs_7.io.allocate.bits.prio[1], _view__T_7.prio[1] connect mshrs_7.io.allocate.bits.prio[2], _view__T_7.prio[2] connect mshrs_7.io.allocate.bits.set, mshrs_7.io.status.bits.set node _mshrs_7_io_allocate_bits_repeat_T = eq(mshrs_7.io.allocate.bits.tag, mshrs_7.io.status.bits.tag) connect mshrs_7.io.allocate.bits.repeat, _mshrs_7_io_allocate_bits_repeat_T node _mshrs_7_io_allocate_valid_T = and(sel_7, will_reload_8) connect mshrs_7.io.allocate.valid, _mshrs_7_io_allocate_valid_T node sel_8 = bits(mshr_selectOH, 8, 8) connect mshrs_8.io.schedule.ready, sel_8 node a_pop_9 = bits(requests.io.valid, 8, 8) node b_pop_9 = bits(requests.io.valid, 20, 20) node c_pop_9 = bits(requests.io.valid, 32, 32) node _bypassMatches_T_73 = bits(lowerMatches1, 8, 8) node _bypassMatches_T_74 = or(c_pop_9, request.bits.prio[2]) node _bypassMatches_T_75 = eq(c_pop_9, UInt<1>(0h0)) node _bypassMatches_T_76 = or(b_pop_9, request.bits.prio[1]) node _bypassMatches_T_77 = eq(b_pop_9, UInt<1>(0h0)) node _bypassMatches_T_78 = eq(a_pop_9, UInt<1>(0h0)) node _bypassMatches_T_79 = mux(_bypassMatches_T_76, _bypassMatches_T_77, _bypassMatches_T_78) node _bypassMatches_T_80 = mux(_bypassMatches_T_74, _bypassMatches_T_75, _bypassMatches_T_79) node bypassMatches_9 = and(_bypassMatches_T_73, _bypassMatches_T_80) node _may_pop_T_9 = or(a_pop_9, b_pop_9) node may_pop_9 = or(_may_pop_T_9, c_pop_9) node _bypass_T_9 = and(request.valid, queue) node bypass_9 = and(_bypass_T_9, bypassMatches_9) node _will_reload_T_9 = or(may_pop_9, bypass_9) node will_reload_9 = and(mshrs_8.io.schedule.bits.reload, _will_reload_T_9) wire _view__WIRE_8 : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>} connect _view__WIRE_8.put, request.bits.put connect _view__WIRE_8.offset, request.bits.offset connect _view__WIRE_8.tag, request.bits.tag connect _view__WIRE_8.source, request.bits.source connect _view__WIRE_8.size, request.bits.size connect _view__WIRE_8.param, request.bits.param connect _view__WIRE_8.opcode, request.bits.opcode connect _view__WIRE_8.control, request.bits.control connect _view__WIRE_8.prio, request.bits.prio node _view__T_8 = mux(bypass_9, _view__WIRE_8, requests.io.data) connect mshrs_8.io.allocate.bits.put, _view__T_8.put connect mshrs_8.io.allocate.bits.offset, _view__T_8.offset connect mshrs_8.io.allocate.bits.tag, _view__T_8.tag connect mshrs_8.io.allocate.bits.source, _view__T_8.source connect mshrs_8.io.allocate.bits.size, _view__T_8.size connect mshrs_8.io.allocate.bits.param, _view__T_8.param connect mshrs_8.io.allocate.bits.opcode, _view__T_8.opcode connect mshrs_8.io.allocate.bits.control, _view__T_8.control connect mshrs_8.io.allocate.bits.prio[0], _view__T_8.prio[0] connect mshrs_8.io.allocate.bits.prio[1], _view__T_8.prio[1] connect mshrs_8.io.allocate.bits.prio[2], _view__T_8.prio[2] connect mshrs_8.io.allocate.bits.set, mshrs_8.io.status.bits.set node _mshrs_8_io_allocate_bits_repeat_T = eq(mshrs_8.io.allocate.bits.tag, mshrs_8.io.status.bits.tag) connect mshrs_8.io.allocate.bits.repeat, _mshrs_8_io_allocate_bits_repeat_T node _mshrs_8_io_allocate_valid_T = and(sel_8, will_reload_9) connect mshrs_8.io.allocate.valid, _mshrs_8_io_allocate_valid_T node sel_9 = bits(mshr_selectOH, 9, 9) connect mshrs_9.io.schedule.ready, sel_9 node a_pop_10 = bits(requests.io.valid, 9, 9) node b_pop_10 = bits(requests.io.valid, 21, 21) node c_pop_10 = bits(requests.io.valid, 33, 33) node _bypassMatches_T_81 = bits(lowerMatches1, 9, 9) node _bypassMatches_T_82 = or(c_pop_10, request.bits.prio[2]) node _bypassMatches_T_83 = eq(c_pop_10, UInt<1>(0h0)) node _bypassMatches_T_84 = or(b_pop_10, request.bits.prio[1]) node _bypassMatches_T_85 = eq(b_pop_10, UInt<1>(0h0)) node _bypassMatches_T_86 = eq(a_pop_10, UInt<1>(0h0)) node _bypassMatches_T_87 = mux(_bypassMatches_T_84, _bypassMatches_T_85, _bypassMatches_T_86) node _bypassMatches_T_88 = mux(_bypassMatches_T_82, _bypassMatches_T_83, _bypassMatches_T_87) node bypassMatches_10 = and(_bypassMatches_T_81, _bypassMatches_T_88) node _may_pop_T_10 = or(a_pop_10, b_pop_10) node may_pop_10 = or(_may_pop_T_10, c_pop_10) node _bypass_T_10 = and(request.valid, queue) node bypass_10 = and(_bypass_T_10, bypassMatches_10) node _will_reload_T_10 = or(may_pop_10, bypass_10) node will_reload_10 = and(mshrs_9.io.schedule.bits.reload, _will_reload_T_10) wire _view__WIRE_9 : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>} connect _view__WIRE_9.put, request.bits.put connect _view__WIRE_9.offset, request.bits.offset connect _view__WIRE_9.tag, request.bits.tag connect _view__WIRE_9.source, request.bits.source connect _view__WIRE_9.size, request.bits.size connect _view__WIRE_9.param, request.bits.param connect _view__WIRE_9.opcode, request.bits.opcode connect _view__WIRE_9.control, request.bits.control connect _view__WIRE_9.prio, request.bits.prio node _view__T_9 = mux(bypass_10, _view__WIRE_9, requests.io.data) connect mshrs_9.io.allocate.bits.put, _view__T_9.put connect mshrs_9.io.allocate.bits.offset, _view__T_9.offset connect mshrs_9.io.allocate.bits.tag, _view__T_9.tag connect mshrs_9.io.allocate.bits.source, _view__T_9.source connect mshrs_9.io.allocate.bits.size, _view__T_9.size connect mshrs_9.io.allocate.bits.param, _view__T_9.param connect mshrs_9.io.allocate.bits.opcode, _view__T_9.opcode connect mshrs_9.io.allocate.bits.control, _view__T_9.control connect mshrs_9.io.allocate.bits.prio[0], _view__T_9.prio[0] connect mshrs_9.io.allocate.bits.prio[1], _view__T_9.prio[1] connect mshrs_9.io.allocate.bits.prio[2], _view__T_9.prio[2] connect mshrs_9.io.allocate.bits.set, mshrs_9.io.status.bits.set node _mshrs_9_io_allocate_bits_repeat_T = eq(mshrs_9.io.allocate.bits.tag, mshrs_9.io.status.bits.tag) connect mshrs_9.io.allocate.bits.repeat, _mshrs_9_io_allocate_bits_repeat_T node _mshrs_9_io_allocate_valid_T = and(sel_9, will_reload_10) connect mshrs_9.io.allocate.valid, _mshrs_9_io_allocate_valid_T node sel_10 = bits(mshr_selectOH, 10, 10) connect mshrs_10.io.schedule.ready, sel_10 node a_pop_11 = bits(requests.io.valid, 10, 10) node b_pop_11 = bits(requests.io.valid, 22, 22) node c_pop_11 = bits(requests.io.valid, 34, 34) node _bypassMatches_T_89 = bits(lowerMatches1, 10, 10) node _bypassMatches_T_90 = or(c_pop_11, request.bits.prio[2]) node _bypassMatches_T_91 = eq(c_pop_11, UInt<1>(0h0)) node _bypassMatches_T_92 = or(b_pop_11, request.bits.prio[1]) node _bypassMatches_T_93 = eq(b_pop_11, UInt<1>(0h0)) node _bypassMatches_T_94 = eq(a_pop_11, UInt<1>(0h0)) node _bypassMatches_T_95 = mux(_bypassMatches_T_92, _bypassMatches_T_93, _bypassMatches_T_94) node _bypassMatches_T_96 = mux(_bypassMatches_T_90, _bypassMatches_T_91, _bypassMatches_T_95) node bypassMatches_11 = and(_bypassMatches_T_89, _bypassMatches_T_96) node _may_pop_T_11 = or(a_pop_11, b_pop_11) node may_pop_11 = or(_may_pop_T_11, c_pop_11) node _bypass_T_11 = and(request.valid, queue) node bypass_11 = and(_bypass_T_11, bypassMatches_11) node _will_reload_T_11 = or(may_pop_11, bypass_11) node will_reload_11 = and(mshrs_10.io.schedule.bits.reload, _will_reload_T_11) wire _view__WIRE_10 : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>} connect _view__WIRE_10.put, request.bits.put connect _view__WIRE_10.offset, request.bits.offset connect _view__WIRE_10.tag, request.bits.tag connect _view__WIRE_10.source, request.bits.source connect _view__WIRE_10.size, request.bits.size connect _view__WIRE_10.param, request.bits.param connect _view__WIRE_10.opcode, request.bits.opcode connect _view__WIRE_10.control, request.bits.control connect _view__WIRE_10.prio, request.bits.prio node _view__T_10 = mux(bypass_11, _view__WIRE_10, requests.io.data) connect mshrs_10.io.allocate.bits.put, _view__T_10.put connect mshrs_10.io.allocate.bits.offset, _view__T_10.offset connect mshrs_10.io.allocate.bits.tag, _view__T_10.tag connect mshrs_10.io.allocate.bits.source, _view__T_10.source connect mshrs_10.io.allocate.bits.size, _view__T_10.size connect mshrs_10.io.allocate.bits.param, _view__T_10.param connect mshrs_10.io.allocate.bits.opcode, _view__T_10.opcode connect mshrs_10.io.allocate.bits.control, _view__T_10.control connect mshrs_10.io.allocate.bits.prio[0], _view__T_10.prio[0] connect mshrs_10.io.allocate.bits.prio[1], _view__T_10.prio[1] connect mshrs_10.io.allocate.bits.prio[2], _view__T_10.prio[2] connect mshrs_10.io.allocate.bits.set, mshrs_10.io.status.bits.set node _mshrs_10_io_allocate_bits_repeat_T = eq(mshrs_10.io.allocate.bits.tag, mshrs_10.io.status.bits.tag) connect mshrs_10.io.allocate.bits.repeat, _mshrs_10_io_allocate_bits_repeat_T node _mshrs_10_io_allocate_valid_T = and(sel_10, will_reload_11) connect mshrs_10.io.allocate.valid, _mshrs_10_io_allocate_valid_T node sel_11 = bits(mshr_selectOH, 11, 11) connect mshrs_11.io.schedule.ready, sel_11 node a_pop_12 = bits(requests.io.valid, 11, 11) node b_pop_12 = bits(requests.io.valid, 23, 23) node c_pop_12 = bits(requests.io.valid, 35, 35) node _bypassMatches_T_97 = bits(lowerMatches1, 11, 11) node _bypassMatches_T_98 = or(c_pop_12, request.bits.prio[2]) node _bypassMatches_T_99 = eq(c_pop_12, UInt<1>(0h0)) node _bypassMatches_T_100 = or(b_pop_12, request.bits.prio[1]) node _bypassMatches_T_101 = eq(b_pop_12, UInt<1>(0h0)) node _bypassMatches_T_102 = eq(a_pop_12, UInt<1>(0h0)) node _bypassMatches_T_103 = mux(_bypassMatches_T_100, _bypassMatches_T_101, _bypassMatches_T_102) node _bypassMatches_T_104 = mux(_bypassMatches_T_98, _bypassMatches_T_99, _bypassMatches_T_103) node bypassMatches_12 = and(_bypassMatches_T_97, _bypassMatches_T_104) node _may_pop_T_12 = or(a_pop_12, b_pop_12) node may_pop_12 = or(_may_pop_T_12, c_pop_12) node _bypass_T_12 = and(request.valid, queue) node bypass_12 = and(_bypass_T_12, bypassMatches_12) node _will_reload_T_12 = or(may_pop_12, bypass_12) node will_reload_12 = and(mshrs_11.io.schedule.bits.reload, _will_reload_T_12) wire _view__WIRE_11 : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>} connect _view__WIRE_11.put, request.bits.put connect _view__WIRE_11.offset, request.bits.offset connect _view__WIRE_11.tag, request.bits.tag connect _view__WIRE_11.source, request.bits.source connect _view__WIRE_11.size, request.bits.size connect _view__WIRE_11.param, request.bits.param connect _view__WIRE_11.opcode, request.bits.opcode connect _view__WIRE_11.control, request.bits.control connect _view__WIRE_11.prio, request.bits.prio node _view__T_11 = mux(bypass_12, _view__WIRE_11, requests.io.data) connect mshrs_11.io.allocate.bits.put, _view__T_11.put connect mshrs_11.io.allocate.bits.offset, _view__T_11.offset connect mshrs_11.io.allocate.bits.tag, _view__T_11.tag connect mshrs_11.io.allocate.bits.source, _view__T_11.source connect mshrs_11.io.allocate.bits.size, _view__T_11.size connect mshrs_11.io.allocate.bits.param, _view__T_11.param connect mshrs_11.io.allocate.bits.opcode, _view__T_11.opcode connect mshrs_11.io.allocate.bits.control, _view__T_11.control connect mshrs_11.io.allocate.bits.prio[0], _view__T_11.prio[0] connect mshrs_11.io.allocate.bits.prio[1], _view__T_11.prio[1] connect mshrs_11.io.allocate.bits.prio[2], _view__T_11.prio[2] connect mshrs_11.io.allocate.bits.set, mshrs_11.io.status.bits.set node _mshrs_11_io_allocate_bits_repeat_T = eq(mshrs_11.io.allocate.bits.tag, mshrs_11.io.status.bits.tag) connect mshrs_11.io.allocate.bits.repeat, _mshrs_11_io_allocate_bits_repeat_T node _mshrs_11_io_allocate_valid_T = and(sel_11, will_reload_12) connect mshrs_11.io.allocate.valid, _mshrs_11_io_allocate_valid_T node _prio_requests_T = not(requests.io.valid) node _prio_requests_T_1 = shr(requests.io.valid, 12) node _prio_requests_T_2 = or(_prio_requests_T, _prio_requests_T_1) node _prio_requests_T_3 = shr(requests.io.valid, 24) node _prio_requests_T_4 = or(_prio_requests_T_2, _prio_requests_T_3) node prio_requests = not(_prio_requests_T_4) node pop_index_hi = cat(mshr_selectOH, mshr_selectOH) node _pop_index_T = cat(pop_index_hi, mshr_selectOH) node _pop_index_T_1 = and(_pop_index_T, prio_requests) node pop_index_hi_1 = bits(_pop_index_T_1, 35, 32) node pop_index_lo = bits(_pop_index_T_1, 31, 0) node _pop_index_T_2 = orr(pop_index_hi_1) node _pop_index_T_3 = or(pop_index_hi_1, pop_index_lo) node pop_index_hi_2 = bits(_pop_index_T_3, 31, 16) node pop_index_lo_1 = bits(_pop_index_T_3, 15, 0) node _pop_index_T_4 = orr(pop_index_hi_2) node _pop_index_T_5 = or(pop_index_hi_2, pop_index_lo_1) node pop_index_hi_3 = bits(_pop_index_T_5, 15, 8) node pop_index_lo_2 = bits(_pop_index_T_5, 7, 0) node _pop_index_T_6 = orr(pop_index_hi_3) node _pop_index_T_7 = or(pop_index_hi_3, pop_index_lo_2) node pop_index_hi_4 = bits(_pop_index_T_7, 7, 4) node pop_index_lo_3 = bits(_pop_index_T_7, 3, 0) node _pop_index_T_8 = orr(pop_index_hi_4) node _pop_index_T_9 = or(pop_index_hi_4, pop_index_lo_3) node pop_index_hi_5 = bits(_pop_index_T_9, 3, 2) node pop_index_lo_4 = bits(_pop_index_T_9, 1, 0) node _pop_index_T_10 = orr(pop_index_hi_5) node _pop_index_T_11 = or(pop_index_hi_5, pop_index_lo_4) node _pop_index_T_12 = bits(_pop_index_T_11, 1, 1) node _pop_index_T_13 = cat(_pop_index_T_10, _pop_index_T_12) node _pop_index_T_14 = cat(_pop_index_T_8, _pop_index_T_13) node _pop_index_T_15 = cat(_pop_index_T_6, _pop_index_T_14) node _pop_index_T_16 = cat(_pop_index_T_4, _pop_index_T_15) node pop_index = cat(_pop_index_T_2, _pop_index_T_16) connect requests.io.pop.valid, will_pop connect requests.io.pop.bits, pop_index node lb_tag_mismatch = neq(scheduleTag, requests.io.data.tag) node _mshr_uses_directory_assuming_no_bypass_T = and(schedule.reload, may_pop) node mshr_uses_directory_assuming_no_bypass = and(_mshr_uses_directory_assuming_no_bypass_T, lb_tag_mismatch) node mshr_uses_directory_for_lb = and(will_pop, lb_tag_mismatch) node _mshr_uses_directory_T = mux(bypass, request.bits.tag, requests.io.data.tag) node _mshr_uses_directory_T_1 = neq(scheduleTag, _mshr_uses_directory_T) node mshr_uses_directory = and(will_reload, _mshr_uses_directory_T_1) node mshr_validOH_lo_lo_hi = cat(mshrs_2.io.status.valid, mshrs_1.io.status.valid) node mshr_validOH_lo_lo = cat(mshr_validOH_lo_lo_hi, mshrs_0.io.status.valid) node mshr_validOH_lo_hi_hi = cat(mshrs_5.io.status.valid, mshrs_4.io.status.valid) node mshr_validOH_lo_hi = cat(mshr_validOH_lo_hi_hi, mshrs_3.io.status.valid) node mshr_validOH_lo = cat(mshr_validOH_lo_hi, mshr_validOH_lo_lo) node mshr_validOH_hi_lo_hi = cat(mshrs_8.io.status.valid, mshrs_7.io.status.valid) node mshr_validOH_hi_lo = cat(mshr_validOH_hi_lo_hi, mshrs_6.io.status.valid) node mshr_validOH_hi_hi_hi = cat(mshrs_11.io.status.valid, mshrs_10.io.status.valid) node mshr_validOH_hi_hi = cat(mshr_validOH_hi_hi_hi, mshrs_9.io.status.valid) node mshr_validOH_hi = cat(mshr_validOH_hi_hi, mshr_validOH_hi_lo) node mshr_validOH = cat(mshr_validOH_hi, mshr_validOH_lo) node _mshr_free_T = not(mshr_validOH) node _mshr_free_T_1 = and(_mshr_free_T, prioFilter) node mshr_free = orr(_mshr_free_T_1) node bypassQueue = and(schedule.reload, bypassMatches) node _request_alloc_cases_T = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0)) node _request_alloc_cases_T_1 = and(alloc, _request_alloc_cases_T) node _request_alloc_cases_T_2 = and(_request_alloc_cases_T_1, mshr_free) node _request_alloc_cases_T_3 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0)) node _request_alloc_cases_T_4 = and(nestB, _request_alloc_cases_T_3) node _request_alloc_cases_T_5 = eq(mshrs_10.io.status.valid, UInt<1>(0h0)) node _request_alloc_cases_T_6 = and(_request_alloc_cases_T_4, _request_alloc_cases_T_5) node _request_alloc_cases_T_7 = eq(mshrs_11.io.status.valid, UInt<1>(0h0)) node _request_alloc_cases_T_8 = and(_request_alloc_cases_T_6, _request_alloc_cases_T_7) node _request_alloc_cases_T_9 = or(_request_alloc_cases_T_2, _request_alloc_cases_T_8) node _request_alloc_cases_T_10 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0)) node _request_alloc_cases_T_11 = and(nestC, _request_alloc_cases_T_10) node _request_alloc_cases_T_12 = eq(mshrs_11.io.status.valid, UInt<1>(0h0)) node _request_alloc_cases_T_13 = and(_request_alloc_cases_T_11, _request_alloc_cases_T_12) node request_alloc_cases = or(_request_alloc_cases_T_9, _request_alloc_cases_T_13) node _request_ready_T = or(bypassQueue, requests.io.push.ready) node _request_ready_T_1 = and(queue, _request_ready_T) node _request_ready_T_2 = or(request_alloc_cases, _request_ready_T_1) connect request.ready, _request_ready_T_2 node alloc_uses_directory = and(request.valid, request_alloc_cases) node _directory_io_read_valid_T = or(mshr_uses_directory, alloc_uses_directory) connect directory.io.read.valid, _directory_io_read_valid_T node _directory_io_read_bits_set_T = mux(mshr_uses_directory_for_lb, scheduleSet, request.bits.set) connect directory.io.read.bits.set, _directory_io_read_bits_set_T node _directory_io_read_bits_tag_T = mux(mshr_uses_directory_for_lb, requests.io.data.tag, request.bits.tag) connect directory.io.read.bits.tag, _directory_io_read_bits_tag_T node _requests_io_push_valid_T = and(request.valid, queue) node _requests_io_push_valid_T_1 = eq(bypassQueue, UInt<1>(0h0)) node _requests_io_push_valid_T_2 = and(_requests_io_push_valid_T, _requests_io_push_valid_T_1) connect requests.io.push.valid, _requests_io_push_valid_T_2 connect requests.io.push.bits.data.put, request.bits.put connect requests.io.push.bits.data.offset, request.bits.offset connect requests.io.push.bits.data.tag, request.bits.tag connect requests.io.push.bits.data.source, request.bits.source connect requests.io.push.bits.data.size, request.bits.size connect requests.io.push.bits.data.param, request.bits.param connect requests.io.push.bits.data.opcode, request.bits.opcode connect requests.io.push.bits.data.control, request.bits.control connect requests.io.push.bits.data.prio[0], request.bits.prio[0] connect requests.io.push.bits.data.prio[1], request.bits.prio[1] connect requests.io.push.bits.data.prio[2], request.bits.prio[2] node _requests_io_push_bits_index_T = shl(lowerMatches1, 0) node requests_io_push_bits_index_hi = bits(_requests_io_push_bits_index_T, 11, 8) node requests_io_push_bits_index_lo = bits(_requests_io_push_bits_index_T, 7, 0) node _requests_io_push_bits_index_T_1 = orr(requests_io_push_bits_index_hi) node _requests_io_push_bits_index_T_2 = or(requests_io_push_bits_index_hi, requests_io_push_bits_index_lo) node requests_io_push_bits_index_hi_1 = bits(_requests_io_push_bits_index_T_2, 7, 4) node requests_io_push_bits_index_lo_1 = bits(_requests_io_push_bits_index_T_2, 3, 0) node _requests_io_push_bits_index_T_3 = orr(requests_io_push_bits_index_hi_1) node _requests_io_push_bits_index_T_4 = or(requests_io_push_bits_index_hi_1, requests_io_push_bits_index_lo_1) node requests_io_push_bits_index_hi_2 = bits(_requests_io_push_bits_index_T_4, 3, 2) node requests_io_push_bits_index_lo_2 = bits(_requests_io_push_bits_index_T_4, 1, 0) node _requests_io_push_bits_index_T_5 = orr(requests_io_push_bits_index_hi_2) node _requests_io_push_bits_index_T_6 = or(requests_io_push_bits_index_hi_2, requests_io_push_bits_index_lo_2) node _requests_io_push_bits_index_T_7 = bits(_requests_io_push_bits_index_T_6, 1, 1) node _requests_io_push_bits_index_T_8 = cat(_requests_io_push_bits_index_T_5, _requests_io_push_bits_index_T_7) node _requests_io_push_bits_index_T_9 = cat(_requests_io_push_bits_index_T_3, _requests_io_push_bits_index_T_8) node _requests_io_push_bits_index_T_10 = cat(_requests_io_push_bits_index_T_1, _requests_io_push_bits_index_T_9) node _requests_io_push_bits_index_T_11 = shl(lowerMatches1, 12) node requests_io_push_bits_index_hi_3 = bits(_requests_io_push_bits_index_T_11, 23, 16) node requests_io_push_bits_index_lo_3 = bits(_requests_io_push_bits_index_T_11, 15, 0) node _requests_io_push_bits_index_T_12 = orr(requests_io_push_bits_index_hi_3) node _requests_io_push_bits_index_T_13 = or(requests_io_push_bits_index_hi_3, requests_io_push_bits_index_lo_3) node requests_io_push_bits_index_hi_4 = bits(_requests_io_push_bits_index_T_13, 15, 8) node requests_io_push_bits_index_lo_4 = bits(_requests_io_push_bits_index_T_13, 7, 0) node _requests_io_push_bits_index_T_14 = orr(requests_io_push_bits_index_hi_4) node _requests_io_push_bits_index_T_15 = or(requests_io_push_bits_index_hi_4, requests_io_push_bits_index_lo_4) node requests_io_push_bits_index_hi_5 = bits(_requests_io_push_bits_index_T_15, 7, 4) node requests_io_push_bits_index_lo_5 = bits(_requests_io_push_bits_index_T_15, 3, 0) node _requests_io_push_bits_index_T_16 = orr(requests_io_push_bits_index_hi_5) node _requests_io_push_bits_index_T_17 = or(requests_io_push_bits_index_hi_5, requests_io_push_bits_index_lo_5) node requests_io_push_bits_index_hi_6 = bits(_requests_io_push_bits_index_T_17, 3, 2) node requests_io_push_bits_index_lo_6 = bits(_requests_io_push_bits_index_T_17, 1, 0) node _requests_io_push_bits_index_T_18 = orr(requests_io_push_bits_index_hi_6) node _requests_io_push_bits_index_T_19 = or(requests_io_push_bits_index_hi_6, requests_io_push_bits_index_lo_6) node _requests_io_push_bits_index_T_20 = bits(_requests_io_push_bits_index_T_19, 1, 1) node _requests_io_push_bits_index_T_21 = cat(_requests_io_push_bits_index_T_18, _requests_io_push_bits_index_T_20) node _requests_io_push_bits_index_T_22 = cat(_requests_io_push_bits_index_T_16, _requests_io_push_bits_index_T_21) node _requests_io_push_bits_index_T_23 = cat(_requests_io_push_bits_index_T_14, _requests_io_push_bits_index_T_22) node _requests_io_push_bits_index_T_24 = cat(_requests_io_push_bits_index_T_12, _requests_io_push_bits_index_T_23) node _requests_io_push_bits_index_T_25 = shl(lowerMatches1, 24) node requests_io_push_bits_index_hi_7 = bits(_requests_io_push_bits_index_T_25, 35, 32) node requests_io_push_bits_index_lo_7 = bits(_requests_io_push_bits_index_T_25, 31, 0) node _requests_io_push_bits_index_T_26 = orr(requests_io_push_bits_index_hi_7) node _requests_io_push_bits_index_T_27 = or(requests_io_push_bits_index_hi_7, requests_io_push_bits_index_lo_7) node requests_io_push_bits_index_hi_8 = bits(_requests_io_push_bits_index_T_27, 31, 16) node requests_io_push_bits_index_lo_8 = bits(_requests_io_push_bits_index_T_27, 15, 0) node _requests_io_push_bits_index_T_28 = orr(requests_io_push_bits_index_hi_8) node _requests_io_push_bits_index_T_29 = or(requests_io_push_bits_index_hi_8, requests_io_push_bits_index_lo_8) node requests_io_push_bits_index_hi_9 = bits(_requests_io_push_bits_index_T_29, 15, 8) node requests_io_push_bits_index_lo_9 = bits(_requests_io_push_bits_index_T_29, 7, 0) node _requests_io_push_bits_index_T_30 = orr(requests_io_push_bits_index_hi_9) node _requests_io_push_bits_index_T_31 = or(requests_io_push_bits_index_hi_9, requests_io_push_bits_index_lo_9) node requests_io_push_bits_index_hi_10 = bits(_requests_io_push_bits_index_T_31, 7, 4) node requests_io_push_bits_index_lo_10 = bits(_requests_io_push_bits_index_T_31, 3, 0) node _requests_io_push_bits_index_T_32 = orr(requests_io_push_bits_index_hi_10) node _requests_io_push_bits_index_T_33 = or(requests_io_push_bits_index_hi_10, requests_io_push_bits_index_lo_10) node requests_io_push_bits_index_hi_11 = bits(_requests_io_push_bits_index_T_33, 3, 2) node requests_io_push_bits_index_lo_11 = bits(_requests_io_push_bits_index_T_33, 1, 0) node _requests_io_push_bits_index_T_34 = orr(requests_io_push_bits_index_hi_11) node _requests_io_push_bits_index_T_35 = or(requests_io_push_bits_index_hi_11, requests_io_push_bits_index_lo_11) node _requests_io_push_bits_index_T_36 = bits(_requests_io_push_bits_index_T_35, 1, 1) node _requests_io_push_bits_index_T_37 = cat(_requests_io_push_bits_index_T_34, _requests_io_push_bits_index_T_36) node _requests_io_push_bits_index_T_38 = cat(_requests_io_push_bits_index_T_32, _requests_io_push_bits_index_T_37) node _requests_io_push_bits_index_T_39 = cat(_requests_io_push_bits_index_T_30, _requests_io_push_bits_index_T_38) node _requests_io_push_bits_index_T_40 = cat(_requests_io_push_bits_index_T_28, _requests_io_push_bits_index_T_39) node _requests_io_push_bits_index_T_41 = cat(_requests_io_push_bits_index_T_26, _requests_io_push_bits_index_T_40) node _requests_io_push_bits_index_T_42 = mux(request.bits.prio[0], _requests_io_push_bits_index_T_10, UInt<1>(0h0)) node _requests_io_push_bits_index_T_43 = mux(request.bits.prio[1], _requests_io_push_bits_index_T_24, UInt<1>(0h0)) node _requests_io_push_bits_index_T_44 = mux(request.bits.prio[2], _requests_io_push_bits_index_T_41, UInt<1>(0h0)) node _requests_io_push_bits_index_T_45 = or(_requests_io_push_bits_index_T_42, _requests_io_push_bits_index_T_43) node _requests_io_push_bits_index_T_46 = or(_requests_io_push_bits_index_T_45, _requests_io_push_bits_index_T_44) wire _requests_io_push_bits_index_WIRE : UInt<6> connect _requests_io_push_bits_index_WIRE, _requests_io_push_bits_index_T_46 connect requests.io.push.bits.index, _requests_io_push_bits_index_WIRE node _mshr_insertOH_T = not(mshr_validOH) node _mshr_insertOH_T_1 = shl(_mshr_insertOH_T, 1) node _mshr_insertOH_T_2 = bits(_mshr_insertOH_T_1, 11, 0) node _mshr_insertOH_T_3 = or(_mshr_insertOH_T, _mshr_insertOH_T_2) node _mshr_insertOH_T_4 = shl(_mshr_insertOH_T_3, 2) node _mshr_insertOH_T_5 = bits(_mshr_insertOH_T_4, 11, 0) node _mshr_insertOH_T_6 = or(_mshr_insertOH_T_3, _mshr_insertOH_T_5) node _mshr_insertOH_T_7 = shl(_mshr_insertOH_T_6, 4) node _mshr_insertOH_T_8 = bits(_mshr_insertOH_T_7, 11, 0) node _mshr_insertOH_T_9 = or(_mshr_insertOH_T_6, _mshr_insertOH_T_8) node _mshr_insertOH_T_10 = shl(_mshr_insertOH_T_9, 8) node _mshr_insertOH_T_11 = bits(_mshr_insertOH_T_10, 11, 0) node _mshr_insertOH_T_12 = or(_mshr_insertOH_T_9, _mshr_insertOH_T_11) node _mshr_insertOH_T_13 = bits(_mshr_insertOH_T_12, 11, 0) node _mshr_insertOH_T_14 = shl(_mshr_insertOH_T_13, 1) node _mshr_insertOH_T_15 = not(_mshr_insertOH_T_14) node _mshr_insertOH_T_16 = not(mshr_validOH) node _mshr_insertOH_T_17 = and(_mshr_insertOH_T_15, _mshr_insertOH_T_16) node mshr_insertOH = and(_mshr_insertOH_T_17, prioFilter) node _T_19 = bits(mshr_insertOH, 0, 0) node _T_20 = bits(mshr_insertOH, 1, 1) node _T_21 = bits(mshr_insertOH, 2, 2) node _T_22 = bits(mshr_insertOH, 3, 3) node _T_23 = bits(mshr_insertOH, 4, 4) node _T_24 = bits(mshr_insertOH, 5, 5) node _T_25 = bits(mshr_insertOH, 6, 6) node _T_26 = bits(mshr_insertOH, 7, 7) node _T_27 = bits(mshr_insertOH, 8, 8) node _T_28 = bits(mshr_insertOH, 9, 9) node _T_29 = bits(mshr_insertOH, 10, 10) node _T_30 = bits(mshr_insertOH, 11, 11) node _T_31 = bits(mshr_insertOH, 12, 12) node _T_32 = and(request.valid, alloc) node _T_33 = and(_T_32, _T_19) node _T_34 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0)) node _T_35 = and(_T_33, _T_34) when _T_35 : connect mshrs_0.io.allocate.valid, UInt<1>(0h1) connect mshrs_0.io.allocate.bits.set, request.bits.set connect mshrs_0.io.allocate.bits.put, request.bits.put connect mshrs_0.io.allocate.bits.offset, request.bits.offset connect mshrs_0.io.allocate.bits.tag, request.bits.tag connect mshrs_0.io.allocate.bits.source, request.bits.source connect mshrs_0.io.allocate.bits.size, request.bits.size connect mshrs_0.io.allocate.bits.param, request.bits.param connect mshrs_0.io.allocate.bits.opcode, request.bits.opcode connect mshrs_0.io.allocate.bits.control, request.bits.control connect mshrs_0.io.allocate.bits.prio[0], request.bits.prio[0] connect mshrs_0.io.allocate.bits.prio[1], request.bits.prio[1] connect mshrs_0.io.allocate.bits.prio[2], request.bits.prio[2] connect mshrs_0.io.allocate.bits.repeat, UInt<1>(0h0) node _T_36 = and(request.valid, alloc) node _T_37 = and(_T_36, _T_20) node _T_38 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0)) node _T_39 = and(_T_37, _T_38) when _T_39 : connect mshrs_1.io.allocate.valid, UInt<1>(0h1) connect mshrs_1.io.allocate.bits.set, request.bits.set connect mshrs_1.io.allocate.bits.put, request.bits.put connect mshrs_1.io.allocate.bits.offset, request.bits.offset connect mshrs_1.io.allocate.bits.tag, request.bits.tag connect mshrs_1.io.allocate.bits.source, request.bits.source connect mshrs_1.io.allocate.bits.size, request.bits.size connect mshrs_1.io.allocate.bits.param, request.bits.param connect mshrs_1.io.allocate.bits.opcode, request.bits.opcode connect mshrs_1.io.allocate.bits.control, request.bits.control connect mshrs_1.io.allocate.bits.prio[0], request.bits.prio[0] connect mshrs_1.io.allocate.bits.prio[1], request.bits.prio[1] connect mshrs_1.io.allocate.bits.prio[2], request.bits.prio[2] connect mshrs_1.io.allocate.bits.repeat, UInt<1>(0h0) node _T_40 = and(request.valid, alloc) node _T_41 = and(_T_40, _T_21) node _T_42 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0)) node _T_43 = and(_T_41, _T_42) when _T_43 : connect mshrs_2.io.allocate.valid, UInt<1>(0h1) connect mshrs_2.io.allocate.bits.set, request.bits.set connect mshrs_2.io.allocate.bits.put, request.bits.put connect mshrs_2.io.allocate.bits.offset, request.bits.offset connect mshrs_2.io.allocate.bits.tag, request.bits.tag connect mshrs_2.io.allocate.bits.source, request.bits.source connect mshrs_2.io.allocate.bits.size, request.bits.size connect mshrs_2.io.allocate.bits.param, request.bits.param connect mshrs_2.io.allocate.bits.opcode, request.bits.opcode connect mshrs_2.io.allocate.bits.control, request.bits.control connect mshrs_2.io.allocate.bits.prio[0], request.bits.prio[0] connect mshrs_2.io.allocate.bits.prio[1], request.bits.prio[1] connect mshrs_2.io.allocate.bits.prio[2], request.bits.prio[2] connect mshrs_2.io.allocate.bits.repeat, UInt<1>(0h0) node _T_44 = and(request.valid, alloc) node _T_45 = and(_T_44, _T_22) node _T_46 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0)) node _T_47 = and(_T_45, _T_46) when _T_47 : connect mshrs_3.io.allocate.valid, UInt<1>(0h1) connect mshrs_3.io.allocate.bits.set, request.bits.set connect mshrs_3.io.allocate.bits.put, request.bits.put connect mshrs_3.io.allocate.bits.offset, request.bits.offset connect mshrs_3.io.allocate.bits.tag, request.bits.tag connect mshrs_3.io.allocate.bits.source, request.bits.source connect mshrs_3.io.allocate.bits.size, request.bits.size connect mshrs_3.io.allocate.bits.param, request.bits.param connect mshrs_3.io.allocate.bits.opcode, request.bits.opcode connect mshrs_3.io.allocate.bits.control, request.bits.control connect mshrs_3.io.allocate.bits.prio[0], request.bits.prio[0] connect mshrs_3.io.allocate.bits.prio[1], request.bits.prio[1] connect mshrs_3.io.allocate.bits.prio[2], request.bits.prio[2] connect mshrs_3.io.allocate.bits.repeat, UInt<1>(0h0) node _T_48 = and(request.valid, alloc) node _T_49 = and(_T_48, _T_23) node _T_50 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0)) node _T_51 = and(_T_49, _T_50) when _T_51 : connect mshrs_4.io.allocate.valid, UInt<1>(0h1) connect mshrs_4.io.allocate.bits.set, request.bits.set connect mshrs_4.io.allocate.bits.put, request.bits.put connect mshrs_4.io.allocate.bits.offset, request.bits.offset connect mshrs_4.io.allocate.bits.tag, request.bits.tag connect mshrs_4.io.allocate.bits.source, request.bits.source connect mshrs_4.io.allocate.bits.size, request.bits.size connect mshrs_4.io.allocate.bits.param, request.bits.param connect mshrs_4.io.allocate.bits.opcode, request.bits.opcode connect mshrs_4.io.allocate.bits.control, request.bits.control connect mshrs_4.io.allocate.bits.prio[0], request.bits.prio[0] connect mshrs_4.io.allocate.bits.prio[1], request.bits.prio[1] connect mshrs_4.io.allocate.bits.prio[2], request.bits.prio[2] connect mshrs_4.io.allocate.bits.repeat, UInt<1>(0h0) node _T_52 = and(request.valid, alloc) node _T_53 = and(_T_52, _T_24) node _T_54 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0)) node _T_55 = and(_T_53, _T_54) when _T_55 : connect mshrs_5.io.allocate.valid, UInt<1>(0h1) connect mshrs_5.io.allocate.bits.set, request.bits.set connect mshrs_5.io.allocate.bits.put, request.bits.put connect mshrs_5.io.allocate.bits.offset, request.bits.offset connect mshrs_5.io.allocate.bits.tag, request.bits.tag connect mshrs_5.io.allocate.bits.source, request.bits.source connect mshrs_5.io.allocate.bits.size, request.bits.size connect mshrs_5.io.allocate.bits.param, request.bits.param connect mshrs_5.io.allocate.bits.opcode, request.bits.opcode connect mshrs_5.io.allocate.bits.control, request.bits.control connect mshrs_5.io.allocate.bits.prio[0], request.bits.prio[0] connect mshrs_5.io.allocate.bits.prio[1], request.bits.prio[1] connect mshrs_5.io.allocate.bits.prio[2], request.bits.prio[2] connect mshrs_5.io.allocate.bits.repeat, UInt<1>(0h0) node _T_56 = and(request.valid, alloc) node _T_57 = and(_T_56, _T_25) node _T_58 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0)) node _T_59 = and(_T_57, _T_58) when _T_59 : connect mshrs_6.io.allocate.valid, UInt<1>(0h1) connect mshrs_6.io.allocate.bits.set, request.bits.set connect mshrs_6.io.allocate.bits.put, request.bits.put connect mshrs_6.io.allocate.bits.offset, request.bits.offset connect mshrs_6.io.allocate.bits.tag, request.bits.tag connect mshrs_6.io.allocate.bits.source, request.bits.source connect mshrs_6.io.allocate.bits.size, request.bits.size connect mshrs_6.io.allocate.bits.param, request.bits.param connect mshrs_6.io.allocate.bits.opcode, request.bits.opcode connect mshrs_6.io.allocate.bits.control, request.bits.control connect mshrs_6.io.allocate.bits.prio[0], request.bits.prio[0] connect mshrs_6.io.allocate.bits.prio[1], request.bits.prio[1] connect mshrs_6.io.allocate.bits.prio[2], request.bits.prio[2] connect mshrs_6.io.allocate.bits.repeat, UInt<1>(0h0) node _T_60 = and(request.valid, alloc) node _T_61 = and(_T_60, _T_26) node _T_62 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0)) node _T_63 = and(_T_61, _T_62) when _T_63 : connect mshrs_7.io.allocate.valid, UInt<1>(0h1) connect mshrs_7.io.allocate.bits.set, request.bits.set connect mshrs_7.io.allocate.bits.put, request.bits.put connect mshrs_7.io.allocate.bits.offset, request.bits.offset connect mshrs_7.io.allocate.bits.tag, request.bits.tag connect mshrs_7.io.allocate.bits.source, request.bits.source connect mshrs_7.io.allocate.bits.size, request.bits.size connect mshrs_7.io.allocate.bits.param, request.bits.param connect mshrs_7.io.allocate.bits.opcode, request.bits.opcode connect mshrs_7.io.allocate.bits.control, request.bits.control connect mshrs_7.io.allocate.bits.prio[0], request.bits.prio[0] connect mshrs_7.io.allocate.bits.prio[1], request.bits.prio[1] connect mshrs_7.io.allocate.bits.prio[2], request.bits.prio[2] connect mshrs_7.io.allocate.bits.repeat, UInt<1>(0h0) node _T_64 = and(request.valid, alloc) node _T_65 = and(_T_64, _T_27) node _T_66 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0)) node _T_67 = and(_T_65, _T_66) when _T_67 : connect mshrs_8.io.allocate.valid, UInt<1>(0h1) connect mshrs_8.io.allocate.bits.set, request.bits.set connect mshrs_8.io.allocate.bits.put, request.bits.put connect mshrs_8.io.allocate.bits.offset, request.bits.offset connect mshrs_8.io.allocate.bits.tag, request.bits.tag connect mshrs_8.io.allocate.bits.source, request.bits.source connect mshrs_8.io.allocate.bits.size, request.bits.size connect mshrs_8.io.allocate.bits.param, request.bits.param connect mshrs_8.io.allocate.bits.opcode, request.bits.opcode connect mshrs_8.io.allocate.bits.control, request.bits.control connect mshrs_8.io.allocate.bits.prio[0], request.bits.prio[0] connect mshrs_8.io.allocate.bits.prio[1], request.bits.prio[1] connect mshrs_8.io.allocate.bits.prio[2], request.bits.prio[2] connect mshrs_8.io.allocate.bits.repeat, UInt<1>(0h0) node _T_68 = and(request.valid, alloc) node _T_69 = and(_T_68, _T_28) node _T_70 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0)) node _T_71 = and(_T_69, _T_70) when _T_71 : connect mshrs_9.io.allocate.valid, UInt<1>(0h1) connect mshrs_9.io.allocate.bits.set, request.bits.set connect mshrs_9.io.allocate.bits.put, request.bits.put connect mshrs_9.io.allocate.bits.offset, request.bits.offset connect mshrs_9.io.allocate.bits.tag, request.bits.tag connect mshrs_9.io.allocate.bits.source, request.bits.source connect mshrs_9.io.allocate.bits.size, request.bits.size connect mshrs_9.io.allocate.bits.param, request.bits.param connect mshrs_9.io.allocate.bits.opcode, request.bits.opcode connect mshrs_9.io.allocate.bits.control, request.bits.control connect mshrs_9.io.allocate.bits.prio[0], request.bits.prio[0] connect mshrs_9.io.allocate.bits.prio[1], request.bits.prio[1] connect mshrs_9.io.allocate.bits.prio[2], request.bits.prio[2] connect mshrs_9.io.allocate.bits.repeat, UInt<1>(0h0) node _T_72 = and(request.valid, alloc) node _T_73 = and(_T_72, _T_29) node _T_74 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0)) node _T_75 = and(_T_73, _T_74) when _T_75 : connect mshrs_10.io.allocate.valid, UInt<1>(0h1) connect mshrs_10.io.allocate.bits.set, request.bits.set connect mshrs_10.io.allocate.bits.put, request.bits.put connect mshrs_10.io.allocate.bits.offset, request.bits.offset connect mshrs_10.io.allocate.bits.tag, request.bits.tag connect mshrs_10.io.allocate.bits.source, request.bits.source connect mshrs_10.io.allocate.bits.size, request.bits.size connect mshrs_10.io.allocate.bits.param, request.bits.param connect mshrs_10.io.allocate.bits.opcode, request.bits.opcode connect mshrs_10.io.allocate.bits.control, request.bits.control connect mshrs_10.io.allocate.bits.prio[0], request.bits.prio[0] connect mshrs_10.io.allocate.bits.prio[1], request.bits.prio[1] connect mshrs_10.io.allocate.bits.prio[2], request.bits.prio[2] connect mshrs_10.io.allocate.bits.repeat, UInt<1>(0h0) node _T_76 = and(request.valid, alloc) node _T_77 = and(_T_76, _T_30) node _T_78 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0)) node _T_79 = and(_T_77, _T_78) when _T_79 : connect mshrs_11.io.allocate.valid, UInt<1>(0h1) connect mshrs_11.io.allocate.bits.set, request.bits.set connect mshrs_11.io.allocate.bits.put, request.bits.put connect mshrs_11.io.allocate.bits.offset, request.bits.offset connect mshrs_11.io.allocate.bits.tag, request.bits.tag connect mshrs_11.io.allocate.bits.source, request.bits.source connect mshrs_11.io.allocate.bits.size, request.bits.size connect mshrs_11.io.allocate.bits.param, request.bits.param connect mshrs_11.io.allocate.bits.opcode, request.bits.opcode connect mshrs_11.io.allocate.bits.control, request.bits.control connect mshrs_11.io.allocate.bits.prio[0], request.bits.prio[0] connect mshrs_11.io.allocate.bits.prio[1], request.bits.prio[1] connect mshrs_11.io.allocate.bits.prio[2], request.bits.prio[2] connect mshrs_11.io.allocate.bits.repeat, UInt<1>(0h0) node _T_80 = and(request.valid, nestB) node _T_81 = eq(mshrs_10.io.status.valid, UInt<1>(0h0)) node _T_82 = and(_T_80, _T_81) node _T_83 = eq(mshrs_11.io.status.valid, UInt<1>(0h0)) node _T_84 = and(_T_82, _T_83) node _T_85 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0)) node _T_86 = and(_T_84, _T_85) when _T_86 : connect mshrs_10.io.allocate.valid, UInt<1>(0h1) connect mshrs_10.io.allocate.bits.set, request.bits.set connect mshrs_10.io.allocate.bits.put, request.bits.put connect mshrs_10.io.allocate.bits.offset, request.bits.offset connect mshrs_10.io.allocate.bits.tag, request.bits.tag connect mshrs_10.io.allocate.bits.source, request.bits.source connect mshrs_10.io.allocate.bits.size, request.bits.size connect mshrs_10.io.allocate.bits.param, request.bits.param connect mshrs_10.io.allocate.bits.opcode, request.bits.opcode connect mshrs_10.io.allocate.bits.control, request.bits.control connect mshrs_10.io.allocate.bits.prio[0], request.bits.prio[0] connect mshrs_10.io.allocate.bits.prio[1], request.bits.prio[1] connect mshrs_10.io.allocate.bits.prio[2], request.bits.prio[2] connect mshrs_10.io.allocate.bits.repeat, UInt<1>(0h0) node _T_87 = eq(request.bits.prio[0], UInt<1>(0h0)) node _T_88 = asUInt(reset) node _T_89 = eq(_T_88, UInt<1>(0h0)) when _T_89 : node _T_90 = eq(_T_87, UInt<1>(0h0)) when _T_90 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Scheduler.scala:291 assert (!request.bits.prio(0))\n") : printf assert(clock, _T_87, UInt<1>(0h1), "") : assert connect mshrs_10.io.allocate.bits.prio[0], UInt<1>(0h0) node _T_91 = and(request.valid, nestC) node _T_92 = eq(mshrs_11.io.status.valid, UInt<1>(0h0)) node _T_93 = and(_T_91, _T_92) node _T_94 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0)) node _T_95 = and(_T_93, _T_94) when _T_95 : connect mshrs_11.io.allocate.valid, UInt<1>(0h1) connect mshrs_11.io.allocate.bits.set, request.bits.set connect mshrs_11.io.allocate.bits.put, request.bits.put connect mshrs_11.io.allocate.bits.offset, request.bits.offset connect mshrs_11.io.allocate.bits.tag, request.bits.tag connect mshrs_11.io.allocate.bits.source, request.bits.source connect mshrs_11.io.allocate.bits.size, request.bits.size connect mshrs_11.io.allocate.bits.param, request.bits.param connect mshrs_11.io.allocate.bits.opcode, request.bits.opcode connect mshrs_11.io.allocate.bits.control, request.bits.control connect mshrs_11.io.allocate.bits.prio[0], request.bits.prio[0] connect mshrs_11.io.allocate.bits.prio[1], request.bits.prio[1] connect mshrs_11.io.allocate.bits.prio[2], request.bits.prio[2] connect mshrs_11.io.allocate.bits.repeat, UInt<1>(0h0) node _T_96 = eq(request.bits.prio[0], UInt<1>(0h0)) node _T_97 = asUInt(reset) node _T_98 = eq(_T_97, UInt<1>(0h0)) when _T_98 : node _T_99 = eq(_T_96, UInt<1>(0h0)) when _T_99 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Scheduler.scala:299 assert (!request.bits.prio(0))\n") : printf_1 assert(clock, _T_96, UInt<1>(0h1), "") : assert_1 node _T_100 = eq(request.bits.prio[1], UInt<1>(0h0)) node _T_101 = asUInt(reset) node _T_102 = eq(_T_101, UInt<1>(0h0)) when _T_102 : node _T_103 = eq(_T_100, UInt<1>(0h0)) when _T_103 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Scheduler.scala:300 assert (!request.bits.prio(1))\n") : printf_2 assert(clock, _T_100, UInt<1>(0h1), "") : assert_2 connect mshrs_11.io.allocate.bits.prio[0], UInt<1>(0h0) connect mshrs_11.io.allocate.bits.prio[1], UInt<1>(0h0) node _dirTarget_T = mux(nestB, UInt<11>(0h400), UInt<12>(0h800)) node dirTarget = mux(alloc, mshr_insertOH, _dirTarget_T) node _directoryFanout_T = mux(alloc_uses_directory, dirTarget, UInt<1>(0h0)) node _directoryFanout_T_1 = mux(mshr_uses_directory, mshr_selectOH, _directoryFanout_T) reg directoryFanout : UInt, clock connect directoryFanout, _directoryFanout_T_1 node _mshrs_0_io_directory_valid_T = bits(directoryFanout, 0, 0) connect mshrs_0.io.directory.valid, _mshrs_0_io_directory_valid_T connect mshrs_0.io.directory.bits.way, directory.io.result.bits.way connect mshrs_0.io.directory.bits.hit, directory.io.result.bits.hit connect mshrs_0.io.directory.bits.tag, directory.io.result.bits.tag connect mshrs_0.io.directory.bits.clients, directory.io.result.bits.clients connect mshrs_0.io.directory.bits.state, directory.io.result.bits.state connect mshrs_0.io.directory.bits.dirty, directory.io.result.bits.dirty node _mshrs_1_io_directory_valid_T = bits(directoryFanout, 1, 1) connect mshrs_1.io.directory.valid, _mshrs_1_io_directory_valid_T connect mshrs_1.io.directory.bits.way, directory.io.result.bits.way connect mshrs_1.io.directory.bits.hit, directory.io.result.bits.hit connect mshrs_1.io.directory.bits.tag, directory.io.result.bits.tag connect mshrs_1.io.directory.bits.clients, directory.io.result.bits.clients connect mshrs_1.io.directory.bits.state, directory.io.result.bits.state connect mshrs_1.io.directory.bits.dirty, directory.io.result.bits.dirty node _mshrs_2_io_directory_valid_T = bits(directoryFanout, 2, 2) connect mshrs_2.io.directory.valid, _mshrs_2_io_directory_valid_T connect mshrs_2.io.directory.bits.way, directory.io.result.bits.way connect mshrs_2.io.directory.bits.hit, directory.io.result.bits.hit connect mshrs_2.io.directory.bits.tag, directory.io.result.bits.tag connect mshrs_2.io.directory.bits.clients, directory.io.result.bits.clients connect mshrs_2.io.directory.bits.state, directory.io.result.bits.state connect mshrs_2.io.directory.bits.dirty, directory.io.result.bits.dirty node _mshrs_3_io_directory_valid_T = bits(directoryFanout, 3, 3) connect mshrs_3.io.directory.valid, _mshrs_3_io_directory_valid_T connect mshrs_3.io.directory.bits.way, directory.io.result.bits.way connect mshrs_3.io.directory.bits.hit, directory.io.result.bits.hit connect mshrs_3.io.directory.bits.tag, directory.io.result.bits.tag connect mshrs_3.io.directory.bits.clients, directory.io.result.bits.clients connect mshrs_3.io.directory.bits.state, directory.io.result.bits.state connect mshrs_3.io.directory.bits.dirty, directory.io.result.bits.dirty node _mshrs_4_io_directory_valid_T = bits(directoryFanout, 4, 4) connect mshrs_4.io.directory.valid, _mshrs_4_io_directory_valid_T connect mshrs_4.io.directory.bits.way, directory.io.result.bits.way connect mshrs_4.io.directory.bits.hit, directory.io.result.bits.hit connect mshrs_4.io.directory.bits.tag, directory.io.result.bits.tag connect mshrs_4.io.directory.bits.clients, directory.io.result.bits.clients connect mshrs_4.io.directory.bits.state, directory.io.result.bits.state connect mshrs_4.io.directory.bits.dirty, directory.io.result.bits.dirty node _mshrs_5_io_directory_valid_T = bits(directoryFanout, 5, 5) connect mshrs_5.io.directory.valid, _mshrs_5_io_directory_valid_T connect mshrs_5.io.directory.bits.way, directory.io.result.bits.way connect mshrs_5.io.directory.bits.hit, directory.io.result.bits.hit connect mshrs_5.io.directory.bits.tag, directory.io.result.bits.tag connect mshrs_5.io.directory.bits.clients, directory.io.result.bits.clients connect mshrs_5.io.directory.bits.state, directory.io.result.bits.state connect mshrs_5.io.directory.bits.dirty, directory.io.result.bits.dirty node _mshrs_6_io_directory_valid_T = bits(directoryFanout, 6, 6) connect mshrs_6.io.directory.valid, _mshrs_6_io_directory_valid_T connect mshrs_6.io.directory.bits.way, directory.io.result.bits.way connect mshrs_6.io.directory.bits.hit, directory.io.result.bits.hit connect mshrs_6.io.directory.bits.tag, directory.io.result.bits.tag connect mshrs_6.io.directory.bits.clients, directory.io.result.bits.clients connect mshrs_6.io.directory.bits.state, directory.io.result.bits.state connect mshrs_6.io.directory.bits.dirty, directory.io.result.bits.dirty node _mshrs_7_io_directory_valid_T = bits(directoryFanout, 7, 7) connect mshrs_7.io.directory.valid, _mshrs_7_io_directory_valid_T connect mshrs_7.io.directory.bits.way, directory.io.result.bits.way connect mshrs_7.io.directory.bits.hit, directory.io.result.bits.hit connect mshrs_7.io.directory.bits.tag, directory.io.result.bits.tag connect mshrs_7.io.directory.bits.clients, directory.io.result.bits.clients connect mshrs_7.io.directory.bits.state, directory.io.result.bits.state connect mshrs_7.io.directory.bits.dirty, directory.io.result.bits.dirty node _mshrs_8_io_directory_valid_T = bits(directoryFanout, 8, 8) connect mshrs_8.io.directory.valid, _mshrs_8_io_directory_valid_T connect mshrs_8.io.directory.bits.way, directory.io.result.bits.way connect mshrs_8.io.directory.bits.hit, directory.io.result.bits.hit connect mshrs_8.io.directory.bits.tag, directory.io.result.bits.tag connect mshrs_8.io.directory.bits.clients, directory.io.result.bits.clients connect mshrs_8.io.directory.bits.state, directory.io.result.bits.state connect mshrs_8.io.directory.bits.dirty, directory.io.result.bits.dirty node _mshrs_9_io_directory_valid_T = bits(directoryFanout, 9, 9) connect mshrs_9.io.directory.valid, _mshrs_9_io_directory_valid_T connect mshrs_9.io.directory.bits.way, directory.io.result.bits.way connect mshrs_9.io.directory.bits.hit, directory.io.result.bits.hit connect mshrs_9.io.directory.bits.tag, directory.io.result.bits.tag connect mshrs_9.io.directory.bits.clients, directory.io.result.bits.clients connect mshrs_9.io.directory.bits.state, directory.io.result.bits.state connect mshrs_9.io.directory.bits.dirty, directory.io.result.bits.dirty node _mshrs_10_io_directory_valid_T = bits(directoryFanout, 10, 10) connect mshrs_10.io.directory.valid, _mshrs_10_io_directory_valid_T connect mshrs_10.io.directory.bits.way, directory.io.result.bits.way connect mshrs_10.io.directory.bits.hit, directory.io.result.bits.hit connect mshrs_10.io.directory.bits.tag, directory.io.result.bits.tag connect mshrs_10.io.directory.bits.clients, directory.io.result.bits.clients connect mshrs_10.io.directory.bits.state, directory.io.result.bits.state connect mshrs_10.io.directory.bits.dirty, directory.io.result.bits.dirty node _mshrs_11_io_directory_valid_T = bits(directoryFanout, 11, 11) connect mshrs_11.io.directory.valid, _mshrs_11_io_directory_valid_T connect mshrs_11.io.directory.bits.way, directory.io.result.bits.way connect mshrs_11.io.directory.bits.hit, directory.io.result.bits.hit connect mshrs_11.io.directory.bits.tag, directory.io.result.bits.tag connect mshrs_11.io.directory.bits.clients, directory.io.result.bits.clients connect mshrs_11.io.directory.bits.state, directory.io.result.bits.state connect mshrs_11.io.directory.bits.dirty, directory.io.result.bits.dirty node _sinkC_io_way_T = eq(mshrs_10.io.status.bits.set, sinkC.io.set) node _sinkC_io_way_T_1 = and(mshrs_10.io.status.valid, _sinkC_io_way_T) node _sinkC_io_way_T_2 = eq(mshrs_0.io.status.bits.set, sinkC.io.set) node _sinkC_io_way_T_3 = and(mshrs_0.io.status.valid, _sinkC_io_way_T_2) node _sinkC_io_way_T_4 = eq(mshrs_1.io.status.bits.set, sinkC.io.set) node _sinkC_io_way_T_5 = and(mshrs_1.io.status.valid, _sinkC_io_way_T_4) node _sinkC_io_way_T_6 = eq(mshrs_2.io.status.bits.set, sinkC.io.set) node _sinkC_io_way_T_7 = and(mshrs_2.io.status.valid, _sinkC_io_way_T_6) node _sinkC_io_way_T_8 = eq(mshrs_3.io.status.bits.set, sinkC.io.set) node _sinkC_io_way_T_9 = and(mshrs_3.io.status.valid, _sinkC_io_way_T_8) node _sinkC_io_way_T_10 = eq(mshrs_4.io.status.bits.set, sinkC.io.set) node _sinkC_io_way_T_11 = and(mshrs_4.io.status.valid, _sinkC_io_way_T_10) node _sinkC_io_way_T_12 = eq(mshrs_5.io.status.bits.set, sinkC.io.set) node _sinkC_io_way_T_13 = and(mshrs_5.io.status.valid, _sinkC_io_way_T_12) node _sinkC_io_way_T_14 = eq(mshrs_6.io.status.bits.set, sinkC.io.set) node _sinkC_io_way_T_15 = and(mshrs_6.io.status.valid, _sinkC_io_way_T_14) node _sinkC_io_way_T_16 = eq(mshrs_7.io.status.bits.set, sinkC.io.set) node _sinkC_io_way_T_17 = and(mshrs_7.io.status.valid, _sinkC_io_way_T_16) node _sinkC_io_way_T_18 = eq(mshrs_8.io.status.bits.set, sinkC.io.set) node _sinkC_io_way_T_19 = and(mshrs_8.io.status.valid, _sinkC_io_way_T_18) node _sinkC_io_way_T_20 = eq(mshrs_9.io.status.bits.set, sinkC.io.set) node _sinkC_io_way_T_21 = and(mshrs_9.io.status.valid, _sinkC_io_way_T_20) node _sinkC_io_way_T_22 = mux(_sinkC_io_way_T_3, mshrs_0.io.status.bits.way, UInt<1>(0h0)) node _sinkC_io_way_T_23 = mux(_sinkC_io_way_T_5, mshrs_1.io.status.bits.way, UInt<1>(0h0)) node _sinkC_io_way_T_24 = mux(_sinkC_io_way_T_7, mshrs_2.io.status.bits.way, UInt<1>(0h0)) node _sinkC_io_way_T_25 = mux(_sinkC_io_way_T_9, mshrs_3.io.status.bits.way, UInt<1>(0h0)) node _sinkC_io_way_T_26 = mux(_sinkC_io_way_T_11, mshrs_4.io.status.bits.way, UInt<1>(0h0)) node _sinkC_io_way_T_27 = mux(_sinkC_io_way_T_13, mshrs_5.io.status.bits.way, UInt<1>(0h0)) node _sinkC_io_way_T_28 = mux(_sinkC_io_way_T_15, mshrs_6.io.status.bits.way, UInt<1>(0h0)) node _sinkC_io_way_T_29 = mux(_sinkC_io_way_T_17, mshrs_7.io.status.bits.way, UInt<1>(0h0)) node _sinkC_io_way_T_30 = mux(_sinkC_io_way_T_19, mshrs_8.io.status.bits.way, UInt<1>(0h0)) node _sinkC_io_way_T_31 = mux(_sinkC_io_way_T_21, mshrs_9.io.status.bits.way, UInt<1>(0h0)) node _sinkC_io_way_T_32 = or(_sinkC_io_way_T_22, _sinkC_io_way_T_23) node _sinkC_io_way_T_33 = or(_sinkC_io_way_T_32, _sinkC_io_way_T_24) node _sinkC_io_way_T_34 = or(_sinkC_io_way_T_33, _sinkC_io_way_T_25) node _sinkC_io_way_T_35 = or(_sinkC_io_way_T_34, _sinkC_io_way_T_26) node _sinkC_io_way_T_36 = or(_sinkC_io_way_T_35, _sinkC_io_way_T_27) node _sinkC_io_way_T_37 = or(_sinkC_io_way_T_36, _sinkC_io_way_T_28) node _sinkC_io_way_T_38 = or(_sinkC_io_way_T_37, _sinkC_io_way_T_29) node _sinkC_io_way_T_39 = or(_sinkC_io_way_T_38, _sinkC_io_way_T_30) node _sinkC_io_way_T_40 = or(_sinkC_io_way_T_39, _sinkC_io_way_T_31) wire _sinkC_io_way_WIRE : UInt<4> connect _sinkC_io_way_WIRE, _sinkC_io_way_T_40 node _sinkC_io_way_T_41 = mux(_sinkC_io_way_T_1, mshrs_10.io.status.bits.way, _sinkC_io_way_WIRE) connect sinkC.io.way, _sinkC_io_way_T_41 wire _sinkD_io_way_WIRE : UInt<4>[12] connect _sinkD_io_way_WIRE[0], mshrs_0.io.status.bits.way connect _sinkD_io_way_WIRE[1], mshrs_1.io.status.bits.way connect _sinkD_io_way_WIRE[2], mshrs_2.io.status.bits.way connect _sinkD_io_way_WIRE[3], mshrs_3.io.status.bits.way connect _sinkD_io_way_WIRE[4], mshrs_4.io.status.bits.way connect _sinkD_io_way_WIRE[5], mshrs_5.io.status.bits.way connect _sinkD_io_way_WIRE[6], mshrs_6.io.status.bits.way connect _sinkD_io_way_WIRE[7], mshrs_7.io.status.bits.way connect _sinkD_io_way_WIRE[8], mshrs_8.io.status.bits.way connect _sinkD_io_way_WIRE[9], mshrs_9.io.status.bits.way connect _sinkD_io_way_WIRE[10], mshrs_10.io.status.bits.way connect _sinkD_io_way_WIRE[11], mshrs_11.io.status.bits.way connect sinkD.io.way, _sinkD_io_way_WIRE[sinkD.io.source] wire _sinkD_io_set_WIRE : UInt<11>[12] connect _sinkD_io_set_WIRE[0], mshrs_0.io.status.bits.set connect _sinkD_io_set_WIRE[1], mshrs_1.io.status.bits.set connect _sinkD_io_set_WIRE[2], mshrs_2.io.status.bits.set connect _sinkD_io_set_WIRE[3], mshrs_3.io.status.bits.set connect _sinkD_io_set_WIRE[4], mshrs_4.io.status.bits.set connect _sinkD_io_set_WIRE[5], mshrs_5.io.status.bits.set connect _sinkD_io_set_WIRE[6], mshrs_6.io.status.bits.set connect _sinkD_io_set_WIRE[7], mshrs_7.io.status.bits.set connect _sinkD_io_set_WIRE[8], mshrs_8.io.status.bits.set connect _sinkD_io_set_WIRE[9], mshrs_9.io.status.bits.set connect _sinkD_io_set_WIRE[10], mshrs_10.io.status.bits.set connect _sinkD_io_set_WIRE[11], mshrs_11.io.status.bits.set connect sinkD.io.set, _sinkD_io_set_WIRE[sinkD.io.source] connect sinkA.io.pb_pop, sourceD.io.pb_pop connect sourceD.io.pb_beat.corrupt, sinkA.io.pb_beat.corrupt connect sourceD.io.pb_beat.mask, sinkA.io.pb_beat.mask connect sourceD.io.pb_beat.data, sinkA.io.pb_beat.data connect sinkC.io.rel_pop, sourceD.io.rel_pop connect sourceD.io.rel_beat.corrupt, sinkC.io.rel_beat.corrupt connect sourceD.io.rel_beat.data, sinkC.io.rel_beat.data connect bankedStore.io.sinkC_adr, sinkC.io.bs_adr connect bankedStore.io.sinkC_dat.data, sinkC.io.bs_dat.data connect bankedStore.io.sinkD_adr, sinkD.io.bs_adr connect bankedStore.io.sinkD_dat.data, sinkD.io.bs_dat.data connect bankedStore.io.sourceC_adr, sourceC.io.bs_adr connect bankedStore.io.sourceD_radr, sourceD.io.bs_radr connect bankedStore.io.sourceD_wadr, sourceD.io.bs_wadr connect bankedStore.io.sourceD_wdat.data, sourceD.io.bs_wdat.data connect sourceC.io.bs_dat.data, bankedStore.io.sourceC_dat.data connect sourceD.io.bs_rdat.data, bankedStore.io.sourceD_rdat.data connect sourceD.io.evict_req.way, sourceC.io.evict_req.way connect sourceD.io.evict_req.set, sourceC.io.evict_req.set connect sourceD.io.grant_req.way, sinkD.io.grant_req.way connect sourceD.io.grant_req.set, sinkD.io.grant_req.set connect sourceC.io.evict_safe, sourceD.io.evict_safe connect sinkD.io.grant_safe, sourceD.io.grant_safe	module InclusiveCacheBankScheduler_7( // @[Scheduler.scala:27:7] input clock, // @[Scheduler.scala:27:7] input reset, // @[Scheduler.scala:27:7] output io_in_a_ready, // @[Scheduler.scala:29:14] input io_in_a_valid, // @[Scheduler.scala:29:14] input [2:0] io_in_a_bits_opcode, // @[Scheduler.scala:29:14] input [2:0] io_in_a_bits_param, // @[Scheduler.scala:29:14] input [2:0] io_in_a_bits_size, // @[Scheduler.scala:29:14] input [5:0] io_in_a_bits_source, // @[Scheduler.scala:29:14] input [31:0] io_in_a_bits_address, // @[Scheduler.scala:29:14] input [15:0] io_in_a_bits_mask, // @[Scheduler.scala:29:14] input [127:0] io_in_a_bits_data, // @[Scheduler.scala:29:14] input io_in_a_bits_corrupt, // @[Scheduler.scala:29:14] input io_in_b_ready, // @[Scheduler.scala:29:14] output io_in_b_valid, // @[Scheduler.scala:29:14] output [1:0] io_in_b_bits_param, // @[Scheduler.scala:29:14] output [31:0] io_in_b_bits_address, // @[Scheduler.scala:29:14] output io_in_c_ready, // @[Scheduler.scala:29:14] input io_in_c_valid, // @[Scheduler.scala:29:14] input [2:0] io_in_c_bits_opcode, // @[Scheduler.scala:29:14] input [2:0] io_in_c_bits_param, // @[Scheduler.scala:29:14] input [2:0] io_in_c_bits_size, // @[Scheduler.scala:29:14] input [5:0] io_in_c_bits_source, // @[Scheduler.scala:29:14] input [31:0] io_in_c_bits_address, // @[Scheduler.scala:29:14] input [127:0] io_in_c_bits_data, // @[Scheduler.scala:29:14] input io_in_c_bits_corrupt, // @[Scheduler.scala:29:14] input io_in_d_ready, // @[Scheduler.scala:29:14] output io_in_d_valid, // @[Scheduler.scala:29:14] output [2:0] io_in_d_bits_opcode, // @[Scheduler.scala:29:14] output [1:0] io_in_d_bits_param, // @[Scheduler.scala:29:14] output [2:0] io_in_d_bits_size, // @[Scheduler.scala:29:14] output [5:0] io_in_d_bits_source, // @[Scheduler.scala:29:14] output [3:0] io_in_d_bits_sink, // @[Scheduler.scala:29:14] output io_in_d_bits_denied, // @[Scheduler.scala:29:14] output [127:0] io_in_d_bits_data, // @[Scheduler.scala:29:14] output io_in_d_bits_corrupt, // @[Scheduler.scala:29:14] input io_in_e_valid, // @[Scheduler.scala:29:14] input [3:0] io_in_e_bits_sink, // @[Scheduler.scala:29:14] input io_out_a_ready, // @[Scheduler.scala:29:14] output io_out_a_valid, // @[Scheduler.scala:29:14] output [2:0] io_out_a_bits_opcode, // @[Scheduler.scala:29:14] output [2:0] io_out_a_bits_param, // @[Scheduler.scala:29:14] output [2:0] io_out_a_bits_size, // @[Scheduler.scala:29:14] output [3:0] io_out_a_bits_source, // @[Scheduler.scala:29:14] output [31:0] io_out_a_bits_address, // @[Scheduler.scala:29:14] output [7:0] io_out_a_bits_mask, // @[Scheduler.scala:29:14] output [63:0] io_out_a_bits_data, // @[Scheduler.scala:29:14] output io_out_a_bits_corrupt, // @[Scheduler.scala:29:14] input io_out_c_ready, // @[Scheduler.scala:29:14] output io_out_c_valid, // @[Scheduler.scala:29:14] output [2:0] io_out_c_bits_opcode, // @[Scheduler.scala:29:14] output [2:0] io_out_c_bits_param, // @[Scheduler.scala:29:14] output [2:0] io_out_c_bits_size, // @[Scheduler.scala:29:14] output [3:0] io_out_c_bits_source, // @[Scheduler.scala:29:14] output [31:0] io_out_c_bits_address, // @[Scheduler.scala:29:14] output [63:0] io_out_c_bits_data, // @[Scheduler.scala:29:14] output io_out_c_bits_corrupt, // @[Scheduler.scala:29:14] output io_out_d_ready, // @[Scheduler.scala:29:14] input io_out_d_valid, // @[Scheduler.scala:29:14] input [2:0] io_out_d_bits_opcode, // @[Scheduler.scala:29:14] input [1:0] io_out_d_bits_param, // @[Scheduler.scala:29:14] input [2:0] io_out_d_bits_size, // @[Scheduler.scala:29:14] input [3:0] io_out_d_bits_source, // @[Scheduler.scala:29:14] input [2:0] io_out_d_bits_sink, // @[Scheduler.scala:29:14] input io_out_d_bits_denied, // @[Scheduler.scala:29:14] input [63:0] io_out_d_bits_data, // @[Scheduler.scala:29:14] input io_out_d_bits_corrupt, // @[Scheduler.scala:29:14] output io_out_e_valid, // @[Scheduler.scala:29:14] output [2:0] io_out_e_bits_sink, // @[Scheduler.scala:29:14] output io_req_ready, // @[Scheduler.scala:29:14] input io_req_valid, // @[Scheduler.scala:29:14] input [31:0] io_req_bits_address, // @[Scheduler.scala:29:14] output io_resp_valid // @[Scheduler.scala:29:14] ); wire [8:0] mshrs_11_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70, :295:103, :297:73] wire [8:0] mshrs_10_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70, :287:131, :289:74] wire [8:0] mshrs_9_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70] wire [8:0] mshrs_8_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70] wire [8:0] mshrs_7_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70] wire [8:0] mshrs_6_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70] wire [8:0] mshrs_5_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70] wire [8:0] mshrs_4_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70] wire [8:0] mshrs_3_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70] wire [8:0] mshrs_2_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70] wire [8:0] mshrs_1_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70] wire [8:0] mshrs_0_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70] wire [5:0] request_bits_put; // @[Scheduler.scala:163:21] wire [5:0] request_bits_offset; // @[Scheduler.scala:163:21] wire [8:0] request_bits_tag; // @[Scheduler.scala:163:21] wire [5:0] request_bits_source; // @[Scheduler.scala:163:21] wire [2:0] request_bits_size; // @[Scheduler.scala:163:21] wire [2:0] request_bits_param; // @[Scheduler.scala:163:21] wire [2:0] request_bits_opcode; // @[Scheduler.scala:163:21] wire request_bits_control; // @[Scheduler.scala:163:21] wire request_bits_prio_2; // @[Scheduler.scala:163:21] wire request_bits_prio_0; // @[Scheduler.scala:163:21] wire _mshrs_11_io_status_valid; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_11_io_status_bits_set; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_11_io_status_bits_tag; // @[Scheduler.scala:71:46] wire _mshrs_11_io_status_bits_blockB; // @[Scheduler.scala:71:46] wire _mshrs_11_io_status_bits_nestB; // @[Scheduler.scala:71:46] wire _mshrs_11_io_status_bits_blockC; // @[Scheduler.scala:71:46] wire _mshrs_11_io_status_bits_nestC; // @[Scheduler.scala:71:46] wire _mshrs_11_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_11_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_11_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_11_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46] wire _mshrs_11_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46] wire _mshrs_11_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_11_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_11_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_11_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46] wire _mshrs_11_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46] wire _mshrs_11_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_11_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_11_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_11_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_11_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_11_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_11_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46] wire _mshrs_11_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46] wire _mshrs_11_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46] wire _mshrs_11_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_11_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_11_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_11_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_11_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_11_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_11_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_11_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_11_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_11_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_11_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46] wire _mshrs_11_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_11_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46] wire _mshrs_11_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46] wire _mshrs_11_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_11_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_11_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_11_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46] wire [1:0] _mshrs_11_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46] wire _mshrs_11_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_11_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46] wire _mshrs_11_io_schedule_bits_reload; // @[Scheduler.scala:71:46] wire _mshrs_10_io_status_valid; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_10_io_status_bits_set; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_10_io_status_bits_tag; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_10_io_status_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_10_io_status_bits_blockB; // @[Scheduler.scala:71:46] wire _mshrs_10_io_status_bits_nestB; // @[Scheduler.scala:71:46] wire _mshrs_10_io_status_bits_blockC; // @[Scheduler.scala:71:46] wire _mshrs_10_io_status_bits_nestC; // @[Scheduler.scala:71:46] wire _mshrs_10_io_schedule_valid; // @[Scheduler.scala:71:46] wire _mshrs_10_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_10_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_10_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_10_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46] wire _mshrs_10_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46] wire _mshrs_10_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_10_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_10_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_10_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46] wire _mshrs_10_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46] wire _mshrs_10_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_10_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_10_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_10_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_10_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_10_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_10_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46] wire _mshrs_10_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46] wire _mshrs_10_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46] wire _mshrs_10_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46] wire _mshrs_10_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_10_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_10_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_10_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_10_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_10_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_10_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_10_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_10_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_10_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_10_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46] wire _mshrs_10_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_10_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46] wire _mshrs_10_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46] wire _mshrs_10_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_10_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_10_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_10_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46] wire [1:0] _mshrs_10_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46] wire _mshrs_10_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_10_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46] wire _mshrs_10_io_schedule_bits_reload; // @[Scheduler.scala:71:46] wire _mshrs_9_io_status_valid; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_9_io_status_bits_set; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_9_io_status_bits_tag; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_9_io_status_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_9_io_status_bits_blockB; // @[Scheduler.scala:71:46] wire _mshrs_9_io_status_bits_nestB; // @[Scheduler.scala:71:46] wire _mshrs_9_io_status_bits_blockC; // @[Scheduler.scala:71:46] wire _mshrs_9_io_status_bits_nestC; // @[Scheduler.scala:71:46] wire _mshrs_9_io_schedule_valid; // @[Scheduler.scala:71:46] wire _mshrs_9_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_9_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_9_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_9_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46] wire _mshrs_9_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46] wire _mshrs_9_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_9_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_9_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_9_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46] wire _mshrs_9_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46] wire _mshrs_9_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_9_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_9_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_9_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_9_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_9_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_9_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46] wire _mshrs_9_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46] wire _mshrs_9_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46] wire _mshrs_9_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46] wire _mshrs_9_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46] wire _mshrs_9_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_9_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_9_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_9_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_9_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_9_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_9_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_9_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_9_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_9_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_9_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46] wire _mshrs_9_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_9_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46] wire _mshrs_9_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46] wire _mshrs_9_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_9_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_9_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_9_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46] wire [1:0] _mshrs_9_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46] wire _mshrs_9_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_9_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46] wire _mshrs_9_io_schedule_bits_reload; // @[Scheduler.scala:71:46] wire _mshrs_8_io_status_valid; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_8_io_status_bits_set; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_8_io_status_bits_tag; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_8_io_status_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_8_io_status_bits_blockB; // @[Scheduler.scala:71:46] wire _mshrs_8_io_status_bits_nestB; // @[Scheduler.scala:71:46] wire _mshrs_8_io_status_bits_blockC; // @[Scheduler.scala:71:46] wire _mshrs_8_io_status_bits_nestC; // @[Scheduler.scala:71:46] wire _mshrs_8_io_schedule_valid; // @[Scheduler.scala:71:46] wire _mshrs_8_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_8_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_8_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_8_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46] wire _mshrs_8_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46] wire _mshrs_8_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_8_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_8_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_8_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46] wire _mshrs_8_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46] wire _mshrs_8_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_8_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_8_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_8_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_8_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_8_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_8_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46] wire _mshrs_8_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46] wire _mshrs_8_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46] wire _mshrs_8_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46] wire _mshrs_8_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46] wire _mshrs_8_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_8_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_8_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_8_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_8_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_8_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_8_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_8_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_8_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_8_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_8_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46] wire _mshrs_8_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_8_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46] wire _mshrs_8_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46] wire _mshrs_8_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_8_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_8_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_8_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46] wire [1:0] _mshrs_8_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46] wire _mshrs_8_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_8_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46] wire _mshrs_8_io_schedule_bits_reload; // @[Scheduler.scala:71:46] wire _mshrs_7_io_status_valid; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_7_io_status_bits_set; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_7_io_status_bits_tag; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_7_io_status_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_7_io_status_bits_blockB; // @[Scheduler.scala:71:46] wire _mshrs_7_io_status_bits_nestB; // @[Scheduler.scala:71:46] wire _mshrs_7_io_status_bits_blockC; // @[Scheduler.scala:71:46] wire _mshrs_7_io_status_bits_nestC; // @[Scheduler.scala:71:46] wire _mshrs_7_io_schedule_valid; // @[Scheduler.scala:71:46] wire _mshrs_7_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_7_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_7_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_7_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46] wire _mshrs_7_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46] wire _mshrs_7_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_7_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_7_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_7_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46] wire _mshrs_7_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46] wire _mshrs_7_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_7_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_7_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_7_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_7_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_7_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_7_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46] wire _mshrs_7_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46] wire _mshrs_7_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46] wire _mshrs_7_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46] wire _mshrs_7_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46] wire _mshrs_7_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_7_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_7_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_7_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_7_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_7_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_7_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_7_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_7_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_7_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_7_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46] wire _mshrs_7_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_7_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46] wire _mshrs_7_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46] wire _mshrs_7_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_7_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_7_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_7_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46] wire [1:0] _mshrs_7_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46] wire _mshrs_7_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_7_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46] wire _mshrs_7_io_schedule_bits_reload; // @[Scheduler.scala:71:46] wire _mshrs_6_io_status_valid; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_6_io_status_bits_set; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_6_io_status_bits_tag; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_6_io_status_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_6_io_status_bits_blockB; // @[Scheduler.scala:71:46] wire _mshrs_6_io_status_bits_nestB; // @[Scheduler.scala:71:46] wire _mshrs_6_io_status_bits_blockC; // @[Scheduler.scala:71:46] wire _mshrs_6_io_status_bits_nestC; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_valid; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_6_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_6_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_6_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_6_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_6_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_6_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_6_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_6_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_6_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_6_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_6_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_6_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_6_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_6_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_6_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_6_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_6_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_6_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_6_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_6_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_6_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_6_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_6_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46] wire [1:0] _mshrs_6_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_6_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_reload; // @[Scheduler.scala:71:46] wire _mshrs_5_io_status_valid; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_5_io_status_bits_set; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_5_io_status_bits_tag; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_5_io_status_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_5_io_status_bits_blockB; // @[Scheduler.scala:71:46] wire _mshrs_5_io_status_bits_nestB; // @[Scheduler.scala:71:46] wire _mshrs_5_io_status_bits_blockC; // @[Scheduler.scala:71:46] wire _mshrs_5_io_status_bits_nestC; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_valid; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_5_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_5_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_5_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_5_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_5_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_5_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_5_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_5_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_5_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_5_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_5_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_5_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_5_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_5_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_5_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_5_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_5_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_5_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_5_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_5_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_5_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_5_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_5_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46] wire [1:0] _mshrs_5_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_5_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_reload; // @[Scheduler.scala:71:46] wire _mshrs_4_io_status_valid; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_4_io_status_bits_set; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_4_io_status_bits_tag; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_4_io_status_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_4_io_status_bits_blockB; // @[Scheduler.scala:71:46] wire _mshrs_4_io_status_bits_nestB; // @[Scheduler.scala:71:46] wire _mshrs_4_io_status_bits_blockC; // @[Scheduler.scala:71:46] wire _mshrs_4_io_status_bits_nestC; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_valid; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_4_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_4_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_4_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_4_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_4_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_4_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_4_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_4_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_4_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_4_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_4_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_4_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_4_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_4_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_4_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_4_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_4_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_4_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_4_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_4_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_4_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_4_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_4_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46] wire [1:0] _mshrs_4_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_4_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_reload; // @[Scheduler.scala:71:46] wire _mshrs_3_io_status_valid; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_3_io_status_bits_set; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_3_io_status_bits_tag; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_3_io_status_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_3_io_status_bits_blockB; // @[Scheduler.scala:71:46] wire _mshrs_3_io_status_bits_nestB; // @[Scheduler.scala:71:46] wire _mshrs_3_io_status_bits_blockC; // @[Scheduler.scala:71:46] wire _mshrs_3_io_status_bits_nestC; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_valid; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_3_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_3_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_3_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_3_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_3_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_3_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_3_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_3_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_3_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_3_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_3_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_3_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_3_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_3_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_3_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_3_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_3_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_3_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_3_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_3_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_3_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_3_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_3_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46] wire [1:0] _mshrs_3_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_3_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_reload; // @[Scheduler.scala:71:46] wire _mshrs_2_io_status_valid; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_2_io_status_bits_set; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_2_io_status_bits_tag; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_2_io_status_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_2_io_status_bits_blockB; // @[Scheduler.scala:71:46] wire _mshrs_2_io_status_bits_nestB; // @[Scheduler.scala:71:46] wire _mshrs_2_io_status_bits_blockC; // @[Scheduler.scala:71:46] wire _mshrs_2_io_status_bits_nestC; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_valid; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_2_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_2_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_2_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_2_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_2_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_2_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_2_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_2_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_2_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_2_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_2_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_2_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_2_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_2_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_2_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_2_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_2_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_2_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_2_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_2_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_2_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_2_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_2_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46] wire [1:0] _mshrs_2_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_2_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_reload; // @[Scheduler.scala:71:46] wire _mshrs_1_io_status_valid; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_1_io_status_bits_set; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_1_io_status_bits_tag; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_1_io_status_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_1_io_status_bits_blockB; // @[Scheduler.scala:71:46] wire _mshrs_1_io_status_bits_nestB; // @[Scheduler.scala:71:46] wire _mshrs_1_io_status_bits_blockC; // @[Scheduler.scala:71:46] wire _mshrs_1_io_status_bits_nestC; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_valid; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_1_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_1_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_1_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_1_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_1_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_1_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_1_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_1_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_1_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_1_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_1_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_1_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_1_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_1_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_1_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_1_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_1_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_1_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_1_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_1_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_1_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_1_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_1_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46] wire [1:0] _mshrs_1_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_1_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_reload; // @[Scheduler.scala:71:46] wire _mshrs_0_io_status_valid; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_0_io_status_bits_set; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_0_io_status_bits_tag; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_0_io_status_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_0_io_status_bits_blockB; // @[Scheduler.scala:71:46] wire _mshrs_0_io_status_bits_nestB; // @[Scheduler.scala:71:46] wire _mshrs_0_io_status_bits_blockC; // @[Scheduler.scala:71:46] wire _mshrs_0_io_status_bits_nestC; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_valid; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_0_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_0_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_0_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_0_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_0_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_0_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_0_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_0_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_0_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_0_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_0_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_0_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_0_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_0_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_0_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_0_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_0_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_0_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_0_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_0_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_0_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_0_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_0_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46] wire [1:0] _mshrs_0_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_0_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_reload; // @[Scheduler.scala:71:46] wire _requests_io_push_ready; // @[Scheduler.scala:70:24] wire [35:0] _requests_io_valid; // @[Scheduler.scala:70:24] wire _requests_io_data_prio_0; // @[Scheduler.scala:70:24] wire _requests_io_data_prio_1; // @[Scheduler.scala:70:24] wire _requests_io_data_prio_2; // @[Scheduler.scala:70:24] wire _requests_io_data_control; // @[Scheduler.scala:70:24] wire [2:0] _requests_io_data_opcode; // @[Scheduler.scala:70:24] wire [2:0] _requests_io_data_param; // @[Scheduler.scala:70:24] wire [2:0] _requests_io_data_size; // @[Scheduler.scala:70:24] wire [5:0] _requests_io_data_source; // @[Scheduler.scala:70:24] wire [8:0] _requests_io_data_tag; // @[Scheduler.scala:70:24] wire [5:0] _requests_io_data_offset; // @[Scheduler.scala:70:24] wire [5:0] _requests_io_data_put; // @[Scheduler.scala:70:24] wire _bankedStore_io_sinkC_adr_ready; // @[Scheduler.scala:69:27] wire _bankedStore_io_sinkD_adr_ready; // @[Scheduler.scala:69:27] wire _bankedStore_io_sourceC_adr_ready; // @[Scheduler.scala:69:27] wire [63:0] _bankedStore_io_sourceC_dat_data; // @[Scheduler.scala:69:27] wire _bankedStore_io_sourceD_radr_ready; // @[Scheduler.scala:69:27] wire [127:0] _bankedStore_io_sourceD_rdat_data; // @[Scheduler.scala:69:27] wire _bankedStore_io_sourceD_wadr_ready; // @[Scheduler.scala:69:27] wire _directory_io_write_ready; // @[Scheduler.scala:68:25] wire _directory_io_result_bits_dirty; // @[Scheduler.scala:68:25] wire [1:0] _directory_io_result_bits_state; // @[Scheduler.scala:68:25] wire _directory_io_result_bits_clients; // @[Scheduler.scala:68:25] wire [8:0] _directory_io_result_bits_tag; // @[Scheduler.scala:68:25] wire _directory_io_result_bits_hit; // @[Scheduler.scala:68:25] wire [3:0] _directory_io_result_bits_way; // @[Scheduler.scala:68:25] wire _directory_io_ready; // @[Scheduler.scala:68:25] wire _sinkX_io_req_valid; // @[Scheduler.scala:58:21] wire [8:0] _sinkX_io_req_bits_tag; // @[Scheduler.scala:58:21] wire [10:0] _sinkX_io_req_bits_set; // @[Scheduler.scala:58:21] wire _sinkE_io_resp_valid; // @[Scheduler.scala:57:21] wire [3:0] _sinkE_io_resp_bits_sink; // @[Scheduler.scala:57:21] wire _sinkD_io_resp_valid; // @[Scheduler.scala:56:21] wire _sinkD_io_resp_bits_last; // @[Scheduler.scala:56:21] wire [2:0] _sinkD_io_resp_bits_opcode; // @[Scheduler.scala:56:21] wire [2:0] _sinkD_io_resp_bits_param; // @[Scheduler.scala:56:21] wire [3:0] _sinkD_io_resp_bits_source; // @[Scheduler.scala:56:21] wire [2:0] _sinkD_io_resp_bits_sink; // @[Scheduler.scala:56:21] wire _sinkD_io_resp_bits_denied; // @[Scheduler.scala:56:21] wire [3:0] _sinkD_io_source; // @[Scheduler.scala:56:21] wire _sinkD_io_bs_adr_valid; // @[Scheduler.scala:56:21] wire _sinkD_io_bs_adr_bits_noop; // @[Scheduler.scala:56:21] wire [3:0] _sinkD_io_bs_adr_bits_way; // @[Scheduler.scala:56:21] wire [10:0] _sinkD_io_bs_adr_bits_set; // @[Scheduler.scala:56:21] wire [2:0] _sinkD_io_bs_adr_bits_beat; // @[Scheduler.scala:56:21] wire [63:0] _sinkD_io_bs_dat_data; // @[Scheduler.scala:56:21] wire [10:0] _sinkD_io_grant_req_set; // @[Scheduler.scala:56:21] wire [3:0] _sinkD_io_grant_req_way; // @[Scheduler.scala:56:21] wire _sinkC_io_req_valid; // @[Scheduler.scala:55:21] wire [2:0] _sinkC_io_req_bits_opcode; // @[Scheduler.scala:55:21] wire [2:0] _sinkC_io_req_bits_param; // @[Scheduler.scala:55:21] wire [2:0] _sinkC_io_req_bits_size; // @[Scheduler.scala:55:21] wire [5:0] _sinkC_io_req_bits_source; // @[Scheduler.scala:55:21] wire [8:0] _sinkC_io_req_bits_tag; // @[Scheduler.scala:55:21] wire [5:0] _sinkC_io_req_bits_offset; // @[Scheduler.scala:55:21] wire [5:0] _sinkC_io_req_bits_put; // @[Scheduler.scala:55:21] wire [10:0] _sinkC_io_req_bits_set; // @[Scheduler.scala:55:21] wire _sinkC_io_resp_valid; // @[Scheduler.scala:55:21] wire _sinkC_io_resp_bits_last; // @[Scheduler.scala:55:21] wire [10:0] _sinkC_io_resp_bits_set; // @[Scheduler.scala:55:21] wire [8:0] _sinkC_io_resp_bits_tag; // @[Scheduler.scala:55:21] wire [5:0] _sinkC_io_resp_bits_source; // @[Scheduler.scala:55:21] wire [2:0] _sinkC_io_resp_bits_param; // @[Scheduler.scala:55:21] wire _sinkC_io_resp_bits_data; // @[Scheduler.scala:55:21] wire [10:0] _sinkC_io_set; // @[Scheduler.scala:55:21] wire _sinkC_io_bs_adr_valid; // @[Scheduler.scala:55:21] wire _sinkC_io_bs_adr_bits_noop; // @[Scheduler.scala:55:21] wire [3:0] _sinkC_io_bs_adr_bits_way; // @[Scheduler.scala:55:21] wire [10:0] _sinkC_io_bs_adr_bits_set; // @[Scheduler.scala:55:21] wire [1:0] _sinkC_io_bs_adr_bits_beat; // @[Scheduler.scala:55:21] wire [1:0] _sinkC_io_bs_adr_bits_mask; // @[Scheduler.scala:55:21] wire [127:0] _sinkC_io_bs_dat_data; // @[Scheduler.scala:55:21] wire _sinkC_io_rel_pop_ready; // @[Scheduler.scala:55:21] wire [127:0] _sinkC_io_rel_beat_data; // @[Scheduler.scala:55:21] wire _sinkC_io_rel_beat_corrupt; // @[Scheduler.scala:55:21] wire _sinkA_io_req_valid; // @[Scheduler.scala:54:21] wire [2:0] _sinkA_io_req_bits_opcode; // @[Scheduler.scala:54:21] wire [2:0] _sinkA_io_req_bits_param; // @[Scheduler.scala:54:21] wire [2:0] _sinkA_io_req_bits_size; // @[Scheduler.scala:54:21] wire [5:0] _sinkA_io_req_bits_source; // @[Scheduler.scala:54:21] wire [8:0] _sinkA_io_req_bits_tag; // @[Scheduler.scala:54:21] wire [5:0] _sinkA_io_req_bits_offset; // @[Scheduler.scala:54:21] wire [5:0] _sinkA_io_req_bits_put; // @[Scheduler.scala:54:21] wire [10:0] _sinkA_io_req_bits_set; // @[Scheduler.scala:54:21] wire _sinkA_io_pb_pop_ready; // @[Scheduler.scala:54:21] wire [127:0] _sinkA_io_pb_beat_data; // @[Scheduler.scala:54:21] wire [15:0] _sinkA_io_pb_beat_mask; // @[Scheduler.scala:54:21] wire _sinkA_io_pb_beat_corrupt; // @[Scheduler.scala:54:21] wire _sourceX_io_req_ready; // @[Scheduler.scala:45:23] wire _sourceE_io_req_ready; // @[Scheduler.scala:44:23] wire _sourceD_io_req_ready; // @[Scheduler.scala:43:23] wire _sourceD_io_pb_pop_valid; // @[Scheduler.scala:43:23] wire [5:0] _sourceD_io_pb_pop_bits_index; // @[Scheduler.scala:43:23] wire _sourceD_io_pb_pop_bits_last; // @[Scheduler.scala:43:23] wire _sourceD_io_rel_pop_valid; // @[Scheduler.scala:43:23] wire [5:0] _sourceD_io_rel_pop_bits_index; // @[Scheduler.scala:43:23] wire _sourceD_io_rel_pop_bits_last; // @[Scheduler.scala:43:23] wire _sourceD_io_bs_radr_valid; // @[Scheduler.scala:43:23] wire [3:0] _sourceD_io_bs_radr_bits_way; // @[Scheduler.scala:43:23] wire [10:0] _sourceD_io_bs_radr_bits_set; // @[Scheduler.scala:43:23] wire [1:0] _sourceD_io_bs_radr_bits_beat; // @[Scheduler.scala:43:23] wire [1:0] _sourceD_io_bs_radr_bits_mask; // @[Scheduler.scala:43:23] wire _sourceD_io_bs_wadr_valid; // @[Scheduler.scala:43:23] wire [3:0] _sourceD_io_bs_wadr_bits_way; // @[Scheduler.scala:43:23] wire [10:0] _sourceD_io_bs_wadr_bits_set; // @[Scheduler.scala:43:23] wire [1:0] _sourceD_io_bs_wadr_bits_beat; // @[Scheduler.scala:43:23] wire [1:0] _sourceD_io_bs_wadr_bits_mask; // @[Scheduler.scala:43:23] wire [127:0] _sourceD_io_bs_wdat_data; // @[Scheduler.scala:43:23] wire _sourceD_io_evict_safe; // @[Scheduler.scala:43:23] wire _sourceD_io_grant_safe; // @[Scheduler.scala:43:23] wire _sourceC_io_req_ready; // @[Scheduler.scala:42:23] wire _sourceC_io_bs_adr_valid; // @[Scheduler.scala:42:23] wire [3:0] _sourceC_io_bs_adr_bits_way; // @[Scheduler.scala:42:23] wire [10:0] _sourceC_io_bs_adr_bits_set; // @[Scheduler.scala:42:23] wire [2:0] _sourceC_io_bs_adr_bits_beat; // @[Scheduler.scala:42:23] wire [10:0] _sourceC_io_evict_req_set; // @[Scheduler.scala:42:23] wire [3:0] _sourceC_io_evict_req_way; // @[Scheduler.scala:42:23] wire _sourceB_io_req_ready; // @[Scheduler.scala:41:23] wire _sourceA_io_req_ready; // @[Scheduler.scala:40:23] wire io_in_a_valid_0 = io_in_a_valid; // @[Scheduler.scala:27:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Scheduler.scala:27:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Scheduler.scala:27:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Scheduler.scala:27:7] wire [5:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Scheduler.scala:27:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Scheduler.scala:27:7] wire [15:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Scheduler.scala:27:7] wire [127:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Scheduler.scala:27:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Scheduler.scala:27:7] wire io_in_b_ready_0 = io_in_b_ready; // @[Scheduler.scala:27:7] wire io_in_c_valid_0 = io_in_c_valid; // @[Scheduler.scala:27:7] wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Scheduler.scala:27:7] wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Scheduler.scala:27:7] wire [2:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Scheduler.scala:27:7] wire [5:0] io_in_c_bits_source_0 = io_in_c_bits_source; // @[Scheduler.scala:27:7] wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Scheduler.scala:27:7] wire [127:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Scheduler.scala:27:7] wire io_in_c_bits_corrupt_0 = io_in_c_bits_corrupt; // @[Scheduler.scala:27:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Scheduler.scala:27:7] wire io_in_e_valid_0 = io_in_e_valid; // @[Scheduler.scala:27:7] wire [3:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Scheduler.scala:27:7] wire io_out_a_ready_0 = io_out_a_ready; // @[Scheduler.scala:27:7] wire io_out_c_ready_0 = io_out_c_ready; // @[Scheduler.scala:27:7] wire io_out_d_valid_0 = io_out_d_valid; // @[Scheduler.scala:27:7] wire [2:0] io_out_d_bits_opcode_0 = io_out_d_bits_opcode; // @[Scheduler.scala:27:7] wire [1:0] io_out_d_bits_param_0 = io_out_d_bits_param; // @[Scheduler.scala:27:7] wire [2:0] io_out_d_bits_size_0 = io_out_d_bits_size; // @[Scheduler.scala:27:7] wire [3:0] io_out_d_bits_source_0 = io_out_d_bits_source; // @[Scheduler.scala:27:7] wire [2:0] io_out_d_bits_sink_0 = io_out_d_bits_sink; // @[Scheduler.scala:27:7] wire io_out_d_bits_denied_0 = io_out_d_bits_denied; // @[Scheduler.scala:27:7] wire [63:0] io_out_d_bits_data_0 = io_out_d_bits_data; // @[Scheduler.scala:27:7] wire io_out_d_bits_corrupt_0 = io_out_d_bits_corrupt; // @[Scheduler.scala:27:7] wire io_req_valid_0 = io_req_valid; // @[Scheduler.scala:27:7] wire [31:0] io_req_bits_address_0 = io_req_bits_address; // @[Scheduler.scala:27:7] wire io_in_b_bits_corrupt = 1'h0; // @[Scheduler.scala:27:7] wire io_out_b_valid = 1'h0; // @[Scheduler.scala:27:7] wire io_out_b_bits_corrupt = 1'h0; // @[Scheduler.scala:27:7] wire io_resp_bits_fail = 1'h0; // @[Scheduler.scala:27:7] wire schedule_x_bits_fail = 1'h0; // @[Mux.scala:30:73] wire _schedule_WIRE_11_bits_fail = 1'h0; // @[Mux.scala:30:73] wire _schedule_WIRE_12_fail = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_196 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_197 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_198 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_199 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_200 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_201 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_202 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_203 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_204 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_205 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_206 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_207 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_208 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_209 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_210 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_211 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_212 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_213 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_214 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_215 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_216 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_217 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_218 = 1'h0; // @[Mux.scala:30:73] wire _schedule_WIRE_13 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_574 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_575 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_598 = 1'h0; // @[Mux.scala:30:73] wire request_bits_prio_1 = 1'h0; // @[Scheduler.scala:163:21] wire _request_bits_T_prio_1 = 1'h0; // @[Scheduler.scala:166:22] wire _request_bits_T_prio_2 = 1'h0; // @[Scheduler.scala:166:22] wire _request_bits_T_1_prio_1 = 1'h0; // @[Scheduler.scala:165:22] wire blockB = 1'h0; // @[Scheduler.scala:175:70] wire nestB = 1'h0; // @[Scheduler.scala:179:70] wire _view__WIRE_prio_1 = 1'h0; // @[Scheduler.scala:233:95] wire _view__WIRE_1_prio_1 = 1'h0; // @[Scheduler.scala:233:95] wire _view__WIRE_2_prio_1 = 1'h0; // @[Scheduler.scala:233:95] wire _view__WIRE_3_prio_1 = 1'h0; // @[Scheduler.scala:233:95] wire _view__WIRE_4_prio_1 = 1'h0; // @[Scheduler.scala:233:95] wire _view__WIRE_5_prio_1 = 1'h0; // @[Scheduler.scala:233:95] wire _view__WIRE_6_prio_1 = 1'h0; // @[Scheduler.scala:233:95] wire _view__WIRE_7_prio_1 = 1'h0; // @[Scheduler.scala:233:95] wire _view__WIRE_8_prio_1 = 1'h0; // @[Scheduler.scala:233:95] wire _view__WIRE_9_prio_1 = 1'h0; // @[Scheduler.scala:233:95] wire _view__WIRE_10_prio_1 = 1'h0; // @[Scheduler.scala:233:95] wire _view__WIRE_11_prio_1 = 1'h0; // @[Scheduler.scala:233:95] wire _request_alloc_cases_T_4 = 1'h0; // @[Scheduler.scala:259:13] wire _request_alloc_cases_T_6 = 1'h0; // @[Scheduler.scala:259:56] wire _request_alloc_cases_T_8 = 1'h0; // @[Scheduler.scala:259:84] wire [2:0] io_in_b_bits_opcode = 3'h6; // @[Scheduler.scala:27:7] wire [2:0] io_in_b_bits_size = 3'h6; // @[Scheduler.scala:27:7] wire [5:0] io_in_b_bits_source = 6'h28; // @[Scheduler.scala:27:7] wire [15:0] io_in_b_bits_mask = 16'hFFFF; // @[Scheduler.scala:27:7] wire [127:0] io_in_b_bits_data = 128'h0; // @[Scheduler.scala:27:7] wire io_in_e_ready = 1'h1; // @[Scheduler.scala:27:7] wire io_out_b_ready = 1'h1; // @[Scheduler.scala:27:7] wire io_out_e_ready = 1'h1; // @[Scheduler.scala:27:7] wire io_resp_ready = 1'h1; // @[Scheduler.scala:27:7] wire _mshr_request_T_253 = 1'h1; // @[Scheduler.scala:107:28] wire _request_bits_T_prio_0 = 1'h1; // @[Scheduler.scala:166:22] wire _queue_T_1 = 1'h1; // @[Scheduler.scala:185:35] wire _queue_T_5 = 1'h1; // @[Scheduler.scala:185:55] wire [2:0] io_out_b_bits_opcode = 3'h0; // @[Scheduler.scala:27:7] wire [2:0] io_out_b_bits_size = 3'h0; // @[Scheduler.scala:27:7] wire [1:0] io_out_b_bits_param = 2'h0; // @[Scheduler.scala:27:7] wire [3:0] io_out_b_bits_source = 4'h0; // @[Scheduler.scala:27:7] wire [3:0] _schedule_WIRE_19_bits_sink = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_WIRE_20_sink = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_334 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_335 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_336 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_337 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_338 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_339 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_340 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_341 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_342 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_343 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_344 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_345 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_346 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_347 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_348 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_349 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_350 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_351 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_352 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_353 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_354 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_355 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_356 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_WIRE_23 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_WIRE_38_bits_source = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_WIRE_39_source = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_748 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_749 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_750 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_751 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_752 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_753 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_754 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_755 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_756 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_757 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_758 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_759 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_760 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_761 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_762 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_763 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_764 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_765 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_766 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_767 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_768 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_769 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_770 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_WIRE_44 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_WIRE_55_bits_source = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_WIRE_56_source = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_978 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_979 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_980 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_981 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_982 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_983 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_984 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_985 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_986 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_987 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_988 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_989 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_990 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_991 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_992 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_993 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_994 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_995 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_996 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_997 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_998 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_999 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_1000 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_WIRE_58 = 4'h0; // @[Mux.scala:30:73] wire [31:0] io_out_b_bits_address = 32'h0; // @[Scheduler.scala:27:7] wire [7:0] io_out_b_bits_mask = 8'h0; // @[Scheduler.scala:27:7] wire [63:0] io_out_b_bits_data = 64'h0; // @[Scheduler.scala:27:7] wire [15:0] io_ways_0 = 16'h0; // @[Scheduler.scala:27:7] wire [15:0] io_ways_1 = 16'h0; // @[Scheduler.scala:27:7] wire [15:0] io_ways_2 = 16'h0; // @[Scheduler.scala:27:7] wire [15:0] io_ways_3 = 16'h0; // @[Scheduler.scala:27:7] wire [15:0] io_ways_4 = 16'h0; // @[Scheduler.scala:27:7] wire [15:0] io_ways_5 = 16'h0; // @[Scheduler.scala:27:7] wire [15:0] io_ways_6 = 16'h0; // @[Scheduler.scala:27:7] wire [15:0] io_ways_7 = 16'h0; // @[Scheduler.scala:27:7] wire [10:0] io_divs_0 = 11'h0; // @[Scheduler.scala:27:7] wire [10:0] io_divs_1 = 11'h0; // @[Scheduler.scala:27:7] wire [10:0] io_divs_2 = 11'h0; // @[Scheduler.scala:27:7] wire [10:0] io_divs_3 = 11'h0; // @[Scheduler.scala:27:7] wire [10:0] io_divs_4 = 11'h0; // @[Scheduler.scala:27:7] wire [10:0] io_divs_5 = 11'h0; // @[Scheduler.scala:27:7] wire [10:0] io_divs_6 = 11'h0; // @[Scheduler.scala:27:7] wire [10:0] io_divs_7 = 11'h0; // @[Scheduler.scala:27:7] wire [11:0] _lowerMatches1_T_1 = 12'h800; // @[Scheduler.scala:200:43] wire [11:0] _dirTarget_T = 12'h800; // @[Scheduler.scala:306:48] wire [4:0] _requests_io_push_bits_index_T_43 = 5'h0; // @[Mux.scala:30:73] wire [9:0] _prioFilter_T_1 = 10'h3FF; // @[Scheduler.scala:182:69] wire [10:0] _lowerMatches1_T_3 = 11'h400; // @[Scheduler.scala:201:43] wire io_in_a_ready_0; // @[Scheduler.scala:27:7] wire [1:0] io_in_b_bits_param_0; // @[Scheduler.scala:27:7] wire [31:0] io_in_b_bits_address_0; // @[Scheduler.scala:27:7] wire io_in_b_valid_0; // @[Scheduler.scala:27:7] wire io_in_c_ready_0; // @[Scheduler.scala:27:7] wire [2:0] io_in_d_bits_opcode_0; // @[Scheduler.scala:27:7] wire [1:0] io_in_d_bits_param_0; // @[Scheduler.scala:27:7] wire [2:0] io_in_d_bits_size_0; // @[Scheduler.scala:27:7] wire [5:0] io_in_d_bits_source_0; // @[Scheduler.scala:27:7] wire [3:0] io_in_d_bits_sink_0; // @[Scheduler.scala:27:7] wire io_in_d_bits_denied_0; // @[Scheduler.scala:27:7] wire [127:0] io_in_d_bits_data_0; // @[Scheduler.scala:27:7] wire io_in_d_bits_corrupt_0; // @[Scheduler.scala:27:7] wire io_in_d_valid_0; // @[Scheduler.scala:27:7] wire [2:0] io_out_a_bits_opcode_0; // @[Scheduler.scala:27:7] wire [2:0] io_out_a_bits_param_0; // @[Scheduler.scala:27:7] wire [2:0] io_out_a_bits_size_0; // @[Scheduler.scala:27:7] wire [3:0] io_out_a_bits_source_0; // @[Scheduler.scala:27:7] wire [31:0] io_out_a_bits_address_0; // @[Scheduler.scala:27:7] wire [7:0] io_out_a_bits_mask_0; // @[Scheduler.scala:27:7] wire [63:0] io_out_a_bits_data_0; // @[Scheduler.scala:27:7] wire io_out_a_bits_corrupt_0; // @[Scheduler.scala:27:7] wire io_out_a_valid_0; // @[Scheduler.scala:27:7] wire [2:0] io_out_c_bits_opcode_0; // @[Scheduler.scala:27:7] wire [2:0] io_out_c_bits_param_0; // @[Scheduler.scala:27:7] wire [2:0] io_out_c_bits_size_0; // @[Scheduler.scala:27:7] wire [3:0] io_out_c_bits_source_0; // @[Scheduler.scala:27:7] wire [31:0] io_out_c_bits_address_0; // @[Scheduler.scala:27:7] wire [63:0] io_out_c_bits_data_0; // @[Scheduler.scala:27:7] wire io_out_c_bits_corrupt_0; // @[Scheduler.scala:27:7] wire io_out_c_valid_0; // @[Scheduler.scala:27:7] wire io_out_d_ready_0; // @[Scheduler.scala:27:7] wire [2:0] io_out_e_bits_sink_0; // @[Scheduler.scala:27:7] wire io_out_e_valid_0; // @[Scheduler.scala:27:7] wire io_req_ready_0; // @[Scheduler.scala:27:7] wire io_resp_valid_0; // @[Scheduler.scala:27:7] wire [10:0] _nestedwb_set_T; // @[Scheduler.scala:155:24] wire [8:0] _nestedwb_tag_T; // @[Scheduler.scala:156:24] wire _nestedwb_b_toN_T_2; // @[Scheduler.scala:157:75] wire _nestedwb_b_toB_T_2; // @[Scheduler.scala:158:75] wire _nestedwb_b_clr_dirty_T; // @[Scheduler.scala:159:37] wire _nestedwb_c_set_dirty_T_1; // @[Scheduler.scala:160:75] wire [10:0] nestedwb_set; // @[Scheduler.scala:75:22] wire [8:0] nestedwb_tag; // @[Scheduler.scala:75:22] wire nestedwb_b_toN; // @[Scheduler.scala:75:22] wire nestedwb_b_toB; // @[Scheduler.scala:75:22] wire nestedwb_b_clr_dirty; // @[Scheduler.scala:75:22] wire nestedwb_c_set_dirty; // @[Scheduler.scala:75:22] wire _mshrs_0_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_0_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71] wire _mshrs_0_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_0_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}] wire _mshrs_0_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 4'h0; // @[Scheduler.scala:56:21, :80:74] wire _mshrs_0_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_0_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}] wire _mshrs_0_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 4'h0; // @[Scheduler.scala:57:21, :81:74] wire _mshrs_0_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_0_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}] wire _mshrs_1_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_1_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71] wire _mshrs_1_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_1_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}] wire _mshrs_1_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 4'h1; // @[Scheduler.scala:56:21, :80:74] wire _mshrs_1_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_1_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}] wire _mshrs_1_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 4'h1; // @[Scheduler.scala:57:21, :81:74] wire _mshrs_1_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_1_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}] wire _mshrs_2_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_2_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71] wire _mshrs_2_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_2_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}] wire _mshrs_2_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 4'h2; // @[Scheduler.scala:56:21, :80:74] wire _mshrs_2_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_2_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}] wire _mshrs_2_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 4'h2; // @[Scheduler.scala:57:21, :81:74] wire _mshrs_2_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_2_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}] wire _mshrs_3_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_3_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71] wire _mshrs_3_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_3_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}] wire _mshrs_3_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 4'h3; // @[Scheduler.scala:56:21, :80:74] wire _mshrs_3_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_3_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}] wire _mshrs_3_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 4'h3; // @[Scheduler.scala:57:21, :81:74] wire _mshrs_3_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_3_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}] wire _mshrs_4_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_4_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71] wire _mshrs_4_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_4_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}] wire _mshrs_4_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 4'h4; // @[Scheduler.scala:56:21, :80:74] wire _mshrs_4_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_4_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}] wire _mshrs_4_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 4'h4; // @[Scheduler.scala:57:21, :81:74] wire _mshrs_4_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_4_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}] wire _mshrs_5_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_5_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71] wire _mshrs_5_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_5_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}] wire _mshrs_5_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 4'h5; // @[Scheduler.scala:56:21, :80:74] wire _mshrs_5_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_5_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}] wire _mshrs_5_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 4'h5; // @[Scheduler.scala:57:21, :81:74] wire _mshrs_5_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_5_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}] wire _mshrs_6_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_6_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71] wire _mshrs_6_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_6_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}] wire _mshrs_6_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 4'h6; // @[Scheduler.scala:56:21, :80:74] wire _mshrs_6_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_6_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}] wire _mshrs_6_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 4'h6; // @[Scheduler.scala:57:21, :81:74] wire _mshrs_6_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_6_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}] wire _mshrs_7_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_7_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71] wire _mshrs_7_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_7_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}] wire _mshrs_7_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 4'h7; // @[Scheduler.scala:56:21, :80:74] wire _mshrs_7_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_7_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}] wire _mshrs_7_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 4'h7; // @[Scheduler.scala:57:21, :81:74] wire _mshrs_7_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_7_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}] wire _mshrs_8_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_8_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71] wire _mshrs_8_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_8_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}] wire _mshrs_8_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 4'h8; // @[Scheduler.scala:56:21, :80:74] wire _mshrs_8_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_8_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}] wire _mshrs_8_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 4'h8; // @[Scheduler.scala:57:21, :81:74] wire _mshrs_8_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_8_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}] wire _mshrs_9_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_9_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71] wire _mshrs_9_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_9_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}] wire _mshrs_9_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 4'h9; // @[Scheduler.scala:56:21, :80:74] wire _mshrs_9_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_9_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}] wire _mshrs_9_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 4'h9; // @[Scheduler.scala:57:21, :81:74] wire _mshrs_9_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_9_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}] wire _mshrs_10_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_10_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71] wire _mshrs_10_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_10_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}] wire _mshrs_10_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 4'hA; // @[Scheduler.scala:56:21, :80:74] wire _mshrs_10_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_10_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}] wire _mshrs_10_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 4'hA; // @[Scheduler.scala:57:21, :81:74] wire _mshrs_10_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_10_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}] wire _mshrs_11_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_11_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71] wire _mshrs_11_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_11_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}] wire _mshrs_11_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 4'hB; // @[Scheduler.scala:56:21, :80:74] wire _mshrs_11_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_11_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}] wire _mshrs_11_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 4'hB; // @[Scheduler.scala:57:21, :81:74] wire _mshrs_11_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_11_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}] wire _mshr_stall_abc_T = _mshrs_0_io_status_bits_set == _mshrs_10_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54] wire _mshr_stall_abc_T_1 = _mshrs_10_io_status_valid & _mshr_stall_abc_T; // @[Scheduler.scala:71:46, :90:{30,54}] wire _mshr_stall_abc_T_2 = _mshrs_0_io_status_bits_set == _mshrs_11_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54] wire _mshr_stall_abc_T_3 = _mshrs_11_io_status_valid & _mshr_stall_abc_T_2; // @[Scheduler.scala:71:46, :91:{30,54}] wire mshr_stall_abc_0 = _mshr_stall_abc_T_1 \| _mshr_stall_abc_T_3; // @[Scheduler.scala:90:{30,86}, :91:30] wire _mshr_stall_abc_T_4 = _mshrs_1_io_status_bits_set == _mshrs_10_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54] wire _mshr_stall_abc_T_5 = _mshrs_10_io_status_valid & _mshr_stall_abc_T_4; // @[Scheduler.scala:71:46, :90:{30,54}] wire _mshr_stall_abc_T_6 = _mshrs_1_io_status_bits_set == _mshrs_11_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54] wire _mshr_stall_abc_T_7 = _mshrs_11_io_status_valid & _mshr_stall_abc_T_6; // @[Scheduler.scala:71:46, :91:{30,54}] wire mshr_stall_abc_1 = _mshr_stall_abc_T_5 \| _mshr_stall_abc_T_7; // @[Scheduler.scala:90:{30,86}, :91:30] wire _mshr_stall_abc_T_8 = _mshrs_2_io_status_bits_set == _mshrs_10_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54] wire _mshr_stall_abc_T_9 = _mshrs_10_io_status_valid & _mshr_stall_abc_T_8; // @[Scheduler.scala:71:46, :90:{30,54}] wire _mshr_stall_abc_T_10 = _mshrs_2_io_status_bits_set == _mshrs_11_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54] wire _mshr_stall_abc_T_11 = _mshrs_11_io_status_valid & _mshr_stall_abc_T_10; // @[Scheduler.scala:71:46, :91:{30,54}] wire mshr_stall_abc_2 = _mshr_stall_abc_T_9 \| _mshr_stall_abc_T_11; // @[Scheduler.scala:90:{30,86}, :91:30] wire _mshr_stall_abc_T_12 = _mshrs_3_io_status_bits_set == _mshrs_10_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54] wire _mshr_stall_abc_T_13 = _mshrs_10_io_status_valid & _mshr_stall_abc_T_12; // @[Scheduler.scala:71:46, :90:{30,54}] wire _mshr_stall_abc_T_14 = _mshrs_3_io_status_bits_set == _mshrs_11_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54] wire _mshr_stall_abc_T_15 = _mshrs_11_io_status_valid & _mshr_stall_abc_T_14; // @[Scheduler.scala:71:46, :91:{30,54}] wire mshr_stall_abc_3 = _mshr_stall_abc_T_13 \| _mshr_stall_abc_T_15; // @[Scheduler.scala:90:{30,86}, :91:30] wire _mshr_stall_abc_T_16 = _mshrs_4_io_status_bits_set == _mshrs_10_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54] wire _mshr_stall_abc_T_17 = _mshrs_10_io_status_valid & _mshr_stall_abc_T_16; // @[Scheduler.scala:71:46, :90:{30,54}] wire _mshr_stall_abc_T_18 = _mshrs_4_io_status_bits_set == _mshrs_11_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54] wire _mshr_stall_abc_T_19 = _mshrs_11_io_status_valid & _mshr_stall_abc_T_18; // @[Scheduler.scala:71:46, :91:{30,54}] wire mshr_stall_abc_4 = _mshr_stall_abc_T_17 \| _mshr_stall_abc_T_19; // @[Scheduler.scala:90:{30,86}, :91:30] wire _mshr_stall_abc_T_20 = _mshrs_5_io_status_bits_set == _mshrs_10_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54] wire _mshr_stall_abc_T_21 = _mshrs_10_io_status_valid & _mshr_stall_abc_T_20; // @[Scheduler.scala:71:46, :90:{30,54}] wire _mshr_stall_abc_T_22 = _mshrs_5_io_status_bits_set == _mshrs_11_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54] wire _mshr_stall_abc_T_23 = _mshrs_11_io_status_valid & _mshr_stall_abc_T_22; // @[Scheduler.scala:71:46, :91:{30,54}] wire mshr_stall_abc_5 = _mshr_stall_abc_T_21 \| _mshr_stall_abc_T_23; // @[Scheduler.scala:90:{30,86}, :91:30] wire _mshr_stall_abc_T_24 = _mshrs_6_io_status_bits_set == _mshrs_10_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54] wire _mshr_stall_abc_T_25 = _mshrs_10_io_status_valid & _mshr_stall_abc_T_24; // @[Scheduler.scala:71:46, :90:{30,54}] wire _mshr_stall_abc_T_26 = _mshrs_6_io_status_bits_set == _mshrs_11_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54] wire _mshr_stall_abc_T_27 = _mshrs_11_io_status_valid & _mshr_stall_abc_T_26; // @[Scheduler.scala:71:46, :91:{30,54}] wire mshr_stall_abc_6 = _mshr_stall_abc_T_25 \| _mshr_stall_abc_T_27; // @[Scheduler.scala:90:{30,86}, :91:30] wire _mshr_stall_abc_T_28 = _mshrs_7_io_status_bits_set == _mshrs_10_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54] wire _mshr_stall_abc_T_29 = _mshrs_10_io_status_valid & _mshr_stall_abc_T_28; // @[Scheduler.scala:71:46, :90:{30,54}] wire _mshr_stall_abc_T_30 = _mshrs_7_io_status_bits_set == _mshrs_11_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54] wire _mshr_stall_abc_T_31 = _mshrs_11_io_status_valid & _mshr_stall_abc_T_30; // @[Scheduler.scala:71:46, :91:{30,54}] wire mshr_stall_abc_7 = _mshr_stall_abc_T_29 \| _mshr_stall_abc_T_31; // @[Scheduler.scala:90:{30,86}, :91:30] wire _mshr_stall_abc_T_32 = _mshrs_8_io_status_bits_set == _mshrs_10_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54] wire _mshr_stall_abc_T_33 = _mshrs_10_io_status_valid & _mshr_stall_abc_T_32; // @[Scheduler.scala:71:46, :90:{30,54}] wire _mshr_stall_abc_T_34 = _mshrs_8_io_status_bits_set == _mshrs_11_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54] wire _mshr_stall_abc_T_35 = _mshrs_11_io_status_valid & _mshr_stall_abc_T_34; // @[Scheduler.scala:71:46, :91:{30,54}] wire mshr_stall_abc_8 = _mshr_stall_abc_T_33 \| _mshr_stall_abc_T_35; // @[Scheduler.scala:90:{30,86}, :91:30] wire _mshr_stall_abc_T_36 = _mshrs_9_io_status_bits_set == _mshrs_10_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54] wire _mshr_stall_abc_T_37 = _mshrs_10_io_status_valid & _mshr_stall_abc_T_36; // @[Scheduler.scala:71:46, :90:{30,54}] wire _mshr_stall_abc_T_38 = _mshrs_9_io_status_bits_set == _mshrs_11_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54] wire _mshr_stall_abc_T_39 = _mshrs_11_io_status_valid & _mshr_stall_abc_T_38; // @[Scheduler.scala:71:46, :91:{30,54}] wire mshr_stall_abc_9 = _mshr_stall_abc_T_37 \| _mshr_stall_abc_T_39; // @[Scheduler.scala:90:{30,86}, :91:30] wire _mshr_stall_bc_T = _mshrs_10_io_status_bits_set == _mshrs_11_io_status_bits_set; // @[Scheduler.scala:71:46, :94:58] wire mshr_stall_bc = _mshrs_11_io_status_valid & _mshr_stall_bc_T; // @[Scheduler.scala:71:46, :94:{28,58}] wire stall_abc_0 = mshr_stall_abc_0 & _mshrs_0_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73] wire stall_abc_1 = mshr_stall_abc_1 & _mshrs_1_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73] wire stall_abc_2 = mshr_stall_abc_2 & _mshrs_2_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73] wire stall_abc_3 = mshr_stall_abc_3 & _mshrs_3_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73] wire stall_abc_4 = mshr_stall_abc_4 & _mshrs_4_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73] wire stall_abc_5 = mshr_stall_abc_5 & _mshrs_5_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73] wire stall_abc_6 = mshr_stall_abc_6 & _mshrs_6_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73] wire stall_abc_7 = mshr_stall_abc_7 & _mshrs_7_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73] wire stall_abc_8 = mshr_stall_abc_8 & _mshrs_8_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73] wire stall_abc_9 = mshr_stall_abc_9 & _mshrs_9_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73] wire _mshr_request_T = ~mshr_stall_abc_0; // @[Scheduler.scala:90:86, :107:28] wire _mshr_request_T_1 = _mshrs_0_io_schedule_valid & _mshr_request_T; // @[Scheduler.scala:71:46, :107:{25,28}] wire _mshr_request_T_2 = ~_mshrs_0_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32] wire _mshr_request_T_3 = _sourceA_io_req_ready \| _mshr_request_T_2; // @[Scheduler.scala:40:23, :108:{29,32}] wire _mshr_request_T_4 = _mshr_request_T_1 & _mshr_request_T_3; // @[Scheduler.scala:107:{25,31}, :108:29] wire _mshr_request_T_5 = ~_mshrs_0_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32] wire _mshr_request_T_6 = _sourceB_io_req_ready \| _mshr_request_T_5; // @[Scheduler.scala:41:23, :109:{29,32}] wire _mshr_request_T_7 = _mshr_request_T_4 & _mshr_request_T_6; // @[Scheduler.scala:107:31, :108:61, :109:29] wire _mshr_request_T_8 = ~_mshrs_0_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32] wire _mshr_request_T_9 = _sourceC_io_req_ready \| _mshr_request_T_8; // @[Scheduler.scala:42:23, :110:{29,32}] wire _mshr_request_T_10 = _mshr_request_T_7 & _mshr_request_T_9; // @[Scheduler.scala:108:61, :109:61, :110:29] wire _mshr_request_T_11 = ~_mshrs_0_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32] wire _mshr_request_T_12 = _sourceD_io_req_ready \| _mshr_request_T_11; // @[Scheduler.scala:43:23, :111:{29,32}] wire _mshr_request_T_13 = _mshr_request_T_10 & _mshr_request_T_12; // @[Scheduler.scala:109:61, :110:61, :111:29] wire _mshr_request_T_14 = ~_mshrs_0_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32] wire _mshr_request_T_15 = _sourceE_io_req_ready \| _mshr_request_T_14; // @[Scheduler.scala:44:23, :112:{29,32}] wire _mshr_request_T_16 = _mshr_request_T_13 & _mshr_request_T_15; // @[Scheduler.scala:110:61, :111:61, :112:29] wire _mshr_request_T_17 = ~_mshrs_0_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32] wire _mshr_request_T_18 = _sourceX_io_req_ready \| _mshr_request_T_17; // @[Scheduler.scala:45:23, :113:{29,32}] wire _mshr_request_T_19 = _mshr_request_T_16 & _mshr_request_T_18; // @[Scheduler.scala:111:61, :112:61, :113:29] wire _mshr_request_T_20 = ~_mshrs_0_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36] wire _mshr_request_T_21 = _directory_io_write_ready \| _mshr_request_T_20; // @[Scheduler.scala:68:25, :114:{33,36}] wire _mshr_request_T_22 = _mshr_request_T_19 & _mshr_request_T_21; // @[Scheduler.scala:112:61, :113:61, :114:33] wire _mshr_request_T_23 = ~mshr_stall_abc_1; // @[Scheduler.scala:90:86, :107:28] wire _mshr_request_T_24 = _mshrs_1_io_schedule_valid & _mshr_request_T_23; // @[Scheduler.scala:71:46, :107:{25,28}] wire _mshr_request_T_25 = ~_mshrs_1_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32] wire _mshr_request_T_26 = _sourceA_io_req_ready \| _mshr_request_T_25; // @[Scheduler.scala:40:23, :108:{29,32}] wire _mshr_request_T_27 = _mshr_request_T_24 & _mshr_request_T_26; // @[Scheduler.scala:107:{25,31}, :108:29] wire _mshr_request_T_28 = ~_mshrs_1_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32] wire _mshr_request_T_29 = _sourceB_io_req_ready \| _mshr_request_T_28; // @[Scheduler.scala:41:23, :109:{29,32}] wire _mshr_request_T_30 = _mshr_request_T_27 & _mshr_request_T_29; // @[Scheduler.scala:107:31, :108:61, :109:29] wire _mshr_request_T_31 = ~_mshrs_1_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32] wire _mshr_request_T_32 = _sourceC_io_req_ready \| _mshr_request_T_31; // @[Scheduler.scala:42:23, :110:{29,32}] wire _mshr_request_T_33 = _mshr_request_T_30 & _mshr_request_T_32; // @[Scheduler.scala:108:61, :109:61, :110:29] wire _mshr_request_T_34 = ~_mshrs_1_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32] wire _mshr_request_T_35 = _sourceD_io_req_ready \| _mshr_request_T_34; // @[Scheduler.scala:43:23, :111:{29,32}] wire _mshr_request_T_36 = _mshr_request_T_33 & _mshr_request_T_35; // @[Scheduler.scala:109:61, :110:61, :111:29] wire _mshr_request_T_37 = ~_mshrs_1_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32] wire _mshr_request_T_38 = _sourceE_io_req_ready \| _mshr_request_T_37; // @[Scheduler.scala:44:23, :112:{29,32}] wire _mshr_request_T_39 = _mshr_request_T_36 & _mshr_request_T_38; // @[Scheduler.scala:110:61, :111:61, :112:29] wire _mshr_request_T_40 = ~_mshrs_1_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32] wire _mshr_request_T_41 = _sourceX_io_req_ready \| _mshr_request_T_40; // @[Scheduler.scala:45:23, :113:{29,32}] wire _mshr_request_T_42 = _mshr_request_T_39 & _mshr_request_T_41; // @[Scheduler.scala:111:61, :112:61, :113:29] wire _mshr_request_T_43 = ~_mshrs_1_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36] wire _mshr_request_T_44 = _directory_io_write_ready \| _mshr_request_T_43; // @[Scheduler.scala:68:25, :114:{33,36}] wire _mshr_request_T_45 = _mshr_request_T_42 & _mshr_request_T_44; // @[Scheduler.scala:112:61, :113:61, :114:33] wire _mshr_request_T_46 = ~mshr_stall_abc_2; // @[Scheduler.scala:90:86, :107:28] wire _mshr_request_T_47 = _mshrs_2_io_schedule_valid & _mshr_request_T_46; // @[Scheduler.scala:71:46, :107:{25,28}] wire _mshr_request_T_48 = ~_mshrs_2_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32] wire _mshr_request_T_49 = _sourceA_io_req_ready \| _mshr_request_T_48; // @[Scheduler.scala:40:23, :108:{29,32}] wire _mshr_request_T_50 = _mshr_request_T_47 & _mshr_request_T_49; // @[Scheduler.scala:107:{25,31}, :108:29] wire _mshr_request_T_51 = ~_mshrs_2_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32] wire _mshr_request_T_52 = _sourceB_io_req_ready \| _mshr_request_T_51; // @[Scheduler.scala:41:23, :109:{29,32}] wire _mshr_request_T_53 = _mshr_request_T_50 & _mshr_request_T_52; // @[Scheduler.scala:107:31, :108:61, :109:29] wire _mshr_request_T_54 = ~_mshrs_2_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32] wire _mshr_request_T_55 = _sourceC_io_req_ready \| _mshr_request_T_54; // @[Scheduler.scala:42:23, :110:{29,32}] wire _mshr_request_T_56 = _mshr_request_T_53 & _mshr_request_T_55; // @[Scheduler.scala:108:61, :109:61, :110:29] wire _mshr_request_T_57 = ~_mshrs_2_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32] wire _mshr_request_T_58 = _sourceD_io_req_ready \| _mshr_request_T_57; // @[Scheduler.scala:43:23, :111:{29,32}] wire _mshr_request_T_59 = _mshr_request_T_56 & _mshr_request_T_58; // @[Scheduler.scala:109:61, :110:61, :111:29] wire _mshr_request_T_60 = ~_mshrs_2_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32] wire _mshr_request_T_61 = _sourceE_io_req_ready \| _mshr_request_T_60; // @[Scheduler.scala:44:23, :112:{29,32}] wire _mshr_request_T_62 = _mshr_request_T_59 & _mshr_request_T_61; // @[Scheduler.scala:110:61, :111:61, :112:29] wire _mshr_request_T_63 = ~_mshrs_2_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32] wire _mshr_request_T_64 = _sourceX_io_req_ready \| _mshr_request_T_63; // @[Scheduler.scala:45:23, :113:{29,32}] wire _mshr_request_T_65 = _mshr_request_T_62 & _mshr_request_T_64; // @[Scheduler.scala:111:61, :112:61, :113:29] wire _mshr_request_T_66 = ~_mshrs_2_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36] wire _mshr_request_T_67 = _directory_io_write_ready \| _mshr_request_T_66; // @[Scheduler.scala:68:25, :114:{33,36}] wire _mshr_request_T_68 = _mshr_request_T_65 & _mshr_request_T_67; // @[Scheduler.scala:112:61, :113:61, :114:33] wire _mshr_request_T_69 = ~mshr_stall_abc_3; // @[Scheduler.scala:90:86, :107:28] wire _mshr_request_T_70 = _mshrs_3_io_schedule_valid & _mshr_request_T_69; // @[Scheduler.scala:71:46, :107:{25,28}] wire _mshr_request_T_71 = ~_mshrs_3_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32] wire _mshr_request_T_72 = _sourceA_io_req_ready \| _mshr_request_T_71; // @[Scheduler.scala:40:23, :108:{29,32}] wire _mshr_request_T_73 = _mshr_request_T_70 & _mshr_request_T_72; // @[Scheduler.scala:107:{25,31}, :108:29] wire _mshr_request_T_74 = ~_mshrs_3_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32] wire _mshr_request_T_75 = _sourceB_io_req_ready \| _mshr_request_T_74; // @[Scheduler.scala:41:23, :109:{29,32}] wire _mshr_request_T_76 = _mshr_request_T_73 & _mshr_request_T_75; // @[Scheduler.scala:107:31, :108:61, :109:29] wire _mshr_request_T_77 = ~_mshrs_3_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32] wire _mshr_request_T_78 = _sourceC_io_req_ready \| _mshr_request_T_77; // @[Scheduler.scala:42:23, :110:{29,32}] wire _mshr_request_T_79 = _mshr_request_T_76 & _mshr_request_T_78; // @[Scheduler.scala:108:61, :109:61, :110:29] wire _mshr_request_T_80 = ~_mshrs_3_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32] wire _mshr_request_T_81 = _sourceD_io_req_ready \| _mshr_request_T_80; // @[Scheduler.scala:43:23, :111:{29,32}] wire _mshr_request_T_82 = _mshr_request_T_79 & _mshr_request_T_81; // @[Scheduler.scala:109:61, :110:61, :111:29] wire _mshr_request_T_83 = ~_mshrs_3_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32] wire _mshr_request_T_84 = _sourceE_io_req_ready \| _mshr_request_T_83; // @[Scheduler.scala:44:23, :112:{29,32}] wire _mshr_request_T_85 = _mshr_request_T_82 & _mshr_request_T_84; // @[Scheduler.scala:110:61, :111:61, :112:29] wire _mshr_request_T_86 = ~_mshrs_3_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32] wire _mshr_request_T_87 = _sourceX_io_req_ready \| _mshr_request_T_86; // @[Scheduler.scala:45:23, :113:{29,32}] wire _mshr_request_T_88 = _mshr_request_T_85 & _mshr_request_T_87; // @[Scheduler.scala:111:61, :112:61, :113:29] wire _mshr_request_T_89 = ~_mshrs_3_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36] wire _mshr_request_T_90 = _directory_io_write_ready \| _mshr_request_T_89; // @[Scheduler.scala:68:25, :114:{33,36}] wire _mshr_request_T_91 = _mshr_request_T_88 & _mshr_request_T_90; // @[Scheduler.scala:112:61, :113:61, :114:33] wire _mshr_request_T_92 = ~mshr_stall_abc_4; // @[Scheduler.scala:90:86, :107:28] wire _mshr_request_T_93 = _mshrs_4_io_schedule_valid & _mshr_request_T_92; // @[Scheduler.scala:71:46, :107:{25,28}] wire _mshr_request_T_94 = ~_mshrs_4_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32] wire _mshr_request_T_95 = _sourceA_io_req_ready \| _mshr_request_T_94; // @[Scheduler.scala:40:23, :108:{29,32}] wire _mshr_request_T_96 = _mshr_request_T_93 & _mshr_request_T_95; // @[Scheduler.scala:107:{25,31}, :108:29] wire _mshr_request_T_97 = ~_mshrs_4_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32] wire _mshr_request_T_98 = _sourceB_io_req_ready \| _mshr_request_T_97; // @[Scheduler.scala:41:23, :109:{29,32}] wire _mshr_request_T_99 = _mshr_request_T_96 & _mshr_request_T_98; // @[Scheduler.scala:107:31, :108:61, :109:29] wire _mshr_request_T_100 = ~_mshrs_4_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32] wire _mshr_request_T_101 = _sourceC_io_req_ready \| _mshr_request_T_100; // @[Scheduler.scala:42:23, :110:{29,32}] wire _mshr_request_T_102 = _mshr_request_T_99 & _mshr_request_T_101; // @[Scheduler.scala:108:61, :109:61, :110:29] wire _mshr_request_T_103 = ~_mshrs_4_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32] wire _mshr_request_T_104 = _sourceD_io_req_ready \| _mshr_request_T_103; // @[Scheduler.scala:43:23, :111:{29,32}] wire _mshr_request_T_105 = _mshr_request_T_102 & _mshr_request_T_104; // @[Scheduler.scala:109:61, :110:61, :111:29] wire _mshr_request_T_106 = ~_mshrs_4_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32] wire _mshr_request_T_107 = _sourceE_io_req_ready \| _mshr_request_T_106; // @[Scheduler.scala:44:23, :112:{29,32}] wire _mshr_request_T_108 = _mshr_request_T_105 & _mshr_request_T_107; // @[Scheduler.scala:110:61, :111:61, :112:29] wire _mshr_request_T_109 = ~_mshrs_4_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32] wire _mshr_request_T_110 = _sourceX_io_req_ready \| _mshr_request_T_109; // @[Scheduler.scala:45:23, :113:{29,32}] wire _mshr_request_T_111 = _mshr_request_T_108 & _mshr_request_T_110; // @[Scheduler.scala:111:61, :112:61, :113:29] wire _mshr_request_T_112 = ~_mshrs_4_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36] wire _mshr_request_T_113 = _directory_io_write_ready \| _mshr_request_T_112; // @[Scheduler.scala:68:25, :114:{33,36}] wire _mshr_request_T_114 = _mshr_request_T_111 & _mshr_request_T_113; // @[Scheduler.scala:112:61, :113:61, :114:33] wire _mshr_request_T_115 = ~mshr_stall_abc_5; // @[Scheduler.scala:90:86, :107:28] wire _mshr_request_T_116 = _mshrs_5_io_schedule_valid & _mshr_request_T_115; // @[Scheduler.scala:71:46, :107:{25,28}] wire _mshr_request_T_117 = ~_mshrs_5_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32] wire _mshr_request_T_118 = _sourceA_io_req_ready \| _mshr_request_T_117; // @[Scheduler.scala:40:23, :108:{29,32}] wire _mshr_request_T_119 = _mshr_request_T_116 & _mshr_request_T_118; // @[Scheduler.scala:107:{25,31}, :108:29] wire _mshr_request_T_120 = ~_mshrs_5_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32] wire _mshr_request_T_121 = _sourceB_io_req_ready \| _mshr_request_T_120; // @[Scheduler.scala:41:23, :109:{29,32}] wire _mshr_request_T_122 = _mshr_request_T_119 & _mshr_request_T_121; // @[Scheduler.scala:107:31, :108:61, :109:29] wire _mshr_request_T_123 = ~_mshrs_5_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32] wire _mshr_request_T_124 = _sourceC_io_req_ready \| _mshr_request_T_123; // @[Scheduler.scala:42:23, :110:{29,32}] wire _mshr_request_T_125 = _mshr_request_T_122 & _mshr_request_T_124; // @[Scheduler.scala:108:61, :109:61, :110:29] wire _mshr_request_T_126 = ~_mshrs_5_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32] wire _mshr_request_T_127 = _sourceD_io_req_ready \| _mshr_request_T_126; // @[Scheduler.scala:43:23, :111:{29,32}] wire _mshr_request_T_128 = _mshr_request_T_125 & _mshr_request_T_127; // @[Scheduler.scala:109:61, :110:61, :111:29] wire _mshr_request_T_129 = ~_mshrs_5_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32] wire _mshr_request_T_130 = _sourceE_io_req_ready \| _mshr_request_T_129; // @[Scheduler.scala:44:23, :112:{29,32}] wire _mshr_request_T_131 = _mshr_request_T_128 & _mshr_request_T_130; // @[Scheduler.scala:110:61, :111:61, :112:29] wire _mshr_request_T_132 = ~_mshrs_5_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32] wire _mshr_request_T_133 = _sourceX_io_req_ready \| _mshr_request_T_132; // @[Scheduler.scala:45:23, :113:{29,32}] wire _mshr_request_T_134 = _mshr_request_T_131 & _mshr_request_T_133; // @[Scheduler.scala:111:61, :112:61, :113:29] wire _mshr_request_T_135 = ~_mshrs_5_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36] wire _mshr_request_T_136 = _directory_io_write_ready \| _mshr_request_T_135; // @[Scheduler.scala:68:25, :114:{33,36}] wire _mshr_request_T_137 = _mshr_request_T_134 & _mshr_request_T_136; // @[Scheduler.scala:112:61, :113:61, :114:33] wire _mshr_request_T_138 = ~mshr_stall_abc_6; // @[Scheduler.scala:90:86, :107:28] wire _mshr_request_T_139 = _mshrs_6_io_schedule_valid & _mshr_request_T_138; // @[Scheduler.scala:71:46, :107:{25,28}] wire _mshr_request_T_140 = ~_mshrs_6_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32] wire _mshr_request_T_141 = _sourceA_io_req_ready \| _mshr_request_T_140; // @[Scheduler.scala:40:23, :108:{29,32}] wire _mshr_request_T_142 = _mshr_request_T_139 & _mshr_request_T_141; // @[Scheduler.scala:107:{25,31}, :108:29] wire _mshr_request_T_143 = ~_mshrs_6_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32] wire _mshr_request_T_144 = _sourceB_io_req_ready \| _mshr_request_T_143; // @[Scheduler.scala:41:23, :109:{29,32}] wire _mshr_request_T_145 = _mshr_request_T_142 & _mshr_request_T_144; // @[Scheduler.scala:107:31, :108:61, :109:29] wire _mshr_request_T_146 = ~_mshrs_6_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32] wire _mshr_request_T_147 = _sourceC_io_req_ready \| _mshr_request_T_146; // @[Scheduler.scala:42:23, :110:{29,32}] wire _mshr_request_T_148 = _mshr_request_T_145 & _mshr_request_T_147; // @[Scheduler.scala:108:61, :109:61, :110:29] wire _mshr_request_T_149 = ~_mshrs_6_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32] wire _mshr_request_T_150 = _sourceD_io_req_ready \| _mshr_request_T_149; // @[Scheduler.scala:43:23, :111:{29,32}] wire _mshr_request_T_151 = _mshr_request_T_148 & _mshr_request_T_150; // @[Scheduler.scala:109:61, :110:61, :111:29] wire _mshr_request_T_152 = ~_mshrs_6_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32] wire _mshr_request_T_153 = _sourceE_io_req_ready \| _mshr_request_T_152; // @[Scheduler.scala:44:23, :112:{29,32}] wire _mshr_request_T_154 = _mshr_request_T_151 & _mshr_request_T_153; // @[Scheduler.scala:110:61, :111:61, :112:29] wire _mshr_request_T_155 = ~_mshrs_6_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32] wire _mshr_request_T_156 = _sourceX_io_req_ready \| _mshr_request_T_155; // @[Scheduler.scala:45:23, :113:{29,32}] wire _mshr_request_T_157 = _mshr_request_T_154 & _mshr_request_T_156; // @[Scheduler.scala:111:61, :112:61, :113:29] wire _mshr_request_T_158 = ~_mshrs_6_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36] wire _mshr_request_T_159 = _directory_io_write_ready \| _mshr_request_T_158; // @[Scheduler.scala:68:25, :114:{33,36}] wire _mshr_request_T_160 = _mshr_request_T_157 & _mshr_request_T_159; // @[Scheduler.scala:112:61, :113:61, :114:33] wire _mshr_request_T_161 = ~mshr_stall_abc_7; // @[Scheduler.scala:90:86, :107:28] wire _mshr_request_T_162 = _mshrs_7_io_schedule_valid & _mshr_request_T_161; // @[Scheduler.scala:71:46, :107:{25,28}] wire _mshr_request_T_163 = ~_mshrs_7_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32] wire _mshr_request_T_164 = _sourceA_io_req_ready \| _mshr_request_T_163; // @[Scheduler.scala:40:23, :108:{29,32}] wire _mshr_request_T_165 = _mshr_request_T_162 & _mshr_request_T_164; // @[Scheduler.scala:107:{25,31}, :108:29] wire _mshr_request_T_166 = ~_mshrs_7_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32] wire _mshr_request_T_167 = _sourceB_io_req_ready \| _mshr_request_T_166; // @[Scheduler.scala:41:23, :109:{29,32}] wire _mshr_request_T_168 = _mshr_request_T_165 & _mshr_request_T_167; // @[Scheduler.scala:107:31, :108:61, :109:29] wire _mshr_request_T_169 = ~_mshrs_7_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32] wire _mshr_request_T_170 = _sourceC_io_req_ready \| _mshr_request_T_169; // @[Scheduler.scala:42:23, :110:{29,32}] wire _mshr_request_T_171 = _mshr_request_T_168 & _mshr_request_T_170; // @[Scheduler.scala:108:61, :109:61, :110:29] wire _mshr_request_T_172 = ~_mshrs_7_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32] wire _mshr_request_T_173 = _sourceD_io_req_ready \| _mshr_request_T_172; // @[Scheduler.scala:43:23, :111:{29,32}] wire _mshr_request_T_174 = _mshr_request_T_171 & _mshr_request_T_173; // @[Scheduler.scala:109:61, :110:61, :111:29] wire _mshr_request_T_175 = ~_mshrs_7_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32] wire _mshr_request_T_176 = _sourceE_io_req_ready \| _mshr_request_T_175; // @[Scheduler.scala:44:23, :112:{29,32}] wire _mshr_request_T_177 = _mshr_request_T_174 & _mshr_request_T_176; // @[Scheduler.scala:110:61, :111:61, :112:29] wire _mshr_request_T_178 = ~_mshrs_7_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32] wire _mshr_request_T_179 = _sourceX_io_req_ready \| _mshr_request_T_178; // @[Scheduler.scala:45:23, :113:{29,32}] wire _mshr_request_T_180 = _mshr_request_T_177 & _mshr_request_T_179; // @[Scheduler.scala:111:61, :112:61, :113:29] wire _mshr_request_T_181 = ~_mshrs_7_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36] wire _mshr_request_T_182 = _directory_io_write_ready \| _mshr_request_T_181; // @[Scheduler.scala:68:25, :114:{33,36}] wire _mshr_request_T_183 = _mshr_request_T_180 & _mshr_request_T_182; // @[Scheduler.scala:112:61, :113:61, :114:33] wire _mshr_request_T_184 = ~mshr_stall_abc_8; // @[Scheduler.scala:90:86, :107:28] wire _mshr_request_T_185 = _mshrs_8_io_schedule_valid & _mshr_request_T_184; // @[Scheduler.scala:71:46, :107:{25,28}] wire _mshr_request_T_186 = ~_mshrs_8_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32] wire _mshr_request_T_187 = _sourceA_io_req_ready \| _mshr_request_T_186; // @[Scheduler.scala:40:23, :108:{29,32}] wire _mshr_request_T_188 = _mshr_request_T_185 & _mshr_request_T_187; // @[Scheduler.scala:107:{25,31}, :108:29] wire _mshr_request_T_189 = ~_mshrs_8_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32] wire _mshr_request_T_190 = _sourceB_io_req_ready \| _mshr_request_T_189; // @[Scheduler.scala:41:23, :109:{29,32}] wire _mshr_request_T_191 = _mshr_request_T_188 & _mshr_request_T_190; // @[Scheduler.scala:107:31, :108:61, :109:29] wire _mshr_request_T_192 = ~_mshrs_8_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32] wire _mshr_request_T_193 = _sourceC_io_req_ready \| _mshr_request_T_192; // @[Scheduler.scala:42:23, :110:{29,32}] wire _mshr_request_T_194 = _mshr_request_T_191 & _mshr_request_T_193; // @[Scheduler.scala:108:61, :109:61, :110:29] wire _mshr_request_T_195 = ~_mshrs_8_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32] wire _mshr_request_T_196 = _sourceD_io_req_ready \| _mshr_request_T_195; // @[Scheduler.scala:43:23, :111:{29,32}] wire _mshr_request_T_197 = _mshr_request_T_194 & _mshr_request_T_196; // @[Scheduler.scala:109:61, :110:61, :111:29] wire _mshr_request_T_198 = ~_mshrs_8_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32] wire _mshr_request_T_199 = _sourceE_io_req_ready \| _mshr_request_T_198; // @[Scheduler.scala:44:23, :112:{29,32}] wire _mshr_request_T_200 = _mshr_request_T_197 & _mshr_request_T_199; // @[Scheduler.scala:110:61, :111:61, :112:29] wire _mshr_request_T_201 = ~_mshrs_8_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32] wire _mshr_request_T_202 = _sourceX_io_req_ready \| _mshr_request_T_201; // @[Scheduler.scala:45:23, :113:{29,32}] wire _mshr_request_T_203 = _mshr_request_T_200 & _mshr_request_T_202; // @[Scheduler.scala:111:61, :112:61, :113:29] wire _mshr_request_T_204 = ~_mshrs_8_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36] wire _mshr_request_T_205 = _directory_io_write_ready \| _mshr_request_T_204; // @[Scheduler.scala:68:25, :114:{33,36}] wire _mshr_request_T_206 = _mshr_request_T_203 & _mshr_request_T_205; // @[Scheduler.scala:112:61, :113:61, :114:33] wire _mshr_request_T_207 = ~mshr_stall_abc_9; // @[Scheduler.scala:90:86, :107:28] wire _mshr_request_T_208 = _mshrs_9_io_schedule_valid & _mshr_request_T_207; // @[Scheduler.scala:71:46, :107:{25,28}] wire _mshr_request_T_209 = ~_mshrs_9_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32] wire _mshr_request_T_210 = _sourceA_io_req_ready \| _mshr_request_T_209; // @[Scheduler.scala:40:23, :108:{29,32}] wire _mshr_request_T_211 = _mshr_request_T_208 & _mshr_request_T_210; // @[Scheduler.scala:107:{25,31}, :108:29] wire _mshr_request_T_212 = ~_mshrs_9_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32] wire _mshr_request_T_213 = _sourceB_io_req_ready \| _mshr_request_T_212; // @[Scheduler.scala:41:23, :109:{29,32}] wire _mshr_request_T_214 = _mshr_request_T_211 & _mshr_request_T_213; // @[Scheduler.scala:107:31, :108:61, :109:29] wire _mshr_request_T_215 = ~_mshrs_9_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32] wire _mshr_request_T_216 = _sourceC_io_req_ready \| _mshr_request_T_215; // @[Scheduler.scala:42:23, :110:{29,32}] wire _mshr_request_T_217 = _mshr_request_T_214 & _mshr_request_T_216; // @[Scheduler.scala:108:61, :109:61, :110:29] wire _mshr_request_T_218 = ~_mshrs_9_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32] wire _mshr_request_T_219 = _sourceD_io_req_ready \| _mshr_request_T_218; // @[Scheduler.scala:43:23, :111:{29,32}] wire _mshr_request_T_220 = _mshr_request_T_217 & _mshr_request_T_219; // @[Scheduler.scala:109:61, :110:61, :111:29] wire _mshr_request_T_221 = ~_mshrs_9_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32] wire _mshr_request_T_222 = _sourceE_io_req_ready \| _mshr_request_T_221; // @[Scheduler.scala:44:23, :112:{29,32}] wire _mshr_request_T_223 = _mshr_request_T_220 & _mshr_request_T_222; // @[Scheduler.scala:110:61, :111:61, :112:29] wire _mshr_request_T_224 = ~_mshrs_9_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32] wire _mshr_request_T_225 = _sourceX_io_req_ready \| _mshr_request_T_224; // @[Scheduler.scala:45:23, :113:{29,32}] wire _mshr_request_T_226 = _mshr_request_T_223 & _mshr_request_T_225; // @[Scheduler.scala:111:61, :112:61, :113:29] wire _mshr_request_T_227 = ~_mshrs_9_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36] wire _mshr_request_T_228 = _directory_io_write_ready \| _mshr_request_T_227; // @[Scheduler.scala:68:25, :114:{33,36}] wire _mshr_request_T_229 = _mshr_request_T_226 & _mshr_request_T_228; // @[Scheduler.scala:112:61, :113:61, :114:33] wire _mshr_request_T_230 = ~mshr_stall_bc; // @[Scheduler.scala:94:28, :107:28] wire _mshr_request_T_231 = _mshrs_10_io_schedule_valid & _mshr_request_T_230; // @[Scheduler.scala:71:46, :107:{25,28}] wire _mshr_request_T_232 = ~_mshrs_10_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32] wire _mshr_request_T_233 = _sourceA_io_req_ready \| _mshr_request_T_232; // @[Scheduler.scala:40:23, :108:{29,32}] wire _mshr_request_T_234 = _mshr_request_T_231 & _mshr_request_T_233; // @[Scheduler.scala:107:{25,31}, :108:29] wire _mshr_request_T_235 = ~_mshrs_10_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32] wire _mshr_request_T_236 = _sourceB_io_req_ready \| _mshr_request_T_235; // @[Scheduler.scala:41:23, :109:{29,32}] wire _mshr_request_T_237 = _mshr_request_T_234 & _mshr_request_T_236; // @[Scheduler.scala:107:31, :108:61, :109:29] wire _mshr_request_T_238 = ~_mshrs_10_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32] wire _mshr_request_T_239 = _sourceC_io_req_ready \| _mshr_request_T_238; // @[Scheduler.scala:42:23, :110:{29,32}] wire _mshr_request_T_240 = _mshr_request_T_237 & _mshr_request_T_239; // @[Scheduler.scala:108:61, :109:61, :110:29] wire _mshr_request_T_241 = ~_mshrs_10_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32] wire _mshr_request_T_242 = _sourceD_io_req_ready \| _mshr_request_T_241; // @[Scheduler.scala:43:23, :111:{29,32}] wire _mshr_request_T_243 = _mshr_request_T_240 & _mshr_request_T_242; // @[Scheduler.scala:109:61, :110:61, :111:29] wire _mshr_request_T_244 = ~_mshrs_10_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32] wire _mshr_request_T_245 = _sourceE_io_req_ready \| _mshr_request_T_244; // @[Scheduler.scala:44:23, :112:{29,32}] wire _mshr_request_T_246 = _mshr_request_T_243 & _mshr_request_T_245; // @[Scheduler.scala:110:61, :111:61, :112:29] wire _mshr_request_T_247 = ~_mshrs_10_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32] wire _mshr_request_T_248 = _sourceX_io_req_ready \| _mshr_request_T_247; // @[Scheduler.scala:45:23, :113:{29,32}] wire _mshr_request_T_249 = _mshr_request_T_246 & _mshr_request_T_248; // @[Scheduler.scala:111:61, :112:61, :113:29] wire _mshr_request_T_250 = ~_mshrs_10_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36] wire _mshr_request_T_251 = _directory_io_write_ready \| _mshr_request_T_250; // @[Scheduler.scala:68:25, :114:{33,36}] wire _mshr_request_T_252 = _mshr_request_T_249 & _mshr_request_T_251; // @[Scheduler.scala:112:61, :113:61, :114:33] wire _mshr_request_T_255 = ~_mshrs_11_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32] wire _mshr_request_T_256 = _sourceA_io_req_ready \| _mshr_request_T_255; // @[Scheduler.scala:40:23, :108:{29,32}] wire _mshr_request_T_254; // @[Scheduler.scala:107:25] wire _mshr_request_T_257 = _mshr_request_T_254 & _mshr_request_T_256; // @[Scheduler.scala:107:{25,31}, :108:29] wire _mshr_request_T_258 = ~_mshrs_11_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32] wire _mshr_request_T_259 = _sourceB_io_req_ready \| _mshr_request_T_258; // @[Scheduler.scala:41:23, :109:{29,32}] wire _mshr_request_T_260 = _mshr_request_T_257 & _mshr_request_T_259; // @[Scheduler.scala:107:31, :108:61, :109:29] wire _mshr_request_T_261 = ~_mshrs_11_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32] wire _mshr_request_T_262 = _sourceC_io_req_ready \| _mshr_request_T_261; // @[Scheduler.scala:42:23, :110:{29,32}] wire _mshr_request_T_263 = _mshr_request_T_260 & _mshr_request_T_262; // @[Scheduler.scala:108:61, :109:61, :110:29] wire _mshr_request_T_264 = ~_mshrs_11_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32] wire _mshr_request_T_265 = _sourceD_io_req_ready \| _mshr_request_T_264; // @[Scheduler.scala:43:23, :111:{29,32}] wire _mshr_request_T_266 = _mshr_request_T_263 & _mshr_request_T_265; // @[Scheduler.scala:109:61, :110:61, :111:29] wire _mshr_request_T_267 = ~_mshrs_11_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32] wire _mshr_request_T_268 = _sourceE_io_req_ready \| _mshr_request_T_267; // @[Scheduler.scala:44:23, :112:{29,32}] wire _mshr_request_T_269 = _mshr_request_T_266 & _mshr_request_T_268; // @[Scheduler.scala:110:61, :111:61, :112:29] wire _mshr_request_T_270 = ~_mshrs_11_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32] wire _mshr_request_T_271 = _sourceX_io_req_ready \| _mshr_request_T_270; // @[Scheduler.scala:45:23, :113:{29,32}] wire _mshr_request_T_272 = _mshr_request_T_269 & _mshr_request_T_271; // @[Scheduler.scala:111:61, :112:61, :113:29] wire _mshr_request_T_273 = ~_mshrs_11_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36] wire _mshr_request_T_274 = _directory_io_write_ready \| _mshr_request_T_273; // @[Scheduler.scala:68:25, :114:{33,36}] wire _mshr_request_T_275 = _mshr_request_T_272 & _mshr_request_T_274; // @[Scheduler.scala:112:61, :113:61, :114:33] wire [1:0] mshr_request_lo_lo_hi = {_mshr_request_T_68, _mshr_request_T_45}; // @[Scheduler.scala:106:25, :113:61] wire [2:0] mshr_request_lo_lo = {mshr_request_lo_lo_hi, _mshr_request_T_22}; // @[Scheduler.scala:106:25, :113:61] wire [1:0] mshr_request_lo_hi_hi = {_mshr_request_T_137, _mshr_request_T_114}; // @[Scheduler.scala:106:25, :113:61] wire [2:0] mshr_request_lo_hi = {mshr_request_lo_hi_hi, _mshr_request_T_91}; // @[Scheduler.scala:106:25, :113:61] wire [5:0] mshr_request_lo = {mshr_request_lo_hi, mshr_request_lo_lo}; // @[Scheduler.scala:106:25] wire [1:0] mshr_request_hi_lo_hi = {_mshr_request_T_206, _mshr_request_T_183}; // @[Scheduler.scala:106:25, :113:61] wire [2:0] mshr_request_hi_lo = {mshr_request_hi_lo_hi, _mshr_request_T_160}; // @[Scheduler.scala:106:25, :113:61] wire [1:0] mshr_request_hi_hi_hi = {_mshr_request_T_275, _mshr_request_T_252}; // @[Scheduler.scala:106:25, :113:61] wire [2:0] mshr_request_hi_hi = {mshr_request_hi_hi_hi, _mshr_request_T_229}; // @[Scheduler.scala:106:25, :113:61] wire [5:0] mshr_request_hi = {mshr_request_hi_hi, mshr_request_hi_lo}; // @[Scheduler.scala:106:25] wire [11:0] mshr_request = {mshr_request_hi, mshr_request_lo}; // @[Scheduler.scala:106:25] reg [11:0] robin_filter; // @[Scheduler.scala:118:29] wire [11:0] _robin_request_T = mshr_request & robin_filter; // @[Scheduler.scala:106:25, :118:29, :119:54] wire [23:0] robin_request = {mshr_request, _robin_request_T}; // @[Scheduler.scala:106:25, :119:{26,54}] wire [24:0] _mshr_selectOH2_T = {robin_request, 1'h0}; // @[package.scala:253:48] wire [23:0] _mshr_selectOH2_T_1 = _mshr_selectOH2_T[23:0]; // @[package.scala:253:{48,53}] wire [23:0] _mshr_selectOH2_T_2 = robin_request \| _mshr_selectOH2_T_1; // @[package.scala:253:{43,53}] wire [25:0] _mshr_selectOH2_T_3 = {_mshr_selectOH2_T_2, 2'h0}; // @[package.scala:253:{43,48}] wire [23:0] _mshr_selectOH2_T_4 = _mshr_selectOH2_T_3[23:0]; // @[package.scala:253:{48,53}] wire [23:0] _mshr_selectOH2_T_5 = _mshr_selectOH2_T_2 \| _mshr_selectOH2_T_4; // @[package.scala:253:{43,53}] wire [27:0] _mshr_selectOH2_T_6 = {_mshr_selectOH2_T_5, 4'h0}; // @[package.scala:253:{43,48}] wire [23:0] _mshr_selectOH2_T_7 = _mshr_selectOH2_T_6[23:0]; // @[package.scala:253:{48,53}] wire [23:0] _mshr_selectOH2_T_8 = _mshr_selectOH2_T_5 \| _mshr_selectOH2_T_7; // @[package.scala:253:{43,53}] wire [31:0] _mshr_selectOH2_T_9 = {_mshr_selectOH2_T_8, 8'h0}; // @[package.scala:253:{43,48}] wire [23:0] _mshr_selectOH2_T_10 = _mshr_selectOH2_T_9[23:0]; // @[package.scala:253:{48,53}] wire [23:0] _mshr_selectOH2_T_11 = _mshr_selectOH2_T_8 \| _mshr_selectOH2_T_10; // @[package.scala:253:{43,53}] wire [39:0] _mshr_selectOH2_T_12 = {_mshr_selectOH2_T_11, 16'h0}; // @[package.scala:253:{43,48}] wire [23:0] _mshr_selectOH2_T_13 = _mshr_selectOH2_T_12[23:0]; // @[package.scala:253:{48,53}] wire [23:0] _mshr_selectOH2_T_14 = _mshr_selectOH2_T_11 \| _mshr_selectOH2_T_13; // @[package.scala:253:{43,53}] wire [23:0] _mshr_selectOH2_T_15 = _mshr_selectOH2_T_14; // @[package.scala:253:43, :254:17] wire [24:0] _mshr_selectOH2_T_16 = {_mshr_selectOH2_T_15, 1'h0}; // @[package.scala:254:17] wire [24:0] _mshr_selectOH2_T_17 = ~_mshr_selectOH2_T_16; // @[Scheduler.scala:120:{24,48}] wire [24:0] mshr_selectOH2 = {1'h0, _mshr_selectOH2_T_17[23:0] & robin_request}; // @[Scheduler.scala:119:26, :120:{24,54}] wire [11:0] _mshr_selectOH_T = mshr_selectOH2[23:12]; // @[Scheduler.scala:120:54, :121:37] wire [11:0] _mshr_selectOH_T_1 = mshr_selectOH2[11:0]; // @[Scheduler.scala:120:54, :121:86] wire [11:0] mshr_selectOH = _mshr_selectOH_T \| _mshr_selectOH_T_1; // @[Scheduler.scala:121:{37,70,86}] wire [3:0] mshr_select_hi = mshr_selectOH[11:8]; // @[OneHot.scala:30:18] wire [7:0] mshr_select_lo = mshr_selectOH[7:0]; // @[OneHot.scala:31:18] wire _mshr_select_T = \|mshr_select_hi; // @[OneHot.scala:30:18, :32:14] wire [7:0] _mshr_select_T_1 = {4'h0, mshr_select_hi} \| mshr_select_lo; // @[OneHot.scala:30:18, :31:18, :32:28] wire [3:0] mshr_select_hi_1 = _mshr_select_T_1[7:4]; // @[OneHot.scala:30:18, :32:28] wire [3:0] mshr_select_lo_1 = _mshr_select_T_1[3:0]; // @[OneHot.scala:31:18, :32:28] wire _mshr_select_T_2 = \|mshr_select_hi_1; // @[OneHot.scala:30:18, :32:14] wire [3:0] _mshr_select_T_3 = mshr_select_hi_1 \| mshr_select_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] mshr_select_hi_2 = _mshr_select_T_3[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] mshr_select_lo_2 = _mshr_select_T_3[1:0]; // @[OneHot.scala:31:18, :32:28] wire _mshr_select_T_4 = \|mshr_select_hi_2; // @[OneHot.scala:30:18, :32:14] wire [1:0] _mshr_select_T_5 = mshr_select_hi_2 \| mshr_select_lo_2; // @[OneHot.scala:30:18, :31:18, :32:28] wire _mshr_select_T_6 = _mshr_select_T_5[1]; // @[OneHot.scala:32:28] wire [1:0] _mshr_select_T_7 = {_mshr_select_T_4, _mshr_select_T_6}; // @[OneHot.scala:32:{10,14}] wire [2:0] _mshr_select_T_8 = {_mshr_select_T_2, _mshr_select_T_7}; // @[OneHot.scala:32:{10,14}] wire [3:0] mshr_select = {_mshr_select_T, _mshr_select_T_8}; // @[OneHot.scala:32:{10,14}] wire [3:0] schedule_a_bits_source = mshr_select; // @[OneHot.scala:32:10] wire [3:0] schedule_d_bits_sink = mshr_select; // @[OneHot.scala:32:10] wire _schedule_T = mshr_selectOH[0]; // @[Mux.scala:32:36] wire _scheduleTag_T = mshr_selectOH[0]; // @[Mux.scala:32:36] wire _scheduleSet_T = mshr_selectOH[0]; // @[Mux.scala:32:36] wire sel = mshr_selectOH[0]; // @[Mux.scala:32:36] wire _schedule_T_1 = mshr_selectOH[1]; // @[Mux.scala:32:36] wire _scheduleTag_T_1 = mshr_selectOH[1]; // @[Mux.scala:32:36] wire _scheduleSet_T_1 = mshr_selectOH[1]; // @[Mux.scala:32:36] wire sel_1 = mshr_selectOH[1]; // @[Mux.scala:32:36] wire _schedule_T_2 = mshr_selectOH[2]; // @[Mux.scala:32:36] wire _scheduleTag_T_2 = mshr_selectOH[2]; // @[Mux.scala:32:36] wire _scheduleSet_T_2 = mshr_selectOH[2]; // @[Mux.scala:32:36] wire sel_2 = mshr_selectOH[2]; // @[Mux.scala:32:36] wire _schedule_T_3 = mshr_selectOH[3]; // @[Mux.scala:32:36] wire _scheduleTag_T_3 = mshr_selectOH[3]; // @[Mux.scala:32:36] wire _scheduleSet_T_3 = mshr_selectOH[3]; // @[Mux.scala:32:36] wire sel_3 = mshr_selectOH[3]; // @[Mux.scala:32:36] wire _schedule_T_4 = mshr_selectOH[4]; // @[Mux.scala:32:36] wire _scheduleTag_T_4 = mshr_selectOH[4]; // @[Mux.scala:32:36] wire _scheduleSet_T_4 = mshr_selectOH[4]; // @[Mux.scala:32:36] wire sel_4 = mshr_selectOH[4]; // @[Mux.scala:32:36] wire _schedule_T_5 = mshr_selectOH[5]; // @[Mux.scala:32:36] wire _scheduleTag_T_5 = mshr_selectOH[5]; // @[Mux.scala:32:36] wire _scheduleSet_T_5 = mshr_selectOH[5]; // @[Mux.scala:32:36] wire sel_5 = mshr_selectOH[5]; // @[Mux.scala:32:36] wire _schedule_T_6 = mshr_selectOH[6]; // @[Mux.scala:32:36] wire _scheduleTag_T_6 = mshr_selectOH[6]; // @[Mux.scala:32:36] wire _scheduleSet_T_6 = mshr_selectOH[6]; // @[Mux.scala:32:36] wire sel_6 = mshr_selectOH[6]; // @[Mux.scala:32:36] wire _schedule_T_7 = mshr_selectOH[7]; // @[Mux.scala:32:36] wire _scheduleTag_T_7 = mshr_selectOH[7]; // @[Mux.scala:32:36] wire _scheduleSet_T_7 = mshr_selectOH[7]; // @[Mux.scala:32:36] wire sel_7 = mshr_selectOH[7]; // @[Mux.scala:32:36] wire _schedule_T_8 = mshr_selectOH[8]; // @[Mux.scala:32:36] wire _scheduleTag_T_8 = mshr_selectOH[8]; // @[Mux.scala:32:36] wire _scheduleSet_T_8 = mshr_selectOH[8]; // @[Mux.scala:32:36] wire sel_8 = mshr_selectOH[8]; // @[Mux.scala:32:36] wire _schedule_T_9 = mshr_selectOH[9]; // @[Mux.scala:32:36] wire _scheduleTag_T_9 = mshr_selectOH[9]; // @[Mux.scala:32:36] wire _scheduleSet_T_9 = mshr_selectOH[9]; // @[Mux.scala:32:36] wire sel_9 = mshr_selectOH[9]; // @[Mux.scala:32:36] wire _schedule_T_10 = mshr_selectOH[10]; // @[Mux.scala:32:36] wire _scheduleTag_T_10 = mshr_selectOH[10]; // @[Mux.scala:32:36] wire _scheduleSet_T_10 = mshr_selectOH[10]; // @[Mux.scala:32:36] wire select_bc = mshr_selectOH[10]; // @[Mux.scala:32:36] wire sel_10 = mshr_selectOH[10]; // @[Mux.scala:32:36] wire _schedule_T_11 = mshr_selectOH[11]; // @[Mux.scala:32:36] wire _scheduleTag_T_11 = mshr_selectOH[11]; // @[Mux.scala:32:36] wire _scheduleSet_T_11 = mshr_selectOH[11]; // @[Mux.scala:32:36] wire select_c = mshr_selectOH[11]; // @[Mux.scala:32:36] wire sel_11 = mshr_selectOH[11]; // @[Mux.scala:32:36] wire _schedule_WIRE_55_valid; // @[Mux.scala:30:73] wire [8:0] _schedule_WIRE_55_bits_tag; // @[Mux.scala:30:73] wire [10:0] _schedule_WIRE_55_bits_set; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_55_bits_param; // @[Mux.scala:30:73] wire _schedule_WIRE_55_bits_block; // @[Mux.scala:30:73] wire _schedule_WIRE_48_valid; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_48_bits_param; // @[Mux.scala:30:73] wire [8:0] _schedule_WIRE_48_bits_tag; // @[Mux.scala:30:73] wire [10:0] _schedule_WIRE_48_bits_set; // @[Mux.scala:30:73] wire _schedule_WIRE_48_bits_clients; // @[Mux.scala:30:73] wire _schedule_WIRE_38_valid; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_38_bits_opcode; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_38_bits_param; // @[Mux.scala:30:73] wire [3:0] _schedule_c_bits_source_T_1; // @[Scheduler.scala:132:32] wire [8:0] _schedule_WIRE_38_bits_tag; // @[Mux.scala:30:73] wire [10:0] _schedule_WIRE_38_bits_set; // @[Mux.scala:30:73] wire [3:0] _schedule_WIRE_38_bits_way; // @[Mux.scala:30:73] wire _schedule_WIRE_38_bits_dirty; // @[Mux.scala:30:73] wire _schedule_WIRE_19_valid; // @[Mux.scala:30:73] wire _schedule_WIRE_19_bits_prio_0; // @[Mux.scala:30:73] wire _schedule_WIRE_19_bits_prio_1; // @[Mux.scala:30:73] wire _schedule_WIRE_19_bits_prio_2; // @[Mux.scala:30:73] wire _schedule_WIRE_19_bits_control; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_19_bits_opcode; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_19_bits_param; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_19_bits_size; // @[Mux.scala:30:73] wire [5:0] _schedule_WIRE_19_bits_source; // @[Mux.scala:30:73] wire [8:0] _schedule_WIRE_19_bits_tag; // @[Mux.scala:30:73] wire [5:0] _schedule_WIRE_19_bits_offset; // @[Mux.scala:30:73] wire [5:0] _schedule_WIRE_19_bits_put; // @[Mux.scala:30:73] wire [10:0] _schedule_WIRE_19_bits_set; // @[Mux.scala:30:73] wire [3:0] _schedule_WIRE_19_bits_way; // @[Mux.scala:30:73] wire _schedule_WIRE_19_bits_bad; // @[Mux.scala:30:73] wire _schedule_WIRE_15_valid; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_15_bits_sink; // @[Mux.scala:30:73] wire _schedule_WIRE_11_valid; // @[Mux.scala:30:73] wire _schedule_WIRE_1_valid; // @[Mux.scala:30:73] wire [10:0] _schedule_WIRE_1_bits_set; // @[Mux.scala:30:73] wire [3:0] _schedule_WIRE_1_bits_way; // @[Mux.scala:30:73] wire _schedule_WIRE_1_bits_data_dirty; // @[Mux.scala:30:73] wire [1:0] _schedule_WIRE_1_bits_data_state; // @[Mux.scala:30:73] wire _schedule_WIRE_1_bits_data_clients; // @[Mux.scala:30:73] wire [8:0] _schedule_WIRE_1_bits_data_tag; // @[Mux.scala:30:73] wire _schedule_WIRE; // @[Mux.scala:30:73] wire [8:0] schedule_a_bits_tag; // @[Mux.scala:30:73] wire [10:0] schedule_a_bits_set; // @[Mux.scala:30:73] wire [2:0] schedule_a_bits_param; // @[Mux.scala:30:73] wire schedule_a_bits_block; // @[Mux.scala:30:73] wire schedule_a_valid; // @[Mux.scala:30:73] wire [2:0] schedule_b_bits_param; // @[Mux.scala:30:73] wire [8:0] schedule_b_bits_tag; // @[Mux.scala:30:73] wire [10:0] schedule_b_bits_set; // @[Mux.scala:30:73] wire schedule_b_bits_clients; // @[Mux.scala:30:73] wire schedule_b_valid; // @[Mux.scala:30:73] wire [2:0] schedule_c_bits_opcode; // @[Mux.scala:30:73] wire [2:0] schedule_c_bits_param; // @[Mux.scala:30:73] wire [3:0] schedule_c_bits_source; // @[Mux.scala:30:73] wire [8:0] schedule_c_bits_tag; // @[Mux.scala:30:73] wire [10:0] schedule_c_bits_set; // @[Mux.scala:30:73] wire [3:0] schedule_c_bits_way; // @[Mux.scala:30:73] wire schedule_c_bits_dirty; // @[Mux.scala:30:73] wire schedule_c_valid; // @[Mux.scala:30:73] wire schedule_d_bits_prio_0; // @[Mux.scala:30:73] wire schedule_d_bits_prio_1; // @[Mux.scala:30:73] wire schedule_d_bits_prio_2; // @[Mux.scala:30:73] wire schedule_d_bits_control; // @[Mux.scala:30:73] wire [2:0] schedule_d_bits_opcode; // @[Mux.scala:30:73] wire [2:0] schedule_d_bits_param; // @[Mux.scala:30:73] wire [2:0] schedule_d_bits_size; // @[Mux.scala:30:73] wire [5:0] schedule_d_bits_source; // @[Mux.scala:30:73] wire [8:0] schedule_d_bits_tag; // @[Mux.scala:30:73] wire [5:0] schedule_d_bits_offset; // @[Mux.scala:30:73] wire [5:0] schedule_d_bits_put; // @[Mux.scala:30:73] wire [10:0] schedule_d_bits_set; // @[Mux.scala:30:73] wire [3:0] schedule_d_bits_way; // @[Mux.scala:30:73] wire schedule_d_bits_bad; // @[Mux.scala:30:73] wire schedule_d_valid; // @[Mux.scala:30:73] wire [2:0] schedule_e_bits_sink; // @[Mux.scala:30:73] wire schedule_e_valid; // @[Mux.scala:30:73] wire schedule_x_valid; // @[Mux.scala:30:73] wire schedule_dir_bits_data_dirty; // @[Mux.scala:30:73] wire [1:0] schedule_dir_bits_data_state; // @[Mux.scala:30:73] wire schedule_dir_bits_data_clients; // @[Mux.scala:30:73] wire [8:0] schedule_dir_bits_data_tag; // @[Mux.scala:30:73] wire [10:0] schedule_dir_bits_set; // @[Mux.scala:30:73] wire [3:0] schedule_dir_bits_way; // @[Mux.scala:30:73] wire schedule_dir_valid; // @[Mux.scala:30:73] wire schedule_reload; // @[Mux.scala:30:73] wire _schedule_T_12 = _schedule_T & _mshrs_0_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36] wire _schedule_T_13 = _schedule_T_1 & _mshrs_1_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36] wire _schedule_T_14 = _schedule_T_2 & _mshrs_2_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36] wire _schedule_T_15 = _schedule_T_3 & _mshrs_3_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36] wire _schedule_T_16 = _schedule_T_4 & _mshrs_4_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36] wire _schedule_T_17 = _schedule_T_5 & _mshrs_5_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36] wire _schedule_T_18 = _schedule_T_6 & _mshrs_6_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36] wire _schedule_T_19 = _schedule_T_7 & _mshrs_7_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36] wire _schedule_T_20 = _schedule_T_8 & _mshrs_8_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36] wire _schedule_T_21 = _schedule_T_9 & _mshrs_9_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36] wire _schedule_T_22 = _schedule_T_10 & _mshrs_10_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36] wire _schedule_T_23 = _schedule_T_11 & _mshrs_11_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36] wire _schedule_T_24 = _schedule_T_12 \| _schedule_T_13; // @[Mux.scala:30:73] wire _schedule_T_25 = _schedule_T_24 \| _schedule_T_14; // @[Mux.scala:30:73] wire _schedule_T_26 = _schedule_T_25 \| _schedule_T_15; // @[Mux.scala:30:73] wire _schedule_T_27 = _schedule_T_26 \| _schedule_T_16; // @[Mux.scala:30:73] wire _schedule_T_28 = _schedule_T_27 \| _schedule_T_17; // @[Mux.scala:30:73] wire _schedule_T_29 = _schedule_T_28 \| _schedule_T_18; // @[Mux.scala:30:73] wire _schedule_T_30 = _schedule_T_29 \| _schedule_T_19; // @[Mux.scala:30:73] wire _schedule_T_31 = _schedule_T_30 \| _schedule_T_20; // @[Mux.scala:30:73] wire _schedule_T_32 = _schedule_T_31 \| _schedule_T_21; // @[Mux.scala:30:73] wire _schedule_T_33 = _schedule_T_32 \| _schedule_T_22; // @[Mux.scala:30:73] wire _schedule_T_34 = _schedule_T_33 \| _schedule_T_23; // @[Mux.scala:30:73] assign _schedule_WIRE = _schedule_T_34; // @[Mux.scala:30:73] assign schedule_reload = _schedule_WIRE; // @[Mux.scala:30:73] wire _schedule_WIRE_10; // @[Mux.scala:30:73] assign schedule_dir_valid = _schedule_WIRE_1_valid; // @[Mux.scala:30:73] wire [10:0] _schedule_WIRE_2_set; // @[Mux.scala:30:73] assign schedule_dir_bits_set = _schedule_WIRE_1_bits_set; // @[Mux.scala:30:73] wire [3:0] _schedule_WIRE_2_way; // @[Mux.scala:30:73] assign schedule_dir_bits_way = _schedule_WIRE_1_bits_way; // @[Mux.scala:30:73] wire _schedule_WIRE_2_data_dirty; // @[Mux.scala:30:73] assign schedule_dir_bits_data_dirty = _schedule_WIRE_1_bits_data_dirty; // @[Mux.scala:30:73] wire [1:0] _schedule_WIRE_2_data_state; // @[Mux.scala:30:73] assign schedule_dir_bits_data_state = _schedule_WIRE_1_bits_data_state; // @[Mux.scala:30:73] wire _schedule_WIRE_2_data_clients; // @[Mux.scala:30:73] assign schedule_dir_bits_data_clients = _schedule_WIRE_1_bits_data_clients; // @[Mux.scala:30:73] wire [8:0] _schedule_WIRE_2_data_tag; // @[Mux.scala:30:73] assign schedule_dir_bits_data_tag = _schedule_WIRE_1_bits_data_tag; // @[Mux.scala:30:73] wire [10:0] _schedule_WIRE_9; // @[Mux.scala:30:73] assign _schedule_WIRE_1_bits_set = _schedule_WIRE_2_set; // @[Mux.scala:30:73] wire [3:0] _schedule_WIRE_8; // @[Mux.scala:30:73] assign _schedule_WIRE_1_bits_way = _schedule_WIRE_2_way; // @[Mux.scala:30:73] wire _schedule_WIRE_3_dirty; // @[Mux.scala:30:73] assign _schedule_WIRE_1_bits_data_dirty = _schedule_WIRE_2_data_dirty; // @[Mux.scala:30:73] wire [1:0] _schedule_WIRE_3_state; // @[Mux.scala:30:73] assign _schedule_WIRE_1_bits_data_state = _schedule_WIRE_2_data_state; // @[Mux.scala:30:73] wire _schedule_WIRE_3_clients; // @[Mux.scala:30:73] assign _schedule_WIRE_1_bits_data_clients = _schedule_WIRE_2_data_clients; // @[Mux.scala:30:73] wire [8:0] _schedule_WIRE_3_tag; // @[Mux.scala:30:73] assign _schedule_WIRE_1_bits_data_tag = _schedule_WIRE_2_data_tag; // @[Mux.scala:30:73] wire _schedule_WIRE_7; // @[Mux.scala:30:73] assign _schedule_WIRE_2_data_dirty = _schedule_WIRE_3_dirty; // @[Mux.scala:30:73] wire [1:0] _schedule_WIRE_6; // @[Mux.scala:30:73] assign _schedule_WIRE_2_data_state = _schedule_WIRE_3_state; // @[Mux.scala:30:73] wire _schedule_WIRE_5; // @[Mux.scala:30:73] assign _schedule_WIRE_2_data_clients = _schedule_WIRE_3_clients; // @[Mux.scala:30:73] wire [8:0] _schedule_WIRE_4; // @[Mux.scala:30:73] assign _schedule_WIRE_2_data_tag = _schedule_WIRE_3_tag; // @[Mux.scala:30:73] wire [8:0] _schedule_T_35 = _schedule_T ? _mshrs_0_io_schedule_bits_dir_bits_data_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_36 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_dir_bits_data_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_37 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_dir_bits_data_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_38 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_dir_bits_data_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_39 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_dir_bits_data_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_40 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_dir_bits_data_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_41 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_dir_bits_data_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_42 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_dir_bits_data_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_43 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_dir_bits_data_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_44 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_dir_bits_data_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_45 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_dir_bits_data_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_46 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_dir_bits_data_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_47 = _schedule_T_35 \| _schedule_T_36; // @[Mux.scala:30:73] wire [8:0] _schedule_T_48 = _schedule_T_47 \| _schedule_T_37; // @[Mux.scala:30:73] wire [8:0] _schedule_T_49 = _schedule_T_48 \| _schedule_T_38; // @[Mux.scala:30:73] wire [8:0] _schedule_T_50 = _schedule_T_49 \| _schedule_T_39; // @[Mux.scala:30:73] wire [8:0] _schedule_T_51 = _schedule_T_50 \| _schedule_T_40; // @[Mux.scala:30:73] wire [8:0] _schedule_T_52 = _schedule_T_51 \| _schedule_T_41; // @[Mux.scala:30:73] wire [8:0] _schedule_T_53 = _schedule_T_52 \| _schedule_T_42; // @[Mux.scala:30:73] wire [8:0] _schedule_T_54 = _schedule_T_53 \| _schedule_T_43; // @[Mux.scala:30:73] wire [8:0] _schedule_T_55 = _schedule_T_54 \| _schedule_T_44; // @[Mux.scala:30:73] wire [8:0] _schedule_T_56 = _schedule_T_55 \| _schedule_T_45; // @[Mux.scala:30:73] wire [8:0] _schedule_T_57 = _schedule_T_56 \| _schedule_T_46; // @[Mux.scala:30:73] assign _schedule_WIRE_4 = _schedule_T_57; // @[Mux.scala:30:73] assign _schedule_WIRE_3_tag = _schedule_WIRE_4; // @[Mux.scala:30:73] wire _schedule_T_58 = _schedule_T & _mshrs_0_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36] wire _schedule_T_59 = _schedule_T_1 & _mshrs_1_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36] wire _schedule_T_60 = _schedule_T_2 & _mshrs_2_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36] wire _schedule_T_61 = _schedule_T_3 & _mshrs_3_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36] wire _schedule_T_62 = _schedule_T_4 & _mshrs_4_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36] wire _schedule_T_63 = _schedule_T_5 & _mshrs_5_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36] wire _schedule_T_64 = _schedule_T_6 & _mshrs_6_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36] wire _schedule_T_65 = _schedule_T_7 & _mshrs_7_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36] wire _schedule_T_66 = _schedule_T_8 & _mshrs_8_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36] wire _schedule_T_67 = _schedule_T_9 & _mshrs_9_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36] wire _schedule_T_68 = _schedule_T_10 & _mshrs_10_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36] wire _schedule_T_69 = _schedule_T_11 & _mshrs_11_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36] wire _schedule_T_70 = _schedule_T_58 \| _schedule_T_59; // @[Mux.scala:30:73] wire _schedule_T_71 = _schedule_T_70 \| _schedule_T_60; // @[Mux.scala:30:73] wire _schedule_T_72 = _schedule_T_71 \| _schedule_T_61; // @[Mux.scala:30:73] wire _schedule_T_73 = _schedule_T_72 \| _schedule_T_62; // @[Mux.scala:30:73] wire _schedule_T_74 = _schedule_T_73 \| _schedule_T_63; // @[Mux.scala:30:73] wire _schedule_T_75 = _schedule_T_74 \| _schedule_T_64; // @[Mux.scala:30:73] wire _schedule_T_76 = _schedule_T_75 \| _schedule_T_65; // @[Mux.scala:30:73] wire _schedule_T_77 = _schedule_T_76 \| _schedule_T_66; // @[Mux.scala:30:73] wire _schedule_T_78 = _schedule_T_77 \| _schedule_T_67; // @[Mux.scala:30:73] wire _schedule_T_79 = _schedule_T_78 \| _schedule_T_68; // @[Mux.scala:30:73] wire _schedule_T_80 = _schedule_T_79 \| _schedule_T_69; // @[Mux.scala:30:73] assign _schedule_WIRE_5 = _schedule_T_80; // @[Mux.scala:30:73] assign _schedule_WIRE_3_clients = _schedule_WIRE_5; // @[Mux.scala:30:73] wire [1:0] _schedule_T_81 = _schedule_T ? _mshrs_0_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _schedule_T_82 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _schedule_T_83 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _schedule_T_84 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _schedule_T_85 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _schedule_T_86 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _schedule_T_87 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _schedule_T_88 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _schedule_T_89 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _schedule_T_90 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _schedule_T_91 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _schedule_T_92 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _schedule_T_93 = _schedule_T_81 \| _schedule_T_82; // @[Mux.scala:30:73] wire [1:0] _schedule_T_94 = _schedule_T_93 \| _schedule_T_83; // @[Mux.scala:30:73] wire [1:0] _schedule_T_95 = _schedule_T_94 \| _schedule_T_84; // @[Mux.scala:30:73] wire [1:0] _schedule_T_96 = _schedule_T_95 \| _schedule_T_85; // @[Mux.scala:30:73] wire [1:0] _schedule_T_97 = _schedule_T_96 \| _schedule_T_86; // @[Mux.scala:30:73] wire [1:0] _schedule_T_98 = _schedule_T_97 \| _schedule_T_87; // @[Mux.scala:30:73] wire [1:0] _schedule_T_99 = _schedule_T_98 \| _schedule_T_88; // @[Mux.scala:30:73] wire [1:0] _schedule_T_100 = _schedule_T_99 \| _schedule_T_89; // @[Mux.scala:30:73] wire [1:0] _schedule_T_101 = _schedule_T_100 \| _schedule_T_90; // @[Mux.scala:30:73] wire [1:0] _schedule_T_102 = _schedule_T_101 \| _schedule_T_91; // @[Mux.scala:30:73] wire [1:0] _schedule_T_103 = _schedule_T_102 \| _schedule_T_92; // @[Mux.scala:30:73] assign _schedule_WIRE_6 = _schedule_T_103; // @[Mux.scala:30:73] assign _schedule_WIRE_3_state = _schedule_WIRE_6; // @[Mux.scala:30:73] wire _schedule_T_104 = _schedule_T & _mshrs_0_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_105 = _schedule_T_1 & _mshrs_1_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_106 = _schedule_T_2 & _mshrs_2_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_107 = _schedule_T_3 & _mshrs_3_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_108 = _schedule_T_4 & _mshrs_4_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_109 = _schedule_T_5 & _mshrs_5_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_110 = _schedule_T_6 & _mshrs_6_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_111 = _schedule_T_7 & _mshrs_7_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_112 = _schedule_T_8 & _mshrs_8_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_113 = _schedule_T_9 & _mshrs_9_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_114 = _schedule_T_10 & _mshrs_10_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_115 = _schedule_T_11 & _mshrs_11_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_116 = _schedule_T_104 \| _schedule_T_105; // @[Mux.scala:30:73] wire _schedule_T_117 = _schedule_T_116 \| _schedule_T_106; // @[Mux.scala:30:73] wire _schedule_T_118 = _schedule_T_117 \| _schedule_T_107; // @[Mux.scala:30:73] wire _schedule_T_119 = _schedule_T_118 \| _schedule_T_108; // @[Mux.scala:30:73] wire _schedule_T_120 = _schedule_T_119 \| _schedule_T_109; // @[Mux.scala:30:73] wire _schedule_T_121 = _schedule_T_120 \| _schedule_T_110; // @[Mux.scala:30:73] wire _schedule_T_122 = _schedule_T_121 \| _schedule_T_111; // @[Mux.scala:30:73] wire _schedule_T_123 = _schedule_T_122 \| _schedule_T_112; // @[Mux.scala:30:73] wire _schedule_T_124 = _schedule_T_123 \| _schedule_T_113; // @[Mux.scala:30:73] wire _schedule_T_125 = _schedule_T_124 \| _schedule_T_114; // @[Mux.scala:30:73] wire _schedule_T_126 = _schedule_T_125 \| _schedule_T_115; // @[Mux.scala:30:73] assign _schedule_WIRE_7 = _schedule_T_126; // @[Mux.scala:30:73] assign _schedule_WIRE_3_dirty = _schedule_WIRE_7; // @[Mux.scala:30:73] wire [3:0] _schedule_T_127 = _schedule_T ? _mshrs_0_io_schedule_bits_dir_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _schedule_T_128 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_dir_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _schedule_T_129 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_dir_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _schedule_T_130 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_dir_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _schedule_T_131 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_dir_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _schedule_T_132 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_dir_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _schedule_T_133 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_dir_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _schedule_T_134 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_dir_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _schedule_T_135 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_dir_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _schedule_T_136 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_dir_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _schedule_T_137 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_dir_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _schedule_T_138 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_dir_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _schedule_T_139 = _schedule_T_127 \| _schedule_T_128; // @[Mux.scala:30:73] wire [3:0] _schedule_T_140 = _schedule_T_139 \| _schedule_T_129; // @[Mux.scala:30:73] wire [3:0] _schedule_T_141 = _schedule_T_140 \| _schedule_T_130; // @[Mux.scala:30:73] wire [3:0] _schedule_T_142 = _schedule_T_141 \| _schedule_T_131; // @[Mux.scala:30:73] wire [3:0] _schedule_T_143 = _schedule_T_142 \| _schedule_T_132; // @[Mux.scala:30:73] wire [3:0] _schedule_T_144 = _schedule_T_143 \| _schedule_T_133; // @[Mux.scala:30:73] wire [3:0] _schedule_T_145 = _schedule_T_144 \| _schedule_T_134; // @[Mux.scala:30:73] wire [3:0] _schedule_T_146 = _schedule_T_145 \| _schedule_T_135; // @[Mux.scala:30:73] wire [3:0] _schedule_T_147 = _schedule_T_146 \| _schedule_T_136; // @[Mux.scala:30:73] wire [3:0] _schedule_T_148 = _schedule_T_147 \| _schedule_T_137; // @[Mux.scala:30:73] wire [3:0] _schedule_T_149 = _schedule_T_148 \| _schedule_T_138; // @[Mux.scala:30:73] assign _schedule_WIRE_8 = _schedule_T_149; // @[Mux.scala:30:73] assign _schedule_WIRE_2_way = _schedule_WIRE_8; // @[Mux.scala:30:73] wire [10:0] _schedule_T_150 = _schedule_T ? _mshrs_0_io_schedule_bits_dir_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_151 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_dir_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_152 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_dir_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_153 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_dir_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_154 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_dir_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_155 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_dir_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_156 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_dir_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_157 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_dir_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_158 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_dir_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_159 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_dir_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_160 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_dir_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_161 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_dir_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_162 = _schedule_T_150 \| _schedule_T_151; // @[Mux.scala:30:73] wire [10:0] _schedule_T_163 = _schedule_T_162 \| _schedule_T_152; // @[Mux.scala:30:73] wire [10:0] _schedule_T_164 = _schedule_T_163 \| _schedule_T_153; // @[Mux.scala:30:73] wire [10:0] _schedule_T_165 = _schedule_T_164 \| _schedule_T_154; // @[Mux.scala:30:73] wire [10:0] _schedule_T_166 = _schedule_T_165 \| _schedule_T_155; // @[Mux.scala:30:73] wire [10:0] _schedule_T_167 = _schedule_T_166 \| _schedule_T_156; // @[Mux.scala:30:73] wire [10:0] _schedule_T_168 = _schedule_T_167 \| _schedule_T_157; // @[Mux.scala:30:73] wire [10:0] _schedule_T_169 = _schedule_T_168 \| _schedule_T_158; // @[Mux.scala:30:73] wire [10:0] _schedule_T_170 = _schedule_T_169 \| _schedule_T_159; // @[Mux.scala:30:73] wire [10:0] _schedule_T_171 = _schedule_T_170 \| _schedule_T_160; // @[Mux.scala:30:73] wire [10:0] _schedule_T_172 = _schedule_T_171 \| _schedule_T_161; // @[Mux.scala:30:73] assign _schedule_WIRE_9 = _schedule_T_172; // @[Mux.scala:30:73] assign _schedule_WIRE_2_set = _schedule_WIRE_9; // @[Mux.scala:30:73] wire _schedule_T_173 = _schedule_T & _mshrs_0_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_174 = _schedule_T_1 & _mshrs_1_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_175 = _schedule_T_2 & _mshrs_2_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_176 = _schedule_T_3 & _mshrs_3_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_177 = _schedule_T_4 & _mshrs_4_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_178 = _schedule_T_5 & _mshrs_5_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_179 = _schedule_T_6 & _mshrs_6_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_180 = _schedule_T_7 & _mshrs_7_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_181 = _schedule_T_8 & _mshrs_8_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_182 = _schedule_T_9 & _mshrs_9_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_183 = _schedule_T_10 & _mshrs_10_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_184 = _schedule_T_11 & _mshrs_11_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_185 = _schedule_T_173 \| _schedule_T_174; // @[Mux.scala:30:73] wire _schedule_T_186 = _schedule_T_185 \| _schedule_T_175; // @[Mux.scala:30:73] wire _schedule_T_187 = _schedule_T_186 \| _schedule_T_176; // @[Mux.scala:30:73] wire _schedule_T_188 = _schedule_T_187 \| _schedule_T_177; // @[Mux.scala:30:73] wire _schedule_T_189 = _schedule_T_188 \| _schedule_T_178; // @[Mux.scala:30:73] wire _schedule_T_190 = _schedule_T_189 \| _schedule_T_179; // @[Mux.scala:30:73] wire _schedule_T_191 = _schedule_T_190 \| _schedule_T_180; // @[Mux.scala:30:73] wire _schedule_T_192 = _schedule_T_191 \| _schedule_T_181; // @[Mux.scala:30:73] wire _schedule_T_193 = _schedule_T_192 \| _schedule_T_182; // @[Mux.scala:30:73] wire _schedule_T_194 = _schedule_T_193 \| _schedule_T_183; // @[Mux.scala:30:73] wire _schedule_T_195 = _schedule_T_194 \| _schedule_T_184; // @[Mux.scala:30:73] assign _schedule_WIRE_10 = _schedule_T_195; // @[Mux.scala:30:73] assign _schedule_WIRE_1_valid = _schedule_WIRE_10; // @[Mux.scala:30:73] wire _schedule_WIRE_14; // @[Mux.scala:30:73] assign schedule_x_valid = _schedule_WIRE_11_valid; // @[Mux.scala:30:73] wire _schedule_T_219 = _schedule_T & _mshrs_0_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_220 = _schedule_T_1 & _mshrs_1_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_221 = _schedule_T_2 & _mshrs_2_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_222 = _schedule_T_3 & _mshrs_3_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_223 = _schedule_T_4 & _mshrs_4_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_224 = _schedule_T_5 & _mshrs_5_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_225 = _schedule_T_6 & _mshrs_6_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_226 = _schedule_T_7 & _mshrs_7_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_227 = _schedule_T_8 & _mshrs_8_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_228 = _schedule_T_9 & _mshrs_9_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_229 = _schedule_T_10 & _mshrs_10_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_230 = _schedule_T_11 & _mshrs_11_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_231 = _schedule_T_219 \| _schedule_T_220; // @[Mux.scala:30:73] wire _schedule_T_232 = _schedule_T_231 \| _schedule_T_221; // @[Mux.scala:30:73] wire _schedule_T_233 = _schedule_T_232 \| _schedule_T_222; // @[Mux.scala:30:73] wire _schedule_T_234 = _schedule_T_233 \| _schedule_T_223; // @[Mux.scala:30:73] wire _schedule_T_235 = _schedule_T_234 \| _schedule_T_224; // @[Mux.scala:30:73] wire _schedule_T_236 = _schedule_T_235 \| _schedule_T_225; // @[Mux.scala:30:73] wire _schedule_T_237 = _schedule_T_236 \| _schedule_T_226; // @[Mux.scala:30:73] wire _schedule_T_238 = _schedule_T_237 \| _schedule_T_227; // @[Mux.scala:30:73] wire _schedule_T_239 = _schedule_T_238 \| _schedule_T_228; // @[Mux.scala:30:73] wire _schedule_T_240 = _schedule_T_239 \| _schedule_T_229; // @[Mux.scala:30:73] wire _schedule_T_241 = _schedule_T_240 \| _schedule_T_230; // @[Mux.scala:30:73] assign _schedule_WIRE_14 = _schedule_T_241; // @[Mux.scala:30:73] assign _schedule_WIRE_11_valid = _schedule_WIRE_14; // @[Mux.scala:30:73] wire _schedule_WIRE_18; // @[Mux.scala:30:73] assign schedule_e_valid = _schedule_WIRE_15_valid; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_16_sink; // @[Mux.scala:30:73] assign schedule_e_bits_sink = _schedule_WIRE_15_bits_sink; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_17; // @[Mux.scala:30:73] assign _schedule_WIRE_15_bits_sink = _schedule_WIRE_16_sink; // @[Mux.scala:30:73] wire [2:0] _schedule_T_242 = _schedule_T ? _mshrs_0_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_243 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_244 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_245 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_246 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_247 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_248 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_249 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_250 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_251 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_252 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_253 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_254 = _schedule_T_242 \| _schedule_T_243; // @[Mux.scala:30:73] wire [2:0] _schedule_T_255 = _schedule_T_254 \| _schedule_T_244; // @[Mux.scala:30:73] wire [2:0] _schedule_T_256 = _schedule_T_255 \| _schedule_T_245; // @[Mux.scala:30:73] wire [2:0] _schedule_T_257 = _schedule_T_256 \| _schedule_T_246; // @[Mux.scala:30:73] wire [2:0] _schedule_T_258 = _schedule_T_257 \| _schedule_T_247; // @[Mux.scala:30:73] wire [2:0] _schedule_T_259 = _schedule_T_258 \| _schedule_T_248; // @[Mux.scala:30:73] wire [2:0] _schedule_T_260 = _schedule_T_259 \| _schedule_T_249; // @[Mux.scala:30:73] wire [2:0] _schedule_T_261 = _schedule_T_260 \| _schedule_T_250; // @[Mux.scala:30:73] wire [2:0] _schedule_T_262 = _schedule_T_261 \| _schedule_T_251; // @[Mux.scala:30:73] wire [2:0] _schedule_T_263 = _schedule_T_262 \| _schedule_T_252; // @[Mux.scala:30:73] wire [2:0] _schedule_T_264 = _schedule_T_263 \| _schedule_T_253; // @[Mux.scala:30:73] assign _schedule_WIRE_17 = _schedule_T_264; // @[Mux.scala:30:73] assign _schedule_WIRE_16_sink = _schedule_WIRE_17; // @[Mux.scala:30:73] wire _schedule_T_265 = _schedule_T & _mshrs_0_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_266 = _schedule_T_1 & _mshrs_1_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_267 = _schedule_T_2 & _mshrs_2_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_268 = _schedule_T_3 & _mshrs_3_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_269 = _schedule_T_4 & _mshrs_4_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_270 = _schedule_T_5 & _mshrs_5_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_271 = _schedule_T_6 & _mshrs_6_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_272 = _schedule_T_7 & _mshrs_7_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_273 = _schedule_T_8 & _mshrs_8_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_274 = _schedule_T_9 & _mshrs_9_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_275 = _schedule_T_10 & _mshrs_10_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_276 = _schedule_T_11 & _mshrs_11_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_277 = _schedule_T_265 \| _schedule_T_266; // @[Mux.scala:30:73] wire _schedule_T_278 = _schedule_T_277 \| _schedule_T_267; // @[Mux.scala:30:73] wire _schedule_T_279 = _schedule_T_278 \| _schedule_T_268; // @[Mux.scala:30:73] wire _schedule_T_280 = _schedule_T_279 \| _schedule_T_269; // @[Mux.scala:30:73] wire _schedule_T_281 = _schedule_T_280 \| _schedule_T_270; // @[Mux.scala:30:73] wire _schedule_T_282 = _schedule_T_281 \| _schedule_T_271; // @[Mux.scala:30:73] wire _schedule_T_283 = _schedule_T_282 \| _schedule_T_272; // @[Mux.scala:30:73] wire _schedule_T_284 = _schedule_T_283 \| _schedule_T_273; // @[Mux.scala:30:73] wire _schedule_T_285 = _schedule_T_284 \| _schedule_T_274; // @[Mux.scala:30:73] wire _schedule_T_286 = _schedule_T_285 \| _schedule_T_275; // @[Mux.scala:30:73] wire _schedule_T_287 = _schedule_T_286 \| _schedule_T_276; // @[Mux.scala:30:73] assign _schedule_WIRE_18 = _schedule_T_287; // @[Mux.scala:30:73] assign _schedule_WIRE_15_valid = _schedule_WIRE_18; // @[Mux.scala:30:73] wire _schedule_WIRE_37; // @[Mux.scala:30:73] assign schedule_d_valid = _schedule_WIRE_19_valid; // @[Mux.scala:30:73] wire _schedule_WIRE_20_prio_0; // @[Mux.scala:30:73] assign schedule_d_bits_prio_0 = _schedule_WIRE_19_bits_prio_0; // @[Mux.scala:30:73] wire _schedule_WIRE_20_prio_1; // @[Mux.scala:30:73] assign schedule_d_bits_prio_1 = _schedule_WIRE_19_bits_prio_1; // @[Mux.scala:30:73] wire _schedule_WIRE_20_prio_2; // @[Mux.scala:30:73] assign schedule_d_bits_prio_2 = _schedule_WIRE_19_bits_prio_2; // @[Mux.scala:30:73] wire _schedule_WIRE_20_control; // @[Mux.scala:30:73] assign schedule_d_bits_control = _schedule_WIRE_19_bits_control; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_20_opcode; // @[Mux.scala:30:73] assign schedule_d_bits_opcode = _schedule_WIRE_19_bits_opcode; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_20_param; // @[Mux.scala:30:73] assign schedule_d_bits_param = _schedule_WIRE_19_bits_param; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_20_size; // @[Mux.scala:30:73] assign schedule_d_bits_size = _schedule_WIRE_19_bits_size; // @[Mux.scala:30:73] wire [5:0] _schedule_WIRE_20_source; // @[Mux.scala:30:73] assign schedule_d_bits_source = _schedule_WIRE_19_bits_source; // @[Mux.scala:30:73] wire [8:0] _schedule_WIRE_20_tag; // @[Mux.scala:30:73] assign schedule_d_bits_tag = _schedule_WIRE_19_bits_tag; // @[Mux.scala:30:73] wire [5:0] _schedule_WIRE_20_offset; // @[Mux.scala:30:73] assign schedule_d_bits_offset = _schedule_WIRE_19_bits_offset; // @[Mux.scala:30:73] wire [5:0] _schedule_WIRE_20_put; // @[Mux.scala:30:73] assign schedule_d_bits_put = _schedule_WIRE_19_bits_put; // @[Mux.scala:30:73] wire [10:0] _schedule_WIRE_20_set; // @[Mux.scala:30:73] assign schedule_d_bits_set = _schedule_WIRE_19_bits_set; // @[Mux.scala:30:73] wire [3:0] _schedule_WIRE_20_way; // @[Mux.scala:30:73] assign schedule_d_bits_way = _schedule_WIRE_19_bits_way; // @[Mux.scala:30:73] wire _schedule_WIRE_20_bad; // @[Mux.scala:30:73] assign schedule_d_bits_bad = _schedule_WIRE_19_bits_bad; // @[Mux.scala:30:73] wire _schedule_WIRE_33_0; // @[Mux.scala:30:73] assign _schedule_WIRE_19_bits_prio_0 = _schedule_WIRE_20_prio_0; // @[Mux.scala:30:73] wire _schedule_WIRE_33_1; // @[Mux.scala:30:73] assign _schedule_WIRE_19_bits_prio_1 = _schedule_WIRE_20_prio_1; // @[Mux.scala:30:73] wire _schedule_WIRE_33_2; // @[Mux.scala:30:73] assign _schedule_WIRE_19_bits_prio_2 = _schedule_WIRE_20_prio_2; // @[Mux.scala:30:73] wire _schedule_WIRE_32; // @[Mux.scala:30:73] assign _schedule_WIRE_19_bits_control = _schedule_WIRE_20_control; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_31; // @[Mux.scala:30:73] assign _schedule_WIRE_19_bits_opcode = _schedule_WIRE_20_opcode; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_30; // @[Mux.scala:30:73] assign _schedule_WIRE_19_bits_param = _schedule_WIRE_20_param; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_29; // @[Mux.scala:30:73] assign _schedule_WIRE_19_bits_size = _schedule_WIRE_20_size; // @[Mux.scala:30:73] wire [5:0] _schedule_WIRE_28; // @[Mux.scala:30:73] assign _schedule_WIRE_19_bits_source = _schedule_WIRE_20_source; // @[Mux.scala:30:73] wire [8:0] _schedule_WIRE_27; // @[Mux.scala:30:73] assign _schedule_WIRE_19_bits_tag = _schedule_WIRE_20_tag; // @[Mux.scala:30:73] wire [5:0] _schedule_WIRE_26; // @[Mux.scala:30:73] assign _schedule_WIRE_19_bits_offset = _schedule_WIRE_20_offset; // @[Mux.scala:30:73] wire [5:0] _schedule_WIRE_25; // @[Mux.scala:30:73] assign _schedule_WIRE_19_bits_put = _schedule_WIRE_20_put; // @[Mux.scala:30:73] wire [10:0] _schedule_WIRE_24; // @[Mux.scala:30:73] assign _schedule_WIRE_19_bits_set = _schedule_WIRE_20_set; // @[Mux.scala:30:73] wire [3:0] _schedule_WIRE_22; // @[Mux.scala:30:73] assign _schedule_WIRE_19_bits_way = _schedule_WIRE_20_way; // @[Mux.scala:30:73] wire _schedule_WIRE_21; // @[Mux.scala:30:73] assign _schedule_WIRE_19_bits_bad = _schedule_WIRE_20_bad; // @[Mux.scala:30:73] wire _schedule_T_288 = _schedule_T & _mshrs_0_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36] wire _schedule_T_289 = _schedule_T_1 & _mshrs_1_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36] wire _schedule_T_290 = _schedule_T_2 & _mshrs_2_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36] wire _schedule_T_291 = _schedule_T_3 & _mshrs_3_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36] wire _schedule_T_292 = _schedule_T_4 & _mshrs_4_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36] wire _schedule_T_293 = _schedule_T_5 & _mshrs_5_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36] wire _schedule_T_294 = _schedule_T_6 & _mshrs_6_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36] wire _schedule_T_295 = _schedule_T_7 & _mshrs_7_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36] wire _schedule_T_296 = _schedule_T_8 & _mshrs_8_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36] wire _schedule_T_297 = _schedule_T_9 & _mshrs_9_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36] wire _schedule_T_298 = _schedule_T_10 & _mshrs_10_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36] wire _schedule_T_299 = _schedule_T_11 & _mshrs_11_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36] wire _schedule_T_300 = _schedule_T_288 \| _schedule_T_289; // @[Mux.scala:30:73] wire _schedule_T_301 = _schedule_T_300 \| _schedule_T_290; // @[Mux.scala:30:73] wire _schedule_T_302 = _schedule_T_301 \| _schedule_T_291; // @[Mux.scala:30:73] wire _schedule_T_303 = _schedule_T_302 \| _schedule_T_292; // @[Mux.scala:30:73] wire _schedule_T_304 = _schedule_T_303 \| _schedule_T_293; // @[Mux.scala:30:73] wire _schedule_T_305 = _schedule_T_304 \| _schedule_T_294; // @[Mux.scala:30:73] wire _schedule_T_306 = _schedule_T_305 \| _schedule_T_295; // @[Mux.scala:30:73] wire _schedule_T_307 = _schedule_T_306 \| _schedule_T_296; // @[Mux.scala:30:73] wire _schedule_T_308 = _schedule_T_307 \| _schedule_T_297; // @[Mux.scala:30:73] wire _schedule_T_309 = _schedule_T_308 \| _schedule_T_298; // @[Mux.scala:30:73] wire _schedule_T_310 = _schedule_T_309 \| _schedule_T_299; // @[Mux.scala:30:73] assign _schedule_WIRE_21 = _schedule_T_310; // @[Mux.scala:30:73] assign _schedule_WIRE_20_bad = _schedule_WIRE_21; // @[Mux.scala:30:73] wire [3:0] _schedule_T_311 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _schedule_T_312 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _schedule_T_313 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _schedule_T_314 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _schedule_T_315 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _schedule_T_316 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _schedule_T_317 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _schedule_T_318 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_d_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _schedule_T_319 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_d_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _schedule_T_320 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_d_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _schedule_T_321 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_d_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _schedule_T_322 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_d_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _schedule_T_323 = _schedule_T_311 \| _schedule_T_312; // @[Mux.scala:30:73] wire [3:0] _schedule_T_324 = _schedule_T_323 \| _schedule_T_313; // @[Mux.scala:30:73] wire [3:0] _schedule_T_325 = _schedule_T_324 \| _schedule_T_314; // @[Mux.scala:30:73] wire [3:0] _schedule_T_326 = _schedule_T_325 \| _schedule_T_315; // @[Mux.scala:30:73] wire [3:0] _schedule_T_327 = _schedule_T_326 \| _schedule_T_316; // @[Mux.scala:30:73] wire [3:0] _schedule_T_328 = _schedule_T_327 \| _schedule_T_317; // @[Mux.scala:30:73] wire [3:0] _schedule_T_329 = _schedule_T_328 \| _schedule_T_318; // @[Mux.scala:30:73] wire [3:0] _schedule_T_330 = _schedule_T_329 \| _schedule_T_319; // @[Mux.scala:30:73] wire [3:0] _schedule_T_331 = _schedule_T_330 \| _schedule_T_320; // @[Mux.scala:30:73] wire [3:0] _schedule_T_332 = _schedule_T_331 \| _schedule_T_321; // @[Mux.scala:30:73] wire [3:0] _schedule_T_333 = _schedule_T_332 \| _schedule_T_322; // @[Mux.scala:30:73] assign _schedule_WIRE_22 = _schedule_T_333; // @[Mux.scala:30:73] assign _schedule_WIRE_20_way = _schedule_WIRE_22; // @[Mux.scala:30:73] wire [10:0] _schedule_T_357 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_358 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_359 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_360 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_361 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_362 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_363 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_364 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_d_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_365 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_d_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_366 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_d_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_367 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_d_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_368 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_d_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_369 = _schedule_T_357 \| _schedule_T_358; // @[Mux.scala:30:73] wire [10:0] _schedule_T_370 = _schedule_T_369 \| _schedule_T_359; // @[Mux.scala:30:73] wire [10:0] _schedule_T_371 = _schedule_T_370 \| _schedule_T_360; // @[Mux.scala:30:73] wire [10:0] _schedule_T_372 = _schedule_T_371 \| _schedule_T_361; // @[Mux.scala:30:73] wire [10:0] _schedule_T_373 = _schedule_T_372 \| _schedule_T_362; // @[Mux.scala:30:73] wire [10:0] _schedule_T_374 = _schedule_T_373 \| _schedule_T_363; // @[Mux.scala:30:73] wire [10:0] _schedule_T_375 = _schedule_T_374 \| _schedule_T_364; // @[Mux.scala:30:73] wire [10:0] _schedule_T_376 = _schedule_T_375 \| _schedule_T_365; // @[Mux.scala:30:73] wire [10:0] _schedule_T_377 = _schedule_T_376 \| _schedule_T_366; // @[Mux.scala:30:73] wire [10:0] _schedule_T_378 = _schedule_T_377 \| _schedule_T_367; // @[Mux.scala:30:73] wire [10:0] _schedule_T_379 = _schedule_T_378 \| _schedule_T_368; // @[Mux.scala:30:73] assign _schedule_WIRE_24 = _schedule_T_379; // @[Mux.scala:30:73] assign _schedule_WIRE_20_set = _schedule_WIRE_24; // @[Mux.scala:30:73] wire [5:0] _schedule_T_380 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_381 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_382 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_383 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_384 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_385 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_386 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_387 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_388 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_389 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_390 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_391 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_392 = _schedule_T_380 \| _schedule_T_381; // @[Mux.scala:30:73] wire [5:0] _schedule_T_393 = _schedule_T_392 \| _schedule_T_382; // @[Mux.scala:30:73] wire [5:0] _schedule_T_394 = _schedule_T_393 \| _schedule_T_383; // @[Mux.scala:30:73] wire [5:0] _schedule_T_395 = _schedule_T_394 \| _schedule_T_384; // @[Mux.scala:30:73] wire [5:0] _schedule_T_396 = _schedule_T_395 \| _schedule_T_385; // @[Mux.scala:30:73] wire [5:0] _schedule_T_397 = _schedule_T_396 \| _schedule_T_386; // @[Mux.scala:30:73] wire [5:0] _schedule_T_398 = _schedule_T_397 \| _schedule_T_387; // @[Mux.scala:30:73] wire [5:0] _schedule_T_399 = _schedule_T_398 \| _schedule_T_388; // @[Mux.scala:30:73] wire [5:0] _schedule_T_400 = _schedule_T_399 \| _schedule_T_389; // @[Mux.scala:30:73] wire [5:0] _schedule_T_401 = _schedule_T_400 \| _schedule_T_390; // @[Mux.scala:30:73] wire [5:0] _schedule_T_402 = _schedule_T_401 \| _schedule_T_391; // @[Mux.scala:30:73] assign _schedule_WIRE_25 = _schedule_T_402; // @[Mux.scala:30:73] assign _schedule_WIRE_20_put = _schedule_WIRE_25; // @[Mux.scala:30:73] wire [5:0] _schedule_T_403 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_404 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_405 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_406 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_407 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_408 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_409 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_410 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_411 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_412 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_413 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_414 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_415 = _schedule_T_403 \| _schedule_T_404; // @[Mux.scala:30:73] wire [5:0] _schedule_T_416 = _schedule_T_415 \| _schedule_T_405; // @[Mux.scala:30:73] wire [5:0] _schedule_T_417 = _schedule_T_416 \| _schedule_T_406; // @[Mux.scala:30:73] wire [5:0] _schedule_T_418 = _schedule_T_417 \| _schedule_T_407; // @[Mux.scala:30:73] wire [5:0] _schedule_T_419 = _schedule_T_418 \| _schedule_T_408; // @[Mux.scala:30:73] wire [5:0] _schedule_T_420 = _schedule_T_419 \| _schedule_T_409; // @[Mux.scala:30:73] wire [5:0] _schedule_T_421 = _schedule_T_420 \| _schedule_T_410; // @[Mux.scala:30:73] wire [5:0] _schedule_T_422 = _schedule_T_421 \| _schedule_T_411; // @[Mux.scala:30:73] wire [5:0] _schedule_T_423 = _schedule_T_422 \| _schedule_T_412; // @[Mux.scala:30:73] wire [5:0] _schedule_T_424 = _schedule_T_423 \| _schedule_T_413; // @[Mux.scala:30:73] wire [5:0] _schedule_T_425 = _schedule_T_424 \| _schedule_T_414; // @[Mux.scala:30:73] assign _schedule_WIRE_26 = _schedule_T_425; // @[Mux.scala:30:73] assign _schedule_WIRE_20_offset = _schedule_WIRE_26; // @[Mux.scala:30:73] wire [8:0] _schedule_T_426 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_427 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_428 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_429 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_430 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_431 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_432 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_433 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_d_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_434 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_d_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_435 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_d_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_436 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_d_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_437 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_d_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_438 = _schedule_T_426 \| _schedule_T_427; // @[Mux.scala:30:73] wire [8:0] _schedule_T_439 = _schedule_T_438 \| _schedule_T_428; // @[Mux.scala:30:73] wire [8:0] _schedule_T_440 = _schedule_T_439 \| _schedule_T_429; // @[Mux.scala:30:73] wire [8:0] _schedule_T_441 = _schedule_T_440 \| _schedule_T_430; // @[Mux.scala:30:73] wire [8:0] _schedule_T_442 = _schedule_T_441 \| _schedule_T_431; // @[Mux.scala:30:73] wire [8:0] _schedule_T_443 = _schedule_T_442 \| _schedule_T_432; // @[Mux.scala:30:73] wire [8:0] _schedule_T_444 = _schedule_T_443 \| _schedule_T_433; // @[Mux.scala:30:73] wire [8:0] _schedule_T_445 = _schedule_T_444 \| _schedule_T_434; // @[Mux.scala:30:73] wire [8:0] _schedule_T_446 = _schedule_T_445 \| _schedule_T_435; // @[Mux.scala:30:73] wire [8:0] _schedule_T_447 = _schedule_T_446 \| _schedule_T_436; // @[Mux.scala:30:73] wire [8:0] _schedule_T_448 = _schedule_T_447 \| _schedule_T_437; // @[Mux.scala:30:73] assign _schedule_WIRE_27 = _schedule_T_448; // @[Mux.scala:30:73] assign _schedule_WIRE_20_tag = _schedule_WIRE_27; // @[Mux.scala:30:73] wire [5:0] _schedule_T_449 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_450 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_451 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_452 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_453 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_454 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_455 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_456 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_457 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_458 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_459 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_460 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_461 = _schedule_T_449 \| _schedule_T_450; // @[Mux.scala:30:73] wire [5:0] _schedule_T_462 = _schedule_T_461 \| _schedule_T_451; // @[Mux.scala:30:73] wire [5:0] _schedule_T_463 = _schedule_T_462 \| _schedule_T_452; // @[Mux.scala:30:73] wire [5:0] _schedule_T_464 = _schedule_T_463 \| _schedule_T_453; // @[Mux.scala:30:73] wire [5:0] _schedule_T_465 = _schedule_T_464 \| _schedule_T_454; // @[Mux.scala:30:73] wire [5:0] _schedule_T_466 = _schedule_T_465 \| _schedule_T_455; // @[Mux.scala:30:73] wire [5:0] _schedule_T_467 = _schedule_T_466 \| _schedule_T_456; // @[Mux.scala:30:73] wire [5:0] _schedule_T_468 = _schedule_T_467 \| _schedule_T_457; // @[Mux.scala:30:73] wire [5:0] _schedule_T_469 = _schedule_T_468 \| _schedule_T_458; // @[Mux.scala:30:73] wire [5:0] _schedule_T_470 = _schedule_T_469 \| _schedule_T_459; // @[Mux.scala:30:73] wire [5:0] _schedule_T_471 = _schedule_T_470 \| _schedule_T_460; // @[Mux.scala:30:73] assign _schedule_WIRE_28 = _schedule_T_471; // @[Mux.scala:30:73] assign _schedule_WIRE_20_source = _schedule_WIRE_28; // @[Mux.scala:30:73] wire [2:0] _schedule_T_472 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_473 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_474 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_475 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_476 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_477 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_478 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_479 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_480 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_481 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_482 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_483 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_484 = _schedule_T_472 \| _schedule_T_473; // @[Mux.scala:30:73] wire [2:0] _schedule_T_485 = _schedule_T_484 \| _schedule_T_474; // @[Mux.scala:30:73] wire [2:0] _schedule_T_486 = _schedule_T_485 \| _schedule_T_475; // @[Mux.scala:30:73] wire [2:0] _schedule_T_487 = _schedule_T_486 \| _schedule_T_476; // @[Mux.scala:30:73] wire [2:0] _schedule_T_488 = _schedule_T_487 \| _schedule_T_477; // @[Mux.scala:30:73] wire [2:0] _schedule_T_489 = _schedule_T_488 \| _schedule_T_478; // @[Mux.scala:30:73] wire [2:0] _schedule_T_490 = _schedule_T_489 \| _schedule_T_479; // @[Mux.scala:30:73] wire [2:0] _schedule_T_491 = _schedule_T_490 \| _schedule_T_480; // @[Mux.scala:30:73] wire [2:0] _schedule_T_492 = _schedule_T_491 \| _schedule_T_481; // @[Mux.scala:30:73] wire [2:0] _schedule_T_493 = _schedule_T_492 \| _schedule_T_482; // @[Mux.scala:30:73] wire [2:0] _schedule_T_494 = _schedule_T_493 \| _schedule_T_483; // @[Mux.scala:30:73] assign _schedule_WIRE_29 = _schedule_T_494; // @[Mux.scala:30:73] assign _schedule_WIRE_20_size = _schedule_WIRE_29; // @[Mux.scala:30:73] wire [2:0] _schedule_T_495 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_496 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_497 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_498 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_499 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_500 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_501 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_502 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_503 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_504 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_505 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_506 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_507 = _schedule_T_495 \| _schedule_T_496; // @[Mux.scala:30:73] wire [2:0] _schedule_T_508 = _schedule_T_507 \| _schedule_T_497; // @[Mux.scala:30:73] wire [2:0] _schedule_T_509 = _schedule_T_508 \| _schedule_T_498; // @[Mux.scala:30:73] wire [2:0] _schedule_T_510 = _schedule_T_509 \| _schedule_T_499; // @[Mux.scala:30:73] wire [2:0] _schedule_T_511 = _schedule_T_510 \| _schedule_T_500; // @[Mux.scala:30:73] wire [2:0] _schedule_T_512 = _schedule_T_511 \| _schedule_T_501; // @[Mux.scala:30:73] wire [2:0] _schedule_T_513 = _schedule_T_512 \| _schedule_T_502; // @[Mux.scala:30:73] wire [2:0] _schedule_T_514 = _schedule_T_513 \| _schedule_T_503; // @[Mux.scala:30:73] wire [2:0] _schedule_T_515 = _schedule_T_514 \| _schedule_T_504; // @[Mux.scala:30:73] wire [2:0] _schedule_T_516 = _schedule_T_515 \| _schedule_T_505; // @[Mux.scala:30:73] wire [2:0] _schedule_T_517 = _schedule_T_516 \| _schedule_T_506; // @[Mux.scala:30:73] assign _schedule_WIRE_30 = _schedule_T_517; // @[Mux.scala:30:73] assign _schedule_WIRE_20_param = _schedule_WIRE_30; // @[Mux.scala:30:73] wire [2:0] _schedule_T_518 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_519 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_520 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_521 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_522 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_523 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_524 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_525 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_526 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_527 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_528 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_529 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_530 = _schedule_T_518 \| _schedule_T_519; // @[Mux.scala:30:73] wire [2:0] _schedule_T_531 = _schedule_T_530 \| _schedule_T_520; // @[Mux.scala:30:73] wire [2:0] _schedule_T_532 = _schedule_T_531 \| _schedule_T_521; // @[Mux.scala:30:73] wire [2:0] _schedule_T_533 = _schedule_T_532 \| _schedule_T_522; // @[Mux.scala:30:73] wire [2:0] _schedule_T_534 = _schedule_T_533 \| _schedule_T_523; // @[Mux.scala:30:73] wire [2:0] _schedule_T_535 = _schedule_T_534 \| _schedule_T_524; // @[Mux.scala:30:73] wire [2:0] _schedule_T_536 = _schedule_T_535 \| _schedule_T_525; // @[Mux.scala:30:73] wire [2:0] _schedule_T_537 = _schedule_T_536 \| _schedule_T_526; // @[Mux.scala:30:73] wire [2:0] _schedule_T_538 = _schedule_T_537 \| _schedule_T_527; // @[Mux.scala:30:73] wire [2:0] _schedule_T_539 = _schedule_T_538 \| _schedule_T_528; // @[Mux.scala:30:73] wire [2:0] _schedule_T_540 = _schedule_T_539 \| _schedule_T_529; // @[Mux.scala:30:73] assign _schedule_WIRE_31 = _schedule_T_540; // @[Mux.scala:30:73] assign _schedule_WIRE_20_opcode = _schedule_WIRE_31; // @[Mux.scala:30:73] wire _schedule_T_541 = _schedule_T & _mshrs_0_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36] wire _schedule_T_542 = _schedule_T_1 & _mshrs_1_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36] wire _schedule_T_543 = _schedule_T_2 & _mshrs_2_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36] wire _schedule_T_544 = _schedule_T_3 & _mshrs_3_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36] wire _schedule_T_545 = _schedule_T_4 & _mshrs_4_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36] wire _schedule_T_546 = _schedule_T_5 & _mshrs_5_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36] wire _schedule_T_547 = _schedule_T_6 & _mshrs_6_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36] wire _schedule_T_548 = _schedule_T_7 & _mshrs_7_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36] wire _schedule_T_549 = _schedule_T_8 & _mshrs_8_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36] wire _schedule_T_550 = _schedule_T_9 & _mshrs_9_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36] wire _schedule_T_551 = _schedule_T_10 & _mshrs_10_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36] wire _schedule_T_552 = _schedule_T_11 & _mshrs_11_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36] wire _schedule_T_553 = _schedule_T_541 \| _schedule_T_542; // @[Mux.scala:30:73] wire _schedule_T_554 = _schedule_T_553 \| _schedule_T_543; // @[Mux.scala:30:73] wire _schedule_T_555 = _schedule_T_554 \| _schedule_T_544; // @[Mux.scala:30:73] wire _schedule_T_556 = _schedule_T_555 \| _schedule_T_545; // @[Mux.scala:30:73] wire _schedule_T_557 = _schedule_T_556 \| _schedule_T_546; // @[Mux.scala:30:73] wire _schedule_T_558 = _schedule_T_557 \| _schedule_T_547; // @[Mux.scala:30:73] wire _schedule_T_559 = _schedule_T_558 \| _schedule_T_548; // @[Mux.scala:30:73] wire _schedule_T_560 = _schedule_T_559 \| _schedule_T_549; // @[Mux.scala:30:73] wire _schedule_T_561 = _schedule_T_560 \| _schedule_T_550; // @[Mux.scala:30:73] wire _schedule_T_562 = _schedule_T_561 \| _schedule_T_551; // @[Mux.scala:30:73] wire _schedule_T_563 = _schedule_T_562 \| _schedule_T_552; // @[Mux.scala:30:73] assign _schedule_WIRE_32 = _schedule_T_563; // @[Mux.scala:30:73] assign _schedule_WIRE_20_control = _schedule_WIRE_32; // @[Mux.scala:30:73] wire _schedule_WIRE_34; // @[Mux.scala:30:73] assign _schedule_WIRE_20_prio_0 = _schedule_WIRE_33_0; // @[Mux.scala:30:73] wire _schedule_WIRE_35; // @[Mux.scala:30:73] assign _schedule_WIRE_20_prio_1 = _schedule_WIRE_33_1; // @[Mux.scala:30:73] wire _schedule_WIRE_36; // @[Mux.scala:30:73] assign _schedule_WIRE_20_prio_2 = _schedule_WIRE_33_2; // @[Mux.scala:30:73] wire _schedule_T_564 = _schedule_T & _mshrs_0_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36] wire _schedule_T_565 = _schedule_T_1 & _mshrs_1_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36] wire _schedule_T_566 = _schedule_T_2 & _mshrs_2_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36] wire _schedule_T_567 = _schedule_T_3 & _mshrs_3_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36] wire _schedule_T_568 = _schedule_T_4 & _mshrs_4_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36] wire _schedule_T_569 = _schedule_T_5 & _mshrs_5_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36] wire _schedule_T_570 = _schedule_T_6 & _mshrs_6_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36] wire _schedule_T_571 = _schedule_T_7 & _mshrs_7_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36] wire _schedule_T_572 = _schedule_T_8 & _mshrs_8_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36] wire _schedule_T_573 = _schedule_T_9 & _mshrs_9_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36] wire _schedule_T_576 = _schedule_T_564 \| _schedule_T_565; // @[Mux.scala:30:73] wire _schedule_T_577 = _schedule_T_576 \| _schedule_T_566; // @[Mux.scala:30:73] wire _schedule_T_578 = _schedule_T_577 \| _schedule_T_567; // @[Mux.scala:30:73] wire _schedule_T_579 = _schedule_T_578 \| _schedule_T_568; // @[Mux.scala:30:73] wire _schedule_T_580 = _schedule_T_579 \| _schedule_T_569; // @[Mux.scala:30:73] wire _schedule_T_581 = _schedule_T_580 \| _schedule_T_570; // @[Mux.scala:30:73] wire _schedule_T_582 = _schedule_T_581 \| _schedule_T_571; // @[Mux.scala:30:73] wire _schedule_T_583 = _schedule_T_582 \| _schedule_T_572; // @[Mux.scala:30:73] wire _schedule_T_584 = _schedule_T_583 \| _schedule_T_573; // @[Mux.scala:30:73] wire _schedule_T_585 = _schedule_T_584; // @[Mux.scala:30:73] wire _schedule_T_586 = _schedule_T_585; // @[Mux.scala:30:73] assign _schedule_WIRE_34 = _schedule_T_586; // @[Mux.scala:30:73] assign _schedule_WIRE_33_0 = _schedule_WIRE_34; // @[Mux.scala:30:73] wire _schedule_T_587 = _schedule_T & _mshrs_0_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36] wire _schedule_T_588 = _schedule_T_1 & _mshrs_1_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36] wire _schedule_T_589 = _schedule_T_2 & _mshrs_2_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36] wire _schedule_T_590 = _schedule_T_3 & _mshrs_3_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36] wire _schedule_T_591 = _schedule_T_4 & _mshrs_4_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36] wire _schedule_T_592 = _schedule_T_5 & _mshrs_5_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36] wire _schedule_T_593 = _schedule_T_6 & _mshrs_6_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36] wire _schedule_T_594 = _schedule_T_7 & _mshrs_7_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36] wire _schedule_T_595 = _schedule_T_8 & _mshrs_8_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36] wire _schedule_T_596 = _schedule_T_9 & _mshrs_9_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36] wire _schedule_T_597 = _schedule_T_10 & _mshrs_10_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36] wire _schedule_T_599 = _schedule_T_587 \| _schedule_T_588; // @[Mux.scala:30:73] wire _schedule_T_600 = _schedule_T_599 \| _schedule_T_589; // @[Mux.scala:30:73] wire _schedule_T_601 = _schedule_T_600 \| _schedule_T_590; // @[Mux.scala:30:73] wire _schedule_T_602 = _schedule_T_601 \| _schedule_T_591; // @[Mux.scala:30:73] wire _schedule_T_603 = _schedule_T_602 \| _schedule_T_592; // @[Mux.scala:30:73] wire _schedule_T_604 = _schedule_T_603 \| _schedule_T_593; // @[Mux.scala:30:73] wire _schedule_T_605 = _schedule_T_604 \| _schedule_T_594; // @[Mux.scala:30:73] wire _schedule_T_606 = _schedule_T_605 \| _schedule_T_595; // @[Mux.scala:30:73] wire _schedule_T_607 = _schedule_T_606 \| _schedule_T_596; // @[Mux.scala:30:73] wire _schedule_T_608 = _schedule_T_607 \| _schedule_T_597; // @[Mux.scala:30:73] wire _schedule_T_609 = _schedule_T_608; // @[Mux.scala:30:73] assign _schedule_WIRE_35 = _schedule_T_609; // @[Mux.scala:30:73] assign _schedule_WIRE_33_1 = _schedule_WIRE_35; // @[Mux.scala:30:73] wire _schedule_T_610 = _schedule_T & _mshrs_0_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36] wire _schedule_T_611 = _schedule_T_1 & _mshrs_1_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36] wire _schedule_T_612 = _schedule_T_2 & _mshrs_2_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36] wire _schedule_T_613 = _schedule_T_3 & _mshrs_3_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36] wire _schedule_T_614 = _schedule_T_4 & _mshrs_4_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36] wire _schedule_T_615 = _schedule_T_5 & _mshrs_5_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36] wire _schedule_T_616 = _schedule_T_6 & _mshrs_6_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36] wire _schedule_T_617 = _schedule_T_7 & _mshrs_7_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36] wire _schedule_T_618 = _schedule_T_8 & _mshrs_8_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36] wire _schedule_T_619 = _schedule_T_9 & _mshrs_9_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36] wire _schedule_T_620 = _schedule_T_10 & _mshrs_10_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36] wire _schedule_T_621 = _schedule_T_11 & _mshrs_11_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36] wire _schedule_T_622 = _schedule_T_610 \| _schedule_T_611; // @[Mux.scala:30:73] wire _schedule_T_623 = _schedule_T_622 \| _schedule_T_612; // @[Mux.scala:30:73] wire _schedule_T_624 = _schedule_T_623 \| _schedule_T_613; // @[Mux.scala:30:73] wire _schedule_T_625 = _schedule_T_624 \| _schedule_T_614; // @[Mux.scala:30:73] wire _schedule_T_626 = _schedule_T_625 \| _schedule_T_615; // @[Mux.scala:30:73] wire _schedule_T_627 = _schedule_T_626 \| _schedule_T_616; // @[Mux.scala:30:73] wire _schedule_T_628 = _schedule_T_627 \| _schedule_T_617; // @[Mux.scala:30:73] wire _schedule_T_629 = _schedule_T_628 \| _schedule_T_618; // @[Mux.scala:30:73] wire _schedule_T_630 = _schedule_T_629 \| _schedule_T_619; // @[Mux.scala:30:73] wire _schedule_T_631 = _schedule_T_630 \| _schedule_T_620; // @[Mux.scala:30:73] wire _schedule_T_632 = _schedule_T_631 \| _schedule_T_621; // @[Mux.scala:30:73] assign _schedule_WIRE_36 = _schedule_T_632; // @[Mux.scala:30:73] assign _schedule_WIRE_33_2 = _schedule_WIRE_36; // @[Mux.scala:30:73] wire _schedule_T_633 = _schedule_T & _mshrs_0_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_634 = _schedule_T_1 & _mshrs_1_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_635 = _schedule_T_2 & _mshrs_2_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_636 = _schedule_T_3 & _mshrs_3_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_637 = _schedule_T_4 & _mshrs_4_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_638 = _schedule_T_5 & _mshrs_5_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_639 = _schedule_T_6 & _mshrs_6_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_640 = _schedule_T_7 & _mshrs_7_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_641 = _schedule_T_8 & _mshrs_8_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_642 = _schedule_T_9 & _mshrs_9_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_643 = _schedule_T_10 & _mshrs_10_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_644 = _schedule_T_11 & _mshrs_11_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_645 = _schedule_T_633 \| _schedule_T_634; // @[Mux.scala:30:73] wire _schedule_T_646 = _schedule_T_645 \| _schedule_T_635; // @[Mux.scala:30:73] wire _schedule_T_647 = _schedule_T_646 \| _schedule_T_636; // @[Mux.scala:30:73] wire _schedule_T_648 = _schedule_T_647 \| _schedule_T_637; // @[Mux.scala:30:73] wire _schedule_T_649 = _schedule_T_648 \| _schedule_T_638; // @[Mux.scala:30:73] wire _schedule_T_650 = _schedule_T_649 \| _schedule_T_639; // @[Mux.scala:30:73] wire _schedule_T_651 = _schedule_T_650 \| _schedule_T_640; // @[Mux.scala:30:73] wire _schedule_T_652 = _schedule_T_651 \| _schedule_T_641; // @[Mux.scala:30:73] wire _schedule_T_653 = _schedule_T_652 \| _schedule_T_642; // @[Mux.scala:30:73] wire _schedule_T_654 = _schedule_T_653 \| _schedule_T_643; // @[Mux.scala:30:73] wire _schedule_T_655 = _schedule_T_654 \| _schedule_T_644; // @[Mux.scala:30:73] assign _schedule_WIRE_37 = _schedule_T_655; // @[Mux.scala:30:73] assign _schedule_WIRE_19_valid = _schedule_WIRE_37; // @[Mux.scala:30:73] wire _schedule_WIRE_47; // @[Mux.scala:30:73] assign schedule_c_valid = _schedule_WIRE_38_valid; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_39_opcode; // @[Mux.scala:30:73] assign schedule_c_bits_opcode = _schedule_WIRE_38_bits_opcode; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_39_param; // @[Mux.scala:30:73] assign schedule_c_bits_param = _schedule_WIRE_38_bits_param; // @[Mux.scala:30:73] wire [8:0] _schedule_WIRE_39_tag; // @[Mux.scala:30:73] assign schedule_c_bits_tag = _schedule_WIRE_38_bits_tag; // @[Mux.scala:30:73] wire [10:0] _schedule_WIRE_39_set; // @[Mux.scala:30:73] assign schedule_c_bits_set = _schedule_WIRE_38_bits_set; // @[Mux.scala:30:73] wire [3:0] _schedule_WIRE_39_way; // @[Mux.scala:30:73] assign schedule_c_bits_way = _schedule_WIRE_38_bits_way; // @[Mux.scala:30:73] wire _schedule_WIRE_39_dirty; // @[Mux.scala:30:73] assign schedule_c_bits_dirty = _schedule_WIRE_38_bits_dirty; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_46; // @[Mux.scala:30:73] assign _schedule_WIRE_38_bits_opcode = _schedule_WIRE_39_opcode; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_45; // @[Mux.scala:30:73] assign _schedule_WIRE_38_bits_param = _schedule_WIRE_39_param; // @[Mux.scala:30:73] wire [8:0] _schedule_WIRE_43; // @[Mux.scala:30:73] assign _schedule_WIRE_38_bits_tag = _schedule_WIRE_39_tag; // @[Mux.scala:30:73] wire [10:0] _schedule_WIRE_42; // @[Mux.scala:30:73] assign _schedule_WIRE_38_bits_set = _schedule_WIRE_39_set; // @[Mux.scala:30:73] wire [3:0] _schedule_WIRE_41; // @[Mux.scala:30:73] assign _schedule_WIRE_38_bits_way = _schedule_WIRE_39_way; // @[Mux.scala:30:73] wire _schedule_WIRE_40; // @[Mux.scala:30:73] assign _schedule_WIRE_38_bits_dirty = _schedule_WIRE_39_dirty; // @[Mux.scala:30:73] wire _schedule_T_656 = _schedule_T & _mshrs_0_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_657 = _schedule_T_1 & _mshrs_1_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_658 = _schedule_T_2 & _mshrs_2_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_659 = _schedule_T_3 & _mshrs_3_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_660 = _schedule_T_4 & _mshrs_4_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_661 = _schedule_T_5 & _mshrs_5_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_662 = _schedule_T_6 & _mshrs_6_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_663 = _schedule_T_7 & _mshrs_7_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_664 = _schedule_T_8 & _mshrs_8_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_665 = _schedule_T_9 & _mshrs_9_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_666 = _schedule_T_10 & _mshrs_10_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_667 = _schedule_T_11 & _mshrs_11_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_668 = _schedule_T_656 \| _schedule_T_657; // @[Mux.scala:30:73] wire _schedule_T_669 = _schedule_T_668 \| _schedule_T_658; // @[Mux.scala:30:73] wire _schedule_T_670 = _schedule_T_669 \| _schedule_T_659; // @[Mux.scala:30:73] wire _schedule_T_671 = _schedule_T_670 \| _schedule_T_660; // @[Mux.scala:30:73] wire _schedule_T_672 = _schedule_T_671 \| _schedule_T_661; // @[Mux.scala:30:73] wire _schedule_T_673 = _schedule_T_672 \| _schedule_T_662; // @[Mux.scala:30:73] wire _schedule_T_674 = _schedule_T_673 \| _schedule_T_663; // @[Mux.scala:30:73] wire _schedule_T_675 = _schedule_T_674 \| _schedule_T_664; // @[Mux.scala:30:73] wire _schedule_T_676 = _schedule_T_675 \| _schedule_T_665; // @[Mux.scala:30:73] wire _schedule_T_677 = _schedule_T_676 \| _schedule_T_666; // @[Mux.scala:30:73] wire _schedule_T_678 = _schedule_T_677 \| _schedule_T_667; // @[Mux.scala:30:73] assign _schedule_WIRE_40 = _schedule_T_678; // @[Mux.scala:30:73] assign _schedule_WIRE_39_dirty = _schedule_WIRE_40; // @[Mux.scala:30:73] wire [3:0] _schedule_T_679 = _schedule_T ? _mshrs_0_io_schedule_bits_c_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _schedule_T_680 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_c_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _schedule_T_681 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_c_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _schedule_T_682 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_c_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _schedule_T_683 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_c_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _schedule_T_684 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_c_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _schedule_T_685 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_c_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _schedule_T_686 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_c_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _schedule_T_687 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_c_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _schedule_T_688 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_c_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _schedule_T_689 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_c_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _schedule_T_690 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_c_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _schedule_T_691 = _schedule_T_679 \| _schedule_T_680; // @[Mux.scala:30:73] wire [3:0] _schedule_T_692 = _schedule_T_691 \| _schedule_T_681; // @[Mux.scala:30:73] wire [3:0] _schedule_T_693 = _schedule_T_692 \| _schedule_T_682; // @[Mux.scala:30:73] wire [3:0] _schedule_T_694 = _schedule_T_693 \| _schedule_T_683; // @[Mux.scala:30:73] wire [3:0] _schedule_T_695 = _schedule_T_694 \| _schedule_T_684; // @[Mux.scala:30:73] wire [3:0] _schedule_T_696 = _schedule_T_695 \| _schedule_T_685; // @[Mux.scala:30:73] wire [3:0] _schedule_T_697 = _schedule_T_696 \| _schedule_T_686; // @[Mux.scala:30:73] wire [3:0] _schedule_T_698 = _schedule_T_697 \| _schedule_T_687; // @[Mux.scala:30:73] wire [3:0] _schedule_T_699 = _schedule_T_698 \| _schedule_T_688; // @[Mux.scala:30:73] wire [3:0] _schedule_T_700 = _schedule_T_699 \| _schedule_T_689; // @[Mux.scala:30:73] wire [3:0] _schedule_T_701 = _schedule_T_700 \| _schedule_T_690; // @[Mux.scala:30:73] assign _schedule_WIRE_41 = _schedule_T_701; // @[Mux.scala:30:73] assign _schedule_WIRE_39_way = _schedule_WIRE_41; // @[Mux.scala:30:73] wire [10:0] _schedule_T_702 = _schedule_T ? _mshrs_0_io_schedule_bits_c_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_703 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_c_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_704 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_c_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_705 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_c_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_706 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_c_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_707 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_c_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_708 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_c_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_709 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_c_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_710 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_c_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_711 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_c_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_712 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_c_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_713 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_c_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_714 = _schedule_T_702 \| _schedule_T_703; // @[Mux.scala:30:73] wire [10:0] _schedule_T_715 = _schedule_T_714 \| _schedule_T_704; // @[Mux.scala:30:73] wire [10:0] _schedule_T_716 = _schedule_T_715 \| _schedule_T_705; // @[Mux.scala:30:73] wire [10:0] _schedule_T_717 = _schedule_T_716 \| _schedule_T_706; // @[Mux.scala:30:73] wire [10:0] _schedule_T_718 = _schedule_T_717 \| _schedule_T_707; // @[Mux.scala:30:73] wire [10:0] _schedule_T_719 = _schedule_T_718 \| _schedule_T_708; // @[Mux.scala:30:73] wire [10:0] _schedule_T_720 = _schedule_T_719 \| _schedule_T_709; // @[Mux.scala:30:73] wire [10:0] _schedule_T_721 = _schedule_T_720 \| _schedule_T_710; // @[Mux.scala:30:73] wire [10:0] _schedule_T_722 = _schedule_T_721 \| _schedule_T_711; // @[Mux.scala:30:73] wire [10:0] _schedule_T_723 = _schedule_T_722 \| _schedule_T_712; // @[Mux.scala:30:73] wire [10:0] _schedule_T_724 = _schedule_T_723 \| _schedule_T_713; // @[Mux.scala:30:73] assign _schedule_WIRE_42 = _schedule_T_724; // @[Mux.scala:30:73] assign _schedule_WIRE_39_set = _schedule_WIRE_42; // @[Mux.scala:30:73] wire [8:0] _schedule_T_725 = _schedule_T ? _mshrs_0_io_schedule_bits_c_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_726 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_c_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_727 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_c_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_728 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_c_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_729 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_c_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_730 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_c_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_731 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_c_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_732 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_c_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_733 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_c_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_734 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_c_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_735 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_c_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_736 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_c_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_737 = _schedule_T_725 \| _schedule_T_726; // @[Mux.scala:30:73] wire [8:0] _schedule_T_738 = _schedule_T_737 \| _schedule_T_727; // @[Mux.scala:30:73] wire [8:0] _schedule_T_739 = _schedule_T_738 \| _schedule_T_728; // @[Mux.scala:30:73] wire [8:0] _schedule_T_740 = _schedule_T_739 \| _schedule_T_729; // @[Mux.scala:30:73] wire [8:0] _schedule_T_741 = _schedule_T_740 \| _schedule_T_730; // @[Mux.scala:30:73] wire [8:0] _schedule_T_742 = _schedule_T_741 \| _schedule_T_731; // @[Mux.scala:30:73] wire [8:0] _schedule_T_743 = _schedule_T_742 \| _schedule_T_732; // @[Mux.scala:30:73] wire [8:0] _schedule_T_744 = _schedule_T_743 \| _schedule_T_733; // @[Mux.scala:30:73] wire [8:0] _schedule_T_745 = _schedule_T_744 \| _schedule_T_734; // @[Mux.scala:30:73] wire [8:0] _schedule_T_746 = _schedule_T_745 \| _schedule_T_735; // @[Mux.scala:30:73] wire [8:0] _schedule_T_747 = _schedule_T_746 \| _schedule_T_736; // @[Mux.scala:30:73] assign _schedule_WIRE_43 = _schedule_T_747; // @[Mux.scala:30:73] assign _schedule_WIRE_39_tag = _schedule_WIRE_43; // @[Mux.scala:30:73] wire [2:0] _schedule_T_771 = _schedule_T ? _mshrs_0_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_772 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_773 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_774 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_775 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_776 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_777 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_778 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_779 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_780 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_781 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_782 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_783 = _schedule_T_771 \| _schedule_T_772; // @[Mux.scala:30:73] wire [2:0] _schedule_T_784 = _schedule_T_783 \| _schedule_T_773; // @[Mux.scala:30:73] wire [2:0] _schedule_T_785 = _schedule_T_784 \| _schedule_T_774; // @[Mux.scala:30:73] wire [2:0] _schedule_T_786 = _schedule_T_785 \| _schedule_T_775; // @[Mux.scala:30:73] wire [2:0] _schedule_T_787 = _schedule_T_786 \| _schedule_T_776; // @[Mux.scala:30:73] wire [2:0] _schedule_T_788 = _schedule_T_787 \| _schedule_T_777; // @[Mux.scala:30:73] wire [2:0] _schedule_T_789 = _schedule_T_788 \| _schedule_T_778; // @[Mux.scala:30:73] wire [2:0] _schedule_T_790 = _schedule_T_789 \| _schedule_T_779; // @[Mux.scala:30:73] wire [2:0] _schedule_T_791 = _schedule_T_790 \| _schedule_T_780; // @[Mux.scala:30:73] wire [2:0] _schedule_T_792 = _schedule_T_791 \| _schedule_T_781; // @[Mux.scala:30:73] wire [2:0] _schedule_T_793 = _schedule_T_792 \| _schedule_T_782; // @[Mux.scala:30:73] assign _schedule_WIRE_45 = _schedule_T_793; // @[Mux.scala:30:73] assign _schedule_WIRE_39_param = _schedule_WIRE_45; // @[Mux.scala:30:73] wire [2:0] _schedule_T_794 = _schedule_T ? _mshrs_0_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_795 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_796 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_797 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_798 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_799 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_800 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_801 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_802 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_803 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_804 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_805 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_806 = _schedule_T_794 \| _schedule_T_795; // @[Mux.scala:30:73] wire [2:0] _schedule_T_807 = _schedule_T_806 \| _schedule_T_796; // @[Mux.scala:30:73] wire [2:0] _schedule_T_808 = _schedule_T_807 \| _schedule_T_797; // @[Mux.scala:30:73] wire [2:0] _schedule_T_809 = _schedule_T_808 \| _schedule_T_798; // @[Mux.scala:30:73] wire [2:0] _schedule_T_810 = _schedule_T_809 \| _schedule_T_799; // @[Mux.scala:30:73] wire [2:0] _schedule_T_811 = _schedule_T_810 \| _schedule_T_800; // @[Mux.scala:30:73] wire [2:0] _schedule_T_812 = _schedule_T_811 \| _schedule_T_801; // @[Mux.scala:30:73] wire [2:0] _schedule_T_813 = _schedule_T_812 \| _schedule_T_802; // @[Mux.scala:30:73] wire [2:0] _schedule_T_814 = _schedule_T_813 \| _schedule_T_803; // @[Mux.scala:30:73] wire [2:0] _schedule_T_815 = _schedule_T_814 \| _schedule_T_804; // @[Mux.scala:30:73] wire [2:0] _schedule_T_816 = _schedule_T_815 \| _schedule_T_805; // @[Mux.scala:30:73] assign _schedule_WIRE_46 = _schedule_T_816; // @[Mux.scala:30:73] assign _schedule_WIRE_39_opcode = _schedule_WIRE_46; // @[Mux.scala:30:73] wire _schedule_T_817 = _schedule_T & _mshrs_0_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_818 = _schedule_T_1 & _mshrs_1_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_819 = _schedule_T_2 & _mshrs_2_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_820 = _schedule_T_3 & _mshrs_3_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_821 = _schedule_T_4 & _mshrs_4_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_822 = _schedule_T_5 & _mshrs_5_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_823 = _schedule_T_6 & _mshrs_6_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_824 = _schedule_T_7 & _mshrs_7_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_825 = _schedule_T_8 & _mshrs_8_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_826 = _schedule_T_9 & _mshrs_9_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_827 = _schedule_T_10 & _mshrs_10_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_828 = _schedule_T_11 & _mshrs_11_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_829 = _schedule_T_817 \| _schedule_T_818; // @[Mux.scala:30:73] wire _schedule_T_830 = _schedule_T_829 \| _schedule_T_819; // @[Mux.scala:30:73] wire _schedule_T_831 = _schedule_T_830 \| _schedule_T_820; // @[Mux.scala:30:73] wire _schedule_T_832 = _schedule_T_831 \| _schedule_T_821; // @[Mux.scala:30:73] wire _schedule_T_833 = _schedule_T_832 \| _schedule_T_822; // @[Mux.scala:30:73] wire _schedule_T_834 = _schedule_T_833 \| _schedule_T_823; // @[Mux.scala:30:73] wire _schedule_T_835 = _schedule_T_834 \| _schedule_T_824; // @[Mux.scala:30:73] wire _schedule_T_836 = _schedule_T_835 \| _schedule_T_825; // @[Mux.scala:30:73] wire _schedule_T_837 = _schedule_T_836 \| _schedule_T_826; // @[Mux.scala:30:73] wire _schedule_T_838 = _schedule_T_837 \| _schedule_T_827; // @[Mux.scala:30:73] wire _schedule_T_839 = _schedule_T_838 \| _schedule_T_828; // @[Mux.scala:30:73] assign _schedule_WIRE_47 = _schedule_T_839; // @[Mux.scala:30:73] assign _schedule_WIRE_38_valid = _schedule_WIRE_47; // @[Mux.scala:30:73] wire _schedule_WIRE_54; // @[Mux.scala:30:73] assign schedule_b_valid = _schedule_WIRE_48_valid; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_49_param; // @[Mux.scala:30:73] assign schedule_b_bits_param = _schedule_WIRE_48_bits_param; // @[Mux.scala:30:73] wire [8:0] _schedule_WIRE_49_tag; // @[Mux.scala:30:73] assign schedule_b_bits_tag = _schedule_WIRE_48_bits_tag; // @[Mux.scala:30:73] wire [10:0] _schedule_WIRE_49_set; // @[Mux.scala:30:73] assign schedule_b_bits_set = _schedule_WIRE_48_bits_set; // @[Mux.scala:30:73] wire _schedule_WIRE_49_clients; // @[Mux.scala:30:73] assign schedule_b_bits_clients = _schedule_WIRE_48_bits_clients; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_53; // @[Mux.scala:30:73] assign _schedule_WIRE_48_bits_param = _schedule_WIRE_49_param; // @[Mux.scala:30:73] wire [8:0] _schedule_WIRE_52; // @[Mux.scala:30:73] assign _schedule_WIRE_48_bits_tag = _schedule_WIRE_49_tag; // @[Mux.scala:30:73] wire [10:0] _schedule_WIRE_51; // @[Mux.scala:30:73] assign _schedule_WIRE_48_bits_set = _schedule_WIRE_49_set; // @[Mux.scala:30:73] wire _schedule_WIRE_50; // @[Mux.scala:30:73] assign _schedule_WIRE_48_bits_clients = _schedule_WIRE_49_clients; // @[Mux.scala:30:73] wire _schedule_T_840 = _schedule_T & _mshrs_0_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36] wire _schedule_T_841 = _schedule_T_1 & _mshrs_1_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36] wire _schedule_T_842 = _schedule_T_2 & _mshrs_2_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36] wire _schedule_T_843 = _schedule_T_3 & _mshrs_3_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36] wire _schedule_T_844 = _schedule_T_4 & _mshrs_4_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36] wire _schedule_T_845 = _schedule_T_5 & _mshrs_5_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36] wire _schedule_T_846 = _schedule_T_6 & _mshrs_6_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36] wire _schedule_T_847 = _schedule_T_7 & _mshrs_7_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36] wire _schedule_T_848 = _schedule_T_8 & _mshrs_8_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36] wire _schedule_T_849 = _schedule_T_9 & _mshrs_9_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36] wire _schedule_T_850 = _schedule_T_10 & _mshrs_10_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36] wire _schedule_T_851 = _schedule_T_11 & _mshrs_11_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36] wire _schedule_T_852 = _schedule_T_840 \| _schedule_T_841; // @[Mux.scala:30:73] wire _schedule_T_853 = _schedule_T_852 \| _schedule_T_842; // @[Mux.scala:30:73] wire _schedule_T_854 = _schedule_T_853 \| _schedule_T_843; // @[Mux.scala:30:73] wire _schedule_T_855 = _schedule_T_854 \| _schedule_T_844; // @[Mux.scala:30:73] wire _schedule_T_856 = _schedule_T_855 \| _schedule_T_845; // @[Mux.scala:30:73] wire _schedule_T_857 = _schedule_T_856 \| _schedule_T_846; // @[Mux.scala:30:73] wire _schedule_T_858 = _schedule_T_857 \| _schedule_T_847; // @[Mux.scala:30:73] wire _schedule_T_859 = _schedule_T_858 \| _schedule_T_848; // @[Mux.scala:30:73] wire _schedule_T_860 = _schedule_T_859 \| _schedule_T_849; // @[Mux.scala:30:73] wire _schedule_T_861 = _schedule_T_860 \| _schedule_T_850; // @[Mux.scala:30:73] wire _schedule_T_862 = _schedule_T_861 \| _schedule_T_851; // @[Mux.scala:30:73] assign _schedule_WIRE_50 = _schedule_T_862; // @[Mux.scala:30:73] assign _schedule_WIRE_49_clients = _schedule_WIRE_50; // @[Mux.scala:30:73] wire [10:0] _schedule_T_863 = _schedule_T ? _mshrs_0_io_schedule_bits_b_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_864 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_b_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_865 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_b_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_866 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_b_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_867 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_b_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_868 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_b_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_869 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_b_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_870 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_b_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_871 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_b_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_872 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_b_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_873 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_b_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_874 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_b_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_875 = _schedule_T_863 \| _schedule_T_864; // @[Mux.scala:30:73] wire [10:0] _schedule_T_876 = _schedule_T_875 \| _schedule_T_865; // @[Mux.scala:30:73] wire [10:0] _schedule_T_877 = _schedule_T_876 \| _schedule_T_866; // @[Mux.scala:30:73] wire [10:0] _schedule_T_878 = _schedule_T_877 \| _schedule_T_867; // @[Mux.scala:30:73] wire [10:0] _schedule_T_879 = _schedule_T_878 \| _schedule_T_868; // @[Mux.scala:30:73] wire [10:0] _schedule_T_880 = _schedule_T_879 \| _schedule_T_869; // @[Mux.scala:30:73] wire [10:0] _schedule_T_881 = _schedule_T_880 \| _schedule_T_870; // @[Mux.scala:30:73] wire [10:0] _schedule_T_882 = _schedule_T_881 \| _schedule_T_871; // @[Mux.scala:30:73] wire [10:0] _schedule_T_883 = _schedule_T_882 \| _schedule_T_872; // @[Mux.scala:30:73] wire [10:0] _schedule_T_884 = _schedule_T_883 \| _schedule_T_873; // @[Mux.scala:30:73] wire [10:0] _schedule_T_885 = _schedule_T_884 \| _schedule_T_874; // @[Mux.scala:30:73] assign _schedule_WIRE_51 = _schedule_T_885; // @[Mux.scala:30:73] assign _schedule_WIRE_49_set = _schedule_WIRE_51; // @[Mux.scala:30:73] wire [8:0] _schedule_T_886 = _schedule_T ? _mshrs_0_io_schedule_bits_b_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_887 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_b_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_888 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_b_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_889 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_b_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_890 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_b_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_891 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_b_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_892 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_b_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_893 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_b_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_894 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_b_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_895 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_b_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_896 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_b_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_897 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_b_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_898 = _schedule_T_886 \| _schedule_T_887; // @[Mux.scala:30:73] wire [8:0] _schedule_T_899 = _schedule_T_898 \| _schedule_T_888; // @[Mux.scala:30:73] wire [8:0] _schedule_T_900 = _schedule_T_899 \| _schedule_T_889; // @[Mux.scala:30:73] wire [8:0] _schedule_T_901 = _schedule_T_900 \| _schedule_T_890; // @[Mux.scala:30:73] wire [8:0] _schedule_T_902 = _schedule_T_901 \| _schedule_T_891; // @[Mux.scala:30:73] wire [8:0] _schedule_T_903 = _schedule_T_902 \| _schedule_T_892; // @[Mux.scala:30:73] wire [8:0] _schedule_T_904 = _schedule_T_903 \| _schedule_T_893; // @[Mux.scala:30:73] wire [8:0] _schedule_T_905 = _schedule_T_904 \| _schedule_T_894; // @[Mux.scala:30:73] wire [8:0] _schedule_T_906 = _schedule_T_905 \| _schedule_T_895; // @[Mux.scala:30:73] wire [8:0] _schedule_T_907 = _schedule_T_906 \| _schedule_T_896; // @[Mux.scala:30:73] wire [8:0] _schedule_T_908 = _schedule_T_907 \| _schedule_T_897; // @[Mux.scala:30:73] assign _schedule_WIRE_52 = _schedule_T_908; // @[Mux.scala:30:73] assign _schedule_WIRE_49_tag = _schedule_WIRE_52; // @[Mux.scala:30:73] wire [2:0] _schedule_T_909 = _schedule_T ? _mshrs_0_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_910 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_911 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_912 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_913 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_914 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_915 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_916 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_917 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_918 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_919 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_920 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_921 = _schedule_T_909 \| _schedule_T_910; // @[Mux.scala:30:73] wire [2:0] _schedule_T_922 = _schedule_T_921 \| _schedule_T_911; // @[Mux.scala:30:73] wire [2:0] _schedule_T_923 = _schedule_T_922 \| _schedule_T_912; // @[Mux.scala:30:73] wire [2:0] _schedule_T_924 = _schedule_T_923 \| _schedule_T_913; // @[Mux.scala:30:73] wire [2:0] _schedule_T_925 = _schedule_T_924 \| _schedule_T_914; // @[Mux.scala:30:73] wire [2:0] _schedule_T_926 = _schedule_T_925 \| _schedule_T_915; // @[Mux.scala:30:73] wire [2:0] _schedule_T_927 = _schedule_T_926 \| _schedule_T_916; // @[Mux.scala:30:73] wire [2:0] _schedule_T_928 = _schedule_T_927 \| _schedule_T_917; // @[Mux.scala:30:73] wire [2:0] _schedule_T_929 = _schedule_T_928 \| _schedule_T_918; // @[Mux.scala:30:73] wire [2:0] _schedule_T_930 = _schedule_T_929 \| _schedule_T_919; // @[Mux.scala:30:73] wire [2:0] _schedule_T_931 = _schedule_T_930 \| _schedule_T_920; // @[Mux.scala:30:73] assign _schedule_WIRE_53 = _schedule_T_931; // @[Mux.scala:30:73] assign _schedule_WIRE_49_param = _schedule_WIRE_53; // @[Mux.scala:30:73] wire _schedule_T_932 = _schedule_T & _mshrs_0_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_933 = _schedule_T_1 & _mshrs_1_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_934 = _schedule_T_2 & _mshrs_2_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_935 = _schedule_T_3 & _mshrs_3_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_936 = _schedule_T_4 & _mshrs_4_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_937 = _schedule_T_5 & _mshrs_5_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_938 = _schedule_T_6 & _mshrs_6_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_939 = _schedule_T_7 & _mshrs_7_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_940 = _schedule_T_8 & _mshrs_8_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_941 = _schedule_T_9 & _mshrs_9_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_942 = _schedule_T_10 & _mshrs_10_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_943 = _schedule_T_11 & _mshrs_11_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_944 = _schedule_T_932 \| _schedule_T_933; // @[Mux.scala:30:73] wire _schedule_T_945 = _schedule_T_944 \| _schedule_T_934; // @[Mux.scala:30:73] wire _schedule_T_946 = _schedule_T_945 \| _schedule_T_935; // @[Mux.scala:30:73] wire _schedule_T_947 = _schedule_T_946 \| _schedule_T_936; // @[Mux.scala:30:73] wire _schedule_T_948 = _schedule_T_947 \| _schedule_T_937; // @[Mux.scala:30:73] wire _schedule_T_949 = _schedule_T_948 \| _schedule_T_938; // @[Mux.scala:30:73] wire _schedule_T_950 = _schedule_T_949 \| _schedule_T_939; // @[Mux.scala:30:73] wire _schedule_T_951 = _schedule_T_950 \| _schedule_T_940; // @[Mux.scala:30:73] wire _schedule_T_952 = _schedule_T_951 \| _schedule_T_941; // @[Mux.scala:30:73] wire _schedule_T_953 = _schedule_T_952 \| _schedule_T_942; // @[Mux.scala:30:73] wire _schedule_T_954 = _schedule_T_953 \| _schedule_T_943; // @[Mux.scala:30:73] assign _schedule_WIRE_54 = _schedule_T_954; // @[Mux.scala:30:73] assign _schedule_WIRE_48_valid = _schedule_WIRE_54; // @[Mux.scala:30:73] wire _schedule_WIRE_62; // @[Mux.scala:30:73] assign schedule_a_valid = _schedule_WIRE_55_valid; // @[Mux.scala:30:73] wire [8:0] _schedule_WIRE_56_tag; // @[Mux.scala:30:73] assign schedule_a_bits_tag = _schedule_WIRE_55_bits_tag; // @[Mux.scala:30:73] wire [10:0] _schedule_WIRE_56_set; // @[Mux.scala:30:73] assign schedule_a_bits_set = _schedule_WIRE_55_bits_set; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_56_param; // @[Mux.scala:30:73] assign schedule_a_bits_param = _schedule_WIRE_55_bits_param; // @[Mux.scala:30:73] wire _schedule_WIRE_56_block; // @[Mux.scala:30:73] assign schedule_a_bits_block = _schedule_WIRE_55_bits_block; // @[Mux.scala:30:73] wire [8:0] _schedule_WIRE_61; // @[Mux.scala:30:73] assign _schedule_WIRE_55_bits_tag = _schedule_WIRE_56_tag; // @[Mux.scala:30:73] wire [10:0] _schedule_WIRE_60; // @[Mux.scala:30:73] assign _schedule_WIRE_55_bits_set = _schedule_WIRE_56_set; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_59; // @[Mux.scala:30:73] assign _schedule_WIRE_55_bits_param = _schedule_WIRE_56_param; // @[Mux.scala:30:73] wire _schedule_WIRE_57; // @[Mux.scala:30:73] assign _schedule_WIRE_55_bits_block = _schedule_WIRE_56_block; // @[Mux.scala:30:73] wire _schedule_T_955 = _schedule_T & _mshrs_0_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36] wire _schedule_T_956 = _schedule_T_1 & _mshrs_1_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36] wire _schedule_T_957 = _schedule_T_2 & _mshrs_2_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36] wire _schedule_T_958 = _schedule_T_3 & _mshrs_3_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36] wire _schedule_T_959 = _schedule_T_4 & _mshrs_4_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36] wire _schedule_T_960 = _schedule_T_5 & _mshrs_5_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36] wire _schedule_T_961 = _schedule_T_6 & _mshrs_6_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36] wire _schedule_T_962 = _schedule_T_7 & _mshrs_7_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36] wire _schedule_T_963 = _schedule_T_8 & _mshrs_8_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36] wire _schedule_T_964 = _schedule_T_9 & _mshrs_9_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36] wire _schedule_T_965 = _schedule_T_10 & _mshrs_10_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36] wire _schedule_T_966 = _schedule_T_11 & _mshrs_11_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36] wire _schedule_T_967 = _schedule_T_955 \| _schedule_T_956; // @[Mux.scala:30:73] wire _schedule_T_968 = _schedule_T_967 \| _schedule_T_957; // @[Mux.scala:30:73] wire _schedule_T_969 = _schedule_T_968 \| _schedule_T_958; // @[Mux.scala:30:73] wire _schedule_T_970 = _schedule_T_969 \| _schedule_T_959; // @[Mux.scala:30:73] wire _schedule_T_971 = _schedule_T_970 \| _schedule_T_960; // @[Mux.scala:30:73] wire _schedule_T_972 = _schedule_T_971 \| _schedule_T_961; // @[Mux.scala:30:73] wire _schedule_T_973 = _schedule_T_972 \| _schedule_T_962; // @[Mux.scala:30:73] wire _schedule_T_974 = _schedule_T_973 \| _schedule_T_963; // @[Mux.scala:30:73] wire _schedule_T_975 = _schedule_T_974 \| _schedule_T_964; // @[Mux.scala:30:73] wire _schedule_T_976 = _schedule_T_975 \| _schedule_T_965; // @[Mux.scala:30:73] wire _schedule_T_977 = _schedule_T_976 \| _schedule_T_966; // @[Mux.scala:30:73] assign _schedule_WIRE_57 = _schedule_T_977; // @[Mux.scala:30:73] assign _schedule_WIRE_56_block = _schedule_WIRE_57; // @[Mux.scala:30:73] wire [2:0] _schedule_T_1001 = _schedule_T ? _mshrs_0_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_1002 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_1003 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_1004 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_1005 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_1006 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_1007 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_1008 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_1009 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_1010 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_1011 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_1012 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_1013 = _schedule_T_1001 \| _schedule_T_1002; // @[Mux.scala:30:73] wire [2:0] _schedule_T_1014 = _schedule_T_1013 \| _schedule_T_1003; // @[Mux.scala:30:73] wire [2:0] _schedule_T_1015 = _schedule_T_1014 \| _schedule_T_1004; // @[Mux.scala:30:73] wire [2:0] _schedule_T_1016 = _schedule_T_1015 \| _schedule_T_1005; // @[Mux.scala:30:73] wire [2:0] _schedule_T_1017 = _schedule_T_1016 \| _schedule_T_1006; // @[Mux.scala:30:73] wire [2:0] _schedule_T_1018 = _schedule_T_1017 \| _schedule_T_1007; // @[Mux.scala:30:73] wire [2:0] _schedule_T_1019 = _schedule_T_1018 \| _schedule_T_1008; // @[Mux.scala:30:73] wire [2:0] _schedule_T_1020 = _schedule_T_1019 \| _schedule_T_1009; // @[Mux.scala:30:73] wire [2:0] _schedule_T_1021 = _schedule_T_1020 \| _schedule_T_1010; // @[Mux.scala:30:73] wire [2:0] _schedule_T_1022 = _schedule_T_1021 \| _schedule_T_1011; // @[Mux.scala:30:73] wire [2:0] _schedule_T_1023 = _schedule_T_1022 \| _schedule_T_1012; // @[Mux.scala:30:73] assign _schedule_WIRE_59 = _schedule_T_1023; // @[Mux.scala:30:73] assign _schedule_WIRE_56_param = _schedule_WIRE_59; // @[Mux.scala:30:73] wire [10:0] _schedule_T_1024 = _schedule_T ? _mshrs_0_io_schedule_bits_a_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_1025 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_a_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_1026 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_a_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_1027 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_a_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_1028 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_a_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_1029 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_a_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_1030 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_a_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_1031 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_a_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_1032 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_a_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_1033 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_a_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_1034 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_a_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_1035 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_a_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_1036 = _schedule_T_1024 \| _schedule_T_1025; // @[Mux.scala:30:73] wire [10:0] _schedule_T_1037 = _schedule_T_1036 \| _schedule_T_1026; // @[Mux.scala:30:73] wire [10:0] _schedule_T_1038 = _schedule_T_1037 \| _schedule_T_1027; // @[Mux.scala:30:73] wire [10:0] _schedule_T_1039 = _schedule_T_1038 \| _schedule_T_1028; // @[Mux.scala:30:73] wire [10:0] _schedule_T_1040 = _schedule_T_1039 \| _schedule_T_1029; // @[Mux.scala:30:73] wire [10:0] _schedule_T_1041 = _schedule_T_1040 \| _schedule_T_1030; // @[Mux.scala:30:73] wire [10:0] _schedule_T_1042 = _schedule_T_1041 \| _schedule_T_1031; // @[Mux.scala:30:73] wire [10:0] _schedule_T_1043 = _schedule_T_1042 \| _schedule_T_1032; // @[Mux.scala:30:73] wire [10:0] _schedule_T_1044 = _schedule_T_1043 \| _schedule_T_1033; // @[Mux.scala:30:73] wire [10:0] _schedule_T_1045 = _schedule_T_1044 \| _schedule_T_1034; // @[Mux.scala:30:73] wire [10:0] _schedule_T_1046 = _schedule_T_1045 \| _schedule_T_1035; // @[Mux.scala:30:73] assign _schedule_WIRE_60 = _schedule_T_1046; // @[Mux.scala:30:73] assign _schedule_WIRE_56_set = _schedule_WIRE_60; // @[Mux.scala:30:73] wire [8:0] _schedule_T_1047 = _schedule_T ? _mshrs_0_io_schedule_bits_a_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_1048 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_a_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_1049 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_a_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_1050 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_a_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_1051 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_a_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_1052 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_a_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_1053 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_a_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_1054 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_a_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_1055 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_a_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_1056 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_a_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_1057 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_a_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_1058 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_a_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_1059 = _schedule_T_1047 \| _schedule_T_1048; // @[Mux.scala:30:73] wire [8:0] _schedule_T_1060 = _schedule_T_1059 \| _schedule_T_1049; // @[Mux.scala:30:73] wire [8:0] _schedule_T_1061 = _schedule_T_1060 \| _schedule_T_1050; // @[Mux.scala:30:73] wire [8:0] _schedule_T_1062 = _schedule_T_1061 \| _schedule_T_1051; // @[Mux.scala:30:73] wire [8:0] _schedule_T_1063 = _schedule_T_1062 \| _schedule_T_1052; // @[Mux.scala:30:73] wire [8:0] _schedule_T_1064 = _schedule_T_1063 \| _schedule_T_1053; // @[Mux.scala:30:73] wire [8:0] _schedule_T_1065 = _schedule_T_1064 \| _schedule_T_1054; // @[Mux.scala:30:73] wire [8:0] _schedule_T_1066 = _schedule_T_1065 \| _schedule_T_1055; // @[Mux.scala:30:73] wire [8:0] _schedule_T_1067 = _schedule_T_1066 \| _schedule_T_1056; // @[Mux.scala:30:73] wire [8:0] _schedule_T_1068 = _schedule_T_1067 \| _schedule_T_1057; // @[Mux.scala:30:73] wire [8:0] _schedule_T_1069 = _schedule_T_1068 \| _schedule_T_1058; // @[Mux.scala:30:73] assign _schedule_WIRE_61 = _schedule_T_1069; // @[Mux.scala:30:73] assign _schedule_WIRE_56_tag = _schedule_WIRE_61; // @[Mux.scala:30:73] wire _schedule_T_1070 = _schedule_T & _mshrs_0_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_1071 = _schedule_T_1 & _mshrs_1_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_1072 = _schedule_T_2 & _mshrs_2_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_1073 = _schedule_T_3 & _mshrs_3_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_1074 = _schedule_T_4 & _mshrs_4_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_1075 = _schedule_T_5 & _mshrs_5_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_1076 = _schedule_T_6 & _mshrs_6_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_1077 = _schedule_T_7 & _mshrs_7_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_1078 = _schedule_T_8 & _mshrs_8_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_1079 = _schedule_T_9 & _mshrs_9_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_1080 = _schedule_T_10 & _mshrs_10_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_1081 = _schedule_T_11 & _mshrs_11_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_1082 = _schedule_T_1070 \| _schedule_T_1071; // @[Mux.scala:30:73] wire _schedule_T_1083 = _schedule_T_1082 \| _schedule_T_1072; // @[Mux.scala:30:73] wire _schedule_T_1084 = _schedule_T_1083 \| _schedule_T_1073; // @[Mux.scala:30:73] wire _schedule_T_1085 = _schedule_T_1084 \| _schedule_T_1074; // @[Mux.scala:30:73] wire _schedule_T_1086 = _schedule_T_1085 \| _schedule_T_1075; // @[Mux.scala:30:73] wire _schedule_T_1087 = _schedule_T_1086 \| _schedule_T_1076; // @[Mux.scala:30:73] wire _schedule_T_1088 = _schedule_T_1087 \| _schedule_T_1077; // @[Mux.scala:30:73] wire _schedule_T_1089 = _schedule_T_1088 \| _schedule_T_1078; // @[Mux.scala:30:73] wire _schedule_T_1090 = _schedule_T_1089 \| _schedule_T_1079; // @[Mux.scala:30:73] wire _schedule_T_1091 = _schedule_T_1090 \| _schedule_T_1080; // @[Mux.scala:30:73] wire _schedule_T_1092 = _schedule_T_1091 \| _schedule_T_1081; // @[Mux.scala:30:73] assign _schedule_WIRE_62 = _schedule_T_1092; // @[Mux.scala:30:73] assign _schedule_WIRE_55_valid = _schedule_WIRE_62; // @[Mux.scala:30:73] wire [8:0] _scheduleTag_T_12 = _scheduleTag_T ? _mshrs_0_io_status_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _scheduleTag_T_13 = _scheduleTag_T_1 ? _mshrs_1_io_status_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _scheduleTag_T_14 = _scheduleTag_T_2 ? _mshrs_2_io_status_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _scheduleTag_T_15 = _scheduleTag_T_3 ? _mshrs_3_io_status_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _scheduleTag_T_16 = _scheduleTag_T_4 ? _mshrs_4_io_status_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _scheduleTag_T_17 = _scheduleTag_T_5 ? _mshrs_5_io_status_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _scheduleTag_T_18 = _scheduleTag_T_6 ? _mshrs_6_io_status_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _scheduleTag_T_19 = _scheduleTag_T_7 ? _mshrs_7_io_status_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _scheduleTag_T_20 = _scheduleTag_T_8 ? _mshrs_8_io_status_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _scheduleTag_T_21 = _scheduleTag_T_9 ? _mshrs_9_io_status_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _scheduleTag_T_22 = _scheduleTag_T_10 ? _mshrs_10_io_status_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _scheduleTag_T_23 = _scheduleTag_T_11 ? _mshrs_11_io_status_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _scheduleTag_T_24 = _scheduleTag_T_12 \| _scheduleTag_T_13; // @[Mux.scala:30:73] wire [8:0] _scheduleTag_T_25 = _scheduleTag_T_24 \| _scheduleTag_T_14; // @[Mux.scala:30:73] wire [8:0] _scheduleTag_T_26 = _scheduleTag_T_25 \| _scheduleTag_T_15; // @[Mux.scala:30:73] wire [8:0] _scheduleTag_T_27 = _scheduleTag_T_26 \| _scheduleTag_T_16; // @[Mux.scala:30:73] wire [8:0] _scheduleTag_T_28 = _scheduleTag_T_27 \| _scheduleTag_T_17; // @[Mux.scala:30:73] wire [8:0] _scheduleTag_T_29 = _scheduleTag_T_28 \| _scheduleTag_T_18; // @[Mux.scala:30:73] wire [8:0] _scheduleTag_T_30 = _scheduleTag_T_29 \| _scheduleTag_T_19; // @[Mux.scala:30:73] wire [8:0] _scheduleTag_T_31 = _scheduleTag_T_30 \| _scheduleTag_T_20; // @[Mux.scala:30:73] wire [8:0] _scheduleTag_T_32 = _scheduleTag_T_31 \| _scheduleTag_T_21; // @[Mux.scala:30:73] wire [8:0] _scheduleTag_T_33 = _scheduleTag_T_32 \| _scheduleTag_T_22; // @[Mux.scala:30:73] wire [8:0] _scheduleTag_T_34 = _scheduleTag_T_33 \| _scheduleTag_T_23; // @[Mux.scala:30:73] wire [8:0] scheduleTag = _scheduleTag_T_34; // @[Mux.scala:30:73] wire [10:0] _scheduleSet_T_12 = _scheduleSet_T ? _mshrs_0_io_status_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _scheduleSet_T_13 = _scheduleSet_T_1 ? _mshrs_1_io_status_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _scheduleSet_T_14 = _scheduleSet_T_2 ? _mshrs_2_io_status_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _scheduleSet_T_15 = _scheduleSet_T_3 ? _mshrs_3_io_status_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _scheduleSet_T_16 = _scheduleSet_T_4 ? _mshrs_4_io_status_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _scheduleSet_T_17 = _scheduleSet_T_5 ? _mshrs_5_io_status_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _scheduleSet_T_18 = _scheduleSet_T_6 ? _mshrs_6_io_status_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _scheduleSet_T_19 = _scheduleSet_T_7 ? _mshrs_7_io_status_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _scheduleSet_T_20 = _scheduleSet_T_8 ? _mshrs_8_io_status_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _scheduleSet_T_21 = _scheduleSet_T_9 ? _mshrs_9_io_status_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _scheduleSet_T_22 = _scheduleSet_T_10 ? _mshrs_10_io_status_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _scheduleSet_T_23 = _scheduleSet_T_11 ? _mshrs_11_io_status_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _scheduleSet_T_24 = _scheduleSet_T_12 \| _scheduleSet_T_13; // @[Mux.scala:30:73] wire [10:0] _scheduleSet_T_25 = _scheduleSet_T_24 \| _scheduleSet_T_14; // @[Mux.scala:30:73] wire [10:0] _scheduleSet_T_26 = _scheduleSet_T_25 \| _scheduleSet_T_15; // @[Mux.scala:30:73] wire [10:0] _scheduleSet_T_27 = _scheduleSet_T_26 \| _scheduleSet_T_16; // @[Mux.scala:30:73] wire [10:0] _scheduleSet_T_28 = _scheduleSet_T_27 \| _scheduleSet_T_17; // @[Mux.scala:30:73] wire [10:0] _scheduleSet_T_29 = _scheduleSet_T_28 \| _scheduleSet_T_18; // @[Mux.scala:30:73] wire [10:0] _scheduleSet_T_30 = _scheduleSet_T_29 \| _scheduleSet_T_19; // @[Mux.scala:30:73] wire [10:0] _scheduleSet_T_31 = _scheduleSet_T_30 \| _scheduleSet_T_20; // @[Mux.scala:30:73] wire [10:0] _scheduleSet_T_32 = _scheduleSet_T_31 \| _scheduleSet_T_21; // @[Mux.scala:30:73] wire [10:0] _scheduleSet_T_33 = _scheduleSet_T_32 \| _scheduleSet_T_22; // @[Mux.scala:30:73] wire [10:0] _scheduleSet_T_34 = _scheduleSet_T_33 \| _scheduleSet_T_23; // @[Mux.scala:30:73] wire [10:0] scheduleSet = _scheduleSet_T_34; // @[Mux.scala:30:73] wire [10:0] _robin_filter_T = mshr_selectOH[11:1]; // @[package.scala:262:48] wire [11:0] _robin_filter_T_1 = {mshr_selectOH[11], mshr_selectOH[10:0] \| _robin_filter_T}; // @[Mux.scala:32:36] wire [9:0] _robin_filter_T_2 = _robin_filter_T_1[11:2]; // @[package.scala:262:{43,48}] wire [11:0] _robin_filter_T_3 = {_robin_filter_T_1[11:10], _robin_filter_T_1[9:0] \| _robin_filter_T_2}; // @[package.scala:262:{43,48}] wire [7:0] _robin_filter_T_4 = _robin_filter_T_3[11:4]; // @[package.scala:262:{43,48}] wire [11:0] _robin_filter_T_5 = {_robin_filter_T_3[11:8], _robin_filter_T_3[7:0] \| _robin_filter_T_4}; // @[package.scala:262:{43,48}] wire [3:0] _robin_filter_T_6 = _robin_filter_T_5[11:8]; // @[package.scala:262:{43,48}] wire [11:0] _robin_filter_T_7 = {_robin_filter_T_5[11:4], _robin_filter_T_5[3:0] \| _robin_filter_T_6}; // @[package.scala:262:{43,48}] wire [11:0] _robin_filter_T_8 = _robin_filter_T_7; // @[package.scala:262:43, :263:17] wire [11:0] _robin_filter_T_9 = ~_robin_filter_T_8; // @[package.scala:263:17] wire _schedule_c_bits_source_T = schedule_c_bits_opcode[1]; // @[Mux.scala:30:73] assign _schedule_c_bits_source_T_1 = _schedule_c_bits_source_T ? mshr_select : 4'h0; // @[OneHot.scala:32:10] assign schedule_c_bits_source = _schedule_c_bits_source_T_1; // @[Mux.scala:30:73] assign _nestedwb_set_T = select_c ? _mshrs_11_io_status_bits_set : _mshrs_10_io_status_bits_set; // @[Scheduler.scala:71:46, :153:32, :155:24] assign nestedwb_set = _nestedwb_set_T; // @[Scheduler.scala:75:22, :155:24] assign _nestedwb_tag_T = select_c ? _mshrs_11_io_status_bits_tag : _mshrs_10_io_status_bits_tag; // @[Scheduler.scala:71:46, :153:32, :156:24] assign nestedwb_tag = _nestedwb_tag_T; // @[Scheduler.scala:75:22, :156:24] wire _GEN = select_bc & _mshrs_10_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :154:32, :157:37] wire _nestedwb_b_toN_T; // @[Scheduler.scala:157:37] assign _nestedwb_b_toN_T = _GEN; // @[Scheduler.scala:157:37] wire _nestedwb_b_toB_T; // @[Scheduler.scala:158:37] assign _nestedwb_b_toB_T = _GEN; // @[Scheduler.scala:157:37, :158:37] assign _nestedwb_b_clr_dirty_T = _GEN; // @[Scheduler.scala:157:37, :159:37] wire _nestedwb_b_toN_T_1 = _mshrs_10_io_schedule_bits_dir_bits_data_state == 2'h0; // @[Scheduler.scala:71:46, :157:123] assign _nestedwb_b_toN_T_2 = _nestedwb_b_toN_T & _nestedwb_b_toN_T_1; // @[Scheduler.scala:157:{37,75,123}] assign nestedwb_b_toN = _nestedwb_b_toN_T_2; // @[Scheduler.scala:75:22, :157:75] wire _nestedwb_b_toB_T_1 = _mshrs_10_io_schedule_bits_dir_bits_data_state == 2'h1; // @[Scheduler.scala:71:46, :158:123] assign _nestedwb_b_toB_T_2 = _nestedwb_b_toB_T & _nestedwb_b_toB_T_1; // @[Scheduler.scala:158:{37,75,123}] assign nestedwb_b_toB = _nestedwb_b_toB_T_2; // @[Scheduler.scala:75:22, :158:75] assign nestedwb_b_clr_dirty = _nestedwb_b_clr_dirty_T; // @[Scheduler.scala:75:22, :159:37] wire _nestedwb_c_set_dirty_T = select_c & _mshrs_11_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :153:32, :160:37] assign _nestedwb_c_set_dirty_T_1 = _nestedwb_c_set_dirty_T & _mshrs_11_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46, :160:{37,75}] assign nestedwb_c_set_dirty = _nestedwb_c_set_dirty_T_1; // @[Scheduler.scala:75:22, :160:75] wire _request_ready_T_2; // @[Scheduler.scala:261:40] wire _request_valid_T_2; // @[Scheduler.scala:164:39] wire _request_bits_T_1_prio_0; // @[Scheduler.scala:165:22] wire _view__WIRE_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_1_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_2_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_3_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_4_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_5_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_6_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_7_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_8_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_9_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_10_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_11_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95] wire _request_bits_T_1_prio_2; // @[Scheduler.scala:165:22] wire _request_bits_T_1_control; // @[Scheduler.scala:165:22] wire _view__WIRE_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_1_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_2_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_3_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_4_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_5_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_6_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_7_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_8_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_9_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_10_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_11_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _request_bits_T_1_opcode; // @[Scheduler.scala:165:22] wire _view__WIRE_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_1_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_2_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_3_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_4_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_5_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_6_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_7_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_8_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_9_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_10_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_11_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _request_bits_T_1_param; // @[Scheduler.scala:165:22] wire [2:0] _view__WIRE_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_1_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_2_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_3_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_4_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_5_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_6_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_7_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_8_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_9_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_10_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_11_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _request_bits_T_1_size; // @[Scheduler.scala:165:22] wire [2:0] _view__WIRE_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_1_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_2_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_3_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_4_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_5_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_6_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_7_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_8_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_9_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_10_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_11_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _request_bits_T_1_source; // @[Scheduler.scala:165:22] wire [2:0] _view__WIRE_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_1_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_2_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_3_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_4_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_5_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_6_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_7_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_8_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_9_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_10_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_11_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95] wire [8:0] _request_bits_T_1_tag; // @[Scheduler.scala:165:22] wire [5:0] _view__WIRE_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_1_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_2_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_3_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_4_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_5_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_6_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_7_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_8_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_9_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_10_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_11_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _request_bits_T_1_offset; // @[Scheduler.scala:165:22] wire [8:0] _view__WIRE_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95] wire [8:0] _view__WIRE_1_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95] wire [8:0] _view__WIRE_2_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95] wire [8:0] _view__WIRE_3_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95] wire [8:0] _view__WIRE_4_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95] wire [8:0] _view__WIRE_5_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95] wire [8:0] _view__WIRE_6_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95] wire [8:0] _view__WIRE_7_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95] wire [8:0] _view__WIRE_8_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95] wire [8:0] _view__WIRE_9_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95] wire [8:0] _view__WIRE_10_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95] wire [8:0] _view__WIRE_11_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _request_bits_T_1_put; // @[Scheduler.scala:165:22] wire [5:0] _view__WIRE_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_1_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_2_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_3_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_4_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_5_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_6_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_7_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_8_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_9_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_10_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_11_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95] wire [10:0] _request_bits_T_1_set; // @[Scheduler.scala:165:22] wire [5:0] _view__WIRE_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_1_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_2_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_3_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_4_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_5_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_6_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_7_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_8_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_9_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_10_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_11_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95] wire [10:0] request_bits_set; // @[Scheduler.scala:163:21] wire request_ready; // @[Scheduler.scala:163:21] wire request_valid; // @[Scheduler.scala:163:21] wire _request_valid_T = _sinkA_io_req_valid \| _sinkX_io_req_valid; // @[Scheduler.scala:54:21, :58:21, :164:62] wire _request_valid_T_1 = _request_valid_T \| _sinkC_io_req_valid; // @[Scheduler.scala:55:21, :164:{62,84}] assign _request_valid_T_2 = _directory_io_ready & _request_valid_T_1; // @[Scheduler.scala:68:25, :164:{39,84}] assign request_valid = _request_valid_T_2; // @[Scheduler.scala:163:21, :164:39] wire [2:0] _request_bits_T_opcode = _sinkX_io_req_valid ? 3'h0 : _sinkA_io_req_bits_opcode; // @[Scheduler.scala:54:21, :58:21, :166:22] wire [2:0] _request_bits_T_param = _sinkX_io_req_valid ? 3'h0 : _sinkA_io_req_bits_param; // @[Scheduler.scala:54:21, :58:21, :166:22] wire [2:0] _request_bits_T_size = _sinkX_io_req_valid ? 3'h6 : _sinkA_io_req_bits_size; // @[Scheduler.scala:54:21, :58:21, :166:22] wire [5:0] _request_bits_T_source = _sinkX_io_req_valid ? 6'h0 : _sinkA_io_req_bits_source; // @[Scheduler.scala:54:21, :58:21, :166:22] wire [8:0] _request_bits_T_tag = _sinkX_io_req_valid ? _sinkX_io_req_bits_tag : _sinkA_io_req_bits_tag; // @[Scheduler.scala:54:21, :58:21, :166:22] wire [5:0] _request_bits_T_offset = _sinkX_io_req_valid ? 6'h0 : _sinkA_io_req_bits_offset; // @[Scheduler.scala:54:21, :58:21, :166:22] wire [5:0] _request_bits_T_put = _sinkX_io_req_valid ? 6'h0 : _sinkA_io_req_bits_put; // @[Scheduler.scala:54:21, :58:21, :166:22] wire [10:0] _request_bits_T_set = _sinkX_io_req_valid ? _sinkX_io_req_bits_set : _sinkA_io_req_bits_set; // @[Scheduler.scala:54:21, :58:21, :166:22] wire _request_bits_T_control; // @[Scheduler.scala:166:22] assign _request_bits_T_1_control = ~_sinkC_io_req_valid & _request_bits_T_control; // @[Scheduler.scala:55:21, :165:22, :166:22] assign _request_bits_T_1_opcode = _sinkC_io_req_valid ? _sinkC_io_req_bits_opcode : _request_bits_T_opcode; // @[Scheduler.scala:55:21, :165:22, :166:22] assign _request_bits_T_1_param = _sinkC_io_req_valid ? _sinkC_io_req_bits_param : _request_bits_T_param; // @[Scheduler.scala:55:21, :165:22, :166:22] assign _request_bits_T_1_size = _sinkC_io_req_valid ? _sinkC_io_req_bits_size : _request_bits_T_size; // @[Scheduler.scala:55:21, :165:22, :166:22] assign _request_bits_T_1_source = _sinkC_io_req_valid ? _sinkC_io_req_bits_source : _request_bits_T_source; // @[Scheduler.scala:55:21, :165:22, :166:22] assign _request_bits_T_1_tag = _sinkC_io_req_valid ? _sinkC_io_req_bits_tag : _request_bits_T_tag; // @[Scheduler.scala:55:21, :165:22, :166:22] assign _request_bits_T_1_offset = _sinkC_io_req_valid ? _sinkC_io_req_bits_offset : _request_bits_T_offset; // @[Scheduler.scala:55:21, :165:22, :166:22] assign _request_bits_T_1_put = _sinkC_io_req_valid ? _sinkC_io_req_bits_put : _request_bits_T_put; // @[Scheduler.scala:55:21, :165:22, :166:22] assign _request_bits_T_1_set = _sinkC_io_req_valid ? _sinkC_io_req_bits_set : _request_bits_T_set; // @[Scheduler.scala:55:21, :165:22, :166:22] assign _request_bits_T_1_prio_0 = ~_sinkC_io_req_valid; // @[Scheduler.scala:55:21, :165:22] assign request_bits_prio_0 = _request_bits_T_1_prio_0; // @[Scheduler.scala:163:21, :165:22] assign request_bits_prio_2 = _request_bits_T_1_prio_2; // @[Scheduler.scala:163:21, :165:22] assign request_bits_control = _request_bits_T_1_control; // @[Scheduler.scala:163:21, :165:22] assign request_bits_opcode = _request_bits_T_1_opcode; // @[Scheduler.scala:163:21, :165:22] assign request_bits_param = _request_bits_T_1_param; // @[Scheduler.scala:163:21, :165:22] assign request_bits_size = _request_bits_T_1_size; // @[Scheduler.scala:163:21, :165:22] assign request_bits_source = _request_bits_T_1_source; // @[Scheduler.scala:163:21, :165:22] assign request_bits_tag = _request_bits_T_1_tag; // @[Scheduler.scala:163:21, :165:22] assign request_bits_offset = _request_bits_T_1_offset; // @[Scheduler.scala:163:21, :165:22] assign request_bits_put = _request_bits_T_1_put; // @[Scheduler.scala:163:21, :165:22] assign request_bits_set = _request_bits_T_1_set; // @[Scheduler.scala:163:21, :165:22] wire _GEN_0 = _directory_io_ready & request_ready; // @[Scheduler.scala:68:25, :163:21, :167:44] wire _sinkC_io_req_ready_T; // @[Scheduler.scala:167:44] assign _sinkC_io_req_ready_T = _GEN_0; // @[Scheduler.scala:167:44] wire _sinkX_io_req_ready_T; // @[Scheduler.scala:168:44] assign _sinkX_io_req_ready_T = _GEN_0; // @[Scheduler.scala:167:44, :168:44] wire _sinkA_io_req_ready_T; // @[Scheduler.scala:169:44] assign _sinkA_io_req_ready_T = _GEN_0; // @[Scheduler.scala:167:44, :169:44] wire _sinkX_io_req_ready_T_1 = ~_sinkC_io_req_valid; // @[Scheduler.scala:55:21, :165:22, :168:64] wire _sinkX_io_req_ready_T_2 = _sinkX_io_req_ready_T & _sinkX_io_req_ready_T_1; // @[Scheduler.scala:168:{44,61,64}] wire _sinkA_io_req_ready_T_1 = ~_sinkC_io_req_valid; // @[Scheduler.scala:55:21, :165:22, :169:64] wire _sinkA_io_req_ready_T_2 = _sinkA_io_req_ready_T & _sinkA_io_req_ready_T_1; // @[Scheduler.scala:169:{44,61,64}] wire _sinkA_io_req_ready_T_3 = ~_sinkX_io_req_valid; // @[Scheduler.scala:58:21, :169:87] wire _sinkA_io_req_ready_T_4 = _sinkA_io_req_ready_T_2 & _sinkA_io_req_ready_T_3; // @[Scheduler.scala:169:{61,84,87}] wire _setMatches_T = _mshrs_0_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83] wire _setMatches_T_1 = _mshrs_0_io_status_valid & _setMatches_T; // @[Scheduler.scala:71:46, :172:{59,83}] wire _setMatches_T_2 = _mshrs_1_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83] wire _setMatches_T_3 = _mshrs_1_io_status_valid & _setMatches_T_2; // @[Scheduler.scala:71:46, :172:{59,83}] wire _setMatches_T_4 = _mshrs_2_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83] wire _setMatches_T_5 = _mshrs_2_io_status_valid & _setMatches_T_4; // @[Scheduler.scala:71:46, :172:{59,83}] wire _setMatches_T_6 = _mshrs_3_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83] wire _setMatches_T_7 = _mshrs_3_io_status_valid & _setMatches_T_6; // @[Scheduler.scala:71:46, :172:{59,83}] wire _setMatches_T_8 = _mshrs_4_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83] wire _setMatches_T_9 = _mshrs_4_io_status_valid & _setMatches_T_8; // @[Scheduler.scala:71:46, :172:{59,83}] wire _setMatches_T_10 = _mshrs_5_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83] wire _setMatches_T_11 = _mshrs_5_io_status_valid & _setMatches_T_10; // @[Scheduler.scala:71:46, :172:{59,83}] wire _setMatches_T_12 = _mshrs_6_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83] wire _setMatches_T_13 = _mshrs_6_io_status_valid & _setMatches_T_12; // @[Scheduler.scala:71:46, :172:{59,83}] wire _setMatches_T_14 = _mshrs_7_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83] wire _setMatches_T_15 = _mshrs_7_io_status_valid & _setMatches_T_14; // @[Scheduler.scala:71:46, :172:{59,83}] wire _setMatches_T_16 = _mshrs_8_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83] wire _setMatches_T_17 = _mshrs_8_io_status_valid & _setMatches_T_16; // @[Scheduler.scala:71:46, :172:{59,83}] wire _setMatches_T_18 = _mshrs_9_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83] wire _setMatches_T_19 = _mshrs_9_io_status_valid & _setMatches_T_18; // @[Scheduler.scala:71:46, :172:{59,83}] wire _setMatches_T_20 = _mshrs_10_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83] wire _setMatches_T_21 = _mshrs_10_io_status_valid & _setMatches_T_20; // @[Scheduler.scala:71:46, :172:{59,83}] wire _setMatches_T_22 = _mshrs_11_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83] wire _setMatches_T_23 = _mshrs_11_io_status_valid & _setMatches_T_22; // @[Scheduler.scala:71:46, :172:{59,83}] wire [1:0] setMatches_lo_lo_hi = {_setMatches_T_5, _setMatches_T_3}; // @[Scheduler.scala:172:{23,59}] wire [2:0] setMatches_lo_lo = {setMatches_lo_lo_hi, _setMatches_T_1}; // @[Scheduler.scala:172:{23,59}] wire [1:0] setMatches_lo_hi_hi = {_setMatches_T_11, _setMatches_T_9}; // @[Scheduler.scala:172:{23,59}] wire [2:0] setMatches_lo_hi = {setMatches_lo_hi_hi, _setMatches_T_7}; // @[Scheduler.scala:172:{23,59}] wire [5:0] setMatches_lo = {setMatches_lo_hi, setMatches_lo_lo}; // @[Scheduler.scala:172:23] wire [1:0] setMatches_hi_lo_hi = {_setMatches_T_17, _setMatches_T_15}; // @[Scheduler.scala:172:{23,59}] wire [2:0] setMatches_hi_lo = {setMatches_hi_lo_hi, _setMatches_T_13}; // @[Scheduler.scala:172:{23,59}] wire [1:0] setMatches_hi_hi_hi = {_setMatches_T_23, _setMatches_T_21}; // @[Scheduler.scala:172:{23,59}] wire [2:0] setMatches_hi_hi = {setMatches_hi_hi_hi, _setMatches_T_19}; // @[Scheduler.scala:172:{23,59}] wire [5:0] setMatches_hi = {setMatches_hi_hi, setMatches_hi_lo}; // @[Scheduler.scala:172:23] wire [11:0] setMatches = {setMatches_hi, setMatches_lo}; // @[Scheduler.scala:172:23] wire _alloc_T = \|setMatches; // @[Scheduler.scala:172:23, :173:27] wire alloc = ~_alloc_T; // @[Scheduler.scala:173:{15,27}] wire _blockB_T = setMatches[0]; // @[Mux.scala:32:36] wire _blockC_T = setMatches[0]; // @[Mux.scala:32:36] wire _nestB_T = setMatches[0]; // @[Mux.scala:32:36] wire _nestC_T = setMatches[0]; // @[Mux.scala:32:36] wire _blockB_T_1 = setMatches[1]; // @[Mux.scala:32:36] wire _blockC_T_1 = setMatches[1]; // @[Mux.scala:32:36] wire _nestB_T_1 = setMatches[1]; // @[Mux.scala:32:36] wire _nestC_T_1 = setMatches[1]; // @[Mux.scala:32:36] wire _blockB_T_2 = setMatches[2]; // @[Mux.scala:32:36] wire _blockC_T_2 = setMatches[2]; // @[Mux.scala:32:36] wire _nestB_T_2 = setMatches[2]; // @[Mux.scala:32:36] wire _nestC_T_2 = setMatches[2]; // @[Mux.scala:32:36] wire _blockB_T_3 = setMatches[3]; // @[Mux.scala:32:36] wire _blockC_T_3 = setMatches[3]; // @[Mux.scala:32:36] wire _nestB_T_3 = setMatches[3]; // @[Mux.scala:32:36] wire _nestC_T_3 = setMatches[3]; // @[Mux.scala:32:36] wire _blockB_T_4 = setMatches[4]; // @[Mux.scala:32:36] wire _blockC_T_4 = setMatches[4]; // @[Mux.scala:32:36] wire _nestB_T_4 = setMatches[4]; // @[Mux.scala:32:36] wire _nestC_T_4 = setMatches[4]; // @[Mux.scala:32:36] wire _blockB_T_5 = setMatches[5]; // @[Mux.scala:32:36] wire _blockC_T_5 = setMatches[5]; // @[Mux.scala:32:36] wire _nestB_T_5 = setMatches[5]; // @[Mux.scala:32:36] wire _nestC_T_5 = setMatches[5]; // @[Mux.scala:32:36] wire _blockB_T_6 = setMatches[6]; // @[Mux.scala:32:36] wire _blockC_T_6 = setMatches[6]; // @[Mux.scala:32:36] wire _nestB_T_6 = setMatches[6]; // @[Mux.scala:32:36] wire _nestC_T_6 = setMatches[6]; // @[Mux.scala:32:36] wire _blockB_T_7 = setMatches[7]; // @[Mux.scala:32:36] wire _blockC_T_7 = setMatches[7]; // @[Mux.scala:32:36] wire _nestB_T_7 = setMatches[7]; // @[Mux.scala:32:36] wire _nestC_T_7 = setMatches[7]; // @[Mux.scala:32:36] wire _blockB_T_8 = setMatches[8]; // @[Mux.scala:32:36] wire _blockC_T_8 = setMatches[8]; // @[Mux.scala:32:36] wire _nestB_T_8 = setMatches[8]; // @[Mux.scala:32:36] wire _nestC_T_8 = setMatches[8]; // @[Mux.scala:32:36] wire _blockB_T_9 = setMatches[9]; // @[Mux.scala:32:36] wire _blockC_T_9 = setMatches[9]; // @[Mux.scala:32:36] wire _nestB_T_9 = setMatches[9]; // @[Mux.scala:32:36] wire _nestC_T_9 = setMatches[9]; // @[Mux.scala:32:36] wire _blockB_T_10 = setMatches[10]; // @[Mux.scala:32:36] wire _blockC_T_10 = setMatches[10]; // @[Mux.scala:32:36] wire _nestB_T_10 = setMatches[10]; // @[Mux.scala:32:36] wire _nestC_T_10 = setMatches[10]; // @[Mux.scala:32:36] wire _blockB_T_11 = setMatches[11]; // @[Mux.scala:32:36] wire _blockC_T_11 = setMatches[11]; // @[Mux.scala:32:36] wire _nestB_T_11 = setMatches[11]; // @[Mux.scala:32:36] wire _nestC_T_11 = setMatches[11]; // @[Mux.scala:32:36] wire _blockB_T_12 = _blockB_T & _mshrs_0_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36] wire _blockB_T_13 = _blockB_T_1 & _mshrs_1_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36] wire _blockB_T_14 = _blockB_T_2 & _mshrs_2_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36] wire _blockB_T_15 = _blockB_T_3 & _mshrs_3_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36] wire _blockB_T_16 = _blockB_T_4 & _mshrs_4_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36] wire _blockB_T_17 = _blockB_T_5 & _mshrs_5_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36] wire _blockB_T_18 = _blockB_T_6 & _mshrs_6_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36] wire _blockB_T_19 = _blockB_T_7 & _mshrs_7_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36] wire _blockB_T_20 = _blockB_T_8 & _mshrs_8_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36] wire _blockB_T_21 = _blockB_T_9 & _mshrs_9_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36] wire _blockB_T_22 = _blockB_T_10 & _mshrs_10_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36] wire _blockB_T_23 = _blockB_T_11 & _mshrs_11_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36] wire _blockB_T_24 = _blockB_T_12 \| _blockB_T_13; // @[Mux.scala:30:73] wire _blockB_T_25 = _blockB_T_24 \| _blockB_T_14; // @[Mux.scala:30:73] wire _blockB_T_26 = _blockB_T_25 \| _blockB_T_15; // @[Mux.scala:30:73] wire _blockB_T_27 = _blockB_T_26 \| _blockB_T_16; // @[Mux.scala:30:73] wire _blockB_T_28 = _blockB_T_27 \| _blockB_T_17; // @[Mux.scala:30:73] wire _blockB_T_29 = _blockB_T_28 \| _blockB_T_18; // @[Mux.scala:30:73] wire _blockB_T_30 = _blockB_T_29 \| _blockB_T_19; // @[Mux.scala:30:73] wire _blockB_T_31 = _blockB_T_30 \| _blockB_T_20; // @[Mux.scala:30:73] wire _blockB_T_32 = _blockB_T_31 \| _blockB_T_21; // @[Mux.scala:30:73] wire _blockB_T_33 = _blockB_T_32 \| _blockB_T_22; // @[Mux.scala:30:73] wire _blockB_T_34 = _blockB_T_33 \| _blockB_T_23; // @[Mux.scala:30:73] wire _blockB_WIRE = _blockB_T_34; // @[Mux.scala:30:73] wire _blockC_T_12 = _blockC_T & _mshrs_0_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36] wire _blockC_T_13 = _blockC_T_1 & _mshrs_1_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36] wire _blockC_T_14 = _blockC_T_2 & _mshrs_2_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36] wire _blockC_T_15 = _blockC_T_3 & _mshrs_3_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36] wire _blockC_T_16 = _blockC_T_4 & _mshrs_4_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36] wire _blockC_T_17 = _blockC_T_5 & _mshrs_5_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36] wire _blockC_T_18 = _blockC_T_6 & _mshrs_6_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36] wire _blockC_T_19 = _blockC_T_7 & _mshrs_7_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36] wire _blockC_T_20 = _blockC_T_8 & _mshrs_8_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36] wire _blockC_T_21 = _blockC_T_9 & _mshrs_9_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36] wire _blockC_T_22 = _blockC_T_10 & _mshrs_10_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36] wire _blockC_T_23 = _blockC_T_11 & _mshrs_11_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36] wire _blockC_T_24 = _blockC_T_12 \| _blockC_T_13; // @[Mux.scala:30:73] wire _blockC_T_25 = _blockC_T_24 \| _blockC_T_14; // @[Mux.scala:30:73] wire _blockC_T_26 = _blockC_T_25 \| _blockC_T_15; // @[Mux.scala:30:73] wire _blockC_T_27 = _blockC_T_26 \| _blockC_T_16; // @[Mux.scala:30:73] wire _blockC_T_28 = _blockC_T_27 \| _blockC_T_17; // @[Mux.scala:30:73] wire _blockC_T_29 = _blockC_T_28 \| _blockC_T_18; // @[Mux.scala:30:73] wire _blockC_T_30 = _blockC_T_29 \| _blockC_T_19; // @[Mux.scala:30:73] wire _blockC_T_31 = _blockC_T_30 \| _blockC_T_20; // @[Mux.scala:30:73] wire _blockC_T_32 = _blockC_T_31 \| _blockC_T_21; // @[Mux.scala:30:73] wire _blockC_T_33 = _blockC_T_32 \| _blockC_T_22; // @[Mux.scala:30:73] wire _blockC_T_34 = _blockC_T_33 \| _blockC_T_23; // @[Mux.scala:30:73] wire _blockC_WIRE = _blockC_T_34; // @[Mux.scala:30:73] wire blockC = _blockC_WIRE & request_bits_prio_2; // @[Mux.scala:30:73] wire _nestB_T_12 = _nestB_T & _mshrs_0_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36] wire _nestB_T_13 = _nestB_T_1 & _mshrs_1_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36] wire _nestB_T_14 = _nestB_T_2 & _mshrs_2_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36] wire _nestB_T_15 = _nestB_T_3 & _mshrs_3_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36] wire _nestB_T_16 = _nestB_T_4 & _mshrs_4_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36] wire _nestB_T_17 = _nestB_T_5 & _mshrs_5_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36] wire _nestB_T_18 = _nestB_T_6 & _mshrs_6_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36] wire _nestB_T_19 = _nestB_T_7 & _mshrs_7_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36] wire _nestB_T_20 = _nestB_T_8 & _mshrs_8_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36] wire _nestB_T_21 = _nestB_T_9 & _mshrs_9_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36] wire _nestB_T_22 = _nestB_T_10 & _mshrs_10_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36] wire _nestB_T_23 = _nestB_T_11 & _mshrs_11_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36] wire _nestB_T_24 = _nestB_T_12 \| _nestB_T_13; // @[Mux.scala:30:73] wire _nestB_T_25 = _nestB_T_24 \| _nestB_T_14; // @[Mux.scala:30:73] wire _nestB_T_26 = _nestB_T_25 \| _nestB_T_15; // @[Mux.scala:30:73] wire _nestB_T_27 = _nestB_T_26 \| _nestB_T_16; // @[Mux.scala:30:73] wire _nestB_T_28 = _nestB_T_27 \| _nestB_T_17; // @[Mux.scala:30:73] wire _nestB_T_29 = _nestB_T_28 \| _nestB_T_18; // @[Mux.scala:30:73] wire _nestB_T_30 = _nestB_T_29 \| _nestB_T_19; // @[Mux.scala:30:73] wire _nestB_T_31 = _nestB_T_30 \| _nestB_T_20; // @[Mux.scala:30:73] wire _nestB_T_32 = _nestB_T_31 \| _nestB_T_21; // @[Mux.scala:30:73] wire _nestB_T_33 = _nestB_T_32 \| _nestB_T_22; // @[Mux.scala:30:73] wire _nestB_T_34 = _nestB_T_33 \| _nestB_T_23; // @[Mux.scala:30:73] wire _nestB_WIRE = _nestB_T_34; // @[Mux.scala:30:73] wire _nestC_T_12 = _nestC_T & _mshrs_0_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36] wire _nestC_T_13 = _nestC_T_1 & _mshrs_1_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36] wire _nestC_T_14 = _nestC_T_2 & _mshrs_2_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36] wire _nestC_T_15 = _nestC_T_3 & _mshrs_3_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36] wire _nestC_T_16 = _nestC_T_4 & _mshrs_4_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36] wire _nestC_T_17 = _nestC_T_5 & _mshrs_5_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36] wire _nestC_T_18 = _nestC_T_6 & _mshrs_6_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36] wire _nestC_T_19 = _nestC_T_7 & _mshrs_7_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36] wire _nestC_T_20 = _nestC_T_8 & _mshrs_8_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36] wire _nestC_T_21 = _nestC_T_9 & _mshrs_9_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36] wire _nestC_T_22 = _nestC_T_10 & _mshrs_10_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36] wire _nestC_T_23 = _nestC_T_11 & _mshrs_11_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36] wire _nestC_T_24 = _nestC_T_12 \| _nestC_T_13; // @[Mux.scala:30:73] wire _nestC_T_25 = _nestC_T_24 \| _nestC_T_14; // @[Mux.scala:30:73] wire _nestC_T_26 = _nestC_T_25 \| _nestC_T_15; // @[Mux.scala:30:73] wire _nestC_T_27 = _nestC_T_26 \| _nestC_T_16; // @[Mux.scala:30:73] wire _nestC_T_28 = _nestC_T_27 \| _nestC_T_17; // @[Mux.scala:30:73] wire _nestC_T_29 = _nestC_T_28 \| _nestC_T_18; // @[Mux.scala:30:73] wire _nestC_T_30 = _nestC_T_29 \| _nestC_T_19; // @[Mux.scala:30:73] wire _nestC_T_31 = _nestC_T_30 \| _nestC_T_20; // @[Mux.scala:30:73] wire _nestC_T_32 = _nestC_T_31 \| _nestC_T_21; // @[Mux.scala:30:73] wire _nestC_T_33 = _nestC_T_32 \| _nestC_T_22; // @[Mux.scala:30:73] wire _nestC_T_34 = _nestC_T_33 \| _nestC_T_23; // @[Mux.scala:30:73] wire _nestC_WIRE = _nestC_T_34; // @[Mux.scala:30:73] wire nestC = _nestC_WIRE & request_bits_prio_2; // @[Mux.scala:30:73] wire _prioFilter_T = ~request_bits_prio_0; // @[Scheduler.scala:163:21, :182:46] wire [1:0] prioFilter_hi = {request_bits_prio_2, _prioFilter_T}; // @[Scheduler.scala:163:21, :182:{23,46}] wire [11:0] prioFilter = {prioFilter_hi, 10'h3FF}; // @[Scheduler.scala:182:23] wire [11:0] lowerMatches = setMatches & prioFilter; // @[Scheduler.scala:172:23, :182:23, :183:33] wire _queue_T = \|lowerMatches; // @[Scheduler.scala:183:33, :185:28] wire _queue_T_2 = _queue_T; // @[Scheduler.scala:185:{28,32}] wire _queue_T_3 = ~nestC; // @[Scheduler.scala:180:70, :185:45] wire _queue_T_4 = _queue_T_2 & _queue_T_3; // @[Scheduler.scala:185:{32,42,45}] wire _queue_T_6 = _queue_T_4; // @[Scheduler.scala:185:{42,52}] wire _queue_T_7 = ~blockC; // @[Scheduler.scala:176:70, :185:66] wire queue = _queue_T_6 & _queue_T_7; // @[Scheduler.scala:185:{52,63,66}] wire _T_12 = request_valid & queue; // @[Scheduler.scala:163:21, :185:63, :195:31] wire _bypass_T; // @[Scheduler.scala:213:30] assign _bypass_T = _T_12; // @[Scheduler.scala:195:31, :213:30] wire _bypass_T_1; // @[Scheduler.scala:231:32] assign _bypass_T_1 = _T_12; // @[Scheduler.scala:195:31, :231:32] wire _bypass_T_2; // @[Scheduler.scala:231:32] assign _bypass_T_2 = _T_12; // @[Scheduler.scala:195:31, :231:32] wire _bypass_T_3; // @[Scheduler.scala:231:32] assign _bypass_T_3 = _T_12; // @[Scheduler.scala:195:31, :231:32] wire _bypass_T_4; // @[Scheduler.scala:231:32] assign _bypass_T_4 = _T_12; // @[Scheduler.scala:195:31, :231:32] wire _bypass_T_5; // @[Scheduler.scala:231:32] assign _bypass_T_5 = _T_12; // @[Scheduler.scala:195:31, :231:32] wire _bypass_T_6; // @[Scheduler.scala:231:32] assign _bypass_T_6 = _T_12; // @[Scheduler.scala:195:31, :231:32] wire _bypass_T_7; // @[Scheduler.scala:231:32] assign _bypass_T_7 = _T_12; // @[Scheduler.scala:195:31, :231:32] wire _bypass_T_8; // @[Scheduler.scala:231:32] assign _bypass_T_8 = _T_12; // @[Scheduler.scala:195:31, :231:32] wire _bypass_T_9; // @[Scheduler.scala:231:32] assign _bypass_T_9 = _T_12; // @[Scheduler.scala:195:31, :231:32] wire _bypass_T_10; // @[Scheduler.scala:231:32] assign _bypass_T_10 = _T_12; // @[Scheduler.scala:195:31, :231:32] wire _bypass_T_11; // @[Scheduler.scala:231:32] assign _bypass_T_11 = _T_12; // @[Scheduler.scala:195:31, :231:32] wire _bypass_T_12; // @[Scheduler.scala:231:32] assign _bypass_T_12 = _T_12; // @[Scheduler.scala:195:31, :231:32] wire _requests_io_push_valid_T; // @[Scheduler.scala:270:43] assign _requests_io_push_valid_T = _T_12; // @[Scheduler.scala:195:31, :270:43] wire _lowerMatches1_T = lowerMatches[11]; // @[Scheduler.scala:183:33, :200:21] wire _lowerMatches1_T_2 = lowerMatches[10]; // @[Scheduler.scala:183:33, :201:21] wire [11:0] _lowerMatches1_T_4 = _lowerMatches1_T_2 ? 12'h400 : lowerMatches; // @[Scheduler.scala:183:33, :201:{8,21}] wire [11:0] lowerMatches1 = _lowerMatches1_T ? 12'h800 : _lowerMatches1_T_4; // @[Scheduler.scala:200:{8,21}, :201:8] wire [11:0] _requests_io_push_bits_index_T = lowerMatches1; // @[Scheduler.scala:200:8, :274:30] wire [23:0] _GEN_1 = {2{mshr_selectOH}}; // @[Scheduler.scala:121:70, :206:30] wire [23:0] selected_requests_hi; // @[Scheduler.scala:206:30] assign selected_requests_hi = _GEN_1; // @[Scheduler.scala:206:30] wire [23:0] pop_index_hi; // @[Scheduler.scala:241:31] assign pop_index_hi = _GEN_1; // @[Scheduler.scala:206:30, :241:31] wire [35:0] _selected_requests_T = {selected_requests_hi, mshr_selectOH}; // @[Scheduler.scala:121:70, :206:30] wire [35:0] selected_requests = _selected_requests_T & _requests_io_valid; // @[Scheduler.scala:70:24, :206:{30,76}] wire [11:0] _a_pop_T = selected_requests[11:0]; // @[Scheduler.scala:206:76, :207:32] wire a_pop = \|_a_pop_T; // @[Scheduler.scala:207:{32,79}] wire [11:0] _b_pop_T = selected_requests[23:12]; // @[Scheduler.scala:206:76, :208:32] wire b_pop = \|_b_pop_T; // @[Scheduler.scala:208:{32,79}] wire _bypassMatches_T_4 = b_pop; // @[Scheduler.scala:208:79, :211:76] wire [11:0] _c_pop_T = selected_requests[35:24]; // @[Scheduler.scala:206:76, :209:32] wire c_pop = \|_c_pop_T; // @[Scheduler.scala:209:{32,79}] wire [11:0] _bypassMatches_T = mshr_selectOH & lowerMatches1; // @[Scheduler.scala:121:70, :200:8, :210:38] wire _bypassMatches_T_1 = \|_bypassMatches_T; // @[Scheduler.scala:210:{38,55}] wire _bypassMatches_T_2 = c_pop \| request_bits_prio_2; // @[Scheduler.scala:163:21, :209:79, :211:33] wire _bypassMatches_T_3 = ~c_pop; // @[Scheduler.scala:209:79, :211:58] wire _bypassMatches_T_5 = ~b_pop; // @[Scheduler.scala:208:79, :211:101] wire _bypassMatches_T_6 = ~a_pop; // @[Scheduler.scala:207:79, :211:109] wire _bypassMatches_T_7 = _bypassMatches_T_4 ? _bypassMatches_T_5 : _bypassMatches_T_6; // @[Scheduler.scala:211:{69,76,101,109}] wire _bypassMatches_T_8 = _bypassMatches_T_2 ? _bypassMatches_T_3 : _bypassMatches_T_7; // @[Scheduler.scala:211:{26,33,58,69}] wire bypassMatches = _bypassMatches_T_1 & _bypassMatches_T_8; // @[Scheduler.scala:210:{55,59}, :211:26] wire _may_pop_T = a_pop \| b_pop; // @[Scheduler.scala:207:79, :208:79, :212:23] wire may_pop = _may_pop_T \| c_pop; // @[Scheduler.scala:209:79, :212:{23,32}] wire bypass = _bypass_T & bypassMatches; // @[Scheduler.scala:210:59, :213:{30,39}] wire _will_reload_T = may_pop \| bypass; // @[Scheduler.scala:212:32, :213:39, :214:49] wire will_reload = schedule_reload & _will_reload_T; // @[Mux.scala:30:73] wire _GEN_2 = schedule_reload & may_pop; // @[Mux.scala:30:73] wire _will_pop_T; // @[Scheduler.scala:215:34] assign _will_pop_T = _GEN_2; // @[Scheduler.scala:215:34] wire _mshr_uses_directory_assuming_no_bypass_T; // @[Scheduler.scala:247:64] assign _mshr_uses_directory_assuming_no_bypass_T = _GEN_2; // @[Scheduler.scala:215:34, :247:64] wire _will_pop_T_1 = ~bypass; // @[Scheduler.scala:213:39, :215:48] wire will_pop = _will_pop_T & _will_pop_T_1; // @[Scheduler.scala:215:{34,45,48}] wire a_pop_1 = _requests_io_valid[0]; // @[Scheduler.scala:70:24, :225:34] wire b_pop_1 = _requests_io_valid[12]; // @[Scheduler.scala:70:24, :226:34] wire _bypassMatches_T_12 = b_pop_1; // @[Scheduler.scala:226:34, :229:78] wire c_pop_1 = _requests_io_valid[24]; // @[Scheduler.scala:70:24, :227:34] wire _bypassMatches_T_9 = lowerMatches1[0]; // @[Scheduler.scala:200:8, :228:38] wire _bypassMatches_T_10 = c_pop_1 \| request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35] wire _bypassMatches_T_11 = ~c_pop_1; // @[Scheduler.scala:227:34, :229:60] wire _bypassMatches_T_13 = ~b_pop_1; // @[Scheduler.scala:226:34, :229:103] wire _bypassMatches_T_14 = ~a_pop_1; // @[Scheduler.scala:225:34, :229:111] wire _bypassMatches_T_15 = _bypassMatches_T_12 ? _bypassMatches_T_13 : _bypassMatches_T_14; // @[Scheduler.scala:229:{71,78,103,111}] wire _bypassMatches_T_16 = _bypassMatches_T_10 ? _bypassMatches_T_11 : _bypassMatches_T_15; // @[Scheduler.scala:229:{28,35,60,71}] wire bypassMatches_1 = _bypassMatches_T_9 & _bypassMatches_T_16; // @[Scheduler.scala:228:{38,42}, :229:28] wire _may_pop_T_1 = a_pop_1 \| b_pop_1; // @[Scheduler.scala:225:34, :226:34, :230:25] wire may_pop_1 = _may_pop_T_1 \| c_pop_1; // @[Scheduler.scala:227:34, :230:{25,34}] wire bypass_1 = _bypass_T_1 & bypassMatches_1; // @[Scheduler.scala:228:42, :231:{32,41}] wire _will_reload_T_1 = may_pop_1 \| bypass_1; // @[Scheduler.scala:230:34, :231:41, :232:61] wire will_reload_1 = _mshrs_0_io_schedule_bits_reload & _will_reload_T_1; // @[Scheduler.scala:71:46, :232:{49,61}] wire _view__T_prio_0 = bypass_1 ? _view__WIRE_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_prio_1 = ~bypass_1 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78] wire _view__T_prio_2 = bypass_1 ? _view__WIRE_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_control = bypass_1 ? _view__WIRE_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_opcode = bypass_1 ? _view__WIRE_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_param = bypass_1 ? _view__WIRE_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_size = bypass_1 ? _view__WIRE_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_source = bypass_1 ? _view__WIRE_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [8:0] _view__T_tag = bypass_1 ? _view__WIRE_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_offset = bypass_1 ? _view__WIRE_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_put = bypass_1 ? _view__WIRE_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _mshrs_0_io_allocate_bits_repeat_T = mshrs_0_io_allocate_bits_tag == _mshrs_0_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70] wire _mshrs_0_io_allocate_valid_T = sel & will_reload_1; // @[Scheduler.scala:223:28, :232:49, :236:32] wire a_pop_2 = _requests_io_valid[1]; // @[Scheduler.scala:70:24, :225:34] wire b_pop_2 = _requests_io_valid[13]; // @[Scheduler.scala:70:24, :226:34] wire _bypassMatches_T_20 = b_pop_2; // @[Scheduler.scala:226:34, :229:78] wire c_pop_2 = _requests_io_valid[25]; // @[Scheduler.scala:70:24, :227:34] wire _bypassMatches_T_17 = lowerMatches1[1]; // @[Scheduler.scala:200:8, :228:38] wire _bypassMatches_T_18 = c_pop_2 \| request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35] wire _bypassMatches_T_19 = ~c_pop_2; // @[Scheduler.scala:227:34, :229:60] wire _bypassMatches_T_21 = ~b_pop_2; // @[Scheduler.scala:226:34, :229:103] wire _bypassMatches_T_22 = ~a_pop_2; // @[Scheduler.scala:225:34, :229:111] wire _bypassMatches_T_23 = _bypassMatches_T_20 ? _bypassMatches_T_21 : _bypassMatches_T_22; // @[Scheduler.scala:229:{71,78,103,111}] wire _bypassMatches_T_24 = _bypassMatches_T_18 ? _bypassMatches_T_19 : _bypassMatches_T_23; // @[Scheduler.scala:229:{28,35,60,71}] wire bypassMatches_2 = _bypassMatches_T_17 & _bypassMatches_T_24; // @[Scheduler.scala:228:{38,42}, :229:28] wire _may_pop_T_2 = a_pop_2 \| b_pop_2; // @[Scheduler.scala:225:34, :226:34, :230:25] wire may_pop_2 = _may_pop_T_2 \| c_pop_2; // @[Scheduler.scala:227:34, :230:{25,34}] wire bypass_2 = _bypass_T_2 & bypassMatches_2; // @[Scheduler.scala:228:42, :231:{32,41}] wire _will_reload_T_2 = may_pop_2 \| bypass_2; // @[Scheduler.scala:230:34, :231:41, :232:61] wire will_reload_2 = _mshrs_1_io_schedule_bits_reload & _will_reload_T_2; // @[Scheduler.scala:71:46, :232:{49,61}] wire _view__T_1_prio_0 = bypass_2 ? _view__WIRE_1_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_1_prio_1 = ~bypass_2 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78] wire _view__T_1_prio_2 = bypass_2 ? _view__WIRE_1_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_1_control = bypass_2 ? _view__WIRE_1_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_1_opcode = bypass_2 ? _view__WIRE_1_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_1_param = bypass_2 ? _view__WIRE_1_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_1_size = bypass_2 ? _view__WIRE_1_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_1_source = bypass_2 ? _view__WIRE_1_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [8:0] _view__T_1_tag = bypass_2 ? _view__WIRE_1_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_1_offset = bypass_2 ? _view__WIRE_1_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_1_put = bypass_2 ? _view__WIRE_1_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _mshrs_1_io_allocate_bits_repeat_T = mshrs_1_io_allocate_bits_tag == _mshrs_1_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70] wire _mshrs_1_io_allocate_valid_T = sel_1 & will_reload_2; // @[Scheduler.scala:223:28, :232:49, :236:32] wire a_pop_3 = _requests_io_valid[2]; // @[Scheduler.scala:70:24, :225:34] wire b_pop_3 = _requests_io_valid[14]; // @[Scheduler.scala:70:24, :226:34] wire _bypassMatches_T_28 = b_pop_3; // @[Scheduler.scala:226:34, :229:78] wire c_pop_3 = _requests_io_valid[26]; // @[Scheduler.scala:70:24, :227:34] wire _bypassMatches_T_25 = lowerMatches1[2]; // @[Scheduler.scala:200:8, :228:38] wire _bypassMatches_T_26 = c_pop_3 \| request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35] wire _bypassMatches_T_27 = ~c_pop_3; // @[Scheduler.scala:227:34, :229:60] wire _bypassMatches_T_29 = ~b_pop_3; // @[Scheduler.scala:226:34, :229:103] wire _bypassMatches_T_30 = ~a_pop_3; // @[Scheduler.scala:225:34, :229:111] wire _bypassMatches_T_31 = _bypassMatches_T_28 ? _bypassMatches_T_29 : _bypassMatches_T_30; // @[Scheduler.scala:229:{71,78,103,111}] wire _bypassMatches_T_32 = _bypassMatches_T_26 ? _bypassMatches_T_27 : _bypassMatches_T_31; // @[Scheduler.scala:229:{28,35,60,71}] wire bypassMatches_3 = _bypassMatches_T_25 & _bypassMatches_T_32; // @[Scheduler.scala:228:{38,42}, :229:28] wire _may_pop_T_3 = a_pop_3 \| b_pop_3; // @[Scheduler.scala:225:34, :226:34, :230:25] wire may_pop_3 = _may_pop_T_3 \| c_pop_3; // @[Scheduler.scala:227:34, :230:{25,34}] wire bypass_3 = _bypass_T_3 & bypassMatches_3; // @[Scheduler.scala:228:42, :231:{32,41}] wire _will_reload_T_3 = may_pop_3 \| bypass_3; // @[Scheduler.scala:230:34, :231:41, :232:61] wire will_reload_3 = _mshrs_2_io_schedule_bits_reload & _will_reload_T_3; // @[Scheduler.scala:71:46, :232:{49,61}] wire _view__T_2_prio_0 = bypass_3 ? _view__WIRE_2_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_2_prio_1 = ~bypass_3 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78] wire _view__T_2_prio_2 = bypass_3 ? _view__WIRE_2_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_2_control = bypass_3 ? _view__WIRE_2_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_2_opcode = bypass_3 ? _view__WIRE_2_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_2_param = bypass_3 ? _view__WIRE_2_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_2_size = bypass_3 ? _view__WIRE_2_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_2_source = bypass_3 ? _view__WIRE_2_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [8:0] _view__T_2_tag = bypass_3 ? _view__WIRE_2_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_2_offset = bypass_3 ? _view__WIRE_2_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_2_put = bypass_3 ? _view__WIRE_2_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _mshrs_2_io_allocate_bits_repeat_T = mshrs_2_io_allocate_bits_tag == _mshrs_2_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70] wire _mshrs_2_io_allocate_valid_T = sel_2 & will_reload_3; // @[Scheduler.scala:223:28, :232:49, :236:32] wire a_pop_4 = _requests_io_valid[3]; // @[Scheduler.scala:70:24, :225:34] wire b_pop_4 = _requests_io_valid[15]; // @[Scheduler.scala:70:24, :226:34] wire _bypassMatches_T_36 = b_pop_4; // @[Scheduler.scala:226:34, :229:78] wire c_pop_4 = _requests_io_valid[27]; // @[Scheduler.scala:70:24, :227:34] wire _bypassMatches_T_33 = lowerMatches1[3]; // @[Scheduler.scala:200:8, :228:38] wire _bypassMatches_T_34 = c_pop_4 \| request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35] wire _bypassMatches_T_35 = ~c_pop_4; // @[Scheduler.scala:227:34, :229:60] wire _bypassMatches_T_37 = ~b_pop_4; // @[Scheduler.scala:226:34, :229:103] wire _bypassMatches_T_38 = ~a_pop_4; // @[Scheduler.scala:225:34, :229:111] wire _bypassMatches_T_39 = _bypassMatches_T_36 ? _bypassMatches_T_37 : _bypassMatches_T_38; // @[Scheduler.scala:229:{71,78,103,111}] wire _bypassMatches_T_40 = _bypassMatches_T_34 ? _bypassMatches_T_35 : _bypassMatches_T_39; // @[Scheduler.scala:229:{28,35,60,71}] wire bypassMatches_4 = _bypassMatches_T_33 & _bypassMatches_T_40; // @[Scheduler.scala:228:{38,42}, :229:28] wire _may_pop_T_4 = a_pop_4 \| b_pop_4; // @[Scheduler.scala:225:34, :226:34, :230:25] wire may_pop_4 = _may_pop_T_4 \| c_pop_4; // @[Scheduler.scala:227:34, :230:{25,34}] wire bypass_4 = _bypass_T_4 & bypassMatches_4; // @[Scheduler.scala:228:42, :231:{32,41}] wire _will_reload_T_4 = may_pop_4 \| bypass_4; // @[Scheduler.scala:230:34, :231:41, :232:61] wire will_reload_4 = _mshrs_3_io_schedule_bits_reload & _will_reload_T_4; // @[Scheduler.scala:71:46, :232:{49,61}] wire _view__T_3_prio_0 = bypass_4 ? _view__WIRE_3_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_3_prio_1 = ~bypass_4 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78] wire _view__T_3_prio_2 = bypass_4 ? _view__WIRE_3_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_3_control = bypass_4 ? _view__WIRE_3_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_3_opcode = bypass_4 ? _view__WIRE_3_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_3_param = bypass_4 ? _view__WIRE_3_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_3_size = bypass_4 ? _view__WIRE_3_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_3_source = bypass_4 ? _view__WIRE_3_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [8:0] _view__T_3_tag = bypass_4 ? _view__WIRE_3_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_3_offset = bypass_4 ? _view__WIRE_3_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_3_put = bypass_4 ? _view__WIRE_3_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _mshrs_3_io_allocate_bits_repeat_T = mshrs_3_io_allocate_bits_tag == _mshrs_3_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70] wire _mshrs_3_io_allocate_valid_T = sel_3 & will_reload_4; // @[Scheduler.scala:223:28, :232:49, :236:32] wire a_pop_5 = _requests_io_valid[4]; // @[Scheduler.scala:70:24, :225:34] wire b_pop_5 = _requests_io_valid[16]; // @[Scheduler.scala:70:24, :226:34] wire _bypassMatches_T_44 = b_pop_5; // @[Scheduler.scala:226:34, :229:78] wire c_pop_5 = _requests_io_valid[28]; // @[Scheduler.scala:70:24, :227:34] wire _bypassMatches_T_41 = lowerMatches1[4]; // @[Scheduler.scala:200:8, :228:38] wire _bypassMatches_T_42 = c_pop_5 \| request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35] wire _bypassMatches_T_43 = ~c_pop_5; // @[Scheduler.scala:227:34, :229:60] wire _bypassMatches_T_45 = ~b_pop_5; // @[Scheduler.scala:226:34, :229:103] wire _bypassMatches_T_46 = ~a_pop_5; // @[Scheduler.scala:225:34, :229:111] wire _bypassMatches_T_47 = _bypassMatches_T_44 ? _bypassMatches_T_45 : _bypassMatches_T_46; // @[Scheduler.scala:229:{71,78,103,111}] wire _bypassMatches_T_48 = _bypassMatches_T_42 ? _bypassMatches_T_43 : _bypassMatches_T_47; // @[Scheduler.scala:229:{28,35,60,71}] wire bypassMatches_5 = _bypassMatches_T_41 & _bypassMatches_T_48; // @[Scheduler.scala:228:{38,42}, :229:28] wire _may_pop_T_5 = a_pop_5 \| b_pop_5; // @[Scheduler.scala:225:34, :226:34, :230:25] wire may_pop_5 = _may_pop_T_5 \| c_pop_5; // @[Scheduler.scala:227:34, :230:{25,34}] wire bypass_5 = _bypass_T_5 & bypassMatches_5; // @[Scheduler.scala:228:42, :231:{32,41}] wire _will_reload_T_5 = may_pop_5 \| bypass_5; // @[Scheduler.scala:230:34, :231:41, :232:61] wire will_reload_5 = _mshrs_4_io_schedule_bits_reload & _will_reload_T_5; // @[Scheduler.scala:71:46, :232:{49,61}] wire _view__T_4_prio_0 = bypass_5 ? _view__WIRE_4_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_4_prio_1 = ~bypass_5 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78] wire _view__T_4_prio_2 = bypass_5 ? _view__WIRE_4_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_4_control = bypass_5 ? _view__WIRE_4_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_4_opcode = bypass_5 ? _view__WIRE_4_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_4_param = bypass_5 ? _view__WIRE_4_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_4_size = bypass_5 ? _view__WIRE_4_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_4_source = bypass_5 ? _view__WIRE_4_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [8:0] _view__T_4_tag = bypass_5 ? _view__WIRE_4_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_4_offset = bypass_5 ? _view__WIRE_4_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_4_put = bypass_5 ? _view__WIRE_4_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _mshrs_4_io_allocate_bits_repeat_T = mshrs_4_io_allocate_bits_tag == _mshrs_4_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70] wire _mshrs_4_io_allocate_valid_T = sel_4 & will_reload_5; // @[Scheduler.scala:223:28, :232:49, :236:32] wire a_pop_6 = _requests_io_valid[5]; // @[Scheduler.scala:70:24, :225:34] wire b_pop_6 = _requests_io_valid[17]; // @[Scheduler.scala:70:24, :226:34] wire _bypassMatches_T_52 = b_pop_6; // @[Scheduler.scala:226:34, :229:78] wire c_pop_6 = _requests_io_valid[29]; // @[Scheduler.scala:70:24, :227:34] wire _bypassMatches_T_49 = lowerMatches1[5]; // @[Scheduler.scala:200:8, :228:38] wire _bypassMatches_T_50 = c_pop_6 \| request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35] wire _bypassMatches_T_51 = ~c_pop_6; // @[Scheduler.scala:227:34, :229:60] wire _bypassMatches_T_53 = ~b_pop_6; // @[Scheduler.scala:226:34, :229:103] wire _bypassMatches_T_54 = ~a_pop_6; // @[Scheduler.scala:225:34, :229:111] wire _bypassMatches_T_55 = _bypassMatches_T_52 ? _bypassMatches_T_53 : _bypassMatches_T_54; // @[Scheduler.scala:229:{71,78,103,111}] wire _bypassMatches_T_56 = _bypassMatches_T_50 ? _bypassMatches_T_51 : _bypassMatches_T_55; // @[Scheduler.scala:229:{28,35,60,71}] wire bypassMatches_6 = _bypassMatches_T_49 & _bypassMatches_T_56; // @[Scheduler.scala:228:{38,42}, :229:28] wire _may_pop_T_6 = a_pop_6 \| b_pop_6; // @[Scheduler.scala:225:34, :226:34, :230:25] wire may_pop_6 = _may_pop_T_6 \| c_pop_6; // @[Scheduler.scala:227:34, :230:{25,34}] wire bypass_6 = _bypass_T_6 & bypassMatches_6; // @[Scheduler.scala:228:42, :231:{32,41}] wire _will_reload_T_6 = may_pop_6 \| bypass_6; // @[Scheduler.scala:230:34, :231:41, :232:61] wire will_reload_6 = _mshrs_5_io_schedule_bits_reload & _will_reload_T_6; // @[Scheduler.scala:71:46, :232:{49,61}] wire _view__T_5_prio_0 = bypass_6 ? _view__WIRE_5_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_5_prio_1 = ~bypass_6 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78] wire _view__T_5_prio_2 = bypass_6 ? _view__WIRE_5_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_5_control = bypass_6 ? _view__WIRE_5_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_5_opcode = bypass_6 ? _view__WIRE_5_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_5_param = bypass_6 ? _view__WIRE_5_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_5_size = bypass_6 ? _view__WIRE_5_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_5_source = bypass_6 ? _view__WIRE_5_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [8:0] _view__T_5_tag = bypass_6 ? _view__WIRE_5_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_5_offset = bypass_6 ? _view__WIRE_5_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_5_put = bypass_6 ? _view__WIRE_5_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _mshrs_5_io_allocate_bits_repeat_T = mshrs_5_io_allocate_bits_tag == _mshrs_5_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70] wire _mshrs_5_io_allocate_valid_T = sel_5 & will_reload_6; // @[Scheduler.scala:223:28, :232:49, :236:32] wire a_pop_7 = _requests_io_valid[6]; // @[Scheduler.scala:70:24, :225:34] wire b_pop_7 = _requests_io_valid[18]; // @[Scheduler.scala:70:24, :226:34] wire _bypassMatches_T_60 = b_pop_7; // @[Scheduler.scala:226:34, :229:78] wire c_pop_7 = _requests_io_valid[30]; // @[Scheduler.scala:70:24, :227:34] wire _bypassMatches_T_57 = lowerMatches1[6]; // @[Scheduler.scala:200:8, :228:38] wire _bypassMatches_T_58 = c_pop_7 \| request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35] wire _bypassMatches_T_59 = ~c_pop_7; // @[Scheduler.scala:227:34, :229:60] wire _bypassMatches_T_61 = ~b_pop_7; // @[Scheduler.scala:226:34, :229:103] wire _bypassMatches_T_62 = ~a_pop_7; // @[Scheduler.scala:225:34, :229:111] wire _bypassMatches_T_63 = _bypassMatches_T_60 ? _bypassMatches_T_61 : _bypassMatches_T_62; // @[Scheduler.scala:229:{71,78,103,111}] wire _bypassMatches_T_64 = _bypassMatches_T_58 ? _bypassMatches_T_59 : _bypassMatches_T_63; // @[Scheduler.scala:229:{28,35,60,71}] wire bypassMatches_7 = _bypassMatches_T_57 & _bypassMatches_T_64; // @[Scheduler.scala:228:{38,42}, :229:28] wire _may_pop_T_7 = a_pop_7 \| b_pop_7; // @[Scheduler.scala:225:34, :226:34, :230:25] wire may_pop_7 = _may_pop_T_7 \| c_pop_7; // @[Scheduler.scala:227:34, :230:{25,34}] wire bypass_7 = _bypass_T_7 & bypassMatches_7; // @[Scheduler.scala:228:42, :231:{32,41}] wire _will_reload_T_7 = may_pop_7 \| bypass_7; // @[Scheduler.scala:230:34, :231:41, :232:61] wire will_reload_7 = _mshrs_6_io_schedule_bits_reload & _will_reload_T_7; // @[Scheduler.scala:71:46, :232:{49,61}] wire _view__T_6_prio_0 = bypass_7 ? _view__WIRE_6_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_6_prio_1 = ~bypass_7 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78] wire _view__T_6_prio_2 = bypass_7 ? _view__WIRE_6_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_6_control = bypass_7 ? _view__WIRE_6_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_6_opcode = bypass_7 ? _view__WIRE_6_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_6_param = bypass_7 ? _view__WIRE_6_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_6_size = bypass_7 ? _view__WIRE_6_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_6_source = bypass_7 ? _view__WIRE_6_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [8:0] _view__T_6_tag = bypass_7 ? _view__WIRE_6_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_6_offset = bypass_7 ? _view__WIRE_6_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_6_put = bypass_7 ? _view__WIRE_6_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _mshrs_6_io_allocate_bits_repeat_T = mshrs_6_io_allocate_bits_tag == _mshrs_6_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70] wire _mshrs_6_io_allocate_valid_T = sel_6 & will_reload_7; // @[Scheduler.scala:223:28, :232:49, :236:32] wire a_pop_8 = _requests_io_valid[7]; // @[Scheduler.scala:70:24, :225:34] wire b_pop_8 = _requests_io_valid[19]; // @[Scheduler.scala:70:24, :226:34] wire _bypassMatches_T_68 = b_pop_8; // @[Scheduler.scala:226:34, :229:78] wire c_pop_8 = _requests_io_valid[31]; // @[Scheduler.scala:70:24, :227:34] wire _bypassMatches_T_65 = lowerMatches1[7]; // @[Scheduler.scala:200:8, :228:38] wire _bypassMatches_T_66 = c_pop_8 \| request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35] wire _bypassMatches_T_67 = ~c_pop_8; // @[Scheduler.scala:227:34, :229:60] wire _bypassMatches_T_69 = ~b_pop_8; // @[Scheduler.scala:226:34, :229:103] wire _bypassMatches_T_70 = ~a_pop_8; // @[Scheduler.scala:225:34, :229:111] wire _bypassMatches_T_71 = _bypassMatches_T_68 ? _bypassMatches_T_69 : _bypassMatches_T_70; // @[Scheduler.scala:229:{71,78,103,111}] wire _bypassMatches_T_72 = _bypassMatches_T_66 ? _bypassMatches_T_67 : _bypassMatches_T_71; // @[Scheduler.scala:229:{28,35,60,71}] wire bypassMatches_8 = _bypassMatches_T_65 & _bypassMatches_T_72; // @[Scheduler.scala:228:{38,42}, :229:28] wire _may_pop_T_8 = a_pop_8 \| b_pop_8; // @[Scheduler.scala:225:34, :226:34, :230:25] wire may_pop_8 = _may_pop_T_8 \| c_pop_8; // @[Scheduler.scala:227:34, :230:{25,34}] wire bypass_8 = _bypass_T_8 & bypassMatches_8; // @[Scheduler.scala:228:42, :231:{32,41}] wire _will_reload_T_8 = may_pop_8 \| bypass_8; // @[Scheduler.scala:230:34, :231:41, :232:61] wire will_reload_8 = _mshrs_7_io_schedule_bits_reload & _will_reload_T_8; // @[Scheduler.scala:71:46, :232:{49,61}] wire _view__T_7_prio_0 = bypass_8 ? _view__WIRE_7_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_7_prio_1 = ~bypass_8 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78] wire _view__T_7_prio_2 = bypass_8 ? _view__WIRE_7_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_7_control = bypass_8 ? _view__WIRE_7_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_7_opcode = bypass_8 ? _view__WIRE_7_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_7_param = bypass_8 ? _view__WIRE_7_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_7_size = bypass_8 ? _view__WIRE_7_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_7_source = bypass_8 ? _view__WIRE_7_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [8:0] _view__T_7_tag = bypass_8 ? _view__WIRE_7_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_7_offset = bypass_8 ? _view__WIRE_7_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_7_put = bypass_8 ? _view__WIRE_7_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _mshrs_7_io_allocate_bits_repeat_T = mshrs_7_io_allocate_bits_tag == _mshrs_7_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70] wire _mshrs_7_io_allocate_valid_T = sel_7 & will_reload_8; // @[Scheduler.scala:223:28, :232:49, :236:32] wire a_pop_9 = _requests_io_valid[8]; // @[Scheduler.scala:70:24, :225:34] wire b_pop_9 = _requests_io_valid[20]; // @[Scheduler.scala:70:24, :226:34] wire _bypassMatches_T_76 = b_pop_9; // @[Scheduler.scala:226:34, :229:78] wire c_pop_9 = _requests_io_valid[32]; // @[Scheduler.scala:70:24, :227:34] wire _bypassMatches_T_73 = lowerMatches1[8]; // @[Scheduler.scala:200:8, :228:38] wire _bypassMatches_T_74 = c_pop_9 \| request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35] wire _bypassMatches_T_75 = ~c_pop_9; // @[Scheduler.scala:227:34, :229:60] wire _bypassMatches_T_77 = ~b_pop_9; // @[Scheduler.scala:226:34, :229:103] wire _bypassMatches_T_78 = ~a_pop_9; // @[Scheduler.scala:225:34, :229:111] wire _bypassMatches_T_79 = _bypassMatches_T_76 ? _bypassMatches_T_77 : _bypassMatches_T_78; // @[Scheduler.scala:229:{71,78,103,111}] wire _bypassMatches_T_80 = _bypassMatches_T_74 ? _bypassMatches_T_75 : _bypassMatches_T_79; // @[Scheduler.scala:229:{28,35,60,71}] wire bypassMatches_9 = _bypassMatches_T_73 & _bypassMatches_T_80; // @[Scheduler.scala:228:{38,42}, :229:28] wire _may_pop_T_9 = a_pop_9 \| b_pop_9; // @[Scheduler.scala:225:34, :226:34, :230:25] wire may_pop_9 = _may_pop_T_9 \| c_pop_9; // @[Scheduler.scala:227:34, :230:{25,34}] wire bypass_9 = _bypass_T_9 & bypassMatches_9; // @[Scheduler.scala:228:42, :231:{32,41}] wire _will_reload_T_9 = may_pop_9 \| bypass_9; // @[Scheduler.scala:230:34, :231:41, :232:61] wire will_reload_9 = _mshrs_8_io_schedule_bits_reload & _will_reload_T_9; // @[Scheduler.scala:71:46, :232:{49,61}] wire _view__T_8_prio_0 = bypass_9 ? _view__WIRE_8_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_8_prio_1 = ~bypass_9 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78] wire _view__T_8_prio_2 = bypass_9 ? _view__WIRE_8_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_8_control = bypass_9 ? _view__WIRE_8_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_8_opcode = bypass_9 ? _view__WIRE_8_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_8_param = bypass_9 ? _view__WIRE_8_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_8_size = bypass_9 ? _view__WIRE_8_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_8_source = bypass_9 ? _view__WIRE_8_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [8:0] _view__T_8_tag = bypass_9 ? _view__WIRE_8_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_8_offset = bypass_9 ? _view__WIRE_8_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_8_put = bypass_9 ? _view__WIRE_8_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _mshrs_8_io_allocate_bits_repeat_T = mshrs_8_io_allocate_bits_tag == _mshrs_8_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70] wire _mshrs_8_io_allocate_valid_T = sel_8 & will_reload_9; // @[Scheduler.scala:223:28, :232:49, :236:32] wire a_pop_10 = _requests_io_valid[9]; // @[Scheduler.scala:70:24, :225:34] wire b_pop_10 = _requests_io_valid[21]; // @[Scheduler.scala:70:24, :226:34] wire _bypassMatches_T_84 = b_pop_10; // @[Scheduler.scala:226:34, :229:78] wire c_pop_10 = _requests_io_valid[33]; // @[Scheduler.scala:70:24, :227:34] wire _bypassMatches_T_81 = lowerMatches1[9]; // @[Scheduler.scala:200:8, :228:38] wire _bypassMatches_T_82 = c_pop_10 \| request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35] wire _bypassMatches_T_83 = ~c_pop_10; // @[Scheduler.scala:227:34, :229:60] wire _bypassMatches_T_85 = ~b_pop_10; // @[Scheduler.scala:226:34, :229:103] wire _bypassMatches_T_86 = ~a_pop_10; // @[Scheduler.scala:225:34, :229:111] wire _bypassMatches_T_87 = _bypassMatches_T_84 ? _bypassMatches_T_85 : _bypassMatches_T_86; // @[Scheduler.scala:229:{71,78,103,111}] wire _bypassMatches_T_88 = _bypassMatches_T_82 ? _bypassMatches_T_83 : _bypassMatches_T_87; // @[Scheduler.scala:229:{28,35,60,71}] wire bypassMatches_10 = _bypassMatches_T_81 & _bypassMatches_T_88; // @[Scheduler.scala:228:{38,42}, :229:28] wire _may_pop_T_10 = a_pop_10 \| b_pop_10; // @[Scheduler.scala:225:34, :226:34, :230:25] wire may_pop_10 = _may_pop_T_10 \| c_pop_10; // @[Scheduler.scala:227:34, :230:{25,34}] wire bypass_10 = _bypass_T_10 & bypassMatches_10; // @[Scheduler.scala:228:42, :231:{32,41}] wire _will_reload_T_10 = may_pop_10 \| bypass_10; // @[Scheduler.scala:230:34, :231:41, :232:61] wire will_reload_10 = _mshrs_9_io_schedule_bits_reload & _will_reload_T_10; // @[Scheduler.scala:71:46, :232:{49,61}] wire _view__T_9_prio_0 = bypass_10 ? _view__WIRE_9_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_9_prio_1 = ~bypass_10 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78] wire _view__T_9_prio_2 = bypass_10 ? _view__WIRE_9_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_9_control = bypass_10 ? _view__WIRE_9_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_9_opcode = bypass_10 ? _view__WIRE_9_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_9_param = bypass_10 ? _view__WIRE_9_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_9_size = bypass_10 ? _view__WIRE_9_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_9_source = bypass_10 ? _view__WIRE_9_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [8:0] _view__T_9_tag = bypass_10 ? _view__WIRE_9_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_9_offset = bypass_10 ? _view__WIRE_9_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_9_put = bypass_10 ? _view__WIRE_9_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _mshrs_9_io_allocate_bits_repeat_T = mshrs_9_io_allocate_bits_tag == _mshrs_9_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70] wire _mshrs_9_io_allocate_valid_T = sel_9 & will_reload_10; // @[Scheduler.scala:223:28, :232:49, :236:32] wire a_pop_11 = _requests_io_valid[10]; // @[Scheduler.scala:70:24, :225:34] wire b_pop_11 = _requests_io_valid[22]; // @[Scheduler.scala:70:24, :226:34] wire _bypassMatches_T_92 = b_pop_11; // @[Scheduler.scala:226:34, :229:78] wire c_pop_11 = _requests_io_valid[34]; // @[Scheduler.scala:70:24, :227:34] wire _bypassMatches_T_89 = lowerMatches1[10]; // @[Scheduler.scala:200:8, :228:38] wire _bypassMatches_T_90 = c_pop_11 \| request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35] wire _bypassMatches_T_91 = ~c_pop_11; // @[Scheduler.scala:227:34, :229:60] wire _bypassMatches_T_93 = ~b_pop_11; // @[Scheduler.scala:226:34, :229:103] wire _bypassMatches_T_94 = ~a_pop_11; // @[Scheduler.scala:225:34, :229:111] wire _bypassMatches_T_95 = _bypassMatches_T_92 ? _bypassMatches_T_93 : _bypassMatches_T_94; // @[Scheduler.scala:229:{71,78,103,111}] wire _bypassMatches_T_96 = _bypassMatches_T_90 ? _bypassMatches_T_91 : _bypassMatches_T_95; // @[Scheduler.scala:229:{28,35,60,71}] wire bypassMatches_11 = _bypassMatches_T_89 & _bypassMatches_T_96; // @[Scheduler.scala:228:{38,42}, :229:28] wire _may_pop_T_11 = a_pop_11 \| b_pop_11; // @[Scheduler.scala:225:34, :226:34, :230:25] wire may_pop_11 = _may_pop_T_11 \| c_pop_11; // @[Scheduler.scala:227:34, :230:{25,34}] wire bypass_11 = _bypass_T_11 & bypassMatches_11; // @[Scheduler.scala:228:42, :231:{32,41}] wire _will_reload_T_11 = may_pop_11 \| bypass_11; // @[Scheduler.scala:230:34, :231:41, :232:61] wire will_reload_11 = _mshrs_10_io_schedule_bits_reload & _will_reload_T_11; // @[Scheduler.scala:71:46, :232:{49,61}] wire _view__T_10_prio_0 = bypass_11 ? _view__WIRE_10_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_10_prio_1 = ~bypass_11 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78] wire _view__T_10_prio_2 = bypass_11 ? _view__WIRE_10_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_10_control = bypass_11 ? _view__WIRE_10_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_10_opcode = bypass_11 ? _view__WIRE_10_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_10_param = bypass_11 ? _view__WIRE_10_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_10_size = bypass_11 ? _view__WIRE_10_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_10_source = bypass_11 ? _view__WIRE_10_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [8:0] _view__T_10_tag = bypass_11 ? _view__WIRE_10_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_10_offset = bypass_11 ? _view__WIRE_10_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_10_put = bypass_11 ? _view__WIRE_10_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _mshrs_10_io_allocate_bits_repeat_T = mshrs_10_io_allocate_bits_tag == _mshrs_10_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70, :287:131, :289:74] wire _mshrs_10_io_allocate_valid_T = sel_10 & will_reload_11; // @[Scheduler.scala:223:28, :232:49, :236:32] wire a_pop_12 = _requests_io_valid[11]; // @[Scheduler.scala:70:24, :225:34] wire b_pop_12 = _requests_io_valid[23]; // @[Scheduler.scala:70:24, :226:34] wire _bypassMatches_T_100 = b_pop_12; // @[Scheduler.scala:226:34, :229:78] wire c_pop_12 = _requests_io_valid[35]; // @[Scheduler.scala:70:24, :227:34] wire _bypassMatches_T_97 = lowerMatches1[11]; // @[Scheduler.scala:200:8, :228:38] wire _bypassMatches_T_98 = c_pop_12 \| request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35] wire _bypassMatches_T_99 = ~c_pop_12; // @[Scheduler.scala:227:34, :229:60] wire _bypassMatches_T_101 = ~b_pop_12; // @[Scheduler.scala:226:34, :229:103] wire _bypassMatches_T_102 = ~a_pop_12; // @[Scheduler.scala:225:34, :229:111] wire _bypassMatches_T_103 = _bypassMatches_T_100 ? _bypassMatches_T_101 : _bypassMatches_T_102; // @[Scheduler.scala:229:{71,78,103,111}] wire _bypassMatches_T_104 = _bypassMatches_T_98 ? _bypassMatches_T_99 : _bypassMatches_T_103; // @[Scheduler.scala:229:{28,35,60,71}] wire bypassMatches_12 = _bypassMatches_T_97 & _bypassMatches_T_104; // @[Scheduler.scala:228:{38,42}, :229:28] wire _may_pop_T_12 = a_pop_12 \| b_pop_12; // @[Scheduler.scala:225:34, :226:34, :230:25] wire may_pop_12 = _may_pop_T_12 \| c_pop_12; // @[Scheduler.scala:227:34, :230:{25,34}] wire bypass_12 = _bypass_T_12 & bypassMatches_12; // @[Scheduler.scala:228:42, :231:{32,41}] wire _will_reload_T_12 = may_pop_12 \| bypass_12; // @[Scheduler.scala:230:34, :231:41, :232:61] wire will_reload_12 = _mshrs_11_io_schedule_bits_reload & _will_reload_T_12; // @[Scheduler.scala:71:46, :232:{49,61}] wire _view__T_11_prio_0 = bypass_12 ? _view__WIRE_11_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_11_prio_1 = ~bypass_12 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78] wire _view__T_11_prio_2 = bypass_12 ? _view__WIRE_11_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_11_control = bypass_12 ? _view__WIRE_11_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_11_opcode = bypass_12 ? _view__WIRE_11_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_11_param = bypass_12 ? _view__WIRE_11_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_11_size = bypass_12 ? _view__WIRE_11_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_11_source = bypass_12 ? _view__WIRE_11_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [8:0] _view__T_11_tag = bypass_12 ? _view__WIRE_11_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_11_offset = bypass_12 ? _view__WIRE_11_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_11_put = bypass_12 ? _view__WIRE_11_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _mshrs_11_io_allocate_bits_repeat_T = mshrs_11_io_allocate_bits_tag == _mshrs_11_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70, :295:103, :297:73] wire _mshrs_11_io_allocate_valid_T = sel_11 & will_reload_12; // @[Scheduler.scala:223:28, :232:49, :236:32] wire [35:0] _prio_requests_T = ~_requests_io_valid; // @[Scheduler.scala:70:24, :240:25] wire [23:0] _prio_requests_T_1 = _requests_io_valid[35:12]; // @[Scheduler.scala:70:24, :240:65] wire [35:0] _prio_requests_T_2 = {_prio_requests_T[35:24], _prio_requests_T[23:0] \| _prio_requests_T_1}; // @[Scheduler.scala:240:{25,44,65}] wire [11:0] _prio_requests_T_3 = _requests_io_valid[35:24]; // @[Scheduler.scala:70:24, :240:103] wire [35:0] _prio_requests_T_4 = {_prio_requests_T_2[35:12], _prio_requests_T_2[11:0] \| _prio_requests_T_3}; // @[Scheduler.scala:240:{44,82,103}] wire [35:0] prio_requests = ~_prio_requests_T_4; // @[Scheduler.scala:240:{23,82}] wire [35:0] _pop_index_T = {pop_index_hi, mshr_selectOH}; // @[Scheduler.scala:121:70, :241:31] wire [35:0] _pop_index_T_1 = _pop_index_T & prio_requests; // @[Scheduler.scala:240:23, :241:{31,77}] wire [3:0] pop_index_hi_1 = _pop_index_T_1[35:32]; // @[OneHot.scala:30:18] wire [31:0] pop_index_lo = _pop_index_T_1[31:0]; // @[OneHot.scala:31:18] wire _pop_index_T_2 = \|pop_index_hi_1; // @[OneHot.scala:30:18, :32:14] wire [31:0] _pop_index_T_3 = {28'h0, pop_index_hi_1} \| pop_index_lo; // @[OneHot.scala:30:18, :31:18, :32:28] wire [15:0] pop_index_hi_2 = _pop_index_T_3[31:16]; // @[OneHot.scala:30:18, :32:28] wire [15:0] pop_index_lo_1 = _pop_index_T_3[15:0]; // @[OneHot.scala:31:18, :32:28] wire _pop_index_T_4 = \|pop_index_hi_2; // @[OneHot.scala:30:18, :32:14] wire [15:0] _pop_index_T_5 = pop_index_hi_2 \| pop_index_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire [7:0] pop_index_hi_3 = _pop_index_T_5[15:8]; // @[OneHot.scala:30:18, :32:28] wire [7:0] pop_index_lo_2 = _pop_index_T_5[7:0]; // @[OneHot.scala:31:18, :32:28] wire _pop_index_T_6 = \|pop_index_hi_3; // @[OneHot.scala:30:18, :32:14] wire [7:0] _pop_index_T_7 = pop_index_hi_3 \| pop_index_lo_2; // @[OneHot.scala:30:18, :31:18, :32:28] wire [3:0] pop_index_hi_4 = _pop_index_T_7[7:4]; // @[OneHot.scala:30:18, :32:28] wire [3:0] pop_index_lo_3 = _pop_index_T_7[3:0]; // @[OneHot.scala:31:18, :32:28] wire _pop_index_T_8 = \|pop_index_hi_4; // @[OneHot.scala:30:18, :32:14] wire [3:0] _pop_index_T_9 = pop_index_hi_4 \| pop_index_lo_3; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] pop_index_hi_5 = _pop_index_T_9[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] pop_index_lo_4 = _pop_index_T_9[1:0]; // @[OneHot.scala:31:18, :32:28] wire _pop_index_T_10 = \|pop_index_hi_5; // @[OneHot.scala:30:18, :32:14] wire [1:0] _pop_index_T_11 = pop_index_hi_5 \| pop_index_lo_4; // @[OneHot.scala:30:18, :31:18, :32:28] wire _pop_index_T_12 = _pop_index_T_11[1]; // @[OneHot.scala:32:28] wire [1:0] _pop_index_T_13 = {_pop_index_T_10, _pop_index_T_12}; // @[OneHot.scala:32:{10,14}] wire [2:0] _pop_index_T_14 = {_pop_index_T_8, _pop_index_T_13}; // @[OneHot.scala:32:{10,14}] wire [3:0] _pop_index_T_15 = {_pop_index_T_6, _pop_index_T_14}; // @[OneHot.scala:32:{10,14}] wire [4:0] _pop_index_T_16 = {_pop_index_T_4, _pop_index_T_15}; // @[OneHot.scala:32:{10,14}] wire [5:0] pop_index = {_pop_index_T_2, _pop_index_T_16}; // @[OneHot.scala:32:{10,14}] wire lb_tag_mismatch = scheduleTag != _requests_io_data_tag; // @[Mux.scala:30:73] wire mshr_uses_directory_assuming_no_bypass = _mshr_uses_directory_assuming_no_bypass_T & lb_tag_mismatch; // @[Scheduler.scala:246:37, :247:{64,75}] wire mshr_uses_directory_for_lb = will_pop & lb_tag_mismatch; // @[Scheduler.scala:215:45, :246:37, :248:45] wire [8:0] _mshr_uses_directory_T = bypass ? request_bits_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :163:21, :213:39, :249:63] wire _mshr_uses_directory_T_1 = scheduleTag != _mshr_uses_directory_T; // @[Mux.scala:30:73] wire mshr_uses_directory = will_reload & _mshr_uses_directory_T_1; // @[Scheduler.scala:214:37, :249:{41,56}] wire [1:0] mshr_validOH_lo_lo_hi = {_mshrs_2_io_status_valid, _mshrs_1_io_status_valid}; // @[Scheduler.scala:71:46, :252:25] wire [2:0] mshr_validOH_lo_lo = {mshr_validOH_lo_lo_hi, _mshrs_0_io_status_valid}; // @[Scheduler.scala:71:46, :252:25] wire [1:0] mshr_validOH_lo_hi_hi = {_mshrs_5_io_status_valid, _mshrs_4_io_status_valid}; // @[Scheduler.scala:71:46, :252:25] wire [2:0] mshr_validOH_lo_hi = {mshr_validOH_lo_hi_hi, _mshrs_3_io_status_valid}; // @[Scheduler.scala:71:46, :252:25] wire [5:0] mshr_validOH_lo = {mshr_validOH_lo_hi, mshr_validOH_lo_lo}; // @[Scheduler.scala:252:25] wire [1:0] mshr_validOH_hi_lo_hi = {_mshrs_8_io_status_valid, _mshrs_7_io_status_valid}; // @[Scheduler.scala:71:46, :252:25] wire [2:0] mshr_validOH_hi_lo = {mshr_validOH_hi_lo_hi, _mshrs_6_io_status_valid}; // @[Scheduler.scala:71:46, :252:25] wire [1:0] mshr_validOH_hi_hi_hi = {_mshrs_11_io_status_valid, _mshrs_10_io_status_valid}; // @[Scheduler.scala:71:46, :252:25] wire [2:0] mshr_validOH_hi_hi = {mshr_validOH_hi_hi_hi, _mshrs_9_io_status_valid}; // @[Scheduler.scala:71:46, :252:25] wire [5:0] mshr_validOH_hi = {mshr_validOH_hi_hi, mshr_validOH_hi_lo}; // @[Scheduler.scala:252:25] wire [11:0] mshr_validOH = {mshr_validOH_hi, mshr_validOH_lo}; // @[Scheduler.scala:252:25] wire [11:0] _mshr_free_T = ~mshr_validOH; // @[Scheduler.scala:252:25, :253:20] wire [11:0] _mshr_free_T_1 = _mshr_free_T & prioFilter; // @[Scheduler.scala:182:23, :253:{20,34}] wire mshr_free = \|_mshr_free_T_1; // @[Scheduler.scala:253:{34,48}] wire bypassQueue = schedule_reload & bypassMatches; // @[Mux.scala:30:73] wire _request_alloc_cases_T = ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16] wire _request_alloc_cases_T_1 = alloc & _request_alloc_cases_T; // @[Scheduler.scala:173:15, :258:{13,16}] wire _request_alloc_cases_T_2 = _request_alloc_cases_T_1 & mshr_free; // @[Scheduler.scala:253:48, :258:{13,56}] wire _request_alloc_cases_T_9 = _request_alloc_cases_T_2; // @[Scheduler.scala:258:{56,70}] wire _request_alloc_cases_T_3 = ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :259:16] wire _request_alloc_cases_T_5 = ~_mshrs_10_io_status_valid; // @[Scheduler.scala:71:46, :259:59] wire _request_alloc_cases_T_7 = ~_mshrs_11_io_status_valid; // @[Scheduler.scala:71:46, :259:87] wire _request_alloc_cases_T_10 = ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :260:16] wire _request_alloc_cases_T_11 = nestC & _request_alloc_cases_T_10; // @[Scheduler.scala:180:70, :260:{13,16}] wire _request_alloc_cases_T_12 = ~_mshrs_11_io_status_valid; // @[Scheduler.scala:71:46, :259:87, :260:59] wire _request_alloc_cases_T_13 = _request_alloc_cases_T_11 & _request_alloc_cases_T_12; // @[Scheduler.scala:260:{13,56,59}] wire request_alloc_cases = _request_alloc_cases_T_9 \| _request_alloc_cases_T_13; // @[Scheduler.scala:258:70, :259:112, :260:56] wire _request_ready_T = bypassQueue \| _requests_io_push_ready; // @[Scheduler.scala:70:24, :256:37, :261:66] wire _request_ready_T_1 = queue & _request_ready_T; // @[Scheduler.scala:185:63, :261:{50,66}] assign _request_ready_T_2 = request_alloc_cases \| _request_ready_T_1; // @[Scheduler.scala:259:112, :261:{40,50}] assign request_ready = _request_ready_T_2; // @[Scheduler.scala:163:21, :261:40] wire alloc_uses_directory = request_valid & request_alloc_cases; // @[Scheduler.scala:163:21, :259:112, :262:44] wire _directory_io_read_valid_T = mshr_uses_directory \| alloc_uses_directory; // @[Scheduler.scala:249:41, :262:44, :265:50] wire [10:0] _directory_io_read_bits_set_T = mshr_uses_directory_for_lb ? scheduleSet : request_bits_set; // @[Mux.scala:30:73] wire [8:0] _directory_io_read_bits_tag_T = mshr_uses_directory_for_lb ? _requests_io_data_tag : request_bits_tag; // @[Scheduler.scala:70:24, :163:21, :248:45, :267:36] wire _requests_io_push_valid_T_1 = ~bypassQueue; // @[Scheduler.scala:256:37, :270:55] wire _requests_io_push_valid_T_2 = _requests_io_push_valid_T & _requests_io_push_valid_T_1; // @[Scheduler.scala:270:{43,52,55}] wire [3:0] requests_io_push_bits_index_hi = _requests_io_push_bits_index_T[11:8]; // @[OneHot.scala:30:18] wire [7:0] requests_io_push_bits_index_lo = _requests_io_push_bits_index_T[7:0]; // @[OneHot.scala:31:18] wire _requests_io_push_bits_index_T_1 = \|requests_io_push_bits_index_hi; // @[OneHot.scala:30:18, :32:14] wire [7:0] _requests_io_push_bits_index_T_2 = {4'h0, requests_io_push_bits_index_hi} \| requests_io_push_bits_index_lo; // @[OneHot.scala:30:18, :31:18, :32:28] wire [3:0] requests_io_push_bits_index_hi_1 = _requests_io_push_bits_index_T_2[7:4]; // @[OneHot.scala:30:18, :32:28] wire [3:0] requests_io_push_bits_index_lo_1 = _requests_io_push_bits_index_T_2[3:0]; // @[OneHot.scala:31:18, :32:28] wire _requests_io_push_bits_index_T_3 = \|requests_io_push_bits_index_hi_1; // @[OneHot.scala:30:18, :32:14] wire [3:0] _requests_io_push_bits_index_T_4 = requests_io_push_bits_index_hi_1 \| requests_io_push_bits_index_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] requests_io_push_bits_index_hi_2 = _requests_io_push_bits_index_T_4[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] requests_io_push_bits_index_lo_2 = _requests_io_push_bits_index_T_4[1:0]; // @[OneHot.scala:31:18, :32:28] wire _requests_io_push_bits_index_T_5 = \|requests_io_push_bits_index_hi_2; // @[OneHot.scala:30:18, :32:14] wire [1:0] _requests_io_push_bits_index_T_6 = requests_io_push_bits_index_hi_2 \| requests_io_push_bits_index_lo_2; // @[OneHot.scala:30:18, :31:18, :32:28] wire _requests_io_push_bits_index_T_7 = _requests_io_push_bits_index_T_6[1]; // @[OneHot.scala:32:28] wire [1:0] _requests_io_push_bits_index_T_8 = {_requests_io_push_bits_index_T_5, _requests_io_push_bits_index_T_7}; // @[OneHot.scala:32:{10,14}] wire [2:0] _requests_io_push_bits_index_T_9 = {_requests_io_push_bits_index_T_3, _requests_io_push_bits_index_T_8}; // @[OneHot.scala:32:{10,14}] wire [3:0] _requests_io_push_bits_index_T_10 = {_requests_io_push_bits_index_T_1, _requests_io_push_bits_index_T_9}; // @[OneHot.scala:32:{10,14}] wire [23:0] _requests_io_push_bits_index_T_11 = {lowerMatches1, 12'h0}; // @[Scheduler.scala:200:8, :275:30] wire [7:0] requests_io_push_bits_index_hi_3 = _requests_io_push_bits_index_T_11[23:16]; // @[OneHot.scala:30:18] wire [15:0] requests_io_push_bits_index_lo_3 = _requests_io_push_bits_index_T_11[15:0]; // @[OneHot.scala:31:18] wire _requests_io_push_bits_index_T_12 = \|requests_io_push_bits_index_hi_3; // @[OneHot.scala:30:18, :32:14] wire [15:0] _requests_io_push_bits_index_T_13 = {8'h0, requests_io_push_bits_index_hi_3} \| requests_io_push_bits_index_lo_3; // @[OneHot.scala:30:18, :31:18, :32:28] wire [7:0] requests_io_push_bits_index_hi_4 = _requests_io_push_bits_index_T_13[15:8]; // @[OneHot.scala:30:18, :32:28] wire [7:0] requests_io_push_bits_index_lo_4 = _requests_io_push_bits_index_T_13[7:0]; // @[OneHot.scala:31:18, :32:28] wire _requests_io_push_bits_index_T_14 = \|requests_io_push_bits_index_hi_4; // @[OneHot.scala:30:18, :32:14] wire [7:0] _requests_io_push_bits_index_T_15 = requests_io_push_bits_index_hi_4 \| requests_io_push_bits_index_lo_4; // @[OneHot.scala:30:18, :31:18, :32:28] wire [3:0] requests_io_push_bits_index_hi_5 = _requests_io_push_bits_index_T_15[7:4]; // @[OneHot.scala:30:18, :32:28] wire [3:0] requests_io_push_bits_index_lo_5 = _requests_io_push_bits_index_T_15[3:0]; // @[OneHot.scala:31:18, :32:28] wire _requests_io_push_bits_index_T_16 = \|requests_io_push_bits_index_hi_5; // @[OneHot.scala:30:18, :32:14] wire [3:0] _requests_io_push_bits_index_T_17 = requests_io_push_bits_index_hi_5 \| requests_io_push_bits_index_lo_5; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] requests_io_push_bits_index_hi_6 = _requests_io_push_bits_index_T_17[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] requests_io_push_bits_index_lo_6 = _requests_io_push_bits_index_T_17[1:0]; // @[OneHot.scala:31:18, :32:28] wire _requests_io_push_bits_index_T_18 = \|requests_io_push_bits_index_hi_6; // @[OneHot.scala:30:18, :32:14] wire [1:0] _requests_io_push_bits_index_T_19 = requests_io_push_bits_index_hi_6 \| requests_io_push_bits_index_lo_6; // @[OneHot.scala:30:18, :31:18, :32:28] wire _requests_io_push_bits_index_T_20 = _requests_io_push_bits_index_T_19[1]; // @[OneHot.scala:32:28] wire [1:0] _requests_io_push_bits_index_T_21 = {_requests_io_push_bits_index_T_18, _requests_io_push_bits_index_T_20}; // @[OneHot.scala:32:{10,14}] wire [2:0] _requests_io_push_bits_index_T_22 = {_requests_io_push_bits_index_T_16, _requests_io_push_bits_index_T_21}; // @[OneHot.scala:32:{10,14}] wire [3:0] _requests_io_push_bits_index_T_23 = {_requests_io_push_bits_index_T_14, _requests_io_push_bits_index_T_22}; // @[OneHot.scala:32:{10,14}] wire [4:0] _requests_io_push_bits_index_T_24 = {_requests_io_push_bits_index_T_12, _requests_io_push_bits_index_T_23}; // @[OneHot.scala:32:{10,14}] wire [35:0] _requests_io_push_bits_index_T_25 = {lowerMatches1, 24'h0}; // @[Scheduler.scala:200:8, :276:30] wire [3:0] requests_io_push_bits_index_hi_7 = _requests_io_push_bits_index_T_25[35:32]; // @[OneHot.scala:30:18] wire [31:0] requests_io_push_bits_index_lo_7 = _requests_io_push_bits_index_T_25[31:0]; // @[OneHot.scala:31:18] wire _requests_io_push_bits_index_T_26 = \|requests_io_push_bits_index_hi_7; // @[OneHot.scala:30:18, :32:14] wire [31:0] _requests_io_push_bits_index_T_27 = {28'h0, requests_io_push_bits_index_hi_7} \| requests_io_push_bits_index_lo_7; // @[OneHot.scala:30:18, :31:18, :32:28] wire [15:0] requests_io_push_bits_index_hi_8 = _requests_io_push_bits_index_T_27[31:16]; // @[OneHot.scala:30:18, :32:28] wire [15:0] requests_io_push_bits_index_lo_8 = _requests_io_push_bits_index_T_27[15:0]; // @[OneHot.scala:31:18, :32:28] wire _requests_io_push_bits_index_T_28 = \|requests_io_push_bits_index_hi_8; // @[OneHot.scala:30:18, :32:14] wire [15:0] _requests_io_push_bits_index_T_29 = requests_io_push_bits_index_hi_8 \| requests_io_push_bits_index_lo_8; // @[OneHot.scala:30:18, :31:18, :32:28] wire [7:0] requests_io_push_bits_index_hi_9 = _requests_io_push_bits_index_T_29[15:8]; // @[OneHot.scala:30:18, :32:28] wire [7:0] requests_io_push_bits_index_lo_9 = _requests_io_push_bits_index_T_29[7:0]; // @[OneHot.scala:31:18, :32:28] wire _requests_io_push_bits_index_T_30 = \|requests_io_push_bits_index_hi_9; // @[OneHot.scala:30:18, :32:14] wire [7:0] _requests_io_push_bits_index_T_31 = requests_io_push_bits_index_hi_9 \| requests_io_push_bits_index_lo_9; // @[OneHot.scala:30:18, :31:18, :32:28] wire [3:0] requests_io_push_bits_index_hi_10 = _requests_io_push_bits_index_T_31[7:4]; // @[OneHot.scala:30:18, :32:28] wire [3:0] requests_io_push_bits_index_lo_10 = _requests_io_push_bits_index_T_31[3:0]; // @[OneHot.scala:31:18, :32:28] wire _requests_io_push_bits_index_T_32 = \|requests_io_push_bits_index_hi_10; // @[OneHot.scala:30:18, :32:14] wire [3:0] _requests_io_push_bits_index_T_33 = requests_io_push_bits_index_hi_10 \| requests_io_push_bits_index_lo_10; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] requests_io_push_bits_index_hi_11 = _requests_io_push_bits_index_T_33[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] requests_io_push_bits_index_lo_11 = _requests_io_push_bits_index_T_33[1:0]; // @[OneHot.scala:31:18, :32:28] wire _requests_io_push_bits_index_T_34 = \|requests_io_push_bits_index_hi_11; // @[OneHot.scala:30:18, :32:14] wire [1:0] _requests_io_push_bits_index_T_35 = requests_io_push_bits_index_hi_11 \| requests_io_push_bits_index_lo_11; // @[OneHot.scala:30:18, :31:18, :32:28] wire _requests_io_push_bits_index_T_36 = _requests_io_push_bits_index_T_35[1]; // @[OneHot.scala:32:28] wire [1:0] _requests_io_push_bits_index_T_37 = {_requests_io_push_bits_index_T_34, _requests_io_push_bits_index_T_36}; // @[OneHot.scala:32:{10,14}] wire [2:0] _requests_io_push_bits_index_T_38 = {_requests_io_push_bits_index_T_32, _requests_io_push_bits_index_T_37}; // @[OneHot.scala:32:{10,14}] wire [3:0] _requests_io_push_bits_index_T_39 = {_requests_io_push_bits_index_T_30, _requests_io_push_bits_index_T_38}; // @[OneHot.scala:32:{10,14}] wire [4:0] _requests_io_push_bits_index_T_40 = {_requests_io_push_bits_index_T_28, _requests_io_push_bits_index_T_39}; // @[OneHot.scala:32:{10,14}] wire [5:0] _requests_io_push_bits_index_T_41 = {_requests_io_push_bits_index_T_26, _requests_io_push_bits_index_T_40}; // @[OneHot.scala:32:{10,14}] wire [3:0] _requests_io_push_bits_index_T_42 = request_bits_prio_0 ? _requests_io_push_bits_index_T_10 : 4'h0; // @[OneHot.scala:32:10] wire [5:0] _requests_io_push_bits_index_T_44 = request_bits_prio_2 ? _requests_io_push_bits_index_T_41 : 6'h0; // @[OneHot.scala:32:10] wire [4:0] _requests_io_push_bits_index_T_45 = {1'h0, _requests_io_push_bits_index_T_42}; // @[Mux.scala:30:73] wire [5:0] _requests_io_push_bits_index_T_46 = {1'h0, _requests_io_push_bits_index_T_45} \| _requests_io_push_bits_index_T_44; // @[Mux.scala:30:73] wire [5:0] _requests_io_push_bits_index_WIRE = _requests_io_push_bits_index_T_46; // @[Mux.scala:30:73] wire [11:0] _mshr_insertOH_T = ~mshr_validOH; // @[Scheduler.scala:252:25, :253:20, :278:32] wire [12:0] _mshr_insertOH_T_1 = {_mshr_insertOH_T, 1'h0}; // @[package.scala:253:48] wire [11:0] _mshr_insertOH_T_2 = _mshr_insertOH_T_1[11:0]; // @[package.scala:253:{48,53}] wire [11:0] _mshr_insertOH_T_3 = _mshr_insertOH_T \| _mshr_insertOH_T_2; // @[package.scala:253:{43,53}] wire [13:0] _mshr_insertOH_T_4 = {_mshr_insertOH_T_3, 2'h0}; // @[package.scala:253:{43,48}] wire [11:0] _mshr_insertOH_T_5 = _mshr_insertOH_T_4[11:0]; // @[package.scala:253:{48,53}] wire [11:0] _mshr_insertOH_T_6 = _mshr_insertOH_T_3 \| _mshr_insertOH_T_5; // @[package.scala:253:{43,53}] wire [15:0] _mshr_insertOH_T_7 = {_mshr_insertOH_T_6, 4'h0}; // @[package.scala:253:{43,48}] wire [11:0] _mshr_insertOH_T_8 = _mshr_insertOH_T_7[11:0]; // @[package.scala:253:{48,53}] wire [11:0] _mshr_insertOH_T_9 = _mshr_insertOH_T_6 \| _mshr_insertOH_T_8; // @[package.scala:253:{43,53}] wire [19:0] _mshr_insertOH_T_10 = {_mshr_insertOH_T_9, 8'h0}; // @[package.scala:253:{43,48}] wire [11:0] _mshr_insertOH_T_11 = _mshr_insertOH_T_10[11:0]; // @[package.scala:253:{48,53}] wire [11:0] _mshr_insertOH_T_12 = _mshr_insertOH_T_9 \| _mshr_insertOH_T_11; // @[package.scala:253:{43,53}] wire [11:0] _mshr_insertOH_T_13 = _mshr_insertOH_T_12; // @[package.scala:253:43, :254:17] wire [12:0] _mshr_insertOH_T_14 = {_mshr_insertOH_T_13, 1'h0}; // @[package.scala:254:17] wire [12:0] _mshr_insertOH_T_15 = ~_mshr_insertOH_T_14; // @[Scheduler.scala:278:{23,47}] wire [11:0] _mshr_insertOH_T_16 = ~mshr_validOH; // @[Scheduler.scala:252:25, :253:20, :278:55] wire [12:0] _mshr_insertOH_T_17 = {1'h0, _mshr_insertOH_T_15[11:0] & _mshr_insertOH_T_16}; // @[Scheduler.scala:278:{23,53,55}] wire [12:0] mshr_insertOH = {1'h0, _mshr_insertOH_T_17[11:0] & prioFilter}; // @[Scheduler.scala:182:23, :278:{53,69}] wire _T_76 = request_valid & alloc; // @[Scheduler.scala:163:21, :173:15, :280:25] wire _T_35 = _T_76 & mshr_insertOH[0] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}] assign mshrs_0_io_allocate_bits_tag = _T_35 ? request_bits_tag : _view__T_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70] wire _T_39 = _T_76 & mshr_insertOH[1] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}] assign mshrs_1_io_allocate_bits_tag = _T_39 ? request_bits_tag : _view__T_1_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70] wire _T_43 = _T_76 & mshr_insertOH[2] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}] assign mshrs_2_io_allocate_bits_tag = _T_43 ? request_bits_tag : _view__T_2_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70] wire _T_47 = _T_76 & mshr_insertOH[3] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}] assign mshrs_3_io_allocate_bits_tag = _T_47 ? request_bits_tag : _view__T_3_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70] wire _T_51 = _T_76 & mshr_insertOH[4] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}] assign mshrs_4_io_allocate_bits_tag = _T_51 ? request_bits_tag : _view__T_4_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70] wire _T_55 = _T_76 & mshr_insertOH[5] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}] assign mshrs_5_io_allocate_bits_tag = _T_55 ? request_bits_tag : _view__T_5_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70] wire _T_59 = _T_76 & mshr_insertOH[6] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}] assign mshrs_6_io_allocate_bits_tag = _T_59 ? request_bits_tag : _view__T_6_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70] wire _T_63 = _T_76 & mshr_insertOH[7] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}] assign mshrs_7_io_allocate_bits_tag = _T_63 ? request_bits_tag : _view__T_7_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70] wire _T_67 = _T_76 & mshr_insertOH[8] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}] assign mshrs_8_io_allocate_bits_tag = _T_67 ? request_bits_tag : _view__T_8_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70] wire _T_71 = _T_76 & mshr_insertOH[9] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}] assign mshrs_9_io_allocate_bits_tag = _T_71 ? request_bits_tag : _view__T_9_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70] wire _T_75 = _T_76 & mshr_insertOH[10] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}] assign mshrs_10_io_allocate_bits_tag = _T_75 ? request_bits_tag : _view__T_10_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70, :287:131, :289:74] wire _T_95 = request_valid & nestC & ~_mshrs_11_io_status_valid & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:71:46, :163:21, :180:70, :193:33, :247:75, :258:16, :259:87, :295:{32,59}] wire _GEN_3 = _T_95 \| _T_76 & mshr_insertOH[11] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:193:33, :236:25, :247:75, :258:16, :278:69, :279:18, :280:{25,34,39,83}, :281:27, :295:{32,59,103}, :296:30] assign mshrs_11_io_allocate_bits_tag = _GEN_3 ? request_bits_tag : _view__T_11_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :236:25, :280:83, :281:27, :282:70, :295:103, :296:30, :297:73]
Generate the Verilog code corresponding to this FIRRTL code module NoCMonitor_2 : input clock : Clock input reset : Reset output io : { flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], credit_return : UInt<3>, vc_free : UInt<3>}} wire _in_flight_WIRE : UInt<1>[3] connect _in_flight_WIRE[0], UInt<1>(0h0) connect _in_flight_WIRE[1], UInt<1>(0h0) connect _in_flight_WIRE[2], UInt<1>(0h0) regreset in_flight : UInt<1>[3], clock, reset, _in_flight_WIRE when io.in.flit[0].valid : when io.in.flit[0].bits.head : connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h1) node _T = eq(in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: Flit head/tail sequencing is broken\n at Monitor.scala:22 assert (!in_flight(flit.bits.virt_channel_id), \"Flit head/tail sequencing is broken\")\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert when io.in.flit[0].bits.tail : connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0) node _T_4 = and(io.in.flit[0].valid, io.in.flit[0].bits.head) when _T_4 : node _T_5 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h0)) node _T_6 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_7 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h1)) node _T_8 = and(_T_6, _T_7) node _T_9 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<3>(0h4)) node _T_10 = and(_T_8, _T_9) node _T_11 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_12 = and(_T_10, _T_11) node _T_13 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_14 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_15 = and(_T_13, _T_14) node _T_16 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<3>(0h4)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_19 = and(_T_17, _T_18) node _T_20 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_21 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hf)) node _T_22 = and(_T_20, _T_21) node _T_23 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<3>(0h4)) node _T_24 = and(_T_22, _T_23) node _T_25 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_26 = and(_T_24, _T_25) node _T_27 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_28 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0he)) node _T_29 = and(_T_27, _T_28) node _T_30 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<3>(0h4)) node _T_31 = and(_T_29, _T_30) node _T_32 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_33 = and(_T_31, _T_32) node _T_34 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_35 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb)) node _T_36 = and(_T_34, _T_35) node _T_37 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<3>(0h4)) node _T_38 = and(_T_36, _T_37) node _T_39 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_40 = and(_T_38, _T_39) node _T_41 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_42 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h2)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<3>(0h4)) node _T_45 = and(_T_43, _T_44) node _T_46 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_47 = and(_T_45, _T_46) node _T_48 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_49 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_50 = and(_T_48, _T_49) node _T_51 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<3>(0h4)) node _T_52 = and(_T_50, _T_51) node _T_53 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_54 = and(_T_52, _T_53) node _T_55 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_56 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd)) node _T_57 = and(_T_55, _T_56) node _T_58 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<3>(0h4)) node _T_59 = and(_T_57, _T_58) node _T_60 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_61 = and(_T_59, _T_60) node _T_62 = or(_T_12, _T_19) node _T_63 = or(_T_62, _T_26) node _T_64 = or(_T_63, _T_33) node _T_65 = or(_T_64, _T_40) node _T_66 = or(_T_65, _T_47) node _T_67 = or(_T_66, _T_54) node _T_68 = or(_T_67, _T_61) node _T_69 = or(_T_5, _T_68) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_1 assert(clock, _T_69, UInt<1>(0h1), "") : assert_1 node _T_73 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h1)) node _T_74 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_75 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_76 = and(_T_74, _T_75) node _T_77 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h3)) node _T_78 = and(_T_76, _T_77) node _T_79 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_80 = and(_T_78, _T_79) node _T_81 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_82 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_83 = and(_T_81, _T_82) node _T_84 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h3)) node _T_85 = and(_T_83, _T_84) node _T_86 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_87 = and(_T_85, _T_86) node _T_88 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_89 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_90 = and(_T_88, _T_89) node _T_91 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h3)) node _T_92 = and(_T_90, _T_91) node _T_93 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_94 = and(_T_92, _T_93) node _T_95 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_96 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_97 = and(_T_95, _T_96) node _T_98 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h3)) node _T_99 = and(_T_97, _T_98) node _T_100 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_101 = and(_T_99, _T_100) node _T_102 = or(_T_80, _T_87) node _T_103 = or(_T_102, _T_94) node _T_104 = or(_T_103, _T_101) node _T_105 = or(_T_73, _T_104) node _T_106 = asUInt(reset) node _T_107 = eq(_T_106, UInt<1>(0h0)) when _T_107 : node _T_108 = eq(_T_105, UInt<1>(0h0)) when _T_108 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_2 assert(clock, _T_105, UInt<1>(0h1), "") : assert_2 node _T_109 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h2)) node _T_110 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_111 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_112 = and(_T_110, _T_111) node _T_113 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_114 = and(_T_112, _T_113) node _T_115 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_116 = and(_T_114, _T_115) node _T_117 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_118 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_119 = and(_T_117, _T_118) node _T_120 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_121 = and(_T_119, _T_120) node _T_122 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_123 = and(_T_121, _T_122) node _T_124 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_125 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_126 = and(_T_124, _T_125) node _T_127 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_128 = and(_T_126, _T_127) node _T_129 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_130 = and(_T_128, _T_129) node _T_131 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_132 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_133 = and(_T_131, _T_132) node _T_134 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_135 = and(_T_133, _T_134) node _T_136 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_137 = and(_T_135, _T_136) node _T_138 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_139 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_140 = and(_T_138, _T_139) node _T_141 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_142 = and(_T_140, _T_141) node _T_143 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_144 = and(_T_142, _T_143) node _T_145 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_146 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_147 = and(_T_145, _T_146) node _T_148 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_149 = and(_T_147, _T_148) node _T_150 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_151 = and(_T_149, _T_150) node _T_152 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_153 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_154 = and(_T_152, _T_153) node _T_155 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_156 = and(_T_154, _T_155) node _T_157 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_158 = and(_T_156, _T_157) node _T_159 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_160 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_161 = and(_T_159, _T_160) node _T_162 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_163 = and(_T_161, _T_162) node _T_164 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(_T_116, _T_123) node _T_167 = or(_T_166, _T_130) node _T_168 = or(_T_167, _T_137) node _T_169 = or(_T_168, _T_144) node _T_170 = or(_T_169, _T_151) node _T_171 = or(_T_170, _T_158) node _T_172 = or(_T_171, _T_165) node _T_173 = or(_T_109, _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_3 assert(clock, _T_173, UInt<1>(0h1), "") : assert_3	module NoCMonitor_2( // @[Monitor.scala:11:7] input clock, // @[Monitor.scala:11:7] input reset, // @[Monitor.scala:11:7] input io_in_flit_0_valid, // @[Monitor.scala:12:14] input io_in_flit_0_bits_head, // @[Monitor.scala:12:14] input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14] input [2:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14] ); reg in_flight_0; // @[Monitor.scala:16:26] reg in_flight_1; // @[Monitor.scala:16:26] reg in_flight_2; // @[Monitor.scala:16:26]
Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_76 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0)) node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1)) node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3)) node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4)) node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6)) node _roundMagUp_T = and(roundingMode_min, io.in.sign) node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0)) node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1) node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2) node adjustedSig = shl(io.in.sig, 0) node doShiftSigDown1 = bits(adjustedSig, 26, 26) wire common_expOut : UInt<9> wire common_fractOut : UInt<23> wire common_overflow : UInt<1> wire common_totalUnderflow : UInt<1> wire common_underflow : UInt<1> wire common_inexact : UInt<1> node _roundMask_T = bits(io.in.sExp, 8, 0) node _roundMask_T_1 = not(_roundMask_T) node roundMask_msb = bits(_roundMask_T_1, 8, 8) node roundMask_lsbs = bits(_roundMask_T_1, 7, 0) node roundMask_msb_1 = bits(roundMask_lsbs, 7, 7) node roundMask_lsbs_1 = bits(roundMask_lsbs, 6, 0) node roundMask_msb_2 = bits(roundMask_lsbs_1, 6, 6) node roundMask_lsbs_2 = bits(roundMask_lsbs_1, 5, 0) node roundMask_shift = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_2) node _roundMask_T_2 = bits(roundMask_shift, 63, 42) node _roundMask_T_3 = bits(_roundMask_T_2, 15, 0) node _roundMask_T_4 = shl(UInt<8>(0hff), 8) node _roundMask_T_5 = xor(UInt<16>(0hffff), _roundMask_T_4) node _roundMask_T_6 = shr(_roundMask_T_3, 8) node _roundMask_T_7 = and(_roundMask_T_6, _roundMask_T_5) node _roundMask_T_8 = bits(_roundMask_T_3, 7, 0) node _roundMask_T_9 = shl(_roundMask_T_8, 8) node _roundMask_T_10 = not(_roundMask_T_5) node _roundMask_T_11 = and(_roundMask_T_9, _roundMask_T_10) node _roundMask_T_12 = or(_roundMask_T_7, _roundMask_T_11) node _roundMask_T_13 = bits(_roundMask_T_5, 11, 0) node _roundMask_T_14 = shl(_roundMask_T_13, 4) node _roundMask_T_15 = xor(_roundMask_T_5, _roundMask_T_14) node _roundMask_T_16 = shr(_roundMask_T_12, 4) node _roundMask_T_17 = and(_roundMask_T_16, _roundMask_T_15) node _roundMask_T_18 = bits(_roundMask_T_12, 11, 0) node _roundMask_T_19 = shl(_roundMask_T_18, 4) node _roundMask_T_20 = not(_roundMask_T_15) node _roundMask_T_21 = and(_roundMask_T_19, _roundMask_T_20) node _roundMask_T_22 = or(_roundMask_T_17, _roundMask_T_21) node _roundMask_T_23 = bits(_roundMask_T_15, 13, 0) node _roundMask_T_24 = shl(_roundMask_T_23, 2) node _roundMask_T_25 = xor(_roundMask_T_15, _roundMask_T_24) node _roundMask_T_26 = shr(_roundMask_T_22, 2) node _roundMask_T_27 = and(_roundMask_T_26, _roundMask_T_25) node _roundMask_T_28 = bits(_roundMask_T_22, 13, 0) node _roundMask_T_29 = shl(_roundMask_T_28, 2) node _roundMask_T_30 = not(_roundMask_T_25) node _roundMask_T_31 = and(_roundMask_T_29, _roundMask_T_30) node _roundMask_T_32 = or(_roundMask_T_27, _roundMask_T_31) node _roundMask_T_33 = bits(_roundMask_T_25, 14, 0) node _roundMask_T_34 = shl(_roundMask_T_33, 1) node _roundMask_T_35 = xor(_roundMask_T_25, _roundMask_T_34) node _roundMask_T_36 = shr(_roundMask_T_32, 1) node _roundMask_T_37 = and(_roundMask_T_36, _roundMask_T_35) node _roundMask_T_38 = bits(_roundMask_T_32, 14, 0) node _roundMask_T_39 = shl(_roundMask_T_38, 1) node _roundMask_T_40 = not(_roundMask_T_35) node _roundMask_T_41 = and(_roundMask_T_39, _roundMask_T_40) node _roundMask_T_42 = or(_roundMask_T_37, _roundMask_T_41) node _roundMask_T_43 = bits(_roundMask_T_2, 21, 16) node _roundMask_T_44 = bits(_roundMask_T_43, 3, 0) node _roundMask_T_45 = bits(_roundMask_T_44, 1, 0) node _roundMask_T_46 = bits(_roundMask_T_45, 0, 0) node _roundMask_T_47 = bits(_roundMask_T_45, 1, 1) node _roundMask_T_48 = cat(_roundMask_T_46, _roundMask_T_47) node _roundMask_T_49 = bits(_roundMask_T_44, 3, 2) node _roundMask_T_50 = bits(_roundMask_T_49, 0, 0) node _roundMask_T_51 = bits(_roundMask_T_49, 1, 1) node _roundMask_T_52 = cat(_roundMask_T_50, _roundMask_T_51) node _roundMask_T_53 = cat(_roundMask_T_48, _roundMask_T_52) node _roundMask_T_54 = bits(_roundMask_T_43, 5, 4) node _roundMask_T_55 = bits(_roundMask_T_54, 0, 0) node _roundMask_T_56 = bits(_roundMask_T_54, 1, 1) node _roundMask_T_57 = cat(_roundMask_T_55, _roundMask_T_56) node _roundMask_T_58 = cat(_roundMask_T_53, _roundMask_T_57) node _roundMask_T_59 = cat(_roundMask_T_42, _roundMask_T_58) node _roundMask_T_60 = not(_roundMask_T_59) node _roundMask_T_61 = mux(roundMask_msb_2, UInt<1>(0h0), _roundMask_T_60) node _roundMask_T_62 = not(_roundMask_T_61) node _roundMask_T_63 = cat(_roundMask_T_62, UInt<3>(0h7)) node roundMask_msb_3 = bits(roundMask_lsbs_1, 6, 6) node roundMask_lsbs_3 = bits(roundMask_lsbs_1, 5, 0) node roundMask_shift_1 = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_3) node _roundMask_T_64 = bits(roundMask_shift_1, 2, 0) node _roundMask_T_65 = bits(_roundMask_T_64, 1, 0) node _roundMask_T_66 = bits(_roundMask_T_65, 0, 0) node _roundMask_T_67 = bits(_roundMask_T_65, 1, 1) node _roundMask_T_68 = cat(_roundMask_T_66, _roundMask_T_67) node _roundMask_T_69 = bits(_roundMask_T_64, 2, 2) node _roundMask_T_70 = cat(_roundMask_T_68, _roundMask_T_69) node _roundMask_T_71 = mux(roundMask_msb_3, _roundMask_T_70, UInt<1>(0h0)) node _roundMask_T_72 = mux(roundMask_msb_1, _roundMask_T_63, _roundMask_T_71) node _roundMask_T_73 = mux(roundMask_msb, _roundMask_T_72, UInt<1>(0h0)) node _roundMask_T_74 = or(_roundMask_T_73, doShiftSigDown1) node roundMask = cat(_roundMask_T_74, UInt<2>(0h3)) node _shiftedRoundMask_T = cat(UInt<1>(0h0), roundMask) node shiftedRoundMask = shr(_shiftedRoundMask_T, 1) node _roundPosMask_T = not(shiftedRoundMask) node roundPosMask = and(_roundPosMask_T, roundMask) node _roundPosBit_T = and(adjustedSig, roundPosMask) node roundPosBit = orr(_roundPosBit_T) node _anyRoundExtra_T = and(adjustedSig, shiftedRoundMask) node anyRoundExtra = orr(_anyRoundExtra_T) node anyRound = or(roundPosBit, anyRoundExtra) node _roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _roundIncr_T_1 = and(_roundIncr_T, roundPosBit) node _roundIncr_T_2 = and(roundMagUp, anyRound) node roundIncr = or(_roundIncr_T_1, _roundIncr_T_2) node _roundedSig_T = or(adjustedSig, roundMask) node _roundedSig_T_1 = shr(_roundedSig_T, 2) node _roundedSig_T_2 = add(_roundedSig_T_1, UInt<1>(0h1)) node _roundedSig_T_3 = and(roundingMode_near_even, roundPosBit) node _roundedSig_T_4 = eq(anyRoundExtra, UInt<1>(0h0)) node _roundedSig_T_5 = and(_roundedSig_T_3, _roundedSig_T_4) node _roundedSig_T_6 = shr(roundMask, 1) node _roundedSig_T_7 = mux(_roundedSig_T_5, _roundedSig_T_6, UInt<26>(0h0)) node _roundedSig_T_8 = not(_roundedSig_T_7) node _roundedSig_T_9 = and(_roundedSig_T_2, _roundedSig_T_8) node _roundedSig_T_10 = not(roundMask) node _roundedSig_T_11 = and(adjustedSig, _roundedSig_T_10) node _roundedSig_T_12 = shr(_roundedSig_T_11, 2) node _roundedSig_T_13 = and(roundingMode_odd, anyRound) node _roundedSig_T_14 = shr(roundPosMask, 1) node _roundedSig_T_15 = mux(_roundedSig_T_13, _roundedSig_T_14, UInt<1>(0h0)) node _roundedSig_T_16 = or(_roundedSig_T_12, _roundedSig_T_15) node roundedSig = mux(roundIncr, _roundedSig_T_9, _roundedSig_T_16) node _sRoundedExp_T = shr(roundedSig, 24) node _sRoundedExp_T_1 = cvt(_sRoundedExp_T) node sRoundedExp = add(io.in.sExp, _sRoundedExp_T_1) node _common_expOut_T = bits(sRoundedExp, 8, 0) connect common_expOut, _common_expOut_T node _common_fractOut_T = bits(roundedSig, 23, 1) node _common_fractOut_T_1 = bits(roundedSig, 22, 0) node _common_fractOut_T_2 = mux(doShiftSigDown1, _common_fractOut_T, _common_fractOut_T_1) connect common_fractOut, _common_fractOut_T_2 node _common_overflow_T = shr(sRoundedExp, 7) node _common_overflow_T_1 = geq(_common_overflow_T, asSInt(UInt<3>(0h3))) connect common_overflow, _common_overflow_T_1 node _common_totalUnderflow_T = lt(sRoundedExp, asSInt(UInt<8>(0h6b))) connect common_totalUnderflow, _common_totalUnderflow_T node _unboundedRange_roundPosBit_T = bits(adjustedSig, 2, 2) node _unboundedRange_roundPosBit_T_1 = bits(adjustedSig, 1, 1) node unboundedRange_roundPosBit = mux(doShiftSigDown1, _unboundedRange_roundPosBit_T, _unboundedRange_roundPosBit_T_1) node _unboundedRange_anyRound_T = bits(adjustedSig, 2, 2) node _unboundedRange_anyRound_T_1 = and(doShiftSigDown1, _unboundedRange_anyRound_T) node _unboundedRange_anyRound_T_2 = bits(adjustedSig, 1, 0) node _unboundedRange_anyRound_T_3 = orr(_unboundedRange_anyRound_T_2) node unboundedRange_anyRound = or(_unboundedRange_anyRound_T_1, _unboundedRange_anyRound_T_3) node _unboundedRange_roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _unboundedRange_roundIncr_T_1 = and(_unboundedRange_roundIncr_T, unboundedRange_roundPosBit) node _unboundedRange_roundIncr_T_2 = and(roundMagUp, unboundedRange_anyRound) node unboundedRange_roundIncr = or(_unboundedRange_roundIncr_T_1, _unboundedRange_roundIncr_T_2) node _roundCarry_T = bits(roundedSig, 25, 25) node _roundCarry_T_1 = bits(roundedSig, 24, 24) node roundCarry = mux(doShiftSigDown1, _roundCarry_T, _roundCarry_T_1) node _common_underflow_T = shr(io.in.sExp, 8) node _common_underflow_T_1 = leq(_common_underflow_T, asSInt(UInt<1>(0h0))) node _common_underflow_T_2 = and(anyRound, _common_underflow_T_1) node _common_underflow_T_3 = bits(roundMask, 3, 3) node _common_underflow_T_4 = bits(roundMask, 2, 2) node _common_underflow_T_5 = mux(doShiftSigDown1, _common_underflow_T_3, _common_underflow_T_4) node _common_underflow_T_6 = and(_common_underflow_T_2, _common_underflow_T_5) node _common_underflow_T_7 = eq(io.detectTininess, UInt<1>(0h1)) node _common_underflow_T_8 = bits(roundMask, 4, 4) node _common_underflow_T_9 = bits(roundMask, 3, 3) node _common_underflow_T_10 = mux(doShiftSigDown1, _common_underflow_T_8, _common_underflow_T_9) node _common_underflow_T_11 = eq(_common_underflow_T_10, UInt<1>(0h0)) node _common_underflow_T_12 = and(_common_underflow_T_7, _common_underflow_T_11) node _common_underflow_T_13 = and(_common_underflow_T_12, roundCarry) node _common_underflow_T_14 = and(_common_underflow_T_13, roundPosBit) node _common_underflow_T_15 = and(_common_underflow_T_14, unboundedRange_roundIncr) node _common_underflow_T_16 = eq(_common_underflow_T_15, UInt<1>(0h0)) node _common_underflow_T_17 = and(_common_underflow_T_6, _common_underflow_T_16) node _common_underflow_T_18 = or(common_totalUnderflow, _common_underflow_T_17) connect common_underflow, _common_underflow_T_18 node _common_inexact_T = or(common_totalUnderflow, anyRound) connect common_inexact, _common_inexact_T node isNaNOut = or(io.invalidExc, io.in.isNaN) node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf) node _commonCase_T = eq(isNaNOut, UInt<1>(0h0)) node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0)) node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1) node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0)) node commonCase = and(_commonCase_T_2, _commonCase_T_3) node overflow = and(commonCase, common_overflow) node underflow = and(commonCase, common_underflow) node _inexact_T = and(commonCase, common_inexact) node inexact = or(overflow, _inexact_T) node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag) node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp) node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow) node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd) node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1) node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0)) node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T) node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp) node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T) node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign) node _expOut_T = or(io.in.isZero, common_totalUnderflow) node _expOut_T_1 = mux(_expOut_T, UInt<9>(0h1c0), UInt<1>(0h0)) node _expOut_T_2 = not(_expOut_T_1) node _expOut_T_3 = and(common_expOut, _expOut_T_2) node _expOut_T_4 = not(UInt<9>(0h6b)) node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0)) node _expOut_T_6 = not(_expOut_T_5) node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6) node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<9>(0h80), UInt<1>(0h0)) node _expOut_T_9 = not(_expOut_T_8) node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9) node _expOut_T_11 = mux(notNaN_isInfOut, UInt<9>(0h40), UInt<1>(0h0)) node _expOut_T_12 = not(_expOut_T_11) node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12) node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<9>(0h6b), UInt<1>(0h0)) node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14) node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<9>(0h17f), UInt<1>(0h0)) node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16) node _expOut_T_18 = mux(notNaN_isInfOut, UInt<9>(0h180), UInt<1>(0h0)) node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18) node _expOut_T_20 = mux(isNaNOut, UInt<9>(0h1c0), UInt<1>(0h0)) node expOut = or(_expOut_T_19, _expOut_T_20) node _fractOut_T = or(isNaNOut, io.in.isZero) node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow) node _fractOut_T_2 = mux(isNaNOut, UInt<23>(0h400000), UInt<1>(0h0)) node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut) node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<23>(0h7fffff), UInt<23>(0h0)) node fractOut = or(_fractOut_T_3, _fractOut_T_4) node _io_out_T = cat(signOut, expOut) node _io_out_T_1 = cat(_io_out_T, fractOut) connect io.out, _io_out_T_1 node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc) node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow) node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact) connect io.exceptionFlags, _io_exceptionFlags_T_3	module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_76( // @[RoundAnyRawFNToRecFN.scala:48:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19] wire [15:0] _roundMask_T_5 = 16'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_4 = 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_10 = 16'hFF00; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_13 = 12'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_14 = 16'hFF0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_15 = 16'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_20 = 16'hF0F0; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_23 = 14'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_24 = 16'h3C3C; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_25 = 16'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_30 = 16'hCCCC; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_33 = 15'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_34 = 16'h6666; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_35 = 16'h5555; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_40 = 16'hAAAA; // @[primitives.scala:77:20] wire [25:0] _roundedSig_T_15 = 26'h0; // @[RoundAnyRawFNToRecFN.scala:181:24] wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14] wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14] wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:257:18] wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:261:18] wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:269:16] wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:273:16] wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:284:13] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:90:53] wire _roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:169:38] wire _unboundedRange_roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:207:38] wire _common_underflow_T_7 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:222:49] wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:32] wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:60] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53] wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53] wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53] wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53] wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53] wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27] wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63] wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42] wire _roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:171:29] wire _roundedSig_T_13 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:181:42] wire _unboundedRange_roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:209:29] wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60] wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45] wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42] wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39] wire notNaN_isSpecialInfOut = io_in_isInf_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :236:49] wire [26:0] adjustedSig = io_in_sig_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :114:22] wire [32:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33] wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66] wire doShiftSigDown1 = adjustedSig[26]; // @[RoundAnyRawFNToRecFN.scala:114:22, :120:57] wire [8:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37] wire [8:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31] wire [22:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16] wire [22:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31] wire _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:196:50] wire common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37] wire _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:200:31] wire common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37] wire _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:217:40] wire common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37] wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49] wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37] wire [8:0] _roundMask_T = io_in_sExp_0[8:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :156:37] wire [8:0] _roundMask_T_1 = ~_roundMask_T; // @[primitives.scala:52:21] wire roundMask_msb = _roundMask_T_1[8]; // @[primitives.scala:52:21, :58:25] wire [7:0] roundMask_lsbs = _roundMask_T_1[7:0]; // @[primitives.scala:52:21, :59:26] wire roundMask_msb_1 = roundMask_lsbs[7]; // @[primitives.scala:58:25, :59:26] wire [6:0] roundMask_lsbs_1 = roundMask_lsbs[6:0]; // @[primitives.scala:59:26] wire roundMask_msb_2 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire roundMask_msb_3 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire [5:0] roundMask_lsbs_2 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [5:0] roundMask_lsbs_3 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> roundMask_lsbs_2); // @[primitives.scala:59:26, :76:56] wire [21:0] _roundMask_T_2 = roundMask_shift[63:42]; // @[primitives.scala:76:56, :78:22] wire [15:0] _roundMask_T_3 = _roundMask_T_2[15:0]; // @[primitives.scala:77:20, :78:22] wire [7:0] _roundMask_T_6 = _roundMask_T_3[15:8]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_7 = {8'h0, _roundMask_T_6}; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_8 = _roundMask_T_3[7:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_9 = {_roundMask_T_8, 8'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_11 = _roundMask_T_9 & 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_12 = _roundMask_T_7 \| _roundMask_T_11; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_16 = _roundMask_T_12[15:4]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_17 = {4'h0, _roundMask_T_16 & 12'hF0F}; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_18 = _roundMask_T_12[11:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_19 = {_roundMask_T_18, 4'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_21 = _roundMask_T_19 & 16'hF0F0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_22 = _roundMask_T_17 \| _roundMask_T_21; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_26 = _roundMask_T_22[15:2]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_27 = {2'h0, _roundMask_T_26 & 14'h3333}; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_28 = _roundMask_T_22[13:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_29 = {_roundMask_T_28, 2'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_31 = _roundMask_T_29 & 16'hCCCC; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_32 = _roundMask_T_27 \| _roundMask_T_31; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_36 = _roundMask_T_32[15:1]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_37 = {1'h0, _roundMask_T_36 & 15'h5555}; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_38 = _roundMask_T_32[14:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_39 = {_roundMask_T_38, 1'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_41 = _roundMask_T_39 & 16'hAAAA; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_42 = _roundMask_T_37 \| _roundMask_T_41; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_43 = _roundMask_T_2[21:16]; // @[primitives.scala:77:20, :78:22] wire [3:0] _roundMask_T_44 = _roundMask_T_43[3:0]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_45 = _roundMask_T_44[1:0]; // @[primitives.scala:77:20] wire _roundMask_T_46 = _roundMask_T_45[0]; // @[primitives.scala:77:20] wire _roundMask_T_47 = _roundMask_T_45[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_48 = {_roundMask_T_46, _roundMask_T_47}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_49 = _roundMask_T_44[3:2]; // @[primitives.scala:77:20] wire _roundMask_T_50 = _roundMask_T_49[0]; // @[primitives.scala:77:20] wire _roundMask_T_51 = _roundMask_T_49[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_52 = {_roundMask_T_50, _roundMask_T_51}; // @[primitives.scala:77:20] wire [3:0] _roundMask_T_53 = {_roundMask_T_48, _roundMask_T_52}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_54 = _roundMask_T_43[5:4]; // @[primitives.scala:77:20] wire _roundMask_T_55 = _roundMask_T_54[0]; // @[primitives.scala:77:20] wire _roundMask_T_56 = _roundMask_T_54[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_57 = {_roundMask_T_55, _roundMask_T_56}; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_58 = {_roundMask_T_53, _roundMask_T_57}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_59 = {_roundMask_T_42, _roundMask_T_58}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_60 = ~_roundMask_T_59; // @[primitives.scala:73:32, :77:20] wire [21:0] _roundMask_T_61 = roundMask_msb_2 ? 22'h0 : _roundMask_T_60; // @[primitives.scala:58:25, :73:{21,32}] wire [21:0] _roundMask_T_62 = ~_roundMask_T_61; // @[primitives.scala:73:{17,21}] wire [24:0] _roundMask_T_63 = {_roundMask_T_62, 3'h7}; // @[primitives.scala:68:58, :73:17] wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> roundMask_lsbs_3); // @[primitives.scala:59:26, :76:56] wire [2:0] _roundMask_T_64 = roundMask_shift_1[2:0]; // @[primitives.scala:76:56, :78:22] wire [1:0] _roundMask_T_65 = _roundMask_T_64[1:0]; // @[primitives.scala:77:20, :78:22] wire _roundMask_T_66 = _roundMask_T_65[0]; // @[primitives.scala:77:20] wire _roundMask_T_67 = _roundMask_T_65[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_68 = {_roundMask_T_66, _roundMask_T_67}; // @[primitives.scala:77:20] wire _roundMask_T_69 = _roundMask_T_64[2]; // @[primitives.scala:77:20, :78:22] wire [2:0] _roundMask_T_70 = {_roundMask_T_68, _roundMask_T_69}; // @[primitives.scala:77:20] wire [2:0] _roundMask_T_71 = roundMask_msb_3 ? _roundMask_T_70 : 3'h0; // @[primitives.scala:58:25, :62:24, :77:20] wire [24:0] _roundMask_T_72 = roundMask_msb_1 ? _roundMask_T_63 : {22'h0, _roundMask_T_71}; // @[primitives.scala:58:25, :62:24, :67:24, :68:58] wire [24:0] _roundMask_T_73 = roundMask_msb ? _roundMask_T_72 : 25'h0; // @[primitives.scala:58:25, :62:24, :67:24] wire [24:0] _roundMask_T_74 = {_roundMask_T_73[24:1], _roundMask_T_73[0] \| doShiftSigDown1}; // @[primitives.scala:62:24] wire [26:0] roundMask = {_roundMask_T_74, 2'h3}; // @[RoundAnyRawFNToRecFN.scala:159:{23,42}] wire [27:0] _shiftedRoundMask_T = {1'h0, roundMask}; // @[RoundAnyRawFNToRecFN.scala:159:42, :162:41] wire [26:0] shiftedRoundMask = _shiftedRoundMask_T[27:1]; // @[RoundAnyRawFNToRecFN.scala:162:{41,53}] wire [26:0] _roundPosMask_T = ~shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:162:53, :163:28] wire [26:0] roundPosMask = _roundPosMask_T & roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :163:{28,46}] wire [26:0] _roundPosBit_T = adjustedSig & roundPosMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :163:46, :164:40] wire roundPosBit = \|_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}] wire _roundIncr_T_1 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:67] wire _roundedSig_T_3 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :175:49] wire [26:0] _anyRoundExtra_T = adjustedSig & shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :162:53, :165:42] wire anyRoundExtra = \|_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}] wire anyRound = roundPosBit \| anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36] wire roundIncr = _roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31] wire [26:0] _roundedSig_T = adjustedSig \| roundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :159:42, :174:32] wire [24:0] _roundedSig_T_1 = _roundedSig_T[26:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}] wire [25:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 26'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}] wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30] wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30] wire [25:0] _roundedSig_T_6 = roundMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:159:42, :177:35] wire [25:0] _roundedSig_T_7 = _roundedSig_T_5 ? _roundedSig_T_6 : 26'h0; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}, :177:35] wire [25:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}] wire [25:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21] wire [26:0] _roundedSig_T_10 = ~roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :180:32] wire [26:0] _roundedSig_T_11 = adjustedSig & _roundedSig_T_10; // @[RoundAnyRawFNToRecFN.scala:114:22, :180:{30,32}] wire [24:0] _roundedSig_T_12 = _roundedSig_T_11[26:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}] wire [25:0] _roundedSig_T_14 = roundPosMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:163:46, :181:67] wire [25:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12}; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}] wire [25:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47] wire [1:0] _sRoundedExp_T = roundedSig[25:24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54] wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}] wire [10:0] sRoundedExp = {io_in_sExp_0[9], io_in_sExp_0} + {{8{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:48:5, :185:{40,76}] assign _common_expOut_T = sRoundedExp[8:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37] assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37] wire [22:0] _common_fractOut_T = roundedSig[23:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27] wire [22:0] _common_fractOut_T_1 = roundedSig[22:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27] assign _common_fractOut_T_2 = doShiftSigDown1 ? _common_fractOut_T : _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :189:16, :190:27, :191:27] assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16] wire [3:0] _common_overflow_T = sRoundedExp[10:7]; // @[RoundAnyRawFNToRecFN.scala:185:40, :196:30] assign _common_overflow_T_1 = $signed(_common_overflow_T) > 4'sh2; // @[RoundAnyRawFNToRecFN.scala:196:{30,50}] assign common_overflow = _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:124:37, :196:50] assign _common_totalUnderflow_T = $signed(sRoundedExp) < 11'sh6B; // @[RoundAnyRawFNToRecFN.scala:185:40, :200:31] assign common_totalUnderflow = _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:125:37, :200:31] wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45] wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45, :205:44] wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:61] wire unboundedRange_roundPosBit = doShiftSigDown1 ? _unboundedRange_roundPosBit_T : _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :203:{16,45,61}] wire _unboundedRange_roundIncr_T_1 = unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:67] wire _unboundedRange_anyRound_T_1 = doShiftSigDown1 & _unboundedRange_anyRound_T; // @[RoundAnyRawFNToRecFN.scala:120:57, :205:{30,44}] wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:114:22, :205:63] wire _unboundedRange_anyRound_T_3 = \|_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}] wire unboundedRange_anyRound = _unboundedRange_anyRound_T_1 \| _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{30,49,70}] wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46] wire _roundCarry_T = roundedSig[25]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27] wire _roundCarry_T_1 = roundedSig[24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27] wire roundCarry = doShiftSigDown1 ? _roundCarry_T : _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :211:16, :212:27, :213:27] wire [1:0] _common_underflow_T = io_in_sExp_0[9:8]; // @[RoundAnyRawFNToRecFN.scala:48:5, :220:49] wire _common_underflow_T_1 = _common_underflow_T != 2'h1; // @[RoundAnyRawFNToRecFN.scala:220:{49,64}] wire _common_underflow_T_2 = anyRound & _common_underflow_T_1; // @[RoundAnyRawFNToRecFN.scala:166:36, :220:{32,64}] wire _common_underflow_T_3 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57] wire _common_underflow_T_9 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57, :225:49] wire _common_underflow_T_4 = roundMask[2]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:71] wire _common_underflow_T_5 = doShiftSigDown1 ? _common_underflow_T_3 : _common_underflow_T_4; // @[RoundAnyRawFNToRecFN.scala:120:57, :221:{30,57,71}] wire _common_underflow_T_6 = _common_underflow_T_2 & _common_underflow_T_5; // @[RoundAnyRawFNToRecFN.scala:220:{32,72}, :221:30] wire _common_underflow_T_8 = roundMask[4]; // @[RoundAnyRawFNToRecFN.scala:159:42, :224:49] wire _common_underflow_T_10 = doShiftSigDown1 ? _common_underflow_T_8 : _common_underflow_T_9; // @[RoundAnyRawFNToRecFN.scala:120:57, :223:39, :224:49, :225:49] wire _common_underflow_T_11 = ~_common_underflow_T_10; // @[RoundAnyRawFNToRecFN.scala:223:{34,39}] wire _common_underflow_T_12 = _common_underflow_T_11; // @[RoundAnyRawFNToRecFN.scala:222:77, :223:34] wire _common_underflow_T_13 = _common_underflow_T_12 & roundCarry; // @[RoundAnyRawFNToRecFN.scala:211:16, :222:77, :226:38] wire _common_underflow_T_14 = _common_underflow_T_13 & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :226:38, :227:45] wire _common_underflow_T_15 = _common_underflow_T_14 & unboundedRange_roundIncr; // @[RoundAnyRawFNToRecFN.scala:208:46, :227:{45,60}] wire _common_underflow_T_16 = ~_common_underflow_T_15; // @[RoundAnyRawFNToRecFN.scala:222:27, :227:60] wire _common_underflow_T_17 = _common_underflow_T_6 & _common_underflow_T_16; // @[RoundAnyRawFNToRecFN.scala:220:72, :221:76, :222:27] assign _common_underflow_T_18 = common_totalUnderflow \| _common_underflow_T_17; // @[RoundAnyRawFNToRecFN.scala:125:37, :217:40, :221:76] assign common_underflow = _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:126:37, :217:40] assign _common_inexact_T = common_totalUnderflow \| anyRound; // @[RoundAnyRawFNToRecFN.scala:125:37, :166:36, :230:49] assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49] wire isNaNOut = io_invalidExc_0 \| io_in_isNaN_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34] wire _commonCase_T = ~isNaNOut; // @[RoundAnyRawFNToRecFN.scala:235:34, :237:22] wire _commonCase_T_1 = ~notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :237:36] wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1; // @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}] wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64] wire commonCase = _commonCase_T_2 & _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}] wire overflow = commonCase & common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32] wire _notNaN_isInfOut_T = overflow; // @[RoundAnyRawFNToRecFN.scala:238:32, :248:45] wire underflow = commonCase & common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37, :237:61, :239:32] wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43] wire inexact = overflow \| _inexact_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}] wire _pegMinNonzeroMagOut_T = commonCase & common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :237:61, :245:20] wire notNaN_isInfOut = notNaN_isSpecialInfOut \| _notNaN_isInfOut_T; // @[RoundAnyRawFNToRecFN.scala:236:49, :248:{32,45}] wire signOut = ~isNaNOut & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22] wire _expOut_T = io_in_isZero_0 \| common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:48:5, :125:37, :253:32] wire [8:0] _expOut_T_1 = _expOut_T ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}] wire [8:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}] wire [8:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14] wire [8:0] _expOut_T_7 = _expOut_T_3; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17] wire [8:0] _expOut_T_10 = _expOut_T_7; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17] wire [8:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 6'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18] wire [8:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}] wire [8:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14] wire [8:0] _expOut_T_15 = _expOut_T_13; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18] wire [8:0] _expOut_T_17 = _expOut_T_15; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15] wire [8:0] _expOut_T_18 = notNaN_isInfOut ? 9'h180 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16] wire [8:0] _expOut_T_19 = _expOut_T_17 \| _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16] wire [8:0] _expOut_T_20 = isNaNOut ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:235:34, :278:16] wire [8:0] expOut = _expOut_T_19 \| _expOut_T_20; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16] wire _fractOut_T = isNaNOut \| io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22] wire _fractOut_T_1 = _fractOut_T \| common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :280:{22,38}] wire [22:0] _fractOut_T_2 = {isNaNOut, 22'h0}; // @[RoundAnyRawFNToRecFN.scala:235:34, :281:16] wire [22:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16] wire [22:0] fractOut = _fractOut_T_3; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11] wire [9:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23] assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}] assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33] wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, 1'h0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:23] wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, overflow}; // @[RoundAnyRawFNToRecFN.scala:238:32, :288:{23,41}] wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, underflow}; // @[RoundAnyRawFNToRecFN.scala:239:32, :288:{41,53}] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}] assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module FPUFMAPipe_l4_f64_1 : input clock : Clock input reset : Reset output io : { flip in : { valid : UInt<1>, bits : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, out : { valid : UInt<1>, bits : { data : UInt<65>, exc : UInt<5>}}} reg valid : UInt<1>, clock connect valid, io.in.valid reg in : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clock when io.in.valid : node one = shl(UInt<1>(0h1), 63) node _zero_T = xor(io.in.bits.in1, io.in.bits.in2) node _zero_T_1 = shl(UInt<1>(0h1), 64) node zero = and(_zero_T, _zero_T_1) connect in, io.in.bits when io.in.bits.swap23 : connect in.in2, one node _T = or(io.in.bits.ren3, io.in.bits.swap23) node _T_1 = eq(_T, UInt<1>(0h0)) when _T_1 : connect in.in3, zero inst fma of MulAddRecFNPipe_l2_e11_s53_1 connect fma.clock, clock connect fma.reset, reset connect fma.io.validin, valid connect fma.io.op, in.fmaCmd connect fma.io.roundingMode, in.rm connect fma.io.detectTininess, UInt<1>(0h1) connect fma.io.a, in.in1 connect fma.io.b, in.in2 connect fma.io.c, in.in3 wire res : { data : UInt<65>, exc : UInt<5>} node _res_data_maskedNaN_T = not(UInt<65>(0h1010000000000000)) node res_data_maskedNaN = and(fma.io.out, _res_data_maskedNaN_T) node _res_data_T = bits(fma.io.out, 63, 61) node _res_data_T_1 = andr(_res_data_T) node _res_data_T_2 = mux(_res_data_T_1, res_data_maskedNaN, fma.io.out) connect res.data, _res_data_T_2 connect res.exc, fma.io.exceptionFlags regreset io_out_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect io_out_pipe_v, fma.io.validout reg io_out_pipe_b : { data : UInt<65>, exc : UInt<5>}, clock when fma.io.validout : connect io_out_pipe_b, res wire io_out_pipe_out : { valid : UInt<1>, bits : { data : UInt<65>, exc : UInt<5>}} connect io_out_pipe_out.valid, io_out_pipe_v connect io_out_pipe_out.bits, io_out_pipe_b connect io.out, io_out_pipe_out	module FPUFMAPipe_l4_f64_1( // @[FPU.scala:697:7] input clock, // @[FPU.scala:697:7] input reset, // @[FPU.scala:697:7] input io_in_valid, // @[FPU.scala:702:14] input io_in_bits_ldst, // @[FPU.scala:702:14] input io_in_bits_wen, // @[FPU.scala:702:14] input io_in_bits_ren1, // @[FPU.scala:702:14] input io_in_bits_ren2, // @[FPU.scala:702:14] input io_in_bits_ren3, // @[FPU.scala:702:14] input io_in_bits_swap12, // @[FPU.scala:702:14] input io_in_bits_swap23, // @[FPU.scala:702:14] input [1:0] io_in_bits_typeTagIn, // @[FPU.scala:702:14] input [1:0] io_in_bits_typeTagOut, // @[FPU.scala:702:14] input io_in_bits_fromint, // @[FPU.scala:702:14] input io_in_bits_toint, // @[FPU.scala:702:14] input io_in_bits_fastpipe, // @[FPU.scala:702:14] input io_in_bits_fma, // @[FPU.scala:702:14] input io_in_bits_div, // @[FPU.scala:702:14] input io_in_bits_sqrt, // @[FPU.scala:702:14] input io_in_bits_wflags, // @[FPU.scala:702:14] input [2:0] io_in_bits_rm, // @[FPU.scala:702:14] input [1:0] io_in_bits_fmaCmd, // @[FPU.scala:702:14] input [1:0] io_in_bits_typ, // @[FPU.scala:702:14] input [1:0] io_in_bits_fmt, // @[FPU.scala:702:14] input [64:0] io_in_bits_in1, // @[FPU.scala:702:14] input [64:0] io_in_bits_in2, // @[FPU.scala:702:14] input [64:0] io_in_bits_in3, // @[FPU.scala:702:14] output io_out_valid, // @[FPU.scala:702:14] output [64:0] io_out_bits_data, // @[FPU.scala:702:14] output [4:0] io_out_bits_exc // @[FPU.scala:702:14] ); wire [64:0] _fma_io_out; // @[FPU.scala:719:19] wire _fma_io_validout; // @[FPU.scala:719:19] wire io_in_valid_0 = io_in_valid; // @[FPU.scala:697:7] wire io_in_bits_ldst_0 = io_in_bits_ldst; // @[FPU.scala:697:7] wire io_in_bits_wen_0 = io_in_bits_wen; // @[FPU.scala:697:7] wire io_in_bits_ren1_0 = io_in_bits_ren1; // @[FPU.scala:697:7] wire io_in_bits_ren2_0 = io_in_bits_ren2; // @[FPU.scala:697:7] wire io_in_bits_ren3_0 = io_in_bits_ren3; // @[FPU.scala:697:7] wire io_in_bits_swap12_0 = io_in_bits_swap12; // @[FPU.scala:697:7] wire io_in_bits_swap23_0 = io_in_bits_swap23; // @[FPU.scala:697:7] wire [1:0] io_in_bits_typeTagIn_0 = io_in_bits_typeTagIn; // @[FPU.scala:697:7] wire [1:0] io_in_bits_typeTagOut_0 = io_in_bits_typeTagOut; // @[FPU.scala:697:7] wire io_in_bits_fromint_0 = io_in_bits_fromint; // @[FPU.scala:697:7] wire io_in_bits_toint_0 = io_in_bits_toint; // @[FPU.scala:697:7] wire io_in_bits_fastpipe_0 = io_in_bits_fastpipe; // @[FPU.scala:697:7] wire io_in_bits_fma_0 = io_in_bits_fma; // @[FPU.scala:697:7] wire io_in_bits_div_0 = io_in_bits_div; // @[FPU.scala:697:7] wire io_in_bits_sqrt_0 = io_in_bits_sqrt; // @[FPU.scala:697:7] wire io_in_bits_wflags_0 = io_in_bits_wflags; // @[FPU.scala:697:7] wire [2:0] io_in_bits_rm_0 = io_in_bits_rm; // @[FPU.scala:697:7] wire [1:0] io_in_bits_fmaCmd_0 = io_in_bits_fmaCmd; // @[FPU.scala:697:7] wire [1:0] io_in_bits_typ_0 = io_in_bits_typ; // @[FPU.scala:697:7] wire [1:0] io_in_bits_fmt_0 = io_in_bits_fmt; // @[FPU.scala:697:7] wire [64:0] io_in_bits_in1_0 = io_in_bits_in1; // @[FPU.scala:697:7] wire [64:0] io_in_bits_in2_0 = io_in_bits_in2; // @[FPU.scala:697:7] wire [64:0] io_in_bits_in3_0 = io_in_bits_in3; // @[FPU.scala:697:7] wire [63:0] one = 64'h8000000000000000; // @[FPU.scala:710:19] wire [64:0] _zero_T_1 = 65'h10000000000000000; // @[FPU.scala:711:57] wire [64:0] _res_data_maskedNaN_T = 65'h1EFEFFFFFFFFFFFFF; // @[FPU.scala:413:27] wire io_in_bits_vec = 1'h0; // @[FPU.scala:697:7] wire io_out_pipe_out_valid; // @[Valid.scala:135:21] wire [64:0] io_out_pipe_out_bits_data; // @[Valid.scala:135:21] wire [4:0] io_out_pipe_out_bits_exc; // @[Valid.scala:135:21] wire [64:0] io_out_bits_data_0; // @[FPU.scala:697:7] wire [4:0] io_out_bits_exc_0; // @[FPU.scala:697:7] wire io_out_valid_0; // @[FPU.scala:697:7] reg valid; // @[FPU.scala:707:22] reg in_ldst; // @[FPU.scala:708:15] reg in_wen; // @[FPU.scala:708:15] reg in_ren1; // @[FPU.scala:708:15] reg in_ren2; // @[FPU.scala:708:15] reg in_ren3; // @[FPU.scala:708:15] reg in_swap12; // @[FPU.scala:708:15] reg in_swap23; // @[FPU.scala:708:15] reg [1:0] in_typeTagIn; // @[FPU.scala:708:15] reg [1:0] in_typeTagOut; // @[FPU.scala:708:15] reg in_fromint; // @[FPU.scala:708:15] reg in_toint; // @[FPU.scala:708:15] reg in_fastpipe; // @[FPU.scala:708:15] reg in_fma; // @[FPU.scala:708:15] reg in_div; // @[FPU.scala:708:15] reg in_sqrt; // @[FPU.scala:708:15] reg in_wflags; // @[FPU.scala:708:15] reg [2:0] in_rm; // @[FPU.scala:708:15] reg [1:0] in_fmaCmd; // @[FPU.scala:708:15] reg [1:0] in_typ; // @[FPU.scala:708:15] reg [1:0] in_fmt; // @[FPU.scala:708:15] reg [64:0] in_in1; // @[FPU.scala:708:15] reg [64:0] in_in2; // @[FPU.scala:708:15] reg [64:0] in_in3; // @[FPU.scala:708:15] wire [64:0] _zero_T = io_in_bits_in1_0 ^ io_in_bits_in2_0; // @[FPU.scala:697:7, :711:32] wire [64:0] zero = _zero_T & 65'h10000000000000000; // @[FPU.scala:711:{32,50}] wire [64:0] _res_data_T_2; // @[FPU.scala:414:10] wire [64:0] res_data; // @[FPU.scala:728:17] wire [4:0] res_exc; // @[FPU.scala:728:17] wire [64:0] res_data_maskedNaN = _fma_io_out & 65'h1EFEFFFFFFFFFFFFF; // @[FPU.scala:413:25, :719:19] wire [2:0] _res_data_T = _fma_io_out[63:61]; // @[FPU.scala:249:25, :719:19] wire _res_data_T_1 = &_res_data_T; // @[FPU.scala:249:{25,56}] assign _res_data_T_2 = _res_data_T_1 ? res_data_maskedNaN : _fma_io_out; // @[FPU.scala:249:56, :413:25, :414:10, :719:19] assign res_data = _res_data_T_2; // @[FPU.scala:414:10, :728:17] reg io_out_pipe_v; // @[Valid.scala:141:24] assign io_out_pipe_out_valid = io_out_pipe_v; // @[Valid.scala:135:21, :141:24] reg [64:0] io_out_pipe_b_data; // @[Valid.scala:142:26] assign io_out_pipe_out_bits_data = io_out_pipe_b_data; // @[Valid.scala:135:21, :142:26] reg [4:0] io_out_pipe_b_exc; // @[Valid.scala:142:26] assign io_out_pipe_out_bits_exc = io_out_pipe_b_exc; // @[Valid.scala:135:21, :142:26] assign io_out_valid_0 = io_out_pipe_out_valid; // @[Valid.scala:135:21] assign io_out_bits_data_0 = io_out_pipe_out_bits_data; // @[Valid.scala:135:21] assign io_out_bits_exc_0 = io_out_pipe_out_bits_exc; // @[Valid.scala:135:21] always @(posedge clock) begin // @[FPU.scala:697:7] valid <= io_in_valid_0; // @[FPU.scala:697:7, :707:22] if (io_in_valid_0) begin // @[FPU.scala:697:7] in_ldst <= io_in_bits_ldst_0; // @[FPU.scala:697:7, :708:15] in_wen <= io_in_bits_wen_0; // @[FPU.scala:697:7, :708:15] in_ren1 <= io_in_bits_ren1_0; // @[FPU.scala:697:7, :708:15] in_ren2 <= io_in_bits_ren2_0; // @[FPU.scala:697:7, :708:15] in_ren3 <= io_in_bits_ren3_0; // @[FPU.scala:697:7, :708:15] in_swap12 <= io_in_bits_swap12_0; // @[FPU.scala:697:7, :708:15] in_swap23 <= io_in_bits_swap23_0; // @[FPU.scala:697:7, :708:15] in_typeTagIn <= io_in_bits_typeTagIn_0; // @[FPU.scala:697:7, :708:15] in_typeTagOut <= io_in_bits_typeTagOut_0; // @[FPU.scala:697:7, :708:15] in_fromint <= io_in_bits_fromint_0; // @[FPU.scala:697:7, :708:15] in_toint <= io_in_bits_toint_0; // @[FPU.scala:697:7, :708:15] in_fastpipe <= io_in_bits_fastpipe_0; // @[FPU.scala:697:7, :708:15] in_fma <= io_in_bits_fma_0; // @[FPU.scala:697:7, :708:15] in_div <= io_in_bits_div_0; // @[FPU.scala:697:7, :708:15] in_sqrt <= io_in_bits_sqrt_0; // @[FPU.scala:697:7, :708:15] in_wflags <= io_in_bits_wflags_0; // @[FPU.scala:697:7, :708:15] in_rm <= io_in_bits_rm_0; // @[FPU.scala:697:7, :708:15] in_fmaCmd <= io_in_bits_fmaCmd_0; // @[FPU.scala:697:7, :708:15] in_typ <= io_in_bits_typ_0; // @[FPU.scala:697:7, :708:15] in_fmt <= io_in_bits_fmt_0; // @[FPU.scala:697:7, :708:15] in_in1 <= io_in_bits_in1_0; // @[FPU.scala:697:7, :708:15] in_in2 <= io_in_bits_swap23_0 ? 65'h8000000000000000 : io_in_bits_in2_0; // @[FPU.scala:697:7, :708:15, :714:8, :715:{23,32}] in_in3 <= io_in_bits_ren3_0 \| io_in_bits_swap23_0 ? io_in_bits_in3_0 : zero; // @[FPU.scala:697:7, :708:15, :711:50, :714:8, :716:{21,37,46}] end if (_fma_io_validout) begin // @[FPU.scala:719:19] io_out_pipe_b_data <= res_data; // @[Valid.scala:142:26] io_out_pipe_b_exc <= res_exc; // @[Valid.scala:142:26] end if (reset) // @[FPU.scala:697:7] io_out_pipe_v <= 1'h0; // @[Valid.scala:141:24] else // @[FPU.scala:697:7] io_out_pipe_v <= _fma_io_validout; // @[Valid.scala:141:24] always @(posedge) MulAddRecFNPipe_l2_e11_s53_1 fma ( // @[FPU.scala:719:19] .clock (clock), .reset (reset), .io_validin (valid), // @[FPU.scala:707:22] .io_op (in_fmaCmd), // @[FPU.scala:708:15] .io_a (in_in1), // @[FPU.scala:708:15] .io_b (in_in2), // @[FPU.scala:708:15] .io_c (in_in3), // @[FPU.scala:708:15] .io_roundingMode (in_rm), // @[FPU.scala:708:15] .io_out (_fma_io_out), .io_exceptionFlags (res_exc), .io_validout (_fma_io_validout) ); // @[FPU.scala:719:19] assign io_out_valid = io_out_valid_0; // @[FPU.scala:697:7] assign io_out_bits_data = io_out_bits_data_0; // @[FPU.scala:697:7] assign io_out_bits_exc = io_out_bits_exc_0; // @[FPU.scala:697:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_19 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE : UInt<1>[8] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 node _source_ok_T_28 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_29 = or(_source_ok_T_28, _source_ok_WIRE[2]) node _source_ok_T_30 = or(_source_ok_T_29, _source_ok_WIRE[3]) node _source_ok_T_31 = or(_source_ok_T_30, _source_ok_WIRE[4]) node _source_ok_T_32 = or(_source_ok_T_31, _source_ok_WIRE[5]) node _source_ok_T_33 = or(_source_ok_T_32, _source_ok_WIRE[6]) node source_ok = or(_source_ok_T_33, _source_ok_WIRE[7]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _T_88 = and(_T_11, _T_24) node _T_89 = and(_T_88, _T_37) node _T_90 = and(_T_89, _T_50) node _T_91 = and(_T_90, _T_63) node _T_92 = and(_T_91, _T_71) node _T_93 = and(_T_92, _T_79) node _T_94 = and(_T_93, _T_87) node _T_95 = asUInt(reset) node _T_96 = eq(_T_95, UInt<1>(0h0)) when _T_96 : node _T_97 = eq(_T_94, UInt<1>(0h0)) when _T_97 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_94, UInt<1>(0h1), "") : assert_1 node _T_98 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_98 : node _T_99 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_100 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_101 = and(_T_99, _T_100) node _T_102 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_103 = shr(io.in.a.bits.source, 2) node _T_104 = eq(_T_103, UInt<1>(0h0)) node _T_105 = leq(UInt<1>(0h0), uncommonBits_4) node _T_106 = and(_T_104, _T_105) node _T_107 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_108 = and(_T_106, _T_107) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_109 = shr(io.in.a.bits.source, 2) node _T_110 = eq(_T_109, UInt<1>(0h1)) node _T_111 = leq(UInt<1>(0h0), uncommonBits_5) node _T_112 = and(_T_110, _T_111) node _T_113 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_114 = and(_T_112, _T_113) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_115 = shr(io.in.a.bits.source, 2) node _T_116 = eq(_T_115, UInt<2>(0h2)) node _T_117 = leq(UInt<1>(0h0), uncommonBits_6) node _T_118 = and(_T_116, _T_117) node _T_119 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_120 = and(_T_118, _T_119) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_121 = shr(io.in.a.bits.source, 2) node _T_122 = eq(_T_121, UInt<2>(0h3)) node _T_123 = leq(UInt<1>(0h0), uncommonBits_7) node _T_124 = and(_T_122, _T_123) node _T_125 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_126 = and(_T_124, _T_125) node _T_127 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_128 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_129 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_130 = or(_T_102, _T_108) node _T_131 = or(_T_130, _T_114) node _T_132 = or(_T_131, _T_120) node _T_133 = or(_T_132, _T_126) node _T_134 = or(_T_133, _T_127) node _T_135 = or(_T_134, _T_128) node _T_136 = or(_T_135, _T_129) node _T_137 = and(_T_101, _T_136) node _T_138 = or(UInt<1>(0h0), _T_137) node _T_139 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_140 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_141 = cvt(_T_140) node _T_142 = and(_T_141, asSInt(UInt<14>(0h2000))) node _T_143 = asSInt(_T_142) node _T_144 = eq(_T_143, asSInt(UInt<1>(0h0))) node _T_145 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_146 = cvt(_T_145) node _T_147 = and(_T_146, asSInt(UInt<13>(0h1000))) node _T_148 = asSInt(_T_147) node _T_149 = eq(_T_148, asSInt(UInt<1>(0h0))) node _T_150 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_151 = cvt(_T_150) node _T_152 = and(_T_151, asSInt(UInt<17>(0h10000))) node _T_153 = asSInt(_T_152) node _T_154 = eq(_T_153, asSInt(UInt<1>(0h0))) node _T_155 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_156 = cvt(_T_155) node _T_157 = and(_T_156, asSInt(UInt<18>(0h2f000))) node _T_158 = asSInt(_T_157) node _T_159 = eq(_T_158, asSInt(UInt<1>(0h0))) node _T_160 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_161 = cvt(_T_160) node _T_162 = and(_T_161, asSInt(UInt<17>(0h10000))) node _T_163 = asSInt(_T_162) node _T_164 = eq(_T_163, asSInt(UInt<1>(0h0))) node _T_165 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_166 = cvt(_T_165) node _T_167 = and(_T_166, asSInt(UInt<27>(0h4000000))) node _T_168 = asSInt(_T_167) node _T_169 = eq(_T_168, asSInt(UInt<1>(0h0))) node _T_170 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_171 = cvt(_T_170) node _T_172 = and(_T_171, asSInt(UInt<13>(0h1000))) node _T_173 = asSInt(_T_172) node _T_174 = eq(_T_173, asSInt(UInt<1>(0h0))) node _T_175 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_176 = cvt(_T_175) node _T_177 = and(_T_176, asSInt(UInt<19>(0h40000))) node _T_178 = asSInt(_T_177) node _T_179 = eq(_T_178, asSInt(UInt<1>(0h0))) node _T_180 = or(_T_144, _T_149) node _T_181 = or(_T_180, _T_154) node _T_182 = or(_T_181, _T_159) node _T_183 = or(_T_182, _T_164) node _T_184 = or(_T_183, _T_169) node _T_185 = or(_T_184, _T_174) node _T_186 = or(_T_185, _T_179) node _T_187 = and(_T_139, _T_186) node _T_188 = or(UInt<1>(0h0), _T_187) node _T_189 = and(_T_138, _T_188) node _T_190 = asUInt(reset) node _T_191 = eq(_T_190, UInt<1>(0h0)) when _T_191 : node _T_192 = eq(_T_189, UInt<1>(0h0)) when _T_192 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_189, UInt<1>(0h1), "") : assert_2 node _T_193 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_194 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_195 = and(_T_193, _T_194) node _T_196 = or(UInt<1>(0h0), _T_195) node _T_197 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_198 = cvt(_T_197) node _T_199 = and(_T_198, asSInt(UInt<14>(0h2000))) node _T_200 = asSInt(_T_199) node _T_201 = eq(_T_200, asSInt(UInt<1>(0h0))) node _T_202 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_203 = cvt(_T_202) node _T_204 = and(_T_203, asSInt(UInt<13>(0h1000))) node _T_205 = asSInt(_T_204) node _T_206 = eq(_T_205, asSInt(UInt<1>(0h0))) node _T_207 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_208 = cvt(_T_207) node _T_209 = and(_T_208, asSInt(UInt<17>(0h10000))) node _T_210 = asSInt(_T_209) node _T_211 = eq(_T_210, asSInt(UInt<1>(0h0))) node _T_212 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_213 = cvt(_T_212) node _T_214 = and(_T_213, asSInt(UInt<18>(0h2f000))) node _T_215 = asSInt(_T_214) node _T_216 = eq(_T_215, asSInt(UInt<1>(0h0))) node _T_217 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_218 = cvt(_T_217) node _T_219 = and(_T_218, asSInt(UInt<17>(0h10000))) node _T_220 = asSInt(_T_219) node _T_221 = eq(_T_220, asSInt(UInt<1>(0h0))) node _T_222 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_223 = cvt(_T_222) node _T_224 = and(_T_223, asSInt(UInt<27>(0h4000000))) node _T_225 = asSInt(_T_224) node _T_226 = eq(_T_225, asSInt(UInt<1>(0h0))) node _T_227 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_228 = cvt(_T_227) node _T_229 = and(_T_228, asSInt(UInt<13>(0h1000))) node _T_230 = asSInt(_T_229) node _T_231 = eq(_T_230, asSInt(UInt<1>(0h0))) node _T_232 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_233 = cvt(_T_232) node _T_234 = and(_T_233, asSInt(UInt<19>(0h40000))) node _T_235 = asSInt(_T_234) node _T_236 = eq(_T_235, asSInt(UInt<1>(0h0))) node _T_237 = or(_T_201, _T_206) node _T_238 = or(_T_237, _T_211) node _T_239 = or(_T_238, _T_216) node _T_240 = or(_T_239, _T_221) node _T_241 = or(_T_240, _T_226) node _T_242 = or(_T_241, _T_231) node _T_243 = or(_T_242, _T_236) node _T_244 = and(_T_196, _T_243) node _T_245 = or(UInt<1>(0h0), _T_244) node _T_246 = and(UInt<1>(0h0), _T_245) node _T_247 = asUInt(reset) node _T_248 = eq(_T_247, UInt<1>(0h0)) when _T_248 : node _T_249 = eq(_T_246, UInt<1>(0h0)) when _T_249 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_246, UInt<1>(0h1), "") : assert_3 node _T_250 = asUInt(reset) node _T_251 = eq(_T_250, UInt<1>(0h0)) when _T_251 : node _T_252 = eq(source_ok, UInt<1>(0h0)) when _T_252 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_253 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_254 = asUInt(reset) node _T_255 = eq(_T_254, UInt<1>(0h0)) when _T_255 : node _T_256 = eq(_T_253, UInt<1>(0h0)) when _T_256 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_253, UInt<1>(0h1), "") : assert_5 node _T_257 = asUInt(reset) node _T_258 = eq(_T_257, UInt<1>(0h0)) when _T_258 : node _T_259 = eq(is_aligned, UInt<1>(0h0)) when _T_259 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_260 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_261 = asUInt(reset) node _T_262 = eq(_T_261, UInt<1>(0h0)) when _T_262 : node _T_263 = eq(_T_260, UInt<1>(0h0)) when _T_263 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_260, UInt<1>(0h1), "") : assert_7 node _T_264 = not(io.in.a.bits.mask) node _T_265 = eq(_T_264, UInt<1>(0h0)) node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(_T_265, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_265, UInt<1>(0h1), "") : assert_8 node _T_269 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_269, UInt<1>(0h1), "") : assert_9 node _T_273 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_273 : node _T_274 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_275 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_276 = and(_T_274, _T_275) node _T_277 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_278 = shr(io.in.a.bits.source, 2) node _T_279 = eq(_T_278, UInt<1>(0h0)) node _T_280 = leq(UInt<1>(0h0), uncommonBits_8) node _T_281 = and(_T_279, _T_280) node _T_282 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_283 = and(_T_281, _T_282) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_284 = shr(io.in.a.bits.source, 2) node _T_285 = eq(_T_284, UInt<1>(0h1)) node _T_286 = leq(UInt<1>(0h0), uncommonBits_9) node _T_287 = and(_T_285, _T_286) node _T_288 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_289 = and(_T_287, _T_288) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_290 = shr(io.in.a.bits.source, 2) node _T_291 = eq(_T_290, UInt<2>(0h2)) node _T_292 = leq(UInt<1>(0h0), uncommonBits_10) node _T_293 = and(_T_291, _T_292) node _T_294 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_295 = and(_T_293, _T_294) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_296 = shr(io.in.a.bits.source, 2) node _T_297 = eq(_T_296, UInt<2>(0h3)) node _T_298 = leq(UInt<1>(0h0), uncommonBits_11) node _T_299 = and(_T_297, _T_298) node _T_300 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_301 = and(_T_299, _T_300) node _T_302 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_303 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_304 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_305 = or(_T_277, _T_283) node _T_306 = or(_T_305, _T_289) node _T_307 = or(_T_306, _T_295) node _T_308 = or(_T_307, _T_301) node _T_309 = or(_T_308, _T_302) node _T_310 = or(_T_309, _T_303) node _T_311 = or(_T_310, _T_304) node _T_312 = and(_T_276, _T_311) node _T_313 = or(UInt<1>(0h0), _T_312) node _T_314 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_315 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_316 = cvt(_T_315) node _T_317 = and(_T_316, asSInt(UInt<14>(0h2000))) node _T_318 = asSInt(_T_317) node _T_319 = eq(_T_318, asSInt(UInt<1>(0h0))) node _T_320 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_321 = cvt(_T_320) node _T_322 = and(_T_321, asSInt(UInt<13>(0h1000))) node _T_323 = asSInt(_T_322) node _T_324 = eq(_T_323, asSInt(UInt<1>(0h0))) node _T_325 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_326 = cvt(_T_325) node _T_327 = and(_T_326, asSInt(UInt<17>(0h10000))) node _T_328 = asSInt(_T_327) node _T_329 = eq(_T_328, asSInt(UInt<1>(0h0))) node _T_330 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<18>(0h2f000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_336 = cvt(_T_335) node _T_337 = and(_T_336, asSInt(UInt<17>(0h10000))) node _T_338 = asSInt(_T_337) node _T_339 = eq(_T_338, asSInt(UInt<1>(0h0))) node _T_340 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_341 = cvt(_T_340) node _T_342 = and(_T_341, asSInt(UInt<27>(0h4000000))) node _T_343 = asSInt(_T_342) node _T_344 = eq(_T_343, asSInt(UInt<1>(0h0))) node _T_345 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_346 = cvt(_T_345) node _T_347 = and(_T_346, asSInt(UInt<13>(0h1000))) node _T_348 = asSInt(_T_347) node _T_349 = eq(_T_348, asSInt(UInt<1>(0h0))) node _T_350 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_351 = cvt(_T_350) node _T_352 = and(_T_351, asSInt(UInt<19>(0h40000))) node _T_353 = asSInt(_T_352) node _T_354 = eq(_T_353, asSInt(UInt<1>(0h0))) node _T_355 = or(_T_319, _T_324) node _T_356 = or(_T_355, _T_329) node _T_357 = or(_T_356, _T_334) node _T_358 = or(_T_357, _T_339) node _T_359 = or(_T_358, _T_344) node _T_360 = or(_T_359, _T_349) node _T_361 = or(_T_360, _T_354) node _T_362 = and(_T_314, _T_361) node _T_363 = or(UInt<1>(0h0), _T_362) node _T_364 = and(_T_313, _T_363) node _T_365 = asUInt(reset) node _T_366 = eq(_T_365, UInt<1>(0h0)) when _T_366 : node _T_367 = eq(_T_364, UInt<1>(0h0)) when _T_367 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_364, UInt<1>(0h1), "") : assert_10 node _T_368 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_369 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_370 = and(_T_368, _T_369) node _T_371 = or(UInt<1>(0h0), _T_370) node _T_372 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_373 = cvt(_T_372) node _T_374 = and(_T_373, asSInt(UInt<14>(0h2000))) node _T_375 = asSInt(_T_374) node _T_376 = eq(_T_375, asSInt(UInt<1>(0h0))) node _T_377 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_378 = cvt(_T_377) node _T_379 = and(_T_378, asSInt(UInt<13>(0h1000))) node _T_380 = asSInt(_T_379) node _T_381 = eq(_T_380, asSInt(UInt<1>(0h0))) node _T_382 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_383 = cvt(_T_382) node _T_384 = and(_T_383, asSInt(UInt<17>(0h10000))) node _T_385 = asSInt(_T_384) node _T_386 = eq(_T_385, asSInt(UInt<1>(0h0))) node _T_387 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_388 = cvt(_T_387) node _T_389 = and(_T_388, asSInt(UInt<18>(0h2f000))) node _T_390 = asSInt(_T_389) node _T_391 = eq(_T_390, asSInt(UInt<1>(0h0))) node _T_392 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_393 = cvt(_T_392) node _T_394 = and(_T_393, asSInt(UInt<17>(0h10000))) node _T_395 = asSInt(_T_394) node _T_396 = eq(_T_395, asSInt(UInt<1>(0h0))) node _T_397 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_398 = cvt(_T_397) node _T_399 = and(_T_398, asSInt(UInt<27>(0h4000000))) node _T_400 = asSInt(_T_399) node _T_401 = eq(_T_400, asSInt(UInt<1>(0h0))) node _T_402 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_403 = cvt(_T_402) node _T_404 = and(_T_403, asSInt(UInt<13>(0h1000))) node _T_405 = asSInt(_T_404) node _T_406 = eq(_T_405, asSInt(UInt<1>(0h0))) node _T_407 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_408 = cvt(_T_407) node _T_409 = and(_T_408, asSInt(UInt<19>(0h40000))) node _T_410 = asSInt(_T_409) node _T_411 = eq(_T_410, asSInt(UInt<1>(0h0))) node _T_412 = or(_T_376, _T_381) node _T_413 = or(_T_412, _T_386) node _T_414 = or(_T_413, _T_391) node _T_415 = or(_T_414, _T_396) node _T_416 = or(_T_415, _T_401) node _T_417 = or(_T_416, _T_406) node _T_418 = or(_T_417, _T_411) node _T_419 = and(_T_371, _T_418) node _T_420 = or(UInt<1>(0h0), _T_419) node _T_421 = and(UInt<1>(0h0), _T_420) node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_T_421, UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_421, UInt<1>(0h1), "") : assert_11 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(source_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_428 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_428, UInt<1>(0h1), "") : assert_13 node _T_432 = asUInt(reset) node _T_433 = eq(_T_432, UInt<1>(0h0)) when _T_433 : node _T_434 = eq(is_aligned, UInt<1>(0h0)) when _T_434 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_435 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_436 = asUInt(reset) node _T_437 = eq(_T_436, UInt<1>(0h0)) when _T_437 : node _T_438 = eq(_T_435, UInt<1>(0h0)) when _T_438 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_435, UInt<1>(0h1), "") : assert_15 node _T_439 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_440 = asUInt(reset) node _T_441 = eq(_T_440, UInt<1>(0h0)) when _T_441 : node _T_442 = eq(_T_439, UInt<1>(0h0)) when _T_442 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_439, UInt<1>(0h1), "") : assert_16 node _T_443 = not(io.in.a.bits.mask) node _T_444 = eq(_T_443, UInt<1>(0h0)) node _T_445 = asUInt(reset) node _T_446 = eq(_T_445, UInt<1>(0h0)) when _T_446 : node _T_447 = eq(_T_444, UInt<1>(0h0)) when _T_447 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_444, UInt<1>(0h1), "") : assert_17 node _T_448 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_449 = asUInt(reset) node _T_450 = eq(_T_449, UInt<1>(0h0)) when _T_450 : node _T_451 = eq(_T_448, UInt<1>(0h0)) when _T_451 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_448, UInt<1>(0h1), "") : assert_18 node _T_452 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_452 : node _T_453 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_454 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_455 = and(_T_453, _T_454) node _T_456 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_457 = shr(io.in.a.bits.source, 2) node _T_458 = eq(_T_457, UInt<1>(0h0)) node _T_459 = leq(UInt<1>(0h0), uncommonBits_12) node _T_460 = and(_T_458, _T_459) node _T_461 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_462 = and(_T_460, _T_461) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_463 = shr(io.in.a.bits.source, 2) node _T_464 = eq(_T_463, UInt<1>(0h1)) node _T_465 = leq(UInt<1>(0h0), uncommonBits_13) node _T_466 = and(_T_464, _T_465) node _T_467 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_468 = and(_T_466, _T_467) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_469 = shr(io.in.a.bits.source, 2) node _T_470 = eq(_T_469, UInt<2>(0h2)) node _T_471 = leq(UInt<1>(0h0), uncommonBits_14) node _T_472 = and(_T_470, _T_471) node _T_473 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_474 = and(_T_472, _T_473) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_475 = shr(io.in.a.bits.source, 2) node _T_476 = eq(_T_475, UInt<2>(0h3)) node _T_477 = leq(UInt<1>(0h0), uncommonBits_15) node _T_478 = and(_T_476, _T_477) node _T_479 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_480 = and(_T_478, _T_479) node _T_481 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_482 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_483 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_484 = or(_T_456, _T_462) node _T_485 = or(_T_484, _T_468) node _T_486 = or(_T_485, _T_474) node _T_487 = or(_T_486, _T_480) node _T_488 = or(_T_487, _T_481) node _T_489 = or(_T_488, _T_482) node _T_490 = or(_T_489, _T_483) node _T_491 = and(_T_455, _T_490) node _T_492 = or(UInt<1>(0h0), _T_491) node _T_493 = asUInt(reset) node _T_494 = eq(_T_493, UInt<1>(0h0)) when _T_494 : node _T_495 = eq(_T_492, UInt<1>(0h0)) when _T_495 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_492, UInt<1>(0h1), "") : assert_19 node _T_496 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_497 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_498 = and(_T_496, _T_497) node _T_499 = or(UInt<1>(0h0), _T_498) node _T_500 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_501 = cvt(_T_500) node _T_502 = and(_T_501, asSInt(UInt<13>(0h1000))) node _T_503 = asSInt(_T_502) node _T_504 = eq(_T_503, asSInt(UInt<1>(0h0))) node _T_505 = and(_T_499, _T_504) node _T_506 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_507 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_508 = and(_T_506, _T_507) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_511 = cvt(_T_510) node _T_512 = and(_T_511, asSInt(UInt<14>(0h2000))) node _T_513 = asSInt(_T_512) node _T_514 = eq(_T_513, asSInt(UInt<1>(0h0))) node _T_515 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_516 = cvt(_T_515) node _T_517 = and(_T_516, asSInt(UInt<17>(0h10000))) node _T_518 = asSInt(_T_517) node _T_519 = eq(_T_518, asSInt(UInt<1>(0h0))) node _T_520 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_521 = cvt(_T_520) node _T_522 = and(_T_521, asSInt(UInt<18>(0h2f000))) node _T_523 = asSInt(_T_522) node _T_524 = eq(_T_523, asSInt(UInt<1>(0h0))) node _T_525 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_526 = cvt(_T_525) node _T_527 = and(_T_526, asSInt(UInt<17>(0h10000))) node _T_528 = asSInt(_T_527) node _T_529 = eq(_T_528, asSInt(UInt<1>(0h0))) node _T_530 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_531 = cvt(_T_530) node _T_532 = and(_T_531, asSInt(UInt<27>(0h4000000))) node _T_533 = asSInt(_T_532) node _T_534 = eq(_T_533, asSInt(UInt<1>(0h0))) node _T_535 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_536 = cvt(_T_535) node _T_537 = and(_T_536, asSInt(UInt<13>(0h1000))) node _T_538 = asSInt(_T_537) node _T_539 = eq(_T_538, asSInt(UInt<1>(0h0))) node _T_540 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_541 = cvt(_T_540) node _T_542 = and(_T_541, asSInt(UInt<19>(0h40000))) node _T_543 = asSInt(_T_542) node _T_544 = eq(_T_543, asSInt(UInt<1>(0h0))) node _T_545 = or(_T_514, _T_519) node _T_546 = or(_T_545, _T_524) node _T_547 = or(_T_546, _T_529) node _T_548 = or(_T_547, _T_534) node _T_549 = or(_T_548, _T_539) node _T_550 = or(_T_549, _T_544) node _T_551 = and(_T_509, _T_550) node _T_552 = or(UInt<1>(0h0), _T_505) node _T_553 = or(_T_552, _T_551) node _T_554 = asUInt(reset) node _T_555 = eq(_T_554, UInt<1>(0h0)) when _T_555 : node _T_556 = eq(_T_553, UInt<1>(0h0)) when _T_556 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_553, UInt<1>(0h1), "") : assert_20 node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(source_ok, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_560 = asUInt(reset) node _T_561 = eq(_T_560, UInt<1>(0h0)) when _T_561 : node _T_562 = eq(is_aligned, UInt<1>(0h0)) when _T_562 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_563 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_564 = asUInt(reset) node _T_565 = eq(_T_564, UInt<1>(0h0)) when _T_565 : node _T_566 = eq(_T_563, UInt<1>(0h0)) when _T_566 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_563, UInt<1>(0h1), "") : assert_23 node _T_567 = eq(io.in.a.bits.mask, mask) node _T_568 = asUInt(reset) node _T_569 = eq(_T_568, UInt<1>(0h0)) when _T_569 : node _T_570 = eq(_T_567, UInt<1>(0h0)) when _T_570 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_567, UInt<1>(0h1), "") : assert_24 node _T_571 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_572 = asUInt(reset) node _T_573 = eq(_T_572, UInt<1>(0h0)) when _T_573 : node _T_574 = eq(_T_571, UInt<1>(0h0)) when _T_574 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_571, UInt<1>(0h1), "") : assert_25 node _T_575 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_575 : node _T_576 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_577 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_578 = and(_T_576, _T_577) node _T_579 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_580 = shr(io.in.a.bits.source, 2) node _T_581 = eq(_T_580, UInt<1>(0h0)) node _T_582 = leq(UInt<1>(0h0), uncommonBits_16) node _T_583 = and(_T_581, _T_582) node _T_584 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_585 = and(_T_583, _T_584) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_586 = shr(io.in.a.bits.source, 2) node _T_587 = eq(_T_586, UInt<1>(0h1)) node _T_588 = leq(UInt<1>(0h0), uncommonBits_17) node _T_589 = and(_T_587, _T_588) node _T_590 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_591 = and(_T_589, _T_590) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_592 = shr(io.in.a.bits.source, 2) node _T_593 = eq(_T_592, UInt<2>(0h2)) node _T_594 = leq(UInt<1>(0h0), uncommonBits_18) node _T_595 = and(_T_593, _T_594) node _T_596 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_597 = and(_T_595, _T_596) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_598 = shr(io.in.a.bits.source, 2) node _T_599 = eq(_T_598, UInt<2>(0h3)) node _T_600 = leq(UInt<1>(0h0), uncommonBits_19) node _T_601 = and(_T_599, _T_600) node _T_602 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_603 = and(_T_601, _T_602) node _T_604 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_605 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_606 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_607 = or(_T_579, _T_585) node _T_608 = or(_T_607, _T_591) node _T_609 = or(_T_608, _T_597) node _T_610 = or(_T_609, _T_603) node _T_611 = or(_T_610, _T_604) node _T_612 = or(_T_611, _T_605) node _T_613 = or(_T_612, _T_606) node _T_614 = and(_T_578, _T_613) node _T_615 = or(UInt<1>(0h0), _T_614) node _T_616 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_617 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_618 = and(_T_616, _T_617) node _T_619 = or(UInt<1>(0h0), _T_618) node _T_620 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_621 = cvt(_T_620) node _T_622 = and(_T_621, asSInt(UInt<13>(0h1000))) node _T_623 = asSInt(_T_622) node _T_624 = eq(_T_623, asSInt(UInt<1>(0h0))) node _T_625 = and(_T_619, _T_624) node _T_626 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_627 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_628 = and(_T_626, _T_627) node _T_629 = or(UInt<1>(0h0), _T_628) node _T_630 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_631 = cvt(_T_630) node _T_632 = and(_T_631, asSInt(UInt<14>(0h2000))) node _T_633 = asSInt(_T_632) node _T_634 = eq(_T_633, asSInt(UInt<1>(0h0))) node _T_635 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_636 = cvt(_T_635) node _T_637 = and(_T_636, asSInt(UInt<18>(0h2f000))) node _T_638 = asSInt(_T_637) node _T_639 = eq(_T_638, asSInt(UInt<1>(0h0))) node _T_640 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_641 = cvt(_T_640) node _T_642 = and(_T_641, asSInt(UInt<17>(0h10000))) node _T_643 = asSInt(_T_642) node _T_644 = eq(_T_643, asSInt(UInt<1>(0h0))) node _T_645 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_646 = cvt(_T_645) node _T_647 = and(_T_646, asSInt(UInt<27>(0h4000000))) node _T_648 = asSInt(_T_647) node _T_649 = eq(_T_648, asSInt(UInt<1>(0h0))) node _T_650 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_651 = cvt(_T_650) node _T_652 = and(_T_651, asSInt(UInt<13>(0h1000))) node _T_653 = asSInt(_T_652) node _T_654 = eq(_T_653, asSInt(UInt<1>(0h0))) node _T_655 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_656 = cvt(_T_655) node _T_657 = and(_T_656, asSInt(UInt<19>(0h40000))) node _T_658 = asSInt(_T_657) node _T_659 = eq(_T_658, asSInt(UInt<1>(0h0))) node _T_660 = or(_T_634, _T_639) node _T_661 = or(_T_660, _T_644) node _T_662 = or(_T_661, _T_649) node _T_663 = or(_T_662, _T_654) node _T_664 = or(_T_663, _T_659) node _T_665 = and(_T_629, _T_664) node _T_666 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_667 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_668 = cvt(_T_667) node _T_669 = and(_T_668, asSInt(UInt<17>(0h10000))) node _T_670 = asSInt(_T_669) node _T_671 = eq(_T_670, asSInt(UInt<1>(0h0))) node _T_672 = and(_T_666, _T_671) node _T_673 = or(UInt<1>(0h0), _T_625) node _T_674 = or(_T_673, _T_665) node _T_675 = or(_T_674, _T_672) node _T_676 = and(_T_615, _T_675) node _T_677 = asUInt(reset) node _T_678 = eq(_T_677, UInt<1>(0h0)) when _T_678 : node _T_679 = eq(_T_676, UInt<1>(0h0)) when _T_679 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_676, UInt<1>(0h1), "") : assert_26 node _T_680 = asUInt(reset) node _T_681 = eq(_T_680, UInt<1>(0h0)) when _T_681 : node _T_682 = eq(source_ok, UInt<1>(0h0)) when _T_682 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_683 = asUInt(reset) node _T_684 = eq(_T_683, UInt<1>(0h0)) when _T_684 : node _T_685 = eq(is_aligned, UInt<1>(0h0)) when _T_685 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_686 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_687 = asUInt(reset) node _T_688 = eq(_T_687, UInt<1>(0h0)) when _T_688 : node _T_689 = eq(_T_686, UInt<1>(0h0)) when _T_689 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_686, UInt<1>(0h1), "") : assert_29 node _T_690 = eq(io.in.a.bits.mask, mask) node _T_691 = asUInt(reset) node _T_692 = eq(_T_691, UInt<1>(0h0)) when _T_692 : node _T_693 = eq(_T_690, UInt<1>(0h0)) when _T_693 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_690, UInt<1>(0h1), "") : assert_30 node _T_694 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_694 : node _T_695 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_696 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_697 = and(_T_695, _T_696) node _T_698 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_699 = shr(io.in.a.bits.source, 2) node _T_700 = eq(_T_699, UInt<1>(0h0)) node _T_701 = leq(UInt<1>(0h0), uncommonBits_20) node _T_702 = and(_T_700, _T_701) node _T_703 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_704 = and(_T_702, _T_703) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_705 = shr(io.in.a.bits.source, 2) node _T_706 = eq(_T_705, UInt<1>(0h1)) node _T_707 = leq(UInt<1>(0h0), uncommonBits_21) node _T_708 = and(_T_706, _T_707) node _T_709 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_710 = and(_T_708, _T_709) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_711 = shr(io.in.a.bits.source, 2) node _T_712 = eq(_T_711, UInt<2>(0h2)) node _T_713 = leq(UInt<1>(0h0), uncommonBits_22) node _T_714 = and(_T_712, _T_713) node _T_715 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_716 = and(_T_714, _T_715) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_717 = shr(io.in.a.bits.source, 2) node _T_718 = eq(_T_717, UInt<2>(0h3)) node _T_719 = leq(UInt<1>(0h0), uncommonBits_23) node _T_720 = and(_T_718, _T_719) node _T_721 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_722 = and(_T_720, _T_721) node _T_723 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_724 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_725 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_726 = or(_T_698, _T_704) node _T_727 = or(_T_726, _T_710) node _T_728 = or(_T_727, _T_716) node _T_729 = or(_T_728, _T_722) node _T_730 = or(_T_729, _T_723) node _T_731 = or(_T_730, _T_724) node _T_732 = or(_T_731, _T_725) node _T_733 = and(_T_697, _T_732) node _T_734 = or(UInt<1>(0h0), _T_733) node _T_735 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_736 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_737 = and(_T_735, _T_736) node _T_738 = or(UInt<1>(0h0), _T_737) node _T_739 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_740 = cvt(_T_739) node _T_741 = and(_T_740, asSInt(UInt<13>(0h1000))) node _T_742 = asSInt(_T_741) node _T_743 = eq(_T_742, asSInt(UInt<1>(0h0))) node _T_744 = and(_T_738, _T_743) node _T_745 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_746 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_747 = and(_T_745, _T_746) node _T_748 = or(UInt<1>(0h0), _T_747) node _T_749 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_750 = cvt(_T_749) node _T_751 = and(_T_750, asSInt(UInt<14>(0h2000))) node _T_752 = asSInt(_T_751) node _T_753 = eq(_T_752, asSInt(UInt<1>(0h0))) node _T_754 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_755 = cvt(_T_754) node _T_756 = and(_T_755, asSInt(UInt<18>(0h2f000))) node _T_757 = asSInt(_T_756) node _T_758 = eq(_T_757, asSInt(UInt<1>(0h0))) node _T_759 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_760 = cvt(_T_759) node _T_761 = and(_T_760, asSInt(UInt<17>(0h10000))) node _T_762 = asSInt(_T_761) node _T_763 = eq(_T_762, asSInt(UInt<1>(0h0))) node _T_764 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_765 = cvt(_T_764) node _T_766 = and(_T_765, asSInt(UInt<27>(0h4000000))) node _T_767 = asSInt(_T_766) node _T_768 = eq(_T_767, asSInt(UInt<1>(0h0))) node _T_769 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_770 = cvt(_T_769) node _T_771 = and(_T_770, asSInt(UInt<13>(0h1000))) node _T_772 = asSInt(_T_771) node _T_773 = eq(_T_772, asSInt(UInt<1>(0h0))) node _T_774 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_775 = cvt(_T_774) node _T_776 = and(_T_775, asSInt(UInt<19>(0h40000))) node _T_777 = asSInt(_T_776) node _T_778 = eq(_T_777, asSInt(UInt<1>(0h0))) node _T_779 = or(_T_753, _T_758) node _T_780 = or(_T_779, _T_763) node _T_781 = or(_T_780, _T_768) node _T_782 = or(_T_781, _T_773) node _T_783 = or(_T_782, _T_778) node _T_784 = and(_T_748, _T_783) node _T_785 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_786 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_787 = cvt(_T_786) node _T_788 = and(_T_787, asSInt(UInt<17>(0h10000))) node _T_789 = asSInt(_T_788) node _T_790 = eq(_T_789, asSInt(UInt<1>(0h0))) node _T_791 = and(_T_785, _T_790) node _T_792 = or(UInt<1>(0h0), _T_744) node _T_793 = or(_T_792, _T_784) node _T_794 = or(_T_793, _T_791) node _T_795 = and(_T_734, _T_794) node _T_796 = asUInt(reset) node _T_797 = eq(_T_796, UInt<1>(0h0)) when _T_797 : node _T_798 = eq(_T_795, UInt<1>(0h0)) when _T_798 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_795, UInt<1>(0h1), "") : assert_31 node _T_799 = asUInt(reset) node _T_800 = eq(_T_799, UInt<1>(0h0)) when _T_800 : node _T_801 = eq(source_ok, UInt<1>(0h0)) when _T_801 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_802 = asUInt(reset) node _T_803 = eq(_T_802, UInt<1>(0h0)) when _T_803 : node _T_804 = eq(is_aligned, UInt<1>(0h0)) when _T_804 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_805 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_806 = asUInt(reset) node _T_807 = eq(_T_806, UInt<1>(0h0)) when _T_807 : node _T_808 = eq(_T_805, UInt<1>(0h0)) when _T_808 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_805, UInt<1>(0h1), "") : assert_34 node _T_809 = not(mask) node _T_810 = and(io.in.a.bits.mask, _T_809) node _T_811 = eq(_T_810, UInt<1>(0h0)) node _T_812 = asUInt(reset) node _T_813 = eq(_T_812, UInt<1>(0h0)) when _T_813 : node _T_814 = eq(_T_811, UInt<1>(0h0)) when _T_814 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_811, UInt<1>(0h1), "") : assert_35 node _T_815 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_815 : node _T_816 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_817 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_818 = and(_T_816, _T_817) node _T_819 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_820 = shr(io.in.a.bits.source, 2) node _T_821 = eq(_T_820, UInt<1>(0h0)) node _T_822 = leq(UInt<1>(0h0), uncommonBits_24) node _T_823 = and(_T_821, _T_822) node _T_824 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_825 = and(_T_823, _T_824) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_826 = shr(io.in.a.bits.source, 2) node _T_827 = eq(_T_826, UInt<1>(0h1)) node _T_828 = leq(UInt<1>(0h0), uncommonBits_25) node _T_829 = and(_T_827, _T_828) node _T_830 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_831 = and(_T_829, _T_830) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_832 = shr(io.in.a.bits.source, 2) node _T_833 = eq(_T_832, UInt<2>(0h2)) node _T_834 = leq(UInt<1>(0h0), uncommonBits_26) node _T_835 = and(_T_833, _T_834) node _T_836 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_837 = and(_T_835, _T_836) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_838 = shr(io.in.a.bits.source, 2) node _T_839 = eq(_T_838, UInt<2>(0h3)) node _T_840 = leq(UInt<1>(0h0), uncommonBits_27) node _T_841 = and(_T_839, _T_840) node _T_842 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_843 = and(_T_841, _T_842) node _T_844 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_845 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_846 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_847 = or(_T_819, _T_825) node _T_848 = or(_T_847, _T_831) node _T_849 = or(_T_848, _T_837) node _T_850 = or(_T_849, _T_843) node _T_851 = or(_T_850, _T_844) node _T_852 = or(_T_851, _T_845) node _T_853 = or(_T_852, _T_846) node _T_854 = and(_T_818, _T_853) node _T_855 = or(UInt<1>(0h0), _T_854) node _T_856 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_857 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_858 = and(_T_856, _T_857) node _T_859 = or(UInt<1>(0h0), _T_858) node _T_860 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_861 = cvt(_T_860) node _T_862 = and(_T_861, asSInt(UInt<15>(0h5000))) node _T_863 = asSInt(_T_862) node _T_864 = eq(_T_863, asSInt(UInt<1>(0h0))) node _T_865 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_866 = cvt(_T_865) node _T_867 = and(_T_866, asSInt(UInt<13>(0h1000))) node _T_868 = asSInt(_T_867) node _T_869 = eq(_T_868, asSInt(UInt<1>(0h0))) node _T_870 = or(_T_864, _T_869) node _T_871 = and(_T_859, _T_870) node _T_872 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_873 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_874 = cvt(_T_873) node _T_875 = and(_T_874, asSInt(UInt<13>(0h1000))) node _T_876 = asSInt(_T_875) node _T_877 = eq(_T_876, asSInt(UInt<1>(0h0))) node _T_878 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_879 = cvt(_T_878) node _T_880 = and(_T_879, asSInt(UInt<17>(0h10000))) node _T_881 = asSInt(_T_880) node _T_882 = eq(_T_881, asSInt(UInt<1>(0h0))) node _T_883 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_884 = cvt(_T_883) node _T_885 = and(_T_884, asSInt(UInt<18>(0h2f000))) node _T_886 = asSInt(_T_885) node _T_887 = eq(_T_886, asSInt(UInt<1>(0h0))) node _T_888 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_889 = cvt(_T_888) node _T_890 = and(_T_889, asSInt(UInt<17>(0h10000))) node _T_891 = asSInt(_T_890) node _T_892 = eq(_T_891, asSInt(UInt<1>(0h0))) node _T_893 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_894 = cvt(_T_893) node _T_895 = and(_T_894, asSInt(UInt<27>(0h4000000))) node _T_896 = asSInt(_T_895) node _T_897 = eq(_T_896, asSInt(UInt<1>(0h0))) node _T_898 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_899 = cvt(_T_898) node _T_900 = and(_T_899, asSInt(UInt<19>(0h40000))) node _T_901 = asSInt(_T_900) node _T_902 = eq(_T_901, asSInt(UInt<1>(0h0))) node _T_903 = or(_T_877, _T_882) node _T_904 = or(_T_903, _T_887) node _T_905 = or(_T_904, _T_892) node _T_906 = or(_T_905, _T_897) node _T_907 = or(_T_906, _T_902) node _T_908 = and(_T_872, _T_907) node _T_909 = or(UInt<1>(0h0), _T_871) node _T_910 = or(_T_909, _T_908) node _T_911 = and(_T_855, _T_910) node _T_912 = asUInt(reset) node _T_913 = eq(_T_912, UInt<1>(0h0)) when _T_913 : node _T_914 = eq(_T_911, UInt<1>(0h0)) when _T_914 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_911, UInt<1>(0h1), "") : assert_36 node _T_915 = asUInt(reset) node _T_916 = eq(_T_915, UInt<1>(0h0)) when _T_916 : node _T_917 = eq(source_ok, UInt<1>(0h0)) when _T_917 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_918 = asUInt(reset) node _T_919 = eq(_T_918, UInt<1>(0h0)) when _T_919 : node _T_920 = eq(is_aligned, UInt<1>(0h0)) when _T_920 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_921 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_922 = asUInt(reset) node _T_923 = eq(_T_922, UInt<1>(0h0)) when _T_923 : node _T_924 = eq(_T_921, UInt<1>(0h0)) when _T_924 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_921, UInt<1>(0h1), "") : assert_39 node _T_925 = eq(io.in.a.bits.mask, mask) node _T_926 = asUInt(reset) node _T_927 = eq(_T_926, UInt<1>(0h0)) when _T_927 : node _T_928 = eq(_T_925, UInt<1>(0h0)) when _T_928 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_925, UInt<1>(0h1), "") : assert_40 node _T_929 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_929 : node _T_930 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_931 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_932 = and(_T_930, _T_931) node _T_933 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_934 = shr(io.in.a.bits.source, 2) node _T_935 = eq(_T_934, UInt<1>(0h0)) node _T_936 = leq(UInt<1>(0h0), uncommonBits_28) node _T_937 = and(_T_935, _T_936) node _T_938 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_939 = and(_T_937, _T_938) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_940 = shr(io.in.a.bits.source, 2) node _T_941 = eq(_T_940, UInt<1>(0h1)) node _T_942 = leq(UInt<1>(0h0), uncommonBits_29) node _T_943 = and(_T_941, _T_942) node _T_944 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_945 = and(_T_943, _T_944) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_946 = shr(io.in.a.bits.source, 2) node _T_947 = eq(_T_946, UInt<2>(0h2)) node _T_948 = leq(UInt<1>(0h0), uncommonBits_30) node _T_949 = and(_T_947, _T_948) node _T_950 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_951 = and(_T_949, _T_950) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_952 = shr(io.in.a.bits.source, 2) node _T_953 = eq(_T_952, UInt<2>(0h3)) node _T_954 = leq(UInt<1>(0h0), uncommonBits_31) node _T_955 = and(_T_953, _T_954) node _T_956 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_957 = and(_T_955, _T_956) node _T_958 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_959 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_960 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_961 = or(_T_933, _T_939) node _T_962 = or(_T_961, _T_945) node _T_963 = or(_T_962, _T_951) node _T_964 = or(_T_963, _T_957) node _T_965 = or(_T_964, _T_958) node _T_966 = or(_T_965, _T_959) node _T_967 = or(_T_966, _T_960) node _T_968 = and(_T_932, _T_967) node _T_969 = or(UInt<1>(0h0), _T_968) node _T_970 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_971 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_972 = and(_T_970, _T_971) node _T_973 = or(UInt<1>(0h0), _T_972) node _T_974 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_975 = cvt(_T_974) node _T_976 = and(_T_975, asSInt(UInt<15>(0h5000))) node _T_977 = asSInt(_T_976) node _T_978 = eq(_T_977, asSInt(UInt<1>(0h0))) node _T_979 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_980 = cvt(_T_979) node _T_981 = and(_T_980, asSInt(UInt<13>(0h1000))) node _T_982 = asSInt(_T_981) node _T_983 = eq(_T_982, asSInt(UInt<1>(0h0))) node _T_984 = or(_T_978, _T_983) node _T_985 = and(_T_973, _T_984) node _T_986 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_987 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_988 = cvt(_T_987) node _T_989 = and(_T_988, asSInt(UInt<13>(0h1000))) node _T_990 = asSInt(_T_989) node _T_991 = eq(_T_990, asSInt(UInt<1>(0h0))) node _T_992 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_993 = cvt(_T_992) node _T_994 = and(_T_993, asSInt(UInt<17>(0h10000))) node _T_995 = asSInt(_T_994) node _T_996 = eq(_T_995, asSInt(UInt<1>(0h0))) node _T_997 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_998 = cvt(_T_997) node _T_999 = and(_T_998, asSInt(UInt<18>(0h2f000))) node _T_1000 = asSInt(_T_999) node _T_1001 = eq(_T_1000, asSInt(UInt<1>(0h0))) node _T_1002 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1003 = cvt(_T_1002) node _T_1004 = and(_T_1003, asSInt(UInt<17>(0h10000))) node _T_1005 = asSInt(_T_1004) node _T_1006 = eq(_T_1005, asSInt(UInt<1>(0h0))) node _T_1007 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1008 = cvt(_T_1007) node _T_1009 = and(_T_1008, asSInt(UInt<27>(0h4000000))) node _T_1010 = asSInt(_T_1009) node _T_1011 = eq(_T_1010, asSInt(UInt<1>(0h0))) node _T_1012 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_1013 = cvt(_T_1012) node _T_1014 = and(_T_1013, asSInt(UInt<19>(0h40000))) node _T_1015 = asSInt(_T_1014) node _T_1016 = eq(_T_1015, asSInt(UInt<1>(0h0))) node _T_1017 = or(_T_991, _T_996) node _T_1018 = or(_T_1017, _T_1001) node _T_1019 = or(_T_1018, _T_1006) node _T_1020 = or(_T_1019, _T_1011) node _T_1021 = or(_T_1020, _T_1016) node _T_1022 = and(_T_986, _T_1021) node _T_1023 = or(UInt<1>(0h0), _T_985) node _T_1024 = or(_T_1023, _T_1022) node _T_1025 = and(_T_969, _T_1024) node _T_1026 = asUInt(reset) node _T_1027 = eq(_T_1026, UInt<1>(0h0)) when _T_1027 : node _T_1028 = eq(_T_1025, UInt<1>(0h0)) when _T_1028 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_1025, UInt<1>(0h1), "") : assert_41 node _T_1029 = asUInt(reset) node _T_1030 = eq(_T_1029, UInt<1>(0h0)) when _T_1030 : node _T_1031 = eq(source_ok, UInt<1>(0h0)) when _T_1031 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_1032 = asUInt(reset) node _T_1033 = eq(_T_1032, UInt<1>(0h0)) when _T_1033 : node _T_1034 = eq(is_aligned, UInt<1>(0h0)) when _T_1034 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_1035 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_1036 = asUInt(reset) node _T_1037 = eq(_T_1036, UInt<1>(0h0)) when _T_1037 : node _T_1038 = eq(_T_1035, UInt<1>(0h0)) when _T_1038 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_1035, UInt<1>(0h1), "") : assert_44 node _T_1039 = eq(io.in.a.bits.mask, mask) node _T_1040 = asUInt(reset) node _T_1041 = eq(_T_1040, UInt<1>(0h0)) when _T_1041 : node _T_1042 = eq(_T_1039, UInt<1>(0h0)) when _T_1042 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_1039, UInt<1>(0h1), "") : assert_45 node _T_1043 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_1043 : node _T_1044 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1045 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1046 = and(_T_1044, _T_1045) node _T_1047 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_1048 = shr(io.in.a.bits.source, 2) node _T_1049 = eq(_T_1048, UInt<1>(0h0)) node _T_1050 = leq(UInt<1>(0h0), uncommonBits_32) node _T_1051 = and(_T_1049, _T_1050) node _T_1052 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_1053 = and(_T_1051, _T_1052) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_1054 = shr(io.in.a.bits.source, 2) node _T_1055 = eq(_T_1054, UInt<1>(0h1)) node _T_1056 = leq(UInt<1>(0h0), uncommonBits_33) node _T_1057 = and(_T_1055, _T_1056) node _T_1058 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_1059 = and(_T_1057, _T_1058) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_1060 = shr(io.in.a.bits.source, 2) node _T_1061 = eq(_T_1060, UInt<2>(0h2)) node _T_1062 = leq(UInt<1>(0h0), uncommonBits_34) node _T_1063 = and(_T_1061, _T_1062) node _T_1064 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_1065 = and(_T_1063, _T_1064) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_1066 = shr(io.in.a.bits.source, 2) node _T_1067 = eq(_T_1066, UInt<2>(0h3)) node _T_1068 = leq(UInt<1>(0h0), uncommonBits_35) node _T_1069 = and(_T_1067, _T_1068) node _T_1070 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_1071 = and(_T_1069, _T_1070) node _T_1072 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1073 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1074 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1075 = or(_T_1047, _T_1053) node _T_1076 = or(_T_1075, _T_1059) node _T_1077 = or(_T_1076, _T_1065) node _T_1078 = or(_T_1077, _T_1071) node _T_1079 = or(_T_1078, _T_1072) node _T_1080 = or(_T_1079, _T_1073) node _T_1081 = or(_T_1080, _T_1074) node _T_1082 = and(_T_1046, _T_1081) node _T_1083 = or(UInt<1>(0h0), _T_1082) node _T_1084 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1085 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1086 = and(_T_1084, _T_1085) node _T_1087 = or(UInt<1>(0h0), _T_1086) node _T_1088 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1089 = cvt(_T_1088) node _T_1090 = and(_T_1089, asSInt(UInt<13>(0h1000))) node _T_1091 = asSInt(_T_1090) node _T_1092 = eq(_T_1091, asSInt(UInt<1>(0h0))) node _T_1093 = and(_T_1087, _T_1092) node _T_1094 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1095 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1096 = cvt(_T_1095) node _T_1097 = and(_T_1096, asSInt(UInt<14>(0h2000))) node _T_1098 = asSInt(_T_1097) node _T_1099 = eq(_T_1098, asSInt(UInt<1>(0h0))) node _T_1100 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1101 = cvt(_T_1100) node _T_1102 = and(_T_1101, asSInt(UInt<17>(0h10000))) node _T_1103 = asSInt(_T_1102) node _T_1104 = eq(_T_1103, asSInt(UInt<1>(0h0))) node _T_1105 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1106 = cvt(_T_1105) node _T_1107 = and(_T_1106, asSInt(UInt<18>(0h2f000))) node _T_1108 = asSInt(_T_1107) node _T_1109 = eq(_T_1108, asSInt(UInt<1>(0h0))) node _T_1110 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1111 = cvt(_T_1110) node _T_1112 = and(_T_1111, asSInt(UInt<17>(0h10000))) node _T_1113 = asSInt(_T_1112) node _T_1114 = eq(_T_1113, asSInt(UInt<1>(0h0))) node _T_1115 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1116 = cvt(_T_1115) node _T_1117 = and(_T_1116, asSInt(UInt<27>(0h4000000))) node _T_1118 = asSInt(_T_1117) node _T_1119 = eq(_T_1118, asSInt(UInt<1>(0h0))) node _T_1120 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1121 = cvt(_T_1120) node _T_1122 = and(_T_1121, asSInt(UInt<13>(0h1000))) node _T_1123 = asSInt(_T_1122) node _T_1124 = eq(_T_1123, asSInt(UInt<1>(0h0))) node _T_1125 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_1126 = cvt(_T_1125) node _T_1127 = and(_T_1126, asSInt(UInt<19>(0h40000))) node _T_1128 = asSInt(_T_1127) node _T_1129 = eq(_T_1128, asSInt(UInt<1>(0h0))) node _T_1130 = or(_T_1099, _T_1104) node _T_1131 = or(_T_1130, _T_1109) node _T_1132 = or(_T_1131, _T_1114) node _T_1133 = or(_T_1132, _T_1119) node _T_1134 = or(_T_1133, _T_1124) node _T_1135 = or(_T_1134, _T_1129) node _T_1136 = and(_T_1094, _T_1135) node _T_1137 = or(UInt<1>(0h0), _T_1093) node _T_1138 = or(_T_1137, _T_1136) node _T_1139 = and(_T_1083, _T_1138) node _T_1140 = asUInt(reset) node _T_1141 = eq(_T_1140, UInt<1>(0h0)) when _T_1141 : node _T_1142 = eq(_T_1139, UInt<1>(0h0)) when _T_1142 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1139, UInt<1>(0h1), "") : assert_46 node _T_1143 = asUInt(reset) node _T_1144 = eq(_T_1143, UInt<1>(0h0)) when _T_1144 : node _T_1145 = eq(source_ok, UInt<1>(0h0)) when _T_1145 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1146 = asUInt(reset) node _T_1147 = eq(_T_1146, UInt<1>(0h0)) when _T_1147 : node _T_1148 = eq(is_aligned, UInt<1>(0h0)) when _T_1148 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1149 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1150 = asUInt(reset) node _T_1151 = eq(_T_1150, UInt<1>(0h0)) when _T_1151 : node _T_1152 = eq(_T_1149, UInt<1>(0h0)) when _T_1152 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1149, UInt<1>(0h1), "") : assert_49 node _T_1153 = eq(io.in.a.bits.mask, mask) node _T_1154 = asUInt(reset) node _T_1155 = eq(_T_1154, UInt<1>(0h0)) when _T_1155 : node _T_1156 = eq(_T_1153, UInt<1>(0h0)) when _T_1156 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1153, UInt<1>(0h1), "") : assert_50 node _T_1157 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1158 = asUInt(reset) node _T_1159 = eq(_T_1158, UInt<1>(0h0)) when _T_1159 : node _T_1160 = eq(_T_1157, UInt<1>(0h0)) when _T_1160 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1157, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1161 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1162 = asUInt(reset) node _T_1163 = eq(_T_1162, UInt<1>(0h0)) when _T_1163 : node _T_1164 = eq(_T_1161, UInt<1>(0h0)) when _T_1164 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1161, UInt<1>(0h1), "") : assert_52 node _source_ok_T_34 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_35 = shr(io.in.d.bits.source, 2) node _source_ok_T_36 = eq(_source_ok_T_35, UInt<1>(0h0)) node _source_ok_T_37 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_38 = and(_source_ok_T_36, _source_ok_T_37) node _source_ok_T_39 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_40 = and(_source_ok_T_38, _source_ok_T_39) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_41 = shr(io.in.d.bits.source, 2) node _source_ok_T_42 = eq(_source_ok_T_41, UInt<1>(0h1)) node _source_ok_T_43 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_44 = and(_source_ok_T_42, _source_ok_T_43) node _source_ok_T_45 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_46 = and(_source_ok_T_44, _source_ok_T_45) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_47 = shr(io.in.d.bits.source, 2) node _source_ok_T_48 = eq(_source_ok_T_47, UInt<2>(0h2)) node _source_ok_T_49 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_50 = and(_source_ok_T_48, _source_ok_T_49) node _source_ok_T_51 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_52 = and(_source_ok_T_50, _source_ok_T_51) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_53 = shr(io.in.d.bits.source, 2) node _source_ok_T_54 = eq(_source_ok_T_53, UInt<2>(0h3)) node _source_ok_T_55 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_56 = and(_source_ok_T_54, _source_ok_T_55) node _source_ok_T_57 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_58 = and(_source_ok_T_56, _source_ok_T_57) node _source_ok_T_59 = eq(io.in.d.bits.source, UInt<6>(0h21)) node _source_ok_T_60 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_61 = eq(io.in.d.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE_1 : UInt<1>[8] connect _source_ok_WIRE_1[0], _source_ok_T_34 connect _source_ok_WIRE_1[1], _source_ok_T_40 connect _source_ok_WIRE_1[2], _source_ok_T_46 connect _source_ok_WIRE_1[3], _source_ok_T_52 connect _source_ok_WIRE_1[4], _source_ok_T_58 connect _source_ok_WIRE_1[5], _source_ok_T_59 connect _source_ok_WIRE_1[6], _source_ok_T_60 connect _source_ok_WIRE_1[7], _source_ok_T_61 node _source_ok_T_62 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_63 = or(_source_ok_T_62, _source_ok_WIRE_1[2]) node _source_ok_T_64 = or(_source_ok_T_63, _source_ok_WIRE_1[3]) node _source_ok_T_65 = or(_source_ok_T_64, _source_ok_WIRE_1[4]) node _source_ok_T_66 = or(_source_ok_T_65, _source_ok_WIRE_1[5]) node _source_ok_T_67 = or(_source_ok_T_66, _source_ok_WIRE_1[6]) node source_ok_1 = or(_source_ok_T_67, _source_ok_WIRE_1[7]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_1165 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1165 : node _T_1166 = asUInt(reset) node _T_1167 = eq(_T_1166, UInt<1>(0h0)) when _T_1167 : node _T_1168 = eq(source_ok_1, UInt<1>(0h0)) when _T_1168 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1169 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1170 = asUInt(reset) node _T_1171 = eq(_T_1170, UInt<1>(0h0)) when _T_1171 : node _T_1172 = eq(_T_1169, UInt<1>(0h0)) when _T_1172 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1169, UInt<1>(0h1), "") : assert_54 node _T_1173 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1174 = asUInt(reset) node _T_1175 = eq(_T_1174, UInt<1>(0h0)) when _T_1175 : node _T_1176 = eq(_T_1173, UInt<1>(0h0)) when _T_1176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1173, UInt<1>(0h1), "") : assert_55 node _T_1177 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1178 = asUInt(reset) node _T_1179 = eq(_T_1178, UInt<1>(0h0)) when _T_1179 : node _T_1180 = eq(_T_1177, UInt<1>(0h0)) when _T_1180 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1177, UInt<1>(0h1), "") : assert_56 node _T_1181 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1182 = asUInt(reset) node _T_1183 = eq(_T_1182, UInt<1>(0h0)) when _T_1183 : node _T_1184 = eq(_T_1181, UInt<1>(0h0)) when _T_1184 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1181, UInt<1>(0h1), "") : assert_57 node _T_1185 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1185 : node _T_1186 = asUInt(reset) node _T_1187 = eq(_T_1186, UInt<1>(0h0)) when _T_1187 : node _T_1188 = eq(source_ok_1, UInt<1>(0h0)) when _T_1188 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1189 = asUInt(reset) node _T_1190 = eq(_T_1189, UInt<1>(0h0)) when _T_1190 : node _T_1191 = eq(sink_ok, UInt<1>(0h0)) when _T_1191 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1192 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1193 = asUInt(reset) node _T_1194 = eq(_T_1193, UInt<1>(0h0)) when _T_1194 : node _T_1195 = eq(_T_1192, UInt<1>(0h0)) when _T_1195 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1192, UInt<1>(0h1), "") : assert_60 node _T_1196 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1197 = asUInt(reset) node _T_1198 = eq(_T_1197, UInt<1>(0h0)) when _T_1198 : node _T_1199 = eq(_T_1196, UInt<1>(0h0)) when _T_1199 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1196, UInt<1>(0h1), "") : assert_61 node _T_1200 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1201 = asUInt(reset) node _T_1202 = eq(_T_1201, UInt<1>(0h0)) when _T_1202 : node _T_1203 = eq(_T_1200, UInt<1>(0h0)) when _T_1203 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1200, UInt<1>(0h1), "") : assert_62 node _T_1204 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1205 = asUInt(reset) node _T_1206 = eq(_T_1205, UInt<1>(0h0)) when _T_1206 : node _T_1207 = eq(_T_1204, UInt<1>(0h0)) when _T_1207 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1204, UInt<1>(0h1), "") : assert_63 node _T_1208 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1209 = or(UInt<1>(0h1), _T_1208) node _T_1210 = asUInt(reset) node _T_1211 = eq(_T_1210, UInt<1>(0h0)) when _T_1211 : node _T_1212 = eq(_T_1209, UInt<1>(0h0)) when _T_1212 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1209, UInt<1>(0h1), "") : assert_64 node _T_1213 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1213 : node _T_1214 = asUInt(reset) node _T_1215 = eq(_T_1214, UInt<1>(0h0)) when _T_1215 : node _T_1216 = eq(source_ok_1, UInt<1>(0h0)) when _T_1216 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1217 = asUInt(reset) node _T_1218 = eq(_T_1217, UInt<1>(0h0)) when _T_1218 : node _T_1219 = eq(sink_ok, UInt<1>(0h0)) when _T_1219 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1220 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1221 = asUInt(reset) node _T_1222 = eq(_T_1221, UInt<1>(0h0)) when _T_1222 : node _T_1223 = eq(_T_1220, UInt<1>(0h0)) when _T_1223 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1220, UInt<1>(0h1), "") : assert_67 node _T_1224 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1225 = asUInt(reset) node _T_1226 = eq(_T_1225, UInt<1>(0h0)) when _T_1226 : node _T_1227 = eq(_T_1224, UInt<1>(0h0)) when _T_1227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1224, UInt<1>(0h1), "") : assert_68 node _T_1228 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1229 = asUInt(reset) node _T_1230 = eq(_T_1229, UInt<1>(0h0)) when _T_1230 : node _T_1231 = eq(_T_1228, UInt<1>(0h0)) when _T_1231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1228, UInt<1>(0h1), "") : assert_69 node _T_1232 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1233 = or(_T_1232, io.in.d.bits.corrupt) node _T_1234 = asUInt(reset) node _T_1235 = eq(_T_1234, UInt<1>(0h0)) when _T_1235 : node _T_1236 = eq(_T_1233, UInt<1>(0h0)) when _T_1236 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1233, UInt<1>(0h1), "") : assert_70 node _T_1237 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1238 = or(UInt<1>(0h1), _T_1237) node _T_1239 = asUInt(reset) node _T_1240 = eq(_T_1239, UInt<1>(0h0)) when _T_1240 : node _T_1241 = eq(_T_1238, UInt<1>(0h0)) when _T_1241 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1238, UInt<1>(0h1), "") : assert_71 node _T_1242 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1242 : node _T_1243 = asUInt(reset) node _T_1244 = eq(_T_1243, UInt<1>(0h0)) when _T_1244 : node _T_1245 = eq(source_ok_1, UInt<1>(0h0)) when _T_1245 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1246 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1247 = asUInt(reset) node _T_1248 = eq(_T_1247, UInt<1>(0h0)) when _T_1248 : node _T_1249 = eq(_T_1246, UInt<1>(0h0)) when _T_1249 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1246, UInt<1>(0h1), "") : assert_73 node _T_1250 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1251 = asUInt(reset) node _T_1252 = eq(_T_1251, UInt<1>(0h0)) when _T_1252 : node _T_1253 = eq(_T_1250, UInt<1>(0h0)) when _T_1253 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1250, UInt<1>(0h1), "") : assert_74 node _T_1254 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1255 = or(UInt<1>(0h1), _T_1254) node _T_1256 = asUInt(reset) node _T_1257 = eq(_T_1256, UInt<1>(0h0)) when _T_1257 : node _T_1258 = eq(_T_1255, UInt<1>(0h0)) when _T_1258 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1255, UInt<1>(0h1), "") : assert_75 node _T_1259 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1259 : node _T_1260 = asUInt(reset) node _T_1261 = eq(_T_1260, UInt<1>(0h0)) when _T_1261 : node _T_1262 = eq(source_ok_1, UInt<1>(0h0)) when _T_1262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1263 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1264 = asUInt(reset) node _T_1265 = eq(_T_1264, UInt<1>(0h0)) when _T_1265 : node _T_1266 = eq(_T_1263, UInt<1>(0h0)) when _T_1266 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1263, UInt<1>(0h1), "") : assert_77 node _T_1267 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1268 = or(_T_1267, io.in.d.bits.corrupt) node _T_1269 = asUInt(reset) node _T_1270 = eq(_T_1269, UInt<1>(0h0)) when _T_1270 : node _T_1271 = eq(_T_1268, UInt<1>(0h0)) when _T_1271 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1268, UInt<1>(0h1), "") : assert_78 node _T_1272 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1273 = or(UInt<1>(0h1), _T_1272) node _T_1274 = asUInt(reset) node _T_1275 = eq(_T_1274, UInt<1>(0h0)) when _T_1275 : node _T_1276 = eq(_T_1273, UInt<1>(0h0)) when _T_1276 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1273, UInt<1>(0h1), "") : assert_79 node _T_1277 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1277 : node _T_1278 = asUInt(reset) node _T_1279 = eq(_T_1278, UInt<1>(0h0)) when _T_1279 : node _T_1280 = eq(source_ok_1, UInt<1>(0h0)) when _T_1280 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1281 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1282 = asUInt(reset) node _T_1283 = eq(_T_1282, UInt<1>(0h0)) when _T_1283 : node _T_1284 = eq(_T_1281, UInt<1>(0h0)) when _T_1284 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1281, UInt<1>(0h1), "") : assert_81 node _T_1285 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1286 = asUInt(reset) node _T_1287 = eq(_T_1286, UInt<1>(0h0)) when _T_1287 : node _T_1288 = eq(_T_1285, UInt<1>(0h0)) when _T_1288 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1285, UInt<1>(0h1), "") : assert_82 node _T_1289 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1290 = or(UInt<1>(0h1), _T_1289) node _T_1291 = asUInt(reset) node _T_1292 = eq(_T_1291, UInt<1>(0h0)) when _T_1292 : node _T_1293 = eq(_T_1290, UInt<1>(0h0)) when _T_1293 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1290, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<7>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1294 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_1295 = asUInt(reset) node _T_1296 = eq(_T_1295, UInt<1>(0h0)) when _T_1296 : node _T_1297 = eq(_T_1294, UInt<1>(0h0)) when _T_1297 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1294, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<7>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_1298 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_1299 = asUInt(reset) node _T_1300 = eq(_T_1299, UInt<1>(0h0)) when _T_1300 : node _T_1301 = eq(_T_1298, UInt<1>(0h0)) when _T_1301 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1298, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1302 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1303 = asUInt(reset) node _T_1304 = eq(_T_1303, UInt<1>(0h0)) when _T_1304 : node _T_1305 = eq(_T_1302, UInt<1>(0h0)) when _T_1305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1302, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1306 = eq(a_first, UInt<1>(0h0)) node _T_1307 = and(io.in.a.valid, _T_1306) when _T_1307 : node _T_1308 = eq(io.in.a.bits.opcode, opcode) node _T_1309 = asUInt(reset) node _T_1310 = eq(_T_1309, UInt<1>(0h0)) when _T_1310 : node _T_1311 = eq(_T_1308, UInt<1>(0h0)) when _T_1311 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1308, UInt<1>(0h1), "") : assert_87 node _T_1312 = eq(io.in.a.bits.param, param) node _T_1313 = asUInt(reset) node _T_1314 = eq(_T_1313, UInt<1>(0h0)) when _T_1314 : node _T_1315 = eq(_T_1312, UInt<1>(0h0)) when _T_1315 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1312, UInt<1>(0h1), "") : assert_88 node _T_1316 = eq(io.in.a.bits.size, size) node _T_1317 = asUInt(reset) node _T_1318 = eq(_T_1317, UInt<1>(0h0)) when _T_1318 : node _T_1319 = eq(_T_1316, UInt<1>(0h0)) when _T_1319 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1316, UInt<1>(0h1), "") : assert_89 node _T_1320 = eq(io.in.a.bits.source, source) node _T_1321 = asUInt(reset) node _T_1322 = eq(_T_1321, UInt<1>(0h0)) when _T_1322 : node _T_1323 = eq(_T_1320, UInt<1>(0h0)) when _T_1323 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1320, UInt<1>(0h1), "") : assert_90 node _T_1324 = eq(io.in.a.bits.address, address) node _T_1325 = asUInt(reset) node _T_1326 = eq(_T_1325, UInt<1>(0h0)) when _T_1326 : node _T_1327 = eq(_T_1324, UInt<1>(0h0)) when _T_1327 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1324, UInt<1>(0h1), "") : assert_91 node _T_1328 = and(io.in.a.ready, io.in.a.valid) node _T_1329 = and(_T_1328, a_first) when _T_1329 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1330 = eq(d_first, UInt<1>(0h0)) node _T_1331 = and(io.in.d.valid, _T_1330) when _T_1331 : node _T_1332 = eq(io.in.d.bits.opcode, opcode_1) node _T_1333 = asUInt(reset) node _T_1334 = eq(_T_1333, UInt<1>(0h0)) when _T_1334 : node _T_1335 = eq(_T_1332, UInt<1>(0h0)) when _T_1335 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1332, UInt<1>(0h1), "") : assert_92 node _T_1336 = eq(io.in.d.bits.param, param_1) node _T_1337 = asUInt(reset) node _T_1338 = eq(_T_1337, UInt<1>(0h0)) when _T_1338 : node _T_1339 = eq(_T_1336, UInt<1>(0h0)) when _T_1339 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1336, UInt<1>(0h1), "") : assert_93 node _T_1340 = eq(io.in.d.bits.size, size_1) node _T_1341 = asUInt(reset) node _T_1342 = eq(_T_1341, UInt<1>(0h0)) when _T_1342 : node _T_1343 = eq(_T_1340, UInt<1>(0h0)) when _T_1343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1340, UInt<1>(0h1), "") : assert_94 node _T_1344 = eq(io.in.d.bits.source, source_1) node _T_1345 = asUInt(reset) node _T_1346 = eq(_T_1345, UInt<1>(0h0)) when _T_1346 : node _T_1347 = eq(_T_1344, UInt<1>(0h0)) when _T_1347 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1344, UInt<1>(0h1), "") : assert_95 node _T_1348 = eq(io.in.d.bits.sink, sink) node _T_1349 = asUInt(reset) node _T_1350 = eq(_T_1349, UInt<1>(0h0)) when _T_1350 : node _T_1351 = eq(_T_1348, UInt<1>(0h0)) when _T_1351 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1348, UInt<1>(0h1), "") : assert_96 node _T_1352 = eq(io.in.d.bits.denied, denied) node _T_1353 = asUInt(reset) node _T_1354 = eq(_T_1353, UInt<1>(0h0)) when _T_1354 : node _T_1355 = eq(_T_1352, UInt<1>(0h0)) when _T_1355 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1352, UInt<1>(0h1), "") : assert_97 node _T_1356 = and(io.in.d.ready, io.in.d.valid) node _T_1357 = and(_T_1356, d_first) when _T_1357 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes : UInt<520>, clock, reset, UInt<520>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<65> connect a_set, UInt<65>(0h0) wire a_set_wo_ready : UInt<65> connect a_set_wo_ready, UInt<65>(0h0) wire a_opcodes_set : UInt<260> connect a_opcodes_set, UInt<260>(0h0) wire a_sizes_set : UInt<520> connect a_sizes_set, UInt<520>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1358 = and(io.in.a.valid, a_first_1) node _T_1359 = and(_T_1358, UInt<1>(0h1)) when _T_1359 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1360 = and(io.in.a.ready, io.in.a.valid) node _T_1361 = and(_T_1360, a_first_1) node _T_1362 = and(_T_1361, UInt<1>(0h1)) when _T_1362 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1363 = dshr(inflight, io.in.a.bits.source) node _T_1364 = bits(_T_1363, 0, 0) node _T_1365 = eq(_T_1364, UInt<1>(0h0)) node _T_1366 = asUInt(reset) node _T_1367 = eq(_T_1366, UInt<1>(0h0)) when _T_1367 : node _T_1368 = eq(_T_1365, UInt<1>(0h0)) when _T_1368 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1365, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<65> connect d_clr, UInt<65>(0h0) wire d_clr_wo_ready : UInt<65> connect d_clr_wo_ready, UInt<65>(0h0) wire d_opcodes_clr : UInt<260> connect d_opcodes_clr, UInt<260>(0h0) wire d_sizes_clr : UInt<520> connect d_sizes_clr, UInt<520>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1369 = and(io.in.d.valid, d_first_1) node _T_1370 = and(_T_1369, UInt<1>(0h1)) node _T_1371 = eq(d_release_ack, UInt<1>(0h0)) node _T_1372 = and(_T_1370, _T_1371) when _T_1372 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1373 = and(io.in.d.ready, io.in.d.valid) node _T_1374 = and(_T_1373, d_first_1) node _T_1375 = and(_T_1374, UInt<1>(0h1)) node _T_1376 = eq(d_release_ack, UInt<1>(0h0)) node _T_1377 = and(_T_1375, _T_1376) when _T_1377 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1378 = and(io.in.d.valid, d_first_1) node _T_1379 = and(_T_1378, UInt<1>(0h1)) node _T_1380 = eq(d_release_ack, UInt<1>(0h0)) node _T_1381 = and(_T_1379, _T_1380) when _T_1381 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1382 = dshr(inflight, io.in.d.bits.source) node _T_1383 = bits(_T_1382, 0, 0) node _T_1384 = or(_T_1383, same_cycle_resp) node _T_1385 = asUInt(reset) node _T_1386 = eq(_T_1385, UInt<1>(0h0)) when _T_1386 : node _T_1387 = eq(_T_1384, UInt<1>(0h0)) when _T_1387 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1384, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1388 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1389 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1390 = or(_T_1388, _T_1389) node _T_1391 = asUInt(reset) node _T_1392 = eq(_T_1391, UInt<1>(0h0)) when _T_1392 : node _T_1393 = eq(_T_1390, UInt<1>(0h0)) when _T_1393 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1390, UInt<1>(0h1), "") : assert_100 node _T_1394 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1395 = asUInt(reset) node _T_1396 = eq(_T_1395, UInt<1>(0h0)) when _T_1396 : node _T_1397 = eq(_T_1394, UInt<1>(0h0)) when _T_1397 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1394, UInt<1>(0h1), "") : assert_101 else : node _T_1398 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1399 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1400 = or(_T_1398, _T_1399) node _T_1401 = asUInt(reset) node _T_1402 = eq(_T_1401, UInt<1>(0h0)) when _T_1402 : node _T_1403 = eq(_T_1400, UInt<1>(0h0)) when _T_1403 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1400, UInt<1>(0h1), "") : assert_102 node _T_1404 = eq(io.in.d.bits.size, a_size_lookup) node _T_1405 = asUInt(reset) node _T_1406 = eq(_T_1405, UInt<1>(0h0)) when _T_1406 : node _T_1407 = eq(_T_1404, UInt<1>(0h0)) when _T_1407 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1404, UInt<1>(0h1), "") : assert_103 node _T_1408 = and(io.in.d.valid, d_first_1) node _T_1409 = and(_T_1408, a_first_1) node _T_1410 = and(_T_1409, io.in.a.valid) node _T_1411 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1412 = and(_T_1410, _T_1411) node _T_1413 = eq(d_release_ack, UInt<1>(0h0)) node _T_1414 = and(_T_1412, _T_1413) when _T_1414 : node _T_1415 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1416 = or(_T_1415, io.in.a.ready) node _T_1417 = asUInt(reset) node _T_1418 = eq(_T_1417, UInt<1>(0h0)) when _T_1418 : node _T_1419 = eq(_T_1416, UInt<1>(0h0)) when _T_1419 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1416, UInt<1>(0h1), "") : assert_104 node _T_1420 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1421 = orr(a_set_wo_ready) node _T_1422 = eq(_T_1421, UInt<1>(0h0)) node _T_1423 = or(_T_1420, _T_1422) node _T_1424 = asUInt(reset) node _T_1425 = eq(_T_1424, UInt<1>(0h0)) when _T_1425 : node _T_1426 = eq(_T_1423, UInt<1>(0h0)) when _T_1426 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1423, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_38 node _T_1427 = orr(inflight) node _T_1428 = eq(_T_1427, UInt<1>(0h0)) node _T_1429 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1430 = or(_T_1428, _T_1429) node _T_1431 = lt(watchdog, plusarg_reader.out) node _T_1432 = or(_T_1430, _T_1431) node _T_1433 = asUInt(reset) node _T_1434 = eq(_T_1433, UInt<1>(0h0)) when _T_1434 : node _T_1435 = eq(_T_1432, UInt<1>(0h0)) when _T_1435 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1432, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1436 = and(io.in.a.ready, io.in.a.valid) node _T_1437 = and(io.in.d.ready, io.in.d.valid) node _T_1438 = or(_T_1436, _T_1437) when _T_1438 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes_1 : UInt<520>, clock, reset, UInt<520>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<7>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<7>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<65> connect c_set, UInt<65>(0h0) wire c_set_wo_ready : UInt<65> connect c_set_wo_ready, UInt<65>(0h0) wire c_opcodes_set : UInt<260> connect c_opcodes_set, UInt<260>(0h0) wire c_sizes_set : UInt<520> connect c_sizes_set, UInt<520>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<7>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1439 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<7>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1440 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1441 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1442 = and(_T_1440, _T_1441) node _T_1443 = and(_T_1439, _T_1442) when _T_1443 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<7>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1444 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1445 = and(_T_1444, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<7>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1446 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1447 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1448 = and(_T_1446, _T_1447) node _T_1449 = and(_T_1445, _T_1448) when _T_1449 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<7>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<7>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1450 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1451 = bits(_T_1450, 0, 0) node _T_1452 = eq(_T_1451, UInt<1>(0h0)) node _T_1453 = asUInt(reset) node _T_1454 = eq(_T_1453, UInt<1>(0h0)) when _T_1454 : node _T_1455 = eq(_T_1452, UInt<1>(0h0)) when _T_1455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1452, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<65> connect d_clr_1, UInt<65>(0h0) wire d_clr_wo_ready_1 : UInt<65> connect d_clr_wo_ready_1, UInt<65>(0h0) wire d_opcodes_clr_1 : UInt<260> connect d_opcodes_clr_1, UInt<260>(0h0) wire d_sizes_clr_1 : UInt<520> connect d_sizes_clr_1, UInt<520>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1456 = and(io.in.d.valid, d_first_2) node _T_1457 = and(_T_1456, UInt<1>(0h1)) node _T_1458 = and(_T_1457, d_release_ack_1) when _T_1458 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1459 = and(io.in.d.ready, io.in.d.valid) node _T_1460 = and(_T_1459, d_first_2) node _T_1461 = and(_T_1460, UInt<1>(0h1)) node _T_1462 = and(_T_1461, d_release_ack_1) when _T_1462 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1463 = and(io.in.d.valid, d_first_2) node _T_1464 = and(_T_1463, UInt<1>(0h1)) node _T_1465 = and(_T_1464, d_release_ack_1) when _T_1465 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1466 = dshr(inflight_1, io.in.d.bits.source) node _T_1467 = bits(_T_1466, 0, 0) node _T_1468 = or(_T_1467, same_cycle_resp_1) node _T_1469 = asUInt(reset) node _T_1470 = eq(_T_1469, UInt<1>(0h0)) when _T_1470 : node _T_1471 = eq(_T_1468, UInt<1>(0h0)) when _T_1471 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1468, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<7>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1472 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1473 = asUInt(reset) node _T_1474 = eq(_T_1473, UInt<1>(0h0)) when _T_1474 : node _T_1475 = eq(_T_1472, UInt<1>(0h0)) when _T_1475 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1472, UInt<1>(0h1), "") : assert_109 else : node _T_1476 = eq(io.in.d.bits.size, c_size_lookup) node _T_1477 = asUInt(reset) node _T_1478 = eq(_T_1477, UInt<1>(0h0)) when _T_1478 : node _T_1479 = eq(_T_1476, UInt<1>(0h0)) when _T_1479 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1476, UInt<1>(0h1), "") : assert_110 node _T_1480 = and(io.in.d.valid, d_first_2) node _T_1481 = and(_T_1480, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<7>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1482 = and(_T_1481, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<7>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1483 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1484 = and(_T_1482, _T_1483) node _T_1485 = and(_T_1484, d_release_ack_1) node _T_1486 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1487 = and(_T_1485, _T_1486) when _T_1487 : node _T_1488 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<7>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1489 = or(_T_1488, _WIRE_23.ready) node _T_1490 = asUInt(reset) node _T_1491 = eq(_T_1490, UInt<1>(0h0)) when _T_1491 : node _T_1492 = eq(_T_1489, UInt<1>(0h0)) when _T_1492 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1489, UInt<1>(0h1), "") : assert_111 node _T_1493 = orr(c_set_wo_ready) when _T_1493 : node _T_1494 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1495 = asUInt(reset) node _T_1496 = eq(_T_1495, UInt<1>(0h0)) when _T_1496 : node _T_1497 = eq(_T_1494, UInt<1>(0h0)) when _T_1497 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1494, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_39 node _T_1498 = orr(inflight_1) node _T_1499 = eq(_T_1498, UInt<1>(0h0)) node _T_1500 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1501 = or(_T_1499, _T_1500) node _T_1502 = lt(watchdog_1, plusarg_reader_1.out) node _T_1503 = or(_T_1501, _T_1502) node _T_1504 = asUInt(reset) node _T_1505 = eq(_T_1504, UInt<1>(0h0)) when _T_1505 : node _T_1506 = eq(_T_1503, UInt<1>(0h0)) when _T_1506 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1503, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<7>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1507 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1508 = and(io.in.d.ready, io.in.d.valid) node _T_1509 = or(_T_1507, _T_1508) when _T_1509 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_19( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_37 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_43 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_49 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_55 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_57 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1027:0] _c_sizes_set_T_1 = 1028'h0; // @[Monitor.scala:768:52] wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79] wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77] wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35] wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35] wire [519:0] c_sizes_set = 520'h0; // @[Monitor.scala:741:34] wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34] wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34] wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = io_in_a_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31] wire _source_ok_T_27 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31] wire _source_ok_T_28 = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_29 = _source_ok_T_28 \| _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_30 = _source_ok_T_29 \| _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_31 = _source_ok_T_30 \| _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_32 = _source_ok_T_31 \| _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_33 = _source_ok_T_32 \| _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_33 \| _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_34 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_34; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_35 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_41 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_47 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_53 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_36 = _source_ok_T_35 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_38 = _source_ok_T_36; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_40; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_42 = _source_ok_T_41 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_44 = _source_ok_T_42; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_46; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_48 = _source_ok_T_47 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_50 = _source_ok_T_48; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_52; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_54 = _source_ok_T_53 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_56 = _source_ok_T_54; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_58 = _source_ok_T_56; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_58; // @[Parameters.scala:1138:31] wire _source_ok_T_59 = io_in_d_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_59; // @[Parameters.scala:1138:31] wire _source_ok_T_60 = io_in_d_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_60; // @[Parameters.scala:1138:31] wire _source_ok_T_61 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_61; // @[Parameters.scala:1138:31] wire _source_ok_T_62 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_63 = _source_ok_T_62 \| _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_64 = _source_ok_T_63 \| _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_65 = _source_ok_T_64 \| _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_66 = _source_ok_T_65 \| _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_67 = _source_ok_T_66 \| _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_67 \| _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _T_1436 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1436; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1436; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1509 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1509; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1509; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1509; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [519:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [64:0] a_set; // @[Monitor.scala:626:34] wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [519:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [9:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [519:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [519:0] _a_size_lookup_T_6 = {512'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [519:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[519:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [127:0] _GEN_3 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35] wire [127:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1362 = _T_1436 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1362 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1362 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1362 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [9:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1362 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [9:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [1027:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1362 ? _a_sizes_set_T_1[519:0] : 520'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [64:0] d_clr; // @[Monitor.scala:664:34] wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [519:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1408 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1408 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1377 = _T_1509 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1377 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1377 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [1038:0] _d_sizes_clr_T_5 = 1039'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1377 ? _d_sizes_clr_T_5[519:0] : 520'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [64:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [259:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [519:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [519:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [519:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [64:0] inflight_1; // @[Monitor.scala:726:35] wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [519:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [519:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [519:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [519:0] _c_size_lookup_T_6 = {512'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [519:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[519:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [64:0] d_clr_1; // @[Monitor.scala:774:34] wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [519:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1480 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1480 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1462 = _T_1509 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1462 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1462 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [1038:0] _d_sizes_clr_T_11 = 1039'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1462 ? _d_sizes_clr_T_11[519:0] : 520'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113] wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [519:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [519:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module IntSyncSyncCrossingSink_n1x1_12 : output auto : { flip in : { sync : UInt<1>[1]}, out : UInt<1>[1]} wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset wire nodeIn : { sync : UInt<1>[1]} invalidate nodeIn.sync[0] wire nodeOut : UInt<1>[1] invalidate nodeOut[0] connect auto.out, nodeOut connect nodeIn, auto.in connect nodeOut, nodeIn.sync	module IntSyncSyncCrossingSink_n1x1_12(); // @[Crossing.scala:96:9] wire auto_in_sync_0 = 1'h0; // @[Crossing.scala:96:9] wire auto_out_0 = 1'h0; // @[Crossing.scala:96:9] wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire nodeIn_sync_0 = 1'h0; // @[MixedNode.scala:551:17] wire nodeOut_0 = 1'h0; // @[MixedNode.scala:542:17] endmodule
Generate the Verilog code corresponding to this FIRRTL code module BranchDecode_1 : input clock : Clock input reset : Reset output io : { flip inst : UInt<32>, flip pc : UInt<40>, out : { is_ret : UInt<1>, is_call : UInt<1>, target : UInt<40>, cfi_type : UInt<3>, sfb_offset : { valid : UInt<1>, bits : UInt<6>}, shadowable : UInt<1>}} wire bpd_csignals_decoded_plaInput : UInt<32> node bpd_csignals_decoded_invInputs = not(bpd_csignals_decoded_plaInput) wire bpd_csignals_decoded : UInt<5> node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0 = bits(bpd_csignals_decoded_plaInput, 0, 0) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1 = bits(bpd_csignals_decoded_plaInput, 1, 1) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2 = bits(bpd_csignals_decoded_invInputs, 2, 2) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3 = bits(bpd_csignals_decoded_invInputs, 3, 3) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4 = bits(bpd_csignals_decoded_plaInput, 4, 4) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5 = bits(bpd_csignals_decoded_invInputs, 5, 5) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6 = bits(bpd_csignals_decoded_invInputs, 6, 6) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7 = bits(bpd_csignals_decoded_invInputs, 12, 12) node bpd_csignals_decoded_andMatrixOutputs_lo_lo = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7) node bpd_csignals_decoded_andMatrixOutputs_lo_hi = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5) node bpd_csignals_decoded_andMatrixOutputs_lo = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi, bpd_csignals_decoded_andMatrixOutputs_lo_lo) node bpd_csignals_decoded_andMatrixOutputs_hi_lo = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3) node bpd_csignals_decoded_andMatrixOutputs_hi_hi = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1) node bpd_csignals_decoded_andMatrixOutputs_hi = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi, bpd_csignals_decoded_andMatrixOutputs_hi_lo) node _bpd_csignals_decoded_andMatrixOutputs_T = cat(bpd_csignals_decoded_andMatrixOutputs_hi, bpd_csignals_decoded_andMatrixOutputs_lo) node bpd_csignals_decoded_andMatrixOutputs_5_2 = andr(_bpd_csignals_decoded_andMatrixOutputs_T) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_1 = bits(bpd_csignals_decoded_plaInput, 0, 0) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_1 = bits(bpd_csignals_decoded_plaInput, 1, 1) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_1 = bits(bpd_csignals_decoded_invInputs, 2, 2) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_1 = bits(bpd_csignals_decoded_plaInput, 4, 4) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_1 = bits(bpd_csignals_decoded_invInputs, 5, 5) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_1 = bits(bpd_csignals_decoded_invInputs, 6, 6) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_1 = bits(bpd_csignals_decoded_invInputs, 12, 12) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_1 = bits(bpd_csignals_decoded_invInputs, 13, 13) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8 = bits(bpd_csignals_decoded_invInputs, 14, 14) node bpd_csignals_decoded_andMatrixOutputs_lo_lo_1 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_1 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_1) node bpd_csignals_decoded_andMatrixOutputs_lo_1 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_1, bpd_csignals_decoded_andMatrixOutputs_lo_lo_1) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_1 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_1) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_1) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_1 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_1) node bpd_csignals_decoded_andMatrixOutputs_hi_1 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_1, bpd_csignals_decoded_andMatrixOutputs_hi_lo_1) node _bpd_csignals_decoded_andMatrixOutputs_T_1 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_1, bpd_csignals_decoded_andMatrixOutputs_lo_1) node bpd_csignals_decoded_andMatrixOutputs_9_2 = andr(_bpd_csignals_decoded_andMatrixOutputs_T_1) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_2 = bits(bpd_csignals_decoded_plaInput, 0, 0) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_2 = bits(bpd_csignals_decoded_plaInput, 1, 1) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_2 = bits(bpd_csignals_decoded_invInputs, 2, 2) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_2 = bits(bpd_csignals_decoded_plaInput, 4, 4) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_2 = bits(bpd_csignals_decoded_plaInput, 5, 5) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_2 = bits(bpd_csignals_decoded_invInputs, 6, 6) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_2 = bits(bpd_csignals_decoded_invInputs, 12, 12) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_2 = bits(bpd_csignals_decoded_invInputs, 13, 13) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_1 = bits(bpd_csignals_decoded_invInputs, 14, 14) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9 = bits(bpd_csignals_decoded_invInputs, 25, 25) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10 = bits(bpd_csignals_decoded_invInputs, 26, 26) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11 = bits(bpd_csignals_decoded_invInputs, 27, 27) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12 = bits(bpd_csignals_decoded_invInputs, 28, 28) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13 = bits(bpd_csignals_decoded_invInputs, 29, 29) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14 = bits(bpd_csignals_decoded_invInputs, 31, 31) node bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13) node bpd_csignals_decoded_andMatrixOutputs_lo_lo_2 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_2 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo) node bpd_csignals_decoded_andMatrixOutputs_lo_2 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_2, bpd_csignals_decoded_andMatrixOutputs_lo_lo_2) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_2) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_2) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_2 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_2) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_1 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_2) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_2 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_1, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo) node bpd_csignals_decoded_andMatrixOutputs_hi_2 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_2, bpd_csignals_decoded_andMatrixOutputs_hi_lo_2) node _bpd_csignals_decoded_andMatrixOutputs_T_2 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_2, bpd_csignals_decoded_andMatrixOutputs_lo_2) node bpd_csignals_decoded_andMatrixOutputs_14_2 = andr(_bpd_csignals_decoded_andMatrixOutputs_T_2) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_3 = bits(bpd_csignals_decoded_plaInput, 0, 0) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_3 = bits(bpd_csignals_decoded_plaInput, 1, 1) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_3 = bits(bpd_csignals_decoded_invInputs, 2, 2) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_3 = bits(bpd_csignals_decoded_invInputs, 3, 3) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_3 = bits(bpd_csignals_decoded_plaInput, 4, 4) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_3 = bits(bpd_csignals_decoded_plaInput, 5, 5) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_3 = bits(bpd_csignals_decoded_invInputs, 6, 6) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_3 = bits(bpd_csignals_decoded_invInputs, 25, 25) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_2 = bits(bpd_csignals_decoded_invInputs, 26, 26) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_1 = bits(bpd_csignals_decoded_invInputs, 27, 27) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_1 = bits(bpd_csignals_decoded_invInputs, 28, 28) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_1 = bits(bpd_csignals_decoded_invInputs, 29, 29) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_1 = bits(bpd_csignals_decoded_invInputs, 30, 30) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_1 = bits(bpd_csignals_decoded_invInputs, 31, 31) node bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_1 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_1) node bpd_csignals_decoded_andMatrixOutputs_lo_lo_3 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_1) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_1 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_1) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_1 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_2) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_3 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_1, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_1) node bpd_csignals_decoded_andMatrixOutputs_lo_3 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_3, bpd_csignals_decoded_andMatrixOutputs_lo_lo_3) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_1 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_3) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_3 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_3) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_1 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_3) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_2 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_3) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_3 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_2, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_1) node bpd_csignals_decoded_andMatrixOutputs_hi_3 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_3, bpd_csignals_decoded_andMatrixOutputs_hi_lo_3) node _bpd_csignals_decoded_andMatrixOutputs_T_3 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_3, bpd_csignals_decoded_andMatrixOutputs_lo_3) node bpd_csignals_decoded_andMatrixOutputs_0_2 = andr(_bpd_csignals_decoded_andMatrixOutputs_T_3) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_4 = bits(bpd_csignals_decoded_plaInput, 0, 0) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_4 = bits(bpd_csignals_decoded_plaInput, 1, 1) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_4 = bits(bpd_csignals_decoded_invInputs, 2, 2) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_4 = bits(bpd_csignals_decoded_plaInput, 4, 4) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_4 = bits(bpd_csignals_decoded_plaInput, 5, 5) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_4 = bits(bpd_csignals_decoded_invInputs, 6, 6) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_4 = bits(bpd_csignals_decoded_invInputs, 13, 13) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_4 = bits(bpd_csignals_decoded_invInputs, 14, 14) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_3 = bits(bpd_csignals_decoded_invInputs, 25, 25) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_2 = bits(bpd_csignals_decoded_invInputs, 26, 26) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_2 = bits(bpd_csignals_decoded_invInputs, 27, 27) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_2 = bits(bpd_csignals_decoded_invInputs, 28, 28) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_2 = bits(bpd_csignals_decoded_invInputs, 29, 29) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_2 = bits(bpd_csignals_decoded_invInputs, 30, 30) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_1 = bits(bpd_csignals_decoded_invInputs, 31, 31) node bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_2 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_2) node bpd_csignals_decoded_andMatrixOutputs_lo_lo_4 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_1) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_2 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_2) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_2 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_2) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_4 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_2, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_2) node bpd_csignals_decoded_andMatrixOutputs_lo_4 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_4, bpd_csignals_decoded_andMatrixOutputs_lo_lo_4) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_1 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_4) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_2 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_4) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_4 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_2, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_1) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_2 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_4) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_3 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_4) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_4 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_3, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_2) node bpd_csignals_decoded_andMatrixOutputs_hi_4 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_4, bpd_csignals_decoded_andMatrixOutputs_hi_lo_4) node _bpd_csignals_decoded_andMatrixOutputs_T_4 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_4, bpd_csignals_decoded_andMatrixOutputs_lo_4) node bpd_csignals_decoded_andMatrixOutputs_2_2 = andr(_bpd_csignals_decoded_andMatrixOutputs_T_4) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_5 = bits(bpd_csignals_decoded_plaInput, 0, 0) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_5 = bits(bpd_csignals_decoded_plaInput, 1, 1) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_5 = bits(bpd_csignals_decoded_plaInput, 2, 2) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_5 = bits(bpd_csignals_decoded_invInputs, 3, 3) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_5 = bits(bpd_csignals_decoded_plaInput, 4, 4) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_5 = bits(bpd_csignals_decoded_plaInput, 5, 5) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_5 = bits(bpd_csignals_decoded_invInputs, 6, 6) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_5 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_5) node bpd_csignals_decoded_andMatrixOutputs_lo_5 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_5) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_5 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_5) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_5 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_5) node bpd_csignals_decoded_andMatrixOutputs_hi_5 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_5, bpd_csignals_decoded_andMatrixOutputs_hi_lo_5) node _bpd_csignals_decoded_andMatrixOutputs_T_5 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_5, bpd_csignals_decoded_andMatrixOutputs_lo_5) node bpd_csignals_decoded_andMatrixOutputs_12_2 = andr(_bpd_csignals_decoded_andMatrixOutputs_T_5) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_6 = bits(bpd_csignals_decoded_plaInput, 0, 0) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_6 = bits(bpd_csignals_decoded_plaInput, 1, 1) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_6 = bits(bpd_csignals_decoded_invInputs, 2, 2) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_6 = bits(bpd_csignals_decoded_invInputs, 3, 3) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_6 = bits(bpd_csignals_decoded_invInputs, 4, 4) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_6 = bits(bpd_csignals_decoded_plaInput, 5, 5) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_6 = bits(bpd_csignals_decoded_plaInput, 6, 6) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_5 = bits(bpd_csignals_decoded_invInputs, 13, 13) node bpd_csignals_decoded_andMatrixOutputs_lo_lo_5 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_5) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_6 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_6) node bpd_csignals_decoded_andMatrixOutputs_lo_6 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_6, bpd_csignals_decoded_andMatrixOutputs_lo_lo_5) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_6 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_6) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_6 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_6) node bpd_csignals_decoded_andMatrixOutputs_hi_6 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_6, bpd_csignals_decoded_andMatrixOutputs_hi_lo_6) node _bpd_csignals_decoded_andMatrixOutputs_T_6 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_6, bpd_csignals_decoded_andMatrixOutputs_lo_6) node bpd_csignals_decoded_andMatrixOutputs_6_2 = andr(_bpd_csignals_decoded_andMatrixOutputs_T_6) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_7 = bits(bpd_csignals_decoded_plaInput, 0, 0) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_7 = bits(bpd_csignals_decoded_plaInput, 1, 1) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_7 = bits(bpd_csignals_decoded_plaInput, 2, 2) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_7 = bits(bpd_csignals_decoded_invInputs, 3, 3) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_7 = bits(bpd_csignals_decoded_invInputs, 4, 4) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_7 = bits(bpd_csignals_decoded_plaInput, 5, 5) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_7 = bits(bpd_csignals_decoded_plaInput, 6, 6) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_6 = bits(bpd_csignals_decoded_invInputs, 12, 12) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_4 = bits(bpd_csignals_decoded_invInputs, 13, 13) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_3 = bits(bpd_csignals_decoded_invInputs, 14, 14) node bpd_csignals_decoded_andMatrixOutputs_lo_lo_6 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_3) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_3 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_7) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_7 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_6) node bpd_csignals_decoded_andMatrixOutputs_lo_7 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_7, bpd_csignals_decoded_andMatrixOutputs_lo_lo_6) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_7 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_7) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_4 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_7) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_7 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_7) node bpd_csignals_decoded_andMatrixOutputs_hi_7 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_7, bpd_csignals_decoded_andMatrixOutputs_hi_lo_7) node _bpd_csignals_decoded_andMatrixOutputs_T_7 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_7, bpd_csignals_decoded_andMatrixOutputs_lo_7) node bpd_csignals_decoded_andMatrixOutputs_15_2 = andr(_bpd_csignals_decoded_andMatrixOutputs_T_7) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_8 = bits(bpd_csignals_decoded_plaInput, 0, 0) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_8 = bits(bpd_csignals_decoded_plaInput, 1, 1) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_8 = bits(bpd_csignals_decoded_plaInput, 2, 2) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_8 = bits(bpd_csignals_decoded_plaInput, 3, 3) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_8 = bits(bpd_csignals_decoded_invInputs, 4, 4) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_8 = bits(bpd_csignals_decoded_plaInput, 5, 5) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_8 = bits(bpd_csignals_decoded_plaInput, 6, 6) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_8 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_8, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_8) node bpd_csignals_decoded_andMatrixOutputs_lo_8 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_8, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_8) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_8 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_8, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_8) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_8 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_8, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_8) node bpd_csignals_decoded_andMatrixOutputs_hi_8 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_8, bpd_csignals_decoded_andMatrixOutputs_hi_lo_8) node _bpd_csignals_decoded_andMatrixOutputs_T_8 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_8, bpd_csignals_decoded_andMatrixOutputs_lo_8) node bpd_csignals_decoded_andMatrixOutputs_11_2 = andr(_bpd_csignals_decoded_andMatrixOutputs_T_8) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_9 = bits(bpd_csignals_decoded_plaInput, 0, 0) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_9 = bits(bpd_csignals_decoded_plaInput, 1, 1) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_9 = bits(bpd_csignals_decoded_invInputs, 2, 2) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_9 = bits(bpd_csignals_decoded_invInputs, 3, 3) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_9 = bits(bpd_csignals_decoded_plaInput, 4, 4) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_9 = bits(bpd_csignals_decoded_invInputs, 5, 5) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_9 = bits(bpd_csignals_decoded_invInputs, 6, 6) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_7 = bits(bpd_csignals_decoded_plaInput, 12, 12) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_5 = bits(bpd_csignals_decoded_invInputs, 13, 13) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_4 = bits(bpd_csignals_decoded_invInputs, 26, 26) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_3 = bits(bpd_csignals_decoded_invInputs, 27, 27) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_3 = bits(bpd_csignals_decoded_invInputs, 28, 28) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_3 = bits(bpd_csignals_decoded_invInputs, 29, 29) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_3 = bits(bpd_csignals_decoded_invInputs, 30, 30) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_2 = bits(bpd_csignals_decoded_invInputs, 31, 31) node bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_3 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_3) node bpd_csignals_decoded_andMatrixOutputs_lo_lo_7 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_2) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_3 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_3) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_4 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_4) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_9 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_4, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_3) node bpd_csignals_decoded_andMatrixOutputs_lo_9 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_9, bpd_csignals_decoded_andMatrixOutputs_lo_lo_7) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_2 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_9, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_7) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_3 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_9, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_9) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_9 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_3, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_2) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_3 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_9, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_9) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_5 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_9, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_9) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_9 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_5, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_3) node bpd_csignals_decoded_andMatrixOutputs_hi_9 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_9, bpd_csignals_decoded_andMatrixOutputs_hi_lo_9) node _bpd_csignals_decoded_andMatrixOutputs_T_9 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_9, bpd_csignals_decoded_andMatrixOutputs_lo_9) node bpd_csignals_decoded_andMatrixOutputs_3_2 = andr(_bpd_csignals_decoded_andMatrixOutputs_T_9) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_10 = bits(bpd_csignals_decoded_plaInput, 0, 0) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_10 = bits(bpd_csignals_decoded_plaInput, 1, 1) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_10 = bits(bpd_csignals_decoded_invInputs, 2, 2) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_10 = bits(bpd_csignals_decoded_plaInput, 3, 3) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_10 = bits(bpd_csignals_decoded_plaInput, 4, 4) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_10 = bits(bpd_csignals_decoded_invInputs, 6, 6) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_10 = bits(bpd_csignals_decoded_plaInput, 12, 12) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_8 = bits(bpd_csignals_decoded_invInputs, 13, 13) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_6 = bits(bpd_csignals_decoded_invInputs, 25, 25) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_5 = bits(bpd_csignals_decoded_invInputs, 26, 26) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_4 = bits(bpd_csignals_decoded_invInputs, 27, 27) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_4 = bits(bpd_csignals_decoded_invInputs, 28, 28) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_4 = bits(bpd_csignals_decoded_invInputs, 29, 29) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_4 = bits(bpd_csignals_decoded_invInputs, 30, 30) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_3 = bits(bpd_csignals_decoded_invInputs, 31, 31) node bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_4 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_4) node bpd_csignals_decoded_andMatrixOutputs_lo_lo_8 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_3) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_4 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_4) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_5 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_5) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_10 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_5, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_4) node bpd_csignals_decoded_andMatrixOutputs_lo_10 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_10, bpd_csignals_decoded_andMatrixOutputs_lo_lo_8) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_3 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_10, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_8) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_4 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_10, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_10) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_10 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_4, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_3) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_4 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_10, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_10) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_6 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_10, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_10) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_10 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_6, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_4) node bpd_csignals_decoded_andMatrixOutputs_hi_10 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_10, bpd_csignals_decoded_andMatrixOutputs_hi_lo_10) node _bpd_csignals_decoded_andMatrixOutputs_T_10 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_10, bpd_csignals_decoded_andMatrixOutputs_lo_10) node bpd_csignals_decoded_andMatrixOutputs_7_2 = andr(_bpd_csignals_decoded_andMatrixOutputs_T_10) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_11 = bits(bpd_csignals_decoded_plaInput, 0, 0) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_11 = bits(bpd_csignals_decoded_plaInput, 1, 1) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_11 = bits(bpd_csignals_decoded_invInputs, 2, 2) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_11 = bits(bpd_csignals_decoded_invInputs, 3, 3) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_11 = bits(bpd_csignals_decoded_plaInput, 4, 4) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_11 = bits(bpd_csignals_decoded_invInputs, 5, 5) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_11 = bits(bpd_csignals_decoded_invInputs, 6, 6) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_9 = bits(bpd_csignals_decoded_plaInput, 13, 13) node bpd_csignals_decoded_andMatrixOutputs_lo_lo_9 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_11, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_9) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_11 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_11, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_11) node bpd_csignals_decoded_andMatrixOutputs_lo_11 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_11, bpd_csignals_decoded_andMatrixOutputs_lo_lo_9) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_11 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_11, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_11) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_11 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_11, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_11) node bpd_csignals_decoded_andMatrixOutputs_hi_11 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_11, bpd_csignals_decoded_andMatrixOutputs_hi_lo_11) node _bpd_csignals_decoded_andMatrixOutputs_T_11 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_11, bpd_csignals_decoded_andMatrixOutputs_lo_11) node bpd_csignals_decoded_andMatrixOutputs_1_2 = andr(_bpd_csignals_decoded_andMatrixOutputs_T_11) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_12 = bits(bpd_csignals_decoded_plaInput, 0, 0) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_12 = bits(bpd_csignals_decoded_plaInput, 1, 1) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_12 = bits(bpd_csignals_decoded_invInputs, 2, 2) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_12 = bits(bpd_csignals_decoded_invInputs, 3, 3) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_12 = bits(bpd_csignals_decoded_invInputs, 4, 4) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_12 = bits(bpd_csignals_decoded_plaInput, 5, 5) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_12 = bits(bpd_csignals_decoded_plaInput, 6, 6) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_10 = bits(bpd_csignals_decoded_plaInput, 14, 14) node bpd_csignals_decoded_andMatrixOutputs_lo_lo_10 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_12, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_10) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_12 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_12, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_12) node bpd_csignals_decoded_andMatrixOutputs_lo_12 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_12, bpd_csignals_decoded_andMatrixOutputs_lo_lo_10) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_12 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_12, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_12) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_12 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_12, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_12) node bpd_csignals_decoded_andMatrixOutputs_hi_12 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_12, bpd_csignals_decoded_andMatrixOutputs_hi_lo_12) node _bpd_csignals_decoded_andMatrixOutputs_T_12 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_12, bpd_csignals_decoded_andMatrixOutputs_lo_12) node bpd_csignals_decoded_andMatrixOutputs_13_2 = andr(_bpd_csignals_decoded_andMatrixOutputs_T_12) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_13 = bits(bpd_csignals_decoded_plaInput, 0, 0) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_13 = bits(bpd_csignals_decoded_plaInput, 1, 1) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_13 = bits(bpd_csignals_decoded_invInputs, 2, 2) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_13 = bits(bpd_csignals_decoded_invInputs, 3, 3) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_13 = bits(bpd_csignals_decoded_plaInput, 4, 4) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_13 = bits(bpd_csignals_decoded_invInputs, 5, 5) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_13 = bits(bpd_csignals_decoded_invInputs, 6, 6) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_11 = bits(bpd_csignals_decoded_plaInput, 12, 12) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_7 = bits(bpd_csignals_decoded_invInputs, 13, 13) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_6 = bits(bpd_csignals_decoded_plaInput, 14, 14) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_5 = bits(bpd_csignals_decoded_invInputs, 26, 26) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_5 = bits(bpd_csignals_decoded_invInputs, 27, 27) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_5 = bits(bpd_csignals_decoded_invInputs, 28, 28) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_5 = bits(bpd_csignals_decoded_invInputs, 29, 29) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_4 = bits(bpd_csignals_decoded_invInputs, 31, 31) node bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_5 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_5) node bpd_csignals_decoded_andMatrixOutputs_lo_lo_11 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_4) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_5 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_5) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_6 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_6) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_13 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_6, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_5) node bpd_csignals_decoded_andMatrixOutputs_lo_13 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_13, bpd_csignals_decoded_andMatrixOutputs_lo_lo_11) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_4 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_13, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_11) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_5 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_13, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_13) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_13 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_5, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_4) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_5 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_13, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_13) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_7 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_13, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_13) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_13 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_7, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_5) node bpd_csignals_decoded_andMatrixOutputs_hi_13 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_13, bpd_csignals_decoded_andMatrixOutputs_hi_lo_13) node _bpd_csignals_decoded_andMatrixOutputs_T_13 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_13, bpd_csignals_decoded_andMatrixOutputs_lo_13) node bpd_csignals_decoded_andMatrixOutputs_4_2 = andr(_bpd_csignals_decoded_andMatrixOutputs_T_13) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_14 = bits(bpd_csignals_decoded_plaInput, 0, 0) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_14 = bits(bpd_csignals_decoded_plaInput, 1, 1) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_14 = bits(bpd_csignals_decoded_invInputs, 2, 2) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_14 = bits(bpd_csignals_decoded_plaInput, 3, 3) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_14 = bits(bpd_csignals_decoded_plaInput, 4, 4) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_14 = bits(bpd_csignals_decoded_invInputs, 6, 6) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_14 = bits(bpd_csignals_decoded_plaInput, 12, 12) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_12 = bits(bpd_csignals_decoded_invInputs, 13, 13) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_8 = bits(bpd_csignals_decoded_plaInput, 14, 14) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_7 = bits(bpd_csignals_decoded_invInputs, 25, 25) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_6 = bits(bpd_csignals_decoded_invInputs, 26, 26) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_6 = bits(bpd_csignals_decoded_invInputs, 27, 27) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_6 = bits(bpd_csignals_decoded_invInputs, 28, 28) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_6 = bits(bpd_csignals_decoded_invInputs, 29, 29) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_5 = bits(bpd_csignals_decoded_invInputs, 31, 31) node bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_6 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_6) node bpd_csignals_decoded_andMatrixOutputs_lo_lo_12 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_5) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_6 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_6) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_7 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_8, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_7) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_14 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_7, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_6) node bpd_csignals_decoded_andMatrixOutputs_lo_14 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_14, bpd_csignals_decoded_andMatrixOutputs_lo_lo_12) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_5 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_14, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_12) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_6 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_14, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_14) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_14 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_6, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_5) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_6 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_14, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_14) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_8 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_14, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_14) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_14 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_8, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_6) node bpd_csignals_decoded_andMatrixOutputs_hi_14 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_14, bpd_csignals_decoded_andMatrixOutputs_hi_lo_14) node _bpd_csignals_decoded_andMatrixOutputs_T_14 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_14, bpd_csignals_decoded_andMatrixOutputs_lo_14) node bpd_csignals_decoded_andMatrixOutputs_8_2 = andr(_bpd_csignals_decoded_andMatrixOutputs_T_14) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_15 = bits(bpd_csignals_decoded_plaInput, 0, 0) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_15 = bits(bpd_csignals_decoded_plaInput, 1, 1) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_15 = bits(bpd_csignals_decoded_invInputs, 2, 2) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_15 = bits(bpd_csignals_decoded_plaInput, 4, 4) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_15 = bits(bpd_csignals_decoded_plaInput, 5, 5) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_15 = bits(bpd_csignals_decoded_invInputs, 6, 6) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_15 = bits(bpd_csignals_decoded_plaInput, 12, 12) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_13 = bits(bpd_csignals_decoded_invInputs, 13, 13) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_9 = bits(bpd_csignals_decoded_plaInput, 14, 14) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_8 = bits(bpd_csignals_decoded_invInputs, 25, 25) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_7 = bits(bpd_csignals_decoded_invInputs, 26, 26) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_7 = bits(bpd_csignals_decoded_invInputs, 27, 27) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_7 = bits(bpd_csignals_decoded_invInputs, 28, 28) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_7 = bits(bpd_csignals_decoded_invInputs, 29, 29) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_6 = bits(bpd_csignals_decoded_invInputs, 31, 31) node bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_7 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_7) node bpd_csignals_decoded_andMatrixOutputs_lo_lo_13 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_6) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_7 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_7) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_8 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_9, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_8) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_15 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_8, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_7) node bpd_csignals_decoded_andMatrixOutputs_lo_15 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_15, bpd_csignals_decoded_andMatrixOutputs_lo_lo_13) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_6 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_15, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_13) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_7 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_15, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_15) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_15 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_7, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_6) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_7 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_15, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_15) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_9 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_15, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_15) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_15 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_9, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_7) node bpd_csignals_decoded_andMatrixOutputs_hi_15 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_15, bpd_csignals_decoded_andMatrixOutputs_hi_lo_15) node _bpd_csignals_decoded_andMatrixOutputs_T_15 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_15, bpd_csignals_decoded_andMatrixOutputs_lo_15) node bpd_csignals_decoded_andMatrixOutputs_10_2 = andr(_bpd_csignals_decoded_andMatrixOutputs_T_15) node bpd_csignals_decoded_orMatrixOutputs_lo = cat(bpd_csignals_decoded_andMatrixOutputs_2_2, bpd_csignals_decoded_andMatrixOutputs_10_2) node bpd_csignals_decoded_orMatrixOutputs_hi = cat(bpd_csignals_decoded_andMatrixOutputs_14_2, bpd_csignals_decoded_andMatrixOutputs_0_2) node _bpd_csignals_decoded_orMatrixOutputs_T = cat(bpd_csignals_decoded_orMatrixOutputs_hi, bpd_csignals_decoded_orMatrixOutputs_lo) node _bpd_csignals_decoded_orMatrixOutputs_T_1 = orr(_bpd_csignals_decoded_orMatrixOutputs_T) node bpd_csignals_decoded_orMatrixOutputs_lo_lo = cat(bpd_csignals_decoded_andMatrixOutputs_8_2, bpd_csignals_decoded_andMatrixOutputs_10_2) node bpd_csignals_decoded_orMatrixOutputs_lo_hi_hi = cat(bpd_csignals_decoded_andMatrixOutputs_7_2, bpd_csignals_decoded_andMatrixOutputs_1_2) node bpd_csignals_decoded_orMatrixOutputs_lo_hi = cat(bpd_csignals_decoded_orMatrixOutputs_lo_hi_hi, bpd_csignals_decoded_andMatrixOutputs_4_2) node bpd_csignals_decoded_orMatrixOutputs_lo_1 = cat(bpd_csignals_decoded_orMatrixOutputs_lo_hi, bpd_csignals_decoded_orMatrixOutputs_lo_lo) node bpd_csignals_decoded_orMatrixOutputs_hi_lo_hi = cat(bpd_csignals_decoded_andMatrixOutputs_0_2, bpd_csignals_decoded_andMatrixOutputs_12_2) node bpd_csignals_decoded_orMatrixOutputs_hi_lo = cat(bpd_csignals_decoded_orMatrixOutputs_hi_lo_hi, bpd_csignals_decoded_andMatrixOutputs_3_2) node bpd_csignals_decoded_orMatrixOutputs_hi_hi_hi = cat(bpd_csignals_decoded_andMatrixOutputs_5_2, bpd_csignals_decoded_andMatrixOutputs_9_2) node bpd_csignals_decoded_orMatrixOutputs_hi_hi = cat(bpd_csignals_decoded_orMatrixOutputs_hi_hi_hi, bpd_csignals_decoded_andMatrixOutputs_14_2) node bpd_csignals_decoded_orMatrixOutputs_hi_1 = cat(bpd_csignals_decoded_orMatrixOutputs_hi_hi, bpd_csignals_decoded_orMatrixOutputs_hi_lo) node _bpd_csignals_decoded_orMatrixOutputs_T_2 = cat(bpd_csignals_decoded_orMatrixOutputs_hi_1, bpd_csignals_decoded_orMatrixOutputs_lo_1) node _bpd_csignals_decoded_orMatrixOutputs_T_3 = orr(_bpd_csignals_decoded_orMatrixOutputs_T_2) node _bpd_csignals_decoded_orMatrixOutputs_T_4 = orr(bpd_csignals_decoded_andMatrixOutputs_15_2) node _bpd_csignals_decoded_orMatrixOutputs_T_5 = orr(bpd_csignals_decoded_andMatrixOutputs_11_2) node _bpd_csignals_decoded_orMatrixOutputs_T_6 = cat(bpd_csignals_decoded_andMatrixOutputs_6_2, bpd_csignals_decoded_andMatrixOutputs_13_2) node _bpd_csignals_decoded_orMatrixOutputs_T_7 = orr(_bpd_csignals_decoded_orMatrixOutputs_T_6) node bpd_csignals_decoded_orMatrixOutputs_lo_2 = cat(_bpd_csignals_decoded_orMatrixOutputs_T_3, _bpd_csignals_decoded_orMatrixOutputs_T_1) node bpd_csignals_decoded_orMatrixOutputs_hi_hi_1 = cat(_bpd_csignals_decoded_orMatrixOutputs_T_7, _bpd_csignals_decoded_orMatrixOutputs_T_5) node bpd_csignals_decoded_orMatrixOutputs_hi_2 = cat(bpd_csignals_decoded_orMatrixOutputs_hi_hi_1, _bpd_csignals_decoded_orMatrixOutputs_T_4) node bpd_csignals_decoded_orMatrixOutputs = cat(bpd_csignals_decoded_orMatrixOutputs_hi_2, bpd_csignals_decoded_orMatrixOutputs_lo_2) node _bpd_csignals_decoded_invMatrixOutputs_T = bits(bpd_csignals_decoded_orMatrixOutputs, 0, 0) node _bpd_csignals_decoded_invMatrixOutputs_T_1 = bits(bpd_csignals_decoded_orMatrixOutputs, 1, 1) node _bpd_csignals_decoded_invMatrixOutputs_T_2 = bits(bpd_csignals_decoded_orMatrixOutputs, 2, 2) node _bpd_csignals_decoded_invMatrixOutputs_T_3 = bits(bpd_csignals_decoded_orMatrixOutputs, 3, 3) node _bpd_csignals_decoded_invMatrixOutputs_T_4 = bits(bpd_csignals_decoded_orMatrixOutputs, 4, 4) node bpd_csignals_decoded_invMatrixOutputs_lo = cat(_bpd_csignals_decoded_invMatrixOutputs_T_1, _bpd_csignals_decoded_invMatrixOutputs_T) node bpd_csignals_decoded_invMatrixOutputs_hi_hi = cat(_bpd_csignals_decoded_invMatrixOutputs_T_4, _bpd_csignals_decoded_invMatrixOutputs_T_3) node bpd_csignals_decoded_invMatrixOutputs_hi = cat(bpd_csignals_decoded_invMatrixOutputs_hi_hi, _bpd_csignals_decoded_invMatrixOutputs_T_2) node bpd_csignals_decoded_invMatrixOutputs = cat(bpd_csignals_decoded_invMatrixOutputs_hi, bpd_csignals_decoded_invMatrixOutputs_lo) connect bpd_csignals_decoded, bpd_csignals_decoded_invMatrixOutputs connect bpd_csignals_decoded_plaInput, io.inst node bpd_csignals_0 = bits(bpd_csignals_decoded, 4, 4) node bpd_csignals_1 = bits(bpd_csignals_decoded, 3, 3) node bpd_csignals_2 = bits(bpd_csignals_decoded, 2, 2) node bpd_csignals_3 = bits(bpd_csignals_decoded, 1, 1) node bpd_csignals_4 = bits(bpd_csignals_decoded, 0, 0) node cs_is_br = bits(bpd_csignals_0, 0, 0) node cs_is_jal = bits(bpd_csignals_1, 0, 0) node cs_is_jalr = bits(bpd_csignals_2, 0, 0) node cs_is_shadowable = bits(bpd_csignals_3, 0, 0) node cs_has_rs2 = bits(bpd_csignals_4, 0, 0) node _io_out_is_call_T = or(cs_is_jal, cs_is_jalr) node _io_out_is_call_T_1 = bits(io.inst, 11, 7) node _io_out_is_call_T_2 = eq(_io_out_is_call_T_1, UInt<1>(0h1)) node _io_out_is_call_T_3 = and(_io_out_is_call_T, _io_out_is_call_T_2) connect io.out.is_call, _io_out_is_call_T_3 node _io_out_is_ret_T = bits(io.inst, 19, 15) node _io_out_is_ret_T_1 = and(_io_out_is_ret_T, UInt<5>(0h1b)) node _io_out_is_ret_T_2 = eq(UInt<1>(0h1), _io_out_is_ret_T_1) node _io_out_is_ret_T_3 = and(cs_is_jalr, _io_out_is_ret_T_2) node _io_out_is_ret_T_4 = bits(io.inst, 11, 7) node _io_out_is_ret_T_5 = eq(_io_out_is_ret_T_4, UInt<1>(0h0)) node _io_out_is_ret_T_6 = and(_io_out_is_ret_T_3, _io_out_is_ret_T_5) connect io.out.is_ret, _io_out_is_ret_T_6 node _io_out_target_b_imm32_T = bits(io.inst, 31, 31) node _io_out_target_b_imm32_T_1 = mux(_io_out_target_b_imm32_T, UInt<20>(0hfffff), UInt<20>(0h0)) node _io_out_target_b_imm32_T_2 = bits(io.inst, 7, 7) node _io_out_target_b_imm32_T_3 = bits(io.inst, 30, 25) node _io_out_target_b_imm32_T_4 = bits(io.inst, 11, 8) node io_out_target_b_imm32_lo = cat(_io_out_target_b_imm32_T_4, UInt<1>(0h0)) node io_out_target_b_imm32_hi_hi = cat(_io_out_target_b_imm32_T_1, _io_out_target_b_imm32_T_2) node io_out_target_b_imm32_hi = cat(io_out_target_b_imm32_hi_hi, _io_out_target_b_imm32_T_3) node io_out_target_b_imm32 = cat(io_out_target_b_imm32_hi, io_out_target_b_imm32_lo) node _io_out_target_T = asSInt(io.pc) node _io_out_target_T_1 = asSInt(io_out_target_b_imm32) node _io_out_target_T_2 = add(_io_out_target_T, _io_out_target_T_1) node _io_out_target_T_3 = tail(_io_out_target_T_2, 1) node _io_out_target_T_4 = asSInt(_io_out_target_T_3) node _io_out_target_T_5 = and(_io_out_target_T_4, asSInt(UInt<2>(0h2))) node _io_out_target_T_6 = asSInt(_io_out_target_T_5) node _io_out_target_T_7 = asUInt(_io_out_target_T_6) node _io_out_target_j_imm32_T = bits(io.inst, 31, 31) node _io_out_target_j_imm32_T_1 = mux(_io_out_target_j_imm32_T, UInt<12>(0hfff), UInt<12>(0h0)) node _io_out_target_j_imm32_T_2 = bits(io.inst, 19, 12) node _io_out_target_j_imm32_T_3 = bits(io.inst, 20, 20) node _io_out_target_j_imm32_T_4 = bits(io.inst, 30, 25) node _io_out_target_j_imm32_T_5 = bits(io.inst, 24, 21) node io_out_target_j_imm32_lo_hi = cat(_io_out_target_j_imm32_T_4, _io_out_target_j_imm32_T_5) node io_out_target_j_imm32_lo = cat(io_out_target_j_imm32_lo_hi, UInt<1>(0h0)) node io_out_target_j_imm32_hi_hi = cat(_io_out_target_j_imm32_T_1, _io_out_target_j_imm32_T_2) node io_out_target_j_imm32_hi = cat(io_out_target_j_imm32_hi_hi, _io_out_target_j_imm32_T_3) node io_out_target_j_imm32 = cat(io_out_target_j_imm32_hi, io_out_target_j_imm32_lo) node _io_out_target_T_8 = asSInt(io.pc) node _io_out_target_T_9 = asSInt(io_out_target_j_imm32) node _io_out_target_T_10 = add(_io_out_target_T_8, _io_out_target_T_9) node _io_out_target_T_11 = tail(_io_out_target_T_10, 1) node _io_out_target_T_12 = asSInt(_io_out_target_T_11) node _io_out_target_T_13 = and(_io_out_target_T_12, asSInt(UInt<2>(0h2))) node _io_out_target_T_14 = asSInt(_io_out_target_T_13) node _io_out_target_T_15 = asUInt(_io_out_target_T_14) node _io_out_target_T_16 = mux(cs_is_br, _io_out_target_T_7, _io_out_target_T_15) connect io.out.target, _io_out_target_T_16 node _io_out_cfi_type_T = mux(cs_is_br, UInt<3>(0h1), UInt<3>(0h0)) node _io_out_cfi_type_T_1 = mux(cs_is_jal, UInt<3>(0h2), _io_out_cfi_type_T) node _io_out_cfi_type_T_2 = mux(cs_is_jalr, UInt<3>(0h3), _io_out_cfi_type_T_1) connect io.out.cfi_type, _io_out_cfi_type_T_2 node _br_offset_T = bits(io.inst, 7, 7) node _br_offset_T_1 = bits(io.inst, 30, 25) node _br_offset_T_2 = bits(io.inst, 11, 8) node br_offset_lo = cat(_br_offset_T_2, UInt<1>(0h0)) node br_offset_hi = cat(_br_offset_T, _br_offset_T_1) node br_offset = cat(br_offset_hi, br_offset_lo) node _io_out_sfb_offset_valid_T = bits(io.inst, 31, 31) node _io_out_sfb_offset_valid_T_1 = eq(_io_out_sfb_offset_valid_T, UInt<1>(0h0)) node _io_out_sfb_offset_valid_T_2 = and(cs_is_br, _io_out_sfb_offset_valid_T_1) node _io_out_sfb_offset_valid_T_3 = neq(br_offset, UInt<1>(0h0)) node _io_out_sfb_offset_valid_T_4 = and(_io_out_sfb_offset_valid_T_2, _io_out_sfb_offset_valid_T_3) node _io_out_sfb_offset_valid_T_5 = shr(br_offset, 6) node _io_out_sfb_offset_valid_T_6 = eq(_io_out_sfb_offset_valid_T_5, UInt<1>(0h0)) node _io_out_sfb_offset_valid_T_7 = and(_io_out_sfb_offset_valid_T_4, _io_out_sfb_offset_valid_T_6) connect io.out.sfb_offset.valid, _io_out_sfb_offset_valid_T_7 connect io.out.sfb_offset.bits, br_offset node _io_out_shadowable_T = eq(cs_has_rs2, UInt<1>(0h0)) node _io_out_shadowable_T_1 = bits(io.inst, 19, 15) node _io_out_shadowable_T_2 = bits(io.inst, 11, 7) node _io_out_shadowable_T_3 = eq(_io_out_shadowable_T_1, _io_out_shadowable_T_2) node _io_out_shadowable_T_4 = or(_io_out_shadowable_T, _io_out_shadowable_T_3) node _io_out_shadowable_T_5 = and(io.inst, UInt<32>(0hfe00707f)) node _io_out_shadowable_T_6 = eq(UInt<6>(0h33), _io_out_shadowable_T_5) node _io_out_shadowable_T_7 = bits(io.inst, 19, 15) node _io_out_shadowable_T_8 = eq(_io_out_shadowable_T_7, UInt<1>(0h0)) node _io_out_shadowable_T_9 = and(_io_out_shadowable_T_6, _io_out_shadowable_T_8) node _io_out_shadowable_T_10 = or(_io_out_shadowable_T_4, _io_out_shadowable_T_9) node _io_out_shadowable_T_11 = and(cs_is_shadowable, _io_out_shadowable_T_10) connect io.out.shadowable, _io_out_shadowable_T_11	module BranchDecode_1( // @[decode.scala:629:7] input clock, // @[decode.scala:629:7] input reset, // @[decode.scala:629:7] input [31:0] io_inst, // @[decode.scala:631:14] input [39:0] io_pc, // @[decode.scala:631:14] output io_out_is_ret, // @[decode.scala:631:14] output io_out_is_call, // @[decode.scala:631:14] output [39:0] io_out_target, // @[decode.scala:631:14] output [2:0] io_out_cfi_type, // @[decode.scala:631:14] output io_out_sfb_offset_valid, // @[decode.scala:631:14] output [5:0] io_out_sfb_offset_bits, // @[decode.scala:631:14] output io_out_shadowable // @[decode.scala:631:14] ); wire [31:0] io_inst_0 = io_inst; // @[decode.scala:629:7] wire [39:0] io_pc_0 = io_pc; // @[decode.scala:629:7] wire [31:0] bpd_csignals_decoded_plaInput = io_inst_0; // @[pla.scala:77:22] wire _io_out_is_ret_T_6; // @[decode.scala:701:72] wire [39:0] _io_out_target_T = io_pc_0; // @[decode.scala:629:7] wire [39:0] _io_out_target_T_8 = io_pc_0; // @[decode.scala:629:7] wire _io_out_is_call_T_3; // @[decode.scala:700:47] wire [39:0] _io_out_target_T_16; // @[decode.scala:703:23] wire [2:0] _io_out_cfi_type_T_2; // @[decode.scala:706:8] wire _io_out_sfb_offset_valid_T_7; // @[decode.scala:716:76] wire _io_out_shadowable_T_11; // @[decode.scala:718:41] wire io_out_sfb_offset_valid_0; // @[decode.scala:629:7] wire [5:0] io_out_sfb_offset_bits_0; // @[decode.scala:629:7] wire io_out_is_ret_0; // @[decode.scala:629:7] wire io_out_is_call_0; // @[decode.scala:629:7] wire [39:0] io_out_target_0; // @[decode.scala:629:7] wire [2:0] io_out_cfi_type_0; // @[decode.scala:629:7] wire io_out_shadowable_0; // @[decode.scala:629:7] wire [31:0] bpd_csignals_decoded_invInputs = ~bpd_csignals_decoded_plaInput; // @[pla.scala:77:22, :78:21] wire [4:0] bpd_csignals_decoded_invMatrixOutputs; // @[pla.scala:120:37] wire [4:0] bpd_csignals_decoded; // @[pla.scala:81:23] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_1 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_2 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_3 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_4 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_5 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_6 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_7 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_8 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_9 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_10 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_11 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_12 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_13 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_14 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_15 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_1 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_2 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_3 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_4 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_5 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_6 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_7 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_8 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_9 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_10 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_11 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_12 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_13 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_14 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_15 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_1 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_2 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_3 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_4 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_6 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_9 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_10 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_11 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_12 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_13 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_14 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_15 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3 = bpd_csignals_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_3 = bpd_csignals_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_5 = bpd_csignals_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_6 = bpd_csignals_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_7 = bpd_csignals_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_9 = bpd_csignals_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_11 = bpd_csignals_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_12 = bpd_csignals_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_13 = bpd_csignals_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_1 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_2 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_3 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_4 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_5 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_9 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_10 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_11 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_13 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_14 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_15 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5 = bpd_csignals_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_1 = bpd_csignals_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_9 = bpd_csignals_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_11 = bpd_csignals_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_13 = bpd_csignals_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_1 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_2 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_3 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_4 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_5 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_9 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_10 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_11 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_13 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_14 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_15 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7 = bpd_csignals_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_1 = bpd_csignals_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_2 = bpd_csignals_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_6 = bpd_csignals_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo = {bpd_csignals_decoded_andMatrixOutputs_lo_hi, bpd_csignals_decoded_andMatrixOutputs_lo_lo}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi = {bpd_csignals_decoded_andMatrixOutputs_hi_hi, bpd_csignals_decoded_andMatrixOutputs_hi_lo}; // @[pla.scala:98:53] wire [7:0] _bpd_csignals_decoded_andMatrixOutputs_T = {bpd_csignals_decoded_andMatrixOutputs_hi, bpd_csignals_decoded_andMatrixOutputs_lo}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_5_2 = &_bpd_csignals_decoded_andMatrixOutputs_T; // @[pla.scala:98:{53,70}] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_1 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_2 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_4 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_5 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_4 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_5 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_8 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_7 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_12 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_13 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8 = bpd_csignals_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_1 = bpd_csignals_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_4 = bpd_csignals_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_3 = bpd_csignals_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_1}; // @[pla.scala:91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_1 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_1, bpd_csignals_decoded_andMatrixOutputs_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_1}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_1}; // @[pla.scala:90:45, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_1 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_1}; // @[pla.scala:91:29, :98:53] wire [4:0] bpd_csignals_decoded_andMatrixOutputs_hi_1 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_1, bpd_csignals_decoded_andMatrixOutputs_hi_lo_1}; // @[pla.scala:98:53] wire [8:0] _bpd_csignals_decoded_andMatrixOutputs_T_1 = {bpd_csignals_decoded_andMatrixOutputs_hi_1, bpd_csignals_decoded_andMatrixOutputs_lo_1}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_9_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_1; // @[pla.scala:98:{53,70}] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_2 = bpd_csignals_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_3 = bpd_csignals_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_4 = bpd_csignals_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_5 = bpd_csignals_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_6 = bpd_csignals_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_7 = bpd_csignals_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_8 = bpd_csignals_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_12 = bpd_csignals_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_15 = bpd_csignals_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9 = bpd_csignals_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_3 = bpd_csignals_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_3 = bpd_csignals_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_6 = bpd_csignals_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_7 = bpd_csignals_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_8 = bpd_csignals_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10 = bpd_csignals_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_2 = bpd_csignals_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_2 = bpd_csignals_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_4 = bpd_csignals_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_5 = bpd_csignals_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_5 = bpd_csignals_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_6 = bpd_csignals_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_7 = bpd_csignals_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11 = bpd_csignals_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_1 = bpd_csignals_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_2 = bpd_csignals_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_3 = bpd_csignals_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_4 = bpd_csignals_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_5 = bpd_csignals_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_6 = bpd_csignals_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_7 = bpd_csignals_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12 = bpd_csignals_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_1 = bpd_csignals_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_2 = bpd_csignals_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_3 = bpd_csignals_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_4 = bpd_csignals_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_5 = bpd_csignals_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_6 = bpd_csignals_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_7 = bpd_csignals_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13 = bpd_csignals_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_1 = bpd_csignals_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_2 = bpd_csignals_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_3 = bpd_csignals_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_4 = bpd_csignals_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_5 = bpd_csignals_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_6 = bpd_csignals_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_7 = bpd_csignals_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14 = bpd_csignals_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_1 = bpd_csignals_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_1 = bpd_csignals_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_2 = bpd_csignals_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_3 = bpd_csignals_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_4 = bpd_csignals_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_5 = bpd_csignals_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_6 = bpd_csignals_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13}; // @[pla.scala:91:29, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_2 = {bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9}; // @[pla.scala:91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_2 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo}; // @[pla.scala:98:53] wire [6:0] bpd_csignals_decoded_andMatrixOutputs_lo_2 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_2, bpd_csignals_decoded_andMatrixOutputs_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_2}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_2}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_2 = {bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_2}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_2}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_2 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_1, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo}; // @[pla.scala:98:53] wire [7:0] bpd_csignals_decoded_andMatrixOutputs_hi_2 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_2, bpd_csignals_decoded_andMatrixOutputs_hi_lo_2}; // @[pla.scala:98:53] wire [14:0] _bpd_csignals_decoded_andMatrixOutputs_T_2 = {bpd_csignals_decoded_andMatrixOutputs_hi_2, bpd_csignals_decoded_andMatrixOutputs_lo_2}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_14_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_2; // @[pla.scala:98:{53,70}] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_1 = bpd_csignals_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_2 = bpd_csignals_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_3 = bpd_csignals_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_4 = bpd_csignals_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_1}; // @[pla.scala:91:29, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_3 = {bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_1}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_1}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_2}; // @[pla.scala:91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_3 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_1, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_1}; // @[pla.scala:98:53] wire [6:0] bpd_csignals_decoded_andMatrixOutputs_lo_3 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_3, bpd_csignals_decoded_andMatrixOutputs_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_3}; // @[pla.scala:90:45, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_3 = {bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_3}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_3}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_2 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_3}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_3 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_2, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_1}; // @[pla.scala:98:53] wire [6:0] bpd_csignals_decoded_andMatrixOutputs_hi_3 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_3, bpd_csignals_decoded_andMatrixOutputs_hi_lo_3}; // @[pla.scala:98:53] wire [13:0] _bpd_csignals_decoded_andMatrixOutputs_T_3 = {bpd_csignals_decoded_andMatrixOutputs_hi_3, bpd_csignals_decoded_andMatrixOutputs_lo_3}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_0_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_3; // @[pla.scala:98:{53,70}] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_2 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_2}; // @[pla.scala:91:29, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_4 = {bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_1}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_2 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_2}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_2 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_2}; // @[pla.scala:91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_4 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_2, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] bpd_csignals_decoded_andMatrixOutputs_lo_4 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_4, bpd_csignals_decoded_andMatrixOutputs_lo_lo_4}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_4}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_2 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_4}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_4 = {bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_2, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_2 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_4}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_3 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_4}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_4 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_3, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_2}; // @[pla.scala:98:53] wire [7:0] bpd_csignals_decoded_andMatrixOutputs_hi_4 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_4, bpd_csignals_decoded_andMatrixOutputs_hi_lo_4}; // @[pla.scala:98:53] wire [14:0] _bpd_csignals_decoded_andMatrixOutputs_T_4 = {bpd_csignals_decoded_andMatrixOutputs_hi_4, bpd_csignals_decoded_andMatrixOutputs_lo_4}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_2_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_4; // @[pla.scala:98:{53,70}] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_5 = bpd_csignals_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_7 = bpd_csignals_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_8 = bpd_csignals_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_5}; // @[pla.scala:90:45, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_5 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_5}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_5}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_5 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_5, bpd_csignals_decoded_andMatrixOutputs_hi_lo_5}; // @[pla.scala:98:53] wire [6:0] _bpd_csignals_decoded_andMatrixOutputs_T_5 = {bpd_csignals_decoded_andMatrixOutputs_hi_5, bpd_csignals_decoded_andMatrixOutputs_lo_5}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_12_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_5; // @[pla.scala:98:{53,70}] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_6 = bpd_csignals_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_7 = bpd_csignals_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_8 = bpd_csignals_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_12 = bpd_csignals_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_6 = bpd_csignals_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_7 = bpd_csignals_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_8 = bpd_csignals_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_12 = bpd_csignals_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_6}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_6 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_6, bpd_csignals_decoded_andMatrixOutputs_lo_lo_5}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_6}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_6}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_6 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_6, bpd_csignals_decoded_andMatrixOutputs_hi_lo_6}; // @[pla.scala:98:53] wire [7:0] _bpd_csignals_decoded_andMatrixOutputs_T_6 = {bpd_csignals_decoded_andMatrixOutputs_hi_6, bpd_csignals_decoded_andMatrixOutputs_lo_6}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_6_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_6; // @[pla.scala:98:{53,70}] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_3}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_3 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_7}; // @[pla.scala:90:45, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_7 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_6}; // @[pla.scala:91:29, :98:53] wire [4:0] bpd_csignals_decoded_andMatrixOutputs_lo_7 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_7, bpd_csignals_decoded_andMatrixOutputs_lo_lo_6}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_7 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_7}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_4 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_7}; // @[pla.scala:90:45, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_7 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_7}; // @[pla.scala:90:45, :98:53] wire [4:0] bpd_csignals_decoded_andMatrixOutputs_hi_7 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_7, bpd_csignals_decoded_andMatrixOutputs_hi_lo_7}; // @[pla.scala:98:53] wire [9:0] _bpd_csignals_decoded_andMatrixOutputs_T_7 = {bpd_csignals_decoded_andMatrixOutputs_hi_7, bpd_csignals_decoded_andMatrixOutputs_lo_7}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_15_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_7; // @[pla.scala:98:{53,70}] wire _bpd_csignals_decoded_orMatrixOutputs_T_4 = bpd_csignals_decoded_andMatrixOutputs_15_2; // @[pla.scala:98:70, :114:36] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_8 = bpd_csignals_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_10 = bpd_csignals_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_14 = bpd_csignals_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_8 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_8, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_8 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_8, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_8}; // @[pla.scala:90:45, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_8 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_8, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_8}; // @[pla.scala:90:45, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_8 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_8, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_8}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_8 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_8, bpd_csignals_decoded_andMatrixOutputs_hi_lo_8}; // @[pla.scala:98:53] wire [6:0] _bpd_csignals_decoded_andMatrixOutputs_T_8 = {bpd_csignals_decoded_andMatrixOutputs_hi_8, bpd_csignals_decoded_andMatrixOutputs_lo_8}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_11_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_8; // @[pla.scala:98:{53,70}] wire _bpd_csignals_decoded_orMatrixOutputs_T_5 = bpd_csignals_decoded_andMatrixOutputs_11_2; // @[pla.scala:98:70, :114:36] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_7 = bpd_csignals_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_10 = bpd_csignals_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_11 = bpd_csignals_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_14 = bpd_csignals_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_15 = bpd_csignals_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_3 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_3}; // @[pla.scala:91:29, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_7 = {bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_2}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_3 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_3}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_4 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_4}; // @[pla.scala:91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_9 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_4, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_3}; // @[pla.scala:98:53] wire [6:0] bpd_csignals_decoded_andMatrixOutputs_lo_9 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_9, bpd_csignals_decoded_andMatrixOutputs_lo_lo_7}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_2 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_9, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_3 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_9, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_9 = {bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_3, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_3 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_9, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_9}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_9, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_9}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_9 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_5, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_3}; // @[pla.scala:98:53] wire [7:0] bpd_csignals_decoded_andMatrixOutputs_hi_9 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_9, bpd_csignals_decoded_andMatrixOutputs_hi_lo_9}; // @[pla.scala:98:53] wire [14:0] _bpd_csignals_decoded_andMatrixOutputs_T_9 = {bpd_csignals_decoded_andMatrixOutputs_hi_9, bpd_csignals_decoded_andMatrixOutputs_lo_9}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_3_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_9; // @[pla.scala:98:{53,70}] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_4 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_4}; // @[pla.scala:91:29, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_8 = {bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_3}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_4 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_4}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_5}; // @[pla.scala:91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_10 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_5, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_4}; // @[pla.scala:98:53] wire [6:0] bpd_csignals_decoded_andMatrixOutputs_lo_10 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_10, bpd_csignals_decoded_andMatrixOutputs_lo_lo_8}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_3 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_10, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_4 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_10, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_10 = {bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_4, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_4 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_10, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_10, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_10}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_10 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_6, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_4}; // @[pla.scala:98:53] wire [7:0] bpd_csignals_decoded_andMatrixOutputs_hi_10 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_10, bpd_csignals_decoded_andMatrixOutputs_hi_lo_10}; // @[pla.scala:98:53] wire [14:0] _bpd_csignals_decoded_andMatrixOutputs_T_10 = {bpd_csignals_decoded_andMatrixOutputs_hi_10, bpd_csignals_decoded_andMatrixOutputs_lo_10}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_7_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_10; // @[pla.scala:98:{53,70}] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_9 = bpd_csignals_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_9 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_11, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_11 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_11, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_11 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_11, bpd_csignals_decoded_andMatrixOutputs_lo_lo_9}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_11 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_11, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_11}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_11 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_11, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_11}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_11 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_11, bpd_csignals_decoded_andMatrixOutputs_hi_lo_11}; // @[pla.scala:98:53] wire [7:0] _bpd_csignals_decoded_andMatrixOutputs_T_11 = {bpd_csignals_decoded_andMatrixOutputs_hi_11, bpd_csignals_decoded_andMatrixOutputs_lo_11}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_1_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_11; // @[pla.scala:98:{53,70}] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_10 = bpd_csignals_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_6 = bpd_csignals_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_8 = bpd_csignals_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_9 = bpd_csignals_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_10 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_12, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_10}; // @[pla.scala:90:45, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_12 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_12, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_12 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_12, bpd_csignals_decoded_andMatrixOutputs_lo_lo_10}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_12 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_12, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_12}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_12 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_12, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_12}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_12 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_12, bpd_csignals_decoded_andMatrixOutputs_hi_lo_12}; // @[pla.scala:98:53] wire [7:0] _bpd_csignals_decoded_andMatrixOutputs_T_12 = {bpd_csignals_decoded_andMatrixOutputs_hi_12, bpd_csignals_decoded_andMatrixOutputs_lo_12}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_13_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_12; // @[pla.scala:98:{53,70}] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_5}; // @[pla.scala:91:29, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_11 = {bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_4}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_5}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_6}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_13 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_6, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_5}; // @[pla.scala:98:53] wire [6:0] bpd_csignals_decoded_andMatrixOutputs_lo_13 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_13, bpd_csignals_decoded_andMatrixOutputs_lo_lo_11}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_4 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_13, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_13, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_13 = {bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_5, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_4}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_13, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_13}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_7 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_13, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_13}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_13 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_7, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_5}; // @[pla.scala:98:53] wire [7:0] bpd_csignals_decoded_andMatrixOutputs_hi_13 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_13, bpd_csignals_decoded_andMatrixOutputs_hi_lo_13}; // @[pla.scala:98:53] wire [14:0] _bpd_csignals_decoded_andMatrixOutputs_T_13 = {bpd_csignals_decoded_andMatrixOutputs_hi_13, bpd_csignals_decoded_andMatrixOutputs_lo_13}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_4_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_13; // @[pla.scala:98:{53,70}] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_6}; // @[pla.scala:91:29, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_12 = {bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_5}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_6}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_7 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_8, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_14 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_7, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_6}; // @[pla.scala:98:53] wire [6:0] bpd_csignals_decoded_andMatrixOutputs_lo_14 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_14, bpd_csignals_decoded_andMatrixOutputs_lo_lo_12}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_14, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_14, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_14 = {bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_6, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_5}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_14, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_8 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_14, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_14}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_14 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_8, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_6}; // @[pla.scala:98:53] wire [7:0] bpd_csignals_decoded_andMatrixOutputs_hi_14 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_14, bpd_csignals_decoded_andMatrixOutputs_hi_lo_14}; // @[pla.scala:98:53] wire [14:0] _bpd_csignals_decoded_andMatrixOutputs_T_14 = {bpd_csignals_decoded_andMatrixOutputs_hi_14, bpd_csignals_decoded_andMatrixOutputs_lo_14}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_8_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_14; // @[pla.scala:98:{53,70}] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_7 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_7}; // @[pla.scala:91:29, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_13 = {bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_6}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_7 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_7}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_8 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_9, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_15 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_8, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_7}; // @[pla.scala:98:53] wire [6:0] bpd_csignals_decoded_andMatrixOutputs_lo_15 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_15, bpd_csignals_decoded_andMatrixOutputs_lo_lo_13}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_15, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_7 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_15, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_15 = {bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_7, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_6}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_7 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_15, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_9 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_15, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_15}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_15 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_9, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_7}; // @[pla.scala:98:53] wire [7:0] bpd_csignals_decoded_andMatrixOutputs_hi_15 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_15, bpd_csignals_decoded_andMatrixOutputs_hi_lo_15}; // @[pla.scala:98:53] wire [14:0] _bpd_csignals_decoded_andMatrixOutputs_T_15 = {bpd_csignals_decoded_andMatrixOutputs_hi_15, bpd_csignals_decoded_andMatrixOutputs_lo_15}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_10_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_15; // @[pla.scala:98:{53,70}] wire [1:0] bpd_csignals_decoded_orMatrixOutputs_lo = {bpd_csignals_decoded_andMatrixOutputs_2_2, bpd_csignals_decoded_andMatrixOutputs_10_2}; // @[pla.scala:98:70, :114:19] wire [1:0] bpd_csignals_decoded_orMatrixOutputs_hi = {bpd_csignals_decoded_andMatrixOutputs_14_2, bpd_csignals_decoded_andMatrixOutputs_0_2}; // @[pla.scala:98:70, :114:19] wire [3:0] _bpd_csignals_decoded_orMatrixOutputs_T = {bpd_csignals_decoded_orMatrixOutputs_hi, bpd_csignals_decoded_orMatrixOutputs_lo}; // @[pla.scala:114:19] wire _bpd_csignals_decoded_orMatrixOutputs_T_1 = \|_bpd_csignals_decoded_orMatrixOutputs_T; // @[pla.scala:114:{19,36}] wire [1:0] bpd_csignals_decoded_orMatrixOutputs_lo_lo = {bpd_csignals_decoded_andMatrixOutputs_8_2, bpd_csignals_decoded_andMatrixOutputs_10_2}; // @[pla.scala:98:70, :114:19] wire [1:0] bpd_csignals_decoded_orMatrixOutputs_lo_hi_hi = {bpd_csignals_decoded_andMatrixOutputs_7_2, bpd_csignals_decoded_andMatrixOutputs_1_2}; // @[pla.scala:98:70, :114:19] wire [2:0] bpd_csignals_decoded_orMatrixOutputs_lo_hi = {bpd_csignals_decoded_orMatrixOutputs_lo_hi_hi, bpd_csignals_decoded_andMatrixOutputs_4_2}; // @[pla.scala:98:70, :114:19] wire [4:0] bpd_csignals_decoded_orMatrixOutputs_lo_1 = {bpd_csignals_decoded_orMatrixOutputs_lo_hi, bpd_csignals_decoded_orMatrixOutputs_lo_lo}; // @[pla.scala:114:19] wire [1:0] bpd_csignals_decoded_orMatrixOutputs_hi_lo_hi = {bpd_csignals_decoded_andMatrixOutputs_0_2, bpd_csignals_decoded_andMatrixOutputs_12_2}; // @[pla.scala:98:70, :114:19] wire [2:0] bpd_csignals_decoded_orMatrixOutputs_hi_lo = {bpd_csignals_decoded_orMatrixOutputs_hi_lo_hi, bpd_csignals_decoded_andMatrixOutputs_3_2}; // @[pla.scala:98:70, :114:19] wire [1:0] bpd_csignals_decoded_orMatrixOutputs_hi_hi_hi = {bpd_csignals_decoded_andMatrixOutputs_5_2, bpd_csignals_decoded_andMatrixOutputs_9_2}; // @[pla.scala:98:70, :114:19] wire [2:0] bpd_csignals_decoded_orMatrixOutputs_hi_hi = {bpd_csignals_decoded_orMatrixOutputs_hi_hi_hi, bpd_csignals_decoded_andMatrixOutputs_14_2}; // @[pla.scala:98:70, :114:19] wire [5:0] bpd_csignals_decoded_orMatrixOutputs_hi_1 = {bpd_csignals_decoded_orMatrixOutputs_hi_hi, bpd_csignals_decoded_orMatrixOutputs_hi_lo}; // @[pla.scala:114:19] wire [10:0] _bpd_csignals_decoded_orMatrixOutputs_T_2 = {bpd_csignals_decoded_orMatrixOutputs_hi_1, bpd_csignals_decoded_orMatrixOutputs_lo_1}; // @[pla.scala:114:19] wire _bpd_csignals_decoded_orMatrixOutputs_T_3 = \|_bpd_csignals_decoded_orMatrixOutputs_T_2; // @[pla.scala:114:{19,36}] wire [1:0] _bpd_csignals_decoded_orMatrixOutputs_T_6 = {bpd_csignals_decoded_andMatrixOutputs_6_2, bpd_csignals_decoded_andMatrixOutputs_13_2}; // @[pla.scala:98:70, :114:19] wire _bpd_csignals_decoded_orMatrixOutputs_T_7 = \|_bpd_csignals_decoded_orMatrixOutputs_T_6; // @[pla.scala:114:{19,36}] wire [1:0] bpd_csignals_decoded_orMatrixOutputs_lo_2 = {_bpd_csignals_decoded_orMatrixOutputs_T_3, _bpd_csignals_decoded_orMatrixOutputs_T_1}; // @[pla.scala:102:36, :114:36] wire [1:0] bpd_csignals_decoded_orMatrixOutputs_hi_hi_1 = {_bpd_csignals_decoded_orMatrixOutputs_T_7, _bpd_csignals_decoded_orMatrixOutputs_T_5}; // @[pla.scala:102:36, :114:36] wire [2:0] bpd_csignals_decoded_orMatrixOutputs_hi_2 = {bpd_csignals_decoded_orMatrixOutputs_hi_hi_1, _bpd_csignals_decoded_orMatrixOutputs_T_4}; // @[pla.scala:102:36, :114:36] wire [4:0] bpd_csignals_decoded_orMatrixOutputs = {bpd_csignals_decoded_orMatrixOutputs_hi_2, bpd_csignals_decoded_orMatrixOutputs_lo_2}; // @[pla.scala:102:36] wire _bpd_csignals_decoded_invMatrixOutputs_T = bpd_csignals_decoded_orMatrixOutputs[0]; // @[pla.scala:102:36, :124:31] wire _bpd_csignals_decoded_invMatrixOutputs_T_1 = bpd_csignals_decoded_orMatrixOutputs[1]; // @[pla.scala:102:36, :124:31] wire _bpd_csignals_decoded_invMatrixOutputs_T_2 = bpd_csignals_decoded_orMatrixOutputs[2]; // @[pla.scala:102:36, :124:31] wire _bpd_csignals_decoded_invMatrixOutputs_T_3 = bpd_csignals_decoded_orMatrixOutputs[3]; // @[pla.scala:102:36, :124:31] wire _bpd_csignals_decoded_invMatrixOutputs_T_4 = bpd_csignals_decoded_orMatrixOutputs[4]; // @[pla.scala:102:36, :124:31] wire [1:0] bpd_csignals_decoded_invMatrixOutputs_lo = {_bpd_csignals_decoded_invMatrixOutputs_T_1, _bpd_csignals_decoded_invMatrixOutputs_T}; // @[pla.scala:120:37, :124:31] wire [1:0] bpd_csignals_decoded_invMatrixOutputs_hi_hi = {_bpd_csignals_decoded_invMatrixOutputs_T_4, _bpd_csignals_decoded_invMatrixOutputs_T_3}; // @[pla.scala:120:37, :124:31] wire [2:0] bpd_csignals_decoded_invMatrixOutputs_hi = {bpd_csignals_decoded_invMatrixOutputs_hi_hi, _bpd_csignals_decoded_invMatrixOutputs_T_2}; // @[pla.scala:120:37, :124:31] assign bpd_csignals_decoded_invMatrixOutputs = {bpd_csignals_decoded_invMatrixOutputs_hi, bpd_csignals_decoded_invMatrixOutputs_lo}; // @[pla.scala:120:37] assign bpd_csignals_decoded = bpd_csignals_decoded_invMatrixOutputs; // @[pla.scala:81:23, :120:37] wire bpd_csignals_0 = bpd_csignals_decoded[4]; // @[pla.scala:81:23] wire cs_is_br = bpd_csignals_0; // @[Decode.scala:50:77] wire bpd_csignals_1 = bpd_csignals_decoded[3]; // @[pla.scala:81:23] wire cs_is_jal = bpd_csignals_1; // @[Decode.scala:50:77] wire bpd_csignals_2 = bpd_csignals_decoded[2]; // @[pla.scala:81:23] wire cs_is_jalr = bpd_csignals_2; // @[Decode.scala:50:77] wire bpd_csignals_3 = bpd_csignals_decoded[1]; // @[pla.scala:81:23] wire cs_is_shadowable = bpd_csignals_3; // @[Decode.scala:50:77] wire bpd_csignals_4 = bpd_csignals_decoded[0]; // @[pla.scala:81:23] wire cs_has_rs2 = bpd_csignals_4; // @[Decode.scala:50:77] wire _io_out_is_call_T = cs_is_jal \| cs_is_jalr; // @[decode.scala:695:34, :696:35, :700:32] wire [4:0] _io_out_is_call_T_1 = io_inst_0[11:7]; // @[decode.scala:629:7] wire [4:0] _io_out_is_ret_T_4 = io_inst_0[11:7]; // @[decode.scala:629:7] wire [4:0] _io_out_shadowable_T_2 = io_inst_0[11:7]; // @[decode.scala:629:7] wire _io_out_is_call_T_2 = _io_out_is_call_T_1 == 5'h1; // @[decode.scala:700:65] assign _io_out_is_call_T_3 = _io_out_is_call_T & _io_out_is_call_T_2; // @[decode.scala:700:{32,47,65}] assign io_out_is_call_0 = _io_out_is_call_T_3; // @[decode.scala:629:7, :700:47] wire [4:0] _io_out_is_ret_T = io_inst_0[19:15]; // @[decode.scala:629:7] wire [4:0] _io_out_shadowable_T_1 = io_inst_0[19:15]; // @[decode.scala:629:7] wire [4:0] _io_out_shadowable_T_7 = io_inst_0[19:15]; // @[decode.scala:629:7] wire [4:0] _io_out_is_ret_T_1 = _io_out_is_ret_T & 5'h1B; // @[decode.scala:701:51] wire _io_out_is_ret_T_2 = _io_out_is_ret_T_1 == 5'h1; // @[decode.scala:701:51] wire _io_out_is_ret_T_3 = cs_is_jalr & _io_out_is_ret_T_2; // @[decode.scala:696:35, :701:{32,51}] wire _io_out_is_ret_T_5 = _io_out_is_ret_T_4 == 5'h0; // @[decode.scala:701:90] assign _io_out_is_ret_T_6 = _io_out_is_ret_T_3 & _io_out_is_ret_T_5; // @[decode.scala:701:{32,72,90}] assign io_out_is_ret_0 = _io_out_is_ret_T_6; // @[decode.scala:629:7, :701:72] wire _io_out_target_b_imm32_T = io_inst_0[31]; // @[decode.scala:629:7] wire _io_out_target_j_imm32_T = io_inst_0[31]; // @[decode.scala:629:7] wire _io_out_sfb_offset_valid_T = io_inst_0[31]; // @[decode.scala:629:7, :716:50] wire [19:0] _io_out_target_b_imm32_T_1 = {20{_io_out_target_b_imm32_T}}; // @[consts.scala:189:{27,35}] wire _io_out_target_b_imm32_T_2 = io_inst_0[7]; // @[decode.scala:629:7] wire _br_offset_T = io_inst_0[7]; // @[decode.scala:629:7, :714:30] wire [5:0] _io_out_target_b_imm32_T_3 = io_inst_0[30:25]; // @[decode.scala:629:7] wire [5:0] _io_out_target_j_imm32_T_4 = io_inst_0[30:25]; // @[decode.scala:629:7] wire [5:0] _br_offset_T_1 = io_inst_0[30:25]; // @[decode.scala:629:7, :714:42] wire [3:0] _io_out_target_b_imm32_T_4 = io_inst_0[11:8]; // @[decode.scala:629:7] wire [3:0] _br_offset_T_2 = io_inst_0[11:8]; // @[decode.scala:629:7, :714:58] wire [4:0] io_out_target_b_imm32_lo = {_io_out_target_b_imm32_T_4, 1'h0}; // @[consts.scala:189:{22,68}] wire [20:0] io_out_target_b_imm32_hi_hi = {_io_out_target_b_imm32_T_1, _io_out_target_b_imm32_T_2}; // @[consts.scala:189:{22,27,46}] wire [26:0] io_out_target_b_imm32_hi = {io_out_target_b_imm32_hi_hi, _io_out_target_b_imm32_T_3}; // @[consts.scala:189:{22,55}] wire [31:0] io_out_target_b_imm32 = {io_out_target_b_imm32_hi, io_out_target_b_imm32_lo}; // @[consts.scala:189:22] wire [31:0] _io_out_target_T_1 = io_out_target_b_imm32; // @[consts.scala:189:22, :190:27] wire [40:0] _io_out_target_T_2 = {_io_out_target_T[39], _io_out_target_T} + {{9{_io_out_target_T_1[31]}}, _io_out_target_T_1}; // @[consts.scala:190:{10,17,27}] wire [39:0] _io_out_target_T_3 = _io_out_target_T_2[39:0]; // @[consts.scala:190:17] wire [39:0] _io_out_target_T_4 = _io_out_target_T_3; // @[consts.scala:190:17] wire [39:0] _io_out_target_T_5 = _io_out_target_T_4 & 40'hFFFFFFFFFE; // @[consts.scala:190:{17,42}] wire [39:0] _io_out_target_T_6 = _io_out_target_T_5; // @[consts.scala:190:42] wire [39:0] _io_out_target_T_7 = _io_out_target_T_6; // @[consts.scala:190:{42,52}] wire [11:0] _io_out_target_j_imm32_T_1 = {12{_io_out_target_j_imm32_T}}; // @[consts.scala:195:{27,35}] wire [7:0] _io_out_target_j_imm32_T_2 = io_inst_0[19:12]; // @[decode.scala:629:7] wire _io_out_target_j_imm32_T_3 = io_inst_0[20]; // @[decode.scala:629:7] wire [3:0] _io_out_target_j_imm32_T_5 = io_inst_0[24:21]; // @[decode.scala:629:7] wire [9:0] io_out_target_j_imm32_lo_hi = {_io_out_target_j_imm32_T_4, _io_out_target_j_imm32_T_5}; // @[consts.scala:195:{22,69,82}] wire [10:0] io_out_target_j_imm32_lo = {io_out_target_j_imm32_lo_hi, 1'h0}; // @[consts.scala:195:22] wire [19:0] io_out_target_j_imm32_hi_hi = {_io_out_target_j_imm32_T_1, _io_out_target_j_imm32_T_2}; // @[consts.scala:195:{22,27,46}] wire [20:0] io_out_target_j_imm32_hi = {io_out_target_j_imm32_hi_hi, _io_out_target_j_imm32_T_3}; // @[consts.scala:195:{22,59}] wire [31:0] io_out_target_j_imm32 = {io_out_target_j_imm32_hi, io_out_target_j_imm32_lo}; // @[consts.scala:195:22] wire [31:0] _io_out_target_T_9 = io_out_target_j_imm32; // @[consts.scala:195:22, :196:27] wire [40:0] _io_out_target_T_10 = {_io_out_target_T_8[39], _io_out_target_T_8} + {{9{_io_out_target_T_9[31]}}, _io_out_target_T_9}; // @[consts.scala:196:{10,17,27}] wire [39:0] _io_out_target_T_11 = _io_out_target_T_10[39:0]; // @[consts.scala:196:17] wire [39:0] _io_out_target_T_12 = _io_out_target_T_11; // @[consts.scala:196:17] wire [39:0] _io_out_target_T_13 = _io_out_target_T_12 & 40'hFFFFFFFFFE; // @[consts.scala:196:{17,42}] wire [39:0] _io_out_target_T_14 = _io_out_target_T_13; // @[consts.scala:196:42] wire [39:0] _io_out_target_T_15 = _io_out_target_T_14; // @[consts.scala:196:{42,52}] assign _io_out_target_T_16 = cs_is_br ? _io_out_target_T_7 : _io_out_target_T_15; // @[decode.scala:694:33, :703:23] assign io_out_target_0 = _io_out_target_T_16; // @[decode.scala:629:7, :703:23] wire [2:0] _io_out_cfi_type_T = {2'h0, cs_is_br}; // @[decode.scala:694:33, :710:8] wire [2:0] _io_out_cfi_type_T_1 = cs_is_jal ? 3'h2 : _io_out_cfi_type_T; // @[decode.scala:695:34, :708:8, :710:8] assign _io_out_cfi_type_T_2 = cs_is_jalr ? 3'h3 : _io_out_cfi_type_T_1; // @[decode.scala:696:35, :706:8, :708:8] assign io_out_cfi_type_0 = _io_out_cfi_type_T_2; // @[decode.scala:629:7, :706:8] wire [4:0] br_offset_lo = {_br_offset_T_2, 1'h0}; // @[decode.scala:714:{22,58}] wire [6:0] br_offset_hi = {_br_offset_T, _br_offset_T_1}; // @[decode.scala:714:{22,30,42}] wire [11:0] br_offset = {br_offset_hi, br_offset_lo}; // @[decode.scala:714:22] wire _io_out_sfb_offset_valid_T_1 = ~_io_out_sfb_offset_valid_T; // @[decode.scala:716:{42,50}] wire _io_out_sfb_offset_valid_T_2 = cs_is_br & _io_out_sfb_offset_valid_T_1; // @[decode.scala:694:33, :716:{39,42}] wire _io_out_sfb_offset_valid_T_3 = \|br_offset; // @[decode.scala:714:22, :716:68] wire _io_out_sfb_offset_valid_T_4 = _io_out_sfb_offset_valid_T_2 & _io_out_sfb_offset_valid_T_3; // @[decode.scala:716:{39,55,68}] wire [5:0] _io_out_sfb_offset_valid_T_5 = br_offset[11:6]; // @[decode.scala:714:22, :716:90] wire _io_out_sfb_offset_valid_T_6 = _io_out_sfb_offset_valid_T_5 == 6'h0; // @[decode.scala:716:{90,117}] assign _io_out_sfb_offset_valid_T_7 = _io_out_sfb_offset_valid_T_4 & _io_out_sfb_offset_valid_T_6; // @[decode.scala:716:{55,76,117}] assign io_out_sfb_offset_valid_0 = _io_out_sfb_offset_valid_T_7; // @[decode.scala:629:7, :716:76] assign io_out_sfb_offset_bits_0 = br_offset[5:0]; // @[decode.scala:629:7, :714:22, :717:27] wire _io_out_shadowable_T = ~cs_has_rs2; // @[decode.scala:698:35, :719:5] wire _io_out_shadowable_T_3 = _io_out_shadowable_T_1 == _io_out_shadowable_T_2; // @[decode.scala:720:22] wire _io_out_shadowable_T_4 = _io_out_shadowable_T \| _io_out_shadowable_T_3; // @[decode.scala:719:{5,17}, :720:22] wire [31:0] _io_out_shadowable_T_5 = io_inst_0 & 32'hFE00707F; // @[decode.scala:629:7, :721:14] wire _io_out_shadowable_T_6 = _io_out_shadowable_T_5 == 32'h33; // @[decode.scala:721:14] wire _io_out_shadowable_T_8 = _io_out_shadowable_T_7 == 5'h0; // @[decode.scala:701:90, :721:41] wire _io_out_shadowable_T_9 = _io_out_shadowable_T_6 & _io_out_shadowable_T_8; // @[decode.scala:721:{14,22,41}] wire _io_out_shadowable_T_10 = _io_out_shadowable_T_4 \| _io_out_shadowable_T_9; // @[decode.scala:719:17, :720:42, :721:22] assign _io_out_shadowable_T_11 = cs_is_shadowable & _io_out_shadowable_T_10; // @[decode.scala:697:41, :718:41, :720:42] assign io_out_shadowable_0 = _io_out_shadowable_T_11; // @[decode.scala:629:7, :718:41] assign io_out_is_ret = io_out_is_ret_0; // @[decode.scala:629:7] assign io_out_is_call = io_out_is_call_0; // @[decode.scala:629:7] assign io_out_target = io_out_target_0; // @[decode.scala:629:7] assign io_out_cfi_type = io_out_cfi_type_0; // @[decode.scala:629:7] assign io_out_sfb_offset_valid = io_out_sfb_offset_valid_0; // @[decode.scala:629:7] assign io_out_sfb_offset_bits = io_out_sfb_offset_bits_0; // @[decode.scala:629:7] assign io_out_shadowable = io_out_shadowable_0; // @[decode.scala:629:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module Tile_231 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_487 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a	module Tile_231( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0, // @[Tile.scala:17:14] output io_bad_dataflow // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] wire io_bad_dataflow_0; // @[Tile.scala:16:7] PE_487 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0), .io_bad_dataflow (io_bad_dataflow_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module IssueSlot_37 : input clock : Clock input reset : Reset output io : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, flip grant : UInt<1>, iss_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, flip in_uop : { valid : UInt<1>, bits : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}}, out_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt<21>}}, flip kill : UInt<1>, flip clear : UInt<1>, flip squash_grant : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<3>, rebusy : UInt<1>}}[5], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip child_rebusys : UInt<3>} regreset slot_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg slot_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, clock wire next_valid : UInt<1> connect next_valid, slot_valid wire next_uop_out : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect next_uop_out, slot_uop node _next_uop_out_br_mask_T = not(io.brupdate.b1.resolve_mask) node _next_uop_out_br_mask_T_1 = and(slot_uop.br_mask, _next_uop_out_br_mask_T) connect next_uop_out.br_mask, _next_uop_out_br_mask_T_1 wire next_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect next_uop, next_uop_out node _killed_T = and(io.brupdate.b1.mispredict_mask, slot_uop.br_mask) node _killed_T_1 = neq(_killed_T, UInt<1>(0h0)) node killed = or(_killed_T_1, io.kill) connect io.valid, slot_valid connect io.out_uop, next_uop node _io_will_be_valid_T = eq(killed, UInt<1>(0h0)) node _io_will_be_valid_T_1 = and(next_valid, _io_will_be_valid_T) connect io.will_be_valid, _io_will_be_valid_T_1 when io.kill : connect slot_valid, UInt<1>(0h0) else : when io.in_uop.valid : connect slot_valid, UInt<1>(0h1) else : when io.clear : connect slot_valid, UInt<1>(0h0) else : node _slot_valid_T = eq(killed, UInt<1>(0h0)) node _slot_valid_T_1 = and(next_valid, _slot_valid_T) connect slot_valid, _slot_valid_T_1 when io.in_uop.valid : connect slot_uop, io.in_uop.bits node _T = eq(slot_valid, UInt<1>(0h0)) node _T_1 = or(_T, io.clear) node _T_2 = or(_T_1, io.kill) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:79 assert (!slot_valid \|\| io.clear \|\| io.kill)\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert else : connect slot_uop, next_uop connect next_uop.iw_p1_bypass_hint, UInt<1>(0h0) connect next_uop.iw_p2_bypass_hint, UInt<1>(0h0) connect next_uop.iw_p3_bypass_hint, UInt<1>(0h0) connect next_uop.iw_p1_speculative_child, UInt<1>(0h0) connect next_uop.iw_p2_speculative_child, UInt<1>(0h0) wire rebusied_prs1 : UInt<1> connect rebusied_prs1, UInt<1>(0h0) wire rebusied_prs2 : UInt<1> connect rebusied_prs2, UInt<1>(0h0) node rebusied = or(rebusied_prs1, rebusied_prs2) node prs1_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs1) node prs1_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs1) node prs1_matches_2 = eq(io.wakeup_ports[2].bits.uop.pdst, slot_uop.prs1) node prs1_matches_3 = eq(io.wakeup_ports[3].bits.uop.pdst, slot_uop.prs1) node prs1_matches_4 = eq(io.wakeup_ports[4].bits.uop.pdst, slot_uop.prs1) node prs2_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs2) node prs2_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs2) node prs2_matches_2 = eq(io.wakeup_ports[2].bits.uop.pdst, slot_uop.prs2) node prs2_matches_3 = eq(io.wakeup_ports[3].bits.uop.pdst, slot_uop.prs2) node prs2_matches_4 = eq(io.wakeup_ports[4].bits.uop.pdst, slot_uop.prs2) node prs3_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs3) node prs3_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs3) node prs3_matches_2 = eq(io.wakeup_ports[2].bits.uop.pdst, slot_uop.prs3) node prs3_matches_3 = eq(io.wakeup_ports[3].bits.uop.pdst, slot_uop.prs3) node prs3_matches_4 = eq(io.wakeup_ports[4].bits.uop.pdst, slot_uop.prs3) node prs1_wakeups_0 = and(io.wakeup_ports[0].valid, prs1_matches_0) node prs1_wakeups_1 = and(io.wakeup_ports[1].valid, prs1_matches_1) node prs1_wakeups_2 = and(io.wakeup_ports[2].valid, prs1_matches_2) node prs1_wakeups_3 = and(io.wakeup_ports[3].valid, prs1_matches_3) node prs1_wakeups_4 = and(io.wakeup_ports[4].valid, prs1_matches_4) node prs2_wakeups_0 = and(io.wakeup_ports[0].valid, prs2_matches_0) node prs2_wakeups_1 = and(io.wakeup_ports[1].valid, prs2_matches_1) node prs2_wakeups_2 = and(io.wakeup_ports[2].valid, prs2_matches_2) node prs2_wakeups_3 = and(io.wakeup_ports[3].valid, prs2_matches_3) node prs2_wakeups_4 = and(io.wakeup_ports[4].valid, prs2_matches_4) node prs3_wakeups_0 = and(io.wakeup_ports[0].valid, prs3_matches_0) node prs3_wakeups_1 = and(io.wakeup_ports[1].valid, prs3_matches_1) node prs3_wakeups_2 = and(io.wakeup_ports[2].valid, prs3_matches_2) node prs3_wakeups_3 = and(io.wakeup_ports[3].valid, prs3_matches_3) node prs3_wakeups_4 = and(io.wakeup_ports[4].valid, prs3_matches_4) node prs1_rebusys_0 = and(io.wakeup_ports[0].bits.rebusy, prs1_matches_0) node prs1_rebusys_1 = and(io.wakeup_ports[1].bits.rebusy, prs1_matches_1) node prs1_rebusys_2 = and(io.wakeup_ports[2].bits.rebusy, prs1_matches_2) node prs1_rebusys_3 = and(io.wakeup_ports[3].bits.rebusy, prs1_matches_3) node prs1_rebusys_4 = and(io.wakeup_ports[4].bits.rebusy, prs1_matches_4) node prs2_rebusys_0 = and(io.wakeup_ports[0].bits.rebusy, prs2_matches_0) node prs2_rebusys_1 = and(io.wakeup_ports[1].bits.rebusy, prs2_matches_1) node prs2_rebusys_2 = and(io.wakeup_ports[2].bits.rebusy, prs2_matches_2) node prs2_rebusys_3 = and(io.wakeup_ports[3].bits.rebusy, prs2_matches_3) node prs2_rebusys_4 = and(io.wakeup_ports[4].bits.rebusy, prs2_matches_4) node _T_6 = or(prs1_wakeups_0, prs1_wakeups_1) node _T_7 = or(_T_6, prs1_wakeups_2) node _T_8 = or(_T_7, prs1_wakeups_3) node _T_9 = or(_T_8, prs1_wakeups_4) when _T_9 : connect next_uop.prs1_busy, UInt<1>(0h0) node _next_uop_iw_p1_speculative_child_T = mux(prs1_wakeups_0, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p1_speculative_child_T_1 = mux(prs1_wakeups_1, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p1_speculative_child_T_2 = mux(prs1_wakeups_2, io.wakeup_ports[2].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p1_speculative_child_T_3 = mux(prs1_wakeups_3, io.wakeup_ports[3].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p1_speculative_child_T_4 = mux(prs1_wakeups_4, io.wakeup_ports[4].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p1_speculative_child_T_5 = or(_next_uop_iw_p1_speculative_child_T, _next_uop_iw_p1_speculative_child_T_1) node _next_uop_iw_p1_speculative_child_T_6 = or(_next_uop_iw_p1_speculative_child_T_5, _next_uop_iw_p1_speculative_child_T_2) node _next_uop_iw_p1_speculative_child_T_7 = or(_next_uop_iw_p1_speculative_child_T_6, _next_uop_iw_p1_speculative_child_T_3) node _next_uop_iw_p1_speculative_child_T_8 = or(_next_uop_iw_p1_speculative_child_T_7, _next_uop_iw_p1_speculative_child_T_4) wire _next_uop_iw_p1_speculative_child_WIRE : UInt<3> connect _next_uop_iw_p1_speculative_child_WIRE, _next_uop_iw_p1_speculative_child_T_8 connect next_uop.iw_p1_speculative_child, _next_uop_iw_p1_speculative_child_WIRE node _next_uop_iw_p1_bypass_hint_T = mux(prs1_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p1_bypass_hint_T_1 = mux(prs1_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p1_bypass_hint_T_2 = mux(prs1_wakeups_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p1_bypass_hint_T_3 = mux(prs1_wakeups_3, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p1_bypass_hint_T_4 = mux(prs1_wakeups_4, io.wakeup_ports[4].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p1_bypass_hint_T_5 = or(_next_uop_iw_p1_bypass_hint_T, _next_uop_iw_p1_bypass_hint_T_1) node _next_uop_iw_p1_bypass_hint_T_6 = or(_next_uop_iw_p1_bypass_hint_T_5, _next_uop_iw_p1_bypass_hint_T_2) node _next_uop_iw_p1_bypass_hint_T_7 = or(_next_uop_iw_p1_bypass_hint_T_6, _next_uop_iw_p1_bypass_hint_T_3) node _next_uop_iw_p1_bypass_hint_T_8 = or(_next_uop_iw_p1_bypass_hint_T_7, _next_uop_iw_p1_bypass_hint_T_4) wire _next_uop_iw_p1_bypass_hint_WIRE : UInt<1> connect _next_uop_iw_p1_bypass_hint_WIRE, _next_uop_iw_p1_bypass_hint_T_8 connect next_uop.iw_p1_bypass_hint, _next_uop_iw_p1_bypass_hint_WIRE node _T_10 = or(prs1_rebusys_0, prs1_rebusys_1) node _T_11 = or(_T_10, prs1_rebusys_2) node _T_12 = or(_T_11, prs1_rebusys_3) node _T_13 = or(_T_12, prs1_rebusys_4) node _T_14 = and(io.child_rebusys, slot_uop.iw_p1_speculative_child) node _T_15 = neq(_T_14, UInt<1>(0h0)) node _T_16 = or(_T_13, _T_15) node _T_17 = eq(slot_uop.lrs1_rtype, UInt<2>(0h0)) node _T_18 = and(_T_16, _T_17) when _T_18 : connect next_uop.prs1_busy, UInt<1>(0h1) connect rebusied_prs1, UInt<1>(0h1) node _T_19 = or(prs2_wakeups_0, prs2_wakeups_1) node _T_20 = or(_T_19, prs2_wakeups_2) node _T_21 = or(_T_20, prs2_wakeups_3) node _T_22 = or(_T_21, prs2_wakeups_4) when _T_22 : connect next_uop.prs2_busy, UInt<1>(0h0) node _next_uop_iw_p2_speculative_child_T = mux(prs2_wakeups_0, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p2_speculative_child_T_1 = mux(prs2_wakeups_1, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p2_speculative_child_T_2 = mux(prs2_wakeups_2, io.wakeup_ports[2].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p2_speculative_child_T_3 = mux(prs2_wakeups_3, io.wakeup_ports[3].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p2_speculative_child_T_4 = mux(prs2_wakeups_4, io.wakeup_ports[4].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p2_speculative_child_T_5 = or(_next_uop_iw_p2_speculative_child_T, _next_uop_iw_p2_speculative_child_T_1) node _next_uop_iw_p2_speculative_child_T_6 = or(_next_uop_iw_p2_speculative_child_T_5, _next_uop_iw_p2_speculative_child_T_2) node _next_uop_iw_p2_speculative_child_T_7 = or(_next_uop_iw_p2_speculative_child_T_6, _next_uop_iw_p2_speculative_child_T_3) node _next_uop_iw_p2_speculative_child_T_8 = or(_next_uop_iw_p2_speculative_child_T_7, _next_uop_iw_p2_speculative_child_T_4) wire _next_uop_iw_p2_speculative_child_WIRE : UInt<3> connect _next_uop_iw_p2_speculative_child_WIRE, _next_uop_iw_p2_speculative_child_T_8 connect next_uop.iw_p2_speculative_child, _next_uop_iw_p2_speculative_child_WIRE node _next_uop_iw_p2_bypass_hint_T = mux(prs2_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p2_bypass_hint_T_1 = mux(prs2_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p2_bypass_hint_T_2 = mux(prs2_wakeups_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p2_bypass_hint_T_3 = mux(prs2_wakeups_3, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p2_bypass_hint_T_4 = mux(prs2_wakeups_4, io.wakeup_ports[4].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p2_bypass_hint_T_5 = or(_next_uop_iw_p2_bypass_hint_T, _next_uop_iw_p2_bypass_hint_T_1) node _next_uop_iw_p2_bypass_hint_T_6 = or(_next_uop_iw_p2_bypass_hint_T_5, _next_uop_iw_p2_bypass_hint_T_2) node _next_uop_iw_p2_bypass_hint_T_7 = or(_next_uop_iw_p2_bypass_hint_T_6, _next_uop_iw_p2_bypass_hint_T_3) node _next_uop_iw_p2_bypass_hint_T_8 = or(_next_uop_iw_p2_bypass_hint_T_7, _next_uop_iw_p2_bypass_hint_T_4) wire _next_uop_iw_p2_bypass_hint_WIRE : UInt<1> connect _next_uop_iw_p2_bypass_hint_WIRE, _next_uop_iw_p2_bypass_hint_T_8 connect next_uop.iw_p2_bypass_hint, _next_uop_iw_p2_bypass_hint_WIRE node _T_23 = or(prs2_rebusys_0, prs2_rebusys_1) node _T_24 = or(_T_23, prs2_rebusys_2) node _T_25 = or(_T_24, prs2_rebusys_3) node _T_26 = or(_T_25, prs2_rebusys_4) node _T_27 = and(io.child_rebusys, slot_uop.iw_p2_speculative_child) node _T_28 = neq(_T_27, UInt<1>(0h0)) node _T_29 = or(_T_26, _T_28) node _T_30 = eq(slot_uop.lrs2_rtype, UInt<2>(0h0)) node _T_31 = and(_T_29, _T_30) when _T_31 : connect next_uop.prs2_busy, UInt<1>(0h1) connect rebusied_prs2, UInt<1>(0h1) node _T_32 = or(prs3_wakeups_0, prs3_wakeups_1) node _T_33 = or(_T_32, prs3_wakeups_2) node _T_34 = or(_T_33, prs3_wakeups_3) node _T_35 = or(_T_34, prs3_wakeups_4) when _T_35 : connect next_uop.prs3_busy, UInt<1>(0h0) node _next_uop_iw_p3_bypass_hint_T = mux(prs3_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p3_bypass_hint_T_1 = mux(prs3_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p3_bypass_hint_T_2 = mux(prs3_wakeups_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p3_bypass_hint_T_3 = mux(prs3_wakeups_3, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p3_bypass_hint_T_4 = mux(prs3_wakeups_4, io.wakeup_ports[4].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p3_bypass_hint_T_5 = or(_next_uop_iw_p3_bypass_hint_T, _next_uop_iw_p3_bypass_hint_T_1) node _next_uop_iw_p3_bypass_hint_T_6 = or(_next_uop_iw_p3_bypass_hint_T_5, _next_uop_iw_p3_bypass_hint_T_2) node _next_uop_iw_p3_bypass_hint_T_7 = or(_next_uop_iw_p3_bypass_hint_T_6, _next_uop_iw_p3_bypass_hint_T_3) node _next_uop_iw_p3_bypass_hint_T_8 = or(_next_uop_iw_p3_bypass_hint_T_7, _next_uop_iw_p3_bypass_hint_T_4) wire _next_uop_iw_p3_bypass_hint_WIRE : UInt<1> connect _next_uop_iw_p3_bypass_hint_WIRE, _next_uop_iw_p3_bypass_hint_T_8 connect next_uop.iw_p3_bypass_hint, _next_uop_iw_p3_bypass_hint_WIRE node _T_36 = eq(io.pred_wakeup_port.bits, slot_uop.ppred) node _T_37 = and(io.pred_wakeup_port.valid, _T_36) when _T_37 : connect next_uop.ppred_busy, UInt<1>(0h0) node _iss_ready_T = eq(slot_uop.prs1_busy, UInt<1>(0h0)) node _iss_ready_T_1 = eq(slot_uop.prs2_busy, UInt<1>(0h0)) node _iss_ready_T_2 = and(_iss_ready_T, _iss_ready_T_1) node _iss_ready_T_3 = and(slot_uop.ppred_busy, UInt<1>(0h1)) node _iss_ready_T_4 = eq(_iss_ready_T_3, UInt<1>(0h0)) node _iss_ready_T_5 = and(_iss_ready_T_2, _iss_ready_T_4) node _iss_ready_T_6 = and(slot_uop.prs3_busy, UInt<1>(0h0)) node _iss_ready_T_7 = eq(_iss_ready_T_6, UInt<1>(0h0)) node iss_ready = and(_iss_ready_T_5, _iss_ready_T_7) node _agen_ready_T = eq(slot_uop.prs1_busy, UInt<1>(0h0)) node _agen_ready_T_1 = and(slot_uop.fu_code[1], _agen_ready_T) node _agen_ready_T_2 = and(slot_uop.ppred_busy, UInt<1>(0h1)) node _agen_ready_T_3 = eq(_agen_ready_T_2, UInt<1>(0h0)) node _agen_ready_T_4 = and(_agen_ready_T_1, _agen_ready_T_3) node agen_ready = and(_agen_ready_T_4, UInt<1>(0h1)) node _dgen_ready_T = eq(slot_uop.prs2_busy, UInt<1>(0h0)) node _dgen_ready_T_1 = and(slot_uop.fu_code[2], _dgen_ready_T) node _dgen_ready_T_2 = and(slot_uop.ppred_busy, UInt<1>(0h1)) node _dgen_ready_T_3 = eq(_dgen_ready_T_2, UInt<1>(0h0)) node _dgen_ready_T_4 = and(_dgen_ready_T_1, _dgen_ready_T_3) node dgen_ready = and(_dgen_ready_T_4, UInt<1>(0h1)) node _io_request_T = eq(slot_uop.iw_issued, UInt<1>(0h0)) node _io_request_T_1 = and(slot_valid, _io_request_T) node _io_request_T_2 = or(iss_ready, agen_ready) node _io_request_T_3 = or(_io_request_T_2, dgen_ready) node _io_request_T_4 = and(_io_request_T_1, _io_request_T_3) connect io.request, _io_request_T_4 connect io.iss_uop, slot_uop connect next_uop.iw_issued, UInt<1>(0h0) connect next_uop.iw_issued_partial_agen, UInt<1>(0h0) connect next_uop.iw_issued_partial_dgen, UInt<1>(0h0) node _T_38 = eq(io.squash_grant, UInt<1>(0h0)) node _T_39 = and(io.grant, _T_38) when _T_39 : connect next_uop.iw_issued, UInt<1>(0h1) node _T_40 = and(slot_uop.fu_code[1], slot_uop.fu_code[2]) when _T_40 : when agen_ready : node _T_41 = eq(io.squash_grant, UInt<1>(0h0)) node _T_42 = and(io.grant, _T_41) when _T_42 : connect next_uop.iw_issued_partial_agen, UInt<1>(0h1) connect io.iss_uop.fu_code[1], UInt<1>(0h1) connect io.iss_uop.fu_code[2], UInt<1>(0h0) else : node _T_43 = eq(io.squash_grant, UInt<1>(0h0)) node _T_44 = and(io.grant, _T_43) when _T_44 : connect next_uop.iw_issued_partial_dgen, UInt<1>(0h1) connect io.iss_uop.fu_code[1], UInt<1>(0h0) connect io.iss_uop.fu_code[2], UInt<1>(0h1) connect io.iss_uop.imm_sel, UInt<3>(0h6) connect io.iss_uop.prs1, slot_uop.prs2 connect io.iss_uop.lrs1_rtype, slot_uop.lrs2_rtype connect io.iss_uop.iw_p1_bypass_hint, slot_uop.iw_p2_bypass_hint else : when slot_uop.fu_code[2] : connect io.iss_uop.imm_sel, UInt<3>(0h6) connect io.iss_uop.prs1, slot_uop.prs2 connect io.iss_uop.lrs1_rtype, slot_uop.lrs2_rtype connect io.iss_uop.iw_p1_bypass_hint, slot_uop.iw_p2_bypass_hint connect io.iss_uop.lrs2_rtype, UInt<2>(0h2) connect io.iss_uop.prs2, io.iss_uop.prs1 node _T_45 = and(slot_valid, slot_uop.iw_issued) when _T_45 : connect next_valid, rebusied when slot_uop.iw_issued_partial_agen : connect next_valid, UInt<1>(0h1) node _T_46 = eq(rebusied_prs1, UInt<1>(0h0)) when _T_46 : connect next_uop.fu_code[1], UInt<1>(0h0) connect next_uop.fu_code[2], UInt<1>(0h1) else : when slot_uop.iw_issued_partial_dgen : connect next_valid, UInt<1>(0h1) node _T_47 = eq(rebusied_prs2, UInt<1>(0h0)) when _T_47 : connect next_uop.fu_code[1], UInt<1>(0h1) connect next_uop.fu_code[2], UInt<1>(0h0)	module IssueSlot_37( // @[issue-slot.scala:49:7] input clock, // @[issue-slot.scala:49:7] input reset, // @[issue-slot.scala:49:7] output io_valid, // @[issue-slot.scala:52:14] output io_will_be_valid, // @[issue-slot.scala:52:14] output io_request, // @[issue-slot.scala:52:14] input io_grant, // @[issue-slot.scala:52:14] output [31:0] io_iss_uop_inst, // @[issue-slot.scala:52:14] output [31:0] io_iss_uop_debug_inst, // @[issue-slot.scala:52:14] output io_iss_uop_is_rvc, // @[issue-slot.scala:52:14] output [39:0] io_iss_uop_debug_pc, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_0, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_1, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_2, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_3, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_0, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_1, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_2, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_3, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_4, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_5, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_6, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_7, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_8, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_9, // @[issue-slot.scala:52:14] output io_iss_uop_iw_issued, // @[issue-slot.scala:52:14] output io_iss_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] output io_iss_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_dis_col_sel, // @[issue-slot.scala:52:14] output [15:0] io_iss_uop_br_mask, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_br_tag, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_br_type, // @[issue-slot.scala:52:14] output io_iss_uop_is_sfb, // @[issue-slot.scala:52:14] output io_iss_uop_is_fence, // @[issue-slot.scala:52:14] output io_iss_uop_is_fencei, // @[issue-slot.scala:52:14] output io_iss_uop_is_sfence, // @[issue-slot.scala:52:14] output io_iss_uop_is_amo, // @[issue-slot.scala:52:14] output io_iss_uop_is_eret, // @[issue-slot.scala:52:14] output io_iss_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] output io_iss_uop_is_rocc, // @[issue-slot.scala:52:14] output io_iss_uop_is_mov, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ftq_idx, // @[issue-slot.scala:52:14] output io_iss_uop_edge_inst, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_pc_lob, // @[issue-slot.scala:52:14] output io_iss_uop_taken, // @[issue-slot.scala:52:14] output io_iss_uop_imm_rename, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_imm_sel, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_pimm, // @[issue-slot.scala:52:14] output [19:0] io_iss_uop_imm_packed, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_op1_sel, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_op2_sel, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_rob_idx, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ldq_idx, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_stq_idx, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_rxq_idx, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_pdst, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs1, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs2, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs3, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ppred, // @[issue-slot.scala:52:14] output io_iss_uop_prs1_busy, // @[issue-slot.scala:52:14] output io_iss_uop_prs2_busy, // @[issue-slot.scala:52:14] output io_iss_uop_prs3_busy, // @[issue-slot.scala:52:14] output io_iss_uop_ppred_busy, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_stale_pdst, // @[issue-slot.scala:52:14] output io_iss_uop_exception, // @[issue-slot.scala:52:14] output [63:0] io_iss_uop_exc_cause, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_mem_cmd, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_mem_size, // @[issue-slot.scala:52:14] output io_iss_uop_mem_signed, // @[issue-slot.scala:52:14] output io_iss_uop_uses_ldq, // @[issue-slot.scala:52:14] output io_iss_uop_uses_stq, // @[issue-slot.scala:52:14] output io_iss_uop_is_unique, // @[issue-slot.scala:52:14] output io_iss_uop_flush_on_commit, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_csr_cmd, // @[issue-slot.scala:52:14] output io_iss_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_ldst, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs1, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs2, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs3, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_dst_rtype, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_lrs1_rtype, // @[issue-slot.scala:52:14] output io_iss_uop_frs3_en, // @[issue-slot.scala:52:14] output io_iss_uop_fcn_dw, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_fcn_op, // @[issue-slot.scala:52:14] output io_iss_uop_fp_val, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_fp_rm, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_typ, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] output io_iss_uop_bp_debug_if, // @[issue-slot.scala:52:14] output io_iss_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_debug_fsrc, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_in_uop_valid, // @[issue-slot.scala:52:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:52:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_0, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_1, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_2, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_0, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_1, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_2, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_4, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_5, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_6, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_7, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_8, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_9, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_issued, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_br_type, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sfence, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_eret, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_rocc, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:52:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:52:14] input io_in_uop_bits_taken, // @[issue-slot.scala:52:14] input io_in_uop_bits_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_pimm, // @[issue-slot.scala:52:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_op2_sel, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:52:14] input io_in_uop_bits_exception, // @[issue-slot.scala:52:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:52:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:52:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:52:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:52:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_csr_cmd, // @[issue-slot.scala:52:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:52:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:52:14] input io_in_uop_bits_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_fcn_op, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_typ, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:52:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:52:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:52:14] output io_out_uop_is_rvc, // @[issue-slot.scala:52:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_0, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_1, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_2, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_3, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_0, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_1, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_2, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_3, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_4, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_5, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_6, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_7, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_8, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_9, // @[issue-slot.scala:52:14] output io_out_uop_iw_issued, // @[issue-slot.scala:52:14] output io_out_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] output io_out_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] output io_out_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] output io_out_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] output io_out_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_dis_col_sel, // @[issue-slot.scala:52:14] output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_br_type, // @[issue-slot.scala:52:14] output io_out_uop_is_sfb, // @[issue-slot.scala:52:14] output io_out_uop_is_fence, // @[issue-slot.scala:52:14] output io_out_uop_is_fencei, // @[issue-slot.scala:52:14] output io_out_uop_is_sfence, // @[issue-slot.scala:52:14] output io_out_uop_is_amo, // @[issue-slot.scala:52:14] output io_out_uop_is_eret, // @[issue-slot.scala:52:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] output io_out_uop_is_rocc, // @[issue-slot.scala:52:14] output io_out_uop_is_mov, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:52:14] output io_out_uop_edge_inst, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:52:14] output io_out_uop_taken, // @[issue-slot.scala:52:14] output io_out_uop_imm_rename, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_imm_sel, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_pimm, // @[issue-slot.scala:52:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_op1_sel, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_op2_sel, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_pdst, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs1, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs2, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs3, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ppred, // @[issue-slot.scala:52:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:52:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:52:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:52:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:52:14] output io_out_uop_exception, // @[issue-slot.scala:52:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:52:14] output io_out_uop_mem_signed, // @[issue-slot.scala:52:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:52:14] output io_out_uop_uses_stq, // @[issue-slot.scala:52:14] output io_out_uop_is_unique, // @[issue-slot.scala:52:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_csr_cmd, // @[issue-slot.scala:52:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:52:14] output io_out_uop_frs3_en, // @[issue-slot.scala:52:14] output io_out_uop_fcn_dw, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_fcn_op, // @[issue-slot.scala:52:14] output io_out_uop_fp_val, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_fp_rm, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_typ, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:52:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:52:14] input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:52:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:52:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_br_type, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sfence, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_eret, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_rocc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_op2_sel, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_fcn_op, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_typ, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:52:14] input io_brupdate_b2_taken, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:52:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:52:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:52:14] input io_kill, // @[issue-slot.scala:52:14] input io_clear, // @[issue-slot.scala:52:14] input io_squash_grant, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_0_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_0_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_0_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_0_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_0_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_0_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_bypassable, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_speculative_mask, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_rebusy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_1_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_1_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_1_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_1_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_1_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_1_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_2_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_2_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_2_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_2_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_2_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_2_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_3_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_3_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_3_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_3_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_3_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_3_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_4_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_4_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_4_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_4_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_4_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_4_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_4_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_4_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_4_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_4_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_4_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_4_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_4_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_4_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input [2:0] io_child_rebusys // @[issue-slot.scala:52:14] ); wire [15:0] next_uop_out_br_mask; // @[util.scala:104:23] wire io_grant_0 = io_grant; // @[issue-slot.scala:49:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:49:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:49:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_0_0 = io_in_uop_bits_iq_type_0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_1_0 = io_in_uop_bits_iq_type_1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_2_0 = io_in_uop_bits_iq_type_2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_3_0 = io_in_uop_bits_iq_type_3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_0_0 = io_in_uop_bits_fu_code_0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_1_0 = io_in_uop_bits_fu_code_1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_2_0 = io_in_uop_bits_fu_code_2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_3_0 = io_in_uop_bits_fu_code_3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_4_0 = io_in_uop_bits_fu_code_4; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_5_0 = io_in_uop_bits_fu_code_5; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_6_0 = io_in_uop_bits_fu_code_6; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_7_0 = io_in_uop_bits_fu_code_7; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_8_0 = io_in_uop_bits_fu_code_8; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_9_0 = io_in_uop_bits_fu_code_9; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_0 = io_in_uop_bits_iw_issued; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_partial_agen_0 = io_in_uop_bits_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_partial_dgen_0 = io_in_uop_bits_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_iw_p1_speculative_child_0 = io_in_uop_bits_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_iw_p2_speculative_child_0 = io_in_uop_bits_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p1_bypass_hint_0 = io_in_uop_bits_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p2_bypass_hint_0 = io_in_uop_bits_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p3_bypass_hint_0 = io_in_uop_bits_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_dis_col_sel_0 = io_in_uop_bits_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_br_type_0 = io_in_uop_bits_br_type; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sfence_0 = io_in_uop_bits_is_sfence; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_eret_0 = io_in_uop_bits_is_eret; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_rocc_0 = io_in_uop_bits_is_rocc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_mov_0 = io_in_uop_bits_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:49:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:49:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:49:7] wire io_in_uop_bits_imm_rename_0 = io_in_uop_bits_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_imm_sel_0 = io_in_uop_bits_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_pimm_0 = io_in_uop_bits_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_op1_sel_0 = io_in_uop_bits_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_op2_sel_0 = io_in_uop_bits_op2_sel; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ldst_0 = io_in_uop_bits_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_wen_0 = io_in_uop_bits_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren1_0 = io_in_uop_bits_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren2_0 = io_in_uop_bits_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren3_0 = io_in_uop_bits_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_swap12_0 = io_in_uop_bits_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_swap23_0 = io_in_uop_bits_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_ctrl_typeTagIn_0 = io_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_ctrl_typeTagOut_0 = io_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fromint_0 = io_in_uop_bits_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_toint_0 = io_in_uop_bits_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fastpipe_0 = io_in_uop_bits_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fma_0 = io_in_uop_bits_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_div_0 = io_in_uop_bits_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_sqrt_0 = io_in_uop_bits_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_wflags_0 = io_in_uop_bits_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_vec_0 = io_in_uop_bits_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:49:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:49:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:49:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:49:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:49:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_csr_cmd_0 = io_in_uop_bits_csr_cmd; // @[issue-slot.scala:49:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fcn_dw_0 = io_in_uop_bits_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_fcn_op_0 = io_in_uop_bits_fcn_op; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_fp_rm_0 = io_in_uop_bits_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_typ_0 = io_in_uop_bits_fp_typ; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:49:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:49:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:49:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:49:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:49:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:49:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:49:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:49:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:49:7] wire io_squash_grant_0 = io_squash_grant; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_0_bits_uop_inst_0 = io_wakeup_ports_0_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_0_bits_uop_debug_inst_0 = io_wakeup_ports_0_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_rvc_0 = io_wakeup_ports_0_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_0_bits_uop_debug_pc_0 = io_wakeup_ports_0_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_0_0 = io_wakeup_ports_0_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_1_0 = io_wakeup_ports_0_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_2_0 = io_wakeup_ports_0_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_3_0 = io_wakeup_ports_0_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_0_0 = io_wakeup_ports_0_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_1_0 = io_wakeup_ports_0_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_2_0 = io_wakeup_ports_0_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_3_0 = io_wakeup_ports_0_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_4_0 = io_wakeup_ports_0_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_5_0 = io_wakeup_ports_0_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_6_0 = io_wakeup_ports_0_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_7_0 = io_wakeup_ports_0_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_8_0 = io_wakeup_ports_0_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_9_0 = io_wakeup_ports_0_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_0 = io_wakeup_ports_0_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel_0 = io_wakeup_ports_0_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_0_bits_uop_br_mask_0 = io_wakeup_ports_0_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_tag_0 = io_wakeup_ports_0_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_type_0 = io_wakeup_ports_0_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sfb_0 = io_wakeup_ports_0_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_fence_0 = io_wakeup_ports_0_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_fencei_0 = io_wakeup_ports_0_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sfence_0 = io_wakeup_ports_0_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_amo_0 = io_wakeup_ports_0_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_eret_0 = io_wakeup_ports_0_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_0_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_rocc_0 = io_wakeup_ports_0_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_mov_0 = io_wakeup_ports_0_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ftq_idx_0 = io_wakeup_ports_0_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_edge_inst_0 = io_wakeup_ports_0_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_pc_lob_0 = io_wakeup_ports_0_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_taken_0 = io_wakeup_ports_0_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_imm_rename_0 = io_wakeup_ports_0_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_imm_sel_0 = io_wakeup_ports_0_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_pimm_0 = io_wakeup_ports_0_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_0_bits_uop_imm_packed_0 = io_wakeup_ports_0_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_op1_sel_0 = io_wakeup_ports_0_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_op2_sel_0 = io_wakeup_ports_0_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_rob_idx_0 = io_wakeup_ports_0_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ldq_idx_0 = io_wakeup_ports_0_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_stq_idx_0 = io_wakeup_ports_0_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_rxq_idx_0 = io_wakeup_ports_0_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_pdst_0 = io_wakeup_ports_0_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs1_0 = io_wakeup_ports_0_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs2_0 = io_wakeup_ports_0_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs3_0 = io_wakeup_ports_0_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ppred_0 = io_wakeup_ports_0_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs1_busy_0 = io_wakeup_ports_0_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs2_busy_0 = io_wakeup_ports_0_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs3_busy_0 = io_wakeup_ports_0_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_ppred_busy_0 = io_wakeup_ports_0_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_stale_pdst_0 = io_wakeup_ports_0_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_exception_0 = io_wakeup_ports_0_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_0_bits_uop_exc_cause_0 = io_wakeup_ports_0_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_mem_cmd_0 = io_wakeup_ports_0_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_mem_size_0 = io_wakeup_ports_0_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_mem_signed_0 = io_wakeup_ports_0_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_uses_ldq_0 = io_wakeup_ports_0_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_uses_stq_0 = io_wakeup_ports_0_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_unique_0 = io_wakeup_ports_0_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_flush_on_commit_0 = io_wakeup_ports_0_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_csr_cmd_0 = io_wakeup_ports_0_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_0_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_ldst_0 = io_wakeup_ports_0_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs1_0 = io_wakeup_ports_0_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs2_0 = io_wakeup_ports_0_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs3_0 = io_wakeup_ports_0_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_dst_rtype_0 = io_wakeup_ports_0_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype_0 = io_wakeup_ports_0_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype_0 = io_wakeup_ports_0_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_frs3_en_0 = io_wakeup_ports_0_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fcn_dw_0 = io_wakeup_ports_0_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_fcn_op_0 = io_wakeup_ports_0_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_val_0 = io_wakeup_ports_0_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_fp_rm_0 = io_wakeup_ports_0_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_typ_0 = io_wakeup_ports_0_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_0_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_bp_debug_if_0 = io_wakeup_ports_0_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_0_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc_0 = io_wakeup_ports_0_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc_0 = io_wakeup_ports_0_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_bypassable_0 = io_wakeup_ports_0_bits_bypassable; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_speculative_mask_0 = io_wakeup_ports_0_bits_speculative_mask; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_rebusy_0 = io_wakeup_ports_0_bits_rebusy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_1_bits_uop_inst_0 = io_wakeup_ports_1_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_1_bits_uop_debug_inst_0 = io_wakeup_ports_1_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_rvc_0 = io_wakeup_ports_1_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_1_bits_uop_debug_pc_0 = io_wakeup_ports_1_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_0_0 = io_wakeup_ports_1_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_1_0 = io_wakeup_ports_1_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_2_0 = io_wakeup_ports_1_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_3_0 = io_wakeup_ports_1_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_0_0 = io_wakeup_ports_1_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_1_0 = io_wakeup_ports_1_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_2_0 = io_wakeup_ports_1_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_3_0 = io_wakeup_ports_1_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_4_0 = io_wakeup_ports_1_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_5_0 = io_wakeup_ports_1_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_6_0 = io_wakeup_ports_1_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_7_0 = io_wakeup_ports_1_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_8_0 = io_wakeup_ports_1_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_9_0 = io_wakeup_ports_1_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_0 = io_wakeup_ports_1_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel_0 = io_wakeup_ports_1_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_1_bits_uop_br_mask_0 = io_wakeup_ports_1_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_tag_0 = io_wakeup_ports_1_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_type_0 = io_wakeup_ports_1_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sfb_0 = io_wakeup_ports_1_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_fence_0 = io_wakeup_ports_1_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_fencei_0 = io_wakeup_ports_1_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sfence_0 = io_wakeup_ports_1_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_amo_0 = io_wakeup_ports_1_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_eret_0 = io_wakeup_ports_1_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_1_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_rocc_0 = io_wakeup_ports_1_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_mov_0 = io_wakeup_ports_1_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ftq_idx_0 = io_wakeup_ports_1_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_edge_inst_0 = io_wakeup_ports_1_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_pc_lob_0 = io_wakeup_ports_1_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_taken_0 = io_wakeup_ports_1_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_imm_rename_0 = io_wakeup_ports_1_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_imm_sel_0 = io_wakeup_ports_1_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_pimm_0 = io_wakeup_ports_1_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_1_bits_uop_imm_packed_0 = io_wakeup_ports_1_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_op1_sel_0 = io_wakeup_ports_1_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_op2_sel_0 = io_wakeup_ports_1_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_rob_idx_0 = io_wakeup_ports_1_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ldq_idx_0 = io_wakeup_ports_1_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_stq_idx_0 = io_wakeup_ports_1_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_rxq_idx_0 = io_wakeup_ports_1_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_pdst_0 = io_wakeup_ports_1_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs1_0 = io_wakeup_ports_1_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs2_0 = io_wakeup_ports_1_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs3_0 = io_wakeup_ports_1_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ppred_0 = io_wakeup_ports_1_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs1_busy_0 = io_wakeup_ports_1_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs2_busy_0 = io_wakeup_ports_1_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs3_busy_0 = io_wakeup_ports_1_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_ppred_busy_0 = io_wakeup_ports_1_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_stale_pdst_0 = io_wakeup_ports_1_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_exception_0 = io_wakeup_ports_1_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_1_bits_uop_exc_cause_0 = io_wakeup_ports_1_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_mem_cmd_0 = io_wakeup_ports_1_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_mem_size_0 = io_wakeup_ports_1_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_mem_signed_0 = io_wakeup_ports_1_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_uses_ldq_0 = io_wakeup_ports_1_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_uses_stq_0 = io_wakeup_ports_1_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_unique_0 = io_wakeup_ports_1_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_flush_on_commit_0 = io_wakeup_ports_1_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_csr_cmd_0 = io_wakeup_ports_1_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_1_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_ldst_0 = io_wakeup_ports_1_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs1_0 = io_wakeup_ports_1_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs2_0 = io_wakeup_ports_1_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs3_0 = io_wakeup_ports_1_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_dst_rtype_0 = io_wakeup_ports_1_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype_0 = io_wakeup_ports_1_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype_0 = io_wakeup_ports_1_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_frs3_en_0 = io_wakeup_ports_1_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fcn_dw_0 = io_wakeup_ports_1_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_fcn_op_0 = io_wakeup_ports_1_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_val_0 = io_wakeup_ports_1_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_fp_rm_0 = io_wakeup_ports_1_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_typ_0 = io_wakeup_ports_1_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_1_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_bp_debug_if_0 = io_wakeup_ports_1_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_1_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc_0 = io_wakeup_ports_1_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc_0 = io_wakeup_ports_1_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_2_bits_uop_inst_0 = io_wakeup_ports_2_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_2_bits_uop_debug_inst_0 = io_wakeup_ports_2_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_rvc_0 = io_wakeup_ports_2_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_2_bits_uop_debug_pc_0 = io_wakeup_ports_2_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_0_0 = io_wakeup_ports_2_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_1_0 = io_wakeup_ports_2_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_2_0 = io_wakeup_ports_2_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_3_0 = io_wakeup_ports_2_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_0_0 = io_wakeup_ports_2_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_1_0 = io_wakeup_ports_2_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_2_0 = io_wakeup_ports_2_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_3_0 = io_wakeup_ports_2_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_4_0 = io_wakeup_ports_2_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_5_0 = io_wakeup_ports_2_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_6_0 = io_wakeup_ports_2_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_7_0 = io_wakeup_ports_2_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_8_0 = io_wakeup_ports_2_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_9_0 = io_wakeup_ports_2_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_0 = io_wakeup_ports_2_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_dis_col_sel_0 = io_wakeup_ports_2_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_2_bits_uop_br_mask_0 = io_wakeup_ports_2_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_br_tag_0 = io_wakeup_ports_2_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_br_type_0 = io_wakeup_ports_2_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sfb_0 = io_wakeup_ports_2_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_fence_0 = io_wakeup_ports_2_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_fencei_0 = io_wakeup_ports_2_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sfence_0 = io_wakeup_ports_2_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_amo_0 = io_wakeup_ports_2_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_eret_0 = io_wakeup_ports_2_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_2_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_rocc_0 = io_wakeup_ports_2_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_mov_0 = io_wakeup_ports_2_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_ftq_idx_0 = io_wakeup_ports_2_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_edge_inst_0 = io_wakeup_ports_2_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_pc_lob_0 = io_wakeup_ports_2_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_taken_0 = io_wakeup_ports_2_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_imm_rename_0 = io_wakeup_ports_2_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_imm_sel_0 = io_wakeup_ports_2_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_pimm_0 = io_wakeup_ports_2_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_2_bits_uop_imm_packed_0 = io_wakeup_ports_2_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_op1_sel_0 = io_wakeup_ports_2_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_op2_sel_0 = io_wakeup_ports_2_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_rob_idx_0 = io_wakeup_ports_2_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_ldq_idx_0 = io_wakeup_ports_2_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_stq_idx_0 = io_wakeup_ports_2_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_rxq_idx_0 = io_wakeup_ports_2_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_pdst_0 = io_wakeup_ports_2_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs1_0 = io_wakeup_ports_2_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs2_0 = io_wakeup_ports_2_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs3_0 = io_wakeup_ports_2_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_ppred_0 = io_wakeup_ports_2_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs1_busy_0 = io_wakeup_ports_2_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs2_busy_0 = io_wakeup_ports_2_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs3_busy_0 = io_wakeup_ports_2_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_ppred_busy_0 = io_wakeup_ports_2_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_stale_pdst_0 = io_wakeup_ports_2_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_exception_0 = io_wakeup_ports_2_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_2_bits_uop_exc_cause_0 = io_wakeup_ports_2_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_mem_cmd_0 = io_wakeup_ports_2_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_mem_size_0 = io_wakeup_ports_2_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_mem_signed_0 = io_wakeup_ports_2_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_uses_ldq_0 = io_wakeup_ports_2_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_uses_stq_0 = io_wakeup_ports_2_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_unique_0 = io_wakeup_ports_2_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_flush_on_commit_0 = io_wakeup_ports_2_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_csr_cmd_0 = io_wakeup_ports_2_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_2_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_ldst_0 = io_wakeup_ports_2_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs1_0 = io_wakeup_ports_2_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs2_0 = io_wakeup_ports_2_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs3_0 = io_wakeup_ports_2_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_dst_rtype_0 = io_wakeup_ports_2_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype_0 = io_wakeup_ports_2_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype_0 = io_wakeup_ports_2_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_frs3_en_0 = io_wakeup_ports_2_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fcn_dw_0 = io_wakeup_ports_2_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_fcn_op_0 = io_wakeup_ports_2_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_val_0 = io_wakeup_ports_2_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_fp_rm_0 = io_wakeup_ports_2_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_typ_0 = io_wakeup_ports_2_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_2_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_bp_debug_if_0 = io_wakeup_ports_2_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_2_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc_0 = io_wakeup_ports_2_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc_0 = io_wakeup_ports_2_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_3_bits_uop_inst_0 = io_wakeup_ports_3_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_3_bits_uop_debug_inst_0 = io_wakeup_ports_3_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_rvc_0 = io_wakeup_ports_3_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_3_bits_uop_debug_pc_0 = io_wakeup_ports_3_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_0_0 = io_wakeup_ports_3_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_1_0 = io_wakeup_ports_3_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_2_0 = io_wakeup_ports_3_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_3_0 = io_wakeup_ports_3_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_0_0 = io_wakeup_ports_3_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_1_0 = io_wakeup_ports_3_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_2_0 = io_wakeup_ports_3_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_3_0 = io_wakeup_ports_3_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_4_0 = io_wakeup_ports_3_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_5_0 = io_wakeup_ports_3_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_6_0 = io_wakeup_ports_3_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_7_0 = io_wakeup_ports_3_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_8_0 = io_wakeup_ports_3_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_9_0 = io_wakeup_ports_3_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_0 = io_wakeup_ports_3_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_dis_col_sel_0 = io_wakeup_ports_3_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_3_bits_uop_br_mask_0 = io_wakeup_ports_3_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_br_tag_0 = io_wakeup_ports_3_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_br_type_0 = io_wakeup_ports_3_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sfb_0 = io_wakeup_ports_3_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_fence_0 = io_wakeup_ports_3_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_fencei_0 = io_wakeup_ports_3_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sfence_0 = io_wakeup_ports_3_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_amo_0 = io_wakeup_ports_3_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_eret_0 = io_wakeup_ports_3_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_3_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_rocc_0 = io_wakeup_ports_3_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_mov_0 = io_wakeup_ports_3_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_ftq_idx_0 = io_wakeup_ports_3_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_edge_inst_0 = io_wakeup_ports_3_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_pc_lob_0 = io_wakeup_ports_3_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_taken_0 = io_wakeup_ports_3_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_imm_rename_0 = io_wakeup_ports_3_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_imm_sel_0 = io_wakeup_ports_3_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_pimm_0 = io_wakeup_ports_3_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_3_bits_uop_imm_packed_0 = io_wakeup_ports_3_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_op1_sel_0 = io_wakeup_ports_3_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_op2_sel_0 = io_wakeup_ports_3_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_rob_idx_0 = io_wakeup_ports_3_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_ldq_idx_0 = io_wakeup_ports_3_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_stq_idx_0 = io_wakeup_ports_3_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_rxq_idx_0 = io_wakeup_ports_3_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_pdst_0 = io_wakeup_ports_3_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs1_0 = io_wakeup_ports_3_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs2_0 = io_wakeup_ports_3_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs3_0 = io_wakeup_ports_3_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_ppred_0 = io_wakeup_ports_3_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs1_busy_0 = io_wakeup_ports_3_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs2_busy_0 = io_wakeup_ports_3_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs3_busy_0 = io_wakeup_ports_3_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_ppred_busy_0 = io_wakeup_ports_3_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_stale_pdst_0 = io_wakeup_ports_3_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_exception_0 = io_wakeup_ports_3_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_3_bits_uop_exc_cause_0 = io_wakeup_ports_3_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_mem_cmd_0 = io_wakeup_ports_3_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_mem_size_0 = io_wakeup_ports_3_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_mem_signed_0 = io_wakeup_ports_3_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_uses_ldq_0 = io_wakeup_ports_3_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_uses_stq_0 = io_wakeup_ports_3_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_unique_0 = io_wakeup_ports_3_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_flush_on_commit_0 = io_wakeup_ports_3_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_csr_cmd_0 = io_wakeup_ports_3_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_3_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_ldst_0 = io_wakeup_ports_3_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs1_0 = io_wakeup_ports_3_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs2_0 = io_wakeup_ports_3_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs3_0 = io_wakeup_ports_3_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_dst_rtype_0 = io_wakeup_ports_3_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype_0 = io_wakeup_ports_3_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype_0 = io_wakeup_ports_3_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_frs3_en_0 = io_wakeup_ports_3_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fcn_dw_0 = io_wakeup_ports_3_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_fcn_op_0 = io_wakeup_ports_3_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_val_0 = io_wakeup_ports_3_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_fp_rm_0 = io_wakeup_ports_3_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_typ_0 = io_wakeup_ports_3_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_3_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_bp_debug_if_0 = io_wakeup_ports_3_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_3_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc_0 = io_wakeup_ports_3_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc_0 = io_wakeup_ports_3_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_valid_0 = io_wakeup_ports_4_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_4_bits_uop_inst_0 = io_wakeup_ports_4_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_4_bits_uop_debug_inst_0 = io_wakeup_ports_4_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_rvc_0 = io_wakeup_ports_4_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_4_bits_uop_debug_pc_0 = io_wakeup_ports_4_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iq_type_0_0 = io_wakeup_ports_4_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iq_type_1_0 = io_wakeup_ports_4_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iq_type_2_0 = io_wakeup_ports_4_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iq_type_3_0 = io_wakeup_ports_4_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_0_0 = io_wakeup_ports_4_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_1_0 = io_wakeup_ports_4_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_2_0 = io_wakeup_ports_4_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_3_0 = io_wakeup_ports_4_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_4_0 = io_wakeup_ports_4_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_5_0 = io_wakeup_ports_4_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_6_0 = io_wakeup_ports_4_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_7_0 = io_wakeup_ports_4_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_8_0 = io_wakeup_ports_4_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fu_code_9_0 = io_wakeup_ports_4_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_issued_0 = io_wakeup_ports_4_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_4_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_4_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_dis_col_sel_0 = io_wakeup_ports_4_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_4_bits_uop_br_mask_0 = io_wakeup_ports_4_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_4_bits_uop_br_tag_0 = io_wakeup_ports_4_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_4_bits_uop_br_type_0 = io_wakeup_ports_4_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_sfb_0 = io_wakeup_ports_4_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_fence_0 = io_wakeup_ports_4_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_fencei_0 = io_wakeup_ports_4_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_sfence_0 = io_wakeup_ports_4_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_amo_0 = io_wakeup_ports_4_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_eret_0 = io_wakeup_ports_4_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_4_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_rocc_0 = io_wakeup_ports_4_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_mov_0 = io_wakeup_ports_4_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_ftq_idx_0 = io_wakeup_ports_4_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_edge_inst_0 = io_wakeup_ports_4_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_pc_lob_0 = io_wakeup_ports_4_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_taken_0 = io_wakeup_ports_4_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_imm_rename_0 = io_wakeup_ports_4_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_imm_sel_0 = io_wakeup_ports_4_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_pimm_0 = io_wakeup_ports_4_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_4_bits_uop_imm_packed_0 = io_wakeup_ports_4_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_op1_sel_0 = io_wakeup_ports_4_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_op2_sel_0 = io_wakeup_ports_4_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_rob_idx_0 = io_wakeup_ports_4_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_ldq_idx_0 = io_wakeup_ports_4_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_stq_idx_0 = io_wakeup_ports_4_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_rxq_idx_0 = io_wakeup_ports_4_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_pdst_0 = io_wakeup_ports_4_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_prs1_0 = io_wakeup_ports_4_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_prs2_0 = io_wakeup_ports_4_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_prs3_0 = io_wakeup_ports_4_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_ppred_0 = io_wakeup_ports_4_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_prs1_busy_0 = io_wakeup_ports_4_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_prs2_busy_0 = io_wakeup_ports_4_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_prs3_busy_0 = io_wakeup_ports_4_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_ppred_busy_0 = io_wakeup_ports_4_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_4_bits_uop_stale_pdst_0 = io_wakeup_ports_4_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_exception_0 = io_wakeup_ports_4_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_4_bits_uop_exc_cause_0 = io_wakeup_ports_4_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_mem_cmd_0 = io_wakeup_ports_4_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_mem_size_0 = io_wakeup_ports_4_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_mem_signed_0 = io_wakeup_ports_4_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_uses_ldq_0 = io_wakeup_ports_4_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_uses_stq_0 = io_wakeup_ports_4_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_is_unique_0 = io_wakeup_ports_4_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_flush_on_commit_0 = io_wakeup_ports_4_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_csr_cmd_0 = io_wakeup_ports_4_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_4_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_ldst_0 = io_wakeup_ports_4_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_lrs1_0 = io_wakeup_ports_4_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_lrs2_0 = io_wakeup_ports_4_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_4_bits_uop_lrs3_0 = io_wakeup_ports_4_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_dst_rtype_0 = io_wakeup_ports_4_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_lrs1_rtype_0 = io_wakeup_ports_4_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_lrs2_rtype_0 = io_wakeup_ports_4_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_frs3_en_0 = io_wakeup_ports_4_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fcn_dw_0 = io_wakeup_ports_4_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_4_bits_uop_fcn_op_0 = io_wakeup_ports_4_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_fp_val_0 = io_wakeup_ports_4_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_fp_rm_0 = io_wakeup_ports_4_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_4_bits_uop_fp_typ_0 = io_wakeup_ports_4_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_4_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_4_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_4_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_bp_debug_if_0 = io_wakeup_ports_4_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_4_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_debug_fsrc_0 = io_wakeup_ports_4_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_uop_debug_tsrc_0 = io_wakeup_ports_4_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire [2:0] io_child_rebusys_0 = io_child_rebusys; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:49:7] wire prs1_rebusys_1 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_2 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_3 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_4 = 1'h0; // @[issue-slot.scala:102:91] wire prs2_rebusys_1 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_2 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_3 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_4 = 1'h0; // @[issue-slot.scala:103:91] wire _next_uop_iw_p1_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _next_uop_iw_p2_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _next_uop_iw_p3_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _iss_ready_T_6 = 1'h0; // @[issue-slot.scala:136:131] wire [1:0] io_iss_uop_lrs2_rtype = 2'h2; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-slot.scala:49:7] wire [2:0] _next_uop_iw_p1_speculative_child_T_1 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _next_uop_iw_p2_speculative_child_T_1 = 3'h0; // @[Mux.scala:30:73] wire io_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_4_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire _iss_ready_T_7 = 1'h1; // @[issue-slot.scala:136:110] wire [2:0] io_wakeup_ports_2_bits_speculative_mask = 3'h1; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_speculative_mask = 3'h2; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_4_bits_speculative_mask = 3'h4; // @[issue-slot.scala:49:7] wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:49:7] wire _io_will_be_valid_T_1; // @[issue-slot.scala:65:34] wire _io_request_T_4; // @[issue-slot.scala:140:51] wire [6:0] io_iss_uop_prs1_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs2_0 = io_iss_uop_prs1_0; // @[issue-slot.scala:49:7] wire [31:0] next_uop_inst; // @[issue-slot.scala:59:28] wire [31:0] next_uop_debug_inst; // @[issue-slot.scala:59:28] wire next_uop_is_rvc; // @[issue-slot.scala:59:28] wire [39:0] next_uop_debug_pc; // @[issue-slot.scala:59:28] wire next_uop_iq_type_0; // @[issue-slot.scala:59:28] wire next_uop_iq_type_1; // @[issue-slot.scala:59:28] wire next_uop_iq_type_2; // @[issue-slot.scala:59:28] wire next_uop_iq_type_3; // @[issue-slot.scala:59:28] wire next_uop_fu_code_0; // @[issue-slot.scala:59:28] wire next_uop_fu_code_1; // @[issue-slot.scala:59:28] wire next_uop_fu_code_2; // @[issue-slot.scala:59:28] wire next_uop_fu_code_3; // @[issue-slot.scala:59:28] wire next_uop_fu_code_4; // @[issue-slot.scala:59:28] wire next_uop_fu_code_5; // @[issue-slot.scala:59:28] wire next_uop_fu_code_6; // @[issue-slot.scala:59:28] wire next_uop_fu_code_7; // @[issue-slot.scala:59:28] wire next_uop_fu_code_8; // @[issue-slot.scala:59:28] wire next_uop_fu_code_9; // @[issue-slot.scala:59:28] wire next_uop_iw_issued; // @[issue-slot.scala:59:28] wire next_uop_iw_issued_partial_agen; // @[issue-slot.scala:59:28] wire next_uop_iw_issued_partial_dgen; // @[issue-slot.scala:59:28] wire [2:0] next_uop_iw_p1_speculative_child; // @[issue-slot.scala:59:28] wire [2:0] next_uop_iw_p2_speculative_child; // @[issue-slot.scala:59:28] wire next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:59:28] wire next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:59:28] wire next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:59:28] wire [2:0] next_uop_dis_col_sel; // @[issue-slot.scala:59:28] wire [15:0] next_uop_br_mask; // @[issue-slot.scala:59:28] wire [3:0] next_uop_br_tag; // @[issue-slot.scala:59:28] wire [3:0] next_uop_br_type; // @[issue-slot.scala:59:28] wire next_uop_is_sfb; // @[issue-slot.scala:59:28] wire next_uop_is_fence; // @[issue-slot.scala:59:28] wire next_uop_is_fencei; // @[issue-slot.scala:59:28] wire next_uop_is_sfence; // @[issue-slot.scala:59:28] wire next_uop_is_amo; // @[issue-slot.scala:59:28] wire next_uop_is_eret; // @[issue-slot.scala:59:28] wire next_uop_is_sys_pc2epc; // @[issue-slot.scala:59:28] wire next_uop_is_rocc; // @[issue-slot.scala:59:28] wire next_uop_is_mov; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ftq_idx; // @[issue-slot.scala:59:28] wire next_uop_edge_inst; // @[issue-slot.scala:59:28] wire [5:0] next_uop_pc_lob; // @[issue-slot.scala:59:28] wire next_uop_taken; // @[issue-slot.scala:59:28] wire next_uop_imm_rename; // @[issue-slot.scala:59:28] wire [2:0] next_uop_imm_sel; // @[issue-slot.scala:59:28] wire [4:0] next_uop_pimm; // @[issue-slot.scala:59:28] wire [19:0] next_uop_imm_packed; // @[issue-slot.scala:59:28] wire [1:0] next_uop_op1_sel; // @[issue-slot.scala:59:28] wire [2:0] next_uop_op2_sel; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ldst; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_wen; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren1; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren2; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren3; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_swap12; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_swap23; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fromint; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_toint; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fma; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_div; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_wflags; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_vec; // @[issue-slot.scala:59:28] wire [6:0] next_uop_rob_idx; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ldq_idx; // @[issue-slot.scala:59:28] wire [4:0] next_uop_stq_idx; // @[issue-slot.scala:59:28] wire [1:0] next_uop_rxq_idx; // @[issue-slot.scala:59:28] wire [6:0] next_uop_pdst; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs1; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs2; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs3; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ppred; // @[issue-slot.scala:59:28] wire next_uop_prs1_busy; // @[issue-slot.scala:59:28] wire next_uop_prs2_busy; // @[issue-slot.scala:59:28] wire next_uop_prs3_busy; // @[issue-slot.scala:59:28] wire next_uop_ppred_busy; // @[issue-slot.scala:59:28] wire [6:0] next_uop_stale_pdst; // @[issue-slot.scala:59:28] wire next_uop_exception; // @[issue-slot.scala:59:28] wire [63:0] next_uop_exc_cause; // @[issue-slot.scala:59:28] wire [4:0] next_uop_mem_cmd; // @[issue-slot.scala:59:28] wire [1:0] next_uop_mem_size; // @[issue-slot.scala:59:28] wire next_uop_mem_signed; // @[issue-slot.scala:59:28] wire next_uop_uses_ldq; // @[issue-slot.scala:59:28] wire next_uop_uses_stq; // @[issue-slot.scala:59:28] wire next_uop_is_unique; // @[issue-slot.scala:59:28] wire next_uop_flush_on_commit; // @[issue-slot.scala:59:28] wire [2:0] next_uop_csr_cmd; // @[issue-slot.scala:59:28] wire next_uop_ldst_is_rs1; // @[issue-slot.scala:59:28] wire [5:0] next_uop_ldst; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs1; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs2; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs3; // @[issue-slot.scala:59:28] wire [1:0] next_uop_dst_rtype; // @[issue-slot.scala:59:28] wire [1:0] next_uop_lrs1_rtype; // @[issue-slot.scala:59:28] wire [1:0] next_uop_lrs2_rtype; // @[issue-slot.scala:59:28] wire next_uop_frs3_en; // @[issue-slot.scala:59:28] wire next_uop_fcn_dw; // @[issue-slot.scala:59:28] wire [4:0] next_uop_fcn_op; // @[issue-slot.scala:59:28] wire next_uop_fp_val; // @[issue-slot.scala:59:28] wire [2:0] next_uop_fp_rm; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_typ; // @[issue-slot.scala:59:28] wire next_uop_xcpt_pf_if; // @[issue-slot.scala:59:28] wire next_uop_xcpt_ae_if; // @[issue-slot.scala:59:28] wire next_uop_xcpt_ma_if; // @[issue-slot.scala:59:28] wire next_uop_bp_debug_if; // @[issue-slot.scala:59:28] wire next_uop_bp_xcpt_if; // @[issue-slot.scala:59:28] wire [2:0] next_uop_debug_fsrc; // @[issue-slot.scala:59:28] wire [2:0] next_uop_debug_tsrc; // @[issue-slot.scala:59:28] wire io_iss_uop_iq_type_0_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_0_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_4_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_5_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_6_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_7_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_8_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_9_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7] wire [31:0] io_iss_uop_inst_0; // @[issue-slot.scala:49:7] wire [31:0] io_iss_uop_debug_inst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_rvc_0; // @[issue-slot.scala:49:7] wire [39:0] io_iss_uop_debug_pc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_partial_agen_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_partial_dgen_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_dis_col_sel_0; // @[issue-slot.scala:49:7] wire [15:0] io_iss_uop_br_mask_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_br_tag_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_br_type_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sfb_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_fence_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_fencei_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sfence_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_amo_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_eret_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_rocc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_mov_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ftq_idx_0; // @[issue-slot.scala:49:7] wire io_iss_uop_edge_inst_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_pc_lob_0; // @[issue-slot.scala:49:7] wire io_iss_uop_taken_0; // @[issue-slot.scala:49:7] wire io_iss_uop_imm_rename_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_imm_sel_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_pimm_0; // @[issue-slot.scala:49:7] wire [19:0] io_iss_uop_imm_packed_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_op1_sel_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_op2_sel_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_rob_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ldq_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_stq_idx_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_rxq_idx_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_pdst_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs3_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ppred_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs1_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs2_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs3_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_ppred_busy_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_stale_pdst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_exception_0; // @[issue-slot.scala:49:7] wire [63:0] io_iss_uop_exc_cause_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_mem_cmd_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_mem_size_0; // @[issue-slot.scala:49:7] wire io_iss_uop_mem_signed_0; // @[issue-slot.scala:49:7] wire io_iss_uop_uses_ldq_0; // @[issue-slot.scala:49:7] wire io_iss_uop_uses_stq_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_unique_0; // @[issue-slot.scala:49:7] wire io_iss_uop_flush_on_commit_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_csr_cmd_0; // @[issue-slot.scala:49:7] wire io_iss_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_ldst_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs2_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs3_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_dst_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7] wire io_iss_uop_frs3_en_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fcn_dw_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_fcn_op_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_val_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_fp_rm_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_typ_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_bp_debug_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_debug_fsrc_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_debug_tsrc_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_0_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_1_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_2_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_0_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_1_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_2_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_4_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_5_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_6_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_7_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_8_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_9_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:49:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:49:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_partial_agen_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_partial_dgen_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_dis_col_sel_0; // @[issue-slot.scala:49:7] wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_br_type_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sfence_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_eret_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_rocc_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_mov_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:49:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:49:7] wire io_out_uop_taken_0; // @[issue-slot.scala:49:7] wire io_out_uop_imm_rename_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_imm_sel_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_pimm_0; // @[issue-slot.scala:49:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_op1_sel_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_op2_sel_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:49:7] wire io_out_uop_exception_0; // @[issue-slot.scala:49:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:49:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:49:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:49:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:49:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_csr_cmd_0; // @[issue-slot.scala:49:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:49:7] wire io_out_uop_fcn_dw_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_fcn_op_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_fp_rm_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_typ_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:49:7] wire io_valid_0; // @[issue-slot.scala:49:7] wire io_will_be_valid_0; // @[issue-slot.scala:49:7] wire io_request_0; // @[issue-slot.scala:49:7] reg slot_valid; // @[issue-slot.scala:55:27] assign io_valid_0 = slot_valid; // @[issue-slot.scala:49:7, :55:27] reg [31:0] slot_uop_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:49:7, :56:21] wire [31:0] next_uop_out_inst = slot_uop_inst; // @[util.scala:104:23] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:49:7, :56:21] wire [31:0] next_uop_out_debug_inst = slot_uop_debug_inst; // @[util.scala:104:23] reg slot_uop_is_rvc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_rvc = slot_uop_is_rvc; // @[util.scala:104:23] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:49:7, :56:21] wire [39:0] next_uop_out_debug_pc = slot_uop_debug_pc; // @[util.scala:104:23] reg slot_uop_iq_type_0; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_0_0 = slot_uop_iq_type_0; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_0 = slot_uop_iq_type_0; // @[util.scala:104:23] reg slot_uop_iq_type_1; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_1_0 = slot_uop_iq_type_1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_1 = slot_uop_iq_type_1; // @[util.scala:104:23] reg slot_uop_iq_type_2; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_2_0 = slot_uop_iq_type_2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_2 = slot_uop_iq_type_2; // @[util.scala:104:23] reg slot_uop_iq_type_3; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_3_0 = slot_uop_iq_type_3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_3 = slot_uop_iq_type_3; // @[util.scala:104:23] reg slot_uop_fu_code_0; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_0_0 = slot_uop_fu_code_0; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_0 = slot_uop_fu_code_0; // @[util.scala:104:23] reg slot_uop_fu_code_1; // @[issue-slot.scala:56:21] wire next_uop_out_fu_code_1 = slot_uop_fu_code_1; // @[util.scala:104:23] reg slot_uop_fu_code_2; // @[issue-slot.scala:56:21] wire next_uop_out_fu_code_2 = slot_uop_fu_code_2; // @[util.scala:104:23] reg slot_uop_fu_code_3; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_3_0 = slot_uop_fu_code_3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_3 = slot_uop_fu_code_3; // @[util.scala:104:23] reg slot_uop_fu_code_4; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_4_0 = slot_uop_fu_code_4; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_4 = slot_uop_fu_code_4; // @[util.scala:104:23] reg slot_uop_fu_code_5; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_5_0 = slot_uop_fu_code_5; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_5 = slot_uop_fu_code_5; // @[util.scala:104:23] reg slot_uop_fu_code_6; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_6_0 = slot_uop_fu_code_6; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_6 = slot_uop_fu_code_6; // @[util.scala:104:23] reg slot_uop_fu_code_7; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_7_0 = slot_uop_fu_code_7; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_7 = slot_uop_fu_code_7; // @[util.scala:104:23] reg slot_uop_fu_code_8; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_8_0 = slot_uop_fu_code_8; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_8 = slot_uop_fu_code_8; // @[util.scala:104:23] reg slot_uop_fu_code_9; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_9_0 = slot_uop_fu_code_9; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_9 = slot_uop_fu_code_9; // @[util.scala:104:23] reg slot_uop_iw_issued; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_issued_0 = slot_uop_iw_issued; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_issued = slot_uop_iw_issued; // @[util.scala:104:23] reg slot_uop_iw_issued_partial_agen; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_issued_partial_agen_0 = slot_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_issued_partial_agen = slot_uop_iw_issued_partial_agen; // @[util.scala:104:23] reg slot_uop_iw_issued_partial_dgen; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_issued_partial_dgen_0 = slot_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_issued_partial_dgen = slot_uop_iw_issued_partial_dgen; // @[util.scala:104:23] reg [2:0] slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p1_speculative_child_0 = slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_iw_p1_speculative_child = slot_uop_iw_p1_speculative_child; // @[util.scala:104:23] reg [2:0] slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p2_speculative_child_0 = slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_iw_p2_speculative_child = slot_uop_iw_p2_speculative_child; // @[util.scala:104:23] reg slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:56:21] wire next_uop_out_iw_p1_bypass_hint = slot_uop_iw_p1_bypass_hint; // @[util.scala:104:23] reg slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p2_bypass_hint_0 = slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p2_bypass_hint = slot_uop_iw_p2_bypass_hint; // @[util.scala:104:23] reg slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p3_bypass_hint_0 = slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p3_bypass_hint = slot_uop_iw_p3_bypass_hint; // @[util.scala:104:23] reg [2:0] slot_uop_dis_col_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_dis_col_sel_0 = slot_uop_dis_col_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_dis_col_sel = slot_uop_dis_col_sel; // @[util.scala:104:23] reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:56:21] assign io_iss_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:49:7, :56:21] reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:56:21] assign io_iss_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_br_tag = slot_uop_br_tag; // @[util.scala:104:23] reg [3:0] slot_uop_br_type; // @[issue-slot.scala:56:21] assign io_iss_uop_br_type_0 = slot_uop_br_type; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_br_type = slot_uop_br_type; // @[util.scala:104:23] reg slot_uop_is_sfb; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sfb = slot_uop_is_sfb; // @[util.scala:104:23] reg slot_uop_is_fence; // @[issue-slot.scala:56:21] assign io_iss_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_fence = slot_uop_is_fence; // @[util.scala:104:23] reg slot_uop_is_fencei; // @[issue-slot.scala:56:21] assign io_iss_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_fencei = slot_uop_is_fencei; // @[util.scala:104:23] reg slot_uop_is_sfence; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sfence_0 = slot_uop_is_sfence; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sfence = slot_uop_is_sfence; // @[util.scala:104:23] reg slot_uop_is_amo; // @[issue-slot.scala:56:21] assign io_iss_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_amo = slot_uop_is_amo; // @[util.scala:104:23] reg slot_uop_is_eret; // @[issue-slot.scala:56:21] assign io_iss_uop_is_eret_0 = slot_uop_is_eret; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_eret = slot_uop_is_eret; // @[util.scala:104:23] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sys_pc2epc = slot_uop_is_sys_pc2epc; // @[util.scala:104:23] reg slot_uop_is_rocc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_rocc_0 = slot_uop_is_rocc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_rocc = slot_uop_is_rocc; // @[util.scala:104:23] reg slot_uop_is_mov; // @[issue-slot.scala:56:21] assign io_iss_uop_is_mov_0 = slot_uop_is_mov; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_mov = slot_uop_is_mov; // @[util.scala:104:23] reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ftq_idx = slot_uop_ftq_idx; // @[util.scala:104:23] reg slot_uop_edge_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_edge_inst = slot_uop_edge_inst; // @[util.scala:104:23] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:56:21] assign io_iss_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_pc_lob = slot_uop_pc_lob; // @[util.scala:104:23] reg slot_uop_taken; // @[issue-slot.scala:56:21] assign io_iss_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_taken = slot_uop_taken; // @[util.scala:104:23] reg slot_uop_imm_rename; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_rename_0 = slot_uop_imm_rename; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_imm_rename = slot_uop_imm_rename; // @[util.scala:104:23] reg [2:0] slot_uop_imm_sel; // @[issue-slot.scala:56:21] wire [2:0] next_uop_out_imm_sel = slot_uop_imm_sel; // @[util.scala:104:23] reg [4:0] slot_uop_pimm; // @[issue-slot.scala:56:21] assign io_iss_uop_pimm_0 = slot_uop_pimm; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_pimm = slot_uop_pimm; // @[util.scala:104:23] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:49:7, :56:21] wire [19:0] next_uop_out_imm_packed = slot_uop_imm_packed; // @[util.scala:104:23] reg [1:0] slot_uop_op1_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_op1_sel_0 = slot_uop_op1_sel; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_op1_sel = slot_uop_op1_sel; // @[util.scala:104:23] reg [2:0] slot_uop_op2_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_op2_sel_0 = slot_uop_op2_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_op2_sel = slot_uop_op2_sel; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ldst_0 = slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ldst = slot_uop_fp_ctrl_ldst; // @[util.scala:104:23] reg slot_uop_fp_ctrl_wen; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_wen_0 = slot_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_wen = slot_uop_fp_ctrl_wen; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren1_0 = slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren1 = slot_uop_fp_ctrl_ren1; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren2_0 = slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren2 = slot_uop_fp_ctrl_ren2; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren3_0 = slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren3 = slot_uop_fp_ctrl_ren3; // @[util.scala:104:23] reg slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_swap12_0 = slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_swap12 = slot_uop_fp_ctrl_swap12; // @[util.scala:104:23] reg slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_swap23_0 = slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_swap23 = slot_uop_fp_ctrl_swap23; // @[util.scala:104:23] reg [1:0] slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_typeTagIn_0 = slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_ctrl_typeTagIn = slot_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23] reg [1:0] slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_typeTagOut_0 = slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_ctrl_typeTagOut = slot_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fromint_0 = slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fromint = slot_uop_fp_ctrl_fromint; // @[util.scala:104:23] reg slot_uop_fp_ctrl_toint; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_toint_0 = slot_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_toint = slot_uop_fp_ctrl_toint; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fastpipe_0 = slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fastpipe = slot_uop_fp_ctrl_fastpipe; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fma; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fma_0 = slot_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fma = slot_uop_fp_ctrl_fma; // @[util.scala:104:23] reg slot_uop_fp_ctrl_div; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_div_0 = slot_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_div = slot_uop_fp_ctrl_div; // @[util.scala:104:23] reg slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_sqrt_0 = slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_sqrt = slot_uop_fp_ctrl_sqrt; // @[util.scala:104:23] reg slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_wflags_0 = slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_wflags = slot_uop_fp_ctrl_wflags; // @[util.scala:104:23] reg slot_uop_fp_ctrl_vec; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_vec_0 = slot_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_vec = slot_uop_fp_ctrl_vec; // @[util.scala:104:23] reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_rob_idx = slot_uop_rob_idx; // @[util.scala:104:23] reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ldq_idx = slot_uop_ldq_idx; // @[util.scala:104:23] reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_stq_idx = slot_uop_stq_idx; // @[util.scala:104:23] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_rxq_idx = slot_uop_rxq_idx; // @[util.scala:104:23] reg [6:0] slot_uop_pdst; // @[issue-slot.scala:56:21] assign io_iss_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_pdst = slot_uop_pdst; // @[util.scala:104:23] reg [6:0] slot_uop_prs1; // @[issue-slot.scala:56:21] wire [6:0] next_uop_out_prs1 = slot_uop_prs1; // @[util.scala:104:23] reg [6:0] slot_uop_prs2; // @[issue-slot.scala:56:21] wire [6:0] next_uop_out_prs2 = slot_uop_prs2; // @[util.scala:104:23] reg [6:0] slot_uop_prs3; // @[issue-slot.scala:56:21] assign io_iss_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs3 = slot_uop_prs3; // @[util.scala:104:23] reg [4:0] slot_uop_ppred; // @[issue-slot.scala:56:21] assign io_iss_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ppred = slot_uop_ppred; // @[util.scala:104:23] reg slot_uop_prs1_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs1_busy = slot_uop_prs1_busy; // @[util.scala:104:23] reg slot_uop_prs2_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs2_busy = slot_uop_prs2_busy; // @[util.scala:104:23] reg slot_uop_prs3_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs3_busy = slot_uop_prs3_busy; // @[util.scala:104:23] reg slot_uop_ppred_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_ppred_busy = slot_uop_ppred_busy; // @[util.scala:104:23] wire _iss_ready_T_3 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :136:88] wire _agen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :137:95] wire _dgen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :138:95] reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:56:21] assign io_iss_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_stale_pdst = slot_uop_stale_pdst; // @[util.scala:104:23] reg slot_uop_exception; // @[issue-slot.scala:56:21] assign io_iss_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_exception = slot_uop_exception; // @[util.scala:104:23] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:56:21] assign io_iss_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:49:7, :56:21] wire [63:0] next_uop_out_exc_cause = slot_uop_exc_cause; // @[util.scala:104:23] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_mem_cmd = slot_uop_mem_cmd; // @[util.scala:104:23] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_mem_size = slot_uop_mem_size; // @[util.scala:104:23] reg slot_uop_mem_signed; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_mem_signed = slot_uop_mem_signed; // @[util.scala:104:23] reg slot_uop_uses_ldq; // @[issue-slot.scala:56:21] assign io_iss_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_uses_ldq = slot_uop_uses_ldq; // @[util.scala:104:23] reg slot_uop_uses_stq; // @[issue-slot.scala:56:21] assign io_iss_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_uses_stq = slot_uop_uses_stq; // @[util.scala:104:23] reg slot_uop_is_unique; // @[issue-slot.scala:56:21] assign io_iss_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_unique = slot_uop_is_unique; // @[util.scala:104:23] reg slot_uop_flush_on_commit; // @[issue-slot.scala:56:21] assign io_iss_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_flush_on_commit = slot_uop_flush_on_commit; // @[util.scala:104:23] reg [2:0] slot_uop_csr_cmd; // @[issue-slot.scala:56:21] assign io_iss_uop_csr_cmd_0 = slot_uop_csr_cmd; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_csr_cmd = slot_uop_csr_cmd; // @[util.scala:104:23] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:56:21] assign io_iss_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_ldst_is_rs1 = slot_uop_ldst_is_rs1; // @[util.scala:104:23] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:56:21] assign io_iss_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_ldst = slot_uop_ldst; // @[util.scala:104:23] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs1 = slot_uop_lrs1; // @[util.scala:104:23] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs2 = slot_uop_lrs2; // @[util.scala:104:23] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs3 = slot_uop_lrs3; // @[util.scala:104:23] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_dst_rtype = slot_uop_dst_rtype; // @[util.scala:104:23] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:56:21] wire [1:0] next_uop_out_lrs1_rtype = slot_uop_lrs1_rtype; // @[util.scala:104:23] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:56:21] wire [1:0] next_uop_out_lrs2_rtype = slot_uop_lrs2_rtype; // @[util.scala:104:23] reg slot_uop_frs3_en; // @[issue-slot.scala:56:21] assign io_iss_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_frs3_en = slot_uop_frs3_en; // @[util.scala:104:23] reg slot_uop_fcn_dw; // @[issue-slot.scala:56:21] assign io_iss_uop_fcn_dw_0 = slot_uop_fcn_dw; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fcn_dw = slot_uop_fcn_dw; // @[util.scala:104:23] reg [4:0] slot_uop_fcn_op; // @[issue-slot.scala:56:21] assign io_iss_uop_fcn_op_0 = slot_uop_fcn_op; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_fcn_op = slot_uop_fcn_op; // @[util.scala:104:23] reg slot_uop_fp_val; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_val = slot_uop_fp_val; // @[util.scala:104:23] reg [2:0] slot_uop_fp_rm; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_rm_0 = slot_uop_fp_rm; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_fp_rm = slot_uop_fp_rm; // @[util.scala:104:23] reg [1:0] slot_uop_fp_typ; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_typ_0 = slot_uop_fp_typ; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_typ = slot_uop_fp_typ; // @[util.scala:104:23] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_pf_if = slot_uop_xcpt_pf_if; // @[util.scala:104:23] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_ae_if = slot_uop_xcpt_ae_if; // @[util.scala:104:23] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_ma_if = slot_uop_xcpt_ma_if; // @[util.scala:104:23] reg slot_uop_bp_debug_if; // @[issue-slot.scala:56:21] assign io_iss_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_bp_debug_if = slot_uop_bp_debug_if; // @[util.scala:104:23] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:56:21] assign io_iss_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_bp_xcpt_if = slot_uop_bp_xcpt_if; // @[util.scala:104:23] reg [2:0] slot_uop_debug_fsrc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_debug_fsrc = slot_uop_debug_fsrc; // @[util.scala:104:23] reg [2:0] slot_uop_debug_tsrc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_debug_tsrc = slot_uop_debug_tsrc; // @[util.scala:104:23] wire next_valid; // @[issue-slot.scala:58:28] assign next_uop_inst = next_uop_out_inst; // @[util.scala:104:23] assign next_uop_debug_inst = next_uop_out_debug_inst; // @[util.scala:104:23] assign next_uop_is_rvc = next_uop_out_is_rvc; // @[util.scala:104:23] assign next_uop_debug_pc = next_uop_out_debug_pc; // @[util.scala:104:23] assign next_uop_iq_type_0 = next_uop_out_iq_type_0; // @[util.scala:104:23] assign next_uop_iq_type_1 = next_uop_out_iq_type_1; // @[util.scala:104:23] assign next_uop_iq_type_2 = next_uop_out_iq_type_2; // @[util.scala:104:23] assign next_uop_iq_type_3 = next_uop_out_iq_type_3; // @[util.scala:104:23] assign next_uop_fu_code_0 = next_uop_out_fu_code_0; // @[util.scala:104:23] assign next_uop_fu_code_3 = next_uop_out_fu_code_3; // @[util.scala:104:23] assign next_uop_fu_code_4 = next_uop_out_fu_code_4; // @[util.scala:104:23] assign next_uop_fu_code_5 = next_uop_out_fu_code_5; // @[util.scala:104:23] assign next_uop_fu_code_6 = next_uop_out_fu_code_6; // @[util.scala:104:23] assign next_uop_fu_code_7 = next_uop_out_fu_code_7; // @[util.scala:104:23] assign next_uop_fu_code_8 = next_uop_out_fu_code_8; // @[util.scala:104:23] assign next_uop_fu_code_9 = next_uop_out_fu_code_9; // @[util.scala:104:23] wire [15:0] _next_uop_out_br_mask_T_1; // @[util.scala:93:25] assign next_uop_dis_col_sel = next_uop_out_dis_col_sel; // @[util.scala:104:23] assign next_uop_br_mask = next_uop_out_br_mask; // @[util.scala:104:23] assign next_uop_br_tag = next_uop_out_br_tag; // @[util.scala:104:23] assign next_uop_br_type = next_uop_out_br_type; // @[util.scala:104:23] assign next_uop_is_sfb = next_uop_out_is_sfb; // @[util.scala:104:23] assign next_uop_is_fence = next_uop_out_is_fence; // @[util.scala:104:23] assign next_uop_is_fencei = next_uop_out_is_fencei; // @[util.scala:104:23] assign next_uop_is_sfence = next_uop_out_is_sfence; // @[util.scala:104:23] assign next_uop_is_amo = next_uop_out_is_amo; // @[util.scala:104:23] assign next_uop_is_eret = next_uop_out_is_eret; // @[util.scala:104:23] assign next_uop_is_sys_pc2epc = next_uop_out_is_sys_pc2epc; // @[util.scala:104:23] assign next_uop_is_rocc = next_uop_out_is_rocc; // @[util.scala:104:23] assign next_uop_is_mov = next_uop_out_is_mov; // @[util.scala:104:23] assign next_uop_ftq_idx = next_uop_out_ftq_idx; // @[util.scala:104:23] assign next_uop_edge_inst = next_uop_out_edge_inst; // @[util.scala:104:23] assign next_uop_pc_lob = next_uop_out_pc_lob; // @[util.scala:104:23] assign next_uop_taken = next_uop_out_taken; // @[util.scala:104:23] assign next_uop_imm_rename = next_uop_out_imm_rename; // @[util.scala:104:23] assign next_uop_imm_sel = next_uop_out_imm_sel; // @[util.scala:104:23] assign next_uop_pimm = next_uop_out_pimm; // @[util.scala:104:23] assign next_uop_imm_packed = next_uop_out_imm_packed; // @[util.scala:104:23] assign next_uop_op1_sel = next_uop_out_op1_sel; // @[util.scala:104:23] assign next_uop_op2_sel = next_uop_out_op2_sel; // @[util.scala:104:23] assign next_uop_fp_ctrl_ldst = next_uop_out_fp_ctrl_ldst; // @[util.scala:104:23] assign next_uop_fp_ctrl_wen = next_uop_out_fp_ctrl_wen; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren1 = next_uop_out_fp_ctrl_ren1; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren2 = next_uop_out_fp_ctrl_ren2; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren3 = next_uop_out_fp_ctrl_ren3; // @[util.scala:104:23] assign next_uop_fp_ctrl_swap12 = next_uop_out_fp_ctrl_swap12; // @[util.scala:104:23] assign next_uop_fp_ctrl_swap23 = next_uop_out_fp_ctrl_swap23; // @[util.scala:104:23] assign next_uop_fp_ctrl_typeTagIn = next_uop_out_fp_ctrl_typeTagIn; // @[util.scala:104:23] assign next_uop_fp_ctrl_typeTagOut = next_uop_out_fp_ctrl_typeTagOut; // @[util.scala:104:23] assign next_uop_fp_ctrl_fromint = next_uop_out_fp_ctrl_fromint; // @[util.scala:104:23] assign next_uop_fp_ctrl_toint = next_uop_out_fp_ctrl_toint; // @[util.scala:104:23] assign next_uop_fp_ctrl_fastpipe = next_uop_out_fp_ctrl_fastpipe; // @[util.scala:104:23] assign next_uop_fp_ctrl_fma = next_uop_out_fp_ctrl_fma; // @[util.scala:104:23] assign next_uop_fp_ctrl_div = next_uop_out_fp_ctrl_div; // @[util.scala:104:23] assign next_uop_fp_ctrl_sqrt = next_uop_out_fp_ctrl_sqrt; // @[util.scala:104:23] assign next_uop_fp_ctrl_wflags = next_uop_out_fp_ctrl_wflags; // @[util.scala:104:23] assign next_uop_fp_ctrl_vec = next_uop_out_fp_ctrl_vec; // @[util.scala:104:23] assign next_uop_rob_idx = next_uop_out_rob_idx; // @[util.scala:104:23] assign next_uop_ldq_idx = next_uop_out_ldq_idx; // @[util.scala:104:23] assign next_uop_stq_idx = next_uop_out_stq_idx; // @[util.scala:104:23] assign next_uop_rxq_idx = next_uop_out_rxq_idx; // @[util.scala:104:23] assign next_uop_pdst = next_uop_out_pdst; // @[util.scala:104:23] assign next_uop_prs1 = next_uop_out_prs1; // @[util.scala:104:23] assign next_uop_prs2 = next_uop_out_prs2; // @[util.scala:104:23] assign next_uop_prs3 = next_uop_out_prs3; // @[util.scala:104:23] assign next_uop_ppred = next_uop_out_ppred; // @[util.scala:104:23] assign next_uop_ppred_busy = next_uop_out_ppred_busy; // @[util.scala:104:23] assign next_uop_stale_pdst = next_uop_out_stale_pdst; // @[util.scala:104:23] assign next_uop_exception = next_uop_out_exception; // @[util.scala:104:23] assign next_uop_exc_cause = next_uop_out_exc_cause; // @[util.scala:104:23] assign next_uop_mem_cmd = next_uop_out_mem_cmd; // @[util.scala:104:23] assign next_uop_mem_size = next_uop_out_mem_size; // @[util.scala:104:23] assign next_uop_mem_signed = next_uop_out_mem_signed; // @[util.scala:104:23] assign next_uop_uses_ldq = next_uop_out_uses_ldq; // @[util.scala:104:23] assign next_uop_uses_stq = next_uop_out_uses_stq; // @[util.scala:104:23] assign next_uop_is_unique = next_uop_out_is_unique; // @[util.scala:104:23] assign next_uop_flush_on_commit = next_uop_out_flush_on_commit; // @[util.scala:104:23] assign next_uop_csr_cmd = next_uop_out_csr_cmd; // @[util.scala:104:23] assign next_uop_ldst_is_rs1 = next_uop_out_ldst_is_rs1; // @[util.scala:104:23] assign next_uop_ldst = next_uop_out_ldst; // @[util.scala:104:23] assign next_uop_lrs1 = next_uop_out_lrs1; // @[util.scala:104:23] assign next_uop_lrs2 = next_uop_out_lrs2; // @[util.scala:104:23] assign next_uop_lrs3 = next_uop_out_lrs3; // @[util.scala:104:23] assign next_uop_dst_rtype = next_uop_out_dst_rtype; // @[util.scala:104:23] assign next_uop_lrs1_rtype = next_uop_out_lrs1_rtype; // @[util.scala:104:23] assign next_uop_lrs2_rtype = next_uop_out_lrs2_rtype; // @[util.scala:104:23] assign next_uop_frs3_en = next_uop_out_frs3_en; // @[util.scala:104:23] assign next_uop_fcn_dw = next_uop_out_fcn_dw; // @[util.scala:104:23] assign next_uop_fcn_op = next_uop_out_fcn_op; // @[util.scala:104:23] assign next_uop_fp_val = next_uop_out_fp_val; // @[util.scala:104:23] assign next_uop_fp_rm = next_uop_out_fp_rm; // @[util.scala:104:23] assign next_uop_fp_typ = next_uop_out_fp_typ; // @[util.scala:104:23] assign next_uop_xcpt_pf_if = next_uop_out_xcpt_pf_if; // @[util.scala:104:23] assign next_uop_xcpt_ae_if = next_uop_out_xcpt_ae_if; // @[util.scala:104:23] assign next_uop_xcpt_ma_if = next_uop_out_xcpt_ma_if; // @[util.scala:104:23] assign next_uop_bp_debug_if = next_uop_out_bp_debug_if; // @[util.scala:104:23] assign next_uop_bp_xcpt_if = next_uop_out_bp_xcpt_if; // @[util.scala:104:23] assign next_uop_debug_fsrc = next_uop_out_debug_fsrc; // @[util.scala:104:23] assign next_uop_debug_tsrc = next_uop_out_debug_tsrc; // @[util.scala:104:23] wire [15:0] _next_uop_out_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _next_uop_out_br_mask_T_1 = slot_uop_br_mask & _next_uop_out_br_mask_T; // @[util.scala:93:{25,27}] assign next_uop_out_br_mask = _next_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23] assign io_out_uop_inst_0 = next_uop_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_inst_0 = next_uop_debug_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_rvc_0 = next_uop_is_rvc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_pc_0 = next_uop_debug_pc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_0_0 = next_uop_iq_type_0; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_1_0 = next_uop_iq_type_1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_2_0 = next_uop_iq_type_2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_3_0 = next_uop_iq_type_3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_0_0 = next_uop_fu_code_0; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_1_0 = next_uop_fu_code_1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_2_0 = next_uop_fu_code_2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_3_0 = next_uop_fu_code_3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_4_0 = next_uop_fu_code_4; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_5_0 = next_uop_fu_code_5; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_6_0 = next_uop_fu_code_6; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_7_0 = next_uop_fu_code_7; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_8_0 = next_uop_fu_code_8; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_9_0 = next_uop_fu_code_9; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_issued_0 = next_uop_iw_issued; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_issued_partial_agen_0 = next_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_issued_partial_dgen_0 = next_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p1_speculative_child_0 = next_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p2_speculative_child_0 = next_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p1_bypass_hint_0 = next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p2_bypass_hint_0 = next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p3_bypass_hint_0 = next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_dis_col_sel_0 = next_uop_dis_col_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_mask_0 = next_uop_br_mask; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_tag_0 = next_uop_br_tag; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_type_0 = next_uop_br_type; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sfb_0 = next_uop_is_sfb; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_fence_0 = next_uop_is_fence; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_fencei_0 = next_uop_is_fencei; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sfence_0 = next_uop_is_sfence; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_amo_0 = next_uop_is_amo; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_eret_0 = next_uop_is_eret; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sys_pc2epc_0 = next_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_rocc_0 = next_uop_is_rocc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_mov_0 = next_uop_is_mov; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ftq_idx_0 = next_uop_ftq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_edge_inst_0 = next_uop_edge_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pc_lob_0 = next_uop_pc_lob; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_taken_0 = next_uop_taken; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_rename_0 = next_uop_imm_rename; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_sel_0 = next_uop_imm_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pimm_0 = next_uop_pimm; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_packed_0 = next_uop_imm_packed; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_op1_sel_0 = next_uop_op1_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_op2_sel_0 = next_uop_op2_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ldst_0 = next_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_wen_0 = next_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren1_0 = next_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren2_0 = next_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren3_0 = next_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_swap12_0 = next_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_swap23_0 = next_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_typeTagIn_0 = next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_typeTagOut_0 = next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fromint_0 = next_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_toint_0 = next_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fastpipe_0 = next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fma_0 = next_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_div_0 = next_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_sqrt_0 = next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_wflags_0 = next_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_vec_0 = next_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_rob_idx_0 = next_uop_rob_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldq_idx_0 = next_uop_ldq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_stq_idx_0 = next_uop_stq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_rxq_idx_0 = next_uop_rxq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pdst_0 = next_uop_pdst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs1_0 = next_uop_prs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs2_0 = next_uop_prs2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs3_0 = next_uop_prs3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ppred_0 = next_uop_ppred; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs1_busy_0 = next_uop_prs1_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs2_busy_0 = next_uop_prs2_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs3_busy_0 = next_uop_prs3_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ppred_busy_0 = next_uop_ppred_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_stale_pdst_0 = next_uop_stale_pdst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_exception_0 = next_uop_exception; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_exc_cause_0 = next_uop_exc_cause; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_cmd_0 = next_uop_mem_cmd; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_size_0 = next_uop_mem_size; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_signed_0 = next_uop_mem_signed; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_uses_ldq_0 = next_uop_uses_ldq; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_uses_stq_0 = next_uop_uses_stq; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_unique_0 = next_uop_is_unique; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_flush_on_commit_0 = next_uop_flush_on_commit; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_csr_cmd_0 = next_uop_csr_cmd; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldst_is_rs1_0 = next_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldst_0 = next_uop_ldst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs1_0 = next_uop_lrs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs2_0 = next_uop_lrs2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs3_0 = next_uop_lrs3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_dst_rtype_0 = next_uop_dst_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs1_rtype_0 = next_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs2_rtype_0 = next_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_frs3_en_0 = next_uop_frs3_en; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fcn_dw_0 = next_uop_fcn_dw; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fcn_op_0 = next_uop_fcn_op; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_val_0 = next_uop_fp_val; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_rm_0 = next_uop_fp_rm; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_typ_0 = next_uop_fp_typ; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_pf_if_0 = next_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_ae_if_0 = next_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_ma_if_0 = next_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_bp_debug_if_0 = next_uop_bp_debug_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_bp_xcpt_if_0 = next_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_fsrc_0 = next_uop_debug_fsrc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_tsrc_0 = next_uop_debug_tsrc; // @[issue-slot.scala:49:7, :59:28] wire [15:0] _killed_T = io_brupdate_b1_mispredict_mask_0 & slot_uop_br_mask; // @[util.scala:126:51] wire _killed_T_1 = \|_killed_T; // @[util.scala:126:{51,59}] wire killed = _killed_T_1 \| io_kill_0; // @[util.scala:61:61, :126:59] wire _io_will_be_valid_T = ~killed; // @[util.scala:61:61] assign _io_will_be_valid_T_1 = next_valid & _io_will_be_valid_T; // @[issue-slot.scala:58:28, :65:{34,37}] assign io_will_be_valid_0 = _io_will_be_valid_T_1; // @[issue-slot.scala:49:7, :65:34] wire _slot_valid_T = ~killed; // @[util.scala:61:61] wire _slot_valid_T_1 = next_valid & _slot_valid_T; // @[issue-slot.scala:58:28, :74:{30,33}]
Generate the Verilog code corresponding to this FIRRTL code module FPU_1 : input clock : Clock input reset : Reset output io : { flip hartid : UInt<2>, flip time : UInt<64>, flip inst : UInt<32>, flip fromint_data : UInt<64>, flip fcsr_rm : UInt<3>, fcsr_flags : { valid : UInt<1>, bits : UInt<5>}, flip v_sew : UInt<3>, store_data : UInt<64>, toint_data : UInt<64>, flip ll_resp_val : UInt<1>, flip ll_resp_type : UInt<3>, flip ll_resp_tag : UInt<5>, flip ll_resp_data : UInt<64>, flip valid : UInt<1>, fcsr_rdy : UInt<1>, nack_mem : UInt<1>, illegal_rm : UInt<1>, flip killx : UInt<1>, flip killm : UInt<1>, dec : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, sboard_set : UInt<1>, sboard_clr : UInt<1>, sboard_clra : UInt<5>, flip keep_clock_enabled : UInt<1>, flip cp_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, cp_resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<65>, exc : UInt<5>}}} reg clock_en_reg : UInt<1>, clock node clock_en = or(clock_en_reg, io.cp_req.valid) inst fp_decoder of FPUDecoder_1 connect fp_decoder.clock, clock connect fp_decoder.reset, reset connect fp_decoder.io.inst, io.inst wire id_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>} connect id_ctrl, fp_decoder.io.sigs regreset ex_reg_valid : UInt<1>, clock, reset, UInt<1>(0h0) connect ex_reg_valid, io.valid reg ex_reg_inst : UInt<32>, clock when io.valid : connect ex_reg_inst, io.inst reg ex_reg_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, clock when io.valid : connect ex_reg_ctrl, id_ctrl reg ex_ra_0 : UInt, clock reg ex_ra_1 : UInt, clock reg ex_ra_2 : UInt, clock reg load_wb : UInt<1>, clock connect load_wb, io.ll_resp_val node _load_wb_typeTag_T = bits(io.ll_resp_type, 1, 0) node _load_wb_typeTag_T_1 = sub(_load_wb_typeTag_T, UInt<1>(0h1)) node _load_wb_typeTag_T_2 = tail(_load_wb_typeTag_T_1, 1) reg load_wb_typeTag : UInt<2>, clock when io.ll_resp_val : connect load_wb_typeTag, _load_wb_typeTag_T_2 reg load_wb_data : UInt<64>, clock when io.ll_resp_val : connect load_wb_data, io.ll_resp_data reg load_wb_tag : UInt<5>, clock when io.ll_resp_val : connect load_wb_tag, io.ll_resp_tag node req_valid = or(ex_reg_valid, io.cp_req.valid) node ex_cp_valid = and(io.cp_req.ready, io.cp_req.valid) regreset mem_cp_valid : UInt<1>, clock, reset, UInt<1>(0h0) connect mem_cp_valid, ex_cp_valid regreset wb_cp_valid : UInt<1>, clock, reset, UInt<1>(0h0) connect wb_cp_valid, mem_cp_valid regreset mem_reg_valid : UInt<1>, clock, reset, UInt<1>(0h0) node _killm_T = or(io.killm, io.nack_mem) node _killm_T_1 = eq(mem_cp_valid, UInt<1>(0h0)) node killm = and(_killm_T, _killm_T_1) node _killx_T = and(mem_reg_valid, killm) node killx = or(io.killx, _killx_T) node _mem_reg_valid_T = eq(killx, UInt<1>(0h0)) node _mem_reg_valid_T_1 = and(ex_reg_valid, _mem_reg_valid_T) node _mem_reg_valid_T_2 = or(_mem_reg_valid_T_1, ex_cp_valid) connect mem_reg_valid, _mem_reg_valid_T_2 reg mem_reg_inst : UInt<32>, clock when ex_reg_valid : connect mem_reg_inst, ex_reg_inst node _wb_reg_valid_T = eq(killm, UInt<1>(0h0)) node _wb_reg_valid_T_1 = or(_wb_reg_valid_T, mem_cp_valid) node _wb_reg_valid_T_2 = and(mem_reg_valid, _wb_reg_valid_T_1) regreset wb_reg_valid : UInt<1>, clock, reset, UInt<1>(0h0) connect wb_reg_valid, _wb_reg_valid_T_2 wire cp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>} connect cp_ctrl.vec, io.cp_req.bits.vec connect cp_ctrl.wflags, io.cp_req.bits.wflags connect cp_ctrl.sqrt, io.cp_req.bits.sqrt connect cp_ctrl.div, io.cp_req.bits.div connect cp_ctrl.fma, io.cp_req.bits.fma connect cp_ctrl.fastpipe, io.cp_req.bits.fastpipe connect cp_ctrl.toint, io.cp_req.bits.toint connect cp_ctrl.fromint, io.cp_req.bits.fromint connect cp_ctrl.typeTagOut, io.cp_req.bits.typeTagOut connect cp_ctrl.typeTagIn, io.cp_req.bits.typeTagIn connect cp_ctrl.swap23, io.cp_req.bits.swap23 connect cp_ctrl.swap12, io.cp_req.bits.swap12 connect cp_ctrl.ren3, io.cp_req.bits.ren3 connect cp_ctrl.ren2, io.cp_req.bits.ren2 connect cp_ctrl.ren1, io.cp_req.bits.ren1 connect cp_ctrl.wen, io.cp_req.bits.wen connect cp_ctrl.ldst, io.cp_req.bits.ldst connect io.cp_resp.valid, UInt<1>(0h0) connect io.cp_resp.bits.data, UInt<1>(0h0) invalidate io.cp_resp.bits.exc node ex_ctrl = mux(ex_cp_valid, cp_ctrl, ex_reg_ctrl) reg mem_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, clock when req_valid : connect mem_ctrl, ex_ctrl reg wb_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, clock when mem_reg_valid : connect wb_ctrl, mem_ctrl wire frfWriteBundle_0 : { clock : Clock, reset : UInt<1>, excpt : UInt<1>, priv_mode : UInt<3>, hartid : UInt<64>, timer : UInt<32>, valid : UInt<1>, pc : UInt<64>, wrdst : UInt<5>, wrdata : UInt<64>, wrenx : UInt<1>, wrenf : UInt<1>, rd0src : UInt<5>, rd0val : UInt<64>, rd1src : UInt<5>, rd1val : UInt<64>, inst : UInt<32>} invalidate frfWriteBundle_0.inst invalidate frfWriteBundle_0.rd1val invalidate frfWriteBundle_0.rd1src invalidate frfWriteBundle_0.rd0val invalidate frfWriteBundle_0.rd0src invalidate frfWriteBundle_0.wrenf invalidate frfWriteBundle_0.wrenx invalidate frfWriteBundle_0.wrdata invalidate frfWriteBundle_0.wrdst invalidate frfWriteBundle_0.pc invalidate frfWriteBundle_0.valid invalidate frfWriteBundle_0.timer invalidate frfWriteBundle_0.hartid invalidate frfWriteBundle_0.priv_mode invalidate frfWriteBundle_0.excpt invalidate frfWriteBundle_0.reset invalidate frfWriteBundle_0.clock wire frfWriteBundle_1 : { clock : Clock, reset : UInt<1>, excpt : UInt<1>, priv_mode : UInt<3>, hartid : UInt<64>, timer : UInt<32>, valid : UInt<1>, pc : UInt<64>, wrdst : UInt<5>, wrdata : UInt<64>, wrenx : UInt<1>, wrenf : UInt<1>, rd0src : UInt<5>, rd0val : UInt<64>, rd1src : UInt<5>, rd1val : UInt<64>, inst : UInt<32>} invalidate frfWriteBundle_1.inst invalidate frfWriteBundle_1.rd1val invalidate frfWriteBundle_1.rd1src invalidate frfWriteBundle_1.rd0val invalidate frfWriteBundle_1.rd0src invalidate frfWriteBundle_1.wrenf invalidate frfWriteBundle_1.wrenx invalidate frfWriteBundle_1.wrdata invalidate frfWriteBundle_1.wrdst invalidate frfWriteBundle_1.pc invalidate frfWriteBundle_1.valid invalidate frfWriteBundle_1.timer invalidate frfWriteBundle_1.hartid invalidate frfWriteBundle_1.priv_mode invalidate frfWriteBundle_1.excpt invalidate frfWriteBundle_1.reset invalidate frfWriteBundle_1.clock connect frfWriteBundle_0.clock, clock connect frfWriteBundle_0.reset, reset connect frfWriteBundle_0.hartid, io.hartid node _frfWriteBundle_0_timer_T = bits(io.time, 31, 0) connect frfWriteBundle_0.timer, _frfWriteBundle_0_timer_T connect frfWriteBundle_0.valid, UInt<1>(0h0) connect frfWriteBundle_0.wrenx, UInt<1>(0h0) connect frfWriteBundle_0.wrenf, UInt<1>(0h0) connect frfWriteBundle_0.excpt, UInt<1>(0h0) connect frfWriteBundle_1.clock, clock connect frfWriteBundle_1.reset, reset connect frfWriteBundle_1.hartid, io.hartid node _frfWriteBundle_1_timer_T = bits(io.time, 31, 0) connect frfWriteBundle_1.timer, _frfWriteBundle_1_timer_T connect frfWriteBundle_1.valid, UInt<1>(0h0) connect frfWriteBundle_1.wrenx, UInt<1>(0h0) connect frfWriteBundle_1.wrenf, UInt<1>(0h0) connect frfWriteBundle_1.excpt, UInt<1>(0h0) cmem regfile : UInt<65> [32] when load_wb : node _wdata_T = eq(load_wb_typeTag, UInt<1>(0h1)) node _wdata_T_1 = mux(_wdata_T, UInt<64>(0hffffffff00000000), UInt<64>(0hffffffffffff0000)) node _wdata_T_2 = eq(load_wb_typeTag, UInt<2>(0h2)) node _wdata_T_3 = mux(_wdata_T_2, UInt<1>(0h0), _wdata_T_1) node _wdata_T_4 = eq(load_wb_typeTag, UInt<2>(0h3)) node _wdata_T_5 = mux(_wdata_T_4, UInt<1>(0h0), _wdata_T_3) node _wdata_T_6 = or(_wdata_T_5, load_wb_data) node wdata_rawIn_sign = bits(_wdata_T_6, 63, 63) node wdata_rawIn_expIn = bits(_wdata_T_6, 62, 52) node wdata_rawIn_fractIn = bits(_wdata_T_6, 51, 0) node wdata_rawIn_isZeroExpIn = eq(wdata_rawIn_expIn, UInt<1>(0h0)) node wdata_rawIn_isZeroFractIn = eq(wdata_rawIn_fractIn, UInt<1>(0h0)) node _wdata_rawIn_normDist_T = bits(wdata_rawIn_fractIn, 0, 0) node _wdata_rawIn_normDist_T_1 = bits(wdata_rawIn_fractIn, 1, 1) node _wdata_rawIn_normDist_T_2 = bits(wdata_rawIn_fractIn, 2, 2) node _wdata_rawIn_normDist_T_3 = bits(wdata_rawIn_fractIn, 3, 3) node _wdata_rawIn_normDist_T_4 = bits(wdata_rawIn_fractIn, 4, 4) node _wdata_rawIn_normDist_T_5 = bits(wdata_rawIn_fractIn, 5, 5) node _wdata_rawIn_normDist_T_6 = bits(wdata_rawIn_fractIn, 6, 6) node _wdata_rawIn_normDist_T_7 = bits(wdata_rawIn_fractIn, 7, 7) node _wdata_rawIn_normDist_T_8 = bits(wdata_rawIn_fractIn, 8, 8) node _wdata_rawIn_normDist_T_9 = bits(wdata_rawIn_fractIn, 9, 9) node _wdata_rawIn_normDist_T_10 = bits(wdata_rawIn_fractIn, 10, 10) node _wdata_rawIn_normDist_T_11 = bits(wdata_rawIn_fractIn, 11, 11) node _wdata_rawIn_normDist_T_12 = bits(wdata_rawIn_fractIn, 12, 12) node _wdata_rawIn_normDist_T_13 = bits(wdata_rawIn_fractIn, 13, 13) node _wdata_rawIn_normDist_T_14 = bits(wdata_rawIn_fractIn, 14, 14) node _wdata_rawIn_normDist_T_15 = bits(wdata_rawIn_fractIn, 15, 15) node _wdata_rawIn_normDist_T_16 = bits(wdata_rawIn_fractIn, 16, 16) node _wdata_rawIn_normDist_T_17 = bits(wdata_rawIn_fractIn, 17, 17) node _wdata_rawIn_normDist_T_18 = bits(wdata_rawIn_fractIn, 18, 18) node _wdata_rawIn_normDist_T_19 = bits(wdata_rawIn_fractIn, 19, 19) node _wdata_rawIn_normDist_T_20 = bits(wdata_rawIn_fractIn, 20, 20) node _wdata_rawIn_normDist_T_21 = bits(wdata_rawIn_fractIn, 21, 21) node _wdata_rawIn_normDist_T_22 = bits(wdata_rawIn_fractIn, 22, 22) node _wdata_rawIn_normDist_T_23 = bits(wdata_rawIn_fractIn, 23, 23) node _wdata_rawIn_normDist_T_24 = bits(wdata_rawIn_fractIn, 24, 24) node _wdata_rawIn_normDist_T_25 = bits(wdata_rawIn_fractIn, 25, 25) node _wdata_rawIn_normDist_T_26 = bits(wdata_rawIn_fractIn, 26, 26) node _wdata_rawIn_normDist_T_27 = bits(wdata_rawIn_fractIn, 27, 27) node _wdata_rawIn_normDist_T_28 = bits(wdata_rawIn_fractIn, 28, 28) node _wdata_rawIn_normDist_T_29 = bits(wdata_rawIn_fractIn, 29, 29) node _wdata_rawIn_normDist_T_30 = bits(wdata_rawIn_fractIn, 30, 30) node _wdata_rawIn_normDist_T_31 = bits(wdata_rawIn_fractIn, 31, 31) node _wdata_rawIn_normDist_T_32 = bits(wdata_rawIn_fractIn, 32, 32) node _wdata_rawIn_normDist_T_33 = bits(wdata_rawIn_fractIn, 33, 33) node _wdata_rawIn_normDist_T_34 = bits(wdata_rawIn_fractIn, 34, 34) node _wdata_rawIn_normDist_T_35 = bits(wdata_rawIn_fractIn, 35, 35) node _wdata_rawIn_normDist_T_36 = bits(wdata_rawIn_fractIn, 36, 36) node _wdata_rawIn_normDist_T_37 = bits(wdata_rawIn_fractIn, 37, 37) node _wdata_rawIn_normDist_T_38 = bits(wdata_rawIn_fractIn, 38, 38) node _wdata_rawIn_normDist_T_39 = bits(wdata_rawIn_fractIn, 39, 39) node _wdata_rawIn_normDist_T_40 = bits(wdata_rawIn_fractIn, 40, 40) node _wdata_rawIn_normDist_T_41 = bits(wdata_rawIn_fractIn, 41, 41) node _wdata_rawIn_normDist_T_42 = bits(wdata_rawIn_fractIn, 42, 42) node _wdata_rawIn_normDist_T_43 = bits(wdata_rawIn_fractIn, 43, 43) node _wdata_rawIn_normDist_T_44 = bits(wdata_rawIn_fractIn, 44, 44) node _wdata_rawIn_normDist_T_45 = bits(wdata_rawIn_fractIn, 45, 45) node _wdata_rawIn_normDist_T_46 = bits(wdata_rawIn_fractIn, 46, 46) node _wdata_rawIn_normDist_T_47 = bits(wdata_rawIn_fractIn, 47, 47) node _wdata_rawIn_normDist_T_48 = bits(wdata_rawIn_fractIn, 48, 48) node _wdata_rawIn_normDist_T_49 = bits(wdata_rawIn_fractIn, 49, 49) node _wdata_rawIn_normDist_T_50 = bits(wdata_rawIn_fractIn, 50, 50) node _wdata_rawIn_normDist_T_51 = bits(wdata_rawIn_fractIn, 51, 51) node _wdata_rawIn_normDist_T_52 = mux(_wdata_rawIn_normDist_T_1, UInt<6>(0h32), UInt<6>(0h33)) node _wdata_rawIn_normDist_T_53 = mux(_wdata_rawIn_normDist_T_2, UInt<6>(0h31), _wdata_rawIn_normDist_T_52) node _wdata_rawIn_normDist_T_54 = mux(_wdata_rawIn_normDist_T_3, UInt<6>(0h30), _wdata_rawIn_normDist_T_53) node _wdata_rawIn_normDist_T_55 = mux(_wdata_rawIn_normDist_T_4, UInt<6>(0h2f), _wdata_rawIn_normDist_T_54) node _wdata_rawIn_normDist_T_56 = mux(_wdata_rawIn_normDist_T_5, UInt<6>(0h2e), _wdata_rawIn_normDist_T_55) node _wdata_rawIn_normDist_T_57 = mux(_wdata_rawIn_normDist_T_6, UInt<6>(0h2d), _wdata_rawIn_normDist_T_56) node _wdata_rawIn_normDist_T_58 = mux(_wdata_rawIn_normDist_T_7, UInt<6>(0h2c), _wdata_rawIn_normDist_T_57) node _wdata_rawIn_normDist_T_59 = mux(_wdata_rawIn_normDist_T_8, UInt<6>(0h2b), _wdata_rawIn_normDist_T_58) node _wdata_rawIn_normDist_T_60 = mux(_wdata_rawIn_normDist_T_9, UInt<6>(0h2a), _wdata_rawIn_normDist_T_59) node _wdata_rawIn_normDist_T_61 = mux(_wdata_rawIn_normDist_T_10, UInt<6>(0h29), _wdata_rawIn_normDist_T_60) node _wdata_rawIn_normDist_T_62 = mux(_wdata_rawIn_normDist_T_11, UInt<6>(0h28), _wdata_rawIn_normDist_T_61) node _wdata_rawIn_normDist_T_63 = mux(_wdata_rawIn_normDist_T_12, UInt<6>(0h27), _wdata_rawIn_normDist_T_62) node _wdata_rawIn_normDist_T_64 = mux(_wdata_rawIn_normDist_T_13, UInt<6>(0h26), _wdata_rawIn_normDist_T_63) node _wdata_rawIn_normDist_T_65 = mux(_wdata_rawIn_normDist_T_14, UInt<6>(0h25), _wdata_rawIn_normDist_T_64) node _wdata_rawIn_normDist_T_66 = mux(_wdata_rawIn_normDist_T_15, UInt<6>(0h24), _wdata_rawIn_normDist_T_65) node _wdata_rawIn_normDist_T_67 = mux(_wdata_rawIn_normDist_T_16, UInt<6>(0h23), _wdata_rawIn_normDist_T_66) node _wdata_rawIn_normDist_T_68 = mux(_wdata_rawIn_normDist_T_17, UInt<6>(0h22), _wdata_rawIn_normDist_T_67) node _wdata_rawIn_normDist_T_69 = mux(_wdata_rawIn_normDist_T_18, UInt<6>(0h21), _wdata_rawIn_normDist_T_68) node _wdata_rawIn_normDist_T_70 = mux(_wdata_rawIn_normDist_T_19, UInt<6>(0h20), _wdata_rawIn_normDist_T_69) node _wdata_rawIn_normDist_T_71 = mux(_wdata_rawIn_normDist_T_20, UInt<5>(0h1f), _wdata_rawIn_normDist_T_70) node _wdata_rawIn_normDist_T_72 = mux(_wdata_rawIn_normDist_T_21, UInt<5>(0h1e), _wdata_rawIn_normDist_T_71) node _wdata_rawIn_normDist_T_73 = mux(_wdata_rawIn_normDist_T_22, UInt<5>(0h1d), _wdata_rawIn_normDist_T_72) node _wdata_rawIn_normDist_T_74 = mux(_wdata_rawIn_normDist_T_23, UInt<5>(0h1c), _wdata_rawIn_normDist_T_73) node _wdata_rawIn_normDist_T_75 = mux(_wdata_rawIn_normDist_T_24, UInt<5>(0h1b), _wdata_rawIn_normDist_T_74) node _wdata_rawIn_normDist_T_76 = mux(_wdata_rawIn_normDist_T_25, UInt<5>(0h1a), _wdata_rawIn_normDist_T_75) node _wdata_rawIn_normDist_T_77 = mux(_wdata_rawIn_normDist_T_26, UInt<5>(0h19), _wdata_rawIn_normDist_T_76) node _wdata_rawIn_normDist_T_78 = mux(_wdata_rawIn_normDist_T_27, UInt<5>(0h18), _wdata_rawIn_normDist_T_77) node _wdata_rawIn_normDist_T_79 = mux(_wdata_rawIn_normDist_T_28, UInt<5>(0h17), _wdata_rawIn_normDist_T_78) node _wdata_rawIn_normDist_T_80 = mux(_wdata_rawIn_normDist_T_29, UInt<5>(0h16), _wdata_rawIn_normDist_T_79) node _wdata_rawIn_normDist_T_81 = mux(_wdata_rawIn_normDist_T_30, UInt<5>(0h15), _wdata_rawIn_normDist_T_80) node _wdata_rawIn_normDist_T_82 = mux(_wdata_rawIn_normDist_T_31, UInt<5>(0h14), _wdata_rawIn_normDist_T_81) node _wdata_rawIn_normDist_T_83 = mux(_wdata_rawIn_normDist_T_32, UInt<5>(0h13), _wdata_rawIn_normDist_T_82) node _wdata_rawIn_normDist_T_84 = mux(_wdata_rawIn_normDist_T_33, UInt<5>(0h12), _wdata_rawIn_normDist_T_83) node _wdata_rawIn_normDist_T_85 = mux(_wdata_rawIn_normDist_T_34, UInt<5>(0h11), _wdata_rawIn_normDist_T_84) node _wdata_rawIn_normDist_T_86 = mux(_wdata_rawIn_normDist_T_35, UInt<5>(0h10), _wdata_rawIn_normDist_T_85) node _wdata_rawIn_normDist_T_87 = mux(_wdata_rawIn_normDist_T_36, UInt<4>(0hf), _wdata_rawIn_normDist_T_86) node _wdata_rawIn_normDist_T_88 = mux(_wdata_rawIn_normDist_T_37, UInt<4>(0he), _wdata_rawIn_normDist_T_87) node _wdata_rawIn_normDist_T_89 = mux(_wdata_rawIn_normDist_T_38, UInt<4>(0hd), _wdata_rawIn_normDist_T_88) node _wdata_rawIn_normDist_T_90 = mux(_wdata_rawIn_normDist_T_39, UInt<4>(0hc), _wdata_rawIn_normDist_T_89) node _wdata_rawIn_normDist_T_91 = mux(_wdata_rawIn_normDist_T_40, UInt<4>(0hb), _wdata_rawIn_normDist_T_90) node _wdata_rawIn_normDist_T_92 = mux(_wdata_rawIn_normDist_T_41, UInt<4>(0ha), _wdata_rawIn_normDist_T_91) node _wdata_rawIn_normDist_T_93 = mux(_wdata_rawIn_normDist_T_42, UInt<4>(0h9), _wdata_rawIn_normDist_T_92) node _wdata_rawIn_normDist_T_94 = mux(_wdata_rawIn_normDist_T_43, UInt<4>(0h8), _wdata_rawIn_normDist_T_93) node _wdata_rawIn_normDist_T_95 = mux(_wdata_rawIn_normDist_T_44, UInt<3>(0h7), _wdata_rawIn_normDist_T_94) node _wdata_rawIn_normDist_T_96 = mux(_wdata_rawIn_normDist_T_45, UInt<3>(0h6), _wdata_rawIn_normDist_T_95) node _wdata_rawIn_normDist_T_97 = mux(_wdata_rawIn_normDist_T_46, UInt<3>(0h5), _wdata_rawIn_normDist_T_96) node _wdata_rawIn_normDist_T_98 = mux(_wdata_rawIn_normDist_T_47, UInt<3>(0h4), _wdata_rawIn_normDist_T_97) node _wdata_rawIn_normDist_T_99 = mux(_wdata_rawIn_normDist_T_48, UInt<2>(0h3), _wdata_rawIn_normDist_T_98) node _wdata_rawIn_normDist_T_100 = mux(_wdata_rawIn_normDist_T_49, UInt<2>(0h2), _wdata_rawIn_normDist_T_99) node _wdata_rawIn_normDist_T_101 = mux(_wdata_rawIn_normDist_T_50, UInt<1>(0h1), _wdata_rawIn_normDist_T_100) node wdata_rawIn_normDist = mux(_wdata_rawIn_normDist_T_51, UInt<1>(0h0), _wdata_rawIn_normDist_T_101) node _wdata_rawIn_subnormFract_T = dshl(wdata_rawIn_fractIn, wdata_rawIn_normDist) node _wdata_rawIn_subnormFract_T_1 = bits(_wdata_rawIn_subnormFract_T, 50, 0) node wdata_rawIn_subnormFract = shl(_wdata_rawIn_subnormFract_T_1, 1) node _wdata_rawIn_adjustedExp_T = xor(wdata_rawIn_normDist, UInt<12>(0hfff)) node _wdata_rawIn_adjustedExp_T_1 = mux(wdata_rawIn_isZeroExpIn, _wdata_rawIn_adjustedExp_T, wdata_rawIn_expIn) node _wdata_rawIn_adjustedExp_T_2 = mux(wdata_rawIn_isZeroExpIn, UInt<2>(0h2), UInt<1>(0h1)) node _wdata_rawIn_adjustedExp_T_3 = or(UInt<11>(0h400), _wdata_rawIn_adjustedExp_T_2) node _wdata_rawIn_adjustedExp_T_4 = add(_wdata_rawIn_adjustedExp_T_1, _wdata_rawIn_adjustedExp_T_3) node wdata_rawIn_adjustedExp = tail(_wdata_rawIn_adjustedExp_T_4, 1) node wdata_rawIn_isZero = and(wdata_rawIn_isZeroExpIn, wdata_rawIn_isZeroFractIn) node _wdata_rawIn_isSpecial_T = bits(wdata_rawIn_adjustedExp, 11, 10) node wdata_rawIn_isSpecial = eq(_wdata_rawIn_isSpecial_T, UInt<2>(0h3)) wire wdata_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} node _wdata_rawIn_out_isNaN_T = eq(wdata_rawIn_isZeroFractIn, UInt<1>(0h0)) node _wdata_rawIn_out_isNaN_T_1 = and(wdata_rawIn_isSpecial, _wdata_rawIn_out_isNaN_T) connect wdata_rawIn.isNaN, _wdata_rawIn_out_isNaN_T_1 node _wdata_rawIn_out_isInf_T = and(wdata_rawIn_isSpecial, wdata_rawIn_isZeroFractIn) connect wdata_rawIn.isInf, _wdata_rawIn_out_isInf_T connect wdata_rawIn.isZero, wdata_rawIn_isZero connect wdata_rawIn.sign, wdata_rawIn_sign node _wdata_rawIn_out_sExp_T = bits(wdata_rawIn_adjustedExp, 11, 0) node _wdata_rawIn_out_sExp_T_1 = cvt(_wdata_rawIn_out_sExp_T) connect wdata_rawIn.sExp, _wdata_rawIn_out_sExp_T_1 node _wdata_rawIn_out_sig_T = eq(wdata_rawIn_isZero, UInt<1>(0h0)) node _wdata_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _wdata_rawIn_out_sig_T) node _wdata_rawIn_out_sig_T_2 = mux(wdata_rawIn_isZeroExpIn, wdata_rawIn_subnormFract, wdata_rawIn_fractIn) node _wdata_rawIn_out_sig_T_3 = cat(_wdata_rawIn_out_sig_T_1, _wdata_rawIn_out_sig_T_2) connect wdata_rawIn.sig, _wdata_rawIn_out_sig_T_3 node _wdata_T_7 = bits(wdata_rawIn.sExp, 11, 9) node _wdata_T_8 = mux(wdata_rawIn.isZero, UInt<3>(0h0), _wdata_T_7) node _wdata_T_9 = mux(wdata_rawIn.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _wdata_T_10 = or(_wdata_T_8, _wdata_T_9) node _wdata_T_11 = cat(wdata_rawIn.sign, _wdata_T_10) node _wdata_T_12 = bits(wdata_rawIn.sExp, 8, 0) node _wdata_T_13 = cat(_wdata_T_11, _wdata_T_12) node _wdata_T_14 = bits(wdata_rawIn.sig, 51, 0) node _wdata_T_15 = cat(_wdata_T_13, _wdata_T_14) node wdata_rawIn_sign_1 = bits(_wdata_T_6, 31, 31) node wdata_rawIn_expIn_1 = bits(_wdata_T_6, 30, 23) node wdata_rawIn_fractIn_1 = bits(_wdata_T_6, 22, 0) node wdata_rawIn_isZeroExpIn_1 = eq(wdata_rawIn_expIn_1, UInt<1>(0h0)) node wdata_rawIn_isZeroFractIn_1 = eq(wdata_rawIn_fractIn_1, UInt<1>(0h0)) node _wdata_rawIn_normDist_T_102 = bits(wdata_rawIn_fractIn_1, 0, 0) node _wdata_rawIn_normDist_T_103 = bits(wdata_rawIn_fractIn_1, 1, 1) node _wdata_rawIn_normDist_T_104 = bits(wdata_rawIn_fractIn_1, 2, 2) node _wdata_rawIn_normDist_T_105 = bits(wdata_rawIn_fractIn_1, 3, 3) node _wdata_rawIn_normDist_T_106 = bits(wdata_rawIn_fractIn_1, 4, 4) node _wdata_rawIn_normDist_T_107 = bits(wdata_rawIn_fractIn_1, 5, 5) node _wdata_rawIn_normDist_T_108 = bits(wdata_rawIn_fractIn_1, 6, 6) node _wdata_rawIn_normDist_T_109 = bits(wdata_rawIn_fractIn_1, 7, 7) node _wdata_rawIn_normDist_T_110 = bits(wdata_rawIn_fractIn_1, 8, 8) node _wdata_rawIn_normDist_T_111 = bits(wdata_rawIn_fractIn_1, 9, 9) node _wdata_rawIn_normDist_T_112 = bits(wdata_rawIn_fractIn_1, 10, 10) node _wdata_rawIn_normDist_T_113 = bits(wdata_rawIn_fractIn_1, 11, 11) node _wdata_rawIn_normDist_T_114 = bits(wdata_rawIn_fractIn_1, 12, 12) node _wdata_rawIn_normDist_T_115 = bits(wdata_rawIn_fractIn_1, 13, 13) node _wdata_rawIn_normDist_T_116 = bits(wdata_rawIn_fractIn_1, 14, 14) node _wdata_rawIn_normDist_T_117 = bits(wdata_rawIn_fractIn_1, 15, 15) node _wdata_rawIn_normDist_T_118 = bits(wdata_rawIn_fractIn_1, 16, 16) node _wdata_rawIn_normDist_T_119 = bits(wdata_rawIn_fractIn_1, 17, 17) node _wdata_rawIn_normDist_T_120 = bits(wdata_rawIn_fractIn_1, 18, 18) node _wdata_rawIn_normDist_T_121 = bits(wdata_rawIn_fractIn_1, 19, 19) node _wdata_rawIn_normDist_T_122 = bits(wdata_rawIn_fractIn_1, 20, 20) node _wdata_rawIn_normDist_T_123 = bits(wdata_rawIn_fractIn_1, 21, 21) node _wdata_rawIn_normDist_T_124 = bits(wdata_rawIn_fractIn_1, 22, 22) node _wdata_rawIn_normDist_T_125 = mux(_wdata_rawIn_normDist_T_103, UInt<5>(0h15), UInt<5>(0h16)) node _wdata_rawIn_normDist_T_126 = mux(_wdata_rawIn_normDist_T_104, UInt<5>(0h14), _wdata_rawIn_normDist_T_125) node _wdata_rawIn_normDist_T_127 = mux(_wdata_rawIn_normDist_T_105, UInt<5>(0h13), _wdata_rawIn_normDist_T_126) node _wdata_rawIn_normDist_T_128 = mux(_wdata_rawIn_normDist_T_106, UInt<5>(0h12), _wdata_rawIn_normDist_T_127) node _wdata_rawIn_normDist_T_129 = mux(_wdata_rawIn_normDist_T_107, UInt<5>(0h11), _wdata_rawIn_normDist_T_128) node _wdata_rawIn_normDist_T_130 = mux(_wdata_rawIn_normDist_T_108, UInt<5>(0h10), _wdata_rawIn_normDist_T_129) node _wdata_rawIn_normDist_T_131 = mux(_wdata_rawIn_normDist_T_109, UInt<4>(0hf), _wdata_rawIn_normDist_T_130) node _wdata_rawIn_normDist_T_132 = mux(_wdata_rawIn_normDist_T_110, UInt<4>(0he), _wdata_rawIn_normDist_T_131) node _wdata_rawIn_normDist_T_133 = mux(_wdata_rawIn_normDist_T_111, UInt<4>(0hd), _wdata_rawIn_normDist_T_132) node _wdata_rawIn_normDist_T_134 = mux(_wdata_rawIn_normDist_T_112, UInt<4>(0hc), _wdata_rawIn_normDist_T_133) node _wdata_rawIn_normDist_T_135 = mux(_wdata_rawIn_normDist_T_113, UInt<4>(0hb), _wdata_rawIn_normDist_T_134) node _wdata_rawIn_normDist_T_136 = mux(_wdata_rawIn_normDist_T_114, UInt<4>(0ha), _wdata_rawIn_normDist_T_135) node _wdata_rawIn_normDist_T_137 = mux(_wdata_rawIn_normDist_T_115, UInt<4>(0h9), _wdata_rawIn_normDist_T_136) node _wdata_rawIn_normDist_T_138 = mux(_wdata_rawIn_normDist_T_116, UInt<4>(0h8), _wdata_rawIn_normDist_T_137) node _wdata_rawIn_normDist_T_139 = mux(_wdata_rawIn_normDist_T_117, UInt<3>(0h7), _wdata_rawIn_normDist_T_138) node _wdata_rawIn_normDist_T_140 = mux(_wdata_rawIn_normDist_T_118, UInt<3>(0h6), _wdata_rawIn_normDist_T_139) node _wdata_rawIn_normDist_T_141 = mux(_wdata_rawIn_normDist_T_119, UInt<3>(0h5), _wdata_rawIn_normDist_T_140) node _wdata_rawIn_normDist_T_142 = mux(_wdata_rawIn_normDist_T_120, UInt<3>(0h4), _wdata_rawIn_normDist_T_141) node _wdata_rawIn_normDist_T_143 = mux(_wdata_rawIn_normDist_T_121, UInt<2>(0h3), _wdata_rawIn_normDist_T_142) node _wdata_rawIn_normDist_T_144 = mux(_wdata_rawIn_normDist_T_122, UInt<2>(0h2), _wdata_rawIn_normDist_T_143) node _wdata_rawIn_normDist_T_145 = mux(_wdata_rawIn_normDist_T_123, UInt<1>(0h1), _wdata_rawIn_normDist_T_144) node wdata_rawIn_normDist_1 = mux(_wdata_rawIn_normDist_T_124, UInt<1>(0h0), _wdata_rawIn_normDist_T_145) node _wdata_rawIn_subnormFract_T_2 = dshl(wdata_rawIn_fractIn_1, wdata_rawIn_normDist_1) node _wdata_rawIn_subnormFract_T_3 = bits(_wdata_rawIn_subnormFract_T_2, 21, 0) node wdata_rawIn_subnormFract_1 = shl(_wdata_rawIn_subnormFract_T_3, 1) node _wdata_rawIn_adjustedExp_T_5 = xor(wdata_rawIn_normDist_1, UInt<9>(0h1ff)) node _wdata_rawIn_adjustedExp_T_6 = mux(wdata_rawIn_isZeroExpIn_1, _wdata_rawIn_adjustedExp_T_5, wdata_rawIn_expIn_1) node _wdata_rawIn_adjustedExp_T_7 = mux(wdata_rawIn_isZeroExpIn_1, UInt<2>(0h2), UInt<1>(0h1)) node _wdata_rawIn_adjustedExp_T_8 = or(UInt<8>(0h80), _wdata_rawIn_adjustedExp_T_7) node _wdata_rawIn_adjustedExp_T_9 = add(_wdata_rawIn_adjustedExp_T_6, _wdata_rawIn_adjustedExp_T_8) node wdata_rawIn_adjustedExp_1 = tail(_wdata_rawIn_adjustedExp_T_9, 1) node wdata_rawIn_isZero_1 = and(wdata_rawIn_isZeroExpIn_1, wdata_rawIn_isZeroFractIn_1) node _wdata_rawIn_isSpecial_T_1 = bits(wdata_rawIn_adjustedExp_1, 8, 7) node wdata_rawIn_isSpecial_1 = eq(_wdata_rawIn_isSpecial_T_1, UInt<2>(0h3)) wire wdata_rawIn_1 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _wdata_rawIn_out_isNaN_T_2 = eq(wdata_rawIn_isZeroFractIn_1, UInt<1>(0h0)) node _wdata_rawIn_out_isNaN_T_3 = and(wdata_rawIn_isSpecial_1, _wdata_rawIn_out_isNaN_T_2) connect wdata_rawIn_1.isNaN, _wdata_rawIn_out_isNaN_T_3 node _wdata_rawIn_out_isInf_T_1 = and(wdata_rawIn_isSpecial_1, wdata_rawIn_isZeroFractIn_1) connect wdata_rawIn_1.isInf, _wdata_rawIn_out_isInf_T_1 connect wdata_rawIn_1.isZero, wdata_rawIn_isZero_1 connect wdata_rawIn_1.sign, wdata_rawIn_sign_1 node _wdata_rawIn_out_sExp_T_2 = bits(wdata_rawIn_adjustedExp_1, 8, 0) node _wdata_rawIn_out_sExp_T_3 = cvt(_wdata_rawIn_out_sExp_T_2) connect wdata_rawIn_1.sExp, _wdata_rawIn_out_sExp_T_3 node _wdata_rawIn_out_sig_T_4 = eq(wdata_rawIn_isZero_1, UInt<1>(0h0)) node _wdata_rawIn_out_sig_T_5 = cat(UInt<1>(0h0), _wdata_rawIn_out_sig_T_4) node _wdata_rawIn_out_sig_T_6 = mux(wdata_rawIn_isZeroExpIn_1, wdata_rawIn_subnormFract_1, wdata_rawIn_fractIn_1) node _wdata_rawIn_out_sig_T_7 = cat(_wdata_rawIn_out_sig_T_5, _wdata_rawIn_out_sig_T_6) connect wdata_rawIn_1.sig, _wdata_rawIn_out_sig_T_7 node _wdata_T_16 = bits(wdata_rawIn_1.sExp, 8, 6) node _wdata_T_17 = mux(wdata_rawIn_1.isZero, UInt<3>(0h0), _wdata_T_16) node _wdata_T_18 = mux(wdata_rawIn_1.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _wdata_T_19 = or(_wdata_T_17, _wdata_T_18) node _wdata_T_20 = cat(wdata_rawIn_1.sign, _wdata_T_19) node _wdata_T_21 = bits(wdata_rawIn_1.sExp, 5, 0) node _wdata_T_22 = cat(_wdata_T_20, _wdata_T_21) node _wdata_T_23 = bits(wdata_rawIn_1.sig, 22, 0) node _wdata_T_24 = cat(_wdata_T_22, _wdata_T_23) node wdata_rawIn_sign_2 = bits(_wdata_T_6, 15, 15) node wdata_rawIn_expIn_2 = bits(_wdata_T_6, 14, 10) node wdata_rawIn_fractIn_2 = bits(_wdata_T_6, 9, 0) node wdata_rawIn_isZeroExpIn_2 = eq(wdata_rawIn_expIn_2, UInt<1>(0h0)) node wdata_rawIn_isZeroFractIn_2 = eq(wdata_rawIn_fractIn_2, UInt<1>(0h0)) node _wdata_rawIn_normDist_T_146 = bits(wdata_rawIn_fractIn_2, 0, 0) node _wdata_rawIn_normDist_T_147 = bits(wdata_rawIn_fractIn_2, 1, 1) node _wdata_rawIn_normDist_T_148 = bits(wdata_rawIn_fractIn_2, 2, 2) node _wdata_rawIn_normDist_T_149 = bits(wdata_rawIn_fractIn_2, 3, 3) node _wdata_rawIn_normDist_T_150 = bits(wdata_rawIn_fractIn_2, 4, 4) node _wdata_rawIn_normDist_T_151 = bits(wdata_rawIn_fractIn_2, 5, 5) node _wdata_rawIn_normDist_T_152 = bits(wdata_rawIn_fractIn_2, 6, 6) node _wdata_rawIn_normDist_T_153 = bits(wdata_rawIn_fractIn_2, 7, 7) node _wdata_rawIn_normDist_T_154 = bits(wdata_rawIn_fractIn_2, 8, 8) node _wdata_rawIn_normDist_T_155 = bits(wdata_rawIn_fractIn_2, 9, 9) node _wdata_rawIn_normDist_T_156 = mux(_wdata_rawIn_normDist_T_147, UInt<4>(0h8), UInt<4>(0h9)) node _wdata_rawIn_normDist_T_157 = mux(_wdata_rawIn_normDist_T_148, UInt<3>(0h7), _wdata_rawIn_normDist_T_156) node _wdata_rawIn_normDist_T_158 = mux(_wdata_rawIn_normDist_T_149, UInt<3>(0h6), _wdata_rawIn_normDist_T_157) node _wdata_rawIn_normDist_T_159 = mux(_wdata_rawIn_normDist_T_150, UInt<3>(0h5), _wdata_rawIn_normDist_T_158) node _wdata_rawIn_normDist_T_160 = mux(_wdata_rawIn_normDist_T_151, UInt<3>(0h4), _wdata_rawIn_normDist_T_159) node _wdata_rawIn_normDist_T_161 = mux(_wdata_rawIn_normDist_T_152, UInt<2>(0h3), _wdata_rawIn_normDist_T_160) node _wdata_rawIn_normDist_T_162 = mux(_wdata_rawIn_normDist_T_153, UInt<2>(0h2), _wdata_rawIn_normDist_T_161) node _wdata_rawIn_normDist_T_163 = mux(_wdata_rawIn_normDist_T_154, UInt<1>(0h1), _wdata_rawIn_normDist_T_162) node wdata_rawIn_normDist_2 = mux(_wdata_rawIn_normDist_T_155, UInt<1>(0h0), _wdata_rawIn_normDist_T_163) node _wdata_rawIn_subnormFract_T_4 = dshl(wdata_rawIn_fractIn_2, wdata_rawIn_normDist_2) node _wdata_rawIn_subnormFract_T_5 = bits(_wdata_rawIn_subnormFract_T_4, 8, 0) node wdata_rawIn_subnormFract_2 = shl(_wdata_rawIn_subnormFract_T_5, 1) node _wdata_rawIn_adjustedExp_T_10 = xor(wdata_rawIn_normDist_2, UInt<6>(0h3f)) node _wdata_rawIn_adjustedExp_T_11 = mux(wdata_rawIn_isZeroExpIn_2, _wdata_rawIn_adjustedExp_T_10, wdata_rawIn_expIn_2) node _wdata_rawIn_adjustedExp_T_12 = mux(wdata_rawIn_isZeroExpIn_2, UInt<2>(0h2), UInt<1>(0h1)) node _wdata_rawIn_adjustedExp_T_13 = or(UInt<5>(0h10), _wdata_rawIn_adjustedExp_T_12) node _wdata_rawIn_adjustedExp_T_14 = add(_wdata_rawIn_adjustedExp_T_11, _wdata_rawIn_adjustedExp_T_13) node wdata_rawIn_adjustedExp_2 = tail(_wdata_rawIn_adjustedExp_T_14, 1) node wdata_rawIn_isZero_2 = and(wdata_rawIn_isZeroExpIn_2, wdata_rawIn_isZeroFractIn_2) node _wdata_rawIn_isSpecial_T_2 = bits(wdata_rawIn_adjustedExp_2, 5, 4) node wdata_rawIn_isSpecial_2 = eq(_wdata_rawIn_isSpecial_T_2, UInt<2>(0h3)) wire wdata_rawIn_2 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<12>} node _wdata_rawIn_out_isNaN_T_4 = eq(wdata_rawIn_isZeroFractIn_2, UInt<1>(0h0)) node _wdata_rawIn_out_isNaN_T_5 = and(wdata_rawIn_isSpecial_2, _wdata_rawIn_out_isNaN_T_4) connect wdata_rawIn_2.isNaN, _wdata_rawIn_out_isNaN_T_5 node _wdata_rawIn_out_isInf_T_2 = and(wdata_rawIn_isSpecial_2, wdata_rawIn_isZeroFractIn_2) connect wdata_rawIn_2.isInf, _wdata_rawIn_out_isInf_T_2 connect wdata_rawIn_2.isZero, wdata_rawIn_isZero_2 connect wdata_rawIn_2.sign, wdata_rawIn_sign_2 node _wdata_rawIn_out_sExp_T_4 = bits(wdata_rawIn_adjustedExp_2, 5, 0) node _wdata_rawIn_out_sExp_T_5 = cvt(_wdata_rawIn_out_sExp_T_4) connect wdata_rawIn_2.sExp, _wdata_rawIn_out_sExp_T_5 node _wdata_rawIn_out_sig_T_8 = eq(wdata_rawIn_isZero_2, UInt<1>(0h0)) node _wdata_rawIn_out_sig_T_9 = cat(UInt<1>(0h0), _wdata_rawIn_out_sig_T_8) node _wdata_rawIn_out_sig_T_10 = mux(wdata_rawIn_isZeroExpIn_2, wdata_rawIn_subnormFract_2, wdata_rawIn_fractIn_2) node _wdata_rawIn_out_sig_T_11 = cat(_wdata_rawIn_out_sig_T_9, _wdata_rawIn_out_sig_T_10) connect wdata_rawIn_2.sig, _wdata_rawIn_out_sig_T_11 node _wdata_T_25 = bits(wdata_rawIn_2.sExp, 5, 3) node _wdata_T_26 = mux(wdata_rawIn_2.isZero, UInt<3>(0h0), _wdata_T_25) node _wdata_T_27 = mux(wdata_rawIn_2.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _wdata_T_28 = or(_wdata_T_26, _wdata_T_27) node _wdata_T_29 = cat(wdata_rawIn_2.sign, _wdata_T_28) node _wdata_T_30 = bits(wdata_rawIn_2.sExp, 2, 0) node _wdata_T_31 = cat(_wdata_T_29, _wdata_T_30) node _wdata_T_32 = bits(wdata_rawIn_2.sig, 9, 0) node _wdata_T_33 = cat(_wdata_T_31, _wdata_T_32) node _wdata_swizzledNaN_T = bits(_wdata_T_24, 32, 29) node _wdata_swizzledNaN_T_1 = bits(_wdata_T_24, 22, 16) node _wdata_swizzledNaN_T_2 = andr(_wdata_swizzledNaN_T_1) node _wdata_swizzledNaN_T_3 = bits(_wdata_T_24, 27, 24) node _wdata_swizzledNaN_T_4 = bits(_wdata_T_33, 15, 15) node _wdata_swizzledNaN_T_5 = bits(_wdata_T_24, 22, 16) node _wdata_swizzledNaN_T_6 = bits(_wdata_T_33, 16, 16) node _wdata_swizzledNaN_T_7 = bits(_wdata_T_33, 14, 0) node wdata_swizzledNaN_lo_hi = cat(_wdata_swizzledNaN_T_5, _wdata_swizzledNaN_T_6) node wdata_swizzledNaN_lo = cat(wdata_swizzledNaN_lo_hi, _wdata_swizzledNaN_T_7) node wdata_swizzledNaN_hi_lo = cat(_wdata_swizzledNaN_T_3, _wdata_swizzledNaN_T_4) node wdata_swizzledNaN_hi_hi = cat(_wdata_swizzledNaN_T, _wdata_swizzledNaN_T_2) node wdata_swizzledNaN_hi = cat(wdata_swizzledNaN_hi_hi, wdata_swizzledNaN_hi_lo) node wdata_swizzledNaN = cat(wdata_swizzledNaN_hi, wdata_swizzledNaN_lo) node _wdata_T_34 = bits(_wdata_T_24, 31, 29) node _wdata_T_35 = andr(_wdata_T_34) node _wdata_T_36 = mux(_wdata_T_35, wdata_swizzledNaN, _wdata_T_24) node _wdata_swizzledNaN_T_8 = bits(_wdata_T_15, 64, 61) node _wdata_swizzledNaN_T_9 = bits(_wdata_T_15, 51, 32) node _wdata_swizzledNaN_T_10 = andr(_wdata_swizzledNaN_T_9) node _wdata_swizzledNaN_T_11 = bits(_wdata_T_15, 59, 53) node _wdata_swizzledNaN_T_12 = bits(_wdata_T_36, 31, 31) node _wdata_swizzledNaN_T_13 = bits(_wdata_T_15, 51, 32) node _wdata_swizzledNaN_T_14 = bits(_wdata_T_36, 32, 32) node _wdata_swizzledNaN_T_15 = bits(_wdata_T_36, 30, 0) node wdata_swizzledNaN_lo_hi_1 = cat(_wdata_swizzledNaN_T_13, _wdata_swizzledNaN_T_14) node wdata_swizzledNaN_lo_1 = cat(wdata_swizzledNaN_lo_hi_1, _wdata_swizzledNaN_T_15) node wdata_swizzledNaN_hi_lo_1 = cat(_wdata_swizzledNaN_T_11, _wdata_swizzledNaN_T_12) node wdata_swizzledNaN_hi_hi_1 = cat(_wdata_swizzledNaN_T_8, _wdata_swizzledNaN_T_10) node wdata_swizzledNaN_hi_1 = cat(wdata_swizzledNaN_hi_hi_1, wdata_swizzledNaN_hi_lo_1) node wdata_swizzledNaN_1 = cat(wdata_swizzledNaN_hi_1, wdata_swizzledNaN_lo_1) node _wdata_T_37 = bits(_wdata_T_15, 63, 61) node _wdata_T_38 = andr(_wdata_T_37) node wdata = mux(_wdata_T_38, wdata_swizzledNaN_1, _wdata_T_15) infer mport MPORT = regfile[load_wb_tag], clock connect MPORT, wdata node _unswizzled_T = bits(wdata, 31, 31) node _unswizzled_T_1 = bits(wdata, 52, 52) node _unswizzled_T_2 = bits(wdata, 30, 0) node unswizzled_hi = cat(_unswizzled_T, _unswizzled_T_1) node unswizzled = cat(unswizzled_hi, _unswizzled_T_2) node _prevOK_T = bits(wdata, 64, 60) node _prevOK_T_1 = andr(_prevOK_T) node _prevOK_T_2 = eq(_prevOK_T_1, UInt<1>(0h0)) node _prevOK_unswizzled_T = bits(unswizzled, 15, 15) node _prevOK_unswizzled_T_1 = bits(unswizzled, 23, 23) node _prevOK_unswizzled_T_2 = bits(unswizzled, 14, 0) node prevOK_unswizzled_hi = cat(_prevOK_unswizzled_T, _prevOK_unswizzled_T_1) node prevOK_unswizzled = cat(prevOK_unswizzled_hi, _prevOK_unswizzled_T_2) node _prevOK_prevOK_T = bits(unswizzled, 32, 28) node _prevOK_prevOK_T_1 = andr(_prevOK_prevOK_T) node _prevOK_prevOK_T_2 = eq(_prevOK_prevOK_T_1, UInt<1>(0h0)) node prevOK_prevOK = or(_prevOK_prevOK_T_2, UInt<1>(0h1)) node _prevOK_curOK_T = bits(unswizzled, 31, 29) node _prevOK_curOK_T_1 = andr(_prevOK_curOK_T) node _prevOK_curOK_T_2 = eq(_prevOK_curOK_T_1, UInt<1>(0h0)) node _prevOK_curOK_T_3 = bits(unswizzled, 28, 28) node _prevOK_curOK_T_4 = bits(unswizzled, 22, 16) node _prevOK_curOK_T_5 = andr(_prevOK_curOK_T_4) node _prevOK_curOK_T_6 = eq(_prevOK_curOK_T_3, _prevOK_curOK_T_5) node prevOK_curOK = or(_prevOK_curOK_T_2, _prevOK_curOK_T_6) node _prevOK_T_3 = and(prevOK_prevOK, prevOK_curOK) node prevOK = or(_prevOK_T_2, _prevOK_T_3) node _curOK_T = bits(wdata, 63, 61) node _curOK_T_1 = andr(_curOK_T) node _curOK_T_2 = eq(_curOK_T_1, UInt<1>(0h0)) node _curOK_T_3 = bits(wdata, 60, 60) node _curOK_T_4 = bits(wdata, 51, 32) node _curOK_T_5 = andr(_curOK_T_4) node _curOK_T_6 = eq(_curOK_T_3, _curOK_T_5) node curOK = or(_curOK_T_2, _curOK_T_6) node _T = and(prevOK, curOK) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed\n at FPU.scala:822 assert(consistent(wdata))\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert connect frfWriteBundle_0.wrdst, load_wb_tag connect frfWriteBundle_0.wrenf, UInt<1>(0h1) node frfWriteBundle_0_wrdata_unrecoded_rawIn_exp = bits(wdata, 63, 52) node _frfWriteBundle_0_wrdata_unrecoded_rawIn_isZero_T = bits(frfWriteBundle_0_wrdata_unrecoded_rawIn_exp, 11, 9) node frfWriteBundle_0_wrdata_unrecoded_rawIn_isZero = eq(_frfWriteBundle_0_wrdata_unrecoded_rawIn_isZero_T, UInt<1>(0h0)) node _frfWriteBundle_0_wrdata_unrecoded_rawIn_isSpecial_T = bits(frfWriteBundle_0_wrdata_unrecoded_rawIn_exp, 11, 10) node frfWriteBundle_0_wrdata_unrecoded_rawIn_isSpecial = eq(_frfWriteBundle_0_wrdata_unrecoded_rawIn_isSpecial_T, UInt<2>(0h3)) wire frfWriteBundle_0_wrdata_unrecoded_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} node _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_isNaN_T = bits(frfWriteBundle_0_wrdata_unrecoded_rawIn_exp, 9, 9) node _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_isNaN_T_1 = and(frfWriteBundle_0_wrdata_unrecoded_rawIn_isSpecial, _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_isNaN_T) connect frfWriteBundle_0_wrdata_unrecoded_rawIn.isNaN, _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_isNaN_T_1 node _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_isInf_T = bits(frfWriteBundle_0_wrdata_unrecoded_rawIn_exp, 9, 9) node _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_isInf_T_1 = eq(_frfWriteBundle_0_wrdata_unrecoded_rawIn_out_isInf_T, UInt<1>(0h0)) node _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_isInf_T_2 = and(frfWriteBundle_0_wrdata_unrecoded_rawIn_isSpecial, _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_isInf_T_1) connect frfWriteBundle_0_wrdata_unrecoded_rawIn.isInf, _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_isInf_T_2 connect frfWriteBundle_0_wrdata_unrecoded_rawIn.isZero, frfWriteBundle_0_wrdata_unrecoded_rawIn_isZero node _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sign_T = bits(wdata, 64, 64) connect frfWriteBundle_0_wrdata_unrecoded_rawIn.sign, _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sign_T node _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sExp_T = cvt(frfWriteBundle_0_wrdata_unrecoded_rawIn_exp) connect frfWriteBundle_0_wrdata_unrecoded_rawIn.sExp, _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sExp_T node _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sig_T = eq(frfWriteBundle_0_wrdata_unrecoded_rawIn_isZero, UInt<1>(0h0)) node _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sig_T) node _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sig_T_2 = bits(wdata, 51, 0) node _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sig_T_3 = cat(_frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sig_T_1, _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sig_T_2) connect frfWriteBundle_0_wrdata_unrecoded_rawIn.sig, _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sig_T_3 node frfWriteBundle_0_wrdata_unrecoded_isSubnormal = lt(frfWriteBundle_0_wrdata_unrecoded_rawIn.sExp, asSInt(UInt<12>(0h402))) node _frfWriteBundle_0_wrdata_unrecoded_denormShiftDist_T = bits(frfWriteBundle_0_wrdata_unrecoded_rawIn.sExp, 5, 0) node _frfWriteBundle_0_wrdata_unrecoded_denormShiftDist_T_1 = sub(UInt<1>(0h1), _frfWriteBundle_0_wrdata_unrecoded_denormShiftDist_T) node frfWriteBundle_0_wrdata_unrecoded_denormShiftDist = tail(_frfWriteBundle_0_wrdata_unrecoded_denormShiftDist_T_1, 1) node _frfWriteBundle_0_wrdata_unrecoded_denormFract_T = shr(frfWriteBundle_0_wrdata_unrecoded_rawIn.sig, 1) node _frfWriteBundle_0_wrdata_unrecoded_denormFract_T_1 = dshr(_frfWriteBundle_0_wrdata_unrecoded_denormFract_T, frfWriteBundle_0_wrdata_unrecoded_denormShiftDist) node frfWriteBundle_0_wrdata_unrecoded_denormFract = bits(_frfWriteBundle_0_wrdata_unrecoded_denormFract_T_1, 51, 0) node _frfWriteBundle_0_wrdata_unrecoded_expOut_T = bits(frfWriteBundle_0_wrdata_unrecoded_rawIn.sExp, 10, 0) node _frfWriteBundle_0_wrdata_unrecoded_expOut_T_1 = sub(_frfWriteBundle_0_wrdata_unrecoded_expOut_T, UInt<11>(0h401)) node _frfWriteBundle_0_wrdata_unrecoded_expOut_T_2 = tail(_frfWriteBundle_0_wrdata_unrecoded_expOut_T_1, 1) node _frfWriteBundle_0_wrdata_unrecoded_expOut_T_3 = mux(frfWriteBundle_0_wrdata_unrecoded_isSubnormal, UInt<1>(0h0), _frfWriteBundle_0_wrdata_unrecoded_expOut_T_2) node _frfWriteBundle_0_wrdata_unrecoded_expOut_T_4 = or(frfWriteBundle_0_wrdata_unrecoded_rawIn.isNaN, frfWriteBundle_0_wrdata_unrecoded_rawIn.isInf) node _frfWriteBundle_0_wrdata_unrecoded_expOut_T_5 = mux(_frfWriteBundle_0_wrdata_unrecoded_expOut_T_4, UInt<11>(0h7ff), UInt<11>(0h0)) node frfWriteBundle_0_wrdata_unrecoded_expOut = or(_frfWriteBundle_0_wrdata_unrecoded_expOut_T_3, _frfWriteBundle_0_wrdata_unrecoded_expOut_T_5) node _frfWriteBundle_0_wrdata_unrecoded_fractOut_T = bits(frfWriteBundle_0_wrdata_unrecoded_rawIn.sig, 51, 0) node _frfWriteBundle_0_wrdata_unrecoded_fractOut_T_1 = mux(frfWriteBundle_0_wrdata_unrecoded_rawIn.isInf, UInt<1>(0h0), _frfWriteBundle_0_wrdata_unrecoded_fractOut_T) node frfWriteBundle_0_wrdata_unrecoded_fractOut = mux(frfWriteBundle_0_wrdata_unrecoded_isSubnormal, frfWriteBundle_0_wrdata_unrecoded_denormFract, _frfWriteBundle_0_wrdata_unrecoded_fractOut_T_1) node frfWriteBundle_0_wrdata_unrecoded_hi = cat(frfWriteBundle_0_wrdata_unrecoded_rawIn.sign, frfWriteBundle_0_wrdata_unrecoded_expOut) node frfWriteBundle_0_wrdata_unrecoded = cat(frfWriteBundle_0_wrdata_unrecoded_hi, frfWriteBundle_0_wrdata_unrecoded_fractOut) node _frfWriteBundle_0_wrdata_prevRecoded_T = bits(wdata, 31, 31) node _frfWriteBundle_0_wrdata_prevRecoded_T_1 = bits(wdata, 52, 52) node _frfWriteBundle_0_wrdata_prevRecoded_T_2 = bits(wdata, 30, 0) node frfWriteBundle_0_wrdata_prevRecoded_hi = cat(_frfWriteBundle_0_wrdata_prevRecoded_T, _frfWriteBundle_0_wrdata_prevRecoded_T_1) node frfWriteBundle_0_wrdata_prevRecoded = cat(frfWriteBundle_0_wrdata_prevRecoded_hi, _frfWriteBundle_0_wrdata_prevRecoded_T_2) node frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_exp = bits(frfWriteBundle_0_wrdata_prevRecoded, 31, 23) node _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isZero_T = bits(frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_exp, 8, 6) node frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isZero = eq(_frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isZero_T, UInt<1>(0h0)) node _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isSpecial_T = bits(frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_exp, 8, 7) node frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isSpecial = eq(_frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isSpecial_T, UInt<2>(0h3)) wire frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_isNaN_T = bits(frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_exp, 6, 6) node _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1 = and(frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isSpecial, _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_isNaN_T) connect frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn.isNaN, _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1 node _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_isInf_T = bits(frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_exp, 6, 6) node _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_isInf_T_1 = eq(_frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_isInf_T, UInt<1>(0h0)) node _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2 = and(frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isSpecial, _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_isInf_T_1) connect frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn.isInf, _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2 connect frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn.isZero, frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isZero node _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_sign_T = bits(frfWriteBundle_0_wrdata_prevRecoded, 32, 32) connect frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn.sign, _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_sign_T node _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_sExp_T = cvt(frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_exp) connect frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn.sExp, _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_sExp_T node _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_sig_T = eq(frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isZero, UInt<1>(0h0)) node _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_sig_T) node _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_sig_T_2 = bits(frfWriteBundle_0_wrdata_prevRecoded, 22, 0) node _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_sig_T_3 = cat(_frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_sig_T_1, _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_sig_T_2) connect frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn.sig, _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_sig_T_3 node frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_isSubnormal = lt(frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn.sExp, asSInt(UInt<9>(0h82))) node _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_denormShiftDist_T = bits(frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn.sExp, 4, 0) node _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_denormShiftDist_T_1 = sub(UInt<1>(0h1), _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_denormShiftDist_T) node frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_denormShiftDist = tail(_frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_denormShiftDist_T_1, 1) node _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_denormFract_T = shr(frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn.sig, 1) node _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_denormFract_T_1 = dshr(_frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_denormFract_T, frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_denormShiftDist) node frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_denormFract = bits(_frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_denormFract_T_1, 22, 0) node _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_expOut_T = bits(frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn.sExp, 7, 0) node _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_expOut_T_1 = sub(_frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_expOut_T, UInt<8>(0h81)) node _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_expOut_T_2 = tail(_frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_expOut_T_1, 1) node _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_expOut_T_3 = mux(frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_isSubnormal, UInt<1>(0h0), _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_expOut_T_2) node _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_expOut_T_4 = or(frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn.isNaN, frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn.isInf) node _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_expOut_T_5 = mux(_frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_expOut_T_4, UInt<8>(0hff), UInt<8>(0h0)) node frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_expOut = or(_frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_expOut_T_3, _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_expOut_T_5) node _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_fractOut_T = bits(frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn.sig, 22, 0) node _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_fractOut_T_1 = mux(frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn.isInf, UInt<1>(0h0), _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_fractOut_T) node frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_fractOut = mux(frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_isSubnormal, frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_denormFract, _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_fractOut_T_1) node frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_hi = cat(frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn.sign, frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_expOut) node frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded = cat(frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_hi, frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_fractOut) node _frfWriteBundle_0_wrdata_prevUnrecoded_prevRecoded_T = bits(frfWriteBundle_0_wrdata_prevRecoded, 15, 15) node _frfWriteBundle_0_wrdata_prevUnrecoded_prevRecoded_T_1 = bits(frfWriteBundle_0_wrdata_prevRecoded, 23, 23) node _frfWriteBundle_0_wrdata_prevUnrecoded_prevRecoded_T_2 = bits(frfWriteBundle_0_wrdata_prevRecoded, 14, 0) node frfWriteBundle_0_wrdata_prevUnrecoded_prevRecoded_hi = cat(_frfWriteBundle_0_wrdata_prevUnrecoded_prevRecoded_T, _frfWriteBundle_0_wrdata_prevUnrecoded_prevRecoded_T_1) node frfWriteBundle_0_wrdata_prevUnrecoded_prevRecoded = cat(frfWriteBundle_0_wrdata_prevUnrecoded_prevRecoded_hi, _frfWriteBundle_0_wrdata_prevUnrecoded_prevRecoded_T_2) node frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_exp = bits(frfWriteBundle_0_wrdata_prevUnrecoded_prevRecoded, 15, 10) node _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isZero_T = bits(frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_exp, 5, 3) node frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isZero = eq(_frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isZero_T, UInt<1>(0h0)) node _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T = bits(frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_exp, 5, 4) node frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isSpecial = eq(_frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T, UInt<2>(0h3)) wire frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<12>} node _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T = bits(frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_exp, 3, 3) node _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1 = and(frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isSpecial, _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T) connect frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn.isNaN, _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1 node _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T = bits(frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_exp, 3, 3) node _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_1 = eq(_frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T, UInt<1>(0h0)) node _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2 = and(frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isSpecial, _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_1) connect frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn.isInf, _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2 connect frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn.isZero, frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isZero node _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T = bits(frfWriteBundle_0_wrdata_prevUnrecoded_prevRecoded, 16, 16) connect frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn.sign, _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T node _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T = cvt(frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_exp) connect frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn.sExp, _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T node _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T = eq(frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isZero, UInt<1>(0h0)) node _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T) node _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_2 = bits(frfWriteBundle_0_wrdata_prevUnrecoded_prevRecoded, 9, 0) node _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3 = cat(_frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_1, _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_2) connect frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn.sig, _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3 node frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_isSubnormal = lt(frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn.sExp, asSInt(UInt<6>(0h12))) node _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_denormShiftDist_T = bits(frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn.sExp, 3, 0) node _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_denormShiftDist_T_1 = sub(UInt<1>(0h1), _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_denormShiftDist_T) node frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_denormShiftDist = tail(_frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_denormShiftDist_T_1, 1) node _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_denormFract_T = shr(frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn.sig, 1) node _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_denormFract_T_1 = dshr(_frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_denormFract_T, frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_denormShiftDist) node frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_denormFract = bits(_frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_denormFract_T_1, 9, 0) node _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_expOut_T = bits(frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn.sExp, 4, 0) node _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_expOut_T_1 = sub(_frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_expOut_T, UInt<5>(0h11)) node _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_expOut_T_2 = tail(_frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_expOut_T_1, 1) node _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_expOut_T_3 = mux(frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_isSubnormal, UInt<1>(0h0), _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_expOut_T_2) node _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_expOut_T_4 = or(frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn.isNaN, frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn.isInf) node _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_expOut_T_5 = mux(_frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_expOut_T_4, UInt<5>(0h1f), UInt<5>(0h0)) node frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_expOut = or(_frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_expOut_T_3, _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_expOut_T_5) node _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_fractOut_T = bits(frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn.sig, 9, 0) node _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_fractOut_T_1 = mux(frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn.isInf, UInt<1>(0h0), _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_fractOut_T) node frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_fractOut = mux(frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_isSubnormal, frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_denormFract, _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_fractOut_T_1) node frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_hi = cat(frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn.sign, frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_expOut) node frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded = cat(frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_hi, frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_fractOut) node _frfWriteBundle_0_wrdata_prevUnrecoded_T = shr(frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded, 16) node _frfWriteBundle_0_wrdata_prevUnrecoded_T_1 = bits(frfWriteBundle_0_wrdata_prevRecoded, 31, 29) node _frfWriteBundle_0_wrdata_prevUnrecoded_T_2 = andr(_frfWriteBundle_0_wrdata_prevUnrecoded_T_1) node _frfWriteBundle_0_wrdata_prevUnrecoded_T_3 = bits(frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded, 15, 0) node _frfWriteBundle_0_wrdata_prevUnrecoded_T_4 = mux(_frfWriteBundle_0_wrdata_prevUnrecoded_T_2, frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded, _frfWriteBundle_0_wrdata_prevUnrecoded_T_3) node frfWriteBundle_0_wrdata_prevUnrecoded = cat(_frfWriteBundle_0_wrdata_prevUnrecoded_T, _frfWriteBundle_0_wrdata_prevUnrecoded_T_4) node _frfWriteBundle_0_wrdata_T = shr(frfWriteBundle_0_wrdata_unrecoded, 32) node _frfWriteBundle_0_wrdata_T_1 = bits(wdata, 63, 61) node _frfWriteBundle_0_wrdata_T_2 = andr(_frfWriteBundle_0_wrdata_T_1) node _frfWriteBundle_0_wrdata_T_3 = bits(frfWriteBundle_0_wrdata_unrecoded, 31, 0) node _frfWriteBundle_0_wrdata_T_4 = mux(_frfWriteBundle_0_wrdata_T_2, frfWriteBundle_0_wrdata_prevUnrecoded, _frfWriteBundle_0_wrdata_T_3) node _frfWriteBundle_0_wrdata_T_5 = cat(_frfWriteBundle_0_wrdata_T, _frfWriteBundle_0_wrdata_T_4) connect frfWriteBundle_0.wrdata, _frfWriteBundle_0_wrdata_T_5 node _ex_rs_T = or(ex_ra_0, UInt<5>(0h0)) node _ex_rs_T_1 = bits(_ex_rs_T, 4, 0) infer mport ex_rs_0 = regfile[_ex_rs_T_1], clock node _ex_rs_T_2 = or(ex_ra_1, UInt<5>(0h0)) node _ex_rs_T_3 = bits(_ex_rs_T_2, 4, 0) infer mport ex_rs_1 = regfile[_ex_rs_T_3], clock node _ex_rs_T_4 = or(ex_ra_2, UInt<5>(0h0)) node _ex_rs_T_5 = bits(_ex_rs_T_4, 4, 0) infer mport ex_rs_2 = regfile[_ex_rs_T_5], clock when io.valid : when id_ctrl.ren1 : node _T_4 = eq(id_ctrl.swap12, UInt<1>(0h0)) when _T_4 : node _ex_ra_0_T = bits(io.inst, 19, 15) connect ex_ra_0, _ex_ra_0_T when id_ctrl.swap12 : node _ex_ra_1_T = bits(io.inst, 19, 15) connect ex_ra_1, _ex_ra_1_T when id_ctrl.ren2 : when id_ctrl.swap12 : node _ex_ra_0_T_1 = bits(io.inst, 24, 20) connect ex_ra_0, _ex_ra_0_T_1 when id_ctrl.swap23 : node _ex_ra_2_T = bits(io.inst, 24, 20) connect ex_ra_2, _ex_ra_2_T node _T_5 = eq(id_ctrl.swap12, UInt<1>(0h0)) node _T_6 = eq(id_ctrl.swap23, UInt<1>(0h0)) node _T_7 = and(_T_5, _T_6) when _T_7 : node _ex_ra_1_T_1 = bits(io.inst, 24, 20) connect ex_ra_1, _ex_ra_1_T_1 when id_ctrl.ren3 : node _ex_ra_2_T_1 = bits(io.inst, 31, 27) connect ex_ra_2, _ex_ra_2_T_1 node _ex_rm_T = bits(ex_reg_inst, 14, 12) node _ex_rm_T_1 = eq(_ex_rm_T, UInt<3>(0h7)) node _ex_rm_T_2 = bits(ex_reg_inst, 14, 12) node ex_rm = mux(_ex_rm_T_1, io.fcsr_rm, _ex_rm_T_2) inst sfma of FPUFMAPipe_l3_f32_1 connect sfma.clock, clock connect sfma.reset, reset node _sfma_io_in_valid_T = and(req_valid, ex_ctrl.fma) node _sfma_io_in_valid_T_1 = eq(ex_ctrl.typeTagOut, UInt<1>(0h1)) node _sfma_io_in_valid_T_2 = and(_sfma_io_in_valid_T, _sfma_io_in_valid_T_1) connect sfma.io.in.valid, _sfma_io_in_valid_T_2 wire sfma_io_in_bits_req : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>} connect sfma_io_in_bits_req.vec, ex_ctrl.vec connect sfma_io_in_bits_req.wflags, ex_ctrl.wflags connect sfma_io_in_bits_req.sqrt, ex_ctrl.sqrt connect sfma_io_in_bits_req.div, ex_ctrl.div connect sfma_io_in_bits_req.fma, ex_ctrl.fma connect sfma_io_in_bits_req.fastpipe, ex_ctrl.fastpipe connect sfma_io_in_bits_req.toint, ex_ctrl.toint connect sfma_io_in_bits_req.fromint, ex_ctrl.fromint connect sfma_io_in_bits_req.typeTagOut, ex_ctrl.typeTagOut connect sfma_io_in_bits_req.typeTagIn, ex_ctrl.typeTagIn connect sfma_io_in_bits_req.swap23, ex_ctrl.swap23 connect sfma_io_in_bits_req.swap12, ex_ctrl.swap12 connect sfma_io_in_bits_req.ren3, ex_ctrl.ren3 connect sfma_io_in_bits_req.ren2, ex_ctrl.ren2 connect sfma_io_in_bits_req.ren1, ex_ctrl.ren1 connect sfma_io_in_bits_req.wen, ex_ctrl.wen connect sfma_io_in_bits_req.ldst, ex_ctrl.ldst connect sfma_io_in_bits_req.rm, ex_rm node _sfma_io_in_bits_req_in1_prev_unswizzled_T = bits(ex_rs_0, 31, 31) node _sfma_io_in_bits_req_in1_prev_unswizzled_T_1 = bits(ex_rs_0, 52, 52) node _sfma_io_in_bits_req_in1_prev_unswizzled_T_2 = bits(ex_rs_0, 30, 0) node sfma_io_in_bits_req_in1_prev_unswizzled_hi = cat(_sfma_io_in_bits_req_in1_prev_unswizzled_T, _sfma_io_in_bits_req_in1_prev_unswizzled_T_1) node sfma_io_in_bits_req_in1_floats_1 = cat(sfma_io_in_bits_req_in1_prev_unswizzled_hi, _sfma_io_in_bits_req_in1_prev_unswizzled_T_2) node _sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T = bits(sfma_io_in_bits_req_in1_floats_1, 15, 15) node _sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_1 = bits(sfma_io_in_bits_req_in1_floats_1, 23, 23) node _sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_2 = bits(sfma_io_in_bits_req_in1_floats_1, 14, 0) node sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_hi = cat(_sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T, _sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_1) node sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled = cat(sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_hi, _sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_2) node sfma_io_in_bits_req_in1_prev_prev_prev_prev_sign = bits(sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled, 16, 16) node sfma_io_in_bits_req_in1_prev_prev_prev_prev_fractIn = bits(sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled, 9, 0) node sfma_io_in_bits_req_in1_prev_prev_prev_prev_expIn = bits(sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled, 15, 10) node _sfma_io_in_bits_req_in1_prev_prev_prev_prev_fractOut_T = shl(sfma_io_in_bits_req_in1_prev_prev_prev_prev_fractIn, 24) node sfma_io_in_bits_req_in1_prev_prev_prev_prev_fractOut = shr(_sfma_io_in_bits_req_in1_prev_prev_prev_prev_fractOut_T, 11) node sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode = bits(sfma_io_in_bits_req_in1_prev_prev_prev_prev_expIn, 5, 3) node _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T = add(sfma_io_in_bits_req_in1_prev_prev_prev_prev_expIn, UInt<9>(0h100)) node _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_1 = tail(_sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T, 1) node _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_2 = sub(_sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_1, UInt<6>(0h20)) node sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase = tail(_sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_2, 1) node _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T = eq(sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode, UInt<1>(0h0)) node _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_1 = geq(sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode, UInt<3>(0h6)) node _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_2 = or(_sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T, _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_1) node _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_3 = bits(sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase, 5, 0) node _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_4 = cat(sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode, _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_3) node _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_5 = bits(sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase, 8, 0) node sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut = mux(_sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_2, _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_4, _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_5) node sfma_io_in_bits_req_in1_prev_prev_prev_prev_hi = cat(sfma_io_in_bits_req_in1_prev_prev_prev_prev_sign, sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut) node sfma_io_in_bits_req_in1_floats_0 = cat(sfma_io_in_bits_req_in1_prev_prev_prev_prev_hi, sfma_io_in_bits_req_in1_prev_prev_prev_prev_fractOut) node _sfma_io_in_bits_req_in1_prev_prev_prev_isbox_T = bits(sfma_io_in_bits_req_in1_floats_1, 32, 28) node sfma_io_in_bits_req_in1_prev_prev_prev_isbox = andr(_sfma_io_in_bits_req_in1_prev_prev_prev_isbox_T) node sfma_io_in_bits_req_in1_prev_prev_0_1 = and(sfma_io_in_bits_req_in1_prev_prev_prev_isbox, UInt<1>(0h1)) node _sfma_io_in_bits_req_in1_prev_isbox_T = bits(ex_rs_0, 64, 60) node sfma_io_in_bits_req_in1_prev_isbox = andr(_sfma_io_in_bits_req_in1_prev_isbox_T) node sfma_io_in_bits_req_in1_oks_0 = and(sfma_io_in_bits_req_in1_prev_isbox, sfma_io_in_bits_req_in1_prev_prev_0_1) node sfma_io_in_bits_req_in1_oks_1 = and(sfma_io_in_bits_req_in1_prev_isbox, UInt<1>(0h1)) node sfma_io_in_bits_req_in1_sign = bits(ex_rs_0, 64, 64) node sfma_io_in_bits_req_in1_fractIn = bits(ex_rs_0, 51, 0) node sfma_io_in_bits_req_in1_expIn = bits(ex_rs_0, 63, 52) node _sfma_io_in_bits_req_in1_fractOut_T = shl(sfma_io_in_bits_req_in1_fractIn, 24) node sfma_io_in_bits_req_in1_fractOut = shr(_sfma_io_in_bits_req_in1_fractOut_T, 53) node sfma_io_in_bits_req_in1_expOut_expCode = bits(sfma_io_in_bits_req_in1_expIn, 11, 9) node _sfma_io_in_bits_req_in1_expOut_commonCase_T = add(sfma_io_in_bits_req_in1_expIn, UInt<9>(0h100)) node _sfma_io_in_bits_req_in1_expOut_commonCase_T_1 = tail(_sfma_io_in_bits_req_in1_expOut_commonCase_T, 1) node _sfma_io_in_bits_req_in1_expOut_commonCase_T_2 = sub(_sfma_io_in_bits_req_in1_expOut_commonCase_T_1, UInt<12>(0h800)) node sfma_io_in_bits_req_in1_expOut_commonCase = tail(_sfma_io_in_bits_req_in1_expOut_commonCase_T_2, 1) node _sfma_io_in_bits_req_in1_expOut_T = eq(sfma_io_in_bits_req_in1_expOut_expCode, UInt<1>(0h0)) node _sfma_io_in_bits_req_in1_expOut_T_1 = geq(sfma_io_in_bits_req_in1_expOut_expCode, UInt<3>(0h6)) node _sfma_io_in_bits_req_in1_expOut_T_2 = or(_sfma_io_in_bits_req_in1_expOut_T, _sfma_io_in_bits_req_in1_expOut_T_1) node _sfma_io_in_bits_req_in1_expOut_T_3 = bits(sfma_io_in_bits_req_in1_expOut_commonCase, 5, 0) node _sfma_io_in_bits_req_in1_expOut_T_4 = cat(sfma_io_in_bits_req_in1_expOut_expCode, _sfma_io_in_bits_req_in1_expOut_T_3) node _sfma_io_in_bits_req_in1_expOut_T_5 = bits(sfma_io_in_bits_req_in1_expOut_commonCase, 8, 0) node sfma_io_in_bits_req_in1_expOut = mux(_sfma_io_in_bits_req_in1_expOut_T_2, _sfma_io_in_bits_req_in1_expOut_T_4, _sfma_io_in_bits_req_in1_expOut_T_5) node sfma_io_in_bits_req_in1_hi = cat(sfma_io_in_bits_req_in1_sign, sfma_io_in_bits_req_in1_expOut) node sfma_io_in_bits_req_in1_floats_2 = cat(sfma_io_in_bits_req_in1_hi, sfma_io_in_bits_req_in1_fractOut) node _sfma_io_in_bits_req_in1_T = mux(sfma_io_in_bits_req_in1_oks_1, UInt<1>(0h0), UInt<33>(0he0400000)) node _sfma_io_in_bits_req_in1_T_1 = or(sfma_io_in_bits_req_in1_floats_1, _sfma_io_in_bits_req_in1_T) connect sfma_io_in_bits_req.in1, _sfma_io_in_bits_req_in1_T_1 node _sfma_io_in_bits_req_in2_prev_unswizzled_T = bits(ex_rs_1, 31, 31) node _sfma_io_in_bits_req_in2_prev_unswizzled_T_1 = bits(ex_rs_1, 52, 52) node _sfma_io_in_bits_req_in2_prev_unswizzled_T_2 = bits(ex_rs_1, 30, 0) node sfma_io_in_bits_req_in2_prev_unswizzled_hi = cat(_sfma_io_in_bits_req_in2_prev_unswizzled_T, _sfma_io_in_bits_req_in2_prev_unswizzled_T_1) node sfma_io_in_bits_req_in2_floats_1 = cat(sfma_io_in_bits_req_in2_prev_unswizzled_hi, _sfma_io_in_bits_req_in2_prev_unswizzled_T_2) node _sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T = bits(sfma_io_in_bits_req_in2_floats_1, 15, 15) node _sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_1 = bits(sfma_io_in_bits_req_in2_floats_1, 23, 23) node _sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_2 = bits(sfma_io_in_bits_req_in2_floats_1, 14, 0) node sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_hi = cat(_sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T, _sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_1) node sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled = cat(sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_hi, _sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_2) node sfma_io_in_bits_req_in2_prev_prev_prev_prev_sign = bits(sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled, 16, 16) node sfma_io_in_bits_req_in2_prev_prev_prev_prev_fractIn = bits(sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled, 9, 0) node sfma_io_in_bits_req_in2_prev_prev_prev_prev_expIn = bits(sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled, 15, 10) node _sfma_io_in_bits_req_in2_prev_prev_prev_prev_fractOut_T = shl(sfma_io_in_bits_req_in2_prev_prev_prev_prev_fractIn, 24) node sfma_io_in_bits_req_in2_prev_prev_prev_prev_fractOut = shr(_sfma_io_in_bits_req_in2_prev_prev_prev_prev_fractOut_T, 11) node sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode = bits(sfma_io_in_bits_req_in2_prev_prev_prev_prev_expIn, 5, 3) node _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T = add(sfma_io_in_bits_req_in2_prev_prev_prev_prev_expIn, UInt<9>(0h100)) node _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_1 = tail(_sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T, 1) node _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_2 = sub(_sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_1, UInt<6>(0h20)) node sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase = tail(_sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_2, 1) node _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T = eq(sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode, UInt<1>(0h0)) node _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_1 = geq(sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode, UInt<3>(0h6)) node _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_2 = or(_sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T, _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_1) node _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_3 = bits(sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase, 5, 0) node _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_4 = cat(sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode, _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_3) node _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_5 = bits(sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase, 8, 0) node sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut = mux(_sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_2, _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_4, _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_5) node sfma_io_in_bits_req_in2_prev_prev_prev_prev_hi = cat(sfma_io_in_bits_req_in2_prev_prev_prev_prev_sign, sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut) node sfma_io_in_bits_req_in2_floats_0 = cat(sfma_io_in_bits_req_in2_prev_prev_prev_prev_hi, sfma_io_in_bits_req_in2_prev_prev_prev_prev_fractOut) node _sfma_io_in_bits_req_in2_prev_prev_prev_isbox_T = bits(sfma_io_in_bits_req_in2_floats_1, 32, 28) node sfma_io_in_bits_req_in2_prev_prev_prev_isbox = andr(_sfma_io_in_bits_req_in2_prev_prev_prev_isbox_T) node sfma_io_in_bits_req_in2_prev_prev_0_1 = and(sfma_io_in_bits_req_in2_prev_prev_prev_isbox, UInt<1>(0h1)) node _sfma_io_in_bits_req_in2_prev_isbox_T = bits(ex_rs_1, 64, 60) node sfma_io_in_bits_req_in2_prev_isbox = andr(_sfma_io_in_bits_req_in2_prev_isbox_T) node sfma_io_in_bits_req_in2_oks_0 = and(sfma_io_in_bits_req_in2_prev_isbox, sfma_io_in_bits_req_in2_prev_prev_0_1) node sfma_io_in_bits_req_in2_oks_1 = and(sfma_io_in_bits_req_in2_prev_isbox, UInt<1>(0h1)) node sfma_io_in_bits_req_in2_sign = bits(ex_rs_1, 64, 64) node sfma_io_in_bits_req_in2_fractIn = bits(ex_rs_1, 51, 0) node sfma_io_in_bits_req_in2_expIn = bits(ex_rs_1, 63, 52) node _sfma_io_in_bits_req_in2_fractOut_T = shl(sfma_io_in_bits_req_in2_fractIn, 24) node sfma_io_in_bits_req_in2_fractOut = shr(_sfma_io_in_bits_req_in2_fractOut_T, 53) node sfma_io_in_bits_req_in2_expOut_expCode = bits(sfma_io_in_bits_req_in2_expIn, 11, 9) node _sfma_io_in_bits_req_in2_expOut_commonCase_T = add(sfma_io_in_bits_req_in2_expIn, UInt<9>(0h100)) node _sfma_io_in_bits_req_in2_expOut_commonCase_T_1 = tail(_sfma_io_in_bits_req_in2_expOut_commonCase_T, 1) node _sfma_io_in_bits_req_in2_expOut_commonCase_T_2 = sub(_sfma_io_in_bits_req_in2_expOut_commonCase_T_1, UInt<12>(0h800)) node sfma_io_in_bits_req_in2_expOut_commonCase = tail(_sfma_io_in_bits_req_in2_expOut_commonCase_T_2, 1) node _sfma_io_in_bits_req_in2_expOut_T = eq(sfma_io_in_bits_req_in2_expOut_expCode, UInt<1>(0h0)) node _sfma_io_in_bits_req_in2_expOut_T_1 = geq(sfma_io_in_bits_req_in2_expOut_expCode, UInt<3>(0h6)) node _sfma_io_in_bits_req_in2_expOut_T_2 = or(_sfma_io_in_bits_req_in2_expOut_T, _sfma_io_in_bits_req_in2_expOut_T_1) node _sfma_io_in_bits_req_in2_expOut_T_3 = bits(sfma_io_in_bits_req_in2_expOut_commonCase, 5, 0) node _sfma_io_in_bits_req_in2_expOut_T_4 = cat(sfma_io_in_bits_req_in2_expOut_expCode, _sfma_io_in_bits_req_in2_expOut_T_3) node _sfma_io_in_bits_req_in2_expOut_T_5 = bits(sfma_io_in_bits_req_in2_expOut_commonCase, 8, 0) node sfma_io_in_bits_req_in2_expOut = mux(_sfma_io_in_bits_req_in2_expOut_T_2, _sfma_io_in_bits_req_in2_expOut_T_4, _sfma_io_in_bits_req_in2_expOut_T_5) node sfma_io_in_bits_req_in2_hi = cat(sfma_io_in_bits_req_in2_sign, sfma_io_in_bits_req_in2_expOut) node sfma_io_in_bits_req_in2_floats_2 = cat(sfma_io_in_bits_req_in2_hi, sfma_io_in_bits_req_in2_fractOut) node _sfma_io_in_bits_req_in2_T = mux(sfma_io_in_bits_req_in2_oks_1, UInt<1>(0h0), UInt<33>(0he0400000)) node _sfma_io_in_bits_req_in2_T_1 = or(sfma_io_in_bits_req_in2_floats_1, _sfma_io_in_bits_req_in2_T) connect sfma_io_in_bits_req.in2, _sfma_io_in_bits_req_in2_T_1 node _sfma_io_in_bits_req_in3_prev_unswizzled_T = bits(ex_rs_2, 31, 31) node _sfma_io_in_bits_req_in3_prev_unswizzled_T_1 = bits(ex_rs_2, 52, 52) node _sfma_io_in_bits_req_in3_prev_unswizzled_T_2 = bits(ex_rs_2, 30, 0) node sfma_io_in_bits_req_in3_prev_unswizzled_hi = cat(_sfma_io_in_bits_req_in3_prev_unswizzled_T, _sfma_io_in_bits_req_in3_prev_unswizzled_T_1) node sfma_io_in_bits_req_in3_floats_1 = cat(sfma_io_in_bits_req_in3_prev_unswizzled_hi, _sfma_io_in_bits_req_in3_prev_unswizzled_T_2) node _sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T = bits(sfma_io_in_bits_req_in3_floats_1, 15, 15) node _sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_1 = bits(sfma_io_in_bits_req_in3_floats_1, 23, 23) node _sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_2 = bits(sfma_io_in_bits_req_in3_floats_1, 14, 0) node sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_hi = cat(_sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T, _sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_1) node sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled = cat(sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_hi, _sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_2) node sfma_io_in_bits_req_in3_prev_prev_prev_prev_sign = bits(sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled, 16, 16) node sfma_io_in_bits_req_in3_prev_prev_prev_prev_fractIn = bits(sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled, 9, 0) node sfma_io_in_bits_req_in3_prev_prev_prev_prev_expIn = bits(sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled, 15, 10) node _sfma_io_in_bits_req_in3_prev_prev_prev_prev_fractOut_T = shl(sfma_io_in_bits_req_in3_prev_prev_prev_prev_fractIn, 24) node sfma_io_in_bits_req_in3_prev_prev_prev_prev_fractOut = shr(_sfma_io_in_bits_req_in3_prev_prev_prev_prev_fractOut_T, 11) node sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode = bits(sfma_io_in_bits_req_in3_prev_prev_prev_prev_expIn, 5, 3) node _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T = add(sfma_io_in_bits_req_in3_prev_prev_prev_prev_expIn, UInt<9>(0h100)) node _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_1 = tail(_sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T, 1) node _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_2 = sub(_sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_1, UInt<6>(0h20)) node sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase = tail(_sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_2, 1) node _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T = eq(sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode, UInt<1>(0h0)) node _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_1 = geq(sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode, UInt<3>(0h6)) node _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_2 = or(_sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T, _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_1) node _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_3 = bits(sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase, 5, 0) node _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_4 = cat(sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode, _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_3) node _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_5 = bits(sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase, 8, 0) node sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut = mux(_sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_2, _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_4, _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_5) node sfma_io_in_bits_req_in3_prev_prev_prev_prev_hi = cat(sfma_io_in_bits_req_in3_prev_prev_prev_prev_sign, sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut) node sfma_io_in_bits_req_in3_floats_0 = cat(sfma_io_in_bits_req_in3_prev_prev_prev_prev_hi, sfma_io_in_bits_req_in3_prev_prev_prev_prev_fractOut) node _sfma_io_in_bits_req_in3_prev_prev_prev_isbox_T = bits(sfma_io_in_bits_req_in3_floats_1, 32, 28) node sfma_io_in_bits_req_in3_prev_prev_prev_isbox = andr(_sfma_io_in_bits_req_in3_prev_prev_prev_isbox_T) node sfma_io_in_bits_req_in3_prev_prev_0_1 = and(sfma_io_in_bits_req_in3_prev_prev_prev_isbox, UInt<1>(0h1)) node _sfma_io_in_bits_req_in3_prev_isbox_T = bits(ex_rs_2, 64, 60) node sfma_io_in_bits_req_in3_prev_isbox = andr(_sfma_io_in_bits_req_in3_prev_isbox_T) node sfma_io_in_bits_req_in3_oks_0 = and(sfma_io_in_bits_req_in3_prev_isbox, sfma_io_in_bits_req_in3_prev_prev_0_1) node sfma_io_in_bits_req_in3_oks_1 = and(sfma_io_in_bits_req_in3_prev_isbox, UInt<1>(0h1)) node sfma_io_in_bits_req_in3_sign = bits(ex_rs_2, 64, 64) node sfma_io_in_bits_req_in3_fractIn = bits(ex_rs_2, 51, 0) node sfma_io_in_bits_req_in3_expIn = bits(ex_rs_2, 63, 52) node _sfma_io_in_bits_req_in3_fractOut_T = shl(sfma_io_in_bits_req_in3_fractIn, 24) node sfma_io_in_bits_req_in3_fractOut = shr(_sfma_io_in_bits_req_in3_fractOut_T, 53) node sfma_io_in_bits_req_in3_expOut_expCode = bits(sfma_io_in_bits_req_in3_expIn, 11, 9) node _sfma_io_in_bits_req_in3_expOut_commonCase_T = add(sfma_io_in_bits_req_in3_expIn, UInt<9>(0h100)) node _sfma_io_in_bits_req_in3_expOut_commonCase_T_1 = tail(_sfma_io_in_bits_req_in3_expOut_commonCase_T, 1) node _sfma_io_in_bits_req_in3_expOut_commonCase_T_2 = sub(_sfma_io_in_bits_req_in3_expOut_commonCase_T_1, UInt<12>(0h800)) node sfma_io_in_bits_req_in3_expOut_commonCase = tail(_sfma_io_in_bits_req_in3_expOut_commonCase_T_2, 1) node _sfma_io_in_bits_req_in3_expOut_T = eq(sfma_io_in_bits_req_in3_expOut_expCode, UInt<1>(0h0)) node _sfma_io_in_bits_req_in3_expOut_T_1 = geq(sfma_io_in_bits_req_in3_expOut_expCode, UInt<3>(0h6)) node _sfma_io_in_bits_req_in3_expOut_T_2 = or(_sfma_io_in_bits_req_in3_expOut_T, _sfma_io_in_bits_req_in3_expOut_T_1) node _sfma_io_in_bits_req_in3_expOut_T_3 = bits(sfma_io_in_bits_req_in3_expOut_commonCase, 5, 0) node _sfma_io_in_bits_req_in3_expOut_T_4 = cat(sfma_io_in_bits_req_in3_expOut_expCode, _sfma_io_in_bits_req_in3_expOut_T_3) node _sfma_io_in_bits_req_in3_expOut_T_5 = bits(sfma_io_in_bits_req_in3_expOut_commonCase, 8, 0) node sfma_io_in_bits_req_in3_expOut = mux(_sfma_io_in_bits_req_in3_expOut_T_2, _sfma_io_in_bits_req_in3_expOut_T_4, _sfma_io_in_bits_req_in3_expOut_T_5) node sfma_io_in_bits_req_in3_hi = cat(sfma_io_in_bits_req_in3_sign, sfma_io_in_bits_req_in3_expOut) node sfma_io_in_bits_req_in3_floats_2 = cat(sfma_io_in_bits_req_in3_hi, sfma_io_in_bits_req_in3_fractOut) node _sfma_io_in_bits_req_in3_T = mux(sfma_io_in_bits_req_in3_oks_1, UInt<1>(0h0), UInt<33>(0he0400000)) node _sfma_io_in_bits_req_in3_T_1 = or(sfma_io_in_bits_req_in3_floats_1, _sfma_io_in_bits_req_in3_T) connect sfma_io_in_bits_req.in3, _sfma_io_in_bits_req_in3_T_1 node _sfma_io_in_bits_req_typ_T = bits(ex_reg_inst, 21, 20) connect sfma_io_in_bits_req.typ, _sfma_io_in_bits_req_typ_T node _sfma_io_in_bits_req_fmt_T = bits(ex_reg_inst, 26, 25) connect sfma_io_in_bits_req.fmt, _sfma_io_in_bits_req_fmt_T node _sfma_io_in_bits_req_fmaCmd_T = bits(ex_reg_inst, 3, 2) node _sfma_io_in_bits_req_fmaCmd_T_1 = eq(ex_ctrl.ren3, UInt<1>(0h0)) node _sfma_io_in_bits_req_fmaCmd_T_2 = bits(ex_reg_inst, 27, 27) node _sfma_io_in_bits_req_fmaCmd_T_3 = and(_sfma_io_in_bits_req_fmaCmd_T_1, _sfma_io_in_bits_req_fmaCmd_T_2) node _sfma_io_in_bits_req_fmaCmd_T_4 = or(_sfma_io_in_bits_req_fmaCmd_T, _sfma_io_in_bits_req_fmaCmd_T_3) connect sfma_io_in_bits_req.fmaCmd, _sfma_io_in_bits_req_fmaCmd_T_4 when ex_cp_valid : connect sfma_io_in_bits_req, io.cp_req.bits when io.cp_req.bits.swap12 : connect sfma_io_in_bits_req.in1, io.cp_req.bits.in2 connect sfma_io_in_bits_req.in2, io.cp_req.bits.in1 when io.cp_req.bits.swap23 : connect sfma_io_in_bits_req.in2, io.cp_req.bits.in3 connect sfma_io_in_bits_req.in3, io.cp_req.bits.in2 connect sfma.io.in.bits.in3, sfma_io_in_bits_req.in3 connect sfma.io.in.bits.in2, sfma_io_in_bits_req.in2 connect sfma.io.in.bits.in1, sfma_io_in_bits_req.in1 connect sfma.io.in.bits.fmt, sfma_io_in_bits_req.fmt connect sfma.io.in.bits.typ, sfma_io_in_bits_req.typ connect sfma.io.in.bits.fmaCmd, sfma_io_in_bits_req.fmaCmd connect sfma.io.in.bits.rm, sfma_io_in_bits_req.rm connect sfma.io.in.bits.vec, sfma_io_in_bits_req.vec connect sfma.io.in.bits.wflags, sfma_io_in_bits_req.wflags connect sfma.io.in.bits.sqrt, sfma_io_in_bits_req.sqrt connect sfma.io.in.bits.div, sfma_io_in_bits_req.div connect sfma.io.in.bits.fma, sfma_io_in_bits_req.fma connect sfma.io.in.bits.fastpipe, sfma_io_in_bits_req.fastpipe connect sfma.io.in.bits.toint, sfma_io_in_bits_req.toint connect sfma.io.in.bits.fromint, sfma_io_in_bits_req.fromint connect sfma.io.in.bits.typeTagOut, sfma_io_in_bits_req.typeTagOut connect sfma.io.in.bits.typeTagIn, sfma_io_in_bits_req.typeTagIn connect sfma.io.in.bits.swap23, sfma_io_in_bits_req.swap23 connect sfma.io.in.bits.swap12, sfma_io_in_bits_req.swap12 connect sfma.io.in.bits.ren3, sfma_io_in_bits_req.ren3 connect sfma.io.in.bits.ren2, sfma_io_in_bits_req.ren2 connect sfma.io.in.bits.ren1, sfma_io_in_bits_req.ren1 connect sfma.io.in.bits.wen, sfma_io_in_bits_req.wen connect sfma.io.in.bits.ldst, sfma_io_in_bits_req.ldst inst fpiu of FPToInt_1 connect fpiu.clock, clock connect fpiu.reset, reset node _fpiu_io_in_valid_T = or(ex_ctrl.toint, ex_ctrl.div) node _fpiu_io_in_valid_T_1 = or(_fpiu_io_in_valid_T, ex_ctrl.sqrt) node _fpiu_io_in_valid_T_2 = and(ex_ctrl.fastpipe, ex_ctrl.wflags) node _fpiu_io_in_valid_T_3 = or(_fpiu_io_in_valid_T_1, _fpiu_io_in_valid_T_2) node _fpiu_io_in_valid_T_4 = and(req_valid, _fpiu_io_in_valid_T_3) connect fpiu.io.in.valid, _fpiu_io_in_valid_T_4 wire fpiu_io_in_bits_req : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>} connect fpiu_io_in_bits_req.vec, ex_ctrl.vec connect fpiu_io_in_bits_req.wflags, ex_ctrl.wflags connect fpiu_io_in_bits_req.sqrt, ex_ctrl.sqrt connect fpiu_io_in_bits_req.div, ex_ctrl.div connect fpiu_io_in_bits_req.fma, ex_ctrl.fma connect fpiu_io_in_bits_req.fastpipe, ex_ctrl.fastpipe connect fpiu_io_in_bits_req.toint, ex_ctrl.toint connect fpiu_io_in_bits_req.fromint, ex_ctrl.fromint connect fpiu_io_in_bits_req.typeTagOut, ex_ctrl.typeTagOut connect fpiu_io_in_bits_req.typeTagIn, ex_ctrl.typeTagIn connect fpiu_io_in_bits_req.swap23, ex_ctrl.swap23 connect fpiu_io_in_bits_req.swap12, ex_ctrl.swap12 connect fpiu_io_in_bits_req.ren3, ex_ctrl.ren3 connect fpiu_io_in_bits_req.ren2, ex_ctrl.ren2 connect fpiu_io_in_bits_req.ren1, ex_ctrl.ren1 connect fpiu_io_in_bits_req.wen, ex_ctrl.wen connect fpiu_io_in_bits_req.ldst, ex_ctrl.ldst connect fpiu_io_in_bits_req.rm, ex_rm node _fpiu_io_in_bits_req_in1_prev_unswizzled_T = bits(ex_rs_0, 31, 31) node _fpiu_io_in_bits_req_in1_prev_unswizzled_T_1 = bits(ex_rs_0, 52, 52) node _fpiu_io_in_bits_req_in1_prev_unswizzled_T_2 = bits(ex_rs_0, 30, 0) node fpiu_io_in_bits_req_in1_prev_unswizzled_hi = cat(_fpiu_io_in_bits_req_in1_prev_unswizzled_T, _fpiu_io_in_bits_req_in1_prev_unswizzled_T_1) node fpiu_io_in_bits_req_in1_prev_unswizzled = cat(fpiu_io_in_bits_req_in1_prev_unswizzled_hi, _fpiu_io_in_bits_req_in1_prev_unswizzled_T_2) node _fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled_T = bits(fpiu_io_in_bits_req_in1_prev_unswizzled, 15, 15) node _fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_1 = bits(fpiu_io_in_bits_req_in1_prev_unswizzled, 23, 23) node _fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_2 = bits(fpiu_io_in_bits_req_in1_prev_unswizzled, 14, 0) node fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled_hi = cat(_fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled_T, _fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_1) node fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled = cat(fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled_hi, _fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_2) node fpiu_io_in_bits_req_in1_prev_prev_prev_prev_sign = bits(fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled, 16, 16) node fpiu_io_in_bits_req_in1_prev_prev_prev_prev_fractIn = bits(fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled, 9, 0) node fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expIn = bits(fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled, 15, 10) node _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_fractOut_T = shl(fpiu_io_in_bits_req_in1_prev_prev_prev_prev_fractIn, 53) node fpiu_io_in_bits_req_in1_prev_prev_prev_prev_fractOut = shr(_fpiu_io_in_bits_req_in1_prev_prev_prev_prev_fractOut_T, 11) node fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode = bits(fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expIn, 5, 3) node _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T = add(fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expIn, UInt<12>(0h800)) node _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_1 = tail(_fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T, 1) node _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_2 = sub(_fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_1, UInt<6>(0h20)) node fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase = tail(_fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_2, 1) node _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T = eq(fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode, UInt<1>(0h0)) node _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_1 = geq(fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode, UInt<3>(0h6)) node _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_2 = or(_fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T, _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_1) node _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_3 = bits(fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase, 8, 0) node _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_4 = cat(fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode, _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_3) node _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_5 = bits(fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase, 11, 0) node fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut = mux(_fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_2, _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_4, _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_5) node fpiu_io_in_bits_req_in1_prev_prev_prev_prev_hi = cat(fpiu_io_in_bits_req_in1_prev_prev_prev_prev_sign, fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut) node fpiu_io_in_bits_req_in1_floats_0 = cat(fpiu_io_in_bits_req_in1_prev_prev_prev_prev_hi, fpiu_io_in_bits_req_in1_prev_prev_prev_prev_fractOut) node _fpiu_io_in_bits_req_in1_prev_prev_prev_isbox_T = bits(fpiu_io_in_bits_req_in1_prev_unswizzled, 32, 28) node fpiu_io_in_bits_req_in1_prev_prev_prev_isbox = andr(_fpiu_io_in_bits_req_in1_prev_prev_prev_isbox_T) node fpiu_io_in_bits_req_in1_prev_prev_0_1 = and(fpiu_io_in_bits_req_in1_prev_prev_prev_isbox, UInt<1>(0h1)) node fpiu_io_in_bits_req_in1_prev_prev_sign = bits(fpiu_io_in_bits_req_in1_prev_unswizzled, 32, 32) node fpiu_io_in_bits_req_in1_prev_prev_fractIn = bits(fpiu_io_in_bits_req_in1_prev_unswizzled, 22, 0) node fpiu_io_in_bits_req_in1_prev_prev_expIn = bits(fpiu_io_in_bits_req_in1_prev_unswizzled, 31, 23) node _fpiu_io_in_bits_req_in1_prev_prev_fractOut_T = shl(fpiu_io_in_bits_req_in1_prev_prev_fractIn, 53) node fpiu_io_in_bits_req_in1_prev_prev_fractOut = shr(_fpiu_io_in_bits_req_in1_prev_prev_fractOut_T, 24) node fpiu_io_in_bits_req_in1_prev_prev_expOut_expCode = bits(fpiu_io_in_bits_req_in1_prev_prev_expIn, 8, 6) node _fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T = add(fpiu_io_in_bits_req_in1_prev_prev_expIn, UInt<12>(0h800)) node _fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_1 = tail(_fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T, 1) node _fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2 = sub(_fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_1, UInt<9>(0h100)) node fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase = tail(_fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2, 1) node _fpiu_io_in_bits_req_in1_prev_prev_expOut_T = eq(fpiu_io_in_bits_req_in1_prev_prev_expOut_expCode, UInt<1>(0h0)) node _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_1 = geq(fpiu_io_in_bits_req_in1_prev_prev_expOut_expCode, UInt<3>(0h6)) node _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_2 = or(_fpiu_io_in_bits_req_in1_prev_prev_expOut_T, _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_1) node _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_3 = bits(fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase, 8, 0) node _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_4 = cat(fpiu_io_in_bits_req_in1_prev_prev_expOut_expCode, _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_3) node _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_5 = bits(fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase, 11, 0) node fpiu_io_in_bits_req_in1_prev_prev_expOut = mux(_fpiu_io_in_bits_req_in1_prev_prev_expOut_T_2, _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_4, _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_5) node fpiu_io_in_bits_req_in1_prev_prev_hi = cat(fpiu_io_in_bits_req_in1_prev_prev_sign, fpiu_io_in_bits_req_in1_prev_prev_expOut) node fpiu_io_in_bits_req_in1_floats_1 = cat(fpiu_io_in_bits_req_in1_prev_prev_hi, fpiu_io_in_bits_req_in1_prev_prev_fractOut) node _fpiu_io_in_bits_req_in1_prev_isbox_T = bits(ex_rs_0, 64, 60) node fpiu_io_in_bits_req_in1_prev_isbox = andr(_fpiu_io_in_bits_req_in1_prev_isbox_T) node fpiu_io_in_bits_req_in1_oks_0 = and(fpiu_io_in_bits_req_in1_prev_isbox, fpiu_io_in_bits_req_in1_prev_prev_0_1) node fpiu_io_in_bits_req_in1_oks_1 = and(fpiu_io_in_bits_req_in1_prev_isbox, UInt<1>(0h1)) node _fpiu_io_in_bits_req_in1_T = eq(ex_ctrl.typeTagIn, UInt<1>(0h1)) node _fpiu_io_in_bits_req_in1_T_1 = mux(_fpiu_io_in_bits_req_in1_T, fpiu_io_in_bits_req_in1_oks_1, fpiu_io_in_bits_req_in1_oks_0) node _fpiu_io_in_bits_req_in1_T_2 = eq(ex_ctrl.typeTagIn, UInt<2>(0h2)) node _fpiu_io_in_bits_req_in1_T_3 = mux(_fpiu_io_in_bits_req_in1_T_2, UInt<1>(0h1), _fpiu_io_in_bits_req_in1_T_1) node _fpiu_io_in_bits_req_in1_T_4 = eq(ex_ctrl.typeTagIn, UInt<2>(0h3)) node _fpiu_io_in_bits_req_in1_T_5 = mux(_fpiu_io_in_bits_req_in1_T_4, UInt<1>(0h1), _fpiu_io_in_bits_req_in1_T_3) node _fpiu_io_in_bits_req_in1_T_6 = eq(ex_ctrl.typeTagIn, UInt<1>(0h1)) node _fpiu_io_in_bits_req_in1_T_7 = mux(_fpiu_io_in_bits_req_in1_T_6, fpiu_io_in_bits_req_in1_floats_1, fpiu_io_in_bits_req_in1_floats_0) node _fpiu_io_in_bits_req_in1_T_8 = eq(ex_ctrl.typeTagIn, UInt<2>(0h2)) node _fpiu_io_in_bits_req_in1_T_9 = mux(_fpiu_io_in_bits_req_in1_T_8, ex_rs_0, _fpiu_io_in_bits_req_in1_T_7) node _fpiu_io_in_bits_req_in1_T_10 = eq(ex_ctrl.typeTagIn, UInt<2>(0h3)) node _fpiu_io_in_bits_req_in1_T_11 = mux(_fpiu_io_in_bits_req_in1_T_10, ex_rs_0, _fpiu_io_in_bits_req_in1_T_9) node _fpiu_io_in_bits_req_in1_T_12 = mux(_fpiu_io_in_bits_req_in1_T_5, _fpiu_io_in_bits_req_in1_T_11, UInt<65>(0he008000000000000)) connect fpiu_io_in_bits_req.in1, _fpiu_io_in_bits_req_in1_T_12 node _fpiu_io_in_bits_req_in2_prev_unswizzled_T = bits(ex_rs_1, 31, 31) node _fpiu_io_in_bits_req_in2_prev_unswizzled_T_1 = bits(ex_rs_1, 52, 52) node _fpiu_io_in_bits_req_in2_prev_unswizzled_T_2 = bits(ex_rs_1, 30, 0) node fpiu_io_in_bits_req_in2_prev_unswizzled_hi = cat(_fpiu_io_in_bits_req_in2_prev_unswizzled_T, _fpiu_io_in_bits_req_in2_prev_unswizzled_T_1) node fpiu_io_in_bits_req_in2_prev_unswizzled = cat(fpiu_io_in_bits_req_in2_prev_unswizzled_hi, _fpiu_io_in_bits_req_in2_prev_unswizzled_T_2) node _fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled_T = bits(fpiu_io_in_bits_req_in2_prev_unswizzled, 15, 15) node _fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_1 = bits(fpiu_io_in_bits_req_in2_prev_unswizzled, 23, 23) node _fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_2 = bits(fpiu_io_in_bits_req_in2_prev_unswizzled, 14, 0) node fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled_hi = cat(_fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled_T, _fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_1) node fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled = cat(fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled_hi, _fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_2) node fpiu_io_in_bits_req_in2_prev_prev_prev_prev_sign = bits(fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled, 16, 16) node fpiu_io_in_bits_req_in2_prev_prev_prev_prev_fractIn = bits(fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled, 9, 0) node fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expIn = bits(fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled, 15, 10) node _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_fractOut_T = shl(fpiu_io_in_bits_req_in2_prev_prev_prev_prev_fractIn, 53) node fpiu_io_in_bits_req_in2_prev_prev_prev_prev_fractOut = shr(_fpiu_io_in_bits_req_in2_prev_prev_prev_prev_fractOut_T, 11) node fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode = bits(fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expIn, 5, 3) node _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T = add(fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expIn, UInt<12>(0h800)) node _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_1 = tail(_fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T, 1) node _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_2 = sub(_fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_1, UInt<6>(0h20)) node fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase = tail(_fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_2, 1) node _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T = eq(fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode, UInt<1>(0h0)) node _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_1 = geq(fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode, UInt<3>(0h6)) node _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_2 = or(_fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T, _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_1) node _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_3 = bits(fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase, 8, 0) node _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_4 = cat(fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode, _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_3) node _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_5 = bits(fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase, 11, 0) node fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut = mux(_fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_2, _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_4, _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_5) node fpiu_io_in_bits_req_in2_prev_prev_prev_prev_hi = cat(fpiu_io_in_bits_req_in2_prev_prev_prev_prev_sign, fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut) node fpiu_io_in_bits_req_in2_floats_0 = cat(fpiu_io_in_bits_req_in2_prev_prev_prev_prev_hi, fpiu_io_in_bits_req_in2_prev_prev_prev_prev_fractOut) node _fpiu_io_in_bits_req_in2_prev_prev_prev_isbox_T = bits(fpiu_io_in_bits_req_in2_prev_unswizzled, 32, 28) node fpiu_io_in_bits_req_in2_prev_prev_prev_isbox = andr(_fpiu_io_in_bits_req_in2_prev_prev_prev_isbox_T) node fpiu_io_in_bits_req_in2_prev_prev_0_1 = and(fpiu_io_in_bits_req_in2_prev_prev_prev_isbox, UInt<1>(0h1)) node fpiu_io_in_bits_req_in2_prev_prev_sign = bits(fpiu_io_in_bits_req_in2_prev_unswizzled, 32, 32) node fpiu_io_in_bits_req_in2_prev_prev_fractIn = bits(fpiu_io_in_bits_req_in2_prev_unswizzled, 22, 0) node fpiu_io_in_bits_req_in2_prev_prev_expIn = bits(fpiu_io_in_bits_req_in2_prev_unswizzled, 31, 23) node _fpiu_io_in_bits_req_in2_prev_prev_fractOut_T = shl(fpiu_io_in_bits_req_in2_prev_prev_fractIn, 53) node fpiu_io_in_bits_req_in2_prev_prev_fractOut = shr(_fpiu_io_in_bits_req_in2_prev_prev_fractOut_T, 24) node fpiu_io_in_bits_req_in2_prev_prev_expOut_expCode = bits(fpiu_io_in_bits_req_in2_prev_prev_expIn, 8, 6) node _fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T = add(fpiu_io_in_bits_req_in2_prev_prev_expIn, UInt<12>(0h800)) node _fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_1 = tail(_fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T, 1) node _fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2 = sub(_fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_1, UInt<9>(0h100)) node fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase = tail(_fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2, 1) node _fpiu_io_in_bits_req_in2_prev_prev_expOut_T = eq(fpiu_io_in_bits_req_in2_prev_prev_expOut_expCode, UInt<1>(0h0)) node _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_1 = geq(fpiu_io_in_bits_req_in2_prev_prev_expOut_expCode, UInt<3>(0h6)) node _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_2 = or(_fpiu_io_in_bits_req_in2_prev_prev_expOut_T, _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_1) node _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_3 = bits(fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase, 8, 0) node _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_4 = cat(fpiu_io_in_bits_req_in2_prev_prev_expOut_expCode, _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_3) node _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_5 = bits(fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase, 11, 0) node fpiu_io_in_bits_req_in2_prev_prev_expOut = mux(_fpiu_io_in_bits_req_in2_prev_prev_expOut_T_2, _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_4, _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_5) node fpiu_io_in_bits_req_in2_prev_prev_hi = cat(fpiu_io_in_bits_req_in2_prev_prev_sign, fpiu_io_in_bits_req_in2_prev_prev_expOut) node fpiu_io_in_bits_req_in2_floats_1 = cat(fpiu_io_in_bits_req_in2_prev_prev_hi, fpiu_io_in_bits_req_in2_prev_prev_fractOut) node _fpiu_io_in_bits_req_in2_prev_isbox_T = bits(ex_rs_1, 64, 60) node fpiu_io_in_bits_req_in2_prev_isbox = andr(_fpiu_io_in_bits_req_in2_prev_isbox_T) node fpiu_io_in_bits_req_in2_oks_0 = and(fpiu_io_in_bits_req_in2_prev_isbox, fpiu_io_in_bits_req_in2_prev_prev_0_1) node fpiu_io_in_bits_req_in2_oks_1 = and(fpiu_io_in_bits_req_in2_prev_isbox, UInt<1>(0h1)) node _fpiu_io_in_bits_req_in2_T = eq(ex_ctrl.typeTagIn, UInt<1>(0h1)) node _fpiu_io_in_bits_req_in2_T_1 = mux(_fpiu_io_in_bits_req_in2_T, fpiu_io_in_bits_req_in2_oks_1, fpiu_io_in_bits_req_in2_oks_0) node _fpiu_io_in_bits_req_in2_T_2 = eq(ex_ctrl.typeTagIn, UInt<2>(0h2)) node _fpiu_io_in_bits_req_in2_T_3 = mux(_fpiu_io_in_bits_req_in2_T_2, UInt<1>(0h1), _fpiu_io_in_bits_req_in2_T_1) node _fpiu_io_in_bits_req_in2_T_4 = eq(ex_ctrl.typeTagIn, UInt<2>(0h3)) node _fpiu_io_in_bits_req_in2_T_5 = mux(_fpiu_io_in_bits_req_in2_T_4, UInt<1>(0h1), _fpiu_io_in_bits_req_in2_T_3) node _fpiu_io_in_bits_req_in2_T_6 = eq(ex_ctrl.typeTagIn, UInt<1>(0h1)) node _fpiu_io_in_bits_req_in2_T_7 = mux(_fpiu_io_in_bits_req_in2_T_6, fpiu_io_in_bits_req_in2_floats_1, fpiu_io_in_bits_req_in2_floats_0) node _fpiu_io_in_bits_req_in2_T_8 = eq(ex_ctrl.typeTagIn, UInt<2>(0h2)) node _fpiu_io_in_bits_req_in2_T_9 = mux(_fpiu_io_in_bits_req_in2_T_8, ex_rs_1, _fpiu_io_in_bits_req_in2_T_7) node _fpiu_io_in_bits_req_in2_T_10 = eq(ex_ctrl.typeTagIn, UInt<2>(0h3)) node _fpiu_io_in_bits_req_in2_T_11 = mux(_fpiu_io_in_bits_req_in2_T_10, ex_rs_1, _fpiu_io_in_bits_req_in2_T_9) node _fpiu_io_in_bits_req_in2_T_12 = mux(_fpiu_io_in_bits_req_in2_T_5, _fpiu_io_in_bits_req_in2_T_11, UInt<65>(0he008000000000000)) connect fpiu_io_in_bits_req.in2, _fpiu_io_in_bits_req_in2_T_12 node _fpiu_io_in_bits_req_in3_prev_unswizzled_T = bits(ex_rs_2, 31, 31) node _fpiu_io_in_bits_req_in3_prev_unswizzled_T_1 = bits(ex_rs_2, 52, 52) node _fpiu_io_in_bits_req_in3_prev_unswizzled_T_2 = bits(ex_rs_2, 30, 0) node fpiu_io_in_bits_req_in3_prev_unswizzled_hi = cat(_fpiu_io_in_bits_req_in3_prev_unswizzled_T, _fpiu_io_in_bits_req_in3_prev_unswizzled_T_1) node fpiu_io_in_bits_req_in3_prev_unswizzled = cat(fpiu_io_in_bits_req_in3_prev_unswizzled_hi, _fpiu_io_in_bits_req_in3_prev_unswizzled_T_2) node _fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled_T = bits(fpiu_io_in_bits_req_in3_prev_unswizzled, 15, 15) node _fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_1 = bits(fpiu_io_in_bits_req_in3_prev_unswizzled, 23, 23) node _fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_2 = bits(fpiu_io_in_bits_req_in3_prev_unswizzled, 14, 0) node fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled_hi = cat(_fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled_T, _fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_1) node fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled = cat(fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled_hi, _fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_2) node fpiu_io_in_bits_req_in3_prev_prev_prev_prev_sign = bits(fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled, 16, 16) node fpiu_io_in_bits_req_in3_prev_prev_prev_prev_fractIn = bits(fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled, 9, 0) node fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expIn = bits(fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled, 15, 10) node _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_fractOut_T = shl(fpiu_io_in_bits_req_in3_prev_prev_prev_prev_fractIn, 53) node fpiu_io_in_bits_req_in3_prev_prev_prev_prev_fractOut = shr(_fpiu_io_in_bits_req_in3_prev_prev_prev_prev_fractOut_T, 11) node fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode = bits(fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expIn, 5, 3) node _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T = add(fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expIn, UInt<12>(0h800)) node _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_1 = tail(_fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T, 1) node _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_2 = sub(_fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_1, UInt<6>(0h20)) node fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase = tail(_fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_2, 1) node _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T = eq(fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode, UInt<1>(0h0)) node _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_1 = geq(fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode, UInt<3>(0h6)) node _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_2 = or(_fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T, _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_1) node _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_3 = bits(fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase, 8, 0) node _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_4 = cat(fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode, _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_3) node _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_5 = bits(fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase, 11, 0) node fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut = mux(_fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_2, _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_4, _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_5) node fpiu_io_in_bits_req_in3_prev_prev_prev_prev_hi = cat(fpiu_io_in_bits_req_in3_prev_prev_prev_prev_sign, fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut) node fpiu_io_in_bits_req_in3_floats_0 = cat(fpiu_io_in_bits_req_in3_prev_prev_prev_prev_hi, fpiu_io_in_bits_req_in3_prev_prev_prev_prev_fractOut) node _fpiu_io_in_bits_req_in3_prev_prev_prev_isbox_T = bits(fpiu_io_in_bits_req_in3_prev_unswizzled, 32, 28) node fpiu_io_in_bits_req_in3_prev_prev_prev_isbox = andr(_fpiu_io_in_bits_req_in3_prev_prev_prev_isbox_T) node fpiu_io_in_bits_req_in3_prev_prev_0_1 = and(fpiu_io_in_bits_req_in3_prev_prev_prev_isbox, UInt<1>(0h1)) node fpiu_io_in_bits_req_in3_prev_prev_sign = bits(fpiu_io_in_bits_req_in3_prev_unswizzled, 32, 32) node fpiu_io_in_bits_req_in3_prev_prev_fractIn = bits(fpiu_io_in_bits_req_in3_prev_unswizzled, 22, 0) node fpiu_io_in_bits_req_in3_prev_prev_expIn = bits(fpiu_io_in_bits_req_in3_prev_unswizzled, 31, 23) node _fpiu_io_in_bits_req_in3_prev_prev_fractOut_T = shl(fpiu_io_in_bits_req_in3_prev_prev_fractIn, 53) node fpiu_io_in_bits_req_in3_prev_prev_fractOut = shr(_fpiu_io_in_bits_req_in3_prev_prev_fractOut_T, 24) node fpiu_io_in_bits_req_in3_prev_prev_expOut_expCode = bits(fpiu_io_in_bits_req_in3_prev_prev_expIn, 8, 6) node _fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T = add(fpiu_io_in_bits_req_in3_prev_prev_expIn, UInt<12>(0h800)) node _fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_1 = tail(_fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T, 1) node _fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_2 = sub(_fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_1, UInt<9>(0h100)) node fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase = tail(_fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_2, 1) node _fpiu_io_in_bits_req_in3_prev_prev_expOut_T = eq(fpiu_io_in_bits_req_in3_prev_prev_expOut_expCode, UInt<1>(0h0)) node _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_1 = geq(fpiu_io_in_bits_req_in3_prev_prev_expOut_expCode, UInt<3>(0h6)) node _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_2 = or(_fpiu_io_in_bits_req_in3_prev_prev_expOut_T, _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_1) node _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_3 = bits(fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase, 8, 0) node _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_4 = cat(fpiu_io_in_bits_req_in3_prev_prev_expOut_expCode, _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_3) node _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_5 = bits(fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase, 11, 0) node fpiu_io_in_bits_req_in3_prev_prev_expOut = mux(_fpiu_io_in_bits_req_in3_prev_prev_expOut_T_2, _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_4, _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_5) node fpiu_io_in_bits_req_in3_prev_prev_hi = cat(fpiu_io_in_bits_req_in3_prev_prev_sign, fpiu_io_in_bits_req_in3_prev_prev_expOut) node fpiu_io_in_bits_req_in3_floats_1 = cat(fpiu_io_in_bits_req_in3_prev_prev_hi, fpiu_io_in_bits_req_in3_prev_prev_fractOut) node _fpiu_io_in_bits_req_in3_prev_isbox_T = bits(ex_rs_2, 64, 60) node fpiu_io_in_bits_req_in3_prev_isbox = andr(_fpiu_io_in_bits_req_in3_prev_isbox_T) node fpiu_io_in_bits_req_in3_oks_0 = and(fpiu_io_in_bits_req_in3_prev_isbox, fpiu_io_in_bits_req_in3_prev_prev_0_1) node fpiu_io_in_bits_req_in3_oks_1 = and(fpiu_io_in_bits_req_in3_prev_isbox, UInt<1>(0h1)) node _fpiu_io_in_bits_req_in3_T = eq(ex_ctrl.typeTagIn, UInt<1>(0h1)) node _fpiu_io_in_bits_req_in3_T_1 = mux(_fpiu_io_in_bits_req_in3_T, fpiu_io_in_bits_req_in3_oks_1, fpiu_io_in_bits_req_in3_oks_0) node _fpiu_io_in_bits_req_in3_T_2 = eq(ex_ctrl.typeTagIn, UInt<2>(0h2)) node _fpiu_io_in_bits_req_in3_T_3 = mux(_fpiu_io_in_bits_req_in3_T_2, UInt<1>(0h1), _fpiu_io_in_bits_req_in3_T_1) node _fpiu_io_in_bits_req_in3_T_4 = eq(ex_ctrl.typeTagIn, UInt<2>(0h3)) node _fpiu_io_in_bits_req_in3_T_5 = mux(_fpiu_io_in_bits_req_in3_T_4, UInt<1>(0h1), _fpiu_io_in_bits_req_in3_T_3) node _fpiu_io_in_bits_req_in3_T_6 = eq(ex_ctrl.typeTagIn, UInt<1>(0h1)) node _fpiu_io_in_bits_req_in3_T_7 = mux(_fpiu_io_in_bits_req_in3_T_6, fpiu_io_in_bits_req_in3_floats_1, fpiu_io_in_bits_req_in3_floats_0) node _fpiu_io_in_bits_req_in3_T_8 = eq(ex_ctrl.typeTagIn, UInt<2>(0h2)) node _fpiu_io_in_bits_req_in3_T_9 = mux(_fpiu_io_in_bits_req_in3_T_8, ex_rs_2, _fpiu_io_in_bits_req_in3_T_7) node _fpiu_io_in_bits_req_in3_T_10 = eq(ex_ctrl.typeTagIn, UInt<2>(0h3)) node _fpiu_io_in_bits_req_in3_T_11 = mux(_fpiu_io_in_bits_req_in3_T_10, ex_rs_2, _fpiu_io_in_bits_req_in3_T_9) node _fpiu_io_in_bits_req_in3_T_12 = mux(_fpiu_io_in_bits_req_in3_T_5, _fpiu_io_in_bits_req_in3_T_11, UInt<65>(0he008000000000000)) connect fpiu_io_in_bits_req.in3, _fpiu_io_in_bits_req_in3_T_12 node _fpiu_io_in_bits_req_typ_T = bits(ex_reg_inst, 21, 20) connect fpiu_io_in_bits_req.typ, _fpiu_io_in_bits_req_typ_T node _fpiu_io_in_bits_req_fmt_T = bits(ex_reg_inst, 26, 25) connect fpiu_io_in_bits_req.fmt, _fpiu_io_in_bits_req_fmt_T node _fpiu_io_in_bits_req_fmaCmd_T = bits(ex_reg_inst, 3, 2) node _fpiu_io_in_bits_req_fmaCmd_T_1 = eq(ex_ctrl.ren3, UInt<1>(0h0)) node _fpiu_io_in_bits_req_fmaCmd_T_2 = bits(ex_reg_inst, 27, 27) node _fpiu_io_in_bits_req_fmaCmd_T_3 = and(_fpiu_io_in_bits_req_fmaCmd_T_1, _fpiu_io_in_bits_req_fmaCmd_T_2) node _fpiu_io_in_bits_req_fmaCmd_T_4 = or(_fpiu_io_in_bits_req_fmaCmd_T, _fpiu_io_in_bits_req_fmaCmd_T_3) connect fpiu_io_in_bits_req.fmaCmd, _fpiu_io_in_bits_req_fmaCmd_T_4 when ex_cp_valid : connect fpiu_io_in_bits_req, io.cp_req.bits when io.cp_req.bits.swap12 : connect fpiu_io_in_bits_req.in1, io.cp_req.bits.in2 connect fpiu_io_in_bits_req.in2, io.cp_req.bits.in1 when io.cp_req.bits.swap23 : connect fpiu_io_in_bits_req.in2, io.cp_req.bits.in3 connect fpiu_io_in_bits_req.in3, io.cp_req.bits.in2 connect fpiu.io.in.bits.in3, fpiu_io_in_bits_req.in3 connect fpiu.io.in.bits.in2, fpiu_io_in_bits_req.in2 connect fpiu.io.in.bits.in1, fpiu_io_in_bits_req.in1 connect fpiu.io.in.bits.fmt, fpiu_io_in_bits_req.fmt connect fpiu.io.in.bits.typ, fpiu_io_in_bits_req.typ connect fpiu.io.in.bits.fmaCmd, fpiu_io_in_bits_req.fmaCmd connect fpiu.io.in.bits.rm, fpiu_io_in_bits_req.rm connect fpiu.io.in.bits.vec, fpiu_io_in_bits_req.vec connect fpiu.io.in.bits.wflags, fpiu_io_in_bits_req.wflags connect fpiu.io.in.bits.sqrt, fpiu_io_in_bits_req.sqrt connect fpiu.io.in.bits.div, fpiu_io_in_bits_req.div connect fpiu.io.in.bits.fma, fpiu_io_in_bits_req.fma connect fpiu.io.in.bits.fastpipe, fpiu_io_in_bits_req.fastpipe connect fpiu.io.in.bits.toint, fpiu_io_in_bits_req.toint connect fpiu.io.in.bits.fromint, fpiu_io_in_bits_req.fromint connect fpiu.io.in.bits.typeTagOut, fpiu_io_in_bits_req.typeTagOut connect fpiu.io.in.bits.typeTagIn, fpiu_io_in_bits_req.typeTagIn connect fpiu.io.in.bits.swap23, fpiu_io_in_bits_req.swap23 connect fpiu.io.in.bits.swap12, fpiu_io_in_bits_req.swap12 connect fpiu.io.in.bits.ren3, fpiu_io_in_bits_req.ren3 connect fpiu.io.in.bits.ren2, fpiu_io_in_bits_req.ren2 connect fpiu.io.in.bits.ren1, fpiu_io_in_bits_req.ren1 connect fpiu.io.in.bits.wen, fpiu_io_in_bits_req.wen connect fpiu.io.in.bits.ldst, fpiu_io_in_bits_req.ldst connect io.store_data, fpiu.io.out.bits.store connect io.toint_data, fpiu.io.out.bits.toint node _T_8 = and(fpiu.io.out.valid, mem_cp_valid) node _T_9 = and(_T_8, mem_ctrl.toint) when _T_9 : connect io.cp_resp.bits.data, fpiu.io.out.bits.toint connect io.cp_resp.valid, UInt<1>(0h1) inst ifpu of IntToFP_1 connect ifpu.clock, clock connect ifpu.reset, reset node _ifpu_io_in_valid_T = and(req_valid, ex_ctrl.fromint) connect ifpu.io.in.valid, _ifpu_io_in_valid_T connect ifpu.io.in.bits.in1, fpiu.io.in.bits.in1 connect ifpu.io.in.bits.typ, fpiu.io.in.bits.typ connect ifpu.io.in.bits.rm, fpiu.io.in.bits.rm connect ifpu.io.in.bits.vec, fpiu.io.in.bits.vec connect ifpu.io.in.bits.wflags, fpiu.io.in.bits.wflags connect ifpu.io.in.bits.sqrt, fpiu.io.in.bits.sqrt connect ifpu.io.in.bits.div, fpiu.io.in.bits.div connect ifpu.io.in.bits.fma, fpiu.io.in.bits.fma connect ifpu.io.in.bits.fastpipe, fpiu.io.in.bits.fastpipe connect ifpu.io.in.bits.toint, fpiu.io.in.bits.toint connect ifpu.io.in.bits.fromint, fpiu.io.in.bits.fromint connect ifpu.io.in.bits.typeTagOut, fpiu.io.in.bits.typeTagOut connect ifpu.io.in.bits.typeTagIn, fpiu.io.in.bits.typeTagIn connect ifpu.io.in.bits.swap23, fpiu.io.in.bits.swap23 connect ifpu.io.in.bits.swap12, fpiu.io.in.bits.swap12 connect ifpu.io.in.bits.ren3, fpiu.io.in.bits.ren3 connect ifpu.io.in.bits.ren2, fpiu.io.in.bits.ren2 connect ifpu.io.in.bits.ren1, fpiu.io.in.bits.ren1 connect ifpu.io.in.bits.wen, fpiu.io.in.bits.wen connect ifpu.io.in.bits.ldst, fpiu.io.in.bits.ldst node _ifpu_io_in_bits_in1_T = mux(ex_cp_valid, io.cp_req.bits.in1, io.fromint_data) connect ifpu.io.in.bits.in1, _ifpu_io_in_bits_in1_T inst fpmu of FPToFP_1 connect fpmu.clock, clock connect fpmu.reset, reset node _fpmu_io_in_valid_T = and(req_valid, ex_ctrl.fastpipe) connect fpmu.io.in.valid, _fpmu_io_in_valid_T connect fpmu.io.in.bits.in3, fpiu.io.in.bits.in3 connect fpmu.io.in.bits.in2, fpiu.io.in.bits.in2 connect fpmu.io.in.bits.in1, fpiu.io.in.bits.in1 connect fpmu.io.in.bits.fmt, fpiu.io.in.bits.fmt connect fpmu.io.in.bits.typ, fpiu.io.in.bits.typ connect fpmu.io.in.bits.fmaCmd, fpiu.io.in.bits.fmaCmd connect fpmu.io.in.bits.rm, fpiu.io.in.bits.rm connect fpmu.io.in.bits.vec, fpiu.io.in.bits.vec connect fpmu.io.in.bits.wflags, fpiu.io.in.bits.wflags connect fpmu.io.in.bits.sqrt, fpiu.io.in.bits.sqrt connect fpmu.io.in.bits.div, fpiu.io.in.bits.div connect fpmu.io.in.bits.fma, fpiu.io.in.bits.fma connect fpmu.io.in.bits.fastpipe, fpiu.io.in.bits.fastpipe connect fpmu.io.in.bits.toint, fpiu.io.in.bits.toint connect fpmu.io.in.bits.fromint, fpiu.io.in.bits.fromint connect fpmu.io.in.bits.typeTagOut, fpiu.io.in.bits.typeTagOut connect fpmu.io.in.bits.typeTagIn, fpiu.io.in.bits.typeTagIn connect fpmu.io.in.bits.swap23, fpiu.io.in.bits.swap23 connect fpmu.io.in.bits.swap12, fpiu.io.in.bits.swap12 connect fpmu.io.in.bits.ren3, fpiu.io.in.bits.ren3 connect fpmu.io.in.bits.ren2, fpiu.io.in.bits.ren2 connect fpmu.io.in.bits.ren1, fpiu.io.in.bits.ren1 connect fpmu.io.in.bits.wen, fpiu.io.in.bits.wen connect fpmu.io.in.bits.ldst, fpiu.io.in.bits.ldst connect fpmu.io.lt, fpiu.io.out.bits.lt wire divSqrt_wen : UInt<1> connect divSqrt_wen, UInt<1>(0h0) wire divSqrt_inFlight : UInt<1> connect divSqrt_inFlight, UInt<1>(0h0) reg divSqrt_waddr : UInt<5>, clock reg divSqrt_cp : UInt<1>, clock wire divSqrt_typeTag : UInt<2> wire divSqrt_wdata : UInt<65> wire divSqrt_flags : UInt<5> invalidate divSqrt_typeTag invalidate divSqrt_wdata invalidate divSqrt_flags inst dfma of FPUFMAPipe_l4_f64_1 connect dfma.clock, clock connect dfma.reset, reset node _dfma_io_in_valid_T = and(req_valid, ex_ctrl.fma) node _dfma_io_in_valid_T_1 = eq(ex_ctrl.typeTagOut, UInt<2>(0h2)) node _dfma_io_in_valid_T_2 = and(_dfma_io_in_valid_T, _dfma_io_in_valid_T_1) connect dfma.io.in.valid, _dfma_io_in_valid_T_2 wire dfma_io_in_bits_req : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>} connect dfma_io_in_bits_req.vec, ex_ctrl.vec connect dfma_io_in_bits_req.wflags, ex_ctrl.wflags connect dfma_io_in_bits_req.sqrt, ex_ctrl.sqrt connect dfma_io_in_bits_req.div, ex_ctrl.div connect dfma_io_in_bits_req.fma, ex_ctrl.fma connect dfma_io_in_bits_req.fastpipe, ex_ctrl.fastpipe connect dfma_io_in_bits_req.toint, ex_ctrl.toint connect dfma_io_in_bits_req.fromint, ex_ctrl.fromint connect dfma_io_in_bits_req.typeTagOut, ex_ctrl.typeTagOut connect dfma_io_in_bits_req.typeTagIn, ex_ctrl.typeTagIn connect dfma_io_in_bits_req.swap23, ex_ctrl.swap23 connect dfma_io_in_bits_req.swap12, ex_ctrl.swap12 connect dfma_io_in_bits_req.ren3, ex_ctrl.ren3 connect dfma_io_in_bits_req.ren2, ex_ctrl.ren2 connect dfma_io_in_bits_req.ren1, ex_ctrl.ren1 connect dfma_io_in_bits_req.wen, ex_ctrl.wen connect dfma_io_in_bits_req.ldst, ex_ctrl.ldst connect dfma_io_in_bits_req.rm, ex_rm node _dfma_io_in_bits_req_in1_prev_unswizzled_T = bits(ex_rs_0, 31, 31) node _dfma_io_in_bits_req_in1_prev_unswizzled_T_1 = bits(ex_rs_0, 52, 52) node _dfma_io_in_bits_req_in1_prev_unswizzled_T_2 = bits(ex_rs_0, 30, 0) node dfma_io_in_bits_req_in1_prev_unswizzled_hi = cat(_dfma_io_in_bits_req_in1_prev_unswizzled_T, _dfma_io_in_bits_req_in1_prev_unswizzled_T_1) node dfma_io_in_bits_req_in1_prev_unswizzled = cat(dfma_io_in_bits_req_in1_prev_unswizzled_hi, _dfma_io_in_bits_req_in1_prev_unswizzled_T_2) node _dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T = bits(dfma_io_in_bits_req_in1_prev_unswizzled, 15, 15) node _dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_1 = bits(dfma_io_in_bits_req_in1_prev_unswizzled, 23, 23) node _dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_2 = bits(dfma_io_in_bits_req_in1_prev_unswizzled, 14, 0) node dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_hi = cat(_dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T, _dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_1) node dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled = cat(dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_hi, _dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_2) node dfma_io_in_bits_req_in1_prev_prev_prev_prev_sign = bits(dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled, 16, 16) node dfma_io_in_bits_req_in1_prev_prev_prev_prev_fractIn = bits(dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled, 9, 0) node dfma_io_in_bits_req_in1_prev_prev_prev_prev_expIn = bits(dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled, 15, 10) node _dfma_io_in_bits_req_in1_prev_prev_prev_prev_fractOut_T = shl(dfma_io_in_bits_req_in1_prev_prev_prev_prev_fractIn, 53) node dfma_io_in_bits_req_in1_prev_prev_prev_prev_fractOut = shr(_dfma_io_in_bits_req_in1_prev_prev_prev_prev_fractOut_T, 11) node dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode = bits(dfma_io_in_bits_req_in1_prev_prev_prev_prev_expIn, 5, 3) node _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T = add(dfma_io_in_bits_req_in1_prev_prev_prev_prev_expIn, UInt<12>(0h800)) node _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_1 = tail(_dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T, 1) node _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_2 = sub(_dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_1, UInt<6>(0h20)) node dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase = tail(_dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_2, 1) node _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T = eq(dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode, UInt<1>(0h0)) node _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_1 = geq(dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode, UInt<3>(0h6)) node _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_2 = or(_dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T, _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_1) node _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_3 = bits(dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase, 8, 0) node _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_4 = cat(dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode, _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_3) node _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_5 = bits(dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase, 11, 0) node dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut = mux(_dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_2, _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_4, _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_5) node dfma_io_in_bits_req_in1_prev_prev_prev_prev_hi = cat(dfma_io_in_bits_req_in1_prev_prev_prev_prev_sign, dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut) node dfma_io_in_bits_req_in1_floats_0 = cat(dfma_io_in_bits_req_in1_prev_prev_prev_prev_hi, dfma_io_in_bits_req_in1_prev_prev_prev_prev_fractOut) node _dfma_io_in_bits_req_in1_prev_prev_prev_isbox_T = bits(dfma_io_in_bits_req_in1_prev_unswizzled, 32, 28) node dfma_io_in_bits_req_in1_prev_prev_prev_isbox = andr(_dfma_io_in_bits_req_in1_prev_prev_prev_isbox_T) node dfma_io_in_bits_req_in1_prev_prev_0_1 = and(dfma_io_in_bits_req_in1_prev_prev_prev_isbox, UInt<1>(0h1)) node dfma_io_in_bits_req_in1_prev_prev_sign = bits(dfma_io_in_bits_req_in1_prev_unswizzled, 32, 32) node dfma_io_in_bits_req_in1_prev_prev_fractIn = bits(dfma_io_in_bits_req_in1_prev_unswizzled, 22, 0) node dfma_io_in_bits_req_in1_prev_prev_expIn = bits(dfma_io_in_bits_req_in1_prev_unswizzled, 31, 23) node _dfma_io_in_bits_req_in1_prev_prev_fractOut_T = shl(dfma_io_in_bits_req_in1_prev_prev_fractIn, 53) node dfma_io_in_bits_req_in1_prev_prev_fractOut = shr(_dfma_io_in_bits_req_in1_prev_prev_fractOut_T, 24) node dfma_io_in_bits_req_in1_prev_prev_expOut_expCode = bits(dfma_io_in_bits_req_in1_prev_prev_expIn, 8, 6) node _dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T = add(dfma_io_in_bits_req_in1_prev_prev_expIn, UInt<12>(0h800)) node _dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_1 = tail(_dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T, 1) node _dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2 = sub(_dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_1, UInt<9>(0h100)) node dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase = tail(_dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2, 1) node _dfma_io_in_bits_req_in1_prev_prev_expOut_T = eq(dfma_io_in_bits_req_in1_prev_prev_expOut_expCode, UInt<1>(0h0)) node _dfma_io_in_bits_req_in1_prev_prev_expOut_T_1 = geq(dfma_io_in_bits_req_in1_prev_prev_expOut_expCode, UInt<3>(0h6)) node _dfma_io_in_bits_req_in1_prev_prev_expOut_T_2 = or(_dfma_io_in_bits_req_in1_prev_prev_expOut_T, _dfma_io_in_bits_req_in1_prev_prev_expOut_T_1) node _dfma_io_in_bits_req_in1_prev_prev_expOut_T_3 = bits(dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase, 8, 0) node _dfma_io_in_bits_req_in1_prev_prev_expOut_T_4 = cat(dfma_io_in_bits_req_in1_prev_prev_expOut_expCode, _dfma_io_in_bits_req_in1_prev_prev_expOut_T_3) node _dfma_io_in_bits_req_in1_prev_prev_expOut_T_5 = bits(dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase, 11, 0) node dfma_io_in_bits_req_in1_prev_prev_expOut = mux(_dfma_io_in_bits_req_in1_prev_prev_expOut_T_2, _dfma_io_in_bits_req_in1_prev_prev_expOut_T_4, _dfma_io_in_bits_req_in1_prev_prev_expOut_T_5) node dfma_io_in_bits_req_in1_prev_prev_hi = cat(dfma_io_in_bits_req_in1_prev_prev_sign, dfma_io_in_bits_req_in1_prev_prev_expOut) node dfma_io_in_bits_req_in1_floats_1 = cat(dfma_io_in_bits_req_in1_prev_prev_hi, dfma_io_in_bits_req_in1_prev_prev_fractOut) node _dfma_io_in_bits_req_in1_prev_isbox_T = bits(ex_rs_0, 64, 60) node dfma_io_in_bits_req_in1_prev_isbox = andr(_dfma_io_in_bits_req_in1_prev_isbox_T) node dfma_io_in_bits_req_in1_oks_0 = and(dfma_io_in_bits_req_in1_prev_isbox, dfma_io_in_bits_req_in1_prev_prev_0_1) node dfma_io_in_bits_req_in1_oks_1 = and(dfma_io_in_bits_req_in1_prev_isbox, UInt<1>(0h1)) node _dfma_io_in_bits_req_in1_T = mux(UInt<1>(0h1), UInt<1>(0h0), UInt<65>(0he008000000000000)) node _dfma_io_in_bits_req_in1_T_1 = or(ex_rs_0, _dfma_io_in_bits_req_in1_T) connect dfma_io_in_bits_req.in1, _dfma_io_in_bits_req_in1_T_1 node _dfma_io_in_bits_req_in2_prev_unswizzled_T = bits(ex_rs_1, 31, 31) node _dfma_io_in_bits_req_in2_prev_unswizzled_T_1 = bits(ex_rs_1, 52, 52) node _dfma_io_in_bits_req_in2_prev_unswizzled_T_2 = bits(ex_rs_1, 30, 0) node dfma_io_in_bits_req_in2_prev_unswizzled_hi = cat(_dfma_io_in_bits_req_in2_prev_unswizzled_T, _dfma_io_in_bits_req_in2_prev_unswizzled_T_1) node dfma_io_in_bits_req_in2_prev_unswizzled = cat(dfma_io_in_bits_req_in2_prev_unswizzled_hi, _dfma_io_in_bits_req_in2_prev_unswizzled_T_2) node _dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T = bits(dfma_io_in_bits_req_in2_prev_unswizzled, 15, 15) node _dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_1 = bits(dfma_io_in_bits_req_in2_prev_unswizzled, 23, 23) node _dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_2 = bits(dfma_io_in_bits_req_in2_prev_unswizzled, 14, 0) node dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_hi = cat(_dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T, _dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_1) node dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled = cat(dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_hi, _dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_2) node dfma_io_in_bits_req_in2_prev_prev_prev_prev_sign = bits(dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled, 16, 16) node dfma_io_in_bits_req_in2_prev_prev_prev_prev_fractIn = bits(dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled, 9, 0) node dfma_io_in_bits_req_in2_prev_prev_prev_prev_expIn = bits(dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled, 15, 10) node _dfma_io_in_bits_req_in2_prev_prev_prev_prev_fractOut_T = shl(dfma_io_in_bits_req_in2_prev_prev_prev_prev_fractIn, 53) node dfma_io_in_bits_req_in2_prev_prev_prev_prev_fractOut = shr(_dfma_io_in_bits_req_in2_prev_prev_prev_prev_fractOut_T, 11) node dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode = bits(dfma_io_in_bits_req_in2_prev_prev_prev_prev_expIn, 5, 3) node _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T = add(dfma_io_in_bits_req_in2_prev_prev_prev_prev_expIn, UInt<12>(0h800)) node _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_1 = tail(_dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T, 1) node _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_2 = sub(_dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_1, UInt<6>(0h20)) node dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase = tail(_dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_2, 1) node _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T = eq(dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode, UInt<1>(0h0)) node _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_1 = geq(dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode, UInt<3>(0h6)) node _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_2 = or(_dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T, _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_1) node _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_3 = bits(dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase, 8, 0) node _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_4 = cat(dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode, _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_3) node _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_5 = bits(dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase, 11, 0) node dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut = mux(_dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_2, _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_4, _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_5) node dfma_io_in_bits_req_in2_prev_prev_prev_prev_hi = cat(dfma_io_in_bits_req_in2_prev_prev_prev_prev_sign, dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut) node dfma_io_in_bits_req_in2_floats_0 = cat(dfma_io_in_bits_req_in2_prev_prev_prev_prev_hi, dfma_io_in_bits_req_in2_prev_prev_prev_prev_fractOut) node _dfma_io_in_bits_req_in2_prev_prev_prev_isbox_T = bits(dfma_io_in_bits_req_in2_prev_unswizzled, 32, 28) node dfma_io_in_bits_req_in2_prev_prev_prev_isbox = andr(_dfma_io_in_bits_req_in2_prev_prev_prev_isbox_T) node dfma_io_in_bits_req_in2_prev_prev_0_1 = and(dfma_io_in_bits_req_in2_prev_prev_prev_isbox, UInt<1>(0h1)) node dfma_io_in_bits_req_in2_prev_prev_sign = bits(dfma_io_in_bits_req_in2_prev_unswizzled, 32, 32) node dfma_io_in_bits_req_in2_prev_prev_fractIn = bits(dfma_io_in_bits_req_in2_prev_unswizzled, 22, 0) node dfma_io_in_bits_req_in2_prev_prev_expIn = bits(dfma_io_in_bits_req_in2_prev_unswizzled, 31, 23) node _dfma_io_in_bits_req_in2_prev_prev_fractOut_T = shl(dfma_io_in_bits_req_in2_prev_prev_fractIn, 53) node dfma_io_in_bits_req_in2_prev_prev_fractOut = shr(_dfma_io_in_bits_req_in2_prev_prev_fractOut_T, 24) node dfma_io_in_bits_req_in2_prev_prev_expOut_expCode = bits(dfma_io_in_bits_req_in2_prev_prev_expIn, 8, 6) node _dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T = add(dfma_io_in_bits_req_in2_prev_prev_expIn, UInt<12>(0h800)) node _dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_1 = tail(_dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T, 1) node _dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2 = sub(_dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_1, UInt<9>(0h100)) node dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase = tail(_dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2, 1) node _dfma_io_in_bits_req_in2_prev_prev_expOut_T = eq(dfma_io_in_bits_req_in2_prev_prev_expOut_expCode, UInt<1>(0h0)) node _dfma_io_in_bits_req_in2_prev_prev_expOut_T_1 = geq(dfma_io_in_bits_req_in2_prev_prev_expOut_expCode, UInt<3>(0h6)) node _dfma_io_in_bits_req_in2_prev_prev_expOut_T_2 = or(_dfma_io_in_bits_req_in2_prev_prev_expOut_T, _dfma_io_in_bits_req_in2_prev_prev_expOut_T_1) node _dfma_io_in_bits_req_in2_prev_prev_expOut_T_3 = bits(dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase, 8, 0) node _dfma_io_in_bits_req_in2_prev_prev_expOut_T_4 = cat(dfma_io_in_bits_req_in2_prev_prev_expOut_expCode, _dfma_io_in_bits_req_in2_prev_prev_expOut_T_3) node _dfma_io_in_bits_req_in2_prev_prev_expOut_T_5 = bits(dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase, 11, 0) node dfma_io_in_bits_req_in2_prev_prev_expOut = mux(_dfma_io_in_bits_req_in2_prev_prev_expOut_T_2, _dfma_io_in_bits_req_in2_prev_prev_expOut_T_4, _dfma_io_in_bits_req_in2_prev_prev_expOut_T_5) node dfma_io_in_bits_req_in2_prev_prev_hi = cat(dfma_io_in_bits_req_in2_prev_prev_sign, dfma_io_in_bits_req_in2_prev_prev_expOut) node dfma_io_in_bits_req_in2_floats_1 = cat(dfma_io_in_bits_req_in2_prev_prev_hi, dfma_io_in_bits_req_in2_prev_prev_fractOut) node _dfma_io_in_bits_req_in2_prev_isbox_T = bits(ex_rs_1, 64, 60) node dfma_io_in_bits_req_in2_prev_isbox = andr(_dfma_io_in_bits_req_in2_prev_isbox_T) node dfma_io_in_bits_req_in2_oks_0 = and(dfma_io_in_bits_req_in2_prev_isbox, dfma_io_in_bits_req_in2_prev_prev_0_1) node dfma_io_in_bits_req_in2_oks_1 = and(dfma_io_in_bits_req_in2_prev_isbox, UInt<1>(0h1)) node _dfma_io_in_bits_req_in2_T = mux(UInt<1>(0h1), UInt<1>(0h0), UInt<65>(0he008000000000000)) node _dfma_io_in_bits_req_in2_T_1 = or(ex_rs_1, _dfma_io_in_bits_req_in2_T) connect dfma_io_in_bits_req.in2, _dfma_io_in_bits_req_in2_T_1 node _dfma_io_in_bits_req_in3_prev_unswizzled_T = bits(ex_rs_2, 31, 31) node _dfma_io_in_bits_req_in3_prev_unswizzled_T_1 = bits(ex_rs_2, 52, 52) node _dfma_io_in_bits_req_in3_prev_unswizzled_T_2 = bits(ex_rs_2, 30, 0) node dfma_io_in_bits_req_in3_prev_unswizzled_hi = cat(_dfma_io_in_bits_req_in3_prev_unswizzled_T, _dfma_io_in_bits_req_in3_prev_unswizzled_T_1) node dfma_io_in_bits_req_in3_prev_unswizzled = cat(dfma_io_in_bits_req_in3_prev_unswizzled_hi, _dfma_io_in_bits_req_in3_prev_unswizzled_T_2) node _dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T = bits(dfma_io_in_bits_req_in3_prev_unswizzled, 15, 15) node _dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_1 = bits(dfma_io_in_bits_req_in3_prev_unswizzled, 23, 23) node _dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_2 = bits(dfma_io_in_bits_req_in3_prev_unswizzled, 14, 0) node dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_hi = cat(_dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T, _dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_1) node dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled = cat(dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_hi, _dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_2) node dfma_io_in_bits_req_in3_prev_prev_prev_prev_sign = bits(dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled, 16, 16) node dfma_io_in_bits_req_in3_prev_prev_prev_prev_fractIn = bits(dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled, 9, 0) node dfma_io_in_bits_req_in3_prev_prev_prev_prev_expIn = bits(dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled, 15, 10) node _dfma_io_in_bits_req_in3_prev_prev_prev_prev_fractOut_T = shl(dfma_io_in_bits_req_in3_prev_prev_prev_prev_fractIn, 53) node dfma_io_in_bits_req_in3_prev_prev_prev_prev_fractOut = shr(_dfma_io_in_bits_req_in3_prev_prev_prev_prev_fractOut_T, 11) node dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode = bits(dfma_io_in_bits_req_in3_prev_prev_prev_prev_expIn, 5, 3) node _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T = add(dfma_io_in_bits_req_in3_prev_prev_prev_prev_expIn, UInt<12>(0h800)) node _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_1 = tail(_dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T, 1) node _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_2 = sub(_dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_1, UInt<6>(0h20)) node dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase = tail(_dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_2, 1) node _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T = eq(dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode, UInt<1>(0h0)) node _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_1 = geq(dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode, UInt<3>(0h6)) node _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_2 = or(_dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T, _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_1) node _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_3 = bits(dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase, 8, 0) node _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_4 = cat(dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode, _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_3) node _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_5 = bits(dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase, 11, 0) node dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut = mux(_dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_2, _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_4, _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_5) node dfma_io_in_bits_req_in3_prev_prev_prev_prev_hi = cat(dfma_io_in_bits_req_in3_prev_prev_prev_prev_sign, dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut) node dfma_io_in_bits_req_in3_floats_0 = cat(dfma_io_in_bits_req_in3_prev_prev_prev_prev_hi, dfma_io_in_bits_req_in3_prev_prev_prev_prev_fractOut) node _dfma_io_in_bits_req_in3_prev_prev_prev_isbox_T = bits(dfma_io_in_bits_req_in3_prev_unswizzled, 32, 28) node dfma_io_in_bits_req_in3_prev_prev_prev_isbox = andr(_dfma_io_in_bits_req_in3_prev_prev_prev_isbox_T) node dfma_io_in_bits_req_in3_prev_prev_0_1 = and(dfma_io_in_bits_req_in3_prev_prev_prev_isbox, UInt<1>(0h1)) node dfma_io_in_bits_req_in3_prev_prev_sign = bits(dfma_io_in_bits_req_in3_prev_unswizzled, 32, 32) node dfma_io_in_bits_req_in3_prev_prev_fractIn = bits(dfma_io_in_bits_req_in3_prev_unswizzled, 22, 0) node dfma_io_in_bits_req_in3_prev_prev_expIn = bits(dfma_io_in_bits_req_in3_prev_unswizzled, 31, 23) node _dfma_io_in_bits_req_in3_prev_prev_fractOut_T = shl(dfma_io_in_bits_req_in3_prev_prev_fractIn, 53) node dfma_io_in_bits_req_in3_prev_prev_fractOut = shr(_dfma_io_in_bits_req_in3_prev_prev_fractOut_T, 24) node dfma_io_in_bits_req_in3_prev_prev_expOut_expCode = bits(dfma_io_in_bits_req_in3_prev_prev_expIn, 8, 6) node _dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T = add(dfma_io_in_bits_req_in3_prev_prev_expIn, UInt<12>(0h800)) node _dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_1 = tail(_dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T, 1) node _dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_2 = sub(_dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_1, UInt<9>(0h100)) node dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase = tail(_dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_2, 1) node _dfma_io_in_bits_req_in3_prev_prev_expOut_T = eq(dfma_io_in_bits_req_in3_prev_prev_expOut_expCode, UInt<1>(0h0)) node _dfma_io_in_bits_req_in3_prev_prev_expOut_T_1 = geq(dfma_io_in_bits_req_in3_prev_prev_expOut_expCode, UInt<3>(0h6)) node _dfma_io_in_bits_req_in3_prev_prev_expOut_T_2 = or(_dfma_io_in_bits_req_in3_prev_prev_expOut_T, _dfma_io_in_bits_req_in3_prev_prev_expOut_T_1) node _dfma_io_in_bits_req_in3_prev_prev_expOut_T_3 = bits(dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase, 8, 0) node _dfma_io_in_bits_req_in3_prev_prev_expOut_T_4 = cat(dfma_io_in_bits_req_in3_prev_prev_expOut_expCode, _dfma_io_in_bits_req_in3_prev_prev_expOut_T_3) node _dfma_io_in_bits_req_in3_prev_prev_expOut_T_5 = bits(dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase, 11, 0) node dfma_io_in_bits_req_in3_prev_prev_expOut = mux(_dfma_io_in_bits_req_in3_prev_prev_expOut_T_2, _dfma_io_in_bits_req_in3_prev_prev_expOut_T_4, _dfma_io_in_bits_req_in3_prev_prev_expOut_T_5) node dfma_io_in_bits_req_in3_prev_prev_hi = cat(dfma_io_in_bits_req_in3_prev_prev_sign, dfma_io_in_bits_req_in3_prev_prev_expOut) node dfma_io_in_bits_req_in3_floats_1 = cat(dfma_io_in_bits_req_in3_prev_prev_hi, dfma_io_in_bits_req_in3_prev_prev_fractOut) node _dfma_io_in_bits_req_in3_prev_isbox_T = bits(ex_rs_2, 64, 60) node dfma_io_in_bits_req_in3_prev_isbox = andr(_dfma_io_in_bits_req_in3_prev_isbox_T) node dfma_io_in_bits_req_in3_oks_0 = and(dfma_io_in_bits_req_in3_prev_isbox, dfma_io_in_bits_req_in3_prev_prev_0_1) node dfma_io_in_bits_req_in3_oks_1 = and(dfma_io_in_bits_req_in3_prev_isbox, UInt<1>(0h1)) node _dfma_io_in_bits_req_in3_T = mux(UInt<1>(0h1), UInt<1>(0h0), UInt<65>(0he008000000000000)) node _dfma_io_in_bits_req_in3_T_1 = or(ex_rs_2, _dfma_io_in_bits_req_in3_T) connect dfma_io_in_bits_req.in3, _dfma_io_in_bits_req_in3_T_1 node _dfma_io_in_bits_req_typ_T = bits(ex_reg_inst, 21, 20) connect dfma_io_in_bits_req.typ, _dfma_io_in_bits_req_typ_T node _dfma_io_in_bits_req_fmt_T = bits(ex_reg_inst, 26, 25) connect dfma_io_in_bits_req.fmt, _dfma_io_in_bits_req_fmt_T node _dfma_io_in_bits_req_fmaCmd_T = bits(ex_reg_inst, 3, 2) node _dfma_io_in_bits_req_fmaCmd_T_1 = eq(ex_ctrl.ren3, UInt<1>(0h0)) node _dfma_io_in_bits_req_fmaCmd_T_2 = bits(ex_reg_inst, 27, 27) node _dfma_io_in_bits_req_fmaCmd_T_3 = and(_dfma_io_in_bits_req_fmaCmd_T_1, _dfma_io_in_bits_req_fmaCmd_T_2) node _dfma_io_in_bits_req_fmaCmd_T_4 = or(_dfma_io_in_bits_req_fmaCmd_T, _dfma_io_in_bits_req_fmaCmd_T_3) connect dfma_io_in_bits_req.fmaCmd, _dfma_io_in_bits_req_fmaCmd_T_4 when ex_cp_valid : connect dfma_io_in_bits_req, io.cp_req.bits when io.cp_req.bits.swap12 : connect dfma_io_in_bits_req.in1, io.cp_req.bits.in2 connect dfma_io_in_bits_req.in2, io.cp_req.bits.in1 when io.cp_req.bits.swap23 : connect dfma_io_in_bits_req.in2, io.cp_req.bits.in3 connect dfma_io_in_bits_req.in3, io.cp_req.bits.in2 connect dfma.io.in.bits.in3, dfma_io_in_bits_req.in3 connect dfma.io.in.bits.in2, dfma_io_in_bits_req.in2 connect dfma.io.in.bits.in1, dfma_io_in_bits_req.in1 connect dfma.io.in.bits.fmt, dfma_io_in_bits_req.fmt connect dfma.io.in.bits.typ, dfma_io_in_bits_req.typ connect dfma.io.in.bits.fmaCmd, dfma_io_in_bits_req.fmaCmd connect dfma.io.in.bits.rm, dfma_io_in_bits_req.rm connect dfma.io.in.bits.vec, dfma_io_in_bits_req.vec connect dfma.io.in.bits.wflags, dfma_io_in_bits_req.wflags connect dfma.io.in.bits.sqrt, dfma_io_in_bits_req.sqrt connect dfma.io.in.bits.div, dfma_io_in_bits_req.div connect dfma.io.in.bits.fma, dfma_io_in_bits_req.fma connect dfma.io.in.bits.fastpipe, dfma_io_in_bits_req.fastpipe connect dfma.io.in.bits.toint, dfma_io_in_bits_req.toint connect dfma.io.in.bits.fromint, dfma_io_in_bits_req.fromint connect dfma.io.in.bits.typeTagOut, dfma_io_in_bits_req.typeTagOut connect dfma.io.in.bits.typeTagIn, dfma_io_in_bits_req.typeTagIn connect dfma.io.in.bits.swap23, dfma_io_in_bits_req.swap23 connect dfma.io.in.bits.swap12, dfma_io_in_bits_req.swap12 connect dfma.io.in.bits.ren3, dfma_io_in_bits_req.ren3 connect dfma.io.in.bits.ren2, dfma_io_in_bits_req.ren2 connect dfma.io.in.bits.ren1, dfma_io_in_bits_req.ren1 connect dfma.io.in.bits.wen, dfma_io_in_bits_req.wen connect dfma.io.in.bits.ldst, dfma_io_in_bits_req.ldst inst hfma of FPUFMAPipe_l3_f16_1 connect hfma.clock, clock connect hfma.reset, reset node _hfma_io_in_valid_T = and(req_valid, ex_ctrl.fma) node _hfma_io_in_valid_T_1 = eq(ex_ctrl.typeTagOut, UInt<1>(0h0)) node _hfma_io_in_valid_T_2 = and(_hfma_io_in_valid_T, _hfma_io_in_valid_T_1) connect hfma.io.in.valid, _hfma_io_in_valid_T_2 wire hfma_io_in_bits_req : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>} connect hfma_io_in_bits_req.vec, ex_ctrl.vec connect hfma_io_in_bits_req.wflags, ex_ctrl.wflags connect hfma_io_in_bits_req.sqrt, ex_ctrl.sqrt connect hfma_io_in_bits_req.div, ex_ctrl.div connect hfma_io_in_bits_req.fma, ex_ctrl.fma connect hfma_io_in_bits_req.fastpipe, ex_ctrl.fastpipe connect hfma_io_in_bits_req.toint, ex_ctrl.toint connect hfma_io_in_bits_req.fromint, ex_ctrl.fromint connect hfma_io_in_bits_req.typeTagOut, ex_ctrl.typeTagOut connect hfma_io_in_bits_req.typeTagIn, ex_ctrl.typeTagIn connect hfma_io_in_bits_req.swap23, ex_ctrl.swap23 connect hfma_io_in_bits_req.swap12, ex_ctrl.swap12 connect hfma_io_in_bits_req.ren3, ex_ctrl.ren3 connect hfma_io_in_bits_req.ren2, ex_ctrl.ren2 connect hfma_io_in_bits_req.ren1, ex_ctrl.ren1 connect hfma_io_in_bits_req.wen, ex_ctrl.wen connect hfma_io_in_bits_req.ldst, ex_ctrl.ldst connect hfma_io_in_bits_req.rm, ex_rm node _hfma_io_in_bits_req_in1_prev_unswizzled_T = bits(ex_rs_0, 31, 31) node _hfma_io_in_bits_req_in1_prev_unswizzled_T_1 = bits(ex_rs_0, 52, 52) node _hfma_io_in_bits_req_in1_prev_unswizzled_T_2 = bits(ex_rs_0, 30, 0) node hfma_io_in_bits_req_in1_prev_unswizzled_hi = cat(_hfma_io_in_bits_req_in1_prev_unswizzled_T, _hfma_io_in_bits_req_in1_prev_unswizzled_T_1) node hfma_io_in_bits_req_in1_prev_unswizzled = cat(hfma_io_in_bits_req_in1_prev_unswizzled_hi, _hfma_io_in_bits_req_in1_prev_unswizzled_T_2) node _hfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T = bits(hfma_io_in_bits_req_in1_prev_unswizzled, 15, 15) node _hfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_1 = bits(hfma_io_in_bits_req_in1_prev_unswizzled, 23, 23) node _hfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_2 = bits(hfma_io_in_bits_req_in1_prev_unswizzled, 14, 0) node hfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_hi = cat(_hfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T, _hfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_1) node hfma_io_in_bits_req_in1_floats_0 = cat(hfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_hi, _hfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_2) node _hfma_io_in_bits_req_in1_prev_prev_prev_isbox_T = bits(hfma_io_in_bits_req_in1_prev_unswizzled, 32, 28) node hfma_io_in_bits_req_in1_prev_prev_prev_isbox = andr(_hfma_io_in_bits_req_in1_prev_prev_prev_isbox_T) node hfma_io_in_bits_req_in1_prev_prev_0_1 = and(hfma_io_in_bits_req_in1_prev_prev_prev_isbox, UInt<1>(0h1)) node hfma_io_in_bits_req_in1_prev_prev_sign = bits(hfma_io_in_bits_req_in1_prev_unswizzled, 32, 32) node hfma_io_in_bits_req_in1_prev_prev_fractIn = bits(hfma_io_in_bits_req_in1_prev_unswizzled, 22, 0) node hfma_io_in_bits_req_in1_prev_prev_expIn = bits(hfma_io_in_bits_req_in1_prev_unswizzled, 31, 23) node _hfma_io_in_bits_req_in1_prev_prev_fractOut_T = shl(hfma_io_in_bits_req_in1_prev_prev_fractIn, 11) node hfma_io_in_bits_req_in1_prev_prev_fractOut = shr(_hfma_io_in_bits_req_in1_prev_prev_fractOut_T, 24) node hfma_io_in_bits_req_in1_prev_prev_expOut_expCode = bits(hfma_io_in_bits_req_in1_prev_prev_expIn, 8, 6) node _hfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T = add(hfma_io_in_bits_req_in1_prev_prev_expIn, UInt<6>(0h20)) node _hfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_1 = tail(_hfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T, 1) node _hfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2 = sub(_hfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_1, UInt<9>(0h100)) node hfma_io_in_bits_req_in1_prev_prev_expOut_commonCase = tail(_hfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2, 1) node _hfma_io_in_bits_req_in1_prev_prev_expOut_T = eq(hfma_io_in_bits_req_in1_prev_prev_expOut_expCode, UInt<1>(0h0)) node _hfma_io_in_bits_req_in1_prev_prev_expOut_T_1 = geq(hfma_io_in_bits_req_in1_prev_prev_expOut_expCode, UInt<3>(0h6)) node _hfma_io_in_bits_req_in1_prev_prev_expOut_T_2 = or(_hfma_io_in_bits_req_in1_prev_prev_expOut_T, _hfma_io_in_bits_req_in1_prev_prev_expOut_T_1) node _hfma_io_in_bits_req_in1_prev_prev_expOut_T_3 = bits(hfma_io_in_bits_req_in1_prev_prev_expOut_commonCase, 2, 0) node _hfma_io_in_bits_req_in1_prev_prev_expOut_T_4 = cat(hfma_io_in_bits_req_in1_prev_prev_expOut_expCode, _hfma_io_in_bits_req_in1_prev_prev_expOut_T_3) node _hfma_io_in_bits_req_in1_prev_prev_expOut_T_5 = bits(hfma_io_in_bits_req_in1_prev_prev_expOut_commonCase, 5, 0) node hfma_io_in_bits_req_in1_prev_prev_expOut = mux(_hfma_io_in_bits_req_in1_prev_prev_expOut_T_2, _hfma_io_in_bits_req_in1_prev_prev_expOut_T_4, _hfma_io_in_bits_req_in1_prev_prev_expOut_T_5) node hfma_io_in_bits_req_in1_prev_prev_hi = cat(hfma_io_in_bits_req_in1_prev_prev_sign, hfma_io_in_bits_req_in1_prev_prev_expOut) node hfma_io_in_bits_req_in1_floats_1 = cat(hfma_io_in_bits_req_in1_prev_prev_hi, hfma_io_in_bits_req_in1_prev_prev_fractOut) node _hfma_io_in_bits_req_in1_prev_isbox_T = bits(ex_rs_0, 64, 60) node hfma_io_in_bits_req_in1_prev_isbox = andr(_hfma_io_in_bits_req_in1_prev_isbox_T) node hfma_io_in_bits_req_in1_oks_0 = and(hfma_io_in_bits_req_in1_prev_isbox, hfma_io_in_bits_req_in1_prev_prev_0_1) node hfma_io_in_bits_req_in1_oks_1 = and(hfma_io_in_bits_req_in1_prev_isbox, UInt<1>(0h1)) node hfma_io_in_bits_req_in1_sign = bits(ex_rs_0, 64, 64) node hfma_io_in_bits_req_in1_fractIn = bits(ex_rs_0, 51, 0) node hfma_io_in_bits_req_in1_expIn = bits(ex_rs_0, 63, 52) node _hfma_io_in_bits_req_in1_fractOut_T = shl(hfma_io_in_bits_req_in1_fractIn, 11) node hfma_io_in_bits_req_in1_fractOut = shr(_hfma_io_in_bits_req_in1_fractOut_T, 53) node hfma_io_in_bits_req_in1_expOut_expCode = bits(hfma_io_in_bits_req_in1_expIn, 11, 9) node _hfma_io_in_bits_req_in1_expOut_commonCase_T = add(hfma_io_in_bits_req_in1_expIn, UInt<6>(0h20)) node _hfma_io_in_bits_req_in1_expOut_commonCase_T_1 = tail(_hfma_io_in_bits_req_in1_expOut_commonCase_T, 1) node _hfma_io_in_bits_req_in1_expOut_commonCase_T_2 = sub(_hfma_io_in_bits_req_in1_expOut_commonCase_T_1, UInt<12>(0h800)) node hfma_io_in_bits_req_in1_expOut_commonCase = tail(_hfma_io_in_bits_req_in1_expOut_commonCase_T_2, 1) node _hfma_io_in_bits_req_in1_expOut_T = eq(hfma_io_in_bits_req_in1_expOut_expCode, UInt<1>(0h0)) node _hfma_io_in_bits_req_in1_expOut_T_1 = geq(hfma_io_in_bits_req_in1_expOut_expCode, UInt<3>(0h6)) node _hfma_io_in_bits_req_in1_expOut_T_2 = or(_hfma_io_in_bits_req_in1_expOut_T, _hfma_io_in_bits_req_in1_expOut_T_1) node _hfma_io_in_bits_req_in1_expOut_T_3 = bits(hfma_io_in_bits_req_in1_expOut_commonCase, 2, 0) node _hfma_io_in_bits_req_in1_expOut_T_4 = cat(hfma_io_in_bits_req_in1_expOut_expCode, _hfma_io_in_bits_req_in1_expOut_T_3) node _hfma_io_in_bits_req_in1_expOut_T_5 = bits(hfma_io_in_bits_req_in1_expOut_commonCase, 5, 0) node hfma_io_in_bits_req_in1_expOut = mux(_hfma_io_in_bits_req_in1_expOut_T_2, _hfma_io_in_bits_req_in1_expOut_T_4, _hfma_io_in_bits_req_in1_expOut_T_5) node hfma_io_in_bits_req_in1_hi = cat(hfma_io_in_bits_req_in1_sign, hfma_io_in_bits_req_in1_expOut) node hfma_io_in_bits_req_in1_floats_2 = cat(hfma_io_in_bits_req_in1_hi, hfma_io_in_bits_req_in1_fractOut) node _hfma_io_in_bits_req_in1_T = mux(hfma_io_in_bits_req_in1_oks_0, UInt<1>(0h0), UInt<17>(0he200)) node _hfma_io_in_bits_req_in1_T_1 = or(hfma_io_in_bits_req_in1_floats_0, _hfma_io_in_bits_req_in1_T) connect hfma_io_in_bits_req.in1, _hfma_io_in_bits_req_in1_T_1 node _hfma_io_in_bits_req_in2_prev_unswizzled_T = bits(ex_rs_1, 31, 31) node _hfma_io_in_bits_req_in2_prev_unswizzled_T_1 = bits(ex_rs_1, 52, 52) node _hfma_io_in_bits_req_in2_prev_unswizzled_T_2 = bits(ex_rs_1, 30, 0) node hfma_io_in_bits_req_in2_prev_unswizzled_hi = cat(_hfma_io_in_bits_req_in2_prev_unswizzled_T, _hfma_io_in_bits_req_in2_prev_unswizzled_T_1) node hfma_io_in_bits_req_in2_prev_unswizzled = cat(hfma_io_in_bits_req_in2_prev_unswizzled_hi, _hfma_io_in_bits_req_in2_prev_unswizzled_T_2) node _hfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T = bits(hfma_io_in_bits_req_in2_prev_unswizzled, 15, 15) node _hfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_1 = bits(hfma_io_in_bits_req_in2_prev_unswizzled, 23, 23) node _hfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_2 = bits(hfma_io_in_bits_req_in2_prev_unswizzled, 14, 0) node hfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_hi = cat(_hfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T, _hfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_1) node hfma_io_in_bits_req_in2_floats_0 = cat(hfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_hi, _hfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_2) node _hfma_io_in_bits_req_in2_prev_prev_prev_isbox_T = bits(hfma_io_in_bits_req_in2_prev_unswizzled, 32, 28) node hfma_io_in_bits_req_in2_prev_prev_prev_isbox = andr(_hfma_io_in_bits_req_in2_prev_prev_prev_isbox_T) node hfma_io_in_bits_req_in2_prev_prev_0_1 = and(hfma_io_in_bits_req_in2_prev_prev_prev_isbox, UInt<1>(0h1)) node hfma_io_in_bits_req_in2_prev_prev_sign = bits(hfma_io_in_bits_req_in2_prev_unswizzled, 32, 32) node hfma_io_in_bits_req_in2_prev_prev_fractIn = bits(hfma_io_in_bits_req_in2_prev_unswizzled, 22, 0) node hfma_io_in_bits_req_in2_prev_prev_expIn = bits(hfma_io_in_bits_req_in2_prev_unswizzled, 31, 23) node _hfma_io_in_bits_req_in2_prev_prev_fractOut_T = shl(hfma_io_in_bits_req_in2_prev_prev_fractIn, 11) node hfma_io_in_bits_req_in2_prev_prev_fractOut = shr(_hfma_io_in_bits_req_in2_prev_prev_fractOut_T, 24) node hfma_io_in_bits_req_in2_prev_prev_expOut_expCode = bits(hfma_io_in_bits_req_in2_prev_prev_expIn, 8, 6) node _hfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T = add(hfma_io_in_bits_req_in2_prev_prev_expIn, UInt<6>(0h20)) node _hfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_1 = tail(_hfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T, 1) node _hfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2 = sub(_hfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_1, UInt<9>(0h100)) node hfma_io_in_bits_req_in2_prev_prev_expOut_commonCase = tail(_hfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2, 1) node _hfma_io_in_bits_req_in2_prev_prev_expOut_T = eq(hfma_io_in_bits_req_in2_prev_prev_expOut_expCode, UInt<1>(0h0)) node _hfma_io_in_bits_req_in2_prev_prev_expOut_T_1 = geq(hfma_io_in_bits_req_in2_prev_prev_expOut_expCode, UInt<3>(0h6)) node _hfma_io_in_bits_req_in2_prev_prev_expOut_T_2 = or(_hfma_io_in_bits_req_in2_prev_prev_expOut_T, _hfma_io_in_bits_req_in2_prev_prev_expOut_T_1) node _hfma_io_in_bits_req_in2_prev_prev_expOut_T_3 = bits(hfma_io_in_bits_req_in2_prev_prev_expOut_commonCase, 2, 0) node _hfma_io_in_bits_req_in2_prev_prev_expOut_T_4 = cat(hfma_io_in_bits_req_in2_prev_prev_expOut_expCode, _hfma_io_in_bits_req_in2_prev_prev_expOut_T_3) node _hfma_io_in_bits_req_in2_prev_prev_expOut_T_5 = bits(hfma_io_in_bits_req_in2_prev_prev_expOut_commonCase, 5, 0) node hfma_io_in_bits_req_in2_prev_prev_expOut = mux(_hfma_io_in_bits_req_in2_prev_prev_expOut_T_2, _hfma_io_in_bits_req_in2_prev_prev_expOut_T_4, _hfma_io_in_bits_req_in2_prev_prev_expOut_T_5) node hfma_io_in_bits_req_in2_prev_prev_hi = cat(hfma_io_in_bits_req_in2_prev_prev_sign, hfma_io_in_bits_req_in2_prev_prev_expOut) node hfma_io_in_bits_req_in2_floats_1 = cat(hfma_io_in_bits_req_in2_prev_prev_hi, hfma_io_in_bits_req_in2_prev_prev_fractOut) node _hfma_io_in_bits_req_in2_prev_isbox_T = bits(ex_rs_1, 64, 60) node hfma_io_in_bits_req_in2_prev_isbox = andr(_hfma_io_in_bits_req_in2_prev_isbox_T) node hfma_io_in_bits_req_in2_oks_0 = and(hfma_io_in_bits_req_in2_prev_isbox, hfma_io_in_bits_req_in2_prev_prev_0_1) node hfma_io_in_bits_req_in2_oks_1 = and(hfma_io_in_bits_req_in2_prev_isbox, UInt<1>(0h1)) node hfma_io_in_bits_req_in2_sign = bits(ex_rs_1, 64, 64) node hfma_io_in_bits_req_in2_fractIn = bits(ex_rs_1, 51, 0) node hfma_io_in_bits_req_in2_expIn = bits(ex_rs_1, 63, 52) node _hfma_io_in_bits_req_in2_fractOut_T = shl(hfma_io_in_bits_req_in2_fractIn, 11) node hfma_io_in_bits_req_in2_fractOut = shr(_hfma_io_in_bits_req_in2_fractOut_T, 53) node hfma_io_in_bits_req_in2_expOut_expCode = bits(hfma_io_in_bits_req_in2_expIn, 11, 9) node _hfma_io_in_bits_req_in2_expOut_commonCase_T = add(hfma_io_in_bits_req_in2_expIn, UInt<6>(0h20)) node _hfma_io_in_bits_req_in2_expOut_commonCase_T_1 = tail(_hfma_io_in_bits_req_in2_expOut_commonCase_T, 1) node _hfma_io_in_bits_req_in2_expOut_commonCase_T_2 = sub(_hfma_io_in_bits_req_in2_expOut_commonCase_T_1, UInt<12>(0h800)) node hfma_io_in_bits_req_in2_expOut_commonCase = tail(_hfma_io_in_bits_req_in2_expOut_commonCase_T_2, 1) node _hfma_io_in_bits_req_in2_expOut_T = eq(hfma_io_in_bits_req_in2_expOut_expCode, UInt<1>(0h0)) node _hfma_io_in_bits_req_in2_expOut_T_1 = geq(hfma_io_in_bits_req_in2_expOut_expCode, UInt<3>(0h6)) node _hfma_io_in_bits_req_in2_expOut_T_2 = or(_hfma_io_in_bits_req_in2_expOut_T, _hfma_io_in_bits_req_in2_expOut_T_1) node _hfma_io_in_bits_req_in2_expOut_T_3 = bits(hfma_io_in_bits_req_in2_expOut_commonCase, 2, 0) node _hfma_io_in_bits_req_in2_expOut_T_4 = cat(hfma_io_in_bits_req_in2_expOut_expCode, _hfma_io_in_bits_req_in2_expOut_T_3) node _hfma_io_in_bits_req_in2_expOut_T_5 = bits(hfma_io_in_bits_req_in2_expOut_commonCase, 5, 0) node hfma_io_in_bits_req_in2_expOut = mux(_hfma_io_in_bits_req_in2_expOut_T_2, _hfma_io_in_bits_req_in2_expOut_T_4, _hfma_io_in_bits_req_in2_expOut_T_5) node hfma_io_in_bits_req_in2_hi = cat(hfma_io_in_bits_req_in2_sign, hfma_io_in_bits_req_in2_expOut) node hfma_io_in_bits_req_in2_floats_2 = cat(hfma_io_in_bits_req_in2_hi, hfma_io_in_bits_req_in2_fractOut) node _hfma_io_in_bits_req_in2_T = mux(hfma_io_in_bits_req_in2_oks_0, UInt<1>(0h0), UInt<17>(0he200)) node _hfma_io_in_bits_req_in2_T_1 = or(hfma_io_in_bits_req_in2_floats_0, _hfma_io_in_bits_req_in2_T) connect hfma_io_in_bits_req.in2, _hfma_io_in_bits_req_in2_T_1 node _hfma_io_in_bits_req_in3_prev_unswizzled_T = bits(ex_rs_2, 31, 31) node _hfma_io_in_bits_req_in3_prev_unswizzled_T_1 = bits(ex_rs_2, 52, 52) node _hfma_io_in_bits_req_in3_prev_unswizzled_T_2 = bits(ex_rs_2, 30, 0) node hfma_io_in_bits_req_in3_prev_unswizzled_hi = cat(_hfma_io_in_bits_req_in3_prev_unswizzled_T, _hfma_io_in_bits_req_in3_prev_unswizzled_T_1) node hfma_io_in_bits_req_in3_prev_unswizzled = cat(hfma_io_in_bits_req_in3_prev_unswizzled_hi, _hfma_io_in_bits_req_in3_prev_unswizzled_T_2) node _hfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T = bits(hfma_io_in_bits_req_in3_prev_unswizzled, 15, 15) node _hfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_1 = bits(hfma_io_in_bits_req_in3_prev_unswizzled, 23, 23) node _hfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_2 = bits(hfma_io_in_bits_req_in3_prev_unswizzled, 14, 0) node hfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_hi = cat(_hfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T, _hfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_1) node hfma_io_in_bits_req_in3_floats_0 = cat(hfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_hi, _hfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_2) node _hfma_io_in_bits_req_in3_prev_prev_prev_isbox_T = bits(hfma_io_in_bits_req_in3_prev_unswizzled, 32, 28) node hfma_io_in_bits_req_in3_prev_prev_prev_isbox = andr(_hfma_io_in_bits_req_in3_prev_prev_prev_isbox_T) node hfma_io_in_bits_req_in3_prev_prev_0_1 = and(hfma_io_in_bits_req_in3_prev_prev_prev_isbox, UInt<1>(0h1)) node hfma_io_in_bits_req_in3_prev_prev_sign = bits(hfma_io_in_bits_req_in3_prev_unswizzled, 32, 32) node hfma_io_in_bits_req_in3_prev_prev_fractIn = bits(hfma_io_in_bits_req_in3_prev_unswizzled, 22, 0) node hfma_io_in_bits_req_in3_prev_prev_expIn = bits(hfma_io_in_bits_req_in3_prev_unswizzled, 31, 23) node _hfma_io_in_bits_req_in3_prev_prev_fractOut_T = shl(hfma_io_in_bits_req_in3_prev_prev_fractIn, 11) node hfma_io_in_bits_req_in3_prev_prev_fractOut = shr(_hfma_io_in_bits_req_in3_prev_prev_fractOut_T, 24) node hfma_io_in_bits_req_in3_prev_prev_expOut_expCode = bits(hfma_io_in_bits_req_in3_prev_prev_expIn, 8, 6) node _hfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T = add(hfma_io_in_bits_req_in3_prev_prev_expIn, UInt<6>(0h20)) node _hfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_1 = tail(_hfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T, 1) node _hfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_2 = sub(_hfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_1, UInt<9>(0h100)) node hfma_io_in_bits_req_in3_prev_prev_expOut_commonCase = tail(_hfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_2, 1) node _hfma_io_in_bits_req_in3_prev_prev_expOut_T = eq(hfma_io_in_bits_req_in3_prev_prev_expOut_expCode, UInt<1>(0h0)) node _hfma_io_in_bits_req_in3_prev_prev_expOut_T_1 = geq(hfma_io_in_bits_req_in3_prev_prev_expOut_expCode, UInt<3>(0h6)) node _hfma_io_in_bits_req_in3_prev_prev_expOut_T_2 = or(_hfma_io_in_bits_req_in3_prev_prev_expOut_T, _hfma_io_in_bits_req_in3_prev_prev_expOut_T_1) node _hfma_io_in_bits_req_in3_prev_prev_expOut_T_3 = bits(hfma_io_in_bits_req_in3_prev_prev_expOut_commonCase, 2, 0) node _hfma_io_in_bits_req_in3_prev_prev_expOut_T_4 = cat(hfma_io_in_bits_req_in3_prev_prev_expOut_expCode, _hfma_io_in_bits_req_in3_prev_prev_expOut_T_3) node _hfma_io_in_bits_req_in3_prev_prev_expOut_T_5 = bits(hfma_io_in_bits_req_in3_prev_prev_expOut_commonCase, 5, 0) node hfma_io_in_bits_req_in3_prev_prev_expOut = mux(_hfma_io_in_bits_req_in3_prev_prev_expOut_T_2, _hfma_io_in_bits_req_in3_prev_prev_expOut_T_4, _hfma_io_in_bits_req_in3_prev_prev_expOut_T_5) node hfma_io_in_bits_req_in3_prev_prev_hi = cat(hfma_io_in_bits_req_in3_prev_prev_sign, hfma_io_in_bits_req_in3_prev_prev_expOut) node hfma_io_in_bits_req_in3_floats_1 = cat(hfma_io_in_bits_req_in3_prev_prev_hi, hfma_io_in_bits_req_in3_prev_prev_fractOut) node _hfma_io_in_bits_req_in3_prev_isbox_T = bits(ex_rs_2, 64, 60) node hfma_io_in_bits_req_in3_prev_isbox = andr(_hfma_io_in_bits_req_in3_prev_isbox_T) node hfma_io_in_bits_req_in3_oks_0 = and(hfma_io_in_bits_req_in3_prev_isbox, hfma_io_in_bits_req_in3_prev_prev_0_1) node hfma_io_in_bits_req_in3_oks_1 = and(hfma_io_in_bits_req_in3_prev_isbox, UInt<1>(0h1)) node hfma_io_in_bits_req_in3_sign = bits(ex_rs_2, 64, 64) node hfma_io_in_bits_req_in3_fractIn = bits(ex_rs_2, 51, 0) node hfma_io_in_bits_req_in3_expIn = bits(ex_rs_2, 63, 52) node _hfma_io_in_bits_req_in3_fractOut_T = shl(hfma_io_in_bits_req_in3_fractIn, 11) node hfma_io_in_bits_req_in3_fractOut = shr(_hfma_io_in_bits_req_in3_fractOut_T, 53) node hfma_io_in_bits_req_in3_expOut_expCode = bits(hfma_io_in_bits_req_in3_expIn, 11, 9) node _hfma_io_in_bits_req_in3_expOut_commonCase_T = add(hfma_io_in_bits_req_in3_expIn, UInt<6>(0h20)) node _hfma_io_in_bits_req_in3_expOut_commonCase_T_1 = tail(_hfma_io_in_bits_req_in3_expOut_commonCase_T, 1) node _hfma_io_in_bits_req_in3_expOut_commonCase_T_2 = sub(_hfma_io_in_bits_req_in3_expOut_commonCase_T_1, UInt<12>(0h800)) node hfma_io_in_bits_req_in3_expOut_commonCase = tail(_hfma_io_in_bits_req_in3_expOut_commonCase_T_2, 1) node _hfma_io_in_bits_req_in3_expOut_T = eq(hfma_io_in_bits_req_in3_expOut_expCode, UInt<1>(0h0)) node _hfma_io_in_bits_req_in3_expOut_T_1 = geq(hfma_io_in_bits_req_in3_expOut_expCode, UInt<3>(0h6)) node _hfma_io_in_bits_req_in3_expOut_T_2 = or(_hfma_io_in_bits_req_in3_expOut_T, _hfma_io_in_bits_req_in3_expOut_T_1) node _hfma_io_in_bits_req_in3_expOut_T_3 = bits(hfma_io_in_bits_req_in3_expOut_commonCase, 2, 0) node _hfma_io_in_bits_req_in3_expOut_T_4 = cat(hfma_io_in_bits_req_in3_expOut_expCode, _hfma_io_in_bits_req_in3_expOut_T_3) node _hfma_io_in_bits_req_in3_expOut_T_5 = bits(hfma_io_in_bits_req_in3_expOut_commonCase, 5, 0) node hfma_io_in_bits_req_in3_expOut = mux(_hfma_io_in_bits_req_in3_expOut_T_2, _hfma_io_in_bits_req_in3_expOut_T_4, _hfma_io_in_bits_req_in3_expOut_T_5) node hfma_io_in_bits_req_in3_hi = cat(hfma_io_in_bits_req_in3_sign, hfma_io_in_bits_req_in3_expOut) node hfma_io_in_bits_req_in3_floats_2 = cat(hfma_io_in_bits_req_in3_hi, hfma_io_in_bits_req_in3_fractOut) node _hfma_io_in_bits_req_in3_T = mux(hfma_io_in_bits_req_in3_oks_0, UInt<1>(0h0), UInt<17>(0he200)) node _hfma_io_in_bits_req_in3_T_1 = or(hfma_io_in_bits_req_in3_floats_0, _hfma_io_in_bits_req_in3_T) connect hfma_io_in_bits_req.in3, _hfma_io_in_bits_req_in3_T_1 node _hfma_io_in_bits_req_typ_T = bits(ex_reg_inst, 21, 20) connect hfma_io_in_bits_req.typ, _hfma_io_in_bits_req_typ_T node _hfma_io_in_bits_req_fmt_T = bits(ex_reg_inst, 26, 25) connect hfma_io_in_bits_req.fmt, _hfma_io_in_bits_req_fmt_T node _hfma_io_in_bits_req_fmaCmd_T = bits(ex_reg_inst, 3, 2) node _hfma_io_in_bits_req_fmaCmd_T_1 = eq(ex_ctrl.ren3, UInt<1>(0h0)) node _hfma_io_in_bits_req_fmaCmd_T_2 = bits(ex_reg_inst, 27, 27) node _hfma_io_in_bits_req_fmaCmd_T_3 = and(_hfma_io_in_bits_req_fmaCmd_T_1, _hfma_io_in_bits_req_fmaCmd_T_2) node _hfma_io_in_bits_req_fmaCmd_T_4 = or(_hfma_io_in_bits_req_fmaCmd_T, _hfma_io_in_bits_req_fmaCmd_T_3) connect hfma_io_in_bits_req.fmaCmd, _hfma_io_in_bits_req_fmaCmd_T_4 when ex_cp_valid : connect hfma_io_in_bits_req, io.cp_req.bits when io.cp_req.bits.swap12 : connect hfma_io_in_bits_req.in1, io.cp_req.bits.in2 connect hfma_io_in_bits_req.in2, io.cp_req.bits.in1 when io.cp_req.bits.swap23 : connect hfma_io_in_bits_req.in2, io.cp_req.bits.in3 connect hfma_io_in_bits_req.in3, io.cp_req.bits.in2 connect hfma.io.in.bits.in3, hfma_io_in_bits_req.in3 connect hfma.io.in.bits.in2, hfma_io_in_bits_req.in2 connect hfma.io.in.bits.in1, hfma_io_in_bits_req.in1 connect hfma.io.in.bits.fmt, hfma_io_in_bits_req.fmt connect hfma.io.in.bits.typ, hfma_io_in_bits_req.typ connect hfma.io.in.bits.fmaCmd, hfma_io_in_bits_req.fmaCmd connect hfma.io.in.bits.rm, hfma_io_in_bits_req.rm connect hfma.io.in.bits.vec, hfma_io_in_bits_req.vec connect hfma.io.in.bits.wflags, hfma_io_in_bits_req.wflags connect hfma.io.in.bits.sqrt, hfma_io_in_bits_req.sqrt connect hfma.io.in.bits.div, hfma_io_in_bits_req.div connect hfma.io.in.bits.fma, hfma_io_in_bits_req.fma connect hfma.io.in.bits.fastpipe, hfma_io_in_bits_req.fastpipe connect hfma.io.in.bits.toint, hfma_io_in_bits_req.toint connect hfma.io.in.bits.fromint, hfma_io_in_bits_req.fromint connect hfma.io.in.bits.typeTagOut, hfma_io_in_bits_req.typeTagOut connect hfma.io.in.bits.typeTagIn, hfma_io_in_bits_req.typeTagIn connect hfma.io.in.bits.swap23, hfma_io_in_bits_req.swap23 connect hfma.io.in.bits.swap12, hfma_io_in_bits_req.swap12 connect hfma.io.in.bits.ren3, hfma_io_in_bits_req.ren3 connect hfma.io.in.bits.ren2, hfma_io_in_bits_req.ren2 connect hfma.io.in.bits.ren1, hfma_io_in_bits_req.ren1 connect hfma.io.in.bits.wen, hfma_io_in_bits_req.wen connect hfma.io.in.bits.ldst, hfma_io_in_bits_req.ldst node _memLatencyMask_T = mux(mem_ctrl.fastpipe, UInt<1>(0h1), UInt<1>(0h0)) node _memLatencyMask_T_1 = mux(mem_ctrl.fromint, UInt<1>(0h1), UInt<1>(0h0)) node _memLatencyMask_T_2 = eq(mem_ctrl.typeTagOut, UInt<1>(0h1)) node _memLatencyMask_T_3 = and(mem_ctrl.fma, _memLatencyMask_T_2) node _memLatencyMask_T_4 = mux(_memLatencyMask_T_3, UInt<2>(0h2), UInt<1>(0h0)) node _memLatencyMask_T_5 = eq(mem_ctrl.typeTagOut, UInt<2>(0h2)) node _memLatencyMask_T_6 = and(mem_ctrl.fma, _memLatencyMask_T_5) node _memLatencyMask_T_7 = mux(_memLatencyMask_T_6, UInt<3>(0h4), UInt<1>(0h0)) node _memLatencyMask_T_8 = eq(mem_ctrl.typeTagOut, UInt<1>(0h0)) node _memLatencyMask_T_9 = and(mem_ctrl.fma, _memLatencyMask_T_8) node _memLatencyMask_T_10 = mux(_memLatencyMask_T_9, UInt<2>(0h2), UInt<1>(0h0)) node _memLatencyMask_T_11 = or(_memLatencyMask_T, _memLatencyMask_T_1) node _memLatencyMask_T_12 = or(_memLatencyMask_T_11, _memLatencyMask_T_4) node _memLatencyMask_T_13 = or(_memLatencyMask_T_12, _memLatencyMask_T_7) node memLatencyMask = or(_memLatencyMask_T_13, _memLatencyMask_T_10) regreset wen : UInt<3>, clock, reset, UInt<3>(0h0) reg wbInfo : { rd : UInt<5>, typeTag : UInt<2>, cp : UInt<1>, pipeid : UInt<3>}[3], clock node _mem_wen_T = or(mem_ctrl.fma, mem_ctrl.fastpipe) node _mem_wen_T_1 = or(_mem_wen_T, mem_ctrl.fromint) node mem_wen = and(mem_reg_valid, _mem_wen_T_1) node _write_port_busy_T = mux(ex_ctrl.fastpipe, UInt<2>(0h2), UInt<1>(0h0)) node _write_port_busy_T_1 = mux(ex_ctrl.fromint, UInt<2>(0h2), UInt<1>(0h0)) node _write_port_busy_T_2 = eq(ex_ctrl.typeTagOut, UInt<1>(0h1)) node _write_port_busy_T_3 = and(ex_ctrl.fma, _write_port_busy_T_2) node _write_port_busy_T_4 = mux(_write_port_busy_T_3, UInt<3>(0h4), UInt<1>(0h0)) node _write_port_busy_T_5 = eq(ex_ctrl.typeTagOut, UInt<2>(0h2)) node _write_port_busy_T_6 = and(ex_ctrl.fma, _write_port_busy_T_5) node _write_port_busy_T_7 = mux(_write_port_busy_T_6, UInt<4>(0h8), UInt<1>(0h0)) node _write_port_busy_T_8 = eq(ex_ctrl.typeTagOut, UInt<1>(0h0)) node _write_port_busy_T_9 = and(ex_ctrl.fma, _write_port_busy_T_8) node _write_port_busy_T_10 = mux(_write_port_busy_T_9, UInt<3>(0h4), UInt<1>(0h0)) node _write_port_busy_T_11 = or(_write_port_busy_T, _write_port_busy_T_1) node _write_port_busy_T_12 = or(_write_port_busy_T_11, _write_port_busy_T_4) node _write_port_busy_T_13 = or(_write_port_busy_T_12, _write_port_busy_T_7) node _write_port_busy_T_14 = or(_write_port_busy_T_13, _write_port_busy_T_10) node _write_port_busy_T_15 = and(memLatencyMask, _write_port_busy_T_14) node _write_port_busy_T_16 = orr(_write_port_busy_T_15) node _write_port_busy_T_17 = and(mem_wen, _write_port_busy_T_16) node _write_port_busy_T_18 = mux(ex_ctrl.fastpipe, UInt<3>(0h4), UInt<1>(0h0)) node _write_port_busy_T_19 = mux(ex_ctrl.fromint, UInt<3>(0h4), UInt<1>(0h0)) node _write_port_busy_T_20 = eq(ex_ctrl.typeTagOut, UInt<1>(0h1)) node _write_port_busy_T_21 = and(ex_ctrl.fma, _write_port_busy_T_20) node _write_port_busy_T_22 = mux(_write_port_busy_T_21, UInt<4>(0h8), UInt<1>(0h0)) node _write_port_busy_T_23 = eq(ex_ctrl.typeTagOut, UInt<2>(0h2)) node _write_port_busy_T_24 = and(ex_ctrl.fma, _write_port_busy_T_23) node _write_port_busy_T_25 = mux(_write_port_busy_T_24, UInt<5>(0h10), UInt<1>(0h0)) node _write_port_busy_T_26 = eq(ex_ctrl.typeTagOut, UInt<1>(0h0)) node _write_port_busy_T_27 = and(ex_ctrl.fma, _write_port_busy_T_26) node _write_port_busy_T_28 = mux(_write_port_busy_T_27, UInt<4>(0h8), UInt<1>(0h0)) node _write_port_busy_T_29 = or(_write_port_busy_T_18, _write_port_busy_T_19) node _write_port_busy_T_30 = or(_write_port_busy_T_29, _write_port_busy_T_22) node _write_port_busy_T_31 = or(_write_port_busy_T_30, _write_port_busy_T_25) node _write_port_busy_T_32 = or(_write_port_busy_T_31, _write_port_busy_T_28) node _write_port_busy_T_33 = and(wen, _write_port_busy_T_32) node _write_port_busy_T_34 = orr(_write_port_busy_T_33) node _write_port_busy_T_35 = or(_write_port_busy_T_17, _write_port_busy_T_34) reg write_port_busy : UInt<1>, clock when req_valid : connect write_port_busy, _write_port_busy_T_35 node _T_10 = and(mem_reg_valid, write_port_busy) node _T_11 = bits(wen, 1, 1) when _T_11 : connect wbInfo[0], wbInfo[1] node _T_12 = bits(wen, 2, 2) when _T_12 : connect wbInfo[1], wbInfo[2] node _wen_T = shr(wen, 1) connect wen, _wen_T when mem_wen : node _T_13 = eq(killm, UInt<1>(0h0)) when _T_13 : node _wen_T_1 = shr(wen, 1) node _wen_T_2 = or(_wen_T_1, memLatencyMask) connect wen, _wen_T_2 node _T_14 = eq(write_port_busy, UInt<1>(0h0)) node _T_15 = bits(memLatencyMask, 0, 0) node _T_16 = and(_T_14, _T_15) when _T_16 : connect wbInfo[0].cp, mem_cp_valid connect wbInfo[0].typeTag, mem_ctrl.typeTagOut node _wbInfo_0_pipeid_T = mux(mem_ctrl.fastpipe, UInt<1>(0h0), UInt<1>(0h0)) node _wbInfo_0_pipeid_T_1 = mux(mem_ctrl.fromint, UInt<1>(0h1), UInt<1>(0h0)) node _wbInfo_0_pipeid_T_2 = eq(mem_ctrl.typeTagOut, UInt<1>(0h1)) node _wbInfo_0_pipeid_T_3 = and(mem_ctrl.fma, _wbInfo_0_pipeid_T_2) node _wbInfo_0_pipeid_T_4 = mux(_wbInfo_0_pipeid_T_3, UInt<2>(0h2), UInt<1>(0h0)) node _wbInfo_0_pipeid_T_5 = eq(mem_ctrl.typeTagOut, UInt<2>(0h2)) node _wbInfo_0_pipeid_T_6 = and(mem_ctrl.fma, _wbInfo_0_pipeid_T_5) node _wbInfo_0_pipeid_T_7 = mux(_wbInfo_0_pipeid_T_6, UInt<2>(0h3), UInt<1>(0h0)) node _wbInfo_0_pipeid_T_8 = eq(mem_ctrl.typeTagOut, UInt<1>(0h0)) node _wbInfo_0_pipeid_T_9 = and(mem_ctrl.fma, _wbInfo_0_pipeid_T_8) node _wbInfo_0_pipeid_T_10 = mux(_wbInfo_0_pipeid_T_9, UInt<3>(0h4), UInt<1>(0h0)) node _wbInfo_0_pipeid_T_11 = or(_wbInfo_0_pipeid_T, _wbInfo_0_pipeid_T_1) node _wbInfo_0_pipeid_T_12 = or(_wbInfo_0_pipeid_T_11, _wbInfo_0_pipeid_T_4) node _wbInfo_0_pipeid_T_13 = or(_wbInfo_0_pipeid_T_12, _wbInfo_0_pipeid_T_7) node _wbInfo_0_pipeid_T_14 = or(_wbInfo_0_pipeid_T_13, _wbInfo_0_pipeid_T_10) connect wbInfo[0].pipeid, _wbInfo_0_pipeid_T_14 node _wbInfo_0_rd_T = bits(mem_reg_inst, 11, 7) connect wbInfo[0].rd, _wbInfo_0_rd_T node _T_17 = eq(write_port_busy, UInt<1>(0h0)) node _T_18 = bits(memLatencyMask, 1, 1) node _T_19 = and(_T_17, _T_18) when _T_19 : connect wbInfo[1].cp, mem_cp_valid connect wbInfo[1].typeTag, mem_ctrl.typeTagOut node _wbInfo_1_pipeid_T = mux(mem_ctrl.fastpipe, UInt<1>(0h0), UInt<1>(0h0)) node _wbInfo_1_pipeid_T_1 = mux(mem_ctrl.fromint, UInt<1>(0h1), UInt<1>(0h0)) node _wbInfo_1_pipeid_T_2 = eq(mem_ctrl.typeTagOut, UInt<1>(0h1)) node _wbInfo_1_pipeid_T_3 = and(mem_ctrl.fma, _wbInfo_1_pipeid_T_2) node _wbInfo_1_pipeid_T_4 = mux(_wbInfo_1_pipeid_T_3, UInt<2>(0h2), UInt<1>(0h0)) node _wbInfo_1_pipeid_T_5 = eq(mem_ctrl.typeTagOut, UInt<2>(0h2)) node _wbInfo_1_pipeid_T_6 = and(mem_ctrl.fma, _wbInfo_1_pipeid_T_5) node _wbInfo_1_pipeid_T_7 = mux(_wbInfo_1_pipeid_T_6, UInt<2>(0h3), UInt<1>(0h0)) node _wbInfo_1_pipeid_T_8 = eq(mem_ctrl.typeTagOut, UInt<1>(0h0)) node _wbInfo_1_pipeid_T_9 = and(mem_ctrl.fma, _wbInfo_1_pipeid_T_8) node _wbInfo_1_pipeid_T_10 = mux(_wbInfo_1_pipeid_T_9, UInt<3>(0h4), UInt<1>(0h0)) node _wbInfo_1_pipeid_T_11 = or(_wbInfo_1_pipeid_T, _wbInfo_1_pipeid_T_1) node _wbInfo_1_pipeid_T_12 = or(_wbInfo_1_pipeid_T_11, _wbInfo_1_pipeid_T_4) node _wbInfo_1_pipeid_T_13 = or(_wbInfo_1_pipeid_T_12, _wbInfo_1_pipeid_T_7) node _wbInfo_1_pipeid_T_14 = or(_wbInfo_1_pipeid_T_13, _wbInfo_1_pipeid_T_10) connect wbInfo[1].pipeid, _wbInfo_1_pipeid_T_14 node _wbInfo_1_rd_T = bits(mem_reg_inst, 11, 7) connect wbInfo[1].rd, _wbInfo_1_rd_T node _T_20 = eq(write_port_busy, UInt<1>(0h0)) node _T_21 = bits(memLatencyMask, 2, 2) node _T_22 = and(_T_20, _T_21) when _T_22 : connect wbInfo[2].cp, mem_cp_valid connect wbInfo[2].typeTag, mem_ctrl.typeTagOut node _wbInfo_2_pipeid_T = mux(mem_ctrl.fastpipe, UInt<1>(0h0), UInt<1>(0h0)) node _wbInfo_2_pipeid_T_1 = mux(mem_ctrl.fromint, UInt<1>(0h1), UInt<1>(0h0)) node _wbInfo_2_pipeid_T_2 = eq(mem_ctrl.typeTagOut, UInt<1>(0h1)) node _wbInfo_2_pipeid_T_3 = and(mem_ctrl.fma, _wbInfo_2_pipeid_T_2) node _wbInfo_2_pipeid_T_4 = mux(_wbInfo_2_pipeid_T_3, UInt<2>(0h2), UInt<1>(0h0)) node _wbInfo_2_pipeid_T_5 = eq(mem_ctrl.typeTagOut, UInt<2>(0h2)) node _wbInfo_2_pipeid_T_6 = and(mem_ctrl.fma, _wbInfo_2_pipeid_T_5) node _wbInfo_2_pipeid_T_7 = mux(_wbInfo_2_pipeid_T_6, UInt<2>(0h3), UInt<1>(0h0)) node _wbInfo_2_pipeid_T_8 = eq(mem_ctrl.typeTagOut, UInt<1>(0h0)) node _wbInfo_2_pipeid_T_9 = and(mem_ctrl.fma, _wbInfo_2_pipeid_T_8) node _wbInfo_2_pipeid_T_10 = mux(_wbInfo_2_pipeid_T_9, UInt<3>(0h4), UInt<1>(0h0)) node _wbInfo_2_pipeid_T_11 = or(_wbInfo_2_pipeid_T, _wbInfo_2_pipeid_T_1) node _wbInfo_2_pipeid_T_12 = or(_wbInfo_2_pipeid_T_11, _wbInfo_2_pipeid_T_4) node _wbInfo_2_pipeid_T_13 = or(_wbInfo_2_pipeid_T_12, _wbInfo_2_pipeid_T_7) node _wbInfo_2_pipeid_T_14 = or(_wbInfo_2_pipeid_T_13, _wbInfo_2_pipeid_T_10) connect wbInfo[2].pipeid, _wbInfo_2_pipeid_T_14 node _wbInfo_2_rd_T = bits(mem_reg_inst, 11, 7) connect wbInfo[2].rd, _wbInfo_2_rd_T node waddr = mux(divSqrt_wen, divSqrt_waddr, wbInfo[0].rd) node wb_cp = mux(divSqrt_wen, divSqrt_cp, wbInfo[0].cp) node wtypeTag = mux(divSqrt_wen, divSqrt_typeTag, wbInfo[0].typeTag) node _wdata_T_39 = eq(wbInfo[0].pipeid, UInt<1>(0h1)) node _wdata_T_40 = mux(_wdata_T_39, ifpu.io.out.bits.data, fpmu.io.out.bits.data) node _wdata_T_41 = eq(wbInfo[0].pipeid, UInt<2>(0h2)) node _wdata_T_42 = mux(_wdata_T_41, sfma.io.out.bits.data, _wdata_T_40) node _wdata_T_43 = eq(wbInfo[0].pipeid, UInt<2>(0h3)) node _wdata_T_44 = mux(_wdata_T_43, dfma.io.out.bits.data, _wdata_T_42) node _wdata_T_45 = eq(wbInfo[0].pipeid, UInt<3>(0h4)) node _wdata_T_46 = mux(_wdata_T_45, hfma.io.out.bits.data, _wdata_T_44) node _wdata_T_47 = eq(wbInfo[0].pipeid, UInt<3>(0h5)) node _wdata_T_48 = mux(_wdata_T_47, hfma.io.out.bits.data, _wdata_T_46) node _wdata_T_49 = eq(wbInfo[0].pipeid, UInt<3>(0h6)) node _wdata_T_50 = mux(_wdata_T_49, hfma.io.out.bits.data, _wdata_T_48) node _wdata_T_51 = eq(wbInfo[0].pipeid, UInt<3>(0h7)) node _wdata_T_52 = mux(_wdata_T_51, hfma.io.out.bits.data, _wdata_T_50) node _wdata_T_53 = mux(divSqrt_wen, divSqrt_wdata, _wdata_T_52) node _wdata_opts_bigger_swizzledNaN_T = andr(UInt<7>(0h7f)) node _wdata_opts_bigger_swizzledNaN_T_1 = bits(_wdata_T_53, 15, 15) node _wdata_opts_bigger_swizzledNaN_T_2 = bits(_wdata_T_53, 16, 16) node _wdata_opts_bigger_swizzledNaN_T_3 = bits(_wdata_T_53, 14, 0) node wdata_opts_bigger_swizzledNaN_lo_hi = cat(UInt<7>(0h7f), _wdata_opts_bigger_swizzledNaN_T_2) node wdata_opts_bigger_swizzledNaN_lo = cat(wdata_opts_bigger_swizzledNaN_lo_hi, _wdata_opts_bigger_swizzledNaN_T_3) node wdata_opts_bigger_swizzledNaN_hi_lo = cat(UInt<4>(0hf), _wdata_opts_bigger_swizzledNaN_T_1) node wdata_opts_bigger_swizzledNaN_hi_hi = cat(UInt<4>(0hf), _wdata_opts_bigger_swizzledNaN_T) node wdata_opts_bigger_swizzledNaN_hi = cat(wdata_opts_bigger_swizzledNaN_hi_hi, wdata_opts_bigger_swizzledNaN_hi_lo) node wdata_opts_bigger_swizzledNaN = cat(wdata_opts_bigger_swizzledNaN_hi, wdata_opts_bigger_swizzledNaN_lo) node _wdata_opts_bigger_T = andr(UInt<3>(0h7)) node wdata_opts_bigger = mux(_wdata_opts_bigger_T, wdata_opts_bigger_swizzledNaN, UInt<33>(0h1ffffffff)) node wdata_opts_0 = or(wdata_opts_bigger, UInt<65>(0h1fffffffe00000000)) node _wdata_opts_bigger_swizzledNaN_T_4 = andr(UInt<20>(0hfffff)) node _wdata_opts_bigger_swizzledNaN_T_5 = bits(_wdata_T_53, 31, 31) node _wdata_opts_bigger_swizzledNaN_T_6 = bits(_wdata_T_53, 32, 32) node _wdata_opts_bigger_swizzledNaN_T_7 = bits(_wdata_T_53, 30, 0) node wdata_opts_bigger_swizzledNaN_lo_hi_1 = cat(UInt<20>(0hfffff), _wdata_opts_bigger_swizzledNaN_T_6) node wdata_opts_bigger_swizzledNaN_lo_1 = cat(wdata_opts_bigger_swizzledNaN_lo_hi_1, _wdata_opts_bigger_swizzledNaN_T_7) node wdata_opts_bigger_swizzledNaN_hi_lo_1 = cat(UInt<7>(0h7f), _wdata_opts_bigger_swizzledNaN_T_5) node wdata_opts_bigger_swizzledNaN_hi_hi_1 = cat(UInt<4>(0hf), _wdata_opts_bigger_swizzledNaN_T_4) node wdata_opts_bigger_swizzledNaN_hi_1 = cat(wdata_opts_bigger_swizzledNaN_hi_hi_1, wdata_opts_bigger_swizzledNaN_hi_lo_1) node wdata_opts_bigger_swizzledNaN_1 = cat(wdata_opts_bigger_swizzledNaN_hi_1, wdata_opts_bigger_swizzledNaN_lo_1) node _wdata_opts_bigger_T_1 = andr(UInt<3>(0h7)) node wdata_opts_bigger_1 = mux(_wdata_opts_bigger_T_1, wdata_opts_bigger_swizzledNaN_1, UInt<65>(0h1ffffffffffffffff)) node wdata_opts_1 = or(wdata_opts_bigger_1, UInt<1>(0h0)) node _wdata_T_54 = eq(wtypeTag, UInt<1>(0h1)) node _wdata_T_55 = mux(_wdata_T_54, wdata_opts_1, wdata_opts_0) node _wdata_T_56 = eq(wtypeTag, UInt<2>(0h2)) node _wdata_T_57 = mux(_wdata_T_56, _wdata_T_53, _wdata_T_55) node _wdata_T_58 = eq(wtypeTag, UInt<2>(0h3)) node wdata_1 = mux(_wdata_T_58, _wdata_T_53, _wdata_T_57) node _wexc_T = eq(wbInfo[0].pipeid, UInt<1>(0h1)) node _wexc_T_1 = mux(_wexc_T, ifpu.io.out.bits.exc, fpmu.io.out.bits.exc) node _wexc_T_2 = eq(wbInfo[0].pipeid, UInt<2>(0h2)) node _wexc_T_3 = mux(_wexc_T_2, sfma.io.out.bits.exc, _wexc_T_1) node _wexc_T_4 = eq(wbInfo[0].pipeid, UInt<2>(0h3)) node _wexc_T_5 = mux(_wexc_T_4, dfma.io.out.bits.exc, _wexc_T_3) node _wexc_T_6 = eq(wbInfo[0].pipeid, UInt<3>(0h4)) node _wexc_T_7 = mux(_wexc_T_6, hfma.io.out.bits.exc, _wexc_T_5) node _wexc_T_8 = eq(wbInfo[0].pipeid, UInt<3>(0h5)) node _wexc_T_9 = mux(_wexc_T_8, hfma.io.out.bits.exc, _wexc_T_7) node _wexc_T_10 = eq(wbInfo[0].pipeid, UInt<3>(0h6)) node _wexc_T_11 = mux(_wexc_T_10, hfma.io.out.bits.exc, _wexc_T_9) node _wexc_T_12 = eq(wbInfo[0].pipeid, UInt<3>(0h7)) node wexc = mux(_wexc_T_12, hfma.io.out.bits.exc, _wexc_T_11) node _T_23 = eq(wbInfo[0].cp, UInt<1>(0h0)) node _T_24 = bits(wen, 0, 0) node _T_25 = and(_T_23, _T_24) node _T_26 = or(_T_25, divSqrt_wen) when _T_26 : node _unswizzled_T_3 = bits(wdata_1, 31, 31) node _unswizzled_T_4 = bits(wdata_1, 52, 52) node _unswizzled_T_5 = bits(wdata_1, 30, 0) node unswizzled_hi_1 = cat(_unswizzled_T_3, _unswizzled_T_4) node unswizzled_1 = cat(unswizzled_hi_1, _unswizzled_T_5) node _prevOK_T_4 = bits(wdata_1, 64, 60) node _prevOK_T_5 = andr(_prevOK_T_4) node _prevOK_T_6 = eq(_prevOK_T_5, UInt<1>(0h0)) node _prevOK_unswizzled_T_3 = bits(unswizzled_1, 15, 15) node _prevOK_unswizzled_T_4 = bits(unswizzled_1, 23, 23) node _prevOK_unswizzled_T_5 = bits(unswizzled_1, 14, 0) node prevOK_unswizzled_hi_1 = cat(_prevOK_unswizzled_T_3, _prevOK_unswizzled_T_4) node prevOK_unswizzled_1 = cat(prevOK_unswizzled_hi_1, _prevOK_unswizzled_T_5) node _prevOK_prevOK_T_3 = bits(unswizzled_1, 32, 28) node _prevOK_prevOK_T_4 = andr(_prevOK_prevOK_T_3) node _prevOK_prevOK_T_5 = eq(_prevOK_prevOK_T_4, UInt<1>(0h0)) node prevOK_prevOK_1 = or(_prevOK_prevOK_T_5, UInt<1>(0h1)) node _prevOK_curOK_T_7 = bits(unswizzled_1, 31, 29) node _prevOK_curOK_T_8 = andr(_prevOK_curOK_T_7) node _prevOK_curOK_T_9 = eq(_prevOK_curOK_T_8, UInt<1>(0h0)) node _prevOK_curOK_T_10 = bits(unswizzled_1, 28, 28) node _prevOK_curOK_T_11 = bits(unswizzled_1, 22, 16) node _prevOK_curOK_T_12 = andr(_prevOK_curOK_T_11) node _prevOK_curOK_T_13 = eq(_prevOK_curOK_T_10, _prevOK_curOK_T_12) node prevOK_curOK_1 = or(_prevOK_curOK_T_9, _prevOK_curOK_T_13) node _prevOK_T_7 = and(prevOK_prevOK_1, prevOK_curOK_1) node prevOK_1 = or(_prevOK_T_6, _prevOK_T_7) node _curOK_T_7 = bits(wdata_1, 63, 61) node _curOK_T_8 = andr(_curOK_T_7) node _curOK_T_9 = eq(_curOK_T_8, UInt<1>(0h0)) node _curOK_T_10 = bits(wdata_1, 60, 60) node _curOK_T_11 = bits(wdata_1, 51, 32) node _curOK_T_12 = andr(_curOK_T_11) node _curOK_T_13 = eq(_curOK_T_10, _curOK_T_12) node curOK_1 = or(_curOK_T_9, _curOK_T_13) node _T_27 = and(prevOK_1, curOK_1) node _T_28 = asUInt(reset) node _T_29 = eq(_T_28, UInt<1>(0h0)) when _T_29 : node _T_30 = eq(_T_27, UInt<1>(0h0)) when _T_30 : printf(clock, UInt<1>(0h1), "Assertion failed\n at FPU.scala:969 assert(consistent(wdata))\n") : printf_1 assert(clock, _T_27, UInt<1>(0h1), "") : assert_1 infer mport MPORT_1 = regfile[waddr], clock connect MPORT_1, wdata_1 connect frfWriteBundle_1.wrdst, waddr connect frfWriteBundle_1.wrenf, UInt<1>(0h1) node frfWriteBundle_1_wrdata_unrecoded_rawIn_exp = bits(wdata_1, 63, 52) node _frfWriteBundle_1_wrdata_unrecoded_rawIn_isZero_T = bits(frfWriteBundle_1_wrdata_unrecoded_rawIn_exp, 11, 9) node frfWriteBundle_1_wrdata_unrecoded_rawIn_isZero = eq(_frfWriteBundle_1_wrdata_unrecoded_rawIn_isZero_T, UInt<1>(0h0)) node _frfWriteBundle_1_wrdata_unrecoded_rawIn_isSpecial_T = bits(frfWriteBundle_1_wrdata_unrecoded_rawIn_exp, 11, 10) node frfWriteBundle_1_wrdata_unrecoded_rawIn_isSpecial = eq(_frfWriteBundle_1_wrdata_unrecoded_rawIn_isSpecial_T, UInt<2>(0h3)) wire frfWriteBundle_1_wrdata_unrecoded_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} node _frfWriteBundle_1_wrdata_unrecoded_rawIn_out_isNaN_T = bits(frfWriteBundle_1_wrdata_unrecoded_rawIn_exp, 9, 9) node _frfWriteBundle_1_wrdata_unrecoded_rawIn_out_isNaN_T_1 = and(frfWriteBundle_1_wrdata_unrecoded_rawIn_isSpecial, _frfWriteBundle_1_wrdata_unrecoded_rawIn_out_isNaN_T) connect frfWriteBundle_1_wrdata_unrecoded_rawIn.isNaN, _frfWriteBundle_1_wrdata_unrecoded_rawIn_out_isNaN_T_1 node _frfWriteBundle_1_wrdata_unrecoded_rawIn_out_isInf_T = bits(frfWriteBundle_1_wrdata_unrecoded_rawIn_exp, 9, 9) node _frfWriteBundle_1_wrdata_unrecoded_rawIn_out_isInf_T_1 = eq(_frfWriteBundle_1_wrdata_unrecoded_rawIn_out_isInf_T, UInt<1>(0h0)) node _frfWriteBundle_1_wrdata_unrecoded_rawIn_out_isInf_T_2 = and(frfWriteBundle_1_wrdata_unrecoded_rawIn_isSpecial, _frfWriteBundle_1_wrdata_unrecoded_rawIn_out_isInf_T_1) connect frfWriteBundle_1_wrdata_unrecoded_rawIn.isInf, _frfWriteBundle_1_wrdata_unrecoded_rawIn_out_isInf_T_2 connect frfWriteBundle_1_wrdata_unrecoded_rawIn.isZero, frfWriteBundle_1_wrdata_unrecoded_rawIn_isZero node _frfWriteBundle_1_wrdata_unrecoded_rawIn_out_sign_T = bits(wdata_1, 64, 64) connect frfWriteBundle_1_wrdata_unrecoded_rawIn.sign, _frfWriteBundle_1_wrdata_unrecoded_rawIn_out_sign_T node _frfWriteBundle_1_wrdata_unrecoded_rawIn_out_sExp_T = cvt(frfWriteBundle_1_wrdata_unrecoded_rawIn_exp) connect frfWriteBundle_1_wrdata_unrecoded_rawIn.sExp, _frfWriteBundle_1_wrdata_unrecoded_rawIn_out_sExp_T node _frfWriteBundle_1_wrdata_unrecoded_rawIn_out_sig_T = eq(frfWriteBundle_1_wrdata_unrecoded_rawIn_isZero, UInt<1>(0h0)) node _frfWriteBundle_1_wrdata_unrecoded_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _frfWriteBundle_1_wrdata_unrecoded_rawIn_out_sig_T) node _frfWriteBundle_1_wrdata_unrecoded_rawIn_out_sig_T_2 = bits(wdata_1, 51, 0) node _frfWriteBundle_1_wrdata_unrecoded_rawIn_out_sig_T_3 = cat(_frfWriteBundle_1_wrdata_unrecoded_rawIn_out_sig_T_1, _frfWriteBundle_1_wrdata_unrecoded_rawIn_out_sig_T_2) connect frfWriteBundle_1_wrdata_unrecoded_rawIn.sig, _frfWriteBundle_1_wrdata_unrecoded_rawIn_out_sig_T_3 node frfWriteBundle_1_wrdata_unrecoded_isSubnormal = lt(frfWriteBundle_1_wrdata_unrecoded_rawIn.sExp, asSInt(UInt<12>(0h402))) node _frfWriteBundle_1_wrdata_unrecoded_denormShiftDist_T = bits(frfWriteBundle_1_wrdata_unrecoded_rawIn.sExp, 5, 0) node _frfWriteBundle_1_wrdata_unrecoded_denormShiftDist_T_1 = sub(UInt<1>(0h1), _frfWriteBundle_1_wrdata_unrecoded_denormShiftDist_T) node frfWriteBundle_1_wrdata_unrecoded_denormShiftDist = tail(_frfWriteBundle_1_wrdata_unrecoded_denormShiftDist_T_1, 1) node _frfWriteBundle_1_wrdata_unrecoded_denormFract_T = shr(frfWriteBundle_1_wrdata_unrecoded_rawIn.sig, 1) node _frfWriteBundle_1_wrdata_unrecoded_denormFract_T_1 = dshr(_frfWriteBundle_1_wrdata_unrecoded_denormFract_T, frfWriteBundle_1_wrdata_unrecoded_denormShiftDist) node frfWriteBundle_1_wrdata_unrecoded_denormFract = bits(_frfWriteBundle_1_wrdata_unrecoded_denormFract_T_1, 51, 0) node _frfWriteBundle_1_wrdata_unrecoded_expOut_T = bits(frfWriteBundle_1_wrdata_unrecoded_rawIn.sExp, 10, 0) node _frfWriteBundle_1_wrdata_unrecoded_expOut_T_1 = sub(_frfWriteBundle_1_wrdata_unrecoded_expOut_T, UInt<11>(0h401)) node _frfWriteBundle_1_wrdata_unrecoded_expOut_T_2 = tail(_frfWriteBundle_1_wrdata_unrecoded_expOut_T_1, 1) node _frfWriteBundle_1_wrdata_unrecoded_expOut_T_3 = mux(frfWriteBundle_1_wrdata_unrecoded_isSubnormal, UInt<1>(0h0), _frfWriteBundle_1_wrdata_unrecoded_expOut_T_2) node _frfWriteBundle_1_wrdata_unrecoded_expOut_T_4 = or(frfWriteBundle_1_wrdata_unrecoded_rawIn.isNaN, frfWriteBundle_1_wrdata_unrecoded_rawIn.isInf) node _frfWriteBundle_1_wrdata_unrecoded_expOut_T_5 = mux(_frfWriteBundle_1_wrdata_unrecoded_expOut_T_4, UInt<11>(0h7ff), UInt<11>(0h0)) node frfWriteBundle_1_wrdata_unrecoded_expOut = or(_frfWriteBundle_1_wrdata_unrecoded_expOut_T_3, _frfWriteBundle_1_wrdata_unrecoded_expOut_T_5) node _frfWriteBundle_1_wrdata_unrecoded_fractOut_T = bits(frfWriteBundle_1_wrdata_unrecoded_rawIn.sig, 51, 0) node _frfWriteBundle_1_wrdata_unrecoded_fractOut_T_1 = mux(frfWriteBundle_1_wrdata_unrecoded_rawIn.isInf, UInt<1>(0h0), _frfWriteBundle_1_wrdata_unrecoded_fractOut_T) node frfWriteBundle_1_wrdata_unrecoded_fractOut = mux(frfWriteBundle_1_wrdata_unrecoded_isSubnormal, frfWriteBundle_1_wrdata_unrecoded_denormFract, _frfWriteBundle_1_wrdata_unrecoded_fractOut_T_1) node frfWriteBundle_1_wrdata_unrecoded_hi = cat(frfWriteBundle_1_wrdata_unrecoded_rawIn.sign, frfWriteBundle_1_wrdata_unrecoded_expOut) node frfWriteBundle_1_wrdata_unrecoded = cat(frfWriteBundle_1_wrdata_unrecoded_hi, frfWriteBundle_1_wrdata_unrecoded_fractOut) node _frfWriteBundle_1_wrdata_prevRecoded_T = bits(wdata_1, 31, 31) node _frfWriteBundle_1_wrdata_prevRecoded_T_1 = bits(wdata_1, 52, 52) node _frfWriteBundle_1_wrdata_prevRecoded_T_2 = bits(wdata_1, 30, 0) node frfWriteBundle_1_wrdata_prevRecoded_hi = cat(_frfWriteBundle_1_wrdata_prevRecoded_T, _frfWriteBundle_1_wrdata_prevRecoded_T_1) node frfWriteBundle_1_wrdata_prevRecoded = cat(frfWriteBundle_1_wrdata_prevRecoded_hi, _frfWriteBundle_1_wrdata_prevRecoded_T_2) node frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn_exp = bits(frfWriteBundle_1_wrdata_prevRecoded, 31, 23) node _frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn_isZero_T = bits(frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn_exp, 8, 6) node frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn_isZero = eq(_frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn_isZero_T, UInt<1>(0h0)) node _frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn_isSpecial_T = bits(frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn_exp, 8, 7) node frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn_isSpecial = eq(_frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn_isSpecial_T, UInt<2>(0h3)) wire frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn_out_isNaN_T = bits(frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn_exp, 6, 6) node _frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1 = and(frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn_isSpecial, _frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn_out_isNaN_T) connect frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn.isNaN, _frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1 node _frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn_out_isInf_T = bits(frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn_exp, 6, 6) node _frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn_out_isInf_T_1 = eq(_frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn_out_isInf_T, UInt<1>(0h0)) node _frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2 = and(frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn_isSpecial, _frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn_out_isInf_T_1) connect frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn.isInf, _frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2 connect frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn.isZero, frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn_isZero node _frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn_out_sign_T = bits(frfWriteBundle_1_wrdata_prevRecoded, 32, 32) connect frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn.sign, _frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn_out_sign_T node _frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn_out_sExp_T = cvt(frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn_exp) connect frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn.sExp, _frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn_out_sExp_T node _frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn_out_sig_T = eq(frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn_isZero, UInt<1>(0h0)) node _frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn_out_sig_T) node _frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn_out_sig_T_2 = bits(frfWriteBundle_1_wrdata_prevRecoded, 22, 0) node _frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn_out_sig_T_3 = cat(_frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn_out_sig_T_1, _frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn_out_sig_T_2) connect frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn.sig, _frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn_out_sig_T_3 node frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_isSubnormal = lt(frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn.sExp, asSInt(UInt<9>(0h82))) node _frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_denormShiftDist_T = bits(frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn.sExp, 4, 0) node _frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_denormShiftDist_T_1 = sub(UInt<1>(0h1), _frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_denormShiftDist_T) node frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_denormShiftDist = tail(_frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_denormShiftDist_T_1, 1) node _frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_denormFract_T = shr(frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn.sig, 1) node _frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_denormFract_T_1 = dshr(_frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_denormFract_T, frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_denormShiftDist) node frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_denormFract = bits(_frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_denormFract_T_1, 22, 0) node _frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_expOut_T = bits(frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn.sExp, 7, 0) node _frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_expOut_T_1 = sub(_frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_expOut_T, UInt<8>(0h81)) node _frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_expOut_T_2 = tail(_frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_expOut_T_1, 1) node _frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_expOut_T_3 = mux(frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_isSubnormal, UInt<1>(0h0), _frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_expOut_T_2) node _frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_expOut_T_4 = or(frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn.isNaN, frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn.isInf) node _frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_expOut_T_5 = mux(_frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_expOut_T_4, UInt<8>(0hff), UInt<8>(0h0)) node frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_expOut = or(_frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_expOut_T_3, _frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_expOut_T_5) node _frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_fractOut_T = bits(frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn.sig, 22, 0) node _frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_fractOut_T_1 = mux(frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn.isInf, UInt<1>(0h0), _frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_fractOut_T) node frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_fractOut = mux(frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_isSubnormal, frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_denormFract, _frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_fractOut_T_1) node frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_hi = cat(frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn.sign, frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_expOut) node frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded = cat(frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_hi, frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_fractOut) node _frfWriteBundle_1_wrdata_prevUnrecoded_prevRecoded_T = bits(frfWriteBundle_1_wrdata_prevRecoded, 15, 15) node _frfWriteBundle_1_wrdata_prevUnrecoded_prevRecoded_T_1 = bits(frfWriteBundle_1_wrdata_prevRecoded, 23, 23) node _frfWriteBundle_1_wrdata_prevUnrecoded_prevRecoded_T_2 = bits(frfWriteBundle_1_wrdata_prevRecoded, 14, 0) node frfWriteBundle_1_wrdata_prevUnrecoded_prevRecoded_hi = cat(_frfWriteBundle_1_wrdata_prevUnrecoded_prevRecoded_T, _frfWriteBundle_1_wrdata_prevUnrecoded_prevRecoded_T_1) node frfWriteBundle_1_wrdata_prevUnrecoded_prevRecoded = cat(frfWriteBundle_1_wrdata_prevUnrecoded_prevRecoded_hi, _frfWriteBundle_1_wrdata_prevUnrecoded_prevRecoded_T_2) node frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn_exp = bits(frfWriteBundle_1_wrdata_prevUnrecoded_prevRecoded, 15, 10) node _frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isZero_T = bits(frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn_exp, 5, 3) node frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isZero = eq(_frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isZero_T, UInt<1>(0h0)) node _frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T = bits(frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn_exp, 5, 4) node frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isSpecial = eq(_frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T, UInt<2>(0h3)) wire frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<12>} node _frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T = bits(frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn_exp, 3, 3) node _frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1 = and(frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isSpecial, _frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T) connect frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn.isNaN, _frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1 node _frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T = bits(frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn_exp, 3, 3) node _frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_1 = eq(_frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T, UInt<1>(0h0)) node _frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2 = and(frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isSpecial, _frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_1) connect frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn.isInf, _frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2 connect frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn.isZero, frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isZero node _frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T = bits(frfWriteBundle_1_wrdata_prevUnrecoded_prevRecoded, 16, 16) connect frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn.sign, _frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T node _frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T = cvt(frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn_exp) connect frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn.sExp, _frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T node _frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T = eq(frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isZero, UInt<1>(0h0)) node _frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T) node _frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_2 = bits(frfWriteBundle_1_wrdata_prevUnrecoded_prevRecoded, 9, 0) node _frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3 = cat(_frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_1, _frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_2) connect frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn.sig, _frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3 node frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_isSubnormal = lt(frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn.sExp, asSInt(UInt<6>(0h12))) node _frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_denormShiftDist_T = bits(frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn.sExp, 3, 0) node _frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_denormShiftDist_T_1 = sub(UInt<1>(0h1), _frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_denormShiftDist_T) node frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_denormShiftDist = tail(_frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_denormShiftDist_T_1, 1) node _frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_denormFract_T = shr(frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn.sig, 1) node _frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_denormFract_T_1 = dshr(_frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_denormFract_T, frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_denormShiftDist) node frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_denormFract = bits(_frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_denormFract_T_1, 9, 0) node _frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_expOut_T = bits(frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn.sExp, 4, 0) node _frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_expOut_T_1 = sub(_frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_expOut_T, UInt<5>(0h11)) node _frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_expOut_T_2 = tail(_frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_expOut_T_1, 1) node _frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_expOut_T_3 = mux(frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_isSubnormal, UInt<1>(0h0), _frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_expOut_T_2) node _frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_expOut_T_4 = or(frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn.isNaN, frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn.isInf) node _frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_expOut_T_5 = mux(_frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_expOut_T_4, UInt<5>(0h1f), UInt<5>(0h0)) node frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_expOut = or(_frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_expOut_T_3, _frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_expOut_T_5) node _frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_fractOut_T = bits(frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn.sig, 9, 0) node _frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_fractOut_T_1 = mux(frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn.isInf, UInt<1>(0h0), _frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_fractOut_T) node frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_fractOut = mux(frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_isSubnormal, frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_denormFract, _frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_fractOut_T_1) node frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_hi = cat(frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn.sign, frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_expOut) node frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded = cat(frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_hi, frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_fractOut) node _frfWriteBundle_1_wrdata_prevUnrecoded_T = shr(frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded, 16) node _frfWriteBundle_1_wrdata_prevUnrecoded_T_1 = bits(frfWriteBundle_1_wrdata_prevRecoded, 31, 29) node _frfWriteBundle_1_wrdata_prevUnrecoded_T_2 = andr(_frfWriteBundle_1_wrdata_prevUnrecoded_T_1) node _frfWriteBundle_1_wrdata_prevUnrecoded_T_3 = bits(frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded, 15, 0) node _frfWriteBundle_1_wrdata_prevUnrecoded_T_4 = mux(_frfWriteBundle_1_wrdata_prevUnrecoded_T_2, frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded, _frfWriteBundle_1_wrdata_prevUnrecoded_T_3) node frfWriteBundle_1_wrdata_prevUnrecoded = cat(_frfWriteBundle_1_wrdata_prevUnrecoded_T, _frfWriteBundle_1_wrdata_prevUnrecoded_T_4) node _frfWriteBundle_1_wrdata_T = shr(frfWriteBundle_1_wrdata_unrecoded, 32) node _frfWriteBundle_1_wrdata_T_1 = bits(wdata_1, 63, 61) node _frfWriteBundle_1_wrdata_T_2 = andr(_frfWriteBundle_1_wrdata_T_1) node _frfWriteBundle_1_wrdata_T_3 = bits(frfWriteBundle_1_wrdata_unrecoded, 31, 0) node _frfWriteBundle_1_wrdata_T_4 = mux(_frfWriteBundle_1_wrdata_T_2, frfWriteBundle_1_wrdata_prevUnrecoded, _frfWriteBundle_1_wrdata_T_3) node _frfWriteBundle_1_wrdata_T_5 = cat(_frfWriteBundle_1_wrdata_T, _frfWriteBundle_1_wrdata_T_4) connect frfWriteBundle_1.wrdata, _frfWriteBundle_1_wrdata_T_5 node _T_31 = bits(wen, 0, 0) node _T_32 = or(_T_31, divSqrt_wen) node _T_33 = and(wb_cp, _T_32) when _T_33 : connect io.cp_resp.bits.data, wdata_1 connect io.cp_resp.valid, UInt<1>(0h1) node _T_34 = eq(io.cp_req.valid, UInt<1>(0h0)) node _T_35 = or(_T_34, UInt<1>(0h0)) node _T_36 = asUInt(reset) node _T_37 = eq(_T_36, UInt<1>(0h0)) when _T_37 : node _T_38 = eq(_T_35, UInt<1>(0h0)) when _T_38 : printf(clock, UInt<1>(0h1), "Assertion failed: FPU only supports coprocessor if FMA pipes have uniform latency List(2, 2, 3, 4, 3)\n at FPU.scala:987 assert(!io.cp_req.valid \|\| pipes.forall(_.lat == pipes.head.lat).B,\n") : printf_2 assert(clock, _T_35, UInt<1>(0h1), "") : assert_2 node _io_cp_req_ready_T = eq(ex_reg_valid, UInt<1>(0h0)) node _io_cp_req_ready_T_1 = neq(wen, UInt<1>(0h0)) node _io_cp_req_ready_T_2 = and(cp_ctrl.toint, _io_cp_req_ready_T_1) node _io_cp_req_ready_T_3 = eq(_io_cp_req_ready_T_2, UInt<1>(0h0)) node _io_cp_req_ready_T_4 = and(_io_cp_req_ready_T, _io_cp_req_ready_T_3) node _io_cp_req_ready_T_5 = eq(divSqrt_inFlight, UInt<1>(0h0)) node _io_cp_req_ready_T_6 = and(_io_cp_req_ready_T_4, _io_cp_req_ready_T_5) connect io.cp_req.ready, _io_cp_req_ready_T_6 node wb_toint_valid = and(wb_reg_valid, wb_ctrl.toint) reg wb_toint_exc : UInt<5>, clock when mem_ctrl.toint : connect wb_toint_exc, fpiu.io.out.bits.exc node _io_fcsr_flags_valid_T = or(wb_toint_valid, divSqrt_wen) node _io_fcsr_flags_valid_T_1 = bits(wen, 0, 0) node _io_fcsr_flags_valid_T_2 = or(_io_fcsr_flags_valid_T, _io_fcsr_flags_valid_T_1) connect io.fcsr_flags.valid, _io_fcsr_flags_valid_T_2 node _io_fcsr_flags_bits_T = mux(wb_toint_valid, wb_toint_exc, UInt<1>(0h0)) node _io_fcsr_flags_bits_T_1 = mux(divSqrt_wen, divSqrt_flags, UInt<1>(0h0)) node _io_fcsr_flags_bits_T_2 = or(_io_fcsr_flags_bits_T, _io_fcsr_flags_bits_T_1) node _io_fcsr_flags_bits_T_3 = bits(wen, 0, 0) node _io_fcsr_flags_bits_T_4 = mux(_io_fcsr_flags_bits_T_3, wexc, UInt<1>(0h0)) node _io_fcsr_flags_bits_T_5 = or(_io_fcsr_flags_bits_T_2, _io_fcsr_flags_bits_T_4) connect io.fcsr_flags.bits, _io_fcsr_flags_bits_T_5 node _divSqrt_write_port_busy_T = or(mem_ctrl.div, mem_ctrl.sqrt) node _divSqrt_write_port_busy_T_1 = orr(wen) node divSqrt_write_port_busy = and(_divSqrt_write_port_busy_T, _divSqrt_write_port_busy_T_1) node _io_fcsr_rdy_T = and(ex_reg_valid, ex_ctrl.wflags) node _io_fcsr_rdy_T_1 = and(mem_reg_valid, mem_ctrl.wflags) node _io_fcsr_rdy_T_2 = or(_io_fcsr_rdy_T, _io_fcsr_rdy_T_1) node _io_fcsr_rdy_T_3 = and(wb_reg_valid, wb_ctrl.toint) node _io_fcsr_rdy_T_4 = or(_io_fcsr_rdy_T_2, _io_fcsr_rdy_T_3) node _io_fcsr_rdy_T_5 = orr(wen) node _io_fcsr_rdy_T_6 = or(_io_fcsr_rdy_T_4, _io_fcsr_rdy_T_5) node _io_fcsr_rdy_T_7 = or(_io_fcsr_rdy_T_6, divSqrt_inFlight) node _io_fcsr_rdy_T_8 = eq(_io_fcsr_rdy_T_7, UInt<1>(0h0)) connect io.fcsr_rdy, _io_fcsr_rdy_T_8 node _io_nack_mem_T = or(write_port_busy, divSqrt_write_port_busy) node _io_nack_mem_T_1 = or(_io_nack_mem_T, divSqrt_inFlight) node _io_nack_mem_T_2 = eq(mem_cp_valid, UInt<1>(0h0)) node _io_nack_mem_T_3 = and(_io_nack_mem_T_1, _io_nack_mem_T_2) connect io.nack_mem, _io_nack_mem_T_3 connect io.dec, id_ctrl node _io_sboard_set_T = eq(wb_cp_valid, UInt<1>(0h0)) node _io_sboard_set_T_1 = and(wb_reg_valid, _io_sboard_set_T) node _io_sboard_set_T_2 = eq(mem_ctrl.typeTagOut, UInt<2>(0h2)) node _io_sboard_set_T_3 = and(mem_ctrl.fma, _io_sboard_set_T_2) node _io_sboard_set_T_4 = or(UInt<1>(0h0), _io_sboard_set_T_3) node _io_sboard_set_T_5 = or(_io_sboard_set_T_4, mem_ctrl.div) node _io_sboard_set_T_6 = or(_io_sboard_set_T_5, mem_ctrl.sqrt) node _io_sboard_set_T_7 = or(_io_sboard_set_T_6, mem_ctrl.vec) reg io_sboard_set_REG : UInt<1>, clock connect io_sboard_set_REG, _io_sboard_set_T_7 node _io_sboard_set_T_8 = and(_io_sboard_set_T_1, io_sboard_set_REG) connect io.sboard_set, _io_sboard_set_T_8 node _io_sboard_clr_T = eq(wb_cp_valid, UInt<1>(0h0)) node _io_sboard_clr_T_1 = bits(wen, 0, 0) node _io_sboard_clr_T_2 = eq(wbInfo[0].pipeid, UInt<2>(0h3)) node _io_sboard_clr_T_3 = or(UInt<1>(0h0), _io_sboard_clr_T_2) node _io_sboard_clr_T_4 = and(_io_sboard_clr_T_1, _io_sboard_clr_T_3) node _io_sboard_clr_T_5 = or(divSqrt_wen, _io_sboard_clr_T_4) node _io_sboard_clr_T_6 = and(_io_sboard_clr_T, _io_sboard_clr_T_5) connect io.sboard_clr, _io_sboard_clr_T_6 connect io.sboard_clra, waddr node _T_39 = and(io.sboard_clr, load_wb) node _io_illegal_rm_T = bits(io.inst, 14, 12) node _io_illegal_rm_T_1 = eq(_io_illegal_rm_T, UInt<3>(0h5)) node _io_illegal_rm_T_2 = eq(_io_illegal_rm_T, UInt<3>(0h6)) node _io_illegal_rm_T_3 = or(_io_illegal_rm_T_1, _io_illegal_rm_T_2) node _io_illegal_rm_T_4 = bits(io.inst, 14, 12) node _io_illegal_rm_T_5 = eq(_io_illegal_rm_T_4, UInt<3>(0h7)) node _io_illegal_rm_T_6 = geq(io.fcsr_rm, UInt<3>(0h5)) node _io_illegal_rm_T_7 = and(_io_illegal_rm_T_5, _io_illegal_rm_T_6) node _io_illegal_rm_T_8 = or(_io_illegal_rm_T_3, _io_illegal_rm_T_7) connect io.illegal_rm, _io_illegal_rm_T_8 node _divSqrt_inValid_T = or(mem_ctrl.div, mem_ctrl.sqrt) node _divSqrt_inValid_T_1 = and(mem_reg_valid, _divSqrt_inValid_T) node _divSqrt_inValid_T_2 = eq(divSqrt_inFlight, UInt<1>(0h0)) node divSqrt_inValid = and(_divSqrt_inValid_T_1, _divSqrt_inValid_T_2) node _divSqrt_killed_T = and(divSqrt_inValid, killm) regreset divSqrt_killed : UInt<1>, clock, reset, UInt<1>(0h1) connect divSqrt_killed, _divSqrt_killed_T when divSqrt_inValid : node _divSqrt_waddr_T = bits(mem_reg_inst, 11, 7) connect divSqrt_waddr, _divSqrt_waddr_T connect divSqrt_cp, mem_cp_valid node _T_40 = and(divSqrt_inFlight, divSqrt_killed) node _T_41 = and(divSqrt_inFlight, mem_reg_valid) node _T_42 = or(mem_ctrl.div, mem_ctrl.sqrt) node _T_43 = and(_T_41, _T_42) node _T_44 = and(mem_reg_valid, divSqrt_write_port_busy) inst divSqrt of DivSqrtRecFM_small_e5_s11_1 connect divSqrt.clock, clock connect divSqrt.reset, divSqrt_killed node _divSqrt_io_inValid_T = eq(mem_ctrl.typeTagOut, UInt<1>(0h0)) node _divSqrt_io_inValid_T_1 = and(divSqrt_inValid, _divSqrt_io_inValid_T) connect divSqrt.io.inValid, _divSqrt_io_inValid_T_1 connect divSqrt.io.sqrtOp, mem_ctrl.sqrt node divSqrt_io_a_sign = bits(fpiu.io.out.bits.in.in1, 64, 64) node divSqrt_io_a_fractIn = bits(fpiu.io.out.bits.in.in1, 51, 0) node divSqrt_io_a_expIn = bits(fpiu.io.out.bits.in.in1, 63, 52) node _divSqrt_io_a_fractOut_T = shl(divSqrt_io_a_fractIn, 11) node divSqrt_io_a_fractOut = shr(_divSqrt_io_a_fractOut_T, 53) node divSqrt_io_a_expOut_expCode = bits(divSqrt_io_a_expIn, 11, 9) node _divSqrt_io_a_expOut_commonCase_T = add(divSqrt_io_a_expIn, UInt<6>(0h20)) node _divSqrt_io_a_expOut_commonCase_T_1 = tail(_divSqrt_io_a_expOut_commonCase_T, 1) node _divSqrt_io_a_expOut_commonCase_T_2 = sub(_divSqrt_io_a_expOut_commonCase_T_1, UInt<12>(0h800)) node divSqrt_io_a_expOut_commonCase = tail(_divSqrt_io_a_expOut_commonCase_T_2, 1) node _divSqrt_io_a_expOut_T = eq(divSqrt_io_a_expOut_expCode, UInt<1>(0h0)) node _divSqrt_io_a_expOut_T_1 = geq(divSqrt_io_a_expOut_expCode, UInt<3>(0h6)) node _divSqrt_io_a_expOut_T_2 = or(_divSqrt_io_a_expOut_T, _divSqrt_io_a_expOut_T_1) node _divSqrt_io_a_expOut_T_3 = bits(divSqrt_io_a_expOut_commonCase, 2, 0) node _divSqrt_io_a_expOut_T_4 = cat(divSqrt_io_a_expOut_expCode, _divSqrt_io_a_expOut_T_3) node _divSqrt_io_a_expOut_T_5 = bits(divSqrt_io_a_expOut_commonCase, 5, 0) node divSqrt_io_a_expOut = mux(_divSqrt_io_a_expOut_T_2, _divSqrt_io_a_expOut_T_4, _divSqrt_io_a_expOut_T_5) node divSqrt_io_a_hi = cat(divSqrt_io_a_sign, divSqrt_io_a_expOut) node _divSqrt_io_a_T = cat(divSqrt_io_a_hi, divSqrt_io_a_fractOut) connect divSqrt.io.a, _divSqrt_io_a_T node divSqrt_io_b_sign = bits(fpiu.io.out.bits.in.in2, 64, 64) node divSqrt_io_b_fractIn = bits(fpiu.io.out.bits.in.in2, 51, 0) node divSqrt_io_b_expIn = bits(fpiu.io.out.bits.in.in2, 63, 52) node _divSqrt_io_b_fractOut_T = shl(divSqrt_io_b_fractIn, 11) node divSqrt_io_b_fractOut = shr(_divSqrt_io_b_fractOut_T, 53) node divSqrt_io_b_expOut_expCode = bits(divSqrt_io_b_expIn, 11, 9) node _divSqrt_io_b_expOut_commonCase_T = add(divSqrt_io_b_expIn, UInt<6>(0h20)) node _divSqrt_io_b_expOut_commonCase_T_1 = tail(_divSqrt_io_b_expOut_commonCase_T, 1) node _divSqrt_io_b_expOut_commonCase_T_2 = sub(_divSqrt_io_b_expOut_commonCase_T_1, UInt<12>(0h800)) node divSqrt_io_b_expOut_commonCase = tail(_divSqrt_io_b_expOut_commonCase_T_2, 1) node _divSqrt_io_b_expOut_T = eq(divSqrt_io_b_expOut_expCode, UInt<1>(0h0)) node _divSqrt_io_b_expOut_T_1 = geq(divSqrt_io_b_expOut_expCode, UInt<3>(0h6)) node _divSqrt_io_b_expOut_T_2 = or(_divSqrt_io_b_expOut_T, _divSqrt_io_b_expOut_T_1) node _divSqrt_io_b_expOut_T_3 = bits(divSqrt_io_b_expOut_commonCase, 2, 0) node _divSqrt_io_b_expOut_T_4 = cat(divSqrt_io_b_expOut_expCode, _divSqrt_io_b_expOut_T_3) node _divSqrt_io_b_expOut_T_5 = bits(divSqrt_io_b_expOut_commonCase, 5, 0) node divSqrt_io_b_expOut = mux(_divSqrt_io_b_expOut_T_2, _divSqrt_io_b_expOut_T_4, _divSqrt_io_b_expOut_T_5) node divSqrt_io_b_hi = cat(divSqrt_io_b_sign, divSqrt_io_b_expOut) node _divSqrt_io_b_T = cat(divSqrt_io_b_hi, divSqrt_io_b_fractOut) connect divSqrt.io.b, _divSqrt_io_b_T connect divSqrt.io.roundingMode, fpiu.io.out.bits.in.rm connect divSqrt.io.detectTininess, UInt<1>(0h1) node _T_45 = eq(divSqrt.io.inReady, UInt<1>(0h0)) when _T_45 : connect divSqrt_inFlight, UInt<1>(0h1) node _T_46 = or(divSqrt.io.outValid_div, divSqrt.io.outValid_sqrt) when _T_46 : node _divSqrt_wen_T = eq(divSqrt_killed, UInt<1>(0h0)) connect divSqrt_wen, _divSqrt_wen_T connect divSqrt_wdata, divSqrt.io.out connect divSqrt_flags, divSqrt.io.exceptionFlags connect divSqrt_typeTag, UInt<1>(0h0) inst divSqrt_1 of DivSqrtRecFM_small_e8_s24_1 connect divSqrt_1.clock, clock connect divSqrt_1.reset, divSqrt_killed node _divSqrt_io_inValid_T_2 = eq(mem_ctrl.typeTagOut, UInt<1>(0h1)) node _divSqrt_io_inValid_T_3 = and(divSqrt_inValid, _divSqrt_io_inValid_T_2) connect divSqrt_1.io.inValid, _divSqrt_io_inValid_T_3 connect divSqrt_1.io.sqrtOp, mem_ctrl.sqrt node divSqrt_io_a_sign_1 = bits(fpiu.io.out.bits.in.in1, 64, 64) node divSqrt_io_a_fractIn_1 = bits(fpiu.io.out.bits.in.in1, 51, 0) node divSqrt_io_a_expIn_1 = bits(fpiu.io.out.bits.in.in1, 63, 52) node _divSqrt_io_a_fractOut_T_1 = shl(divSqrt_io_a_fractIn_1, 24) node divSqrt_io_a_fractOut_1 = shr(_divSqrt_io_a_fractOut_T_1, 53) node divSqrt_io_a_expOut_expCode_1 = bits(divSqrt_io_a_expIn_1, 11, 9) node _divSqrt_io_a_expOut_commonCase_T_3 = add(divSqrt_io_a_expIn_1, UInt<9>(0h100)) node _divSqrt_io_a_expOut_commonCase_T_4 = tail(_divSqrt_io_a_expOut_commonCase_T_3, 1) node _divSqrt_io_a_expOut_commonCase_T_5 = sub(_divSqrt_io_a_expOut_commonCase_T_4, UInt<12>(0h800)) node divSqrt_io_a_expOut_commonCase_1 = tail(_divSqrt_io_a_expOut_commonCase_T_5, 1) node _divSqrt_io_a_expOut_T_6 = eq(divSqrt_io_a_expOut_expCode_1, UInt<1>(0h0)) node _divSqrt_io_a_expOut_T_7 = geq(divSqrt_io_a_expOut_expCode_1, UInt<3>(0h6)) node _divSqrt_io_a_expOut_T_8 = or(_divSqrt_io_a_expOut_T_6, _divSqrt_io_a_expOut_T_7) node _divSqrt_io_a_expOut_T_9 = bits(divSqrt_io_a_expOut_commonCase_1, 5, 0) node _divSqrt_io_a_expOut_T_10 = cat(divSqrt_io_a_expOut_expCode_1, _divSqrt_io_a_expOut_T_9) node _divSqrt_io_a_expOut_T_11 = bits(divSqrt_io_a_expOut_commonCase_1, 8, 0) node divSqrt_io_a_expOut_1 = mux(_divSqrt_io_a_expOut_T_8, _divSqrt_io_a_expOut_T_10, _divSqrt_io_a_expOut_T_11) node divSqrt_io_a_hi_1 = cat(divSqrt_io_a_sign_1, divSqrt_io_a_expOut_1) node _divSqrt_io_a_T_1 = cat(divSqrt_io_a_hi_1, divSqrt_io_a_fractOut_1) connect divSqrt_1.io.a, _divSqrt_io_a_T_1 node divSqrt_io_b_sign_1 = bits(fpiu.io.out.bits.in.in2, 64, 64) node divSqrt_io_b_fractIn_1 = bits(fpiu.io.out.bits.in.in2, 51, 0) node divSqrt_io_b_expIn_1 = bits(fpiu.io.out.bits.in.in2, 63, 52) node _divSqrt_io_b_fractOut_T_1 = shl(divSqrt_io_b_fractIn_1, 24) node divSqrt_io_b_fractOut_1 = shr(_divSqrt_io_b_fractOut_T_1, 53) node divSqrt_io_b_expOut_expCode_1 = bits(divSqrt_io_b_expIn_1, 11, 9) node _divSqrt_io_b_expOut_commonCase_T_3 = add(divSqrt_io_b_expIn_1, UInt<9>(0h100)) node _divSqrt_io_b_expOut_commonCase_T_4 = tail(_divSqrt_io_b_expOut_commonCase_T_3, 1) node _divSqrt_io_b_expOut_commonCase_T_5 = sub(_divSqrt_io_b_expOut_commonCase_T_4, UInt<12>(0h800)) node divSqrt_io_b_expOut_commonCase_1 = tail(_divSqrt_io_b_expOut_commonCase_T_5, 1) node _divSqrt_io_b_expOut_T_6 = eq(divSqrt_io_b_expOut_expCode_1, UInt<1>(0h0)) node _divSqrt_io_b_expOut_T_7 = geq(divSqrt_io_b_expOut_expCode_1, UInt<3>(0h6)) node _divSqrt_io_b_expOut_T_8 = or(_divSqrt_io_b_expOut_T_6, _divSqrt_io_b_expOut_T_7) node _divSqrt_io_b_expOut_T_9 = bits(divSqrt_io_b_expOut_commonCase_1, 5, 0) node _divSqrt_io_b_expOut_T_10 = cat(divSqrt_io_b_expOut_expCode_1, _divSqrt_io_b_expOut_T_9) node _divSqrt_io_b_expOut_T_11 = bits(divSqrt_io_b_expOut_commonCase_1, 8, 0) node divSqrt_io_b_expOut_1 = mux(_divSqrt_io_b_expOut_T_8, _divSqrt_io_b_expOut_T_10, _divSqrt_io_b_expOut_T_11) node divSqrt_io_b_hi_1 = cat(divSqrt_io_b_sign_1, divSqrt_io_b_expOut_1) node _divSqrt_io_b_T_1 = cat(divSqrt_io_b_hi_1, divSqrt_io_b_fractOut_1) connect divSqrt_1.io.b, _divSqrt_io_b_T_1 connect divSqrt_1.io.roundingMode, fpiu.io.out.bits.in.rm connect divSqrt_1.io.detectTininess, UInt<1>(0h1) node _T_47 = eq(divSqrt_1.io.inReady, UInt<1>(0h0)) when _T_47 : connect divSqrt_inFlight, UInt<1>(0h1) node _T_48 = or(divSqrt_1.io.outValid_div, divSqrt_1.io.outValid_sqrt) when _T_48 : node _divSqrt_wen_T_1 = eq(divSqrt_killed, UInt<1>(0h0)) connect divSqrt_wen, _divSqrt_wen_T_1 node _divSqrt_wdata_maskedNaN_T = not(UInt<33>(0h10800000)) node divSqrt_wdata_maskedNaN = and(divSqrt_1.io.out, _divSqrt_wdata_maskedNaN_T) node _divSqrt_wdata_T = bits(divSqrt_1.io.out, 31, 29) node _divSqrt_wdata_T_1 = andr(_divSqrt_wdata_T) node _divSqrt_wdata_T_2 = mux(_divSqrt_wdata_T_1, divSqrt_wdata_maskedNaN, divSqrt_1.io.out) connect divSqrt_wdata, _divSqrt_wdata_T_2 connect divSqrt_flags, divSqrt_1.io.exceptionFlags connect divSqrt_typeTag, UInt<1>(0h1) inst divSqrt_2 of DivSqrtRecFM_small_e11_s53_1 connect divSqrt_2.clock, clock connect divSqrt_2.reset, divSqrt_killed node _divSqrt_io_inValid_T_4 = eq(mem_ctrl.typeTagOut, UInt<2>(0h2)) node _divSqrt_io_inValid_T_5 = and(divSqrt_inValid, _divSqrt_io_inValid_T_4) connect divSqrt_2.io.inValid, _divSqrt_io_inValid_T_5 connect divSqrt_2.io.sqrtOp, mem_ctrl.sqrt connect divSqrt_2.io.a, fpiu.io.out.bits.in.in1 connect divSqrt_2.io.b, fpiu.io.out.bits.in.in2 connect divSqrt_2.io.roundingMode, fpiu.io.out.bits.in.rm connect divSqrt_2.io.detectTininess, UInt<1>(0h1) node _T_49 = eq(divSqrt_2.io.inReady, UInt<1>(0h0)) when _T_49 : connect divSqrt_inFlight, UInt<1>(0h1) node _T_50 = or(divSqrt_2.io.outValid_div, divSqrt_2.io.outValid_sqrt) when _T_50 : node _divSqrt_wen_T_2 = eq(divSqrt_killed, UInt<1>(0h0)) connect divSqrt_wen, _divSqrt_wen_T_2 node _divSqrt_wdata_maskedNaN_T_1 = not(UInt<65>(0h1010000000000000)) node divSqrt_wdata_maskedNaN_1 = and(divSqrt_2.io.out, _divSqrt_wdata_maskedNaN_T_1) node _divSqrt_wdata_T_3 = bits(divSqrt_2.io.out, 63, 61) node _divSqrt_wdata_T_4 = andr(_divSqrt_wdata_T_3) node _divSqrt_wdata_T_5 = mux(_divSqrt_wdata_T_4, divSqrt_wdata_maskedNaN_1, divSqrt_2.io.out) connect divSqrt_wdata, _divSqrt_wdata_T_5 connect divSqrt_flags, divSqrt_2.io.exceptionFlags connect divSqrt_typeTag, UInt<2>(0h2) when divSqrt_killed : connect divSqrt_inFlight, UInt<1>(0h0) node _clock_en_reg_T = eq(UInt<1>(0h0), UInt<1>(0h0)) node _clock_en_reg_T_1 = or(_clock_en_reg_T, io.keep_clock_enabled) node _clock_en_reg_T_2 = or(_clock_en_reg_T_1, io.valid) node _clock_en_reg_T_3 = or(_clock_en_reg_T_2, req_valid) node _clock_en_reg_T_4 = or(_clock_en_reg_T_3, mem_reg_valid) node _clock_en_reg_T_5 = or(_clock_en_reg_T_4, mem_cp_valid) node _clock_en_reg_T_6 = or(_clock_en_reg_T_5, wb_reg_valid) node _clock_en_reg_T_7 = or(_clock_en_reg_T_6, wb_cp_valid) node _clock_en_reg_T_8 = orr(wen) node _clock_en_reg_T_9 = or(_clock_en_reg_T_7, _clock_en_reg_T_8) node _clock_en_reg_T_10 = or(_clock_en_reg_T_9, divSqrt_inFlight) node _clock_en_reg_T_11 = or(_clock_en_reg_T_10, io.ll_resp_val) connect clock_en_reg, _clock_en_reg_T_11	module FPU_1( // @[FPU.scala:735:7] input clock, // @[FPU.scala:735:7] input reset, // @[FPU.scala:735:7] input [1:0] io_hartid, // @[FPU.scala:736:14] input [63:0] io_time, // @[FPU.scala:736:14] input [31:0] io_inst, // @[FPU.scala:736:14] input [63:0] io_fromint_data, // @[FPU.scala:736:14] input [2:0] io_fcsr_rm, // @[FPU.scala:736:14] output io_fcsr_flags_valid, // @[FPU.scala:736:14] output [4:0] io_fcsr_flags_bits, // @[FPU.scala:736:14] output [63:0] io_store_data, // @[FPU.scala:736:14] output [63:0] io_toint_data, // @[FPU.scala:736:14] input io_ll_resp_val, // @[FPU.scala:736:14] input [2:0] io_ll_resp_type, // @[FPU.scala:736:14] input [4:0] io_ll_resp_tag, // @[FPU.scala:736:14] input [63:0] io_ll_resp_data, // @[FPU.scala:736:14] input io_valid, // @[FPU.scala:736:14] output io_fcsr_rdy, // @[FPU.scala:736:14] output io_nack_mem, // @[FPU.scala:736:14] output io_illegal_rm, // @[FPU.scala:736:14] input io_killx, // @[FPU.scala:736:14] input io_killm, // @[FPU.scala:736:14] output io_dec_ldst, // @[FPU.scala:736:14] output io_dec_wen, // @[FPU.scala:736:14] output io_dec_ren1, // @[FPU.scala:736:14] output io_dec_ren2, // @[FPU.scala:736:14] output io_dec_ren3, // @[FPU.scala:736:14] output io_dec_swap12, // @[FPU.scala:736:14] output io_dec_swap23, // @[FPU.scala:736:14] output [1:0] io_dec_typeTagIn, // @[FPU.scala:736:14] output [1:0] io_dec_typeTagOut, // @[FPU.scala:736:14] output io_dec_fromint, // @[FPU.scala:736:14] output io_dec_toint, // @[FPU.scala:736:14] output io_dec_fastpipe, // @[FPU.scala:736:14] output io_dec_fma, // @[FPU.scala:736:14] output io_dec_div, // @[FPU.scala:736:14] output io_dec_sqrt, // @[FPU.scala:736:14] output io_dec_wflags, // @[FPU.scala:736:14] output io_dec_vec, // @[FPU.scala:736:14] output io_sboard_set, // @[FPU.scala:736:14] output io_sboard_clr, // @[FPU.scala:736:14] output [4:0] io_sboard_clra, // @[FPU.scala:736:14] input io_keep_clock_enabled // @[FPU.scala:736:14] ); wire wdata_rawIn_2_isNaN; // @[rawFloatFromFN.scala:63:19] wire wdata_rawIn_1_isNaN; // @[rawFloatFromFN.scala:63:19] wire wdata_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19] wire _divSqrt_2_io_inReady; // @[FPU.scala:1027:55] wire _divSqrt_2_io_outValid_div; // @[FPU.scala:1027:55] wire _divSqrt_2_io_outValid_sqrt; // @[FPU.scala:1027:55] wire [64:0] _divSqrt_2_io_out; // @[FPU.scala:1027:55] wire [4:0] _divSqrt_2_io_exceptionFlags; // @[FPU.scala:1027:55] wire _divSqrt_1_io_inReady; // @[FPU.scala:1027:55] wire _divSqrt_1_io_outValid_div; // @[FPU.scala:1027:55] wire _divSqrt_1_io_outValid_sqrt; // @[FPU.scala:1027:55] wire [32:0] _divSqrt_1_io_out; // @[FPU.scala:1027:55] wire [4:0] _divSqrt_1_io_exceptionFlags; // @[FPU.scala:1027:55] wire _divSqrt_io_inReady; // @[FPU.scala:1027:55] wire _divSqrt_io_outValid_div; // @[FPU.scala:1027:55] wire _divSqrt_io_outValid_sqrt; // @[FPU.scala:1027:55] wire [16:0] _divSqrt_io_out; // @[FPU.scala:1027:55] wire [4:0] _divSqrt_io_exceptionFlags; // @[FPU.scala:1027:55] wire [64:0] _hfma_io_out_bits_data; // @[FPU.scala:919:28] wire [4:0] _hfma_io_out_bits_exc; // @[FPU.scala:919:28] wire [64:0] _dfma_io_out_bits_data; // @[FPU.scala:913:28] wire [4:0] _dfma_io_out_bits_exc; // @[FPU.scala:913:28] wire [64:0] _fpmu_io_out_bits_data; // @[FPU.scala:891:20] wire [4:0] _fpmu_io_out_bits_exc; // @[FPU.scala:891:20] wire [64:0] _ifpu_io_out_bits_data; // @[FPU.scala:886:20] wire [4:0] _ifpu_io_out_bits_exc; // @[FPU.scala:886:20] wire [2:0] _fpiu_io_out_bits_in_rm; // @[FPU.scala:876:20] wire [64:0] _fpiu_io_out_bits_in_in1; // @[FPU.scala:876:20] wire [64:0] _fpiu_io_out_bits_in_in2; // @[FPU.scala:876:20] wire _fpiu_io_out_bits_lt; // @[FPU.scala:876:20] wire [4:0] _fpiu_io_out_bits_exc; // @[FPU.scala:876:20] wire [64:0] _sfma_io_out_bits_data; // @[FPU.scala:872:20] wire [4:0] _sfma_io_out_bits_exc; // @[FPU.scala:872:20] wire [64:0] _regfile_ext_R0_data; // @[FPU.scala:818:20] wire [64:0] _regfile_ext_R1_data; // @[FPU.scala:818:20] wire [64:0] _regfile_ext_R2_data; // @[FPU.scala:818:20] wire [1:0] io_hartid_0 = io_hartid; // @[FPU.scala:735:7] wire [63:0] io_time_0 = io_time; // @[FPU.scala:735:7] wire [31:0] io_inst_0 = io_inst; // @[FPU.scala:735:7] wire [63:0] io_fromint_data_0 = io_fromint_data; // @[FPU.scala:735:7] wire [2:0] io_fcsr_rm_0 = io_fcsr_rm; // @[FPU.scala:735:7] wire io_ll_resp_val_0 = io_ll_resp_val; // @[FPU.scala:735:7] wire [2:0] io_ll_resp_type_0 = io_ll_resp_type; // @[FPU.scala:735:7] wire [4:0] io_ll_resp_tag_0 = io_ll_resp_tag; // @[FPU.scala:735:7] wire [63:0] io_ll_resp_data_0 = io_ll_resp_data; // @[FPU.scala:735:7] wire io_valid_0 = io_valid; // @[FPU.scala:735:7] wire io_killx_0 = io_killx; // @[FPU.scala:735:7] wire io_killm_0 = io_killm; // @[FPU.scala:735:7] wire io_keep_clock_enabled_0 = io_keep_clock_enabled; // @[FPU.scala:735:7] wire frfWriteBundle_0_clock = clock; // @[FPU.scala:805:44] wire frfWriteBundle_0_reset = reset; // @[FPU.scala:805:44] wire frfWriteBundle_1_clock = clock; // @[FPU.scala:805:44] wire frfWriteBundle_1_reset = reset; // @[FPU.scala:805:44] wire clock_en = 1'h1; // @[FPU.scala:735:7, :745:31] wire _killm_T_1 = 1'h1; // @[FPU.scala:735:7, :785:44] wire prevOK_prevOK = 1'h1; // @[FPU.scala:384:33, :735:7] wire _wdata_opts_bigger_swizzledNaN_T = 1'h1; // @[FPU.scala:338:42, :735:7] wire _wdata_opts_bigger_T = 1'h1; // @[FPU.scala:249:56, :735:7] wire _wdata_opts_bigger_swizzledNaN_T_4 = 1'h1; // @[FPU.scala:338:42, :735:7] wire _wdata_opts_bigger_T_1 = 1'h1; // @[FPU.scala:249:56, :735:7] wire prevOK_prevOK_1 = 1'h1; // @[FPU.scala:384:33, :735:7] wire _io_cp_req_ready_T_3 = 1'h1; // @[FPU.scala:735:7, :991:39] wire _io_nack_mem_T_2 = 1'h1; // @[FPU.scala:735:7, :1003:86] wire _io_sboard_set_T = 1'h1; // @[FPU.scala:735:7, :1006:36] wire _io_sboard_clr_T = 1'h1; // @[FPU.scala:735:7, :1007:20] wire _clock_en_reg_T = 1'h1; // @[FPU.scala:735:7, :1051:19] wire _clock_en_reg_T_1 = 1'h1; // @[FPU.scala:735:7, :1051:37] wire _clock_en_reg_T_2 = 1'h1; // @[FPU.scala:735:7, :1052:27] wire _clock_en_reg_T_3 = 1'h1; // @[FPU.scala:735:7, :1053:14] wire _clock_en_reg_T_4 = 1'h1; // @[FPU.scala:735:7, :1054:15] wire _clock_en_reg_T_5 = 1'h1; // @[FPU.scala:735:7, :1055:19] wire _clock_en_reg_T_6 = 1'h1; // @[FPU.scala:735:7, :1055:35] wire _clock_en_reg_T_7 = 1'h1; // @[FPU.scala:735:7, :1056:18] wire _clock_en_reg_T_9 = 1'h1; // @[FPU.scala:735:7, :1056:33] wire _clock_en_reg_T_10 = 1'h1; // @[FPU.scala:735:7, :1057:13] wire _clock_en_reg_T_11 = 1'h1; // @[FPU.scala:735:7, :1057:33] wire io_cp_req_valid = 1'h0; // @[FPU.scala:735:7] wire io_cp_req_bits_ldst = 1'h0; // @[FPU.scala:735:7] wire io_cp_req_bits_wen = 1'h0; // @[FPU.scala:735:7] wire io_cp_req_bits_ren1 = 1'h0; // @[FPU.scala:735:7] wire io_cp_req_bits_ren2 = 1'h0; // @[FPU.scala:735:7] wire io_cp_req_bits_ren3 = 1'h0; // @[FPU.scala:735:7] wire io_cp_req_bits_swap12 = 1'h0; // @[FPU.scala:735:7] wire io_cp_req_bits_swap23 = 1'h0; // @[FPU.scala:735:7] wire io_cp_req_bits_fromint = 1'h0; // @[FPU.scala:735:7] wire io_cp_req_bits_toint = 1'h0; // @[FPU.scala:735:7] wire io_cp_req_bits_fastpipe = 1'h0; // @[FPU.scala:735:7] wire io_cp_req_bits_fma = 1'h0; // @[FPU.scala:735:7] wire io_cp_req_bits_div = 1'h0; // @[FPU.scala:735:7] wire io_cp_req_bits_sqrt = 1'h0; // @[FPU.scala:735:7] wire io_cp_req_bits_wflags = 1'h0; // @[FPU.scala:735:7] wire io_cp_req_bits_vec = 1'h0; // @[FPU.scala:735:7] wire io_cp_resp_ready = 1'h0; // @[FPU.scala:735:7] wire ex_cp_valid = 1'h0; // @[Decoupled.scala:51:35] wire cp_ctrl_ldst = 1'h0; // @[FPU.scala:794:21] wire cp_ctrl_wen = 1'h0; // @[FPU.scala:794:21] wire cp_ctrl_ren1 = 1'h0; // @[FPU.scala:794:21] wire cp_ctrl_ren2 = 1'h0; // @[FPU.scala:794:21] wire cp_ctrl_ren3 = 1'h0; // @[FPU.scala:794:21] wire cp_ctrl_swap12 = 1'h0; // @[FPU.scala:794:21] wire cp_ctrl_swap23 = 1'h0; // @[FPU.scala:794:21] wire cp_ctrl_fromint = 1'h0; // @[FPU.scala:794:21] wire cp_ctrl_toint = 1'h0; // @[FPU.scala:794:21] wire cp_ctrl_fastpipe = 1'h0; // @[FPU.scala:794:21] wire cp_ctrl_fma = 1'h0; // @[FPU.scala:794:21] wire cp_ctrl_div = 1'h0; // @[FPU.scala:794:21] wire cp_ctrl_sqrt = 1'h0; // @[FPU.scala:794:21] wire cp_ctrl_wflags = 1'h0; // @[FPU.scala:794:21] wire cp_ctrl_vec = 1'h0; // @[FPU.scala:794:21] wire frfWriteBundle_0_excpt = 1'h0; // @[FPU.scala:805:44] wire frfWriteBundle_0_valid = 1'h0; // @[FPU.scala:805:44] wire frfWriteBundle_0_wrenx = 1'h0; // @[FPU.scala:805:44] wire frfWriteBundle_1_excpt = 1'h0; // @[FPU.scala:805:44] wire frfWriteBundle_1_valid = 1'h0; // @[FPU.scala:805:44] wire frfWriteBundle_1_wrenx = 1'h0; // @[FPU.scala:805:44] wire _wbInfo_0_pipeid_T = 1'h0; // @[FPU.scala:928:63] wire _wbInfo_1_pipeid_T = 1'h0; // @[FPU.scala:928:63] wire _wbInfo_2_pipeid_T = 1'h0; // @[FPU.scala:928:63] wire _io_cp_req_ready_T_2 = 1'h0; // @[FPU.scala:991:55] wire [64:0] io_cp_req_bits_in1 = 65'h0; // @[FPU.scala:735:7] wire [64:0] io_cp_req_bits_in2 = 65'h0; // @[FPU.scala:735:7] wire [64:0] io_cp_req_bits_in3 = 65'h0; // @[FPU.scala:735:7] wire [64:0] _dfma_io_in_bits_req_in1_T = 65'h0; // @[FPU.scala:372:31] wire [64:0] _dfma_io_in_bits_req_in2_T = 65'h0; // @[FPU.scala:372:31] wire [64:0] _dfma_io_in_bits_req_in3_T = 65'h0; // @[FPU.scala:372:31] wire [2:0] io_v_sew = 3'h0; // @[FPU.scala:735:7] wire [2:0] io_cp_req_bits_rm = 3'h0; // @[FPU.scala:735:7] wire [2:0] frfWriteBundle_0_priv_mode = 3'h0; // @[FPU.scala:805:44] wire [2:0] frfWriteBundle_1_priv_mode = 3'h0; // @[FPU.scala:805:44] wire [1:0] io_cp_req_bits_typeTagIn = 2'h0; // @[FPU.scala:735:7] wire [1:0] io_cp_req_bits_typeTagOut = 2'h0; // @[FPU.scala:735:7] wire [1:0] io_cp_req_bits_fmaCmd = 2'h0; // @[FPU.scala:735:7] wire [1:0] io_cp_req_bits_typ = 2'h0; // @[FPU.scala:735:7] wire [1:0] io_cp_req_bits_fmt = 2'h0; // @[FPU.scala:735:7] wire [1:0] cp_ctrl_typeTagIn = 2'h0; // @[FPU.scala:794:21] wire [1:0] cp_ctrl_typeTagOut = 2'h0; // @[FPU.scala:794:21] wire [4:0] io_cp_resp_bits_exc = 5'h0; // @[FPU.scala:735:7] wire [4:0] frfWriteBundle_0_rd0src = 5'h0; // @[FPU.scala:805:44] wire [4:0] frfWriteBundle_0_rd1src = 5'h0; // @[FPU.scala:805:44] wire [4:0] frfWriteBundle_1_rd0src = 5'h0; // @[FPU.scala:805:44] wire [4:0] frfWriteBundle_1_rd1src = 5'h0; // @[FPU.scala:805:44] wire [64:0] _divSqrt_wdata_maskedNaN_T_1 = 65'h1EFEFFFFFFFFFFFFF; // @[FPU.scala:413:27] wire [32:0] _divSqrt_wdata_maskedNaN_T = 33'h1EF7FFFFF; // @[FPU.scala:413:27] wire [4:0] wdata_opts_bigger_swizzledNaN_hi_hi = 5'h1F; // @[FPU.scala:336:26] wire [4:0] wdata_opts_bigger_swizzledNaN_hi_hi_1 = 5'h1F; // @[FPU.scala:336:26] wire [31:0] frfWriteBundle_0_inst = 32'h0; // @[FPU.scala:805:44] wire [31:0] frfWriteBundle_1_inst = 32'h0; // @[FPU.scala:805:44] wire [63:0] frfWriteBundle_0_pc = 64'h0; // @[FPU.scala:805:44] wire [63:0] frfWriteBundle_0_rd0val = 64'h0; // @[FPU.scala:805:44] wire [63:0] frfWriteBundle_0_rd1val = 64'h0; // @[FPU.scala:805:44] wire [63:0] frfWriteBundle_1_pc = 64'h0; // @[FPU.scala:805:44] wire [63:0] frfWriteBundle_1_rd0val = 64'h0; // @[FPU.scala:805:44] wire [63:0] frfWriteBundle_1_rd1val = 64'h0; // @[FPU.scala:805:44] wire _io_fcsr_flags_valid_T_2; // @[FPU.scala:995:56] wire [4:0] _io_fcsr_flags_bits_T_5; // @[FPU.scala:998:42] wire _io_fcsr_rdy_T_8; // @[FPU.scala:1002:18] wire _io_nack_mem_T_3; // @[FPU.scala:1003:83] wire _io_illegal_rm_T_8; // @[FPU.scala:1011:53] wire id_ctrl_ldst; // @[FPU.scala:752:25] wire id_ctrl_wen; // @[FPU.scala:752:25] wire id_ctrl_ren1; // @[FPU.scala:752:25] wire id_ctrl_ren2; // @[FPU.scala:752:25] wire id_ctrl_ren3; // @[FPU.scala:752:25] wire id_ctrl_swap12; // @[FPU.scala:752:25] wire id_ctrl_swap23; // @[FPU.scala:752:25] wire [1:0] id_ctrl_typeTagIn; // @[FPU.scala:752:25] wire [1:0] id_ctrl_typeTagOut; // @[FPU.scala:752:25] wire id_ctrl_fromint; // @[FPU.scala:752:25] wire id_ctrl_toint; // @[FPU.scala:752:25] wire id_ctrl_fastpipe; // @[FPU.scala:752:25] wire id_ctrl_fma; // @[FPU.scala:752:25] wire id_ctrl_div; // @[FPU.scala:752:25] wire id_ctrl_sqrt; // @[FPU.scala:752:25] wire id_ctrl_wflags; // @[FPU.scala:752:25] wire id_ctrl_vec; // @[FPU.scala:752:25] wire _io_sboard_set_T_8; // @[FPU.scala:1006:49] wire _io_sboard_clr_T_6; // @[FPU.scala:1007:33] wire [4:0] waddr; // @[FPU.scala:963:18] wire _io_cp_req_ready_T_6; // @[FPU.scala:991:71] wire io_fcsr_flags_valid_0; // @[FPU.scala:735:7] wire [4:0] io_fcsr_flags_bits_0; // @[FPU.scala:735:7] wire io_dec_ldst_0; // @[FPU.scala:735:7] wire io_dec_wen_0; // @[FPU.scala:735:7] wire io_dec_ren1_0; // @[FPU.scala:735:7] wire io_dec_ren2_0; // @[FPU.scala:735:7] wire io_dec_ren3_0; // @[FPU.scala:735:7] wire io_dec_swap12_0; // @[FPU.scala:735:7] wire io_dec_swap23_0; // @[FPU.scala:735:7] wire [1:0] io_dec_typeTagIn_0; // @[FPU.scala:735:7] wire [1:0] io_dec_typeTagOut_0; // @[FPU.scala:735:7] wire io_dec_fromint_0; // @[FPU.scala:735:7] wire io_dec_toint_0; // @[FPU.scala:735:7] wire io_dec_fastpipe_0; // @[FPU.scala:735:7] wire io_dec_fma_0; // @[FPU.scala:735:7] wire io_dec_div_0; // @[FPU.scala:735:7] wire io_dec_sqrt_0; // @[FPU.scala:735:7] wire io_dec_wflags_0; // @[FPU.scala:735:7] wire io_dec_vec_0; // @[FPU.scala:735:7] wire io_cp_req_ready; // @[FPU.scala:735:7] wire [64:0] io_cp_resp_bits_data; // @[FPU.scala:735:7] wire io_cp_resp_valid; // @[FPU.scala:735:7] wire [63:0] io_store_data_0; // @[FPU.scala:735:7] wire [63:0] io_toint_data_0; // @[FPU.scala:735:7] wire io_fcsr_rdy_0; // @[FPU.scala:735:7] wire io_nack_mem_0; // @[FPU.scala:735:7] wire io_illegal_rm_0; // @[FPU.scala:735:7] wire io_sboard_set_0; // @[FPU.scala:735:7] wire io_sboard_clr_0; // @[FPU.scala:735:7] wire [4:0] io_sboard_clra_0; // @[FPU.scala:735:7] assign io_dec_ldst_0 = id_ctrl_ldst; // @[FPU.scala:735:7, :752:25] assign io_dec_wen_0 = id_ctrl_wen; // @[FPU.scala:735:7, :752:25] assign io_dec_ren1_0 = id_ctrl_ren1; // @[FPU.scala:735:7, :752:25] assign io_dec_ren2_0 = id_ctrl_ren2; // @[FPU.scala:735:7, :752:25] assign io_dec_ren3_0 = id_ctrl_ren3; // @[FPU.scala:735:7, :752:25] assign io_dec_swap12_0 = id_ctrl_swap12; // @[FPU.scala:735:7, :752:25] assign io_dec_swap23_0 = id_ctrl_swap23; // @[FPU.scala:735:7, :752:25] assign io_dec_typeTagIn_0 = id_ctrl_typeTagIn; // @[FPU.scala:735:7, :752:25] assign io_dec_typeTagOut_0 = id_ctrl_typeTagOut; // @[FPU.scala:735:7, :752:25] assign io_dec_fromint_0 = id_ctrl_fromint; // @[FPU.scala:735:7, :752:25] assign io_dec_toint_0 = id_ctrl_toint; // @[FPU.scala:735:7, :752:25] assign io_dec_fastpipe_0 = id_ctrl_fastpipe; // @[FPU.scala:735:7, :752:25] assign io_dec_fma_0 = id_ctrl_fma; // @[FPU.scala:735:7, :752:25] assign io_dec_div_0 = id_ctrl_div; // @[FPU.scala:735:7, :752:25] assign io_dec_sqrt_0 = id_ctrl_sqrt; // @[FPU.scala:735:7, :752:25] assign io_dec_wflags_0 = id_ctrl_wflags; // @[FPU.scala:735:7, :752:25] assign io_dec_vec_0 = id_ctrl_vec; // @[FPU.scala:735:7, :752:25] reg ex_reg_valid; // @[FPU.scala:767:29] wire req_valid = ex_reg_valid; // @[FPU.scala:767:29, :780:32] reg [31:0] ex_reg_inst; // @[FPU.scala:768:30] reg ex_reg_ctrl_ldst; // @[FPU.scala:769:30] wire ex_ctrl_ldst = ex_reg_ctrl_ldst; // @[FPU.scala:769:30, :800:20] reg ex_reg_ctrl_wen; // @[FPU.scala:769:30] wire ex_ctrl_wen = ex_reg_ctrl_wen; // @[FPU.scala:769:30, :800:20] reg ex_reg_ctrl_ren1; // @[FPU.scala:769:30] wire ex_ctrl_ren1 = ex_reg_ctrl_ren1; // @[FPU.scala:769:30, :800:20] reg ex_reg_ctrl_ren2; // @[FPU.scala:769:30] wire ex_ctrl_ren2 = ex_reg_ctrl_ren2; // @[FPU.scala:769:30, :800:20] reg ex_reg_ctrl_ren3; // @[FPU.scala:769:30] wire ex_ctrl_ren3 = ex_reg_ctrl_ren3; // @[FPU.scala:769:30, :800:20] reg ex_reg_ctrl_swap12; // @[FPU.scala:769:30] wire ex_ctrl_swap12 = ex_reg_ctrl_swap12; // @[FPU.scala:769:30, :800:20] reg ex_reg_ctrl_swap23; // @[FPU.scala:769:30] wire ex_ctrl_swap23 = ex_reg_ctrl_swap23; // @[FPU.scala:769:30, :800:20] reg [1:0] ex_reg_ctrl_typeTagIn; // @[FPU.scala:769:30] wire [1:0] ex_ctrl_typeTagIn = ex_reg_ctrl_typeTagIn; // @[FPU.scala:769:30, :800:20] reg [1:0] ex_reg_ctrl_typeTagOut; // @[FPU.scala:769:30] wire [1:0] ex_ctrl_typeTagOut = ex_reg_ctrl_typeTagOut; // @[FPU.scala:769:30, :800:20] reg ex_reg_ctrl_fromint; // @[FPU.scala:769:30] wire ex_ctrl_fromint = ex_reg_ctrl_fromint; // @[FPU.scala:769:30, :800:20] reg ex_reg_ctrl_toint; // @[FPU.scala:769:30] wire ex_ctrl_toint = ex_reg_ctrl_toint; // @[FPU.scala:769:30, :800:20] reg ex_reg_ctrl_fastpipe; // @[FPU.scala:769:30] wire ex_ctrl_fastpipe = ex_reg_ctrl_fastpipe; // @[FPU.scala:769:30, :800:20] reg ex_reg_ctrl_fma; // @[FPU.scala:769:30] wire ex_ctrl_fma = ex_reg_ctrl_fma; // @[FPU.scala:769:30, :800:20] reg ex_reg_ctrl_div; // @[FPU.scala:769:30] wire ex_ctrl_div = ex_reg_ctrl_div; // @[FPU.scala:769:30, :800:20] reg ex_reg_ctrl_sqrt; // @[FPU.scala:769:30] wire ex_ctrl_sqrt = ex_reg_ctrl_sqrt; // @[FPU.scala:769:30, :800:20] reg ex_reg_ctrl_wflags; // @[FPU.scala:769:30] wire ex_ctrl_wflags = ex_reg_ctrl_wflags; // @[FPU.scala:769:30, :800:20] reg ex_reg_ctrl_vec; // @[FPU.scala:769:30] wire ex_ctrl_vec = ex_reg_ctrl_vec; // @[FPU.scala:769:30, :800:20] reg [4:0] ex_ra_0; // @[FPU.scala:770:31] wire [4:0] _ex_rs_T = ex_ra_0; // @[FPU.scala:770:31, :832:37] reg [4:0] ex_ra_1; // @[FPU.scala:770:31] wire [4:0] _ex_rs_T_2 = ex_ra_1; // @[FPU.scala:770:31, :832:37] reg [4:0] ex_ra_2; // @[FPU.scala:770:31] wire [4:0] _ex_rs_T_4 = ex_ra_2; // @[FPU.scala:770:31, :832:37] reg load_wb; // @[FPU.scala:773:24] wire frfWriteBundle_0_wrenf = load_wb; // @[FPU.scala:773:24, :805:44] wire [1:0] _load_wb_typeTag_T = io_ll_resp_type_0[1:0]; // @[FPU.scala:735:7, :774:50] wire [2:0] _load_wb_typeTag_T_1 = {1'h0, _load_wb_typeTag_T} - 3'h1; // @[FPU.scala:774:{50,56}] wire [1:0] _load_wb_typeTag_T_2 = _load_wb_typeTag_T_1[1:0]; // @[FPU.scala:774:56] reg [1:0] load_wb_typeTag; // @[FPU.scala:774:34] reg [63:0] load_wb_data; // @[FPU.scala:775:31] reg [4:0] load_wb_tag; // @[FPU.scala:776:30] wire [4:0] frfWriteBundle_0_wrdst = load_wb_tag; // @[FPU.scala:776:30, :805:44] reg mem_reg_valid; // @[FPU.scala:784:30] wire _killm_T = io_killm_0 \| io_nack_mem_0; // @[FPU.scala:735:7, :785:25] wire killm = _killm_T; // @[FPU.scala:785:{25,41}] wire _killx_T = mem_reg_valid & killm; // @[FPU.scala:784:30, :785:41, :789:41] wire killx = io_killx_0 \| _killx_T; // @[FPU.scala:735:7, :789:{24,41}] wire _mem_reg_valid_T = ~killx; // @[FPU.scala:789:24, :790:36] wire _mem_reg_valid_T_1 = ex_reg_valid & _mem_reg_valid_T; // @[FPU.scala:767:29, :790:{33,36}] wire _mem_reg_valid_T_2 = _mem_reg_valid_T_1; // @[FPU.scala:790:{33,43}] reg [31:0] mem_reg_inst; // @[FPU.scala:791:31] wire _wb_reg_valid_T = ~killm; // @[FPU.scala:785:41, :792:48] wire _wb_reg_valid_T_1 = _wb_reg_valid_T; // @[FPU.scala:792:{48,55}] wire _wb_reg_valid_T_2 = mem_reg_valid & _wb_reg_valid_T_1; // @[FPU.scala:784:30, :792:{44,55}] reg wb_reg_valid; // @[FPU.scala:792:29] wire _io_sboard_set_T_1 = wb_reg_valid; // @[FPU.scala:792:29, :1006:33] wire sfma_io_in_bits_req_ldst = ex_ctrl_ldst; // @[FPU.scala:800:20, :848:19] wire fpiu_io_in_bits_req_ldst = ex_ctrl_ldst; // @[FPU.scala:800:20, :848:19] wire dfma_io_in_bits_req_ldst = ex_ctrl_ldst; // @[FPU.scala:800:20, :848:19] wire hfma_io_in_bits_req_ldst = ex_ctrl_ldst; // @[FPU.scala:800:20, :848:19] wire sfma_io_in_bits_req_wen = ex_ctrl_wen; // @[FPU.scala:800:20, :848:19] wire fpiu_io_in_bits_req_wen = ex_ctrl_wen; // @[FPU.scala:800:20, :848:19] wire dfma_io_in_bits_req_wen = ex_ctrl_wen; // @[FPU.scala:800:20, :848:19] wire hfma_io_in_bits_req_wen = ex_ctrl_wen; // @[FPU.scala:800:20, :848:19] wire sfma_io_in_bits_req_ren1 = ex_ctrl_ren1; // @[FPU.scala:800:20, :848:19] wire fpiu_io_in_bits_req_ren1 = ex_ctrl_ren1; // @[FPU.scala:800:20, :848:19] wire dfma_io_in_bits_req_ren1 = ex_ctrl_ren1; // @[FPU.scala:800:20, :848:19] wire hfma_io_in_bits_req_ren1 = ex_ctrl_ren1; // @[FPU.scala:800:20, :848:19] wire sfma_io_in_bits_req_ren2 = ex_ctrl_ren2; // @[FPU.scala:800:20, :848:19] wire fpiu_io_in_bits_req_ren2 = ex_ctrl_ren2; // @[FPU.scala:800:20, :848:19] wire dfma_io_in_bits_req_ren2 = ex_ctrl_ren2; // @[FPU.scala:800:20, :848:19] wire hfma_io_in_bits_req_ren2 = ex_ctrl_ren2; // @[FPU.scala:800:20, :848:19] wire sfma_io_in_bits_req_ren3 = ex_ctrl_ren3; // @[FPU.scala:800:20, :848:19] wire fpiu_io_in_bits_req_ren3 = ex_ctrl_ren3; // @[FPU.scala:800:20, :848:19] wire dfma_io_in_bits_req_ren3 = ex_ctrl_ren3; // @[FPU.scala:800:20, :848:19] wire hfma_io_in_bits_req_ren3 = ex_ctrl_ren3; // @[FPU.scala:800:20, :848:19] wire sfma_io_in_bits_req_swap12 = ex_ctrl_swap12; // @[FPU.scala:800:20, :848:19] wire fpiu_io_in_bits_req_swap12 = ex_ctrl_swap12; // @[FPU.scala:800:20, :848:19] wire dfma_io_in_bits_req_swap12 = ex_ctrl_swap12; // @[FPU.scala:800:20, :848:19] wire hfma_io_in_bits_req_swap12 = ex_ctrl_swap12; // @[FPU.scala:800:20, :848:19] wire sfma_io_in_bits_req_swap23 = ex_ctrl_swap23; // @[FPU.scala:800:20, :848:19] wire fpiu_io_in_bits_req_swap23 = ex_ctrl_swap23; // @[FPU.scala:800:20, :848:19] wire dfma_io_in_bits_req_swap23 = ex_ctrl_swap23; // @[FPU.scala:800:20, :848:19] wire hfma_io_in_bits_req_swap23 = ex_ctrl_swap23; // @[FPU.scala:800:20, :848:19] wire [1:0] sfma_io_in_bits_req_typeTagIn = ex_ctrl_typeTagIn; // @[FPU.scala:800:20, :848:19] wire [1:0] fpiu_io_in_bits_req_typeTagIn = ex_ctrl_typeTagIn; // @[FPU.scala:800:20, :848:19] wire [1:0] dfma_io_in_bits_req_typeTagIn = ex_ctrl_typeTagIn; // @[FPU.scala:800:20, :848:19] wire [1:0] hfma_io_in_bits_req_typeTagIn = ex_ctrl_typeTagIn; // @[FPU.scala:800:20, :848:19] wire [1:0] sfma_io_in_bits_req_typeTagOut = ex_ctrl_typeTagOut; // @[FPU.scala:800:20, :848:19] wire [1:0] fpiu_io_in_bits_req_typeTagOut = ex_ctrl_typeTagOut; // @[FPU.scala:800:20, :848:19] wire [1:0] dfma_io_in_bits_req_typeTagOut = ex_ctrl_typeTagOut; // @[FPU.scala:800:20, :848:19] wire [1:0] hfma_io_in_bits_req_typeTagOut = ex_ctrl_typeTagOut; // @[FPU.scala:800:20, :848:19] wire sfma_io_in_bits_req_fromint = ex_ctrl_fromint; // @[FPU.scala:800:20, :848:19] wire fpiu_io_in_bits_req_fromint = ex_ctrl_fromint; // @[FPU.scala:800:20, :848:19] wire dfma_io_in_bits_req_fromint = ex_ctrl_fromint; // @[FPU.scala:800:20, :848:19] wire hfma_io_in_bits_req_fromint = ex_ctrl_fromint; // @[FPU.scala:800:20, :848:19] wire sfma_io_in_bits_req_toint = ex_ctrl_toint; // @[FPU.scala:800:20, :848:19] wire fpiu_io_in_bits_req_toint = ex_ctrl_toint; // @[FPU.scala:800:20, :848:19] wire dfma_io_in_bits_req_toint = ex_ctrl_toint; // @[FPU.scala:800:20, :848:19] wire hfma_io_in_bits_req_toint = ex_ctrl_toint; // @[FPU.scala:800:20, :848:19] wire sfma_io_in_bits_req_fastpipe = ex_ctrl_fastpipe; // @[FPU.scala:800:20, :848:19] wire fpiu_io_in_bits_req_fastpipe = ex_ctrl_fastpipe; // @[FPU.scala:800:20, :848:19] wire dfma_io_in_bits_req_fastpipe = ex_ctrl_fastpipe; // @[FPU.scala:800:20, :848:19] wire hfma_io_in_bits_req_fastpipe = ex_ctrl_fastpipe; // @[FPU.scala:800:20, :848:19] wire sfma_io_in_bits_req_fma = ex_ctrl_fma; // @[FPU.scala:800:20, :848:19] wire fpiu_io_in_bits_req_fma = ex_ctrl_fma; // @[FPU.scala:800:20, :848:19] wire dfma_io_in_bits_req_fma = ex_ctrl_fma; // @[FPU.scala:800:20, :848:19] wire hfma_io_in_bits_req_fma = ex_ctrl_fma; // @[FPU.scala:800:20, :848:19] wire sfma_io_in_bits_req_div = ex_ctrl_div; // @[FPU.scala:800:20, :848:19] wire fpiu_io_in_bits_req_div = ex_ctrl_div; // @[FPU.scala:800:20, :848:19] wire dfma_io_in_bits_req_div = ex_ctrl_div; // @[FPU.scala:800:20, :848:19] wire hfma_io_in_bits_req_div = ex_ctrl_div; // @[FPU.scala:800:20, :848:19] wire sfma_io_in_bits_req_sqrt = ex_ctrl_sqrt; // @[FPU.scala:800:20, :848:19] wire fpiu_io_in_bits_req_sqrt = ex_ctrl_sqrt; // @[FPU.scala:800:20, :848:19] wire dfma_io_in_bits_req_sqrt = ex_ctrl_sqrt; // @[FPU.scala:800:20, :848:19] wire hfma_io_in_bits_req_sqrt = ex_ctrl_sqrt; // @[FPU.scala:800:20, :848:19] wire sfma_io_in_bits_req_wflags = ex_ctrl_wflags; // @[FPU.scala:800:20, :848:19] wire fpiu_io_in_bits_req_wflags = ex_ctrl_wflags; // @[FPU.scala:800:20, :848:19] wire dfma_io_in_bits_req_wflags = ex_ctrl_wflags; // @[FPU.scala:800:20, :848:19] wire hfma_io_in_bits_req_wflags = ex_ctrl_wflags; // @[FPU.scala:800:20, :848:19] wire sfma_io_in_bits_req_vec = ex_ctrl_vec; // @[FPU.scala:800:20, :848:19] wire fpiu_io_in_bits_req_vec = ex_ctrl_vec; // @[FPU.scala:800:20, :848:19] wire dfma_io_in_bits_req_vec = ex_ctrl_vec; // @[FPU.scala:800:20, :848:19] wire hfma_io_in_bits_req_vec = ex_ctrl_vec; // @[FPU.scala:800:20, :848:19] reg mem_ctrl_ldst; // @[FPU.scala:801:27] reg mem_ctrl_wen; // @[FPU.scala:801:27] reg mem_ctrl_ren1; // @[FPU.scala:801:27] reg mem_ctrl_ren2; // @[FPU.scala:801:27] reg mem_ctrl_ren3; // @[FPU.scala:801:27] reg mem_ctrl_swap12; // @[FPU.scala:801:27] reg mem_ctrl_swap23; // @[FPU.scala:801:27] reg [1:0] mem_ctrl_typeTagIn; // @[FPU.scala:801:27] reg [1:0] mem_ctrl_typeTagOut; // @[FPU.scala:801:27] reg mem_ctrl_fromint; // @[FPU.scala:801:27] wire _memLatencyMask_T_1 = mem_ctrl_fromint; // @[FPU.scala:801:27, :926:23] wire _wbInfo_0_pipeid_T_1 = mem_ctrl_fromint; // @[FPU.scala:801:27, :928:63] wire _wbInfo_1_pipeid_T_1 = mem_ctrl_fromint; // @[FPU.scala:801:27, :928:63] wire _wbInfo_2_pipeid_T_1 = mem_ctrl_fromint; // @[FPU.scala:801:27, :928:63] reg mem_ctrl_toint; // @[FPU.scala:801:27] reg mem_ctrl_fastpipe; // @[FPU.scala:801:27] wire _memLatencyMask_T = mem_ctrl_fastpipe; // @[FPU.scala:801:27, :926:23] reg mem_ctrl_fma; // @[FPU.scala:801:27] reg mem_ctrl_div; // @[FPU.scala:801:27] reg mem_ctrl_sqrt; // @[FPU.scala:801:27] reg mem_ctrl_wflags; // @[FPU.scala:801:27] reg mem_ctrl_vec; // @[FPU.scala:801:27] reg wb_ctrl_ldst; // @[FPU.scala:802:26] reg wb_ctrl_wen; // @[FPU.scala:802:26] reg wb_ctrl_ren1; // @[FPU.scala:802:26] reg wb_ctrl_ren2; // @[FPU.scala:802:26] reg wb_ctrl_ren3; // @[FPU.scala:802:26] reg wb_ctrl_swap12; // @[FPU.scala:802:26] reg wb_ctrl_swap23; // @[FPU.scala:802:26] reg [1:0] wb_ctrl_typeTagIn; // @[FPU.scala:802:26] reg [1:0] wb_ctrl_typeTagOut; // @[FPU.scala:802:26] reg wb_ctrl_fromint; // @[FPU.scala:802:26] reg wb_ctrl_toint; // @[FPU.scala:802:26] reg wb_ctrl_fastpipe; // @[FPU.scala:802:26] reg wb_ctrl_fma; // @[FPU.scala:802:26] reg wb_ctrl_div; // @[FPU.scala:802:26] reg wb_ctrl_sqrt; // @[FPU.scala:802:26] reg wb_ctrl_wflags; // @[FPU.scala:802:26] reg wb_ctrl_vec; // @[FPU.scala:802:26] wire [31:0] _frfWriteBundle_0_timer_T; // @[FPU.scala:810:23] wire [63:0] _frfWriteBundle_0_wrdata_T_5; // @[FPU.scala:446:10] wire [63:0] frfWriteBundle_0_hartid; // @[FPU.scala:805:44] wire [31:0] frfWriteBundle_0_timer; // @[FPU.scala:805:44] wire [63:0] frfWriteBundle_0_wrdata; // @[FPU.scala:805:44] wire [31:0] _frfWriteBundle_1_timer_T; // @[FPU.scala:810:23] wire [63:0] _frfWriteBundle_1_wrdata_T_5; // @[FPU.scala:446:10] wire [63:0] frfWriteBundle_1_hartid; // @[FPU.scala:805:44] wire [31:0] frfWriteBundle_1_timer; // @[FPU.scala:805:44] wire [4:0] frfWriteBundle_1_wrdst; // @[FPU.scala:805:44] wire [63:0] frfWriteBundle_1_wrdata; // @[FPU.scala:805:44] wire frfWriteBundle_1_wrenf; // @[FPU.scala:805:44] wire [63:0] _GEN = {62'h0, io_hartid_0}; // @[FPU.scala:735:7, :809:14] assign frfWriteBundle_0_hartid = _GEN; // @[FPU.scala:805:44, :809:14] assign frfWriteBundle_1_hartid = _GEN; // @[FPU.scala:805:44, :809:14] assign _frfWriteBundle_0_timer_T = io_time_0[31:0]; // @[FPU.scala:735:7, :810:23] assign _frfWriteBundle_1_timer_T = io_time_0[31:0]; // @[FPU.scala:735:7, :810:23] assign frfWriteBundle_0_timer = _frfWriteBundle_0_timer_T; // @[FPU.scala:805:44, :810:23] assign frfWriteBundle_1_timer = _frfWriteBundle_1_timer_T; // @[FPU.scala:805:44, :810:23] wire _wdata_T = load_wb_typeTag == 2'h1; // @[package.scala:39:86] wire [63:0] _wdata_T_1 = _wdata_T ? 64'hFFFFFFFF00000000 : 64'hFFFFFFFFFFFF0000; // @[package.scala:39:{76,86}] wire _wdata_T_2 = load_wb_typeTag == 2'h2; // @[package.scala:39:86] wire [63:0] _wdata_T_3 = _wdata_T_2 ? 64'h0 : _wdata_T_1; // @[package.scala:39:{76,86}] wire _wdata_T_4 = &load_wb_typeTag; // @[package.scala:39:86] wire [63:0] _wdata_T_5 = _wdata_T_4 ? 64'h0 : _wdata_T_3; // @[package.scala:39:{76,86}] wire [63:0] _wdata_T_6 = _wdata_T_5 \| load_wb_data; // @[package.scala:39:76] wire wdata_rawIn_sign = _wdata_T_6[63]; // @[FPU.scala:431:23] wire wdata_rawIn_sign_0 = wdata_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19] wire [10:0] wdata_rawIn_expIn = _wdata_T_6[62:52]; // @[FPU.scala:431:23] wire [51:0] wdata_rawIn_fractIn = _wdata_T_6[51:0]; // @[FPU.scala:431:23] wire wdata_rawIn_isZeroExpIn = wdata_rawIn_expIn == 11'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire wdata_rawIn_isZeroFractIn = wdata_rawIn_fractIn == 52'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _wdata_rawIn_normDist_T = wdata_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_1 = wdata_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_2 = wdata_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_3 = wdata_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_4 = wdata_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_5 = wdata_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_6 = wdata_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_7 = wdata_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_8 = wdata_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_9 = wdata_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_10 = wdata_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_11 = wdata_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_12 = wdata_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_13 = wdata_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_14 = wdata_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_15 = wdata_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_16 = wdata_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_17 = wdata_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_18 = wdata_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_19 = wdata_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_20 = wdata_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_21 = wdata_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_22 = wdata_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_23 = wdata_rawIn_fractIn[23]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_24 = wdata_rawIn_fractIn[24]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_25 = wdata_rawIn_fractIn[25]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_26 = wdata_rawIn_fractIn[26]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_27 = wdata_rawIn_fractIn[27]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_28 = wdata_rawIn_fractIn[28]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_29 = wdata_rawIn_fractIn[29]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_30 = wdata_rawIn_fractIn[30]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_31 = wdata_rawIn_fractIn[31]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_32 = wdata_rawIn_fractIn[32]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_33 = wdata_rawIn_fractIn[33]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_34 = wdata_rawIn_fractIn[34]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_35 = wdata_rawIn_fractIn[35]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_36 = wdata_rawIn_fractIn[36]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_37 = wdata_rawIn_fractIn[37]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_38 = wdata_rawIn_fractIn[38]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_39 = wdata_rawIn_fractIn[39]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_40 = wdata_rawIn_fractIn[40]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_41 = wdata_rawIn_fractIn[41]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_42 = wdata_rawIn_fractIn[42]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_43 = wdata_rawIn_fractIn[43]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_44 = wdata_rawIn_fractIn[44]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_45 = wdata_rawIn_fractIn[45]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_46 = wdata_rawIn_fractIn[46]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_47 = wdata_rawIn_fractIn[47]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_48 = wdata_rawIn_fractIn[48]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_49 = wdata_rawIn_fractIn[49]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_50 = wdata_rawIn_fractIn[50]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_51 = wdata_rawIn_fractIn[51]; // @[rawFloatFromFN.scala:46:21] wire [5:0] _wdata_rawIn_normDist_T_52 = {5'h19, ~_wdata_rawIn_normDist_T_1}; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_53 = _wdata_rawIn_normDist_T_2 ? 6'h31 : _wdata_rawIn_normDist_T_52; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_54 = _wdata_rawIn_normDist_T_3 ? 6'h30 : _wdata_rawIn_normDist_T_53; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_55 = _wdata_rawIn_normDist_T_4 ? 6'h2F : _wdata_rawIn_normDist_T_54; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_56 = _wdata_rawIn_normDist_T_5 ? 6'h2E : _wdata_rawIn_normDist_T_55; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_57 = _wdata_rawIn_normDist_T_6 ? 6'h2D : _wdata_rawIn_normDist_T_56; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_58 = _wdata_rawIn_normDist_T_7 ? 6'h2C : _wdata_rawIn_normDist_T_57; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_59 = _wdata_rawIn_normDist_T_8 ? 6'h2B : _wdata_rawIn_normDist_T_58; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_60 = _wdata_rawIn_normDist_T_9 ? 6'h2A : _wdata_rawIn_normDist_T_59; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_61 = _wdata_rawIn_normDist_T_10 ? 6'h29 : _wdata_rawIn_normDist_T_60; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_62 = _wdata_rawIn_normDist_T_11 ? 6'h28 : _wdata_rawIn_normDist_T_61; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_63 = _wdata_rawIn_normDist_T_12 ? 6'h27 : _wdata_rawIn_normDist_T_62; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_64 = _wdata_rawIn_normDist_T_13 ? 6'h26 : _wdata_rawIn_normDist_T_63; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_65 = _wdata_rawIn_normDist_T_14 ? 6'h25 : _wdata_rawIn_normDist_T_64; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_66 = _wdata_rawIn_normDist_T_15 ? 6'h24 : _wdata_rawIn_normDist_T_65; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_67 = _wdata_rawIn_normDist_T_16 ? 6'h23 : _wdata_rawIn_normDist_T_66; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_68 = _wdata_rawIn_normDist_T_17 ? 6'h22 : _wdata_rawIn_normDist_T_67; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_69 = _wdata_rawIn_normDist_T_18 ? 6'h21 : _wdata_rawIn_normDist_T_68; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_70 = _wdata_rawIn_normDist_T_19 ? 6'h20 : _wdata_rawIn_normDist_T_69; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_71 = _wdata_rawIn_normDist_T_20 ? 6'h1F : _wdata_rawIn_normDist_T_70; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_72 = _wdata_rawIn_normDist_T_21 ? 6'h1E : _wdata_rawIn_normDist_T_71; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_73 = _wdata_rawIn_normDist_T_22 ? 6'h1D : _wdata_rawIn_normDist_T_72; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_74 = _wdata_rawIn_normDist_T_23 ? 6'h1C : _wdata_rawIn_normDist_T_73; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_75 = _wdata_rawIn_normDist_T_24 ? 6'h1B : _wdata_rawIn_normDist_T_74; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_76 = _wdata_rawIn_normDist_T_25 ? 6'h1A : _wdata_rawIn_normDist_T_75; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_77 = _wdata_rawIn_normDist_T_26 ? 6'h19 : _wdata_rawIn_normDist_T_76; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_78 = _wdata_rawIn_normDist_T_27 ? 6'h18 : _wdata_rawIn_normDist_T_77; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_79 = _wdata_rawIn_normDist_T_28 ? 6'h17 : _wdata_rawIn_normDist_T_78; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_80 = _wdata_rawIn_normDist_T_29 ? 6'h16 : _wdata_rawIn_normDist_T_79; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_81 = _wdata_rawIn_normDist_T_30 ? 6'h15 : _wdata_rawIn_normDist_T_80; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_82 = _wdata_rawIn_normDist_T_31 ? 6'h14 : _wdata_rawIn_normDist_T_81; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_83 = _wdata_rawIn_normDist_T_32 ? 6'h13 : _wdata_rawIn_normDist_T_82; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_84 = _wdata_rawIn_normDist_T_33 ? 6'h12 : _wdata_rawIn_normDist_T_83; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_85 = _wdata_rawIn_normDist_T_34 ? 6'h11 : _wdata_rawIn_normDist_T_84; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_86 = _wdata_rawIn_normDist_T_35 ? 6'h10 : _wdata_rawIn_normDist_T_85; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_87 = _wdata_rawIn_normDist_T_36 ? 6'hF : _wdata_rawIn_normDist_T_86; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_88 = _wdata_rawIn_normDist_T_37 ? 6'hE : _wdata_rawIn_normDist_T_87; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_89 = _wdata_rawIn_normDist_T_38 ? 6'hD : _wdata_rawIn_normDist_T_88; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_90 = _wdata_rawIn_normDist_T_39 ? 6'hC : _wdata_rawIn_normDist_T_89; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_91 = _wdata_rawIn_normDist_T_40 ? 6'hB : _wdata_rawIn_normDist_T_90; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_92 = _wdata_rawIn_normDist_T_41 ? 6'hA : _wdata_rawIn_normDist_T_91; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_93 = _wdata_rawIn_normDist_T_42 ? 6'h9 : _wdata_rawIn_normDist_T_92; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_94 = _wdata_rawIn_normDist_T_43 ? 6'h8 : _wdata_rawIn_normDist_T_93; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_95 = _wdata_rawIn_normDist_T_44 ? 6'h7 : _wdata_rawIn_normDist_T_94; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_96 = _wdata_rawIn_normDist_T_45 ? 6'h6 : _wdata_rawIn_normDist_T_95; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_97 = _wdata_rawIn_normDist_T_46 ? 6'h5 : _wdata_rawIn_normDist_T_96; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_98 = _wdata_rawIn_normDist_T_47 ? 6'h4 : _wdata_rawIn_normDist_T_97; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_99 = _wdata_rawIn_normDist_T_48 ? 6'h3 : _wdata_rawIn_normDist_T_98; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_100 = _wdata_rawIn_normDist_T_49 ? 6'h2 : _wdata_rawIn_normDist_T_99; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_101 = _wdata_rawIn_normDist_T_50 ? 6'h1 : _wdata_rawIn_normDist_T_100; // @[Mux.scala:50:70] wire [5:0] wdata_rawIn_normDist = _wdata_rawIn_normDist_T_51 ? 6'h0 : _wdata_rawIn_normDist_T_101; // @[Mux.scala:50:70] wire [114:0] _wdata_rawIn_subnormFract_T = {63'h0, wdata_rawIn_fractIn} << wdata_rawIn_normDist; // @[Mux.scala:50:70] wire [50:0] _wdata_rawIn_subnormFract_T_1 = _wdata_rawIn_subnormFract_T[50:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [51:0] wdata_rawIn_subnormFract = {_wdata_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [11:0] _wdata_rawIn_adjustedExp_T = {6'h3F, ~wdata_rawIn_normDist}; // @[Mux.scala:50:70] wire [11:0] _wdata_rawIn_adjustedExp_T_1 = wdata_rawIn_isZeroExpIn ? _wdata_rawIn_adjustedExp_T : {1'h0, wdata_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _wdata_rawIn_adjustedExp_T_2 = wdata_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [10:0] _wdata_rawIn_adjustedExp_T_3 = {9'h100, _wdata_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}] wire [12:0] _wdata_rawIn_adjustedExp_T_4 = {1'h0, _wdata_rawIn_adjustedExp_T_1} + {2'h0, _wdata_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [11:0] wdata_rawIn_adjustedExp = _wdata_rawIn_adjustedExp_T_4[11:0]; // @[rawFloatFromFN.scala:57:9] wire [11:0] _wdata_rawIn_out_sExp_T = wdata_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28] wire wdata_rawIn_isZero = wdata_rawIn_isZeroExpIn & wdata_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire wdata_rawIn_isZero_0 = wdata_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _wdata_rawIn_isSpecial_T = wdata_rawIn_adjustedExp[11:10]; // @[rawFloatFromFN.scala:57:9, :61:32] wire wdata_rawIn_isSpecial = &_wdata_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}] wire _wdata_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28] wire _wdata_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28] wire _wdata_T_9 = wdata_rawIn_isNaN; // @[recFNFromFN.scala:49:20] wire [12:0] _wdata_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42] wire [53:0] _wdata_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27] wire wdata_rawIn_isInf; // @[rawFloatFromFN.scala:63:19] wire [12:0] wdata_rawIn_sExp; // @[rawFloatFromFN.scala:63:19] wire [53:0] wdata_rawIn_sig; // @[rawFloatFromFN.scala:63:19] wire _wdata_rawIn_out_isNaN_T = ~wdata_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31] assign _wdata_rawIn_out_isNaN_T_1 = wdata_rawIn_isSpecial & _wdata_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign wdata_rawIn_isNaN = _wdata_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28] assign _wdata_rawIn_out_isInf_T = wdata_rawIn_isSpecial & wdata_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign wdata_rawIn_isInf = _wdata_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28] assign _wdata_rawIn_out_sExp_T_1 = {1'h0, _wdata_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}] assign wdata_rawIn_sExp = _wdata_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42] wire _wdata_rawIn_out_sig_T = ~wdata_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _wdata_rawIn_out_sig_T_1 = {1'h0, _wdata_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}] wire [51:0] _wdata_rawIn_out_sig_T_2 = wdata_rawIn_isZeroExpIn ? wdata_rawIn_subnormFract : wdata_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _wdata_rawIn_out_sig_T_3 = {_wdata_rawIn_out_sig_T_1, _wdata_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign wdata_rawIn_sig = _wdata_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _wdata_T_7 = wdata_rawIn_sExp[11:9]; // @[recFNFromFN.scala:48:50] wire [2:0] _wdata_T_8 = wdata_rawIn_isZero_0 ? 3'h0 : _wdata_T_7; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _wdata_T_10 = {_wdata_T_8[2:1], _wdata_T_8[0] \| _wdata_T_9}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _wdata_T_11 = {wdata_rawIn_sign_0, _wdata_T_10}; // @[recFNFromFN.scala:47:20, :48:76] wire [8:0] _wdata_T_12 = wdata_rawIn_sExp[8:0]; // @[recFNFromFN.scala:50:23] wire [12:0] _wdata_T_13 = {_wdata_T_11, _wdata_T_12}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [51:0] _wdata_T_14 = wdata_rawIn_sig[51:0]; // @[recFNFromFN.scala:51:22] wire [64:0] _wdata_T_15 = {_wdata_T_13, _wdata_T_14}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire wdata_rawIn_sign_1 = _wdata_T_6[31]; // @[FPU.scala:431:23] wire wdata_rawIn_1_sign = wdata_rawIn_sign_1; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] wdata_rawIn_expIn_1 = _wdata_T_6[30:23]; // @[FPU.scala:431:23] wire [22:0] wdata_rawIn_fractIn_1 = _wdata_T_6[22:0]; // @[FPU.scala:431:23] wire wdata_rawIn_isZeroExpIn_1 = wdata_rawIn_expIn_1 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire wdata_rawIn_isZeroFractIn_1 = wdata_rawIn_fractIn_1 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _wdata_rawIn_normDist_T_102 = wdata_rawIn_fractIn_1[0]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_103 = wdata_rawIn_fractIn_1[1]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_104 = wdata_rawIn_fractIn_1[2]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_105 = wdata_rawIn_fractIn_1[3]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_106 = wdata_rawIn_fractIn_1[4]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_107 = wdata_rawIn_fractIn_1[5]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_108 = wdata_rawIn_fractIn_1[6]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_109 = wdata_rawIn_fractIn_1[7]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_110 = wdata_rawIn_fractIn_1[8]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_111 = wdata_rawIn_fractIn_1[9]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_112 = wdata_rawIn_fractIn_1[10]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_113 = wdata_rawIn_fractIn_1[11]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_114 = wdata_rawIn_fractIn_1[12]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_115 = wdata_rawIn_fractIn_1[13]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_116 = wdata_rawIn_fractIn_1[14]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_117 = wdata_rawIn_fractIn_1[15]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_118 = wdata_rawIn_fractIn_1[16]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_119 = wdata_rawIn_fractIn_1[17]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_120 = wdata_rawIn_fractIn_1[18]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_121 = wdata_rawIn_fractIn_1[19]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_122 = wdata_rawIn_fractIn_1[20]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_123 = wdata_rawIn_fractIn_1[21]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_124 = wdata_rawIn_fractIn_1[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _wdata_rawIn_normDist_T_125 = _wdata_rawIn_normDist_T_103 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _wdata_rawIn_normDist_T_126 = _wdata_rawIn_normDist_T_104 ? 5'h14 : _wdata_rawIn_normDist_T_125; // @[Mux.scala:50:70] wire [4:0] _wdata_rawIn_normDist_T_127 = _wdata_rawIn_normDist_T_105 ? 5'h13 : _wdata_rawIn_normDist_T_126; // @[Mux.scala:50:70] wire [4:0] _wdata_rawIn_normDist_T_128 = _wdata_rawIn_normDist_T_106 ? 5'h12 : _wdata_rawIn_normDist_T_127; // @[Mux.scala:50:70] wire [4:0] _wdata_rawIn_normDist_T_129 = _wdata_rawIn_normDist_T_107 ? 5'h11 : _wdata_rawIn_normDist_T_128; // @[Mux.scala:50:70] wire [4:0] _wdata_rawIn_normDist_T_130 = _wdata_rawIn_normDist_T_108 ? 5'h10 : _wdata_rawIn_normDist_T_129; // @[Mux.scala:50:70] wire [4:0] _wdata_rawIn_normDist_T_131 = _wdata_rawIn_normDist_T_109 ? 5'hF : _wdata_rawIn_normDist_T_130; // @[Mux.scala:50:70] wire [4:0] _wdata_rawIn_normDist_T_132 = _wdata_rawIn_normDist_T_110 ? 5'hE : _wdata_rawIn_normDist_T_131; // @[Mux.scala:50:70] wire [4:0] _wdata_rawIn_normDist_T_133 = _wdata_rawIn_normDist_T_111 ? 5'hD : _wdata_rawIn_normDist_T_132; // @[Mux.scala:50:70] wire [4:0] _wdata_rawIn_normDist_T_134 = _wdata_rawIn_normDist_T_112 ? 5'hC : _wdata_rawIn_normDist_T_133; // @[Mux.scala:50:70] wire [4:0] _wdata_rawIn_normDist_T_135 = _wdata_rawIn_normDist_T_113 ? 5'hB : _wdata_rawIn_normDist_T_134; // @[Mux.scala:50:70] wire [4:0] _wdata_rawIn_normDist_T_136 = _wdata_rawIn_normDist_T_114 ? 5'hA : _wdata_rawIn_normDist_T_135; // @[Mux.scala:50:70] wire [4:0] _wdata_rawIn_normDist_T_137 = _wdata_rawIn_normDist_T_115 ? 5'h9 : _wdata_rawIn_normDist_T_136; // @[Mux.scala:50:70] wire [4:0] _wdata_rawIn_normDist_T_138 = _wdata_rawIn_normDist_T_116 ? 5'h8 : _wdata_rawIn_normDist_T_137; // @[Mux.scala:50:70] wire [4:0] _wdata_rawIn_normDist_T_139 = _wdata_rawIn_normDist_T_117 ? 5'h7 : _wdata_rawIn_normDist_T_138; // @[Mux.scala:50:70] wire [4:0] _wdata_rawIn_normDist_T_140 = _wdata_rawIn_normDist_T_118 ? 5'h6 : _wdata_rawIn_normDist_T_139; // @[Mux.scala:50:70] wire [4:0] _wdata_rawIn_normDist_T_141 = _wdata_rawIn_normDist_T_119 ? 5'h5 : _wdata_rawIn_normDist_T_140; // @[Mux.scala:50:70] wire [4:0] _wdata_rawIn_normDist_T_142 = _wdata_rawIn_normDist_T_120 ? 5'h4 : _wdata_rawIn_normDist_T_141; // @[Mux.scala:50:70] wire [4:0] _wdata_rawIn_normDist_T_143 = _wdata_rawIn_normDist_T_121 ? 5'h3 : _wdata_rawIn_normDist_T_142; // @[Mux.scala:50:70] wire [4:0] _wdata_rawIn_normDist_T_144 = _wdata_rawIn_normDist_T_122 ? 5'h2 : _wdata_rawIn_normDist_T_143; // @[Mux.scala:50:70] wire [4:0] _wdata_rawIn_normDist_T_145 = _wdata_rawIn_normDist_T_123 ? 5'h1 : _wdata_rawIn_normDist_T_144; // @[Mux.scala:50:70] wire [4:0] wdata_rawIn_normDist_1 = _wdata_rawIn_normDist_T_124 ? 5'h0 : _wdata_rawIn_normDist_T_145; // @[Mux.scala:50:70] wire [53:0] _wdata_rawIn_subnormFract_T_2 = {31'h0, wdata_rawIn_fractIn_1} << wdata_rawIn_normDist_1; // @[Mux.scala:50:70] wire [21:0] _wdata_rawIn_subnormFract_T_3 = _wdata_rawIn_subnormFract_T_2[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] wdata_rawIn_subnormFract_1 = {_wdata_rawIn_subnormFract_T_3, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _wdata_rawIn_adjustedExp_T_5 = {4'hF, ~wdata_rawIn_normDist_1}; // @[Mux.scala:50:70] wire [8:0] _wdata_rawIn_adjustedExp_T_6 = wdata_rawIn_isZeroExpIn_1 ? _wdata_rawIn_adjustedExp_T_5 : {1'h0, wdata_rawIn_expIn_1}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _wdata_rawIn_adjustedExp_T_7 = wdata_rawIn_isZeroExpIn_1 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _wdata_rawIn_adjustedExp_T_8 = {6'h20, _wdata_rawIn_adjustedExp_T_7}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _wdata_rawIn_adjustedExp_T_9 = {1'h0, _wdata_rawIn_adjustedExp_T_6} + {2'h0, _wdata_rawIn_adjustedExp_T_8}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [8:0] wdata_rawIn_adjustedExp_1 = _wdata_rawIn_adjustedExp_T_9[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _wdata_rawIn_out_sExp_T_2 = wdata_rawIn_adjustedExp_1; // @[rawFloatFromFN.scala:57:9, :68:28] wire wdata_rawIn_isZero_1 = wdata_rawIn_isZeroExpIn_1 & wdata_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire wdata_rawIn_1_isZero = wdata_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _wdata_rawIn_isSpecial_T_1 = wdata_rawIn_adjustedExp_1[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire wdata_rawIn_isSpecial_1 = &_wdata_rawIn_isSpecial_T_1; // @[rawFloatFromFN.scala:61:{32,57}] wire _wdata_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:64:28] wire _wdata_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:65:28] wire _wdata_T_18 = wdata_rawIn_1_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _wdata_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:68:42] wire [24:0] _wdata_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:70:27] wire wdata_rawIn_1_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] wdata_rawIn_1_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] wdata_rawIn_1_sig; // @[rawFloatFromFN.scala:63:19] wire _wdata_rawIn_out_isNaN_T_2 = ~wdata_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :64:31] assign _wdata_rawIn_out_isNaN_T_3 = wdata_rawIn_isSpecial_1 & _wdata_rawIn_out_isNaN_T_2; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign wdata_rawIn_1_isNaN = _wdata_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:63:19, :64:28] assign _wdata_rawIn_out_isInf_T_1 = wdata_rawIn_isSpecial_1 & wdata_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign wdata_rawIn_1_isInf = _wdata_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:63:19, :65:28] assign _wdata_rawIn_out_sExp_T_3 = {1'h0, _wdata_rawIn_out_sExp_T_2}; // @[rawFloatFromFN.scala:68:{28,42}] assign wdata_rawIn_1_sExp = _wdata_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:63:19, :68:42] wire _wdata_rawIn_out_sig_T_4 = ~wdata_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _wdata_rawIn_out_sig_T_5 = {1'h0, _wdata_rawIn_out_sig_T_4}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _wdata_rawIn_out_sig_T_6 = wdata_rawIn_isZeroExpIn_1 ? wdata_rawIn_subnormFract_1 : wdata_rawIn_fractIn_1; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _wdata_rawIn_out_sig_T_7 = {_wdata_rawIn_out_sig_T_5, _wdata_rawIn_out_sig_T_6}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign wdata_rawIn_1_sig = _wdata_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _wdata_T_16 = wdata_rawIn_1_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _wdata_T_17 = wdata_rawIn_1_isZero ? 3'h0 : _wdata_T_16; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _wdata_T_19 = {_wdata_T_17[2:1], _wdata_T_17[0] \| _wdata_T_18}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _wdata_T_20 = {wdata_rawIn_1_sign, _wdata_T_19}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _wdata_T_21 = wdata_rawIn_1_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _wdata_T_22 = {_wdata_T_20, _wdata_T_21}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _wdata_T_23 = wdata_rawIn_1_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] _wdata_T_24 = {_wdata_T_22, _wdata_T_23}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire wdata_rawIn_sign_2 = _wdata_T_6[15]; // @[FPU.scala:431:23] wire wdata_rawIn_2_sign = wdata_rawIn_sign_2; // @[rawFloatFromFN.scala:44:18, :63:19] wire [4:0] wdata_rawIn_expIn_2 = _wdata_T_6[14:10]; // @[FPU.scala:431:23] wire [9:0] wdata_rawIn_fractIn_2 = _wdata_T_6[9:0]; // @[FPU.scala:431:23] wire wdata_rawIn_isZeroExpIn_2 = wdata_rawIn_expIn_2 == 5'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire wdata_rawIn_isZeroFractIn_2 = wdata_rawIn_fractIn_2 == 10'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _wdata_rawIn_normDist_T_146 = wdata_rawIn_fractIn_2[0]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_147 = wdata_rawIn_fractIn_2[1]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_148 = wdata_rawIn_fractIn_2[2]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_149 = wdata_rawIn_fractIn_2[3]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_150 = wdata_rawIn_fractIn_2[4]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_151 = wdata_rawIn_fractIn_2[5]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_152 = wdata_rawIn_fractIn_2[6]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_153 = wdata_rawIn_fractIn_2[7]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_154 = wdata_rawIn_fractIn_2[8]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_155 = wdata_rawIn_fractIn_2[9]; // @[rawFloatFromFN.scala:46:21] wire [3:0] _wdata_rawIn_normDist_T_156 = {3'h4, ~_wdata_rawIn_normDist_T_147}; // @[Mux.scala:50:70] wire [3:0] _wdata_rawIn_normDist_T_157 = _wdata_rawIn_normDist_T_148 ? 4'h7 : _wdata_rawIn_normDist_T_156; // @[Mux.scala:50:70] wire [3:0] _wdata_rawIn_normDist_T_158 = _wdata_rawIn_normDist_T_149 ? 4'h6 : _wdata_rawIn_normDist_T_157; // @[Mux.scala:50:70] wire [3:0] _wdata_rawIn_normDist_T_159 = _wdata_rawIn_normDist_T_150 ? 4'h5 : _wdata_rawIn_normDist_T_158; // @[Mux.scala:50:70] wire [3:0] _wdata_rawIn_normDist_T_160 = _wdata_rawIn_normDist_T_151 ? 4'h4 : _wdata_rawIn_normDist_T_159; // @[Mux.scala:50:70] wire [3:0] _wdata_rawIn_normDist_T_161 = _wdata_rawIn_normDist_T_152 ? 4'h3 : _wdata_rawIn_normDist_T_160; // @[Mux.scala:50:70] wire [3:0] _wdata_rawIn_normDist_T_162 = _wdata_rawIn_normDist_T_153 ? 4'h2 : _wdata_rawIn_normDist_T_161; // @[Mux.scala:50:70] wire [3:0] _wdata_rawIn_normDist_T_163 = _wdata_rawIn_normDist_T_154 ? 4'h1 : _wdata_rawIn_normDist_T_162; // @[Mux.scala:50:70] wire [3:0] wdata_rawIn_normDist_2 = _wdata_rawIn_normDist_T_155 ? 4'h0 : _wdata_rawIn_normDist_T_163; // @[Mux.scala:50:70] wire [24:0] _wdata_rawIn_subnormFract_T_4 = {15'h0, wdata_rawIn_fractIn_2} << wdata_rawIn_normDist_2; // @[Mux.scala:50:70] wire [8:0] _wdata_rawIn_subnormFract_T_5 = _wdata_rawIn_subnormFract_T_4[8:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [9:0] wdata_rawIn_subnormFract_2 = {_wdata_rawIn_subnormFract_T_5, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [5:0] _wdata_rawIn_adjustedExp_T_10 = {2'h3, ~wdata_rawIn_normDist_2}; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_adjustedExp_T_11 = wdata_rawIn_isZeroExpIn_2 ? _wdata_rawIn_adjustedExp_T_10 : {1'h0, wdata_rawIn_expIn_2}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _wdata_rawIn_adjustedExp_T_12 = wdata_rawIn_isZeroExpIn_2 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [4:0] _wdata_rawIn_adjustedExp_T_13 = {3'h4, _wdata_rawIn_adjustedExp_T_12}; // @[rawFloatFromFN.scala:58:{9,14}] wire [6:0] _wdata_rawIn_adjustedExp_T_14 = {1'h0, _wdata_rawIn_adjustedExp_T_11} + {2'h0, _wdata_rawIn_adjustedExp_T_13}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [5:0] wdata_rawIn_adjustedExp_2 = _wdata_rawIn_adjustedExp_T_14[5:0]; // @[rawFloatFromFN.scala:57:9] wire [5:0] _wdata_rawIn_out_sExp_T_4 = wdata_rawIn_adjustedExp_2; // @[rawFloatFromFN.scala:57:9, :68:28] wire wdata_rawIn_isZero_2 = wdata_rawIn_isZeroExpIn_2 & wdata_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire wdata_rawIn_2_isZero = wdata_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _wdata_rawIn_isSpecial_T_2 = wdata_rawIn_adjustedExp_2[5:4]; // @[rawFloatFromFN.scala:57:9, :61:32] wire wdata_rawIn_isSpecial_2 = &_wdata_rawIn_isSpecial_T_2; // @[rawFloatFromFN.scala:61:{32,57}] wire _wdata_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:64:28] wire _wdata_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:65:28] wire _wdata_T_27 = wdata_rawIn_2_isNaN; // @[recFNFromFN.scala:49:20] wire [6:0] _wdata_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:68:42] wire [11:0] _wdata_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:70:27] wire wdata_rawIn_2_isInf; // @[rawFloatFromFN.scala:63:19] wire [6:0] wdata_rawIn_2_sExp; // @[rawFloatFromFN.scala:63:19] wire [11:0] wdata_rawIn_2_sig; // @[rawFloatFromFN.scala:63:19] wire _wdata_rawIn_out_isNaN_T_4 = ~wdata_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :64:31] assign _wdata_rawIn_out_isNaN_T_5 = wdata_rawIn_isSpecial_2 & _wdata_rawIn_out_isNaN_T_4; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign wdata_rawIn_2_isNaN = _wdata_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:63:19, :64:28] assign _wdata_rawIn_out_isInf_T_2 = wdata_rawIn_isSpecial_2 & wdata_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign wdata_rawIn_2_isInf = _wdata_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:63:19, :65:28] assign _wdata_rawIn_out_sExp_T_5 = {1'h0, _wdata_rawIn_out_sExp_T_4}; // @[rawFloatFromFN.scala:68:{28,42}] assign wdata_rawIn_2_sExp = _wdata_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:63:19, :68:42] wire _wdata_rawIn_out_sig_T_8 = ~wdata_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _wdata_rawIn_out_sig_T_9 = {1'h0, _wdata_rawIn_out_sig_T_8}; // @[rawFloatFromFN.scala:70:{16,19}] wire [9:0] _wdata_rawIn_out_sig_T_10 = wdata_rawIn_isZeroExpIn_2 ? wdata_rawIn_subnormFract_2 : wdata_rawIn_fractIn_2; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _wdata_rawIn_out_sig_T_11 = {_wdata_rawIn_out_sig_T_9, _wdata_rawIn_out_sig_T_10}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign wdata_rawIn_2_sig = _wdata_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _wdata_T_25 = wdata_rawIn_2_sExp[5:3]; // @[recFNFromFN.scala:48:50] wire [2:0] _wdata_T_26 = wdata_rawIn_2_isZero ? 3'h0 : _wdata_T_25; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _wdata_T_28 = {_wdata_T_26[2:1], _wdata_T_26[0] \| _wdata_T_27}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _wdata_T_29 = {wdata_rawIn_2_sign, _wdata_T_28}; // @[recFNFromFN.scala:47:20, :48:76] wire [2:0] _wdata_T_30 = wdata_rawIn_2_sExp[2:0]; // @[recFNFromFN.scala:50:23] wire [6:0] _wdata_T_31 = {_wdata_T_29, _wdata_T_30}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [9:0] _wdata_T_32 = wdata_rawIn_2_sig[9:0]; // @[recFNFromFN.scala:51:22] wire [16:0] _wdata_T_33 = {_wdata_T_31, _wdata_T_32}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [3:0] _wdata_swizzledNaN_T = _wdata_T_24[32:29]; // @[FPU.scala:337:8] wire [6:0] _wdata_swizzledNaN_T_1 = _wdata_T_24[22:16]; // @[FPU.scala:338:8] wire [6:0] _wdata_swizzledNaN_T_5 = _wdata_T_24[22:16]; // @[FPU.scala:338:8, :341:8] wire _wdata_swizzledNaN_T_2 = &_wdata_swizzledNaN_T_1; // @[FPU.scala:338:{8,42}] wire [3:0] _wdata_swizzledNaN_T_3 = _wdata_T_24[27:24]; // @[FPU.scala:339:8] wire _wdata_swizzledNaN_T_4 = _wdata_T_33[15]; // @[FPU.scala:340:8] wire _wdata_swizzledNaN_T_6 = _wdata_T_33[16]; // @[FPU.scala:342:8] wire [14:0] _wdata_swizzledNaN_T_7 = _wdata_T_33[14:0]; // @[FPU.scala:343:8] wire [7:0] wdata_swizzledNaN_lo_hi = {_wdata_swizzledNaN_T_5, _wdata_swizzledNaN_T_6}; // @[FPU.scala:336:26, :341:8, :342:8] wire [22:0] wdata_swizzledNaN_lo = {wdata_swizzledNaN_lo_hi, _wdata_swizzledNaN_T_7}; // @[FPU.scala:336:26, :343:8] wire [4:0] wdata_swizzledNaN_hi_lo = {_wdata_swizzledNaN_T_3, _wdata_swizzledNaN_T_4}; // @[FPU.scala:336:26, :339:8, :340:8] wire [4:0] wdata_swizzledNaN_hi_hi = {_wdata_swizzledNaN_T, _wdata_swizzledNaN_T_2}; // @[FPU.scala:336:26, :337:8, :338:42] wire [9:0] wdata_swizzledNaN_hi = {wdata_swizzledNaN_hi_hi, wdata_swizzledNaN_hi_lo}; // @[FPU.scala:336:26] wire [32:0] wdata_swizzledNaN = {wdata_swizzledNaN_hi, wdata_swizzledNaN_lo}; // @[FPU.scala:336:26] wire [2:0] _wdata_T_34 = _wdata_T_24[31:29]; // @[FPU.scala:249:25] wire _wdata_T_35 = &_wdata_T_34; // @[FPU.scala:249:{25,56}] wire [32:0] _wdata_T_36 = _wdata_T_35 ? wdata_swizzledNaN : _wdata_T_24; // @[FPU.scala:249:56, :336:26, :344:8] wire [3:0] _wdata_swizzledNaN_T_8 = _wdata_T_15[64:61]; // @[FPU.scala:337:8] wire [19:0] _wdata_swizzledNaN_T_9 = _wdata_T_15[51:32]; // @[FPU.scala:338:8] wire [19:0] _wdata_swizzledNaN_T_13 = _wdata_T_15[51:32]; // @[FPU.scala:338:8, :341:8] wire _wdata_swizzledNaN_T_10 = &_wdata_swizzledNaN_T_9; // @[FPU.scala:338:{8,42}] wire [6:0] _wdata_swizzledNaN_T_11 = _wdata_T_15[59:53]; // @[FPU.scala:339:8] wire _wdata_swizzledNaN_T_12 = _wdata_T_36[31]; // @[FPU.scala:340:8, :344:8] wire _wdata_swizzledNaN_T_14 = _wdata_T_36[32]; // @[FPU.scala:342:8, :344:8] wire [30:0] _wdata_swizzledNaN_T_15 = _wdata_T_36[30:0]; // @[FPU.scala:343:8, :344:8] wire [20:0] wdata_swizzledNaN_lo_hi_1 = {_wdata_swizzledNaN_T_13, _wdata_swizzledNaN_T_14}; // @[FPU.scala:336:26, :341:8, :342:8] wire [51:0] wdata_swizzledNaN_lo_1 = {wdata_swizzledNaN_lo_hi_1, _wdata_swizzledNaN_T_15}; // @[FPU.scala:336:26, :343:8] wire [7:0] wdata_swizzledNaN_hi_lo_1 = {_wdata_swizzledNaN_T_11, _wdata_swizzledNaN_T_12}; // @[FPU.scala:336:26, :339:8, :340:8] wire [4:0] wdata_swizzledNaN_hi_hi_1 = {_wdata_swizzledNaN_T_8, _wdata_swizzledNaN_T_10}; // @[FPU.scala:336:26, :337:8, :338:42] wire [12:0] wdata_swizzledNaN_hi_1 = {wdata_swizzledNaN_hi_hi_1, wdata_swizzledNaN_hi_lo_1}; // @[FPU.scala:336:26] wire [64:0] wdata_swizzledNaN_1 = {wdata_swizzledNaN_hi_1, wdata_swizzledNaN_lo_1}; // @[FPU.scala:336:26] wire [2:0] _wdata_T_37 = _wdata_T_15[63:61]; // @[FPU.scala:249:25] wire _wdata_T_38 = &_wdata_T_37; // @[FPU.scala:249:{25,56}] wire [64:0] wdata = _wdata_T_38 ? wdata_swizzledNaN_1 : _wdata_T_15; // @[FPU.scala:249:56, :336:26, :344:8] wire _unswizzled_T = wdata[31]; // @[FPU.scala:344:8, :381:10] wire _frfWriteBundle_0_wrdata_prevRecoded_T = wdata[31]; // @[FPU.scala:344:8, :381:10, :442:10] wire _unswizzled_T_1 = wdata[52]; // @[FPU.scala:344:8, :382:10] wire _frfWriteBundle_0_wrdata_prevRecoded_T_1 = wdata[52]; // @[FPU.scala:344:8, :382:10, :443:10] wire [30:0] _unswizzled_T_2 = wdata[30:0]; // @[FPU.scala:344:8, :383:10] wire [30:0] _frfWriteBundle_0_wrdata_prevRecoded_T_2 = wdata[30:0]; // @[FPU.scala:344:8, :383:10, :444:10] wire [1:0] unswizzled_hi = {_unswizzled_T, _unswizzled_T_1}; // @[FPU.scala:380:27, :381:10, :382:10] wire [32:0] unswizzled = {unswizzled_hi, _unswizzled_T_2}; // @[FPU.scala:380:27, :383:10] wire [4:0] _prevOK_T = wdata[64:60]; // @[FPU.scala:332:49, :344:8] wire _prevOK_T_1 = &_prevOK_T; // @[FPU.scala:332:{49,84}] wire _prevOK_T_2 = ~_prevOK_T_1; // @[FPU.scala:332:84, :384:20] wire _prevOK_unswizzled_T = unswizzled[15]; // @[FPU.scala:380:27, :381:10] wire _prevOK_unswizzled_T_1 = unswizzled[23]; // @[FPU.scala:380:27, :382:10] wire [14:0] _prevOK_unswizzled_T_2 = unswizzled[14:0]; // @[FPU.scala:380:27, :383:10] wire [1:0] prevOK_unswizzled_hi = {_prevOK_unswizzled_T, _prevOK_unswizzled_T_1}; // @[FPU.scala:380:27, :381:10, :382:10] wire [16:0] prevOK_unswizzled = {prevOK_unswizzled_hi, _prevOK_unswizzled_T_2}; // @[FPU.scala:380:27, :383:10] wire [4:0] _prevOK_prevOK_T = unswizzled[32:28]; // @[FPU.scala:332:49, :380:27] wire _prevOK_prevOK_T_1 = &_prevOK_prevOK_T; // @[FPU.scala:332:{49,84}] wire _prevOK_prevOK_T_2 = ~_prevOK_prevOK_T_1; // @[FPU.scala:332:84, :384:20] wire [2:0] _prevOK_curOK_T = unswizzled[31:29]; // @[FPU.scala:249:25, :380:27] wire _prevOK_curOK_T_1 = &_prevOK_curOK_T; // @[FPU.scala:249:{25,56}] wire _prevOK_curOK_T_2 = ~_prevOK_curOK_T_1; // @[FPU.scala:249:56, :385:19] wire _prevOK_curOK_T_3 = unswizzled[28]; // @[FPU.scala:380:27, :385:35] wire [6:0] _prevOK_curOK_T_4 = unswizzled[22:16]; // @[FPU.scala:380:27, :385:60] wire _prevOK_curOK_T_5 = &_prevOK_curOK_T_4; // @[FPU.scala:385:{60,96}] wire _prevOK_curOK_T_6 = _prevOK_curOK_T_3 == _prevOK_curOK_T_5; // @[FPU.scala:385:{35,55,96}] wire prevOK_curOK = _prevOK_curOK_T_2 \| _prevOK_curOK_T_6; // @[FPU.scala:385:{19,31,55}] wire _prevOK_T_3 = prevOK_curOK; // @[FPU.scala:385:31, :386:14] wire prevOK = _prevOK_T_2 \| _prevOK_T_3; // @[FPU.scala:384:{20,33}, :386:14] wire [2:0] _curOK_T = wdata[63:61]; // @[FPU.scala:249:25, :344:8] wire [2:0] _frfWriteBundle_0_wrdata_T_1 = wdata[63:61]; // @[FPU.scala:249:25, :344:8] wire _curOK_T_1 = &_curOK_T; // @[FPU.scala:249:{25,56}] wire _curOK_T_2 = ~_curOK_T_1; // @[FPU.scala:249:56, :385:19] wire _curOK_T_3 = wdata[60]; // @[FPU.scala:344:8, :385:35] wire [19:0] _curOK_T_4 = wdata[51:32]; // @[FPU.scala:344:8, :385:60] wire _curOK_T_5 = &_curOK_T_4; // @[FPU.scala:385:{60,96}] wire _curOK_T_6 = _curOK_T_3 == _curOK_T_5; // @[FPU.scala:385:{35,55,96}] wire curOK = _curOK_T_2 \| _curOK_T_6; // @[FPU.scala:385:{19,31,55}] wire [11:0] frfWriteBundle_0_wrdata_unrecoded_rawIn_exp = wdata[63:52]; // @[FPU.scala:344:8] wire [2:0] _frfWriteBundle_0_wrdata_unrecoded_rawIn_isZero_T = frfWriteBundle_0_wrdata_unrecoded_rawIn_exp[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire frfWriteBundle_0_wrdata_unrecoded_rawIn_isZero = _frfWriteBundle_0_wrdata_unrecoded_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire frfWriteBundle_0_wrdata_unrecoded_rawIn_isZero_0 = frfWriteBundle_0_wrdata_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _frfWriteBundle_0_wrdata_unrecoded_rawIn_isSpecial_T = frfWriteBundle_0_wrdata_unrecoded_rawIn_exp[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire frfWriteBundle_0_wrdata_unrecoded_rawIn_isSpecial = &_frfWriteBundle_0_wrdata_unrecoded_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [12:0] _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [53:0] _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire frfWriteBundle_0_wrdata_unrecoded_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire frfWriteBundle_0_wrdata_unrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire frfWriteBundle_0_wrdata_unrecoded_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [12:0] frfWriteBundle_0_wrdata_unrecoded_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [53:0] frfWriteBundle_0_wrdata_unrecoded_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_isNaN_T = frfWriteBundle_0_wrdata_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_isInf_T = frfWriteBundle_0_wrdata_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_isNaN_T_1 = frfWriteBundle_0_wrdata_unrecoded_rawIn_isSpecial & _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign frfWriteBundle_0_wrdata_unrecoded_rawIn_isNaN = _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_isInf_T_1 = ~_frfWriteBundle_0_wrdata_unrecoded_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_isInf_T_2 = frfWriteBundle_0_wrdata_unrecoded_rawIn_isSpecial & _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign frfWriteBundle_0_wrdata_unrecoded_rawIn_isInf = _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sign_T = wdata[64]; // @[FPU.scala:344:8] assign frfWriteBundle_0_wrdata_unrecoded_rawIn_sign = _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sExp_T = {1'h0, frfWriteBundle_0_wrdata_unrecoded_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign frfWriteBundle_0_wrdata_unrecoded_rawIn_sExp = _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sig_T = ~frfWriteBundle_0_wrdata_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sig_T_1 = {1'h0, _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [51:0] _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sig_T_2 = wdata[51:0]; // @[FPU.scala:344:8] assign _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sig_T_3 = {_frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sig_T_1, _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign frfWriteBundle_0_wrdata_unrecoded_rawIn_sig = _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire frfWriteBundle_0_wrdata_unrecoded_isSubnormal = $signed(frfWriteBundle_0_wrdata_unrecoded_rawIn_sExp) < 13'sh402; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _frfWriteBundle_0_wrdata_unrecoded_denormShiftDist_T = frfWriteBundle_0_wrdata_unrecoded_rawIn_sExp[5:0]; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] _frfWriteBundle_0_wrdata_unrecoded_denormShiftDist_T_1 = 7'h1 - {1'h0, _frfWriteBundle_0_wrdata_unrecoded_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}] wire [5:0] frfWriteBundle_0_wrdata_unrecoded_denormShiftDist = _frfWriteBundle_0_wrdata_unrecoded_denormShiftDist_T_1[5:0]; // @[fNFromRecFN.scala:52:35] wire [52:0] _frfWriteBundle_0_wrdata_unrecoded_denormFract_T = frfWriteBundle_0_wrdata_unrecoded_rawIn_sig[53:1]; // @[rawFloatFromRecFN.scala:55:23] wire [52:0] _frfWriteBundle_0_wrdata_unrecoded_denormFract_T_1 = _frfWriteBundle_0_wrdata_unrecoded_denormFract_T >> frfWriteBundle_0_wrdata_unrecoded_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [51:0] frfWriteBundle_0_wrdata_unrecoded_denormFract = _frfWriteBundle_0_wrdata_unrecoded_denormFract_T_1[51:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [10:0] _frfWriteBundle_0_wrdata_unrecoded_expOut_T = frfWriteBundle_0_wrdata_unrecoded_rawIn_sExp[10:0]; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] _frfWriteBundle_0_wrdata_unrecoded_expOut_T_1 = {1'h0, _frfWriteBundle_0_wrdata_unrecoded_expOut_T} - 12'h401; // @[fNFromRecFN.scala:58:{27,45}] wire [10:0] _frfWriteBundle_0_wrdata_unrecoded_expOut_T_2 = _frfWriteBundle_0_wrdata_unrecoded_expOut_T_1[10:0]; // @[fNFromRecFN.scala:58:45] wire [10:0] _frfWriteBundle_0_wrdata_unrecoded_expOut_T_3 = frfWriteBundle_0_wrdata_unrecoded_isSubnormal ? 11'h0 : _frfWriteBundle_0_wrdata_unrecoded_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _frfWriteBundle_0_wrdata_unrecoded_expOut_T_4 = frfWriteBundle_0_wrdata_unrecoded_rawIn_isNaN \| frfWriteBundle_0_wrdata_unrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _frfWriteBundle_0_wrdata_unrecoded_expOut_T_5 = {11{_frfWriteBundle_0_wrdata_unrecoded_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}] wire [10:0] frfWriteBundle_0_wrdata_unrecoded_expOut = _frfWriteBundle_0_wrdata_unrecoded_expOut_T_3 \| _frfWriteBundle_0_wrdata_unrecoded_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [51:0] _frfWriteBundle_0_wrdata_unrecoded_fractOut_T = frfWriteBundle_0_wrdata_unrecoded_rawIn_sig[51:0]; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] _frfWriteBundle_0_wrdata_unrecoded_fractOut_T_1 = frfWriteBundle_0_wrdata_unrecoded_rawIn_isInf ? 52'h0 : _frfWriteBundle_0_wrdata_unrecoded_fractOut_T; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] frfWriteBundle_0_wrdata_unrecoded_fractOut = frfWriteBundle_0_wrdata_unrecoded_isSubnormal ? frfWriteBundle_0_wrdata_unrecoded_denormFract : _frfWriteBundle_0_wrdata_unrecoded_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [11:0] frfWriteBundle_0_wrdata_unrecoded_hi = {frfWriteBundle_0_wrdata_unrecoded_rawIn_sign, frfWriteBundle_0_wrdata_unrecoded_expOut}; // @[rawFloatFromRecFN.scala:55:23] wire [63:0] frfWriteBundle_0_wrdata_unrecoded = {frfWriteBundle_0_wrdata_unrecoded_hi, frfWriteBundle_0_wrdata_unrecoded_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12] wire [1:0] frfWriteBundle_0_wrdata_prevRecoded_hi = {_frfWriteBundle_0_wrdata_prevRecoded_T, _frfWriteBundle_0_wrdata_prevRecoded_T_1}; // @[FPU.scala:441:28, :442:10, :443:10] wire [32:0] frfWriteBundle_0_wrdata_prevRecoded = {frfWriteBundle_0_wrdata_prevRecoded_hi, _frfWriteBundle_0_wrdata_prevRecoded_T_2}; // @[FPU.scala:441:28, :444:10] wire [8:0] frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_exp = frfWriteBundle_0_wrdata_prevRecoded[31:23]; // @[FPU.scala:441:28] wire [2:0] _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isZero_T = frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isZero = _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isZero_0 = frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isSpecial_T = frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isSpecial = &_frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_isNaN_T = frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_isInf_T = frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1 = frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isSpecial & _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isNaN = _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_isInf_T_1 = ~_frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2 = frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isSpecial & _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isInf = _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_sign_T = frfWriteBundle_0_wrdata_prevRecoded[32]; // @[FPU.scala:441:28] assign frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_sign = _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_sExp_T = {1'h0, frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_sExp = _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_sig_T = ~frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_sig_T_1 = {1'h0, _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_sig_T_2 = frfWriteBundle_0_wrdata_prevRecoded[22:0]; // @[FPU.scala:441:28] assign _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_sig_T_3 = {_frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_sig_T_1, _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_sig = _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_isSubnormal = $signed(frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_denormShiftDist_T = frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_denormShiftDist_T_1 = 6'h1 - {1'h0, _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_denormShiftDist = _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_denormShiftDist_T_1[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_denormFract_T = frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_denormFract_T_1 = _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_denormFract_T >> frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_denormFract = _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_denormFract_T_1[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_expOut_T = frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_expOut_T_1 = {1'h0, _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_expOut_T} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_expOut_T_2 = _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_expOut_T_1[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_expOut_T_3 = frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_isSubnormal ? 8'h0 : _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_expOut_T_4 = frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isNaN \| frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_expOut_T_5 = {8{_frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_expOut = _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_expOut_T_3 \| _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_fractOut_T = frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_fractOut_T_1 = frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isInf ? 23'h0 : _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_fractOut_T; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_fractOut = frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_isSubnormal ? frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_denormFract : _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_hi = {frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_sign, frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_expOut}; // @[rawFloatFromRecFN.scala:55:23] wire [31:0] frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded = {frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_hi, frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12] wire _frfWriteBundle_0_wrdata_prevUnrecoded_prevRecoded_T = frfWriteBundle_0_wrdata_prevRecoded[15]; // @[FPU.scala:441:28, :442:10] wire _frfWriteBundle_0_wrdata_prevUnrecoded_prevRecoded_T_1 = frfWriteBundle_0_wrdata_prevRecoded[23]; // @[FPU.scala:441:28, :443:10] wire [14:0] _frfWriteBundle_0_wrdata_prevUnrecoded_prevRecoded_T_2 = frfWriteBundle_0_wrdata_prevRecoded[14:0]; // @[FPU.scala:441:28, :444:10] wire [1:0] frfWriteBundle_0_wrdata_prevUnrecoded_prevRecoded_hi = {_frfWriteBundle_0_wrdata_prevUnrecoded_prevRecoded_T, _frfWriteBundle_0_wrdata_prevUnrecoded_prevRecoded_T_1}; // @[FPU.scala:441:28, :442:10, :443:10] wire [16:0] frfWriteBundle_0_wrdata_prevUnrecoded_prevRecoded = {frfWriteBundle_0_wrdata_prevUnrecoded_prevRecoded_hi, _frfWriteBundle_0_wrdata_prevUnrecoded_prevRecoded_T_2}; // @[FPU.scala:441:28, :444:10] wire [5:0] frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_exp = frfWriteBundle_0_wrdata_prevUnrecoded_prevRecoded[15:10]; // @[FPU.scala:441:28] wire [2:0] _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isZero_T = frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_exp[5:3]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isZero = _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isZero_0 = frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T = frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_exp[5:4]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isSpecial = &_frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [6:0] _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [11:0] _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T = frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_exp[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T = frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_exp[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1 = frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isSpecial & _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isNaN = _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_1 = ~_frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2 = frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isSpecial & _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isInf = _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T = frfWriteBundle_0_wrdata_prevUnrecoded_prevRecoded[16]; // @[FPU.scala:441:28] assign frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_sign = _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T = {1'h0, frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_sExp = _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T = ~frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_1 = {1'h0, _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [9:0] _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_2 = frfWriteBundle_0_wrdata_prevUnrecoded_prevRecoded[9:0]; // @[FPU.scala:441:28] assign _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3 = {_frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_1, _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_sig = _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_isSubnormal = $signed(frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_sExp) < 7'sh12; // @[rawFloatFromRecFN.scala:55:23] wire [3:0] _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_denormShiftDist_T = frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_sExp[3:0]; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_denormShiftDist_T_1 = 5'h1 - {1'h0, _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}] wire [3:0] frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_denormShiftDist = _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_denormShiftDist_T_1[3:0]; // @[fNFromRecFN.scala:52:35] wire [10:0] _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_denormFract_T = frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_sig[11:1]; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_denormFract_T_1 = _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_denormFract_T >> frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [9:0] frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_denormFract = _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_denormFract_T_1[9:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [4:0] _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_expOut_T = frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_expOut_T_1 = {1'h0, _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_expOut_T} - 6'h11; // @[fNFromRecFN.scala:58:{27,45}] wire [4:0] _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_expOut_T_2 = _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_expOut_T_1[4:0]; // @[fNFromRecFN.scala:58:45] wire [4:0] _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_expOut_T_3 = frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_isSubnormal ? 5'h0 : _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_expOut_T_4 = frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isNaN \| frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_expOut_T_5 = {5{_frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}] wire [4:0] frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_expOut = _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_expOut_T_3 \| _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [9:0] _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_fractOut_T = frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_sig[9:0]; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_fractOut_T_1 = frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isInf ? 10'h0 : _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_fractOut_T; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_fractOut = frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_isSubnormal ? frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_denormFract : _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [5:0] frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_hi = {frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_sign, frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_expOut}; // @[rawFloatFromRecFN.scala:55:23] wire [15:0] frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded = {frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_hi, frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12] wire [15:0] _frfWriteBundle_0_wrdata_prevUnrecoded_T = frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded[31:16]; // @[FPU.scala:446:21] wire [2:0] _frfWriteBundle_0_wrdata_prevUnrecoded_T_1 = frfWriteBundle_0_wrdata_prevRecoded[31:29]; // @[FPU.scala:249:25, :441:28] wire _frfWriteBundle_0_wrdata_prevUnrecoded_T_2 = &_frfWriteBundle_0_wrdata_prevUnrecoded_T_1; // @[FPU.scala:249:{25,56}] wire [15:0] _frfWriteBundle_0_wrdata_prevUnrecoded_T_3 = frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded[15:0]; // @[FPU.scala:446:81] wire [15:0] _frfWriteBundle_0_wrdata_prevUnrecoded_T_4 = _frfWriteBundle_0_wrdata_prevUnrecoded_T_2 ? frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded : _frfWriteBundle_0_wrdata_prevUnrecoded_T_3; // @[FPU.scala:249:56, :446:{44,81}] wire [31:0] frfWriteBundle_0_wrdata_prevUnrecoded = {_frfWriteBundle_0_wrdata_prevUnrecoded_T, _frfWriteBundle_0_wrdata_prevUnrecoded_T_4}; // @[FPU.scala:446:{10,21,44}] wire [31:0] _frfWriteBundle_0_wrdata_T = frfWriteBundle_0_wrdata_unrecoded[63:32]; // @[FPU.scala:446:21] wire _frfWriteBundle_0_wrdata_T_2 = &_frfWriteBundle_0_wrdata_T_1; // @[FPU.scala:249:{25,56}] wire [31:0] _frfWriteBundle_0_wrdata_T_3 = frfWriteBundle_0_wrdata_unrecoded[31:0]; // @[FPU.scala:446:81] wire [31:0] _frfWriteBundle_0_wrdata_T_4 = _frfWriteBundle_0_wrdata_T_2 ? frfWriteBundle_0_wrdata_prevUnrecoded : _frfWriteBundle_0_wrdata_T_3; // @[FPU.scala:249:56, :446:{10,44,81}] assign _frfWriteBundle_0_wrdata_T_5 = {_frfWriteBundle_0_wrdata_T, _frfWriteBundle_0_wrdata_T_4}; // @[FPU.scala:446:{10,21,44}] assign frfWriteBundle_0_wrdata = _frfWriteBundle_0_wrdata_T_5; // @[FPU.scala:446:10, :805:44] wire [4:0] _ex_rs_T_1 = _ex_rs_T; // @[FPU.scala:832:37] wire [4:0] _ex_rs_T_3 = _ex_rs_T_2; // @[FPU.scala:832:37] wire [4:0] _ex_rs_T_5 = _ex_rs_T_4; // @[FPU.scala:832:37] wire [4:0] _ex_ra_0_T = io_inst_0[19:15]; // @[FPU.scala:735:7, :835:51] wire [4:0] _ex_ra_1_T = io_inst_0[19:15]; // @[FPU.scala:735:7, :835:51, :836:50] wire [4:0] _ex_ra_0_T_1 = io_inst_0[24:20]; // @[FPU.scala:735:7, :839:50] wire [4:0] _ex_ra_2_T = io_inst_0[24:20]; // @[FPU.scala:735:7, :839:50, :840:50] wire [4:0] _ex_ra_1_T_1 = io_inst_0[24:20]; // @[FPU.scala:735:7, :839:50, :841:70] wire [4:0] _ex_ra_2_T_1 = io_inst_0[31:27]; // @[FPU.scala:735:7, :843:46] wire [2:0] _ex_rm_T = ex_reg_inst[14:12]; // @[FPU.scala:768:30, :845:30] wire [2:0] _ex_rm_T_2 = ex_reg_inst[14:12]; // @[FPU.scala:768:30, :845:{30,70}] wire _ex_rm_T_1 = &_ex_rm_T; // @[FPU.scala:845:{30,38}] wire [2:0] ex_rm = _ex_rm_T_1 ? io_fcsr_rm_0 : _ex_rm_T_2; // @[FPU.scala:735:7, :845:{18,38,70}] wire [2:0] sfma_io_in_bits_req_rm = ex_rm; // @[FPU.scala:845:18, :848:19] wire [2:0] fpiu_io_in_bits_req_rm = ex_rm; // @[FPU.scala:845:18, :848:19] wire [2:0] dfma_io_in_bits_req_rm = ex_rm; // @[FPU.scala:845:18, :848:19] wire [2:0] hfma_io_in_bits_req_rm = ex_rm; // @[FPU.scala:845:18, :848:19] wire _GEN_0 = req_valid & ex_ctrl_fma; // @[FPU.scala:780:32, :800:20, :873:33] wire _sfma_io_in_valid_T; // @[FPU.scala:873:33] assign _sfma_io_in_valid_T = _GEN_0; // @[FPU.scala:873:33] wire _dfma_io_in_valid_T; // @[FPU.scala:914:41] assign _dfma_io_in_valid_T = _GEN_0; // @[FPU.scala:873:33, :914:41] wire _hfma_io_in_valid_T; // @[FPU.scala:920:41] assign _hfma_io_in_valid_T = _GEN_0; // @[FPU.scala:873:33, :920:41] wire _GEN_1 = ex_ctrl_typeTagOut == 2'h1; // @[FPU.scala:800:20, :873:70] wire _sfma_io_in_valid_T_1; // @[FPU.scala:873:70] assign _sfma_io_in_valid_T_1 = _GEN_1; // @[FPU.scala:873:70] wire _write_port_busy_T_2; // @[FPU.scala:911:72] assign _write_port_busy_T_2 = _GEN_1; // @[FPU.scala:873:70, :911:72] wire _write_port_busy_T_20; // @[FPU.scala:911:72] assign _write_port_busy_T_20 = _GEN_1; // @[FPU.scala:873:70, :911:72] wire _sfma_io_in_valid_T_2 = _sfma_io_in_valid_T & _sfma_io_in_valid_T_1; // @[FPU.scala:873:{33,48,70}] wire [1:0] _sfma_io_in_bits_req_fmaCmd_T_4; // @[FPU.scala:857:36] wire [1:0] _sfma_io_in_bits_req_typ_T; // @[FPU.scala:855:27] wire [1:0] _sfma_io_in_bits_req_fmt_T; // @[FPU.scala:856:27] wire [1:0] sfma_io_in_bits_req_fmaCmd; // @[FPU.scala:848:19] wire [1:0] sfma_io_in_bits_req_typ; // @[FPU.scala:848:19] wire [1:0] sfma_io_in_bits_req_fmt; // @[FPU.scala:848:19] wire [64:0] sfma_io_in_bits_req_in1; // @[FPU.scala:848:19] wire [64:0] sfma_io_in_bits_req_in2; // @[FPU.scala:848:19] wire [64:0] sfma_io_in_bits_req_in3; // @[FPU.scala:848:19] wire _sfma_io_in_bits_req_in1_prev_unswizzled_T = _regfile_ext_R2_data[31]; // @[FPU.scala:357:14, :818:20] wire _fpiu_io_in_bits_req_in1_prev_unswizzled_T = _regfile_ext_R2_data[31]; // @[FPU.scala:357:14, :818:20] wire _dfma_io_in_bits_req_in1_prev_unswizzled_T = _regfile_ext_R2_data[31]; // @[FPU.scala:357:14, :818:20] wire _hfma_io_in_bits_req_in1_prev_unswizzled_T = _regfile_ext_R2_data[31]; // @[FPU.scala:357:14, :818:20] wire _sfma_io_in_bits_req_in1_prev_unswizzled_T_1 = _regfile_ext_R2_data[52]; // @[FPU.scala:358:14, :818:20] wire _fpiu_io_in_bits_req_in1_prev_unswizzled_T_1 = _regfile_ext_R2_data[52]; // @[FPU.scala:358:14, :818:20] wire _dfma_io_in_bits_req_in1_prev_unswizzled_T_1 = _regfile_ext_R2_data[52]; // @[FPU.scala:358:14, :818:20] wire _hfma_io_in_bits_req_in1_prev_unswizzled_T_1 = _regfile_ext_R2_data[52]; // @[FPU.scala:358:14, :818:20] wire [30:0] _sfma_io_in_bits_req_in1_prev_unswizzled_T_2 = _regfile_ext_R2_data[30:0]; // @[FPU.scala:359:14, :818:20] wire [30:0] _fpiu_io_in_bits_req_in1_prev_unswizzled_T_2 = _regfile_ext_R2_data[30:0]; // @[FPU.scala:359:14, :818:20] wire [30:0] _dfma_io_in_bits_req_in1_prev_unswizzled_T_2 = _regfile_ext_R2_data[30:0]; // @[FPU.scala:359:14, :818:20] wire [30:0] _hfma_io_in_bits_req_in1_prev_unswizzled_T_2 = _regfile_ext_R2_data[30:0]; // @[FPU.scala:359:14, :818:20] wire [1:0] sfma_io_in_bits_req_in1_prev_unswizzled_hi = {_sfma_io_in_bits_req_in1_prev_unswizzled_T, _sfma_io_in_bits_req_in1_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [32:0] sfma_io_in_bits_req_in1_floats_1 = {sfma_io_in_bits_req_in1_prev_unswizzled_hi, _sfma_io_in_bits_req_in1_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire _sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T = sfma_io_in_bits_req_in1_floats_1[15]; // @[FPU.scala:356:31, :357:14] wire _sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_1 = sfma_io_in_bits_req_in1_floats_1[23]; // @[FPU.scala:356:31, :358:14] wire [14:0] _sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_2 = sfma_io_in_bits_req_in1_floats_1[14:0]; // @[FPU.scala:356:31, :359:14] wire [1:0] sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_hi = {_sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T, _sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [16:0] sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled = {sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_hi, _sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire sfma_io_in_bits_req_in1_prev_prev_prev_prev_sign = sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled[16]; // @[FPU.scala:274:17, :356:31] wire [9:0] sfma_io_in_bits_req_in1_prev_prev_prev_prev_fractIn = sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled[9:0]; // @[FPU.scala:275:20, :356:31] wire [5:0] sfma_io_in_bits_req_in1_prev_prev_prev_prev_expIn = sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled[15:10]; // @[FPU.scala:276:18, :356:31] wire [33:0] _sfma_io_in_bits_req_in1_prev_prev_prev_prev_fractOut_T = {sfma_io_in_bits_req_in1_prev_prev_prev_prev_fractIn, 24'h0}; // @[FPU.scala:275:20, :277:28] wire [22:0] sfma_io_in_bits_req_in1_prev_prev_prev_prev_fractOut = _sfma_io_in_bits_req_in1_prev_prev_prev_prev_fractOut_T[33:11]; // @[FPU.scala:277:{28,38}] wire [2:0] sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode = sfma_io_in_bits_req_in1_prev_prev_prev_prev_expIn[5:3]; // @[FPU.scala:276:18, :279:26] wire [9:0] _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T = {4'h0, sfma_io_in_bits_req_in1_prev_prev_prev_prev_expIn} + 10'h100; // @[FPU.scala:276:18, :280:31] wire [8:0] _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_1 = _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T[8:0]; // @[FPU.scala:280:31] wire [9:0] _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_2 = {1'h0, _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_1} - 10'h20; // @[FPU.scala:280:{31,50}] wire [8:0] sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase = _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_2[8:0]; // @[FPU.scala:280:50] wire [8:0] _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_5 = sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T = sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_1 = sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_2 = _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T \| _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [5:0] _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_3 = sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:69] wire [8:0] _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_4 = {sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode, _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [8:0] sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut = _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_2 ? _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_4 : _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [9:0] sfma_io_in_bits_req_in1_prev_prev_prev_prev_hi = {sfma_io_in_bits_req_in1_prev_prev_prev_prev_sign, sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [32:0] sfma_io_in_bits_req_in1_floats_0 = {sfma_io_in_bits_req_in1_prev_prev_prev_prev_hi, sfma_io_in_bits_req_in1_prev_prev_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire [4:0] _sfma_io_in_bits_req_in1_prev_prev_prev_isbox_T = sfma_io_in_bits_req_in1_floats_1[32:28]; // @[FPU.scala:332:49, :356:31] wire sfma_io_in_bits_req_in1_prev_prev_prev_isbox = &_sfma_io_in_bits_req_in1_prev_prev_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire sfma_io_in_bits_req_in1_prev_prev_0_1 = sfma_io_in_bits_req_in1_prev_prev_prev_isbox; // @[FPU.scala:332:84, :362:32] wire [4:0] _sfma_io_in_bits_req_in1_prev_isbox_T = _regfile_ext_R2_data[64:60]; // @[FPU.scala:332:49, :818:20] wire [4:0] _fpiu_io_in_bits_req_in1_prev_isbox_T = _regfile_ext_R2_data[64:60]; // @[FPU.scala:332:49, :818:20] wire [4:0] _dfma_io_in_bits_req_in1_prev_isbox_T = _regfile_ext_R2_data[64:60]; // @[FPU.scala:332:49, :818:20] wire [4:0] _hfma_io_in_bits_req_in1_prev_isbox_T = _regfile_ext_R2_data[64:60]; // @[FPU.scala:332:49, :818:20] wire sfma_io_in_bits_req_in1_prev_isbox = &_sfma_io_in_bits_req_in1_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire sfma_io_in_bits_req_in1_oks_1 = sfma_io_in_bits_req_in1_prev_isbox; // @[FPU.scala:332:84, :362:32] wire sfma_io_in_bits_req_in1_oks_0 = sfma_io_in_bits_req_in1_prev_isbox & sfma_io_in_bits_req_in1_prev_prev_0_1; // @[FPU.scala:332:84, :362:32] wire sfma_io_in_bits_req_in1_sign = _regfile_ext_R2_data[64]; // @[FPU.scala:274:17, :818:20] wire hfma_io_in_bits_req_in1_sign = _regfile_ext_R2_data[64]; // @[FPU.scala:274:17, :818:20] wire [51:0] sfma_io_in_bits_req_in1_fractIn = _regfile_ext_R2_data[51:0]; // @[FPU.scala:275:20, :818:20] wire [51:0] hfma_io_in_bits_req_in1_fractIn = _regfile_ext_R2_data[51:0]; // @[FPU.scala:275:20, :818:20] wire [11:0] sfma_io_in_bits_req_in1_expIn = _regfile_ext_R2_data[63:52]; // @[FPU.scala:276:18, :818:20] wire [11:0] hfma_io_in_bits_req_in1_expIn = _regfile_ext_R2_data[63:52]; // @[FPU.scala:276:18, :818:20] wire [75:0] _sfma_io_in_bits_req_in1_fractOut_T = {sfma_io_in_bits_req_in1_fractIn, 24'h0}; // @[FPU.scala:275:20, :277:28] wire [22:0] sfma_io_in_bits_req_in1_fractOut = _sfma_io_in_bits_req_in1_fractOut_T[75:53]; // @[FPU.scala:277:{28,38}] wire [2:0] sfma_io_in_bits_req_in1_expOut_expCode = sfma_io_in_bits_req_in1_expIn[11:9]; // @[FPU.scala:276:18, :279:26] wire [12:0] _sfma_io_in_bits_req_in1_expOut_commonCase_T = {1'h0, sfma_io_in_bits_req_in1_expIn} + 13'h100; // @[FPU.scala:276:18, :280:31] wire [11:0] _sfma_io_in_bits_req_in1_expOut_commonCase_T_1 = _sfma_io_in_bits_req_in1_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _sfma_io_in_bits_req_in1_expOut_commonCase_T_2 = {1'h0, _sfma_io_in_bits_req_in1_expOut_commonCase_T_1} - 13'h800; // @[FPU.scala:280:{31,50}] wire [11:0] sfma_io_in_bits_req_in1_expOut_commonCase = _sfma_io_in_bits_req_in1_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire _sfma_io_in_bits_req_in1_expOut_T = sfma_io_in_bits_req_in1_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _sfma_io_in_bits_req_in1_expOut_T_1 = sfma_io_in_bits_req_in1_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _sfma_io_in_bits_req_in1_expOut_T_2 = _sfma_io_in_bits_req_in1_expOut_T \| _sfma_io_in_bits_req_in1_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [5:0] _sfma_io_in_bits_req_in1_expOut_T_3 = sfma_io_in_bits_req_in1_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:69] wire [8:0] _sfma_io_in_bits_req_in1_expOut_T_4 = {sfma_io_in_bits_req_in1_expOut_expCode, _sfma_io_in_bits_req_in1_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [8:0] _sfma_io_in_bits_req_in1_expOut_T_5 = sfma_io_in_bits_req_in1_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:97] wire [8:0] sfma_io_in_bits_req_in1_expOut = _sfma_io_in_bits_req_in1_expOut_T_2 ? _sfma_io_in_bits_req_in1_expOut_T_4 : _sfma_io_in_bits_req_in1_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [9:0] sfma_io_in_bits_req_in1_hi = {sfma_io_in_bits_req_in1_sign, sfma_io_in_bits_req_in1_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [32:0] sfma_io_in_bits_req_in1_floats_2 = {sfma_io_in_bits_req_in1_hi, sfma_io_in_bits_req_in1_fractOut}; // @[FPU.scala:277:38, :283:8] wire [32:0] _sfma_io_in_bits_req_in1_T = sfma_io_in_bits_req_in1_oks_1 ? 33'h0 : 33'hE0400000; // @[FPU.scala:362:32, :372:31] wire [32:0] _sfma_io_in_bits_req_in1_T_1 = sfma_io_in_bits_req_in1_floats_1 \| _sfma_io_in_bits_req_in1_T; // @[FPU.scala:356:31, :372:{26,31}] assign sfma_io_in_bits_req_in1 = {32'h0, _sfma_io_in_bits_req_in1_T_1}; // @[FPU.scala:372:26, :848:19, :852:13] wire _sfma_io_in_bits_req_in2_prev_unswizzled_T = _regfile_ext_R1_data[31]; // @[FPU.scala:357:14, :818:20] wire _fpiu_io_in_bits_req_in2_prev_unswizzled_T = _regfile_ext_R1_data[31]; // @[FPU.scala:357:14, :818:20] wire _dfma_io_in_bits_req_in2_prev_unswizzled_T = _regfile_ext_R1_data[31]; // @[FPU.scala:357:14, :818:20] wire _hfma_io_in_bits_req_in2_prev_unswizzled_T = _regfile_ext_R1_data[31]; // @[FPU.scala:357:14, :818:20] wire _sfma_io_in_bits_req_in2_prev_unswizzled_T_1 = _regfile_ext_R1_data[52]; // @[FPU.scala:358:14, :818:20] wire _fpiu_io_in_bits_req_in2_prev_unswizzled_T_1 = _regfile_ext_R1_data[52]; // @[FPU.scala:358:14, :818:20] wire _dfma_io_in_bits_req_in2_prev_unswizzled_T_1 = _regfile_ext_R1_data[52]; // @[FPU.scala:358:14, :818:20] wire _hfma_io_in_bits_req_in2_prev_unswizzled_T_1 = _regfile_ext_R1_data[52]; // @[FPU.scala:358:14, :818:20] wire [30:0] _sfma_io_in_bits_req_in2_prev_unswizzled_T_2 = _regfile_ext_R1_data[30:0]; // @[FPU.scala:359:14, :818:20] wire [30:0] _fpiu_io_in_bits_req_in2_prev_unswizzled_T_2 = _regfile_ext_R1_data[30:0]; // @[FPU.scala:359:14, :818:20] wire [30:0] _dfma_io_in_bits_req_in2_prev_unswizzled_T_2 = _regfile_ext_R1_data[30:0]; // @[FPU.scala:359:14, :818:20] wire [30:0] _hfma_io_in_bits_req_in2_prev_unswizzled_T_2 = _regfile_ext_R1_data[30:0]; // @[FPU.scala:359:14, :818:20] wire [1:0] sfma_io_in_bits_req_in2_prev_unswizzled_hi = {_sfma_io_in_bits_req_in2_prev_unswizzled_T, _sfma_io_in_bits_req_in2_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [32:0] sfma_io_in_bits_req_in2_floats_1 = {sfma_io_in_bits_req_in2_prev_unswizzled_hi, _sfma_io_in_bits_req_in2_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire _sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T = sfma_io_in_bits_req_in2_floats_1[15]; // @[FPU.scala:356:31, :357:14] wire _sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_1 = sfma_io_in_bits_req_in2_floats_1[23]; // @[FPU.scala:356:31, :358:14] wire [14:0] _sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_2 = sfma_io_in_bits_req_in2_floats_1[14:0]; // @[FPU.scala:356:31, :359:14] wire [1:0] sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_hi = {_sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T, _sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [16:0] sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled = {sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_hi, _sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire sfma_io_in_bits_req_in2_prev_prev_prev_prev_sign = sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled[16]; // @[FPU.scala:274:17, :356:31] wire [9:0] sfma_io_in_bits_req_in2_prev_prev_prev_prev_fractIn = sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled[9:0]; // @[FPU.scala:275:20, :356:31] wire [5:0] sfma_io_in_bits_req_in2_prev_prev_prev_prev_expIn = sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled[15:10]; // @[FPU.scala:276:18, :356:31] wire [33:0] _sfma_io_in_bits_req_in2_prev_prev_prev_prev_fractOut_T = {sfma_io_in_bits_req_in2_prev_prev_prev_prev_fractIn, 24'h0}; // @[FPU.scala:275:20, :277:28] wire [22:0] sfma_io_in_bits_req_in2_prev_prev_prev_prev_fractOut = _sfma_io_in_bits_req_in2_prev_prev_prev_prev_fractOut_T[33:11]; // @[FPU.scala:277:{28,38}] wire [2:0] sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode = sfma_io_in_bits_req_in2_prev_prev_prev_prev_expIn[5:3]; // @[FPU.scala:276:18, :279:26] wire [9:0] _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T = {4'h0, sfma_io_in_bits_req_in2_prev_prev_prev_prev_expIn} + 10'h100; // @[FPU.scala:276:18, :280:31] wire [8:0] _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_1 = _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T[8:0]; // @[FPU.scala:280:31] wire [9:0] _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_2 = {1'h0, _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_1} - 10'h20; // @[FPU.scala:280:{31,50}] wire [8:0] sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase = _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_2[8:0]; // @[FPU.scala:280:50] wire [8:0] _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_5 = sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T = sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_1 = sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_2 = _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T \| _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [5:0] _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_3 = sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:69] wire [8:0] _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_4 = {sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode, _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [8:0] sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut = _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_2 ? _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_4 : _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [9:0] sfma_io_in_bits_req_in2_prev_prev_prev_prev_hi = {sfma_io_in_bits_req_in2_prev_prev_prev_prev_sign, sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [32:0] sfma_io_in_bits_req_in2_floats_0 = {sfma_io_in_bits_req_in2_prev_prev_prev_prev_hi, sfma_io_in_bits_req_in2_prev_prev_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire [4:0] _sfma_io_in_bits_req_in2_prev_prev_prev_isbox_T = sfma_io_in_bits_req_in2_floats_1[32:28]; // @[FPU.scala:332:49, :356:31] wire sfma_io_in_bits_req_in2_prev_prev_prev_isbox = &_sfma_io_in_bits_req_in2_prev_prev_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire sfma_io_in_bits_req_in2_prev_prev_0_1 = sfma_io_in_bits_req_in2_prev_prev_prev_isbox; // @[FPU.scala:332:84, :362:32] wire [4:0] _sfma_io_in_bits_req_in2_prev_isbox_T = _regfile_ext_R1_data[64:60]; // @[FPU.scala:332:49, :818:20] wire [4:0] _fpiu_io_in_bits_req_in2_prev_isbox_T = _regfile_ext_R1_data[64:60]; // @[FPU.scala:332:49, :818:20] wire [4:0] _dfma_io_in_bits_req_in2_prev_isbox_T = _regfile_ext_R1_data[64:60]; // @[FPU.scala:332:49, :818:20] wire [4:0] _hfma_io_in_bits_req_in2_prev_isbox_T = _regfile_ext_R1_data[64:60]; // @[FPU.scala:332:49, :818:20] wire sfma_io_in_bits_req_in2_prev_isbox = &_sfma_io_in_bits_req_in2_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire sfma_io_in_bits_req_in2_oks_1 = sfma_io_in_bits_req_in2_prev_isbox; // @[FPU.scala:332:84, :362:32] wire sfma_io_in_bits_req_in2_oks_0 = sfma_io_in_bits_req_in2_prev_isbox & sfma_io_in_bits_req_in2_prev_prev_0_1; // @[FPU.scala:332:84, :362:32] wire sfma_io_in_bits_req_in2_sign = _regfile_ext_R1_data[64]; // @[FPU.scala:274:17, :818:20] wire hfma_io_in_bits_req_in2_sign = _regfile_ext_R1_data[64]; // @[FPU.scala:274:17, :818:20] wire [51:0] sfma_io_in_bits_req_in2_fractIn = _regfile_ext_R1_data[51:0]; // @[FPU.scala:275:20, :818:20] wire [51:0] hfma_io_in_bits_req_in2_fractIn = _regfile_ext_R1_data[51:0]; // @[FPU.scala:275:20, :818:20] wire [11:0] sfma_io_in_bits_req_in2_expIn = _regfile_ext_R1_data[63:52]; // @[FPU.scala:276:18, :818:20] wire [11:0] hfma_io_in_bits_req_in2_expIn = _regfile_ext_R1_data[63:52]; // @[FPU.scala:276:18, :818:20] wire [75:0] _sfma_io_in_bits_req_in2_fractOut_T = {sfma_io_in_bits_req_in2_fractIn, 24'h0}; // @[FPU.scala:275:20, :277:28] wire [22:0] sfma_io_in_bits_req_in2_fractOut = _sfma_io_in_bits_req_in2_fractOut_T[75:53]; // @[FPU.scala:277:{28,38}] wire [2:0] sfma_io_in_bits_req_in2_expOut_expCode = sfma_io_in_bits_req_in2_expIn[11:9]; // @[FPU.scala:276:18, :279:26] wire [12:0] _sfma_io_in_bits_req_in2_expOut_commonCase_T = {1'h0, sfma_io_in_bits_req_in2_expIn} + 13'h100; // @[FPU.scala:276:18, :280:31] wire [11:0] _sfma_io_in_bits_req_in2_expOut_commonCase_T_1 = _sfma_io_in_bits_req_in2_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _sfma_io_in_bits_req_in2_expOut_commonCase_T_2 = {1'h0, _sfma_io_in_bits_req_in2_expOut_commonCase_T_1} - 13'h800; // @[FPU.scala:280:{31,50}] wire [11:0] sfma_io_in_bits_req_in2_expOut_commonCase = _sfma_io_in_bits_req_in2_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire _sfma_io_in_bits_req_in2_expOut_T = sfma_io_in_bits_req_in2_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _sfma_io_in_bits_req_in2_expOut_T_1 = sfma_io_in_bits_req_in2_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _sfma_io_in_bits_req_in2_expOut_T_2 = _sfma_io_in_bits_req_in2_expOut_T \| _sfma_io_in_bits_req_in2_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [5:0] _sfma_io_in_bits_req_in2_expOut_T_3 = sfma_io_in_bits_req_in2_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:69] wire [8:0] _sfma_io_in_bits_req_in2_expOut_T_4 = {sfma_io_in_bits_req_in2_expOut_expCode, _sfma_io_in_bits_req_in2_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [8:0] _sfma_io_in_bits_req_in2_expOut_T_5 = sfma_io_in_bits_req_in2_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:97] wire [8:0] sfma_io_in_bits_req_in2_expOut = _sfma_io_in_bits_req_in2_expOut_T_2 ? _sfma_io_in_bits_req_in2_expOut_T_4 : _sfma_io_in_bits_req_in2_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [9:0] sfma_io_in_bits_req_in2_hi = {sfma_io_in_bits_req_in2_sign, sfma_io_in_bits_req_in2_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [32:0] sfma_io_in_bits_req_in2_floats_2 = {sfma_io_in_bits_req_in2_hi, sfma_io_in_bits_req_in2_fractOut}; // @[FPU.scala:277:38, :283:8] wire [32:0] _sfma_io_in_bits_req_in2_T = sfma_io_in_bits_req_in2_oks_1 ? 33'h0 : 33'hE0400000; // @[FPU.scala:362:32, :372:31] wire [32:0] _sfma_io_in_bits_req_in2_T_1 = sfma_io_in_bits_req_in2_floats_1 \| _sfma_io_in_bits_req_in2_T; // @[FPU.scala:356:31, :372:{26,31}] assign sfma_io_in_bits_req_in2 = {32'h0, _sfma_io_in_bits_req_in2_T_1}; // @[FPU.scala:372:26, :848:19, :853:13] wire _sfma_io_in_bits_req_in3_prev_unswizzled_T = _regfile_ext_R0_data[31]; // @[FPU.scala:357:14, :818:20] wire _fpiu_io_in_bits_req_in3_prev_unswizzled_T = _regfile_ext_R0_data[31]; // @[FPU.scala:357:14, :818:20] wire _dfma_io_in_bits_req_in3_prev_unswizzled_T = _regfile_ext_R0_data[31]; // @[FPU.scala:357:14, :818:20] wire _hfma_io_in_bits_req_in3_prev_unswizzled_T = _regfile_ext_R0_data[31]; // @[FPU.scala:357:14, :818:20] wire _sfma_io_in_bits_req_in3_prev_unswizzled_T_1 = _regfile_ext_R0_data[52]; // @[FPU.scala:358:14, :818:20] wire _fpiu_io_in_bits_req_in3_prev_unswizzled_T_1 = _regfile_ext_R0_data[52]; // @[FPU.scala:358:14, :818:20] wire _dfma_io_in_bits_req_in3_prev_unswizzled_T_1 = _regfile_ext_R0_data[52]; // @[FPU.scala:358:14, :818:20] wire _hfma_io_in_bits_req_in3_prev_unswizzled_T_1 = _regfile_ext_R0_data[52]; // @[FPU.scala:358:14, :818:20] wire [30:0] _sfma_io_in_bits_req_in3_prev_unswizzled_T_2 = _regfile_ext_R0_data[30:0]; // @[FPU.scala:359:14, :818:20] wire [30:0] _fpiu_io_in_bits_req_in3_prev_unswizzled_T_2 = _regfile_ext_R0_data[30:0]; // @[FPU.scala:359:14, :818:20] wire [30:0] _dfma_io_in_bits_req_in3_prev_unswizzled_T_2 = _regfile_ext_R0_data[30:0]; // @[FPU.scala:359:14, :818:20] wire [30:0] _hfma_io_in_bits_req_in3_prev_unswizzled_T_2 = _regfile_ext_R0_data[30:0]; // @[FPU.scala:359:14, :818:20] wire [1:0] sfma_io_in_bits_req_in3_prev_unswizzled_hi = {_sfma_io_in_bits_req_in3_prev_unswizzled_T, _sfma_io_in_bits_req_in3_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [32:0] sfma_io_in_bits_req_in3_floats_1 = {sfma_io_in_bits_req_in3_prev_unswizzled_hi, _sfma_io_in_bits_req_in3_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire _sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T = sfma_io_in_bits_req_in3_floats_1[15]; // @[FPU.scala:356:31, :357:14] wire _sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_1 = sfma_io_in_bits_req_in3_floats_1[23]; // @[FPU.scala:356:31, :358:14] wire [14:0] _sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_2 = sfma_io_in_bits_req_in3_floats_1[14:0]; // @[FPU.scala:356:31, :359:14] wire [1:0] sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_hi = {_sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T, _sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [16:0] sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled = {sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_hi, _sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire sfma_io_in_bits_req_in3_prev_prev_prev_prev_sign = sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled[16]; // @[FPU.scala:274:17, :356:31] wire [9:0] sfma_io_in_bits_req_in3_prev_prev_prev_prev_fractIn = sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled[9:0]; // @[FPU.scala:275:20, :356:31] wire [5:0] sfma_io_in_bits_req_in3_prev_prev_prev_prev_expIn = sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled[15:10]; // @[FPU.scala:276:18, :356:31] wire [33:0] _sfma_io_in_bits_req_in3_prev_prev_prev_prev_fractOut_T = {sfma_io_in_bits_req_in3_prev_prev_prev_prev_fractIn, 24'h0}; // @[FPU.scala:275:20, :277:28] wire [22:0] sfma_io_in_bits_req_in3_prev_prev_prev_prev_fractOut = _sfma_io_in_bits_req_in3_prev_prev_prev_prev_fractOut_T[33:11]; // @[FPU.scala:277:{28,38}] wire [2:0] sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode = sfma_io_in_bits_req_in3_prev_prev_prev_prev_expIn[5:3]; // @[FPU.scala:276:18, :279:26] wire [9:0] _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T = {4'h0, sfma_io_in_bits_req_in3_prev_prev_prev_prev_expIn} + 10'h100; // @[FPU.scala:276:18, :280:31] wire [8:0] _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_1 = _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T[8:0]; // @[FPU.scala:280:31] wire [9:0] _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_2 = {1'h0, _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_1} - 10'h20; // @[FPU.scala:280:{31,50}] wire [8:0] sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase = _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_2[8:0]; // @[FPU.scala:280:50] wire [8:0] _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_5 = sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T = sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_1 = sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_2 = _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T \| _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [5:0] _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_3 = sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:69] wire [8:0] _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_4 = {sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode, _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [8:0] sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut = _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_2 ? _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_4 : _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [9:0] sfma_io_in_bits_req_in3_prev_prev_prev_prev_hi = {sfma_io_in_bits_req_in3_prev_prev_prev_prev_sign, sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [32:0] sfma_io_in_bits_req_in3_floats_0 = {sfma_io_in_bits_req_in3_prev_prev_prev_prev_hi, sfma_io_in_bits_req_in3_prev_prev_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire [4:0] _sfma_io_in_bits_req_in3_prev_prev_prev_isbox_T = sfma_io_in_bits_req_in3_floats_1[32:28]; // @[FPU.scala:332:49, :356:31] wire sfma_io_in_bits_req_in3_prev_prev_prev_isbox = &_sfma_io_in_bits_req_in3_prev_prev_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire sfma_io_in_bits_req_in3_prev_prev_0_1 = sfma_io_in_bits_req_in3_prev_prev_prev_isbox; // @[FPU.scala:332:84, :362:32] wire [4:0] _sfma_io_in_bits_req_in3_prev_isbox_T = _regfile_ext_R0_data[64:60]; // @[FPU.scala:332:49, :818:20] wire [4:0] _fpiu_io_in_bits_req_in3_prev_isbox_T = _regfile_ext_R0_data[64:60]; // @[FPU.scala:332:49, :818:20] wire [4:0] _dfma_io_in_bits_req_in3_prev_isbox_T = _regfile_ext_R0_data[64:60]; // @[FPU.scala:332:49, :818:20] wire [4:0] _hfma_io_in_bits_req_in3_prev_isbox_T = _regfile_ext_R0_data[64:60]; // @[FPU.scala:332:49, :818:20] wire sfma_io_in_bits_req_in3_prev_isbox = &_sfma_io_in_bits_req_in3_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire sfma_io_in_bits_req_in3_oks_1 = sfma_io_in_bits_req_in3_prev_isbox; // @[FPU.scala:332:84, :362:32] wire sfma_io_in_bits_req_in3_oks_0 = sfma_io_in_bits_req_in3_prev_isbox & sfma_io_in_bits_req_in3_prev_prev_0_1; // @[FPU.scala:332:84, :362:32] wire sfma_io_in_bits_req_in3_sign = _regfile_ext_R0_data[64]; // @[FPU.scala:274:17, :818:20] wire hfma_io_in_bits_req_in3_sign = _regfile_ext_R0_data[64]; // @[FPU.scala:274:17, :818:20] wire [51:0] sfma_io_in_bits_req_in3_fractIn = _regfile_ext_R0_data[51:0]; // @[FPU.scala:275:20, :818:20] wire [51:0] hfma_io_in_bits_req_in3_fractIn = _regfile_ext_R0_data[51:0]; // @[FPU.scala:275:20, :818:20] wire [11:0] sfma_io_in_bits_req_in3_expIn = _regfile_ext_R0_data[63:52]; // @[FPU.scala:276:18, :818:20] wire [11:0] hfma_io_in_bits_req_in3_expIn = _regfile_ext_R0_data[63:52]; // @[FPU.scala:276:18, :818:20] wire [75:0] _sfma_io_in_bits_req_in3_fractOut_T = {sfma_io_in_bits_req_in3_fractIn, 24'h0}; // @[FPU.scala:275:20, :277:28] wire [22:0] sfma_io_in_bits_req_in3_fractOut = _sfma_io_in_bits_req_in3_fractOut_T[75:53]; // @[FPU.scala:277:{28,38}] wire [2:0] sfma_io_in_bits_req_in3_expOut_expCode = sfma_io_in_bits_req_in3_expIn[11:9]; // @[FPU.scala:276:18, :279:26] wire [12:0] _sfma_io_in_bits_req_in3_expOut_commonCase_T = {1'h0, sfma_io_in_bits_req_in3_expIn} + 13'h100; // @[FPU.scala:276:18, :280:31] wire [11:0] _sfma_io_in_bits_req_in3_expOut_commonCase_T_1 = _sfma_io_in_bits_req_in3_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _sfma_io_in_bits_req_in3_expOut_commonCase_T_2 = {1'h0, _sfma_io_in_bits_req_in3_expOut_commonCase_T_1} - 13'h800; // @[FPU.scala:280:{31,50}] wire [11:0] sfma_io_in_bits_req_in3_expOut_commonCase = _sfma_io_in_bits_req_in3_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire _sfma_io_in_bits_req_in3_expOut_T = sfma_io_in_bits_req_in3_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _sfma_io_in_bits_req_in3_expOut_T_1 = sfma_io_in_bits_req_in3_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _sfma_io_in_bits_req_in3_expOut_T_2 = _sfma_io_in_bits_req_in3_expOut_T \| _sfma_io_in_bits_req_in3_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [5:0] _sfma_io_in_bits_req_in3_expOut_T_3 = sfma_io_in_bits_req_in3_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:69] wire [8:0] _sfma_io_in_bits_req_in3_expOut_T_4 = {sfma_io_in_bits_req_in3_expOut_expCode, _sfma_io_in_bits_req_in3_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [8:0] _sfma_io_in_bits_req_in3_expOut_T_5 = sfma_io_in_bits_req_in3_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:97] wire [8:0] sfma_io_in_bits_req_in3_expOut = _sfma_io_in_bits_req_in3_expOut_T_2 ? _sfma_io_in_bits_req_in3_expOut_T_4 : _sfma_io_in_bits_req_in3_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [9:0] sfma_io_in_bits_req_in3_hi = {sfma_io_in_bits_req_in3_sign, sfma_io_in_bits_req_in3_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [32:0] sfma_io_in_bits_req_in3_floats_2 = {sfma_io_in_bits_req_in3_hi, sfma_io_in_bits_req_in3_fractOut}; // @[FPU.scala:277:38, :283:8] wire [32:0] _sfma_io_in_bits_req_in3_T = sfma_io_in_bits_req_in3_oks_1 ? 33'h0 : 33'hE0400000; // @[FPU.scala:362:32, :372:31] wire [32:0] _sfma_io_in_bits_req_in3_T_1 = sfma_io_in_bits_req_in3_floats_1 \| _sfma_io_in_bits_req_in3_T; // @[FPU.scala:356:31, :372:{26,31}] assign sfma_io_in_bits_req_in3 = {32'h0, _sfma_io_in_bits_req_in3_T_1}; // @[FPU.scala:372:26, :848:19, :854:13] assign _sfma_io_in_bits_req_typ_T = ex_reg_inst[21:20]; // @[FPU.scala:768:30, :855:27] wire [1:0] _fpiu_io_in_bits_req_typ_T = ex_reg_inst[21:20]; // @[FPU.scala:768:30, :855:27] wire [1:0] _dfma_io_in_bits_req_typ_T = ex_reg_inst[21:20]; // @[FPU.scala:768:30, :855:27] wire [1:0] _hfma_io_in_bits_req_typ_T = ex_reg_inst[21:20]; // @[FPU.scala:768:30, :855:27] assign sfma_io_in_bits_req_typ = _sfma_io_in_bits_req_typ_T; // @[FPU.scala:848:19, :855:27] assign _sfma_io_in_bits_req_fmt_T = ex_reg_inst[26:25]; // @[FPU.scala:768:30, :856:27] wire [1:0] _fpiu_io_in_bits_req_fmt_T = ex_reg_inst[26:25]; // @[FPU.scala:768:30, :856:27] wire [1:0] _dfma_io_in_bits_req_fmt_T = ex_reg_inst[26:25]; // @[FPU.scala:768:30, :856:27] wire [1:0] _hfma_io_in_bits_req_fmt_T = ex_reg_inst[26:25]; // @[FPU.scala:768:30, :856:27] assign sfma_io_in_bits_req_fmt = _sfma_io_in_bits_req_fmt_T; // @[FPU.scala:848:19, :856:27] wire [1:0] _sfma_io_in_bits_req_fmaCmd_T = ex_reg_inst[3:2]; // @[FPU.scala:768:30, :857:30] wire [1:0] _fpiu_io_in_bits_req_fmaCmd_T = ex_reg_inst[3:2]; // @[FPU.scala:768:30, :857:30] wire [1:0] _dfma_io_in_bits_req_fmaCmd_T = ex_reg_inst[3:2]; // @[FPU.scala:768:30, :857:30] wire [1:0] _hfma_io_in_bits_req_fmaCmd_T = ex_reg_inst[3:2]; // @[FPU.scala:768:30, :857:30] wire _sfma_io_in_bits_req_fmaCmd_T_1 = ~ex_ctrl_ren3; // @[FPU.scala:800:20, :857:39] wire _sfma_io_in_bits_req_fmaCmd_T_2 = ex_reg_inst[27]; // @[FPU.scala:768:30, :857:67] wire _fpiu_io_in_bits_req_fmaCmd_T_2 = ex_reg_inst[27]; // @[FPU.scala:768:30, :857:67] wire _dfma_io_in_bits_req_fmaCmd_T_2 = ex_reg_inst[27]; // @[FPU.scala:768:30, :857:67] wire _hfma_io_in_bits_req_fmaCmd_T_2 = ex_reg_inst[27]; // @[FPU.scala:768:30, :857:67] wire _sfma_io_in_bits_req_fmaCmd_T_3 = _sfma_io_in_bits_req_fmaCmd_T_1 & _sfma_io_in_bits_req_fmaCmd_T_2; // @[FPU.scala:857:{39,53,67}] assign _sfma_io_in_bits_req_fmaCmd_T_4 = {_sfma_io_in_bits_req_fmaCmd_T[1], _sfma_io_in_bits_req_fmaCmd_T[0] \| _sfma_io_in_bits_req_fmaCmd_T_3}; // @[FPU.scala:857:{30,36,53}] assign sfma_io_in_bits_req_fmaCmd = _sfma_io_in_bits_req_fmaCmd_T_4; // @[FPU.scala:848:19, :857:36] wire _fpiu_io_in_valid_T = ex_ctrl_toint \| ex_ctrl_div; // @[FPU.scala:800:20, :877:51] wire _fpiu_io_in_valid_T_1 = _fpiu_io_in_valid_T \| ex_ctrl_sqrt; // @[FPU.scala:800:20, :877:{51,66}] wire _fpiu_io_in_valid_T_2 = ex_ctrl_fastpipe & ex_ctrl_wflags; // @[FPU.scala:800:20, :877:103] wire _fpiu_io_in_valid_T_3 = _fpiu_io_in_valid_T_1 \| _fpiu_io_in_valid_T_2; // @[FPU.scala:877:{66,82,103}] wire _fpiu_io_in_valid_T_4 = req_valid & _fpiu_io_in_valid_T_3; // @[FPU.scala:780:32, :877:{33,82}] wire [1:0] _fpiu_io_in_bits_req_fmaCmd_T_4; // @[FPU.scala:857:36] wire [64:0] _fpiu_io_in_bits_req_in1_T_12; // @[FPU.scala:369:10] wire [64:0] _fpiu_io_in_bits_req_in2_T_12; // @[FPU.scala:369:10] wire [64:0] _fpiu_io_in_bits_req_in3_T_12; // @[FPU.scala:369:10] wire [1:0] fpiu_io_in_bits_req_fmaCmd; // @[FPU.scala:848:19] wire [1:0] fpiu_io_in_bits_req_typ; // @[FPU.scala:848:19] wire [1:0] fpiu_io_in_bits_req_fmt; // @[FPU.scala:848:19] wire [64:0] fpiu_io_in_bits_req_in1; // @[FPU.scala:848:19] wire [64:0] fpiu_io_in_bits_req_in2; // @[FPU.scala:848:19] wire [64:0] fpiu_io_in_bits_req_in3; // @[FPU.scala:848:19] wire [1:0] fpiu_io_in_bits_req_in1_prev_unswizzled_hi = {_fpiu_io_in_bits_req_in1_prev_unswizzled_T, _fpiu_io_in_bits_req_in1_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [32:0] fpiu_io_in_bits_req_in1_prev_unswizzled = {fpiu_io_in_bits_req_in1_prev_unswizzled_hi, _fpiu_io_in_bits_req_in1_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire _fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled_T = fpiu_io_in_bits_req_in1_prev_unswizzled[15]; // @[FPU.scala:356:31, :357:14] wire _fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_1 = fpiu_io_in_bits_req_in1_prev_unswizzled[23]; // @[FPU.scala:356:31, :358:14] wire [14:0] _fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_2 = fpiu_io_in_bits_req_in1_prev_unswizzled[14:0]; // @[FPU.scala:356:31, :359:14] wire [1:0] fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled_hi = {_fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled_T, _fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [16:0] fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled = {fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled_hi, _fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire fpiu_io_in_bits_req_in1_prev_prev_prev_prev_sign = fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled[16]; // @[FPU.scala:274:17, :356:31] wire [9:0] fpiu_io_in_bits_req_in1_prev_prev_prev_prev_fractIn = fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled[9:0]; // @[FPU.scala:275:20, :356:31] wire [5:0] fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expIn = fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled[15:10]; // @[FPU.scala:276:18, :356:31] wire [62:0] _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_fractOut_T = {fpiu_io_in_bits_req_in1_prev_prev_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28] wire [51:0] fpiu_io_in_bits_req_in1_prev_prev_prev_prev_fractOut = _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_fractOut_T[62:11]; // @[FPU.scala:277:{28,38}] wire [2:0] fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode = fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expIn[5:3]; // @[FPU.scala:276:18, :279:26] wire [12:0] _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T = {7'h0, fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31] wire [11:0] _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_1 = _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_2 = {1'h0, _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_1} - 13'h20; // @[FPU.scala:280:{31,50}] wire [11:0] fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase = _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire [11:0] _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_5 = fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T = fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_1 = fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_2 = _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T \| _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [8:0] _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_3 = fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69] wire [11:0] _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_4 = {fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode, _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [11:0] fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut = _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_2 ? _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_4 : _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [12:0] fpiu_io_in_bits_req_in1_prev_prev_prev_prev_hi = {fpiu_io_in_bits_req_in1_prev_prev_prev_prev_sign, fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [64:0] fpiu_io_in_bits_req_in1_floats_0 = {fpiu_io_in_bits_req_in1_prev_prev_prev_prev_hi, fpiu_io_in_bits_req_in1_prev_prev_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire [4:0] _fpiu_io_in_bits_req_in1_prev_prev_prev_isbox_T = fpiu_io_in_bits_req_in1_prev_unswizzled[32:28]; // @[FPU.scala:332:49, :356:31] wire fpiu_io_in_bits_req_in1_prev_prev_prev_isbox = &_fpiu_io_in_bits_req_in1_prev_prev_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire fpiu_io_in_bits_req_in1_prev_prev_0_1 = fpiu_io_in_bits_req_in1_prev_prev_prev_isbox; // @[FPU.scala:332:84, :362:32] wire fpiu_io_in_bits_req_in1_prev_prev_sign = fpiu_io_in_bits_req_in1_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31] wire [22:0] fpiu_io_in_bits_req_in1_prev_prev_fractIn = fpiu_io_in_bits_req_in1_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31] wire [8:0] fpiu_io_in_bits_req_in1_prev_prev_expIn = fpiu_io_in_bits_req_in1_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31] wire [75:0] _fpiu_io_in_bits_req_in1_prev_prev_fractOut_T = {fpiu_io_in_bits_req_in1_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28] wire [51:0] fpiu_io_in_bits_req_in1_prev_prev_fractOut = _fpiu_io_in_bits_req_in1_prev_prev_fractOut_T[75:24]; // @[FPU.scala:277:{28,38}] wire [2:0] fpiu_io_in_bits_req_in1_prev_prev_expOut_expCode = fpiu_io_in_bits_req_in1_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26] wire [12:0] _fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T = {4'h0, fpiu_io_in_bits_req_in1_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31] wire [11:0] _fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_1 = _fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2 = {1'h0, _fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_1} - 13'h100; // @[FPU.scala:280:{31,50}] wire [11:0] fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase = _fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire [11:0] _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_5 = fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _fpiu_io_in_bits_req_in1_prev_prev_expOut_T = fpiu_io_in_bits_req_in1_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_1 = fpiu_io_in_bits_req_in1_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_2 = _fpiu_io_in_bits_req_in1_prev_prev_expOut_T \| _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [8:0] _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_3 = fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69] wire [11:0] _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_4 = {fpiu_io_in_bits_req_in1_prev_prev_expOut_expCode, _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [11:0] fpiu_io_in_bits_req_in1_prev_prev_expOut = _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_2 ? _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_4 : _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [12:0] fpiu_io_in_bits_req_in1_prev_prev_hi = {fpiu_io_in_bits_req_in1_prev_prev_sign, fpiu_io_in_bits_req_in1_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [64:0] fpiu_io_in_bits_req_in1_floats_1 = {fpiu_io_in_bits_req_in1_prev_prev_hi, fpiu_io_in_bits_req_in1_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire fpiu_io_in_bits_req_in1_prev_isbox = &_fpiu_io_in_bits_req_in1_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire fpiu_io_in_bits_req_in1_oks_1 = fpiu_io_in_bits_req_in1_prev_isbox; // @[FPU.scala:332:84, :362:32] wire fpiu_io_in_bits_req_in1_oks_0 = fpiu_io_in_bits_req_in1_prev_isbox & fpiu_io_in_bits_req_in1_prev_prev_0_1; // @[FPU.scala:332:84, :362:32] wire _GEN_2 = ex_ctrl_typeTagIn == 2'h1; // @[package.scala:39:86] wire _fpiu_io_in_bits_req_in1_T; // @[package.scala:39:86] assign _fpiu_io_in_bits_req_in1_T = _GEN_2; // @[package.scala:39:86] wire _fpiu_io_in_bits_req_in1_T_6; // @[package.scala:39:86] assign _fpiu_io_in_bits_req_in1_T_6 = _GEN_2; // @[package.scala:39:86] wire _fpiu_io_in_bits_req_in2_T; // @[package.scala:39:86] assign _fpiu_io_in_bits_req_in2_T = _GEN_2; // @[package.scala:39:86] wire _fpiu_io_in_bits_req_in2_T_6; // @[package.scala:39:86] assign _fpiu_io_in_bits_req_in2_T_6 = _GEN_2; // @[package.scala:39:86] wire _fpiu_io_in_bits_req_in3_T; // @[package.scala:39:86] assign _fpiu_io_in_bits_req_in3_T = _GEN_2; // @[package.scala:39:86] wire _fpiu_io_in_bits_req_in3_T_6; // @[package.scala:39:86] assign _fpiu_io_in_bits_req_in3_T_6 = _GEN_2; // @[package.scala:39:86] wire _fpiu_io_in_bits_req_in1_T_1 = _fpiu_io_in_bits_req_in1_T ? fpiu_io_in_bits_req_in1_oks_1 : fpiu_io_in_bits_req_in1_oks_0; // @[package.scala:39:{76,86}] wire _GEN_3 = ex_ctrl_typeTagIn == 2'h2; // @[package.scala:39:86] wire _fpiu_io_in_bits_req_in1_T_2; // @[package.scala:39:86] assign _fpiu_io_in_bits_req_in1_T_2 = _GEN_3; // @[package.scala:39:86] wire _fpiu_io_in_bits_req_in1_T_8; // @[package.scala:39:86] assign _fpiu_io_in_bits_req_in1_T_8 = _GEN_3; // @[package.scala:39:86] wire _fpiu_io_in_bits_req_in2_T_2; // @[package.scala:39:86] assign _fpiu_io_in_bits_req_in2_T_2 = _GEN_3; // @[package.scala:39:86] wire _fpiu_io_in_bits_req_in2_T_8; // @[package.scala:39:86] assign _fpiu_io_in_bits_req_in2_T_8 = _GEN_3; // @[package.scala:39:86] wire _fpiu_io_in_bits_req_in3_T_2; // @[package.scala:39:86] assign _fpiu_io_in_bits_req_in3_T_2 = _GEN_3; // @[package.scala:39:86] wire _fpiu_io_in_bits_req_in3_T_8; // @[package.scala:39:86] assign _fpiu_io_in_bits_req_in3_T_8 = _GEN_3; // @[package.scala:39:86] wire _fpiu_io_in_bits_req_in1_T_3 = _fpiu_io_in_bits_req_in1_T_2 \| _fpiu_io_in_bits_req_in1_T_1; // @[package.scala:39:{76,86}] wire _fpiu_io_in_bits_req_in1_T_4 = &ex_ctrl_typeTagIn; // @[package.scala:39:86] wire _fpiu_io_in_bits_req_in1_T_5 = _fpiu_io_in_bits_req_in1_T_4 \| _fpiu_io_in_bits_req_in1_T_3; // @[package.scala:39:{76,86}] wire [64:0] _fpiu_io_in_bits_req_in1_T_7 = _fpiu_io_in_bits_req_in1_T_6 ? fpiu_io_in_bits_req_in1_floats_1 : fpiu_io_in_bits_req_in1_floats_0; // @[package.scala:39:{76,86}] wire [64:0] _fpiu_io_in_bits_req_in1_T_9 = _fpiu_io_in_bits_req_in1_T_8 ? _regfile_ext_R2_data : _fpiu_io_in_bits_req_in1_T_7; // @[package.scala:39:{76,86}] wire _fpiu_io_in_bits_req_in1_T_10 = &ex_ctrl_typeTagIn; // @[package.scala:39:86] wire [64:0] _fpiu_io_in_bits_req_in1_T_11 = _fpiu_io_in_bits_req_in1_T_10 ? _regfile_ext_R2_data : _fpiu_io_in_bits_req_in1_T_9; // @[package.scala:39:{76,86}] assign _fpiu_io_in_bits_req_in1_T_12 = _fpiu_io_in_bits_req_in1_T_5 ? _fpiu_io_in_bits_req_in1_T_11 : 65'hE008000000000000; // @[package.scala:39:76] assign fpiu_io_in_bits_req_in1 = _fpiu_io_in_bits_req_in1_T_12; // @[FPU.scala:369:10, :848:19] wire [1:0] fpiu_io_in_bits_req_in2_prev_unswizzled_hi = {_fpiu_io_in_bits_req_in2_prev_unswizzled_T, _fpiu_io_in_bits_req_in2_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [32:0] fpiu_io_in_bits_req_in2_prev_unswizzled = {fpiu_io_in_bits_req_in2_prev_unswizzled_hi, _fpiu_io_in_bits_req_in2_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire _fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled_T = fpiu_io_in_bits_req_in2_prev_unswizzled[15]; // @[FPU.scala:356:31, :357:14] wire _fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_1 = fpiu_io_in_bits_req_in2_prev_unswizzled[23]; // @[FPU.scala:356:31, :358:14] wire [14:0] _fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_2 = fpiu_io_in_bits_req_in2_prev_unswizzled[14:0]; // @[FPU.scala:356:31, :359:14] wire [1:0] fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled_hi = {_fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled_T, _fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [16:0] fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled = {fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled_hi, _fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire fpiu_io_in_bits_req_in2_prev_prev_prev_prev_sign = fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled[16]; // @[FPU.scala:274:17, :356:31] wire [9:0] fpiu_io_in_bits_req_in2_prev_prev_prev_prev_fractIn = fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled[9:0]; // @[FPU.scala:275:20, :356:31] wire [5:0] fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expIn = fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled[15:10]; // @[FPU.scala:276:18, :356:31] wire [62:0] _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_fractOut_T = {fpiu_io_in_bits_req_in2_prev_prev_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28] wire [51:0] fpiu_io_in_bits_req_in2_prev_prev_prev_prev_fractOut = _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_fractOut_T[62:11]; // @[FPU.scala:277:{28,38}] wire [2:0] fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode = fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expIn[5:3]; // @[FPU.scala:276:18, :279:26] wire [12:0] _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T = {7'h0, fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31] wire [11:0] _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_1 = _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_2 = {1'h0, _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_1} - 13'h20; // @[FPU.scala:280:{31,50}] wire [11:0] fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase = _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire [11:0] _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_5 = fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T = fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_1 = fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_2 = _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T \| _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [8:0] _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_3 = fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69] wire [11:0] _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_4 = {fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode, _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [11:0] fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut = _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_2 ? _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_4 : _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [12:0] fpiu_io_in_bits_req_in2_prev_prev_prev_prev_hi = {fpiu_io_in_bits_req_in2_prev_prev_prev_prev_sign, fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [64:0] fpiu_io_in_bits_req_in2_floats_0 = {fpiu_io_in_bits_req_in2_prev_prev_prev_prev_hi, fpiu_io_in_bits_req_in2_prev_prev_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire [4:0] _fpiu_io_in_bits_req_in2_prev_prev_prev_isbox_T = fpiu_io_in_bits_req_in2_prev_unswizzled[32:28]; // @[FPU.scala:332:49, :356:31] wire fpiu_io_in_bits_req_in2_prev_prev_prev_isbox = &_fpiu_io_in_bits_req_in2_prev_prev_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire fpiu_io_in_bits_req_in2_prev_prev_0_1 = fpiu_io_in_bits_req_in2_prev_prev_prev_isbox; // @[FPU.scala:332:84, :362:32] wire fpiu_io_in_bits_req_in2_prev_prev_sign = fpiu_io_in_bits_req_in2_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31] wire [22:0] fpiu_io_in_bits_req_in2_prev_prev_fractIn = fpiu_io_in_bits_req_in2_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31] wire [8:0] fpiu_io_in_bits_req_in2_prev_prev_expIn = fpiu_io_in_bits_req_in2_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31] wire [75:0] _fpiu_io_in_bits_req_in2_prev_prev_fractOut_T = {fpiu_io_in_bits_req_in2_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28] wire [51:0] fpiu_io_in_bits_req_in2_prev_prev_fractOut = _fpiu_io_in_bits_req_in2_prev_prev_fractOut_T[75:24]; // @[FPU.scala:277:{28,38}] wire [2:0] fpiu_io_in_bits_req_in2_prev_prev_expOut_expCode = fpiu_io_in_bits_req_in2_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26] wire [12:0] _fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T = {4'h0, fpiu_io_in_bits_req_in2_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31] wire [11:0] _fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_1 = _fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2 = {1'h0, _fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_1} - 13'h100; // @[FPU.scala:280:{31,50}] wire [11:0] fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase = _fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire [11:0] _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_5 = fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _fpiu_io_in_bits_req_in2_prev_prev_expOut_T = fpiu_io_in_bits_req_in2_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_1 = fpiu_io_in_bits_req_in2_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_2 = _fpiu_io_in_bits_req_in2_prev_prev_expOut_T \| _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [8:0] _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_3 = fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69] wire [11:0] _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_4 = {fpiu_io_in_bits_req_in2_prev_prev_expOut_expCode, _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [11:0] fpiu_io_in_bits_req_in2_prev_prev_expOut = _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_2 ? _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_4 : _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [12:0] fpiu_io_in_bits_req_in2_prev_prev_hi = {fpiu_io_in_bits_req_in2_prev_prev_sign, fpiu_io_in_bits_req_in2_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [64:0] fpiu_io_in_bits_req_in2_floats_1 = {fpiu_io_in_bits_req_in2_prev_prev_hi, fpiu_io_in_bits_req_in2_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire fpiu_io_in_bits_req_in2_prev_isbox = &_fpiu_io_in_bits_req_in2_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire fpiu_io_in_bits_req_in2_oks_1 = fpiu_io_in_bits_req_in2_prev_isbox; // @[FPU.scala:332:84, :362:32] wire fpiu_io_in_bits_req_in2_oks_0 = fpiu_io_in_bits_req_in2_prev_isbox & fpiu_io_in_bits_req_in2_prev_prev_0_1; // @[FPU.scala:332:84, :362:32] wire _fpiu_io_in_bits_req_in2_T_1 = _fpiu_io_in_bits_req_in2_T ? fpiu_io_in_bits_req_in2_oks_1 : fpiu_io_in_bits_req_in2_oks_0; // @[package.scala:39:{76,86}] wire _fpiu_io_in_bits_req_in2_T_3 = _fpiu_io_in_bits_req_in2_T_2 \| _fpiu_io_in_bits_req_in2_T_1; // @[package.scala:39:{76,86}] wire _fpiu_io_in_bits_req_in2_T_4 = &ex_ctrl_typeTagIn; // @[package.scala:39:86] wire _fpiu_io_in_bits_req_in2_T_5 = _fpiu_io_in_bits_req_in2_T_4 \| _fpiu_io_in_bits_req_in2_T_3; // @[package.scala:39:{76,86}] wire [64:0] _fpiu_io_in_bits_req_in2_T_7 = _fpiu_io_in_bits_req_in2_T_6 ? fpiu_io_in_bits_req_in2_floats_1 : fpiu_io_in_bits_req_in2_floats_0; // @[package.scala:39:{76,86}] wire [64:0] _fpiu_io_in_bits_req_in2_T_9 = _fpiu_io_in_bits_req_in2_T_8 ? _regfile_ext_R1_data : _fpiu_io_in_bits_req_in2_T_7; // @[package.scala:39:{76,86}] wire _fpiu_io_in_bits_req_in2_T_10 = &ex_ctrl_typeTagIn; // @[package.scala:39:86] wire [64:0] _fpiu_io_in_bits_req_in2_T_11 = _fpiu_io_in_bits_req_in2_T_10 ? _regfile_ext_R1_data : _fpiu_io_in_bits_req_in2_T_9; // @[package.scala:39:{76,86}] assign _fpiu_io_in_bits_req_in2_T_12 = _fpiu_io_in_bits_req_in2_T_5 ? _fpiu_io_in_bits_req_in2_T_11 : 65'hE008000000000000; // @[package.scala:39:76] assign fpiu_io_in_bits_req_in2 = _fpiu_io_in_bits_req_in2_T_12; // @[FPU.scala:369:10, :848:19] wire [1:0] fpiu_io_in_bits_req_in3_prev_unswizzled_hi = {_fpiu_io_in_bits_req_in3_prev_unswizzled_T, _fpiu_io_in_bits_req_in3_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [32:0] fpiu_io_in_bits_req_in3_prev_unswizzled = {fpiu_io_in_bits_req_in3_prev_unswizzled_hi, _fpiu_io_in_bits_req_in3_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire _fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled_T = fpiu_io_in_bits_req_in3_prev_unswizzled[15]; // @[FPU.scala:356:31, :357:14] wire _fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_1 = fpiu_io_in_bits_req_in3_prev_unswizzled[23]; // @[FPU.scala:356:31, :358:14] wire [14:0] _fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_2 = fpiu_io_in_bits_req_in3_prev_unswizzled[14:0]; // @[FPU.scala:356:31, :359:14] wire [1:0] fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled_hi = {_fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled_T, _fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [16:0] fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled = {fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled_hi, _fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire fpiu_io_in_bits_req_in3_prev_prev_prev_prev_sign = fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled[16]; // @[FPU.scala:274:17, :356:31] wire [9:0] fpiu_io_in_bits_req_in3_prev_prev_prev_prev_fractIn = fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled[9:0]; // @[FPU.scala:275:20, :356:31] wire [5:0] fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expIn = fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled[15:10]; // @[FPU.scala:276:18, :356:31] wire [62:0] _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_fractOut_T = {fpiu_io_in_bits_req_in3_prev_prev_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28] wire [51:0] fpiu_io_in_bits_req_in3_prev_prev_prev_prev_fractOut = _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_fractOut_T[62:11]; // @[FPU.scala:277:{28,38}] wire [2:0] fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode = fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expIn[5:3]; // @[FPU.scala:276:18, :279:26] wire [12:0] _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T = {7'h0, fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31] wire [11:0] _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_1 = _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_2 = {1'h0, _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_1} - 13'h20; // @[FPU.scala:280:{31,50}] wire [11:0] fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase = _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire [11:0] _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_5 = fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T = fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_1 = fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_2 = _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T \| _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [8:0] _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_3 = fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69] wire [11:0] _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_4 = {fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode, _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [11:0] fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut = _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_2 ? _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_4 : _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [12:0] fpiu_io_in_bits_req_in3_prev_prev_prev_prev_hi = {fpiu_io_in_bits_req_in3_prev_prev_prev_prev_sign, fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [64:0] fpiu_io_in_bits_req_in3_floats_0 = {fpiu_io_in_bits_req_in3_prev_prev_prev_prev_hi, fpiu_io_in_bits_req_in3_prev_prev_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire [4:0] _fpiu_io_in_bits_req_in3_prev_prev_prev_isbox_T = fpiu_io_in_bits_req_in3_prev_unswizzled[32:28]; // @[FPU.scala:332:49, :356:31] wire fpiu_io_in_bits_req_in3_prev_prev_prev_isbox = &_fpiu_io_in_bits_req_in3_prev_prev_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire fpiu_io_in_bits_req_in3_prev_prev_0_1 = fpiu_io_in_bits_req_in3_prev_prev_prev_isbox; // @[FPU.scala:332:84, :362:32] wire fpiu_io_in_bits_req_in3_prev_prev_sign = fpiu_io_in_bits_req_in3_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31] wire [22:0] fpiu_io_in_bits_req_in3_prev_prev_fractIn = fpiu_io_in_bits_req_in3_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31] wire [8:0] fpiu_io_in_bits_req_in3_prev_prev_expIn = fpiu_io_in_bits_req_in3_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31] wire [75:0] _fpiu_io_in_bits_req_in3_prev_prev_fractOut_T = {fpiu_io_in_bits_req_in3_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28] wire [51:0] fpiu_io_in_bits_req_in3_prev_prev_fractOut = _fpiu_io_in_bits_req_in3_prev_prev_fractOut_T[75:24]; // @[FPU.scala:277:{28,38}] wire [2:0] fpiu_io_in_bits_req_in3_prev_prev_expOut_expCode = fpiu_io_in_bits_req_in3_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26] wire [12:0] _fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T = {4'h0, fpiu_io_in_bits_req_in3_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31] wire [11:0] _fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_1 = _fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_2 = {1'h0, _fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_1} - 13'h100; // @[FPU.scala:280:{31,50}] wire [11:0] fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase = _fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire [11:0] _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_5 = fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _fpiu_io_in_bits_req_in3_prev_prev_expOut_T = fpiu_io_in_bits_req_in3_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_1 = fpiu_io_in_bits_req_in3_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_2 = _fpiu_io_in_bits_req_in3_prev_prev_expOut_T \| _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [8:0] _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_3 = fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69] wire [11:0] _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_4 = {fpiu_io_in_bits_req_in3_prev_prev_expOut_expCode, _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [11:0] fpiu_io_in_bits_req_in3_prev_prev_expOut = _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_2 ? _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_4 : _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [12:0] fpiu_io_in_bits_req_in3_prev_prev_hi = {fpiu_io_in_bits_req_in3_prev_prev_sign, fpiu_io_in_bits_req_in3_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [64:0] fpiu_io_in_bits_req_in3_floats_1 = {fpiu_io_in_bits_req_in3_prev_prev_hi, fpiu_io_in_bits_req_in3_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire fpiu_io_in_bits_req_in3_prev_isbox = &_fpiu_io_in_bits_req_in3_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire fpiu_io_in_bits_req_in3_oks_1 = fpiu_io_in_bits_req_in3_prev_isbox; // @[FPU.scala:332:84, :362:32] wire fpiu_io_in_bits_req_in3_oks_0 = fpiu_io_in_bits_req_in3_prev_isbox & fpiu_io_in_bits_req_in3_prev_prev_0_1; // @[FPU.scala:332:84, :362:32] wire _fpiu_io_in_bits_req_in3_T_1 = _fpiu_io_in_bits_req_in3_T ? fpiu_io_in_bits_req_in3_oks_1 : fpiu_io_in_bits_req_in3_oks_0; // @[package.scala:39:{76,86}] wire _fpiu_io_in_bits_req_in3_T_3 = _fpiu_io_in_bits_req_in3_T_2 \| _fpiu_io_in_bits_req_in3_T_1; // @[package.scala:39:{76,86}] wire _fpiu_io_in_bits_req_in3_T_4 = &ex_ctrl_typeTagIn; // @[package.scala:39:86] wire _fpiu_io_in_bits_req_in3_T_5 = _fpiu_io_in_bits_req_in3_T_4 \| _fpiu_io_in_bits_req_in3_T_3; // @[package.scala:39:{76,86}] wire [64:0] _fpiu_io_in_bits_req_in3_T_7 = _fpiu_io_in_bits_req_in3_T_6 ? fpiu_io_in_bits_req_in3_floats_1 : fpiu_io_in_bits_req_in3_floats_0; // @[package.scala:39:{76,86}] wire [64:0] _fpiu_io_in_bits_req_in3_T_9 = _fpiu_io_in_bits_req_in3_T_8 ? _regfile_ext_R0_data : _fpiu_io_in_bits_req_in3_T_7; // @[package.scala:39:{76,86}] wire _fpiu_io_in_bits_req_in3_T_10 = &ex_ctrl_typeTagIn; // @[package.scala:39:86] wire [64:0] _fpiu_io_in_bits_req_in3_T_11 = _fpiu_io_in_bits_req_in3_T_10 ? _regfile_ext_R0_data : _fpiu_io_in_bits_req_in3_T_9; // @[package.scala:39:{76,86}] assign _fpiu_io_in_bits_req_in3_T_12 = _fpiu_io_in_bits_req_in3_T_5 ? _fpiu_io_in_bits_req_in3_T_11 : 65'hE008000000000000; // @[package.scala:39:76] assign fpiu_io_in_bits_req_in3 = _fpiu_io_in_bits_req_in3_T_12; // @[FPU.scala:369:10, :848:19] assign fpiu_io_in_bits_req_typ = _fpiu_io_in_bits_req_typ_T; // @[FPU.scala:848:19, :855:27] assign fpiu_io_in_bits_req_fmt = _fpiu_io_in_bits_req_fmt_T; // @[FPU.scala:848:19, :856:27] wire _fpiu_io_in_bits_req_fmaCmd_T_1 = ~ex_ctrl_ren3; // @[FPU.scala:800:20, :857:39] wire _fpiu_io_in_bits_req_fmaCmd_T_3 = _fpiu_io_in_bits_req_fmaCmd_T_1 & _fpiu_io_in_bits_req_fmaCmd_T_2; // @[FPU.scala:857:{39,53,67}] assign _fpiu_io_in_bits_req_fmaCmd_T_4 = {_fpiu_io_in_bits_req_fmaCmd_T[1], _fpiu_io_in_bits_req_fmaCmd_T[0] \| _fpiu_io_in_bits_req_fmaCmd_T_3}; // @[FPU.scala:857:{30,36,53}] assign fpiu_io_in_bits_req_fmaCmd = _fpiu_io_in_bits_req_fmaCmd_T_4; // @[FPU.scala:848:19, :857:36] wire _ifpu_io_in_valid_T = req_valid & ex_ctrl_fromint; // @[FPU.scala:780:32, :800:20, :887:33] wire [64:0] _ifpu_io_in_bits_in1_T = {1'h0, io_fromint_data_0}; // @[FPU.scala:735:7, :889:29] wire _fpmu_io_in_valid_T = req_valid & ex_ctrl_fastpipe; // @[FPU.scala:780:32, :800:20, :892:33] wire divSqrt_wen; // @[FPU.scala:896:32] wire divSqrt_inFlight; // @[FPU.scala:897:37] reg [4:0] divSqrt_waddr; // @[FPU.scala:898:26] reg divSqrt_cp; // @[FPU.scala:899:23] wire [1:0] divSqrt_typeTag; // @[FPU.scala:900:29] wire [64:0] divSqrt_wdata; // @[FPU.scala:901:27] wire [4:0] divSqrt_flags; // @[FPU.scala:902:27] wire _GEN_4 = ex_ctrl_typeTagOut == 2'h2; // @[FPU.scala:800:20, :914:78] wire _dfma_io_in_valid_T_1; // @[FPU.scala:914:78] assign _dfma_io_in_valid_T_1 = _GEN_4; // @[FPU.scala:914:78] wire _write_port_busy_T_5; // @[FPU.scala:916:78] assign _write_port_busy_T_5 = _GEN_4; // @[FPU.scala:914:78, :916:78] wire _write_port_busy_T_23; // @[FPU.scala:916:78] assign _write_port_busy_T_23 = _GEN_4; // @[FPU.scala:914:78, :916:78] wire _dfma_io_in_valid_T_2 = _dfma_io_in_valid_T & _dfma_io_in_valid_T_1; // @[FPU.scala:914:{41,56,78}] wire [1:0] _dfma_io_in_bits_req_fmaCmd_T_4; // @[FPU.scala:857:36] wire [64:0] _dfma_io_in_bits_req_in1_T_1; // @[FPU.scala:372:26] wire [64:0] _dfma_io_in_bits_req_in2_T_1; // @[FPU.scala:372:26] wire [64:0] _dfma_io_in_bits_req_in3_T_1; // @[FPU.scala:372:26] wire [1:0] dfma_io_in_bits_req_fmaCmd; // @[FPU.scala:848:19] wire [1:0] dfma_io_in_bits_req_typ; // @[FPU.scala:848:19] wire [1:0] dfma_io_in_bits_req_fmt; // @[FPU.scala:848:19] wire [64:0] dfma_io_in_bits_req_in1; // @[FPU.scala:848:19] wire [64:0] dfma_io_in_bits_req_in2; // @[FPU.scala:848:19] wire [64:0] dfma_io_in_bits_req_in3; // @[FPU.scala:848:19] wire [1:0] dfma_io_in_bits_req_in1_prev_unswizzled_hi = {_dfma_io_in_bits_req_in1_prev_unswizzled_T, _dfma_io_in_bits_req_in1_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [32:0] dfma_io_in_bits_req_in1_prev_unswizzled = {dfma_io_in_bits_req_in1_prev_unswizzled_hi, _dfma_io_in_bits_req_in1_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire _dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T = dfma_io_in_bits_req_in1_prev_unswizzled[15]; // @[FPU.scala:356:31, :357:14] wire _dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_1 = dfma_io_in_bits_req_in1_prev_unswizzled[23]; // @[FPU.scala:356:31, :358:14] wire [14:0] _dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_2 = dfma_io_in_bits_req_in1_prev_unswizzled[14:0]; // @[FPU.scala:356:31, :359:14] wire [1:0] dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_hi = {_dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T, _dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [16:0] dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled = {dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_hi, _dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire dfma_io_in_bits_req_in1_prev_prev_prev_prev_sign = dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled[16]; // @[FPU.scala:274:17, :356:31] wire [9:0] dfma_io_in_bits_req_in1_prev_prev_prev_prev_fractIn = dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled[9:0]; // @[FPU.scala:275:20, :356:31] wire [5:0] dfma_io_in_bits_req_in1_prev_prev_prev_prev_expIn = dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled[15:10]; // @[FPU.scala:276:18, :356:31] wire [62:0] _dfma_io_in_bits_req_in1_prev_prev_prev_prev_fractOut_T = {dfma_io_in_bits_req_in1_prev_prev_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28] wire [51:0] dfma_io_in_bits_req_in1_prev_prev_prev_prev_fractOut = _dfma_io_in_bits_req_in1_prev_prev_prev_prev_fractOut_T[62:11]; // @[FPU.scala:277:{28,38}] wire [2:0] dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode = dfma_io_in_bits_req_in1_prev_prev_prev_prev_expIn[5:3]; // @[FPU.scala:276:18, :279:26] wire [12:0] _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T = {7'h0, dfma_io_in_bits_req_in1_prev_prev_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31] wire [11:0] _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_1 = _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_2 = {1'h0, _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_1} - 13'h20; // @[FPU.scala:280:{31,50}] wire [11:0] dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase = _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire [11:0] _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_5 = dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T = dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_1 = dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_2 = _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T \| _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [8:0] _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_3 = dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69] wire [11:0] _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_4 = {dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode, _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [11:0] dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut = _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_2 ? _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_4 : _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [12:0] dfma_io_in_bits_req_in1_prev_prev_prev_prev_hi = {dfma_io_in_bits_req_in1_prev_prev_prev_prev_sign, dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [64:0] dfma_io_in_bits_req_in1_floats_0 = {dfma_io_in_bits_req_in1_prev_prev_prev_prev_hi, dfma_io_in_bits_req_in1_prev_prev_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire [4:0] _dfma_io_in_bits_req_in1_prev_prev_prev_isbox_T = dfma_io_in_bits_req_in1_prev_unswizzled[32:28]; // @[FPU.scala:332:49, :356:31] wire dfma_io_in_bits_req_in1_prev_prev_prev_isbox = &_dfma_io_in_bits_req_in1_prev_prev_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire dfma_io_in_bits_req_in1_prev_prev_0_1 = dfma_io_in_bits_req_in1_prev_prev_prev_isbox; // @[FPU.scala:332:84, :362:32] wire dfma_io_in_bits_req_in1_prev_prev_sign = dfma_io_in_bits_req_in1_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31] wire [22:0] dfma_io_in_bits_req_in1_prev_prev_fractIn = dfma_io_in_bits_req_in1_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31] wire [8:0] dfma_io_in_bits_req_in1_prev_prev_expIn = dfma_io_in_bits_req_in1_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31] wire [75:0] _dfma_io_in_bits_req_in1_prev_prev_fractOut_T = {dfma_io_in_bits_req_in1_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28] wire [51:0] dfma_io_in_bits_req_in1_prev_prev_fractOut = _dfma_io_in_bits_req_in1_prev_prev_fractOut_T[75:24]; // @[FPU.scala:277:{28,38}] wire [2:0] dfma_io_in_bits_req_in1_prev_prev_expOut_expCode = dfma_io_in_bits_req_in1_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26] wire [12:0] _dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T = {4'h0, dfma_io_in_bits_req_in1_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31] wire [11:0] _dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_1 = _dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2 = {1'h0, _dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_1} - 13'h100; // @[FPU.scala:280:{31,50}] wire [11:0] dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase = _dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire [11:0] _dfma_io_in_bits_req_in1_prev_prev_expOut_T_5 = dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _dfma_io_in_bits_req_in1_prev_prev_expOut_T = dfma_io_in_bits_req_in1_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _dfma_io_in_bits_req_in1_prev_prev_expOut_T_1 = dfma_io_in_bits_req_in1_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _dfma_io_in_bits_req_in1_prev_prev_expOut_T_2 = _dfma_io_in_bits_req_in1_prev_prev_expOut_T \| _dfma_io_in_bits_req_in1_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [8:0] _dfma_io_in_bits_req_in1_prev_prev_expOut_T_3 = dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69] wire [11:0] _dfma_io_in_bits_req_in1_prev_prev_expOut_T_4 = {dfma_io_in_bits_req_in1_prev_prev_expOut_expCode, _dfma_io_in_bits_req_in1_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [11:0] dfma_io_in_bits_req_in1_prev_prev_expOut = _dfma_io_in_bits_req_in1_prev_prev_expOut_T_2 ? _dfma_io_in_bits_req_in1_prev_prev_expOut_T_4 : _dfma_io_in_bits_req_in1_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [12:0] dfma_io_in_bits_req_in1_prev_prev_hi = {dfma_io_in_bits_req_in1_prev_prev_sign, dfma_io_in_bits_req_in1_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [64:0] dfma_io_in_bits_req_in1_floats_1 = {dfma_io_in_bits_req_in1_prev_prev_hi, dfma_io_in_bits_req_in1_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire dfma_io_in_bits_req_in1_prev_isbox = &_dfma_io_in_bits_req_in1_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire dfma_io_in_bits_req_in1_oks_1 = dfma_io_in_bits_req_in1_prev_isbox; // @[FPU.scala:332:84, :362:32] wire dfma_io_in_bits_req_in1_oks_0 = dfma_io_in_bits_req_in1_prev_isbox & dfma_io_in_bits_req_in1_prev_prev_0_1; // @[FPU.scala:332:84, :362:32] assign dfma_io_in_bits_req_in1 = _dfma_io_in_bits_req_in1_T_1; // @[FPU.scala:372:26, :848:19] wire [1:0] dfma_io_in_bits_req_in2_prev_unswizzled_hi = {_dfma_io_in_bits_req_in2_prev_unswizzled_T, _dfma_io_in_bits_req_in2_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [32:0] dfma_io_in_bits_req_in2_prev_unswizzled = {dfma_io_in_bits_req_in2_prev_unswizzled_hi, _dfma_io_in_bits_req_in2_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire _dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T = dfma_io_in_bits_req_in2_prev_unswizzled[15]; // @[FPU.scala:356:31, :357:14] wire _dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_1 = dfma_io_in_bits_req_in2_prev_unswizzled[23]; // @[FPU.scala:356:31, :358:14] wire [14:0] _dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_2 = dfma_io_in_bits_req_in2_prev_unswizzled[14:0]; // @[FPU.scala:356:31, :359:14] wire [1:0] dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_hi = {_dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T, _dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [16:0] dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled = {dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_hi, _dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire dfma_io_in_bits_req_in2_prev_prev_prev_prev_sign = dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled[16]; // @[FPU.scala:274:17, :356:31] wire [9:0] dfma_io_in_bits_req_in2_prev_prev_prev_prev_fractIn = dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled[9:0]; // @[FPU.scala:275:20, :356:31] wire [5:0] dfma_io_in_bits_req_in2_prev_prev_prev_prev_expIn = dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled[15:10]; // @[FPU.scala:276:18, :356:31] wire [62:0] _dfma_io_in_bits_req_in2_prev_prev_prev_prev_fractOut_T = {dfma_io_in_bits_req_in2_prev_prev_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28] wire [51:0] dfma_io_in_bits_req_in2_prev_prev_prev_prev_fractOut = _dfma_io_in_bits_req_in2_prev_prev_prev_prev_fractOut_T[62:11]; // @[FPU.scala:277:{28,38}] wire [2:0] dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode = dfma_io_in_bits_req_in2_prev_prev_prev_prev_expIn[5:3]; // @[FPU.scala:276:18, :279:26] wire [12:0] _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T = {7'h0, dfma_io_in_bits_req_in2_prev_prev_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31] wire [11:0] _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_1 = _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_2 = {1'h0, _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_1} - 13'h20; // @[FPU.scala:280:{31,50}] wire [11:0] dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase = _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire [11:0] _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_5 = dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T = dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_1 = dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_2 = _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T \| _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [8:0] _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_3 = dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69] wire [11:0] _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_4 = {dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode, _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [11:0] dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut = _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_2 ? _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_4 : _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [12:0] dfma_io_in_bits_req_in2_prev_prev_prev_prev_hi = {dfma_io_in_bits_req_in2_prev_prev_prev_prev_sign, dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [64:0] dfma_io_in_bits_req_in2_floats_0 = {dfma_io_in_bits_req_in2_prev_prev_prev_prev_hi, dfma_io_in_bits_req_in2_prev_prev_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire [4:0] _dfma_io_in_bits_req_in2_prev_prev_prev_isbox_T = dfma_io_in_bits_req_in2_prev_unswizzled[32:28]; // @[FPU.scala:332:49, :356:31] wire dfma_io_in_bits_req_in2_prev_prev_prev_isbox = &_dfma_io_in_bits_req_in2_prev_prev_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire dfma_io_in_bits_req_in2_prev_prev_0_1 = dfma_io_in_bits_req_in2_prev_prev_prev_isbox; // @[FPU.scala:332:84, :362:32] wire dfma_io_in_bits_req_in2_prev_prev_sign = dfma_io_in_bits_req_in2_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31] wire [22:0] dfma_io_in_bits_req_in2_prev_prev_fractIn = dfma_io_in_bits_req_in2_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31] wire [8:0] dfma_io_in_bits_req_in2_prev_prev_expIn = dfma_io_in_bits_req_in2_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31] wire [75:0] _dfma_io_in_bits_req_in2_prev_prev_fractOut_T = {dfma_io_in_bits_req_in2_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28] wire [51:0] dfma_io_in_bits_req_in2_prev_prev_fractOut = _dfma_io_in_bits_req_in2_prev_prev_fractOut_T[75:24]; // @[FPU.scala:277:{28,38}] wire [2:0] dfma_io_in_bits_req_in2_prev_prev_expOut_expCode = dfma_io_in_bits_req_in2_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26] wire [12:0] _dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T = {4'h0, dfma_io_in_bits_req_in2_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31] wire [11:0] _dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_1 = _dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2 = {1'h0, _dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_1} - 13'h100; // @[FPU.scala:280:{31,50}] wire [11:0] dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase = _dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire [11:0] _dfma_io_in_bits_req_in2_prev_prev_expOut_T_5 = dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _dfma_io_in_bits_req_in2_prev_prev_expOut_T = dfma_io_in_bits_req_in2_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _dfma_io_in_bits_req_in2_prev_prev_expOut_T_1 = dfma_io_in_bits_req_in2_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _dfma_io_in_bits_req_in2_prev_prev_expOut_T_2 = _dfma_io_in_bits_req_in2_prev_prev_expOut_T \| _dfma_io_in_bits_req_in2_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [8:0] _dfma_io_in_bits_req_in2_prev_prev_expOut_T_3 = dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69] wire [11:0] _dfma_io_in_bits_req_in2_prev_prev_expOut_T_4 = {dfma_io_in_bits_req_in2_prev_prev_expOut_expCode, _dfma_io_in_bits_req_in2_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [11:0] dfma_io_in_bits_req_in2_prev_prev_expOut = _dfma_io_in_bits_req_in2_prev_prev_expOut_T_2 ? _dfma_io_in_bits_req_in2_prev_prev_expOut_T_4 : _dfma_io_in_bits_req_in2_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [12:0] dfma_io_in_bits_req_in2_prev_prev_hi = {dfma_io_in_bits_req_in2_prev_prev_sign, dfma_io_in_bits_req_in2_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [64:0] dfma_io_in_bits_req_in2_floats_1 = {dfma_io_in_bits_req_in2_prev_prev_hi, dfma_io_in_bits_req_in2_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire dfma_io_in_bits_req_in2_prev_isbox = &_dfma_io_in_bits_req_in2_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire dfma_io_in_bits_req_in2_oks_1 = dfma_io_in_bits_req_in2_prev_isbox; // @[FPU.scala:332:84, :362:32] wire dfma_io_in_bits_req_in2_oks_0 = dfma_io_in_bits_req_in2_prev_isbox & dfma_io_in_bits_req_in2_prev_prev_0_1; // @[FPU.scala:332:84, :362:32] assign dfma_io_in_bits_req_in2 = _dfma_io_in_bits_req_in2_T_1; // @[FPU.scala:372:26, :848:19] wire [1:0] dfma_io_in_bits_req_in3_prev_unswizzled_hi = {_dfma_io_in_bits_req_in3_prev_unswizzled_T, _dfma_io_in_bits_req_in3_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [32:0] dfma_io_in_bits_req_in3_prev_unswizzled = {dfma_io_in_bits_req_in3_prev_unswizzled_hi, _dfma_io_in_bits_req_in3_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire _dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T = dfma_io_in_bits_req_in3_prev_unswizzled[15]; // @[FPU.scala:356:31, :357:14] wire _dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_1 = dfma_io_in_bits_req_in3_prev_unswizzled[23]; // @[FPU.scala:356:31, :358:14] wire [14:0] _dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_2 = dfma_io_in_bits_req_in3_prev_unswizzled[14:0]; // @[FPU.scala:356:31, :359:14] wire [1:0] dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_hi = {_dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T, _dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [16:0] dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled = {dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_hi, _dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire dfma_io_in_bits_req_in3_prev_prev_prev_prev_sign = dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled[16]; // @[FPU.scala:274:17, :356:31] wire [9:0] dfma_io_in_bits_req_in3_prev_prev_prev_prev_fractIn = dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled[9:0]; // @[FPU.scala:275:20, :356:31] wire [5:0] dfma_io_in_bits_req_in3_prev_prev_prev_prev_expIn = dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled[15:10]; // @[FPU.scala:276:18, :356:31] wire [62:0] _dfma_io_in_bits_req_in3_prev_prev_prev_prev_fractOut_T = {dfma_io_in_bits_req_in3_prev_prev_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28] wire [51:0] dfma_io_in_bits_req_in3_prev_prev_prev_prev_fractOut = _dfma_io_in_bits_req_in3_prev_prev_prev_prev_fractOut_T[62:11]; // @[FPU.scala:277:{28,38}] wire [2:0] dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode = dfma_io_in_bits_req_in3_prev_prev_prev_prev_expIn[5:3]; // @[FPU.scala:276:18, :279:26] wire [12:0] _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T = {7'h0, dfma_io_in_bits_req_in3_prev_prev_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31] wire [11:0] _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_1 = _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_2 = {1'h0, _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_1} - 13'h20; // @[FPU.scala:280:{31,50}] wire [11:0] dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase = _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire [11:0] _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_5 = dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T = dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_1 = dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_2 = _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T \| _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [8:0] _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_3 = dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69] wire [11:0] _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_4 = {dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode, _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [11:0] dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut = _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_2 ? _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_4 : _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [12:0] dfma_io_in_bits_req_in3_prev_prev_prev_prev_hi = {dfma_io_in_bits_req_in3_prev_prev_prev_prev_sign, dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [64:0] dfma_io_in_bits_req_in3_floats_0 = {dfma_io_in_bits_req_in3_prev_prev_prev_prev_hi, dfma_io_in_bits_req_in3_prev_prev_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire [4:0] _dfma_io_in_bits_req_in3_prev_prev_prev_isbox_T = dfma_io_in_bits_req_in3_prev_unswizzled[32:28]; // @[FPU.scala:332:49, :356:31] wire dfma_io_in_bits_req_in3_prev_prev_prev_isbox = &_dfma_io_in_bits_req_in3_prev_prev_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire dfma_io_in_bits_req_in3_prev_prev_0_1 = dfma_io_in_bits_req_in3_prev_prev_prev_isbox; // @[FPU.scala:332:84, :362:32] wire dfma_io_in_bits_req_in3_prev_prev_sign = dfma_io_in_bits_req_in3_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31] wire [22:0] dfma_io_in_bits_req_in3_prev_prev_fractIn = dfma_io_in_bits_req_in3_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31] wire [8:0] dfma_io_in_bits_req_in3_prev_prev_expIn = dfma_io_in_bits_req_in3_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31] wire [75:0] _dfma_io_in_bits_req_in3_prev_prev_fractOut_T = {dfma_io_in_bits_req_in3_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28] wire [51:0] dfma_io_in_bits_req_in3_prev_prev_fractOut = _dfma_io_in_bits_req_in3_prev_prev_fractOut_T[75:24]; // @[FPU.scala:277:{28,38}] wire [2:0] dfma_io_in_bits_req_in3_prev_prev_expOut_expCode = dfma_io_in_bits_req_in3_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26] wire [12:0] _dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T = {4'h0, dfma_io_in_bits_req_in3_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31] wire [11:0] _dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_1 = _dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_2 = {1'h0, _dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_1} - 13'h100; // @[FPU.scala:280:{31,50}] wire [11:0] dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase = _dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire [11:0] _dfma_io_in_bits_req_in3_prev_prev_expOut_T_5 = dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _dfma_io_in_bits_req_in3_prev_prev_expOut_T = dfma_io_in_bits_req_in3_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _dfma_io_in_bits_req_in3_prev_prev_expOut_T_1 = dfma_io_in_bits_req_in3_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _dfma_io_in_bits_req_in3_prev_prev_expOut_T_2 = _dfma_io_in_bits_req_in3_prev_prev_expOut_T \| _dfma_io_in_bits_req_in3_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [8:0] _dfma_io_in_bits_req_in3_prev_prev_expOut_T_3 = dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69] wire [11:0] _dfma_io_in_bits_req_in3_prev_prev_expOut_T_4 = {dfma_io_in_bits_req_in3_prev_prev_expOut_expCode, _dfma_io_in_bits_req_in3_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [11:0] dfma_io_in_bits_req_in3_prev_prev_expOut = _dfma_io_in_bits_req_in3_prev_prev_expOut_T_2 ? _dfma_io_in_bits_req_in3_prev_prev_expOut_T_4 : _dfma_io_in_bits_req_in3_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [12:0] dfma_io_in_bits_req_in3_prev_prev_hi = {dfma_io_in_bits_req_in3_prev_prev_sign, dfma_io_in_bits_req_in3_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [64:0] dfma_io_in_bits_req_in3_floats_1 = {dfma_io_in_bits_req_in3_prev_prev_hi, dfma_io_in_bits_req_in3_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire dfma_io_in_bits_req_in3_prev_isbox = &_dfma_io_in_bits_req_in3_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire dfma_io_in_bits_req_in3_oks_1 = dfma_io_in_bits_req_in3_prev_isbox; // @[FPU.scala:332:84, :362:32] wire dfma_io_in_bits_req_in3_oks_0 = dfma_io_in_bits_req_in3_prev_isbox & dfma_io_in_bits_req_in3_prev_prev_0_1; // @[FPU.scala:332:84, :362:32] assign dfma_io_in_bits_req_in3 = _dfma_io_in_bits_req_in3_T_1; // @[FPU.scala:372:26, :848:19] assign dfma_io_in_bits_req_typ = _dfma_io_in_bits_req_typ_T; // @[FPU.scala:848:19, :855:27] assign dfma_io_in_bits_req_fmt = _dfma_io_in_bits_req_fmt_T; // @[FPU.scala:848:19, :856:27] wire _dfma_io_in_bits_req_fmaCmd_T_1 = ~ex_ctrl_ren3; // @[FPU.scala:800:20, :857:39] wire _dfma_io_in_bits_req_fmaCmd_T_3 = _dfma_io_in_bits_req_fmaCmd_T_1 & _dfma_io_in_bits_req_fmaCmd_T_2; // @[FPU.scala:857:{39,53,67}] assign _dfma_io_in_bits_req_fmaCmd_T_4 = {_dfma_io_in_bits_req_fmaCmd_T[1], _dfma_io_in_bits_req_fmaCmd_T[0] \| _dfma_io_in_bits_req_fmaCmd_T_3}; // @[FPU.scala:857:{30,36,53}] assign dfma_io_in_bits_req_fmaCmd = _dfma_io_in_bits_req_fmaCmd_T_4; // @[FPU.scala:848:19, :857:36] wire _GEN_5 = ex_ctrl_typeTagOut == 2'h0; // @[FPU.scala:800:20, :920:78] wire _hfma_io_in_valid_T_1; // @[FPU.scala:920:78] assign _hfma_io_in_valid_T_1 = _GEN_5; // @[FPU.scala:920:78] wire _write_port_busy_T_8; // @[FPU.scala:922:78] assign _write_port_busy_T_8 = _GEN_5; // @[FPU.scala:920:78, :922:78] wire _write_port_busy_T_26; // @[FPU.scala:922:78] assign _write_port_busy_T_26 = _GEN_5; // @[FPU.scala:920:78, :922:78] wire _hfma_io_in_valid_T_2 = _hfma_io_in_valid_T & _hfma_io_in_valid_T_1; // @[FPU.scala:920:{41,56,78}] wire [1:0] _hfma_io_in_bits_req_fmaCmd_T_4; // @[FPU.scala:857:36] wire [1:0] hfma_io_in_bits_req_fmaCmd; // @[FPU.scala:848:19] wire [1:0] hfma_io_in_bits_req_typ; // @[FPU.scala:848:19] wire [1:0] hfma_io_in_bits_req_fmt; // @[FPU.scala:848:19] wire [64:0] hfma_io_in_bits_req_in1; // @[FPU.scala:848:19] wire [64:0] hfma_io_in_bits_req_in2; // @[FPU.scala:848:19] wire [64:0] hfma_io_in_bits_req_in3; // @[FPU.scala:848:19] wire [1:0] hfma_io_in_bits_req_in1_prev_unswizzled_hi = {_hfma_io_in_bits_req_in1_prev_unswizzled_T, _hfma_io_in_bits_req_in1_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [32:0] hfma_io_in_bits_req_in1_prev_unswizzled = {hfma_io_in_bits_req_in1_prev_unswizzled_hi, _hfma_io_in_bits_req_in1_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire _hfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T = hfma_io_in_bits_req_in1_prev_unswizzled[15]; // @[FPU.scala:356:31, :357:14] wire _hfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_1 = hfma_io_in_bits_req_in1_prev_unswizzled[23]; // @[FPU.scala:356:31, :358:14] wire [14:0] _hfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_2 = hfma_io_in_bits_req_in1_prev_unswizzled[14:0]; // @[FPU.scala:356:31, :359:14] wire [1:0] hfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_hi = {_hfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T, _hfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [16:0] hfma_io_in_bits_req_in1_floats_0 = {hfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_hi, _hfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire [4:0] _hfma_io_in_bits_req_in1_prev_prev_prev_isbox_T = hfma_io_in_bits_req_in1_prev_unswizzled[32:28]; // @[FPU.scala:332:49, :356:31] wire hfma_io_in_bits_req_in1_prev_prev_prev_isbox = &_hfma_io_in_bits_req_in1_prev_prev_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire hfma_io_in_bits_req_in1_prev_prev_0_1 = hfma_io_in_bits_req_in1_prev_prev_prev_isbox; // @[FPU.scala:332:84, :362:32] wire hfma_io_in_bits_req_in1_prev_prev_sign = hfma_io_in_bits_req_in1_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31] wire [22:0] hfma_io_in_bits_req_in1_prev_prev_fractIn = hfma_io_in_bits_req_in1_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31] wire [8:0] hfma_io_in_bits_req_in1_prev_prev_expIn = hfma_io_in_bits_req_in1_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31] wire [33:0] _hfma_io_in_bits_req_in1_prev_prev_fractOut_T = {hfma_io_in_bits_req_in1_prev_prev_fractIn, 11'h0}; // @[FPU.scala:275:20, :277:28] wire [9:0] hfma_io_in_bits_req_in1_prev_prev_fractOut = _hfma_io_in_bits_req_in1_prev_prev_fractOut_T[33:24]; // @[FPU.scala:277:{28,38}] wire [2:0] hfma_io_in_bits_req_in1_prev_prev_expOut_expCode = hfma_io_in_bits_req_in1_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26] wire [9:0] _hfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T = {1'h0, hfma_io_in_bits_req_in1_prev_prev_expIn} + 10'h20; // @[FPU.scala:276:18, :280:31] wire [8:0] _hfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_1 = _hfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T[8:0]; // @[FPU.scala:280:31] wire [9:0] _hfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2 = {1'h0, _hfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_1} - 10'h100; // @[FPU.scala:280:{31,50}] wire [8:0] hfma_io_in_bits_req_in1_prev_prev_expOut_commonCase = _hfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2[8:0]; // @[FPU.scala:280:50] wire _hfma_io_in_bits_req_in1_prev_prev_expOut_T = hfma_io_in_bits_req_in1_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _hfma_io_in_bits_req_in1_prev_prev_expOut_T_1 = hfma_io_in_bits_req_in1_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _hfma_io_in_bits_req_in1_prev_prev_expOut_T_2 = _hfma_io_in_bits_req_in1_prev_prev_expOut_T \| _hfma_io_in_bits_req_in1_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [2:0] _hfma_io_in_bits_req_in1_prev_prev_expOut_T_3 = hfma_io_in_bits_req_in1_prev_prev_expOut_commonCase[2:0]; // @[FPU.scala:280:50, :281:69] wire [5:0] _hfma_io_in_bits_req_in1_prev_prev_expOut_T_4 = {hfma_io_in_bits_req_in1_prev_prev_expOut_expCode, _hfma_io_in_bits_req_in1_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [5:0] _hfma_io_in_bits_req_in1_prev_prev_expOut_T_5 = hfma_io_in_bits_req_in1_prev_prev_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:97] wire [5:0] hfma_io_in_bits_req_in1_prev_prev_expOut = _hfma_io_in_bits_req_in1_prev_prev_expOut_T_2 ? _hfma_io_in_bits_req_in1_prev_prev_expOut_T_4 : _hfma_io_in_bits_req_in1_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [6:0] hfma_io_in_bits_req_in1_prev_prev_hi = {hfma_io_in_bits_req_in1_prev_prev_sign, hfma_io_in_bits_req_in1_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [16:0] hfma_io_in_bits_req_in1_floats_1 = {hfma_io_in_bits_req_in1_prev_prev_hi, hfma_io_in_bits_req_in1_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire hfma_io_in_bits_req_in1_prev_isbox = &_hfma_io_in_bits_req_in1_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire hfma_io_in_bits_req_in1_oks_1 = hfma_io_in_bits_req_in1_prev_isbox; // @[FPU.scala:332:84, :362:32] wire hfma_io_in_bits_req_in1_oks_0 = hfma_io_in_bits_req_in1_prev_isbox & hfma_io_in_bits_req_in1_prev_prev_0_1; // @[FPU.scala:332:84, :362:32] wire [62:0] _hfma_io_in_bits_req_in1_fractOut_T = {hfma_io_in_bits_req_in1_fractIn, 11'h0}; // @[FPU.scala:275:20, :277:28] wire [9:0] hfma_io_in_bits_req_in1_fractOut = _hfma_io_in_bits_req_in1_fractOut_T[62:53]; // @[FPU.scala:277:{28,38}] wire [2:0] hfma_io_in_bits_req_in1_expOut_expCode = hfma_io_in_bits_req_in1_expIn[11:9]; // @[FPU.scala:276:18, :279:26] wire [12:0] _hfma_io_in_bits_req_in1_expOut_commonCase_T = {1'h0, hfma_io_in_bits_req_in1_expIn} + 13'h20; // @[FPU.scala:276:18, :280:31] wire [11:0] _hfma_io_in_bits_req_in1_expOut_commonCase_T_1 = _hfma_io_in_bits_req_in1_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _hfma_io_in_bits_req_in1_expOut_commonCase_T_2 = {1'h0, _hfma_io_in_bits_req_in1_expOut_commonCase_T_1} - 13'h800; // @[FPU.scala:280:{31,50}] wire [11:0] hfma_io_in_bits_req_in1_expOut_commonCase = _hfma_io_in_bits_req_in1_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire _hfma_io_in_bits_req_in1_expOut_T = hfma_io_in_bits_req_in1_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _hfma_io_in_bits_req_in1_expOut_T_1 = hfma_io_in_bits_req_in1_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _hfma_io_in_bits_req_in1_expOut_T_2 = _hfma_io_in_bits_req_in1_expOut_T \| _hfma_io_in_bits_req_in1_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [2:0] _hfma_io_in_bits_req_in1_expOut_T_3 = hfma_io_in_bits_req_in1_expOut_commonCase[2:0]; // @[FPU.scala:280:50, :281:69] wire [5:0] _hfma_io_in_bits_req_in1_expOut_T_4 = {hfma_io_in_bits_req_in1_expOut_expCode, _hfma_io_in_bits_req_in1_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [5:0] _hfma_io_in_bits_req_in1_expOut_T_5 = hfma_io_in_bits_req_in1_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:97] wire [5:0] hfma_io_in_bits_req_in1_expOut = _hfma_io_in_bits_req_in1_expOut_T_2 ? _hfma_io_in_bits_req_in1_expOut_T_4 : _hfma_io_in_bits_req_in1_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [6:0] hfma_io_in_bits_req_in1_hi = {hfma_io_in_bits_req_in1_sign, hfma_io_in_bits_req_in1_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [16:0] hfma_io_in_bits_req_in1_floats_2 = {hfma_io_in_bits_req_in1_hi, hfma_io_in_bits_req_in1_fractOut}; // @[FPU.scala:277:38, :283:8] wire [16:0] _hfma_io_in_bits_req_in1_T = hfma_io_in_bits_req_in1_oks_0 ? 17'h0 : 17'hE200; // @[FPU.scala:362:32, :372:31] wire [16:0] _hfma_io_in_bits_req_in1_T_1 = hfma_io_in_bits_req_in1_floats_0 \| _hfma_io_in_bits_req_in1_T; // @[FPU.scala:356:31, :372:{26,31}] assign hfma_io_in_bits_req_in1 = {48'h0, _hfma_io_in_bits_req_in1_T_1}; // @[FPU.scala:372:26, :848:19, :852:13] wire [1:0] hfma_io_in_bits_req_in2_prev_unswizzled_hi = {_hfma_io_in_bits_req_in2_prev_unswizzled_T, _hfma_io_in_bits_req_in2_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [32:0] hfma_io_in_bits_req_in2_prev_unswizzled = {hfma_io_in_bits_req_in2_prev_unswizzled_hi, _hfma_io_in_bits_req_in2_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire _hfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T = hfma_io_in_bits_req_in2_prev_unswizzled[15]; // @[FPU.scala:356:31, :357:14] wire _hfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_1 = hfma_io_in_bits_req_in2_prev_unswizzled[23]; // @[FPU.scala:356:31, :358:14] wire [14:0] _hfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_2 = hfma_io_in_bits_req_in2_prev_unswizzled[14:0]; // @[FPU.scala:356:31, :359:14] wire [1:0] hfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_hi = {_hfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T, _hfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [16:0] hfma_io_in_bits_req_in2_floats_0 = {hfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_hi, _hfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire [4:0] _hfma_io_in_bits_req_in2_prev_prev_prev_isbox_T = hfma_io_in_bits_req_in2_prev_unswizzled[32:28]; // @[FPU.scala:332:49, :356:31] wire hfma_io_in_bits_req_in2_prev_prev_prev_isbox = &_hfma_io_in_bits_req_in2_prev_prev_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire hfma_io_in_bits_req_in2_prev_prev_0_1 = hfma_io_in_bits_req_in2_prev_prev_prev_isbox; // @[FPU.scala:332:84, :362:32] wire hfma_io_in_bits_req_in2_prev_prev_sign = hfma_io_in_bits_req_in2_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31] wire [22:0] hfma_io_in_bits_req_in2_prev_prev_fractIn = hfma_io_in_bits_req_in2_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31] wire [8:0] hfma_io_in_bits_req_in2_prev_prev_expIn = hfma_io_in_bits_req_in2_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31] wire [33:0] _hfma_io_in_bits_req_in2_prev_prev_fractOut_T = {hfma_io_in_bits_req_in2_prev_prev_fractIn, 11'h0}; // @[FPU.scala:275:20, :277:28] wire [9:0] hfma_io_in_bits_req_in2_prev_prev_fractOut = _hfma_io_in_bits_req_in2_prev_prev_fractOut_T[33:24]; // @[FPU.scala:277:{28,38}] wire [2:0] hfma_io_in_bits_req_in2_prev_prev_expOut_expCode = hfma_io_in_bits_req_in2_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26] wire [9:0] _hfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T = {1'h0, hfma_io_in_bits_req_in2_prev_prev_expIn} + 10'h20; // @[FPU.scala:276:18, :280:31] wire [8:0] _hfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_1 = _hfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T[8:0]; // @[FPU.scala:280:31] wire [9:0] _hfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2 = {1'h0, _hfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_1} - 10'h100; // @[FPU.scala:280:{31,50}] wire [8:0] hfma_io_in_bits_req_in2_prev_prev_expOut_commonCase = _hfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2[8:0]; // @[FPU.scala:280:50] wire _hfma_io_in_bits_req_in2_prev_prev_expOut_T = hfma_io_in_bits_req_in2_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _hfma_io_in_bits_req_in2_prev_prev_expOut_T_1 = hfma_io_in_bits_req_in2_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _hfma_io_in_bits_req_in2_prev_prev_expOut_T_2 = _hfma_io_in_bits_req_in2_prev_prev_expOut_T \| _hfma_io_in_bits_req_in2_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [2:0] _hfma_io_in_bits_req_in2_prev_prev_expOut_T_3 = hfma_io_in_bits_req_in2_prev_prev_expOut_commonCase[2:0]; // @[FPU.scala:280:50, :281:69] wire [5:0] _hfma_io_in_bits_req_in2_prev_prev_expOut_T_4 = {hfma_io_in_bits_req_in2_prev_prev_expOut_expCode, _hfma_io_in_bits_req_in2_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [5:0] _hfma_io_in_bits_req_in2_prev_prev_expOut_T_5 = hfma_io_in_bits_req_in2_prev_prev_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:97] wire [5:0] hfma_io_in_bits_req_in2_prev_prev_expOut = _hfma_io_in_bits_req_in2_prev_prev_expOut_T_2 ? _hfma_io_in_bits_req_in2_prev_prev_expOut_T_4 : _hfma_io_in_bits_req_in2_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [6:0] hfma_io_in_bits_req_in2_prev_prev_hi = {hfma_io_in_bits_req_in2_prev_prev_sign, hfma_io_in_bits_req_in2_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [16:0] hfma_io_in_bits_req_in2_floats_1 = {hfma_io_in_bits_req_in2_prev_prev_hi, hfma_io_in_bits_req_in2_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire hfma_io_in_bits_req_in2_prev_isbox = &_hfma_io_in_bits_req_in2_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire hfma_io_in_bits_req_in2_oks_1 = hfma_io_in_bits_req_in2_prev_isbox; // @[FPU.scala:332:84, :362:32] wire hfma_io_in_bits_req_in2_oks_0 = hfma_io_in_bits_req_in2_prev_isbox & hfma_io_in_bits_req_in2_prev_prev_0_1; // @[FPU.scala:332:84, :362:32] wire [62:0] _hfma_io_in_bits_req_in2_fractOut_T = {hfma_io_in_bits_req_in2_fractIn, 11'h0}; // @[FPU.scala:275:20, :277:28] wire [9:0] hfma_io_in_bits_req_in2_fractOut = _hfma_io_in_bits_req_in2_fractOut_T[62:53]; // @[FPU.scala:277:{28,38}] wire [2:0] hfma_io_in_bits_req_in2_expOut_expCode = hfma_io_in_bits_req_in2_expIn[11:9]; // @[FPU.scala:276:18, :279:26] wire [12:0] _hfma_io_in_bits_req_in2_expOut_commonCase_T = {1'h0, hfma_io_in_bits_req_in2_expIn} + 13'h20; // @[FPU.scala:276:18, :280:31] wire [11:0] _hfma_io_in_bits_req_in2_expOut_commonCase_T_1 = _hfma_io_in_bits_req_in2_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _hfma_io_in_bits_req_in2_expOut_commonCase_T_2 = {1'h0, _hfma_io_in_bits_req_in2_expOut_commonCase_T_1} - 13'h800; // @[FPU.scala:280:{31,50}] wire [11:0] hfma_io_in_bits_req_in2_expOut_commonCase = _hfma_io_in_bits_req_in2_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire _hfma_io_in_bits_req_in2_expOut_T = hfma_io_in_bits_req_in2_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _hfma_io_in_bits_req_in2_expOut_T_1 = hfma_io_in_bits_req_in2_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _hfma_io_in_bits_req_in2_expOut_T_2 = _hfma_io_in_bits_req_in2_expOut_T \| _hfma_io_in_bits_req_in2_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [2:0] _hfma_io_in_bits_req_in2_expOut_T_3 = hfma_io_in_bits_req_in2_expOut_commonCase[2:0]; // @[FPU.scala:280:50, :281:69] wire [5:0] _hfma_io_in_bits_req_in2_expOut_T_4 = {hfma_io_in_bits_req_in2_expOut_expCode, _hfma_io_in_bits_req_in2_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [5:0] _hfma_io_in_bits_req_in2_expOut_T_5 = hfma_io_in_bits_req_in2_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:97] wire [5:0] hfma_io_in_bits_req_in2_expOut = _hfma_io_in_bits_req_in2_expOut_T_2 ? _hfma_io_in_bits_req_in2_expOut_T_4 : _hfma_io_in_bits_req_in2_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [6:0] hfma_io_in_bits_req_in2_hi = {hfma_io_in_bits_req_in2_sign, hfma_io_in_bits_req_in2_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [16:0] hfma_io_in_bits_req_in2_floats_2 = {hfma_io_in_bits_req_in2_hi, hfma_io_in_bits_req_in2_fractOut}; // @[FPU.scala:277:38, :283:8] wire [16:0] _hfma_io_in_bits_req_in2_T = hfma_io_in_bits_req_in2_oks_0 ? 17'h0 : 17'hE200; // @[FPU.scala:362:32, :372:31] wire [16:0] _hfma_io_in_bits_req_in2_T_1 = hfma_io_in_bits_req_in2_floats_0 \| _hfma_io_in_bits_req_in2_T; // @[FPU.scala:356:31, :372:{26,31}] assign hfma_io_in_bits_req_in2 = {48'h0, _hfma_io_in_bits_req_in2_T_1}; // @[FPU.scala:372:26, :848:19, :852:13, :853:13] wire [1:0] hfma_io_in_bits_req_in3_prev_unswizzled_hi = {_hfma_io_in_bits_req_in3_prev_unswizzled_T, _hfma_io_in_bits_req_in3_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [32:0] hfma_io_in_bits_req_in3_prev_unswizzled = {hfma_io_in_bits_req_in3_prev_unswizzled_hi, _hfma_io_in_bits_req_in3_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire _hfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T = hfma_io_in_bits_req_in3_prev_unswizzled[15]; // @[FPU.scala:356:31, :357:14] wire _hfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_1 = hfma_io_in_bits_req_in3_prev_unswizzled[23]; // @[FPU.scala:356:31, :358:14] wire [14:0] _hfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_2 = hfma_io_in_bits_req_in3_prev_unswizzled[14:0]; // @[FPU.scala:356:31, :359:14] wire [1:0] hfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_hi = {_hfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T, _hfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [16:0] hfma_io_in_bits_req_in3_floats_0 = {hfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_hi, _hfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire [4:0] _hfma_io_in_bits_req_in3_prev_prev_prev_isbox_T = hfma_io_in_bits_req_in3_prev_unswizzled[32:28]; // @[FPU.scala:332:49, :356:31] wire hfma_io_in_bits_req_in3_prev_prev_prev_isbox = &_hfma_io_in_bits_req_in3_prev_prev_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire hfma_io_in_bits_req_in3_prev_prev_0_1 = hfma_io_in_bits_req_in3_prev_prev_prev_isbox; // @[FPU.scala:332:84, :362:32] wire hfma_io_in_bits_req_in3_prev_prev_sign = hfma_io_in_bits_req_in3_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31] wire [22:0] hfma_io_in_bits_req_in3_prev_prev_fractIn = hfma_io_in_bits_req_in3_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31] wire [8:0] hfma_io_in_bits_req_in3_prev_prev_expIn = hfma_io_in_bits_req_in3_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31] wire [33:0] _hfma_io_in_bits_req_in3_prev_prev_fractOut_T = {hfma_io_in_bits_req_in3_prev_prev_fractIn, 11'h0}; // @[FPU.scala:275:20, :277:28] wire [9:0] hfma_io_in_bits_req_in3_prev_prev_fractOut = _hfma_io_in_bits_req_in3_prev_prev_fractOut_T[33:24]; // @[FPU.scala:277:{28,38}] wire [2:0] hfma_io_in_bits_req_in3_prev_prev_expOut_expCode = hfma_io_in_bits_req_in3_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26] wire [9:0] _hfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T = {1'h0, hfma_io_in_bits_req_in3_prev_prev_expIn} + 10'h20; // @[FPU.scala:276:18, :280:31] wire [8:0] _hfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_1 = _hfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T[8:0]; // @[FPU.scala:280:31] wire [9:0] _hfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_2 = {1'h0, _hfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_1} - 10'h100; // @[FPU.scala:280:{31,50}] wire [8:0] hfma_io_in_bits_req_in3_prev_prev_expOut_commonCase = _hfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_2[8:0]; // @[FPU.scala:280:50] wire _hfma_io_in_bits_req_in3_prev_prev_expOut_T = hfma_io_in_bits_req_in3_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _hfma_io_in_bits_req_in3_prev_prev_expOut_T_1 = hfma_io_in_bits_req_in3_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _hfma_io_in_bits_req_in3_prev_prev_expOut_T_2 = _hfma_io_in_bits_req_in3_prev_prev_expOut_T \| _hfma_io_in_bits_req_in3_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [2:0] _hfma_io_in_bits_req_in3_prev_prev_expOut_T_3 = hfma_io_in_bits_req_in3_prev_prev_expOut_commonCase[2:0]; // @[FPU.scala:280:50, :281:69] wire [5:0] _hfma_io_in_bits_req_in3_prev_prev_expOut_T_4 = {hfma_io_in_bits_req_in3_prev_prev_expOut_expCode, _hfma_io_in_bits_req_in3_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [5:0] _hfma_io_in_bits_req_in3_prev_prev_expOut_T_5 = hfma_io_in_bits_req_in3_prev_prev_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:97] wire [5:0] hfma_io_in_bits_req_in3_prev_prev_expOut = _hfma_io_in_bits_req_in3_prev_prev_expOut_T_2 ? _hfma_io_in_bits_req_in3_prev_prev_expOut_T_4 : _hfma_io_in_bits_req_in3_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [6:0] hfma_io_in_bits_req_in3_prev_prev_hi = {hfma_io_in_bits_req_in3_prev_prev_sign, hfma_io_in_bits_req_in3_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [16:0] hfma_io_in_bits_req_in3_floats_1 = {hfma_io_in_bits_req_in3_prev_prev_hi, hfma_io_in_bits_req_in3_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire hfma_io_in_bits_req_in3_prev_isbox = &_hfma_io_in_bits_req_in3_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire hfma_io_in_bits_req_in3_oks_1 = hfma_io_in_bits_req_in3_prev_isbox; // @[FPU.scala:332:84, :362:32] wire hfma_io_in_bits_req_in3_oks_0 = hfma_io_in_bits_req_in3_prev_isbox & hfma_io_in_bits_req_in3_prev_prev_0_1; // @[FPU.scala:332:84, :362:32] wire [62:0] _hfma_io_in_bits_req_in3_fractOut_T = {hfma_io_in_bits_req_in3_fractIn, 11'h0}; // @[FPU.scala:275:20, :277:28] wire [9:0] hfma_io_in_bits_req_in3_fractOut = _hfma_io_in_bits_req_in3_fractOut_T[62:53]; // @[FPU.scala:277:{28,38}] wire [2:0] hfma_io_in_bits_req_in3_expOut_expCode = hfma_io_in_bits_req_in3_expIn[11:9]; // @[FPU.scala:276:18, :279:26] wire [12:0] _hfma_io_in_bits_req_in3_expOut_commonCase_T = {1'h0, hfma_io_in_bits_req_in3_expIn} + 13'h20; // @[FPU.scala:276:18, :280:31] wire [11:0] _hfma_io_in_bits_req_in3_expOut_commonCase_T_1 = _hfma_io_in_bits_req_in3_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _hfma_io_in_bits_req_in3_expOut_commonCase_T_2 = {1'h0, _hfma_io_in_bits_req_in3_expOut_commonCase_T_1} - 13'h800; // @[FPU.scala:280:{31,50}] wire [11:0] hfma_io_in_bits_req_in3_expOut_commonCase = _hfma_io_in_bits_req_in3_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire _hfma_io_in_bits_req_in3_expOut_T = hfma_io_in_bits_req_in3_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _hfma_io_in_bits_req_in3_expOut_T_1 = hfma_io_in_bits_req_in3_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _hfma_io_in_bits_req_in3_expOut_T_2 = _hfma_io_in_bits_req_in3_expOut_T \| _hfma_io_in_bits_req_in3_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [2:0] _hfma_io_in_bits_req_in3_expOut_T_3 = hfma_io_in_bits_req_in3_expOut_commonCase[2:0]; // @[FPU.scala:280:50, :281:69] wire [5:0] _hfma_io_in_bits_req_in3_expOut_T_4 = {hfma_io_in_bits_req_in3_expOut_expCode, _hfma_io_in_bits_req_in3_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [5:0] _hfma_io_in_bits_req_in3_expOut_T_5 = hfma_io_in_bits_req_in3_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:97] wire [5:0] hfma_io_in_bits_req_in3_expOut = _hfma_io_in_bits_req_in3_expOut_T_2 ? _hfma_io_in_bits_req_in3_expOut_T_4 : _hfma_io_in_bits_req_in3_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [6:0] hfma_io_in_bits_req_in3_hi = {hfma_io_in_bits_req_in3_sign, hfma_io_in_bits_req_in3_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [16:0] hfma_io_in_bits_req_in3_floats_2 = {hfma_io_in_bits_req_in3_hi, hfma_io_in_bits_req_in3_fractOut}; // @[FPU.scala:277:38, :283:8] wire [16:0] _hfma_io_in_bits_req_in3_T = hfma_io_in_bits_req_in3_oks_0 ? 17'h0 : 17'hE200; // @[FPU.scala:362:32, :372:31] wire [16:0] _hfma_io_in_bits_req_in3_T_1 = hfma_io_in_bits_req_in3_floats_0 \| _hfma_io_in_bits_req_in3_T; // @[FPU.scala:356:31, :372:{26,31}] assign hfma_io_in_bits_req_in3 = {48'h0, _hfma_io_in_bits_req_in3_T_1}; // @[FPU.scala:372:26, :848:19, :852:13, :854:13] assign hfma_io_in_bits_req_typ = _hfma_io_in_bits_req_typ_T; // @[FPU.scala:848:19, :855:27] assign hfma_io_in_bits_req_fmt = _hfma_io_in_bits_req_fmt_T; // @[FPU.scala:848:19, :856:27] wire _hfma_io_in_bits_req_fmaCmd_T_1 = ~ex_ctrl_ren3; // @[FPU.scala:800:20, :857:39] wire _hfma_io_in_bits_req_fmaCmd_T_3 = _hfma_io_in_bits_req_fmaCmd_T_1 & _hfma_io_in_bits_req_fmaCmd_T_2; // @[FPU.scala:857:{39,53,67}] assign _hfma_io_in_bits_req_fmaCmd_T_4 = {_hfma_io_in_bits_req_fmaCmd_T[1], _hfma_io_in_bits_req_fmaCmd_T[0] \| _hfma_io_in_bits_req_fmaCmd_T_3}; // @[FPU.scala:857:{30,36,53}] assign hfma_io_in_bits_req_fmaCmd = _hfma_io_in_bits_req_fmaCmd_T_4; // @[FPU.scala:848:19, :857:36] wire _GEN_6 = mem_ctrl_typeTagOut == 2'h1; // @[FPU.scala:801:27, :911:72] wire _memLatencyMask_T_2; // @[FPU.scala:911:72] assign _memLatencyMask_T_2 = _GEN_6; // @[FPU.scala:911:72] wire _wbInfo_0_pipeid_T_2; // @[FPU.scala:911:72] assign _wbInfo_0_pipeid_T_2 = _GEN_6; // @[FPU.scala:911:72] wire _wbInfo_1_pipeid_T_2; // @[FPU.scala:911:72] assign _wbInfo_1_pipeid_T_2 = _GEN_6; // @[FPU.scala:911:72] wire _wbInfo_2_pipeid_T_2; // @[FPU.scala:911:72] assign _wbInfo_2_pipeid_T_2 = _GEN_6; // @[FPU.scala:911:72] wire _divSqrt_io_inValid_T_2; // @[FPU.scala:1028:52] assign _divSqrt_io_inValid_T_2 = _GEN_6; // @[FPU.scala:911:72, :1028:52] wire _memLatencyMask_T_3 = mem_ctrl_fma & _memLatencyMask_T_2; // @[FPU.scala:801:27, :911:{56,72}] wire [1:0] _memLatencyMask_T_4 = {_memLatencyMask_T_3, 1'h0}; // @[FPU.scala:911:56, :926:23] wire _GEN_7 = mem_ctrl_typeTagOut == 2'h2; // @[FPU.scala:801:27, :916:78] wire _memLatencyMask_T_5; // @[FPU.scala:916:78] assign _memLatencyMask_T_5 = _GEN_7; // @[FPU.scala:916:78] wire _wbInfo_0_pipeid_T_5; // @[FPU.scala:916:78] assign _wbInfo_0_pipeid_T_5 = _GEN_7; // @[FPU.scala:916:78] wire _wbInfo_1_pipeid_T_5; // @[FPU.scala:916:78] assign _wbInfo_1_pipeid_T_5 = _GEN_7; // @[FPU.scala:916:78] wire _wbInfo_2_pipeid_T_5; // @[FPU.scala:916:78] assign _wbInfo_2_pipeid_T_5 = _GEN_7; // @[FPU.scala:916:78] wire _io_sboard_set_T_2; // @[FPU.scala:916:78] assign _io_sboard_set_T_2 = _GEN_7; // @[FPU.scala:916:78] wire _divSqrt_io_inValid_T_4; // @[FPU.scala:1028:52] assign _divSqrt_io_inValid_T_4 = _GEN_7; // @[FPU.scala:916:78, :1028:52] wire _memLatencyMask_T_6 = mem_ctrl_fma & _memLatencyMask_T_5; // @[FPU.scala:801:27, :916:{62,78}] wire [2:0] _memLatencyMask_T_7 = {_memLatencyMask_T_6, 2'h0}; // @[FPU.scala:916:62, :926:23] wire _GEN_8 = mem_ctrl_typeTagOut == 2'h0; // @[FPU.scala:801:27, :922:78] wire _memLatencyMask_T_8; // @[FPU.scala:922:78] assign _memLatencyMask_T_8 = _GEN_8; // @[FPU.scala:922:78] wire _wbInfo_0_pipeid_T_8; // @[FPU.scala:922:78] assign _wbInfo_0_pipeid_T_8 = _GEN_8; // @[FPU.scala:922:78] wire _wbInfo_1_pipeid_T_8; // @[FPU.scala:922:78] assign _wbInfo_1_pipeid_T_8 = _GEN_8; // @[FPU.scala:922:78] wire _wbInfo_2_pipeid_T_8; // @[FPU.scala:922:78] assign _wbInfo_2_pipeid_T_8 = _GEN_8; // @[FPU.scala:922:78] wire _divSqrt_io_inValid_T; // @[FPU.scala:1028:52] assign _divSqrt_io_inValid_T = _GEN_8; // @[FPU.scala:922:78, :1028:52] wire _memLatencyMask_T_9 = mem_ctrl_fma & _memLatencyMask_T_8; // @[FPU.scala:801:27, :922:{62,78}] wire [1:0] _memLatencyMask_T_10 = {_memLatencyMask_T_9, 1'h0}; // @[FPU.scala:922:62, :926:23] wire _memLatencyMask_T_11 = _memLatencyMask_T \| _memLatencyMask_T_1; // @[FPU.scala:926:{23,72}] wire [1:0] _memLatencyMask_T_12 = {1'h0, _memLatencyMask_T_11} \| _memLatencyMask_T_4; // @[FPU.scala:926:{23,72}] wire [2:0] _memLatencyMask_T_13 = {1'h0, _memLatencyMask_T_12} \| _memLatencyMask_T_7; // @[FPU.scala:926:{23,72}] wire [2:0] memLatencyMask = {_memLatencyMask_T_13[2], _memLatencyMask_T_13[1:0] \| _memLatencyMask_T_10}; // @[FPU.scala:926:{23,72}] reg [2:0] wen; // @[FPU.scala:939:20] reg [4:0] wbInfo_0_rd; // @[FPU.scala:940:19] reg [1:0] wbInfo_0_typeTag; // @[FPU.scala:940:19] reg wbInfo_0_cp; // @[FPU.scala:940:19] reg [2:0] wbInfo_0_pipeid; // @[FPU.scala:940:19] reg [4:0] wbInfo_1_rd; // @[FPU.scala:940:19] reg [1:0] wbInfo_1_typeTag; // @[FPU.scala:940:19] reg wbInfo_1_cp; // @[FPU.scala:940:19] reg [2:0] wbInfo_1_pipeid; // @[FPU.scala:940:19] reg [4:0] wbInfo_2_rd; // @[FPU.scala:940:19] reg [1:0] wbInfo_2_typeTag; // @[FPU.scala:940:19] reg wbInfo_2_cp; // @[FPU.scala:940:19] reg [2:0] wbInfo_2_pipeid; // @[FPU.scala:940:19] wire _mem_wen_T = mem_ctrl_fma \| mem_ctrl_fastpipe; // @[FPU.scala:801:27, :941:48] wire _mem_wen_T_1 = _mem_wen_T \| mem_ctrl_fromint; // @[FPU.scala:801:27, :941:{48,69}] wire mem_wen = mem_reg_valid & _mem_wen_T_1; // @[FPU.scala:784:30, :941:{31,69}] wire [1:0] _write_port_busy_T = {ex_ctrl_fastpipe, 1'h0}; // @[FPU.scala:800:20, :926:23] wire [1:0] _write_port_busy_T_1 = {ex_ctrl_fromint, 1'h0}; // @[FPU.scala:800:20, :926:23] wire _write_port_busy_T_3 = ex_ctrl_fma & _write_port_busy_T_2; // @[FPU.scala:800:20, :911:{56,72}] wire [2:0] _write_port_busy_T_4 = {_write_port_busy_T_3, 2'h0}; // @[FPU.scala:911:56, :926:23] wire _write_port_busy_T_6 = ex_ctrl_fma & _write_port_busy_T_5; // @[FPU.scala:800:20, :916:{62,78}] wire [3:0] _write_port_busy_T_7 = {_write_port_busy_T_6, 3'h0}; // @[FPU.scala:916:62, :926:23] wire _write_port_busy_T_9 = ex_ctrl_fma & _write_port_busy_T_8; // @[FPU.scala:800:20, :922:{62,78}] wire [2:0] _write_port_busy_T_10 = {_write_port_busy_T_9, 2'h0}; // @[FPU.scala:922:62, :926:23] wire [1:0] _write_port_busy_T_11 = _write_port_busy_T \| _write_port_busy_T_1; // @[FPU.scala:926:{23,72}] wire [2:0] _write_port_busy_T_12 = {1'h0, _write_port_busy_T_11} \| _write_port_busy_T_4; // @[FPU.scala:926:{23,72}] wire [3:0] _write_port_busy_T_13 = {1'h0, _write_port_busy_T_12} \| _write_port_busy_T_7; // @[FPU.scala:926:{23,72}] wire [3:0] _write_port_busy_T_14 = {_write_port_busy_T_13[3], _write_port_busy_T_13[2:0] \| _write_port_busy_T_10}; // @[FPU.scala:926:{23,72}] wire [3:0] _write_port_busy_T_15 = {1'h0, _write_port_busy_T_14[2:0] & memLatencyMask}; // @[FPU.scala:926:72, :942:62] wire _write_port_busy_T_16 = \|_write_port_busy_T_15; // @[FPU.scala:942:{62,89}] wire _write_port_busy_T_17 = mem_wen & _write_port_busy_T_16; // @[FPU.scala:941:31, :942:{43,89}] wire [2:0] _write_port_busy_T_18 = {ex_ctrl_fastpipe, 2'h0}; // @[FPU.scala:800:20, :926:23] wire [2:0] _write_port_busy_T_19 = {ex_ctrl_fromint, 2'h0}; // @[FPU.scala:800:20, :926:23] wire _write_port_busy_T_21 = ex_ctrl_fma & _write_port_busy_T_20; // @[FPU.scala:800:20, :911:{56,72}] wire [3:0] _write_port_busy_T_22 = {_write_port_busy_T_21, 3'h0}; // @[FPU.scala:911:56, :926:23] wire _write_port_busy_T_24 = ex_ctrl_fma & _write_port_busy_T_23; // @[FPU.scala:800:20, :916:{62,78}] wire [4:0] _write_port_busy_T_25 = {_write_port_busy_T_24, 4'h0}; // @[FPU.scala:916:62, :926:23] wire _write_port_busy_T_27 = ex_ctrl_fma & _write_port_busy_T_26; // @[FPU.scala:800:20, :922:{62,78}] wire [3:0] _write_port_busy_T_28 = {_write_port_busy_T_27, 3'h0}; // @[FPU.scala:922:62, :926:23] wire [2:0] _write_port_busy_T_29 = _write_port_busy_T_18 \| _write_port_busy_T_19; // @[FPU.scala:926:{23,72}] wire [3:0] _write_port_busy_T_30 = {1'h0, _write_port_busy_T_29} \| _write_port_busy_T_22; // @[FPU.scala:926:{23,72}] wire [4:0] _write_port_busy_T_31 = {1'h0, _write_port_busy_T_30} \| _write_port_busy_T_25; // @[FPU.scala:926:{23,72}] wire [4:0] _write_port_busy_T_32 = {_write_port_busy_T_31[4], _write_port_busy_T_31[3:0] \| _write_port_busy_T_28}; // @[FPU.scala:926:{23,72}] wire [4:0] _write_port_busy_T_33 = {2'h0, _write_port_busy_T_32[2:0] & wen}; // @[FPU.scala:926:72, :939:20, :942:101] wire _write_port_busy_T_34 = \|_write_port_busy_T_33; // @[FPU.scala:942:{101,128}] wire _write_port_busy_T_35 = _write_port_busy_T_17 \| _write_port_busy_T_34; // @[FPU.scala:942:{43,93,128}] reg write_port_busy; // @[FPU.scala:942:34] wire [1:0] _wen_T = wen[2:1]; // @[FPU.scala:939:20, :948:14] wire [1:0] _wen_T_1 = wen[2:1]; // @[FPU.scala:939:20, :948:14, :951:18] wire [2:0] _wen_T_2 = {1'h0, _wen_T_1} \| memLatencyMask; // @[FPU.scala:926:72, :951:{18,23}] wire _wbInfo_0_pipeid_T_11 = _wbInfo_0_pipeid_T_1; // @[FPU.scala:928:{63,100}] wire _wbInfo_0_pipeid_T_3 = mem_ctrl_fma & _wbInfo_0_pipeid_T_2; // @[FPU.scala:801:27, :911:{56,72}] wire [1:0] _wbInfo_0_pipeid_T_4 = {_wbInfo_0_pipeid_T_3, 1'h0}; // @[FPU.scala:911:56, :928:63] wire _wbInfo_0_pipeid_T_6 = mem_ctrl_fma & _wbInfo_0_pipeid_T_5; // @[FPU.scala:801:27, :916:{62,78}] wire [1:0] _wbInfo_0_pipeid_T_7 = {2{_wbInfo_0_pipeid_T_6}}; // @[FPU.scala:916:62, :928:63] wire _wbInfo_0_pipeid_T_9 = mem_ctrl_fma & _wbInfo_0_pipeid_T_8; // @[FPU.scala:801:27, :922:{62,78}] wire [2:0] _wbInfo_0_pipeid_T_10 = {_wbInfo_0_pipeid_T_9, 2'h0}; // @[FPU.scala:922:62, :928:63] wire [1:0] _wbInfo_0_pipeid_T_12 = {1'h0, _wbInfo_0_pipeid_T_11} \| _wbInfo_0_pipeid_T_4; // @[FPU.scala:928:{63,100}] wire [1:0] _wbInfo_0_pipeid_T_13 = _wbInfo_0_pipeid_T_12 \| _wbInfo_0_pipeid_T_7; // @[FPU.scala:928:{63,100}] wire [2:0] _wbInfo_0_pipeid_T_14 = {1'h0, _wbInfo_0_pipeid_T_13} \| _wbInfo_0_pipeid_T_10; // @[FPU.scala:928:{63,100}] wire [4:0] _wbInfo_0_rd_T = mem_reg_inst[11:7]; // @[FPU.scala:791:31, :958:37] wire [4:0] _wbInfo_1_rd_T = mem_reg_inst[11:7]; // @[FPU.scala:791:31, :958:37] wire [4:0] _wbInfo_2_rd_T = mem_reg_inst[11:7]; // @[FPU.scala:791:31, :958:37] wire [4:0] _divSqrt_waddr_T = mem_reg_inst[11:7]; // @[FPU.scala:791:31, :958:37, :1017:36] wire _wbInfo_1_pipeid_T_11 = _wbInfo_1_pipeid_T_1; // @[FPU.scala:928:{63,100}] wire _wbInfo_1_pipeid_T_3 = mem_ctrl_fma & _wbInfo_1_pipeid_T_2; // @[FPU.scala:801:27, :911:{56,72}] wire [1:0] _wbInfo_1_pipeid_T_4 = {_wbInfo_1_pipeid_T_3, 1'h0}; // @[FPU.scala:911:56, :928:63] wire _wbInfo_1_pipeid_T_6 = mem_ctrl_fma & _wbInfo_1_pipeid_T_5; // @[FPU.scala:801:27, :916:{62,78}] wire [1:0] _wbInfo_1_pipeid_T_7 = {2{_wbInfo_1_pipeid_T_6}}; // @[FPU.scala:916:62, :928:63] wire _wbInfo_1_pipeid_T_9 = mem_ctrl_fma & _wbInfo_1_pipeid_T_8; // @[FPU.scala:801:27, :922:{62,78}] wire [2:0] _wbInfo_1_pipeid_T_10 = {_wbInfo_1_pipeid_T_9, 2'h0}; // @[FPU.scala:922:62, :928:63] wire [1:0] _wbInfo_1_pipeid_T_12 = {1'h0, _wbInfo_1_pipeid_T_11} \| _wbInfo_1_pipeid_T_4; // @[FPU.scala:928:{63,100}] wire [1:0] _wbInfo_1_pipeid_T_13 = _wbInfo_1_pipeid_T_12 \| _wbInfo_1_pipeid_T_7; // @[FPU.scala:928:{63,100}] wire [2:0] _wbInfo_1_pipeid_T_14 = {1'h0, _wbInfo_1_pipeid_T_13} \| _wbInfo_1_pipeid_T_10; // @[FPU.scala:928:{63,100}] wire _wbInfo_2_pipeid_T_11 = _wbInfo_2_pipeid_T_1; // @[FPU.scala:928:{63,100}] wire _wbInfo_2_pipeid_T_3 = mem_ctrl_fma & _wbInfo_2_pipeid_T_2; // @[FPU.scala:801:27, :911:{56,72}] wire [1:0] _wbInfo_2_pipeid_T_4 = {_wbInfo_2_pipeid_T_3, 1'h0}; // @[FPU.scala:911:56, :928:63] wire _wbInfo_2_pipeid_T_6 = mem_ctrl_fma & _wbInfo_2_pipeid_T_5; // @[FPU.scala:801:27, :916:{62,78}] wire [1:0] _wbInfo_2_pipeid_T_7 = {2{_wbInfo_2_pipeid_T_6}}; // @[FPU.scala:916:62, :928:63] wire _wbInfo_2_pipeid_T_9 = mem_ctrl_fma & _wbInfo_2_pipeid_T_8; // @[FPU.scala:801:27, :922:{62,78}] wire [2:0] _wbInfo_2_pipeid_T_10 = {_wbInfo_2_pipeid_T_9, 2'h0}; // @[FPU.scala:922:62, :928:63] wire [1:0] _wbInfo_2_pipeid_T_12 = {1'h0, _wbInfo_2_pipeid_T_11} \| _wbInfo_2_pipeid_T_4; // @[FPU.scala:928:{63,100}] wire [1:0] _wbInfo_2_pipeid_T_13 = _wbInfo_2_pipeid_T_12 \| _wbInfo_2_pipeid_T_7; // @[FPU.scala:928:{63,100}] wire [2:0] _wbInfo_2_pipeid_T_14 = {1'h0, _wbInfo_2_pipeid_T_13} \| _wbInfo_2_pipeid_T_10; // @[FPU.scala:928:{63,100}] assign waddr = divSqrt_wen ? divSqrt_waddr : wbInfo_0_rd; // @[FPU.scala:896:32, :898:26, :940:19, :963:18] assign io_sboard_clra_0 = waddr; // @[FPU.scala:735:7, :963:18] assign frfWriteBundle_1_wrdst = waddr; // @[FPU.scala:805:44, :963:18] wire wb_cp = divSqrt_wen ? divSqrt_cp : wbInfo_0_cp; // @[FPU.scala:896:32, :899:23, :940:19, :964:18] wire [1:0] wtypeTag = divSqrt_wen ? divSqrt_typeTag : wbInfo_0_typeTag; // @[FPU.scala:896:32, :900:29, :940:19, :965:21] wire _GEN_9 = wbInfo_0_pipeid == 3'h1; // @[package.scala:39:86] wire _wdata_T_39; // @[package.scala:39:86] assign _wdata_T_39 = _GEN_9; // @[package.scala:39:86] wire _wexc_T; // @[package.scala:39:86] assign _wexc_T = _GEN_9; // @[package.scala:39:86] wire [64:0] _wdata_T_40 = _wdata_T_39 ? _ifpu_io_out_bits_data : _fpmu_io_out_bits_data; // @[package.scala:39:{76,86}] wire _GEN_10 = wbInfo_0_pipeid == 3'h2; // @[package.scala:39:86] wire _wdata_T_41; // @[package.scala:39:86] assign _wdata_T_41 = _GEN_10; // @[package.scala:39:86] wire _wexc_T_2; // @[package.scala:39:86] assign _wexc_T_2 = _GEN_10; // @[package.scala:39:86] wire [64:0] _wdata_T_42 = _wdata_T_41 ? _sfma_io_out_bits_data : _wdata_T_40; // @[package.scala:39:{76,86}] wire _GEN_11 = wbInfo_0_pipeid == 3'h3; // @[package.scala:39:86] wire _wdata_T_43; // @[package.scala:39:86] assign _wdata_T_43 = _GEN_11; // @[package.scala:39:86] wire _wexc_T_4; // @[package.scala:39:86] assign _wexc_T_4 = _GEN_11; // @[package.scala:39:86] wire _io_sboard_clr_T_2; // @[FPU.scala:1007:99] assign _io_sboard_clr_T_2 = _GEN_11; // @[package.scala:39:86] wire [64:0] _wdata_T_44 = _wdata_T_43 ? _dfma_io_out_bits_data : _wdata_T_42; // @[package.scala:39:{76,86}] wire _GEN_12 = wbInfo_0_pipeid == 3'h4; // @[package.scala:39:86] wire _wdata_T_45; // @[package.scala:39:86] assign _wdata_T_45 = _GEN_12; // @[package.scala:39:86] wire _wexc_T_6; // @[package.scala:39:86] assign _wexc_T_6 = _GEN_12; // @[package.scala:39:86] wire [64:0] _wdata_T_46 = _wdata_T_45 ? _hfma_io_out_bits_data : _wdata_T_44; // @[package.scala:39:{76,86}] wire _GEN_13 = wbInfo_0_pipeid == 3'h5; // @[package.scala:39:86] wire _wdata_T_47; // @[package.scala:39:86] assign _wdata_T_47 = _GEN_13; // @[package.scala:39:86] wire _wexc_T_8; // @[package.scala:39:86] assign _wexc_T_8 = _GEN_13; // @[package.scala:39:86] wire [64:0] _wdata_T_48 = _wdata_T_47 ? _hfma_io_out_bits_data : _wdata_T_46; // @[package.scala:39:{76,86}] wire _GEN_14 = wbInfo_0_pipeid == 3'h6; // @[package.scala:39:86] wire _wdata_T_49; // @[package.scala:39:86] assign _wdata_T_49 = _GEN_14; // @[package.scala:39:86] wire _wexc_T_10; // @[package.scala:39:86] assign _wexc_T_10 = _GEN_14; // @[package.scala:39:86] wire [64:0] _wdata_T_50 = _wdata_T_49 ? _hfma_io_out_bits_data : _wdata_T_48; // @[package.scala:39:{76,86}] wire _wdata_T_51 = &wbInfo_0_pipeid; // @[package.scala:39:86] wire [64:0] _wdata_T_52 = _wdata_T_51 ? _hfma_io_out_bits_data : _wdata_T_50; // @[package.scala:39:{76,86}] wire [64:0] _wdata_T_53 = divSqrt_wen ? divSqrt_wdata : _wdata_T_52; // @[package.scala:39:76] wire _wdata_opts_bigger_swizzledNaN_T_1 = _wdata_T_53[15]; // @[FPU.scala:340:8, :966:22] wire _wdata_opts_bigger_swizzledNaN_T_2 = _wdata_T_53[16]; // @[FPU.scala:342:8, :966:22] wire [14:0] _wdata_opts_bigger_swizzledNaN_T_3 = _wdata_T_53[14:0]; // @[FPU.scala:343:8, :966:22] wire [7:0] wdata_opts_bigger_swizzledNaN_lo_hi = {7'h7F, _wdata_opts_bigger_swizzledNaN_T_2}; // @[FPU.scala:336:26, :342:8] wire [22:0] wdata_opts_bigger_swizzledNaN_lo = {wdata_opts_bigger_swizzledNaN_lo_hi, _wdata_opts_bigger_swizzledNaN_T_3}; // @[FPU.scala:336:26, :343:8] wire [4:0] wdata_opts_bigger_swizzledNaN_hi_lo = {4'hF, _wdata_opts_bigger_swizzledNaN_T_1}; // @[FPU.scala:336:26, :340:8] wire [9:0] wdata_opts_bigger_swizzledNaN_hi = {5'h1F, wdata_opts_bigger_swizzledNaN_hi_lo}; // @[FPU.scala:336:26] wire [32:0] wdata_opts_bigger_swizzledNaN = {wdata_opts_bigger_swizzledNaN_hi, wdata_opts_bigger_swizzledNaN_lo}; // @[FPU.scala:336:26] wire [32:0] wdata_opts_bigger = wdata_opts_bigger_swizzledNaN; // @[FPU.scala:336:26, :344:8] wire [64:0] wdata_opts_0 = {32'hFFFFFFFF, wdata_opts_bigger}; // @[FPU.scala:344:8, :398:14] wire _wdata_opts_bigger_swizzledNaN_T_5 = _wdata_T_53[31]; // @[FPU.scala:340:8, :966:22] wire _wdata_opts_bigger_swizzledNaN_T_6 = _wdata_T_53[32]; // @[FPU.scala:342:8, :966:22] wire [30:0] _wdata_opts_bigger_swizzledNaN_T_7 = _wdata_T_53[30:0]; // @[FPU.scala:343:8, :966:22] wire [20:0] wdata_opts_bigger_swizzledNaN_lo_hi_1 = {20'hFFFFF, _wdata_opts_bigger_swizzledNaN_T_6}; // @[FPU.scala:336:26, :342:8] wire [51:0] wdata_opts_bigger_swizzledNaN_lo_1 = {wdata_opts_bigger_swizzledNaN_lo_hi_1, _wdata_opts_bigger_swizzledNaN_T_7}; // @[FPU.scala:336:26, :343:8] wire [7:0] wdata_opts_bigger_swizzledNaN_hi_lo_1 = {7'h7F, _wdata_opts_bigger_swizzledNaN_T_5}; // @[FPU.scala:336:26, :340:8] wire [12:0] wdata_opts_bigger_swizzledNaN_hi_1 = {5'h1F, wdata_opts_bigger_swizzledNaN_hi_lo_1}; // @[FPU.scala:336:26] wire [64:0] wdata_opts_bigger_swizzledNaN_1 = {wdata_opts_bigger_swizzledNaN_hi_1, wdata_opts_bigger_swizzledNaN_lo_1}; // @[FPU.scala:336:26] wire [64:0] wdata_opts_bigger_1 = wdata_opts_bigger_swizzledNaN_1; // @[FPU.scala:336:26, :344:8] wire [64:0] wdata_opts_1 = wdata_opts_bigger_1; // @[FPU.scala:344:8, :398:14] wire _wdata_T_54 = wtypeTag == 2'h1; // @[package.scala:39:86] wire [64:0] _wdata_T_55 = _wdata_T_54 ? wdata_opts_1 : wdata_opts_0; // @[package.scala:39:{76,86}] wire _wdata_T_56 = wtypeTag == 2'h2; // @[package.scala:39:86] wire [64:0] _wdata_T_57 = _wdata_T_56 ? _wdata_T_53 : _wdata_T_55; // @[package.scala:39:{76,86}] wire _wdata_T_58 = &wtypeTag; // @[package.scala:39:86] wire [64:0] wdata_1 = _wdata_T_58 ? _wdata_T_53 : _wdata_T_57; // @[package.scala:39:{76,86}] wire [4:0] _wexc_T_1 = _wexc_T ? _ifpu_io_out_bits_exc : _fpmu_io_out_bits_exc; // @[package.scala:39:{76,86}] wire [4:0] _wexc_T_3 = _wexc_T_2 ? _sfma_io_out_bits_exc : _wexc_T_1; // @[package.scala:39:{76,86}] wire [4:0] _wexc_T_5 = _wexc_T_4 ? _dfma_io_out_bits_exc : _wexc_T_3; // @[package.scala:39:{76,86}] wire [4:0] _wexc_T_7 = _wexc_T_6 ? _hfma_io_out_bits_exc : _wexc_T_5; // @[package.scala:39:{76,86}] wire [4:0] _wexc_T_9 = _wexc_T_8 ? _hfma_io_out_bits_exc : _wexc_T_7; // @[package.scala:39:{76,86}] wire [4:0] _wexc_T_11 = _wexc_T_10 ? _hfma_io_out_bits_exc : _wexc_T_9; // @[package.scala:39:{76,86}] wire _wexc_T_12 = &wbInfo_0_pipeid; // @[package.scala:39:86] wire [4:0] wexc = _wexc_T_12 ? _hfma_io_out_bits_exc : _wexc_T_11; // @[package.scala:39:{76,86}] wire _io_fcsr_flags_valid_T_1 = wen[0]; // @[FPU.scala:939:20, :968:30, :995:62] wire _io_fcsr_flags_bits_T_3 = wen[0]; // @[FPU.scala:939:20, :968:30, :999:12] wire _io_sboard_clr_T_1 = wen[0]; // @[FPU.scala:939:20, :968:30, :1007:56] assign frfWriteBundle_1_wrenf = ~wbInfo_0_cp & wen[0] \| divSqrt_wen; // @[FPU.scala:805:44, :896:32, :939:20, :940:19, :968:{10,24,30,35}] wire _unswizzled_T_3 = wdata_1[31]; // @[package.scala:39:76] wire _frfWriteBundle_1_wrdata_prevRecoded_T = wdata_1[31]; // @[package.scala:39:76] wire _unswizzled_T_4 = wdata_1[52]; // @[package.scala:39:76] wire _frfWriteBundle_1_wrdata_prevRecoded_T_1 = wdata_1[52]; // @[package.scala:39:76] wire [30:0] _unswizzled_T_5 = wdata_1[30:0]; // @[package.scala:39:76] wire [30:0] _frfWriteBundle_1_wrdata_prevRecoded_T_2 = wdata_1[30:0]; // @[package.scala:39:76] wire [1:0] unswizzled_hi_1 = {_unswizzled_T_3, _unswizzled_T_4}; // @[FPU.scala:380:27, :381:10, :382:10] wire [32:0] unswizzled_1 = {unswizzled_hi_1, _unswizzled_T_5}; // @[FPU.scala:380:27, :383:10] wire [4:0] _prevOK_T_4 = wdata_1[64:60]; // @[package.scala:39:76] wire _prevOK_T_5 = &_prevOK_T_4; // @[FPU.scala:332:{49,84}] wire _prevOK_T_6 = ~_prevOK_T_5; // @[FPU.scala:332:84, :384:20] wire _prevOK_unswizzled_T_3 = unswizzled_1[15]; // @[FPU.scala:380:27, :381:10] wire _prevOK_unswizzled_T_4 = unswizzled_1[23]; // @[FPU.scala:380:27, :382:10] wire [14:0] _prevOK_unswizzled_T_5 = unswizzled_1[14:0]; // @[FPU.scala:380:27, :383:10] wire [1:0] prevOK_unswizzled_hi_1 = {_prevOK_unswizzled_T_3, _prevOK_unswizzled_T_4}; // @[FPU.scala:380:27, :381:10, :382:10] wire [16:0] prevOK_unswizzled_1 = {prevOK_unswizzled_hi_1, _prevOK_unswizzled_T_5}; // @[FPU.scala:380:27, :383:10] wire [4:0] _prevOK_prevOK_T_3 = unswizzled_1[32:28]; // @[FPU.scala:332:49, :380:27] wire _prevOK_prevOK_T_4 = &_prevOK_prevOK_T_3; // @[FPU.scala:332:{49,84}] wire _prevOK_prevOK_T_5 = ~_prevOK_prevOK_T_4; // @[FPU.scala:332:84, :384:20] wire [2:0] _prevOK_curOK_T_7 = unswizzled_1[31:29]; // @[FPU.scala:249:25, :380:27] wire _prevOK_curOK_T_8 = &_prevOK_curOK_T_7; // @[FPU.scala:249:{25,56}] wire _prevOK_curOK_T_9 = ~_prevOK_curOK_T_8; // @[FPU.scala:249:56, :385:19] wire _prevOK_curOK_T_10 = unswizzled_1[28]; // @[FPU.scala:380:27, :385:35] wire [6:0] _prevOK_curOK_T_11 = unswizzled_1[22:16]; // @[FPU.scala:380:27, :385:60] wire _prevOK_curOK_T_12 = &_prevOK_curOK_T_11; // @[FPU.scala:385:{60,96}] wire _prevOK_curOK_T_13 = _prevOK_curOK_T_10 == _prevOK_curOK_T_12; // @[FPU.scala:385:{35,55,96}] wire prevOK_curOK_1 = _prevOK_curOK_T_9 \| _prevOK_curOK_T_13; // @[FPU.scala:385:{19,31,55}] wire _prevOK_T_7 = prevOK_curOK_1; // @[FPU.scala:385:31, :386:14] wire prevOK_1 = _prevOK_T_6 \| _prevOK_T_7; // @[FPU.scala:384:{20,33}, :386:14] wire [2:0] _curOK_T_7 = wdata_1[63:61]; // @[package.scala:39:76] wire [2:0] _frfWriteBundle_1_wrdata_T_1 = wdata_1[63:61]; // @[package.scala:39:76] wire _curOK_T_8 = &_curOK_T_7; // @[FPU.scala:249:{25,56}] wire _curOK_T_9 = ~_curOK_T_8; // @[FPU.scala:249:56, :385:19] wire _curOK_T_10 = wdata_1[60]; // @[package.scala:39:76] wire [19:0] _curOK_T_11 = wdata_1[51:32]; // @[package.scala:39:76] wire _curOK_T_12 = &_curOK_T_11; // @[FPU.scala:385:{60,96}] wire _curOK_T_13 = _curOK_T_10 == _curOK_T_12; // @[FPU.scala:385:{35,55,96}] wire curOK_1 = _curOK_T_9 \| _curOK_T_13; // @[FPU.scala:385:{19,31,55}]
Generate the Verilog code corresponding to this FIRRTL code module MSHR_43 : input clock : Clock input reset : Reset output io : { flip allocate : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, repeat : UInt<1>}}, flip directory : { valid : UInt<1>, bits : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>, hit : UInt<1>, way : UInt<4>}}, status : { valid : UInt<1>, bits : { set : UInt<11>, tag : UInt<9>, way : UInt<4>, blockB : UInt<1>, nestB : UInt<1>, blockC : UInt<1>, nestC : UInt<1>}}, schedule : { flip ready : UInt<1>, valid : UInt<1>, bits : { a : { valid : UInt<1>, bits : { tag : UInt<9>, set : UInt<11>, param : UInt<3>, source : UInt<4>, block : UInt<1>}}, b : { valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<9>, set : UInt<11>, clients : UInt<1>}}, c : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, source : UInt<4>, tag : UInt<9>, set : UInt<11>, way : UInt<4>, dirty : UInt<1>}}, d : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, sink : UInt<4>, way : UInt<4>, bad : UInt<1>}}, e : { valid : UInt<1>, bits : { sink : UInt<3>}}, x : { valid : UInt<1>, bits : { fail : UInt<1>}}, dir : { valid : UInt<1>, bits : { set : UInt<11>, way : UInt<4>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>}}}, reload : UInt<1>}}, flip sinkc : { valid : UInt<1>, bits : { last : UInt<1>, set : UInt<11>, tag : UInt<9>, source : UInt<6>, param : UInt<3>, data : UInt<1>}}, flip sinkd : { valid : UInt<1>, bits : { last : UInt<1>, opcode : UInt<3>, param : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>}}, flip sinke : { valid : UInt<1>, bits : { sink : UInt<4>}}, flip nestedwb : { set : UInt<11>, tag : UInt<9>, b_toN : UInt<1>, b_toB : UInt<1>, b_clr_dirty : UInt<1>, c_set_dirty : UInt<1>}} regreset request_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg request : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>}, clock regreset meta_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg meta : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>, hit : UInt<1>, way : UInt<4>}, clock when meta_valid : node _T = eq(meta.state, UInt<2>(0h0)) when _T : node _T_1 = orr(meta.clients) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:105 assert (!meta.clients.orR)\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert node _T_6 = eq(meta.dirty, UInt<1>(0h0)) node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : node _T_9 = eq(_T_6, UInt<1>(0h0)) when _T_9 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:106 assert (!meta.dirty)\n") : printf_1 assert(clock, _T_6, UInt<1>(0h1), "") : assert_1 node _T_10 = eq(meta.state, UInt<2>(0h1)) when _T_10 : node _T_11 = eq(meta.dirty, UInt<1>(0h0)) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:109 assert (!meta.dirty)\n") : printf_2 assert(clock, _T_11, UInt<1>(0h1), "") : assert_2 node _T_15 = eq(meta.state, UInt<2>(0h2)) when _T_15 : node _T_16 = orr(meta.clients) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:112 assert (meta.clients.orR)\n") : printf_3 assert(clock, _T_16, UInt<1>(0h1), "") : assert_3 node _T_20 = sub(meta.clients, UInt<1>(0h1)) node _T_21 = tail(_T_20, 1) node _T_22 = and(meta.clients, _T_21) node _T_23 = eq(_T_22, UInt<1>(0h0)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:113 assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one\n") : printf_4 assert(clock, _T_23, UInt<1>(0h1), "") : assert_4 node _T_27 = eq(meta.state, UInt<2>(0h3)) when _T_27 : skip regreset s_rprobe : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_rprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_rprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_release : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_releaseack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_pprobe : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_acquire : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_flush : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantlast : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grant : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_probeack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_grantack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_execute : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_writeback : UInt<1>, clock, reset, UInt<1>(0h1) reg sink : UInt<3>, clock reg gotT : UInt<1>, clock reg bad_grant : UInt<1>, clock reg probes_done : UInt<1>, clock reg probes_toN : UInt<1>, clock reg probes_noT : UInt<1>, clock node _T_28 = neq(meta.state, UInt<2>(0h0)) node _T_29 = and(meta_valid, _T_28) node _T_30 = eq(io.nestedwb.set, request.set) node _T_31 = and(_T_29, _T_30) node _T_32 = eq(io.nestedwb.tag, meta.tag) node _T_33 = and(_T_31, _T_32) when _T_33 : when io.nestedwb.b_clr_dirty : connect meta.dirty, UInt<1>(0h0) when io.nestedwb.c_set_dirty : connect meta.dirty, UInt<1>(0h1) when io.nestedwb.b_toB : connect meta.state, UInt<2>(0h1) when io.nestedwb.b_toN : connect meta.hit, UInt<1>(0h0) connect io.status.valid, request_valid connect io.status.bits.set, request.set connect io.status.bits.tag, request.tag connect io.status.bits.way, meta.way node _io_status_bits_blockB_T = eq(meta_valid, UInt<1>(0h0)) node _io_status_bits_blockB_T_1 = eq(w_releaseack, UInt<1>(0h0)) node _io_status_bits_blockB_T_2 = eq(w_rprobeacklast, UInt<1>(0h0)) node _io_status_bits_blockB_T_3 = or(_io_status_bits_blockB_T_1, _io_status_bits_blockB_T_2) node _io_status_bits_blockB_T_4 = eq(w_pprobeacklast, UInt<1>(0h0)) node _io_status_bits_blockB_T_5 = or(_io_status_bits_blockB_T_3, _io_status_bits_blockB_T_4) node _io_status_bits_blockB_T_6 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_blockB_T_7 = and(_io_status_bits_blockB_T_5, _io_status_bits_blockB_T_6) node _io_status_bits_blockB_T_8 = or(_io_status_bits_blockB_T, _io_status_bits_blockB_T_7) connect io.status.bits.blockB, _io_status_bits_blockB_T_8 node _io_status_bits_nestB_T = and(meta_valid, w_releaseack) node _io_status_bits_nestB_T_1 = and(_io_status_bits_nestB_T, w_rprobeacklast) node _io_status_bits_nestB_T_2 = and(_io_status_bits_nestB_T_1, w_pprobeacklast) node _io_status_bits_nestB_T_3 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_nestB_T_4 = and(_io_status_bits_nestB_T_2, _io_status_bits_nestB_T_3) connect io.status.bits.nestB, _io_status_bits_nestB_T_4 node _io_status_bits_blockC_T = eq(meta_valid, UInt<1>(0h0)) connect io.status.bits.blockC, _io_status_bits_blockC_T node _io_status_bits_nestC_T = eq(w_rprobeackfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_1 = eq(w_pprobeackfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_2 = or(_io_status_bits_nestC_T, _io_status_bits_nestC_T_1) node _io_status_bits_nestC_T_3 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_4 = or(_io_status_bits_nestC_T_2, _io_status_bits_nestC_T_3) node _io_status_bits_nestC_T_5 = and(meta_valid, _io_status_bits_nestC_T_4) connect io.status.bits.nestC, _io_status_bits_nestC_T_5 node _T_34 = eq(io.status.bits.nestB, UInt<1>(0h0)) node _T_35 = eq(io.status.bits.blockB, UInt<1>(0h0)) node _T_36 = or(_T_34, _T_35) node _T_37 = asUInt(reset) node _T_38 = eq(_T_37, UInt<1>(0h0)) when _T_38 : node _T_39 = eq(_T_36, UInt<1>(0h0)) when _T_39 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:179 assert (!io.status.bits.nestB \|\| !io.status.bits.blockB)\n") : printf_5 assert(clock, _T_36, UInt<1>(0h1), "") : assert_5 node _T_40 = eq(io.status.bits.nestC, UInt<1>(0h0)) node _T_41 = eq(io.status.bits.blockC, UInt<1>(0h0)) node _T_42 = or(_T_40, _T_41) node _T_43 = asUInt(reset) node _T_44 = eq(_T_43, UInt<1>(0h0)) when _T_44 : node _T_45 = eq(_T_42, UInt<1>(0h0)) when _T_45 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:180 assert (!io.status.bits.nestC \|\| !io.status.bits.blockC)\n") : printf_6 assert(clock, _T_42, UInt<1>(0h1), "") : assert_6 node _no_wait_T = and(w_rprobeacklast, w_releaseack) node _no_wait_T_1 = and(_no_wait_T, w_grantlast) node _no_wait_T_2 = and(_no_wait_T_1, w_pprobeacklast) node no_wait = and(_no_wait_T_2, w_grantack) node _io_schedule_bits_a_valid_T = eq(s_acquire, UInt<1>(0h0)) node _io_schedule_bits_a_valid_T_1 = and(_io_schedule_bits_a_valid_T, s_release) node _io_schedule_bits_a_valid_T_2 = and(_io_schedule_bits_a_valid_T_1, s_pprobe) connect io.schedule.bits.a.valid, _io_schedule_bits_a_valid_T_2 node _io_schedule_bits_b_valid_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_valid_T_1 = eq(s_pprobe, UInt<1>(0h0)) node _io_schedule_bits_b_valid_T_2 = or(_io_schedule_bits_b_valid_T, _io_schedule_bits_b_valid_T_1) connect io.schedule.bits.b.valid, _io_schedule_bits_b_valid_T_2 node _io_schedule_bits_c_valid_T = eq(s_release, UInt<1>(0h0)) node _io_schedule_bits_c_valid_T_1 = and(_io_schedule_bits_c_valid_T, w_rprobeackfirst) node _io_schedule_bits_c_valid_T_2 = eq(s_probeack, UInt<1>(0h0)) node _io_schedule_bits_c_valid_T_3 = and(_io_schedule_bits_c_valid_T_2, w_pprobeackfirst) node _io_schedule_bits_c_valid_T_4 = or(_io_schedule_bits_c_valid_T_1, _io_schedule_bits_c_valid_T_3) connect io.schedule.bits.c.valid, _io_schedule_bits_c_valid_T_4 node _io_schedule_bits_d_valid_T = eq(s_execute, UInt<1>(0h0)) node _io_schedule_bits_d_valid_T_1 = and(_io_schedule_bits_d_valid_T, w_pprobeack) node _io_schedule_bits_d_valid_T_2 = and(_io_schedule_bits_d_valid_T_1, w_grant) connect io.schedule.bits.d.valid, _io_schedule_bits_d_valid_T_2 node _io_schedule_bits_e_valid_T = eq(s_grantack, UInt<1>(0h0)) node _io_schedule_bits_e_valid_T_1 = and(_io_schedule_bits_e_valid_T, w_grantfirst) connect io.schedule.bits.e.valid, _io_schedule_bits_e_valid_T_1 node _io_schedule_bits_x_valid_T = eq(s_flush, UInt<1>(0h0)) node _io_schedule_bits_x_valid_T_1 = and(_io_schedule_bits_x_valid_T, w_releaseack) connect io.schedule.bits.x.valid, _io_schedule_bits_x_valid_T_1 node _io_schedule_bits_dir_valid_T = eq(s_release, UInt<1>(0h0)) node _io_schedule_bits_dir_valid_T_1 = and(_io_schedule_bits_dir_valid_T, w_rprobeackfirst) node _io_schedule_bits_dir_valid_T_2 = eq(s_writeback, UInt<1>(0h0)) node _io_schedule_bits_dir_valid_T_3 = and(_io_schedule_bits_dir_valid_T_2, no_wait) node _io_schedule_bits_dir_valid_T_4 = or(_io_schedule_bits_dir_valid_T_1, _io_schedule_bits_dir_valid_T_3) connect io.schedule.bits.dir.valid, _io_schedule_bits_dir_valid_T_4 connect io.schedule.bits.reload, no_wait node _io_schedule_valid_T = or(io.schedule.bits.a.valid, io.schedule.bits.b.valid) node _io_schedule_valid_T_1 = or(_io_schedule_valid_T, io.schedule.bits.c.valid) node _io_schedule_valid_T_2 = or(_io_schedule_valid_T_1, io.schedule.bits.d.valid) node _io_schedule_valid_T_3 = or(_io_schedule_valid_T_2, io.schedule.bits.e.valid) node _io_schedule_valid_T_4 = or(_io_schedule_valid_T_3, io.schedule.bits.x.valid) node _io_schedule_valid_T_5 = or(_io_schedule_valid_T_4, io.schedule.bits.dir.valid) connect io.schedule.valid, _io_schedule_valid_T_5 when io.schedule.ready : connect s_rprobe, UInt<1>(0h1) when w_rprobeackfirst : connect s_release, UInt<1>(0h1) connect s_pprobe, UInt<1>(0h1) node _T_46 = and(s_release, s_pprobe) when _T_46 : connect s_acquire, UInt<1>(0h1) when w_releaseack : connect s_flush, UInt<1>(0h1) when w_pprobeackfirst : connect s_probeack, UInt<1>(0h1) when w_grantfirst : connect s_grantack, UInt<1>(0h1) node _T_47 = and(w_pprobeack, w_grant) when _T_47 : connect s_execute, UInt<1>(0h1) when no_wait : connect s_writeback, UInt<1>(0h1) when no_wait : connect request_valid, UInt<1>(0h0) connect meta_valid, UInt<1>(0h0) wire final_meta_writeback : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>, hit : UInt<1>, way : UInt<4>} connect final_meta_writeback, meta node req_clientBit = eq(request.source, UInt<6>(0h28)) node _req_needT_T = bits(request.opcode, 2, 2) node _req_needT_T_1 = eq(_req_needT_T, UInt<1>(0h0)) node _req_needT_T_2 = eq(request.opcode, UInt<3>(0h5)) node _req_needT_T_3 = eq(request.param, UInt<1>(0h1)) node _req_needT_T_4 = and(_req_needT_T_2, _req_needT_T_3) node _req_needT_T_5 = or(_req_needT_T_1, _req_needT_T_4) node _req_needT_T_6 = eq(request.opcode, UInt<3>(0h6)) node _req_needT_T_7 = eq(request.opcode, UInt<3>(0h7)) node _req_needT_T_8 = or(_req_needT_T_6, _req_needT_T_7) node _req_needT_T_9 = neq(request.param, UInt<2>(0h0)) node _req_needT_T_10 = and(_req_needT_T_8, _req_needT_T_9) node req_needT = or(_req_needT_T_5, _req_needT_T_10) node _req_acquire_T = eq(request.opcode, UInt<3>(0h6)) node _req_acquire_T_1 = eq(request.opcode, UInt<3>(0h7)) node req_acquire = or(_req_acquire_T, _req_acquire_T_1) node _meta_no_clients_T = orr(meta.clients) node meta_no_clients = eq(_meta_no_clients_T, UInt<1>(0h0)) node _req_promoteT_T = eq(meta.state, UInt<2>(0h3)) node _req_promoteT_T_1 = and(meta_no_clients, _req_promoteT_T) node _req_promoteT_T_2 = mux(meta.hit, _req_promoteT_T_1, gotT) node req_promoteT = and(req_acquire, _req_promoteT_T_2) node _T_48 = and(request.prio[2], UInt<1>(0h1)) when _T_48 : node _final_meta_writeback_dirty_T = bits(request.opcode, 0, 0) node _final_meta_writeback_dirty_T_1 = or(meta.dirty, _final_meta_writeback_dirty_T) connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_1 node _final_meta_writeback_state_T = neq(request.param, UInt<3>(0h3)) node _final_meta_writeback_state_T_1 = eq(meta.state, UInt<2>(0h2)) node _final_meta_writeback_state_T_2 = and(_final_meta_writeback_state_T, _final_meta_writeback_state_T_1) node _final_meta_writeback_state_T_3 = mux(_final_meta_writeback_state_T_2, UInt<2>(0h3), meta.state) connect final_meta_writeback.state, _final_meta_writeback_state_T_3 node _final_meta_writeback_clients_T = eq(request.param, UInt<3>(0h1)) node _final_meta_writeback_clients_T_1 = eq(request.param, UInt<3>(0h2)) node _final_meta_writeback_clients_T_2 = or(_final_meta_writeback_clients_T, _final_meta_writeback_clients_T_1) node _final_meta_writeback_clients_T_3 = eq(request.param, UInt<3>(0h5)) node _final_meta_writeback_clients_T_4 = or(_final_meta_writeback_clients_T_2, _final_meta_writeback_clients_T_3) node _final_meta_writeback_clients_T_5 = mux(_final_meta_writeback_clients_T_4, req_clientBit, UInt<1>(0h0)) node _final_meta_writeback_clients_T_6 = not(_final_meta_writeback_clients_T_5) node _final_meta_writeback_clients_T_7 = and(meta.clients, _final_meta_writeback_clients_T_6) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_7 connect final_meta_writeback.hit, UInt<1>(0h1) else : node _T_49 = and(request.control, UInt<1>(0h1)) when _T_49 : when meta.hit : connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h0) node _final_meta_writeback_clients_T_8 = not(probes_toN) node _final_meta_writeback_clients_T_9 = and(meta.clients, _final_meta_writeback_clients_T_8) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_9 connect final_meta_writeback.hit, UInt<1>(0h0) else : node _final_meta_writeback_dirty_T_2 = and(meta.hit, meta.dirty) node _final_meta_writeback_dirty_T_3 = bits(request.opcode, 2, 2) node _final_meta_writeback_dirty_T_4 = eq(_final_meta_writeback_dirty_T_3, UInt<1>(0h0)) node _final_meta_writeback_dirty_T_5 = or(_final_meta_writeback_dirty_T_2, _final_meta_writeback_dirty_T_4) connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_5 node _final_meta_writeback_state_T_4 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_5 = eq(meta.hit, UInt<1>(0h0)) node _final_meta_writeback_state_T_6 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_7 = mux(gotT, _final_meta_writeback_state_T_6, UInt<2>(0h1)) node _final_meta_writeback_state_T_8 = and(meta_no_clients, req_acquire) node _final_meta_writeback_state_T_9 = mux(_final_meta_writeback_state_T_8, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_10 = eq(UInt<2>(0h1), meta.state) node _final_meta_writeback_state_T_11 = mux(_final_meta_writeback_state_T_10, UInt<2>(0h1), UInt<2>(0h1)) node _final_meta_writeback_state_T_12 = eq(UInt<2>(0h2), meta.state) node _final_meta_writeback_state_T_13 = mux(_final_meta_writeback_state_T_12, UInt<2>(0h3), _final_meta_writeback_state_T_11) node _final_meta_writeback_state_T_14 = eq(UInt<2>(0h3), meta.state) node _final_meta_writeback_state_T_15 = mux(_final_meta_writeback_state_T_14, _final_meta_writeback_state_T_9, _final_meta_writeback_state_T_13) node _final_meta_writeback_state_T_16 = mux(_final_meta_writeback_state_T_5, _final_meta_writeback_state_T_7, _final_meta_writeback_state_T_15) node _final_meta_writeback_state_T_17 = mux(req_needT, _final_meta_writeback_state_T_4, _final_meta_writeback_state_T_16) connect final_meta_writeback.state, _final_meta_writeback_state_T_17 node _final_meta_writeback_clients_T_10 = not(probes_toN) node _final_meta_writeback_clients_T_11 = and(meta.clients, _final_meta_writeback_clients_T_10) node _final_meta_writeback_clients_T_12 = mux(meta.hit, _final_meta_writeback_clients_T_11, UInt<1>(0h0)) node _final_meta_writeback_clients_T_13 = mux(req_acquire, req_clientBit, UInt<1>(0h0)) node _final_meta_writeback_clients_T_14 = or(_final_meta_writeback_clients_T_12, _final_meta_writeback_clients_T_13) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_14 connect final_meta_writeback.tag, request.tag connect final_meta_writeback.hit, UInt<1>(0h1) when bad_grant : when meta.hit : node _T_50 = eq(meta_valid, UInt<1>(0h0)) node _T_51 = eq(meta.state, UInt<2>(0h1)) node _T_52 = or(_T_50, _T_51) node _T_53 = asUInt(reset) node _T_54 = eq(_T_53, UInt<1>(0h0)) when _T_54 : node _T_55 = eq(_T_52, UInt<1>(0h0)) when _T_55 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:254 assert (!meta_valid \|\| meta.state === BRANCH)\n") : printf_7 assert(clock, _T_52, UInt<1>(0h1), "") : assert_7 connect final_meta_writeback.hit, UInt<1>(0h1) connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h1) node _final_meta_writeback_clients_T_15 = not(probes_toN) node _final_meta_writeback_clients_T_16 = and(meta.clients, _final_meta_writeback_clients_T_15) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_16 else : connect final_meta_writeback.hit, UInt<1>(0h0) connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h0) connect final_meta_writeback.clients, UInt<1>(0h0) wire invalid : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} connect invalid.dirty, UInt<1>(0h0) connect invalid.state, UInt<2>(0h0) connect invalid.clients, UInt<1>(0h0) connect invalid.tag, UInt<1>(0h0) node _honour_BtoT_T = and(meta.clients, req_clientBit) node _honour_BtoT_T_1 = orr(_honour_BtoT_T) node honour_BtoT = and(meta.hit, _honour_BtoT_T_1) node _excluded_client_T = and(meta.hit, request.prio[0]) node _excluded_client_T_1 = eq(request.opcode, UInt<3>(0h6)) node _excluded_client_T_2 = eq(request.opcode, UInt<3>(0h7)) node _excluded_client_T_3 = or(_excluded_client_T_1, _excluded_client_T_2) node _excluded_client_T_4 = eq(request.opcode, UInt<3>(0h4)) node _excluded_client_T_5 = or(_excluded_client_T_3, _excluded_client_T_4) node _excluded_client_T_6 = eq(request.opcode, UInt<3>(0h5)) node _excluded_client_T_7 = and(_excluded_client_T_6, UInt<1>(0h0)) node _excluded_client_T_8 = or(_excluded_client_T_5, _excluded_client_T_7) node _excluded_client_T_9 = and(_excluded_client_T, _excluded_client_T_8) node excluded_client = mux(_excluded_client_T_9, req_clientBit, UInt<1>(0h0)) connect io.schedule.bits.a.bits.tag, request.tag connect io.schedule.bits.a.bits.set, request.set node _io_schedule_bits_a_bits_param_T = mux(meta.hit, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_a_bits_param_T_1 = mux(req_needT, _io_schedule_bits_a_bits_param_T, UInt<2>(0h0)) connect io.schedule.bits.a.bits.param, _io_schedule_bits_a_bits_param_T_1 node _io_schedule_bits_a_bits_block_T = neq(request.size, UInt<3>(0h6)) node _io_schedule_bits_a_bits_block_T_1 = eq(request.opcode, UInt<1>(0h0)) node _io_schedule_bits_a_bits_block_T_2 = eq(request.opcode, UInt<3>(0h7)) node _io_schedule_bits_a_bits_block_T_3 = or(_io_schedule_bits_a_bits_block_T_1, _io_schedule_bits_a_bits_block_T_2) node _io_schedule_bits_a_bits_block_T_4 = eq(_io_schedule_bits_a_bits_block_T_3, UInt<1>(0h0)) node _io_schedule_bits_a_bits_block_T_5 = or(_io_schedule_bits_a_bits_block_T, _io_schedule_bits_a_bits_block_T_4) connect io.schedule.bits.a.bits.block, _io_schedule_bits_a_bits_block_T_5 connect io.schedule.bits.a.bits.source, UInt<1>(0h0) node _io_schedule_bits_b_bits_param_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_bits_param_T_1 = mux(req_needT, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_b_bits_param_T_2 = mux(request.prio[1], request.param, _io_schedule_bits_b_bits_param_T_1) node _io_schedule_bits_b_bits_param_T_3 = mux(_io_schedule_bits_b_bits_param_T, UInt<2>(0h2), _io_schedule_bits_b_bits_param_T_2) connect io.schedule.bits.b.bits.param, _io_schedule_bits_b_bits_param_T_3 node _io_schedule_bits_b_bits_tag_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_bits_tag_T_1 = mux(_io_schedule_bits_b_bits_tag_T, meta.tag, request.tag) connect io.schedule.bits.b.bits.tag, _io_schedule_bits_b_bits_tag_T_1 connect io.schedule.bits.b.bits.set, request.set node _io_schedule_bits_b_bits_clients_T = not(excluded_client) node _io_schedule_bits_b_bits_clients_T_1 = and(meta.clients, _io_schedule_bits_b_bits_clients_T) connect io.schedule.bits.b.bits.clients, _io_schedule_bits_b_bits_clients_T_1 node _io_schedule_bits_c_bits_opcode_T = mux(meta.dirty, UInt<3>(0h7), UInt<3>(0h6)) connect io.schedule.bits.c.bits.opcode, _io_schedule_bits_c_bits_opcode_T node _io_schedule_bits_c_bits_param_T = eq(meta.state, UInt<2>(0h1)) node _io_schedule_bits_c_bits_param_T_1 = mux(_io_schedule_bits_c_bits_param_T, UInt<3>(0h2), UInt<3>(0h1)) connect io.schedule.bits.c.bits.param, _io_schedule_bits_c_bits_param_T_1 connect io.schedule.bits.c.bits.source, UInt<1>(0h0) connect io.schedule.bits.c.bits.tag, meta.tag connect io.schedule.bits.c.bits.set, request.set connect io.schedule.bits.c.bits.way, meta.way connect io.schedule.bits.c.bits.dirty, meta.dirty connect io.schedule.bits.d.bits.set, request.set connect io.schedule.bits.d.bits.put, request.put connect io.schedule.bits.d.bits.offset, request.offset connect io.schedule.bits.d.bits.tag, request.tag connect io.schedule.bits.d.bits.source, request.source connect io.schedule.bits.d.bits.size, request.size connect io.schedule.bits.d.bits.param, request.param connect io.schedule.bits.d.bits.opcode, request.opcode connect io.schedule.bits.d.bits.control, request.control connect io.schedule.bits.d.bits.prio, request.prio node _io_schedule_bits_d_bits_param_T = eq(req_acquire, UInt<1>(0h0)) node _io_schedule_bits_d_bits_param_T_1 = mux(req_promoteT, UInt<2>(0h1), UInt<2>(0h0)) node _io_schedule_bits_d_bits_param_T_2 = mux(honour_BtoT, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_d_bits_param_T_3 = eq(UInt<2>(0h0), request.param) node _io_schedule_bits_d_bits_param_T_4 = mux(_io_schedule_bits_d_bits_param_T_3, _io_schedule_bits_d_bits_param_T_1, request.param) node _io_schedule_bits_d_bits_param_T_5 = eq(UInt<2>(0h2), request.param) node _io_schedule_bits_d_bits_param_T_6 = mux(_io_schedule_bits_d_bits_param_T_5, _io_schedule_bits_d_bits_param_T_2, _io_schedule_bits_d_bits_param_T_4) node _io_schedule_bits_d_bits_param_T_7 = eq(UInt<2>(0h1), request.param) node _io_schedule_bits_d_bits_param_T_8 = mux(_io_schedule_bits_d_bits_param_T_7, UInt<2>(0h1), _io_schedule_bits_d_bits_param_T_6) node _io_schedule_bits_d_bits_param_T_9 = mux(_io_schedule_bits_d_bits_param_T, request.param, _io_schedule_bits_d_bits_param_T_8) connect io.schedule.bits.d.bits.param, _io_schedule_bits_d_bits_param_T_9 connect io.schedule.bits.d.bits.sink, UInt<1>(0h0) connect io.schedule.bits.d.bits.way, meta.way connect io.schedule.bits.d.bits.bad, bad_grant connect io.schedule.bits.e.bits.sink, sink connect io.schedule.bits.x.bits.fail, UInt<1>(0h0) connect io.schedule.bits.dir.bits.set, request.set connect io.schedule.bits.dir.bits.way, meta.way node _io_schedule_bits_dir_bits_data_T = eq(s_release, UInt<1>(0h0)) wire _io_schedule_bits_dir_bits_data_WIRE : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} connect _io_schedule_bits_dir_bits_data_WIRE.tag, final_meta_writeback.tag connect _io_schedule_bits_dir_bits_data_WIRE.clients, final_meta_writeback.clients connect _io_schedule_bits_dir_bits_data_WIRE.state, final_meta_writeback.state connect _io_schedule_bits_dir_bits_data_WIRE.dirty, final_meta_writeback.dirty node _io_schedule_bits_dir_bits_data_T_1 = mux(_io_schedule_bits_dir_bits_data_T, invalid, _io_schedule_bits_dir_bits_data_WIRE) connect io.schedule.bits.dir.bits.data, _io_schedule_bits_dir_bits_data_T_1 node _evict_T = eq(meta.hit, UInt<1>(0h0)) wire evict : UInt connect evict, UInt<1>(0h0) node evict_c = orr(meta.clients) node _evict_T_1 = eq(UInt<2>(0h1), meta.state) when _evict_T_1 : node _evict_out_T = mux(evict_c, UInt<1>(0h0), UInt<1>(0h1)) connect evict, _evict_out_T else : node _evict_T_2 = eq(UInt<2>(0h2), meta.state) when _evict_T_2 : node _evict_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect evict, _evict_out_T_1 else : node _evict_T_3 = eq(UInt<2>(0h3), meta.state) when _evict_T_3 : node _evict_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _evict_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _evict_out_T_4 = mux(evict_c, _evict_out_T_2, _evict_out_T_3) connect evict, _evict_out_T_4 else : node _evict_T_4 = eq(UInt<2>(0h0), meta.state) when _evict_T_4 : connect evict, UInt<4>(0h8) node _evict_T_5 = eq(_evict_T, UInt<1>(0h0)) when _evict_T_5 : connect evict, UInt<4>(0h8) wire before : UInt connect before, UInt<1>(0h0) node before_c = orr(meta.clients) node _before_T = eq(UInt<2>(0h1), meta.state) when _before_T : node _before_out_T = mux(before_c, UInt<1>(0h0), UInt<1>(0h1)) connect before, _before_out_T else : node _before_T_1 = eq(UInt<2>(0h2), meta.state) when _before_T_1 : node _before_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect before, _before_out_T_1 else : node _before_T_2 = eq(UInt<2>(0h3), meta.state) when _before_T_2 : node _before_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _before_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _before_out_T_4 = mux(before_c, _before_out_T_2, _before_out_T_3) connect before, _before_out_T_4 else : node _before_T_3 = eq(UInt<2>(0h0), meta.state) when _before_T_3 : connect before, UInt<4>(0h8) node _before_T_4 = eq(meta.hit, UInt<1>(0h0)) when _before_T_4 : connect before, UInt<4>(0h8) wire after : UInt connect after, UInt<1>(0h0) node after_c = orr(final_meta_writeback.clients) node _after_T = eq(UInt<2>(0h1), final_meta_writeback.state) when _after_T : node _after_out_T = mux(after_c, UInt<1>(0h0), UInt<1>(0h1)) connect after, _after_out_T else : node _after_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state) when _after_T_1 : node _after_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect after, _after_out_T_1 else : node _after_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state) when _after_T_2 : node _after_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _after_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _after_out_T_4 = mux(after_c, _after_out_T_2, _after_out_T_3) connect after, _after_out_T_4 else : node _after_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state) when _after_T_3 : connect after, UInt<4>(0h8) node _after_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) when _after_T_4 : connect after, UInt<4>(0h8) node _T_56 = eq(s_release, UInt<1>(0h0)) node _T_57 = and(_T_56, w_rprobeackfirst) node _T_58 = and(_T_57, io.schedule.ready) when _T_58 : node _T_59 = eq(evict, UInt<1>(0h1)) node _T_60 = eq(_T_59, UInt<1>(0h0)) node _T_61 = asUInt(reset) node _T_62 = eq(_T_61, UInt<1>(0h0)) when _T_62 : node _T_63 = eq(_T_60, UInt<1>(0h0)) when _T_63 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_8 assert(clock, _T_60, UInt<1>(0h1), "") : assert_8 node _T_64 = eq(before, UInt<1>(0h1)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(_T_65, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_9 assert(clock, _T_65, UInt<1>(0h1), "") : assert_9 node _T_69 = eq(evict, UInt<1>(0h0)) node _T_70 = eq(_T_69, UInt<1>(0h0)) node _T_71 = asUInt(reset) node _T_72 = eq(_T_71, UInt<1>(0h0)) when _T_72 : node _T_73 = eq(_T_70, UInt<1>(0h0)) when _T_73 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_10 assert(clock, _T_70, UInt<1>(0h1), "") : assert_10 node _T_74 = eq(before, UInt<1>(0h0)) node _T_75 = eq(_T_74, UInt<1>(0h0)) node _T_76 = asUInt(reset) node _T_77 = eq(_T_76, UInt<1>(0h0)) when _T_77 : node _T_78 = eq(_T_75, UInt<1>(0h0)) when _T_78 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_11 assert(clock, _T_75, UInt<1>(0h1), "") : assert_11 node _T_79 = eq(evict, UInt<3>(0h7)) node _T_80 = eq(before, UInt<3>(0h7)) node _T_81 = eq(evict, UInt<3>(0h5)) node _T_82 = eq(before, UInt<3>(0h5)) node _T_83 = eq(evict, UInt<3>(0h4)) node _T_84 = eq(before, UInt<3>(0h4)) node _T_85 = eq(evict, UInt<3>(0h6)) node _T_86 = eq(before, UInt<3>(0h6)) node _T_87 = eq(evict, UInt<2>(0h3)) node _T_88 = eq(before, UInt<2>(0h3)) node _T_89 = eq(evict, UInt<2>(0h2)) node _T_90 = eq(before, UInt<2>(0h2)) node _T_91 = eq(s_writeback, UInt<1>(0h0)) node _T_92 = and(_T_91, no_wait) node _T_93 = and(_T_92, io.schedule.ready) when _T_93 : node _T_94 = eq(before, UInt<4>(0h8)) node _T_95 = eq(after, UInt<1>(0h1)) node _T_96 = and(_T_94, _T_95) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = asUInt(reset) node _T_99 = eq(_T_98, UInt<1>(0h0)) when _T_99 : node _T_100 = eq(_T_97, UInt<1>(0h0)) when _T_100 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_12 assert(clock, _T_97, UInt<1>(0h1), "") : assert_12 node _T_101 = eq(before, UInt<4>(0h8)) node _T_102 = eq(after, UInt<1>(0h0)) node _T_103 = and(_T_101, _T_102) node _T_104 = eq(_T_103, UInt<1>(0h0)) node _T_105 = asUInt(reset) node _T_106 = eq(_T_105, UInt<1>(0h0)) when _T_106 : node _T_107 = eq(_T_104, UInt<1>(0h0)) when _T_107 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_13 assert(clock, _T_104, UInt<1>(0h1), "") : assert_13 node _T_108 = eq(before, UInt<4>(0h8)) node _T_109 = eq(after, UInt<3>(0h7)) node _T_110 = and(_T_108, _T_109) node _T_111 = eq(before, UInt<4>(0h8)) node _T_112 = eq(after, UInt<3>(0h5)) node _T_113 = and(_T_111, _T_112) node _T_114 = eq(_T_113, UInt<1>(0h0)) node _T_115 = asUInt(reset) node _T_116 = eq(_T_115, UInt<1>(0h0)) when _T_116 : node _T_117 = eq(_T_114, UInt<1>(0h0)) when _T_117 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_14 assert(clock, _T_114, UInt<1>(0h1), "") : assert_14 node _T_118 = eq(before, UInt<4>(0h8)) node _T_119 = eq(after, UInt<3>(0h4)) node _T_120 = and(_T_118, _T_119) node _T_121 = eq(_T_120, UInt<1>(0h0)) node _T_122 = asUInt(reset) node _T_123 = eq(_T_122, UInt<1>(0h0)) when _T_123 : node _T_124 = eq(_T_121, UInt<1>(0h0)) when _T_124 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_15 assert(clock, _T_121, UInt<1>(0h1), "") : assert_15 node _T_125 = eq(before, UInt<4>(0h8)) node _T_126 = eq(after, UInt<3>(0h6)) node _T_127 = and(_T_125, _T_126) node _T_128 = eq(before, UInt<4>(0h8)) node _T_129 = eq(after, UInt<2>(0h3)) node _T_130 = and(_T_128, _T_129) node _T_131 = eq(before, UInt<4>(0h8)) node _T_132 = eq(after, UInt<2>(0h2)) node _T_133 = and(_T_131, _T_132) node _T_134 = eq(_T_133, UInt<1>(0h0)) node _T_135 = asUInt(reset) node _T_136 = eq(_T_135, UInt<1>(0h0)) when _T_136 : node _T_137 = eq(_T_134, UInt<1>(0h0)) when _T_137 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_16 assert(clock, _T_134, UInt<1>(0h1), "") : assert_16 node _T_138 = eq(before, UInt<1>(0h1)) node _T_139 = eq(after, UInt<4>(0h8)) node _T_140 = and(_T_138, _T_139) node _T_141 = eq(_T_140, UInt<1>(0h0)) node _T_142 = asUInt(reset) node _T_143 = eq(_T_142, UInt<1>(0h0)) when _T_143 : node _T_144 = eq(_T_141, UInt<1>(0h0)) when _T_144 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_17 assert(clock, _T_141, UInt<1>(0h1), "") : assert_17 node _T_145 = eq(before, UInt<1>(0h1)) node _T_146 = eq(after, UInt<1>(0h0)) node _T_147 = and(_T_145, _T_146) node _T_148 = eq(_T_147, UInt<1>(0h0)) node _T_149 = asUInt(reset) node _T_150 = eq(_T_149, UInt<1>(0h0)) when _T_150 : node _T_151 = eq(_T_148, UInt<1>(0h0)) when _T_151 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_18 assert(clock, _T_148, UInt<1>(0h1), "") : assert_18 node _T_152 = eq(before, UInt<1>(0h1)) node _T_153 = eq(after, UInt<3>(0h7)) node _T_154 = and(_T_152, _T_153) node _T_155 = eq(_T_154, UInt<1>(0h0)) node _T_156 = asUInt(reset) node _T_157 = eq(_T_156, UInt<1>(0h0)) when _T_157 : node _T_158 = eq(_T_155, UInt<1>(0h0)) when _T_158 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_19 assert(clock, _T_155, UInt<1>(0h1), "") : assert_19 node _T_159 = eq(before, UInt<1>(0h1)) node _T_160 = eq(after, UInt<3>(0h5)) node _T_161 = and(_T_159, _T_160) node _T_162 = eq(_T_161, UInt<1>(0h0)) node _T_163 = asUInt(reset) node _T_164 = eq(_T_163, UInt<1>(0h0)) when _T_164 : node _T_165 = eq(_T_162, UInt<1>(0h0)) when _T_165 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_20 assert(clock, _T_162, UInt<1>(0h1), "") : assert_20 node _T_166 = eq(before, UInt<1>(0h1)) node _T_167 = eq(after, UInt<3>(0h4)) node _T_168 = and(_T_166, _T_167) node _T_169 = eq(_T_168, UInt<1>(0h0)) node _T_170 = asUInt(reset) node _T_171 = eq(_T_170, UInt<1>(0h0)) when _T_171 : node _T_172 = eq(_T_169, UInt<1>(0h0)) when _T_172 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_21 assert(clock, _T_169, UInt<1>(0h1), "") : assert_21 node _T_173 = eq(before, UInt<1>(0h1)) node _T_174 = eq(after, UInt<3>(0h6)) node _T_175 = and(_T_173, _T_174) node _T_176 = eq(_T_175, UInt<1>(0h0)) node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_T_176, UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_22 assert(clock, _T_176, UInt<1>(0h1), "") : assert_22 node _T_180 = eq(before, UInt<1>(0h1)) node _T_181 = eq(after, UInt<2>(0h3)) node _T_182 = and(_T_180, _T_181) node _T_183 = eq(_T_182, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(before, UInt<1>(0h1)) node _T_188 = eq(after, UInt<2>(0h2)) node _T_189 = and(_T_187, _T_188) node _T_190 = eq(_T_189, UInt<1>(0h0)) node _T_191 = asUInt(reset) node _T_192 = eq(_T_191, UInt<1>(0h0)) when _T_192 : node _T_193 = eq(_T_190, UInt<1>(0h0)) when _T_193 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_24 assert(clock, _T_190, UInt<1>(0h1), "") : assert_24 node _T_194 = eq(before, UInt<1>(0h0)) node _T_195 = eq(after, UInt<4>(0h8)) node _T_196 = and(_T_194, _T_195) node _T_197 = eq(_T_196, UInt<1>(0h0)) node _T_198 = asUInt(reset) node _T_199 = eq(_T_198, UInt<1>(0h0)) when _T_199 : node _T_200 = eq(_T_197, UInt<1>(0h0)) when _T_200 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_25 assert(clock, _T_197, UInt<1>(0h1), "") : assert_25 node _T_201 = eq(before, UInt<1>(0h0)) node _T_202 = eq(after, UInt<1>(0h1)) node _T_203 = and(_T_201, _T_202) node _T_204 = eq(_T_203, UInt<1>(0h0)) node _T_205 = asUInt(reset) node _T_206 = eq(_T_205, UInt<1>(0h0)) when _T_206 : node _T_207 = eq(_T_204, UInt<1>(0h0)) when _T_207 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_26 assert(clock, _T_204, UInt<1>(0h1), "") : assert_26 node _T_208 = eq(before, UInt<1>(0h0)) node _T_209 = eq(after, UInt<3>(0h7)) node _T_210 = and(_T_208, _T_209) node _T_211 = eq(_T_210, UInt<1>(0h0)) node _T_212 = asUInt(reset) node _T_213 = eq(_T_212, UInt<1>(0h0)) when _T_213 : node _T_214 = eq(_T_211, UInt<1>(0h0)) when _T_214 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_27 assert(clock, _T_211, UInt<1>(0h1), "") : assert_27 node _T_215 = eq(before, UInt<1>(0h0)) node _T_216 = eq(after, UInt<3>(0h5)) node _T_217 = and(_T_215, _T_216) node _T_218 = eq(_T_217, UInt<1>(0h0)) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_28 assert(clock, _T_218, UInt<1>(0h1), "") : assert_28 node _T_222 = eq(before, UInt<1>(0h0)) node _T_223 = eq(after, UInt<3>(0h6)) node _T_224 = and(_T_222, _T_223) node _T_225 = eq(_T_224, UInt<1>(0h0)) node _T_226 = asUInt(reset) node _T_227 = eq(_T_226, UInt<1>(0h0)) when _T_227 : node _T_228 = eq(_T_225, UInt<1>(0h0)) when _T_228 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_29 assert(clock, _T_225, UInt<1>(0h1), "") : assert_29 node _T_229 = eq(before, UInt<1>(0h0)) node _T_230 = eq(after, UInt<3>(0h4)) node _T_231 = and(_T_229, _T_230) node _T_232 = eq(_T_231, UInt<1>(0h0)) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(before, UInt<1>(0h0)) node _T_237 = eq(after, UInt<2>(0h3)) node _T_238 = and(_T_236, _T_237) node _T_239 = eq(_T_238, UInt<1>(0h0)) node _T_240 = asUInt(reset) node _T_241 = eq(_T_240, UInt<1>(0h0)) when _T_241 : node _T_242 = eq(_T_239, UInt<1>(0h0)) when _T_242 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_31 assert(clock, _T_239, UInt<1>(0h1), "") : assert_31 node _T_243 = eq(before, UInt<1>(0h0)) node _T_244 = eq(after, UInt<2>(0h2)) node _T_245 = and(_T_243, _T_244) node _T_246 = eq(_T_245, UInt<1>(0h0)) node _T_247 = asUInt(reset) node _T_248 = eq(_T_247, UInt<1>(0h0)) when _T_248 : node _T_249 = eq(_T_246, UInt<1>(0h0)) when _T_249 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_32 assert(clock, _T_246, UInt<1>(0h1), "") : assert_32 node _T_250 = eq(before, UInt<3>(0h7)) node _T_251 = eq(after, UInt<4>(0h8)) node _T_252 = and(_T_250, _T_251) node _T_253 = eq(_T_252, UInt<1>(0h0)) node _T_254 = asUInt(reset) node _T_255 = eq(_T_254, UInt<1>(0h0)) when _T_255 : node _T_256 = eq(_T_253, UInt<1>(0h0)) when _T_256 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_33 assert(clock, _T_253, UInt<1>(0h1), "") : assert_33 node _T_257 = eq(before, UInt<3>(0h7)) node _T_258 = eq(after, UInt<1>(0h1)) node _T_259 = and(_T_257, _T_258) node _T_260 = eq(_T_259, UInt<1>(0h0)) node _T_261 = asUInt(reset) node _T_262 = eq(_T_261, UInt<1>(0h0)) when _T_262 : node _T_263 = eq(_T_260, UInt<1>(0h0)) when _T_263 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_34 assert(clock, _T_260, UInt<1>(0h1), "") : assert_34 node _T_264 = eq(before, UInt<3>(0h7)) node _T_265 = eq(after, UInt<1>(0h0)) node _T_266 = and(_T_264, _T_265) node _T_267 = eq(_T_266, UInt<1>(0h0)) node _T_268 = asUInt(reset) node _T_269 = eq(_T_268, UInt<1>(0h0)) when _T_269 : node _T_270 = eq(_T_267, UInt<1>(0h0)) when _T_270 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_35 assert(clock, _T_267, UInt<1>(0h1), "") : assert_35 node _T_271 = eq(before, UInt<3>(0h7)) node _T_272 = eq(after, UInt<3>(0h5)) node _T_273 = and(_T_271, _T_272) node _T_274 = eq(_T_273, UInt<1>(0h0)) node _T_275 = asUInt(reset) node _T_276 = eq(_T_275, UInt<1>(0h0)) when _T_276 : node _T_277 = eq(_T_274, UInt<1>(0h0)) when _T_277 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_36 assert(clock, _T_274, UInt<1>(0h1), "") : assert_36 node _T_278 = eq(before, UInt<3>(0h7)) node _T_279 = eq(after, UInt<3>(0h6)) node _T_280 = and(_T_278, _T_279) node _T_281 = eq(before, UInt<3>(0h7)) node _T_282 = eq(after, UInt<3>(0h4)) node _T_283 = and(_T_281, _T_282) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = asUInt(reset) node _T_286 = eq(_T_285, UInt<1>(0h0)) when _T_286 : node _T_287 = eq(_T_284, UInt<1>(0h0)) when _T_287 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_37 assert(clock, _T_284, UInt<1>(0h1), "") : assert_37 node _T_288 = eq(before, UInt<3>(0h7)) node _T_289 = eq(after, UInt<2>(0h3)) node _T_290 = and(_T_288, _T_289) node _T_291 = eq(before, UInt<3>(0h7)) node _T_292 = eq(after, UInt<2>(0h2)) node _T_293 = and(_T_291, _T_292) node _T_294 = eq(_T_293, UInt<1>(0h0)) node _T_295 = asUInt(reset) node _T_296 = eq(_T_295, UInt<1>(0h0)) when _T_296 : node _T_297 = eq(_T_294, UInt<1>(0h0)) when _T_297 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_38 assert(clock, _T_294, UInt<1>(0h1), "") : assert_38 node _T_298 = eq(before, UInt<3>(0h5)) node _T_299 = eq(after, UInt<4>(0h8)) node _T_300 = and(_T_298, _T_299) node _T_301 = eq(_T_300, UInt<1>(0h0)) node _T_302 = asUInt(reset) node _T_303 = eq(_T_302, UInt<1>(0h0)) when _T_303 : node _T_304 = eq(_T_301, UInt<1>(0h0)) when _T_304 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_39 assert(clock, _T_301, UInt<1>(0h1), "") : assert_39 node _T_305 = eq(before, UInt<3>(0h5)) node _T_306 = eq(after, UInt<1>(0h1)) node _T_307 = and(_T_305, _T_306) node _T_308 = eq(_T_307, UInt<1>(0h0)) node _T_309 = asUInt(reset) node _T_310 = eq(_T_309, UInt<1>(0h0)) when _T_310 : node _T_311 = eq(_T_308, UInt<1>(0h0)) when _T_311 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_40 assert(clock, _T_308, UInt<1>(0h1), "") : assert_40 node _T_312 = eq(before, UInt<3>(0h5)) node _T_313 = eq(after, UInt<1>(0h0)) node _T_314 = and(_T_312, _T_313) node _T_315 = eq(_T_314, UInt<1>(0h0)) node _T_316 = asUInt(reset) node _T_317 = eq(_T_316, UInt<1>(0h0)) when _T_317 : node _T_318 = eq(_T_315, UInt<1>(0h0)) when _T_318 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_41 assert(clock, _T_315, UInt<1>(0h1), "") : assert_41 node _T_319 = eq(before, UInt<3>(0h5)) node _T_320 = eq(after, UInt<3>(0h7)) node _T_321 = and(_T_319, _T_320) node _T_322 = eq(before, UInt<3>(0h5)) node _T_323 = eq(after, UInt<3>(0h6)) node _T_324 = and(_T_322, _T_323) node _T_325 = eq(before, UInt<3>(0h5)) node _T_326 = eq(after, UInt<3>(0h4)) node _T_327 = and(_T_325, _T_326) node _T_328 = eq(_T_327, UInt<1>(0h0)) node _T_329 = asUInt(reset) node _T_330 = eq(_T_329, UInt<1>(0h0)) when _T_330 : node _T_331 = eq(_T_328, UInt<1>(0h0)) when _T_331 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_42 assert(clock, _T_328, UInt<1>(0h1), "") : assert_42 node _T_332 = eq(before, UInt<3>(0h5)) node _T_333 = eq(after, UInt<2>(0h3)) node _T_334 = and(_T_332, _T_333) node _T_335 = eq(before, UInt<3>(0h5)) node _T_336 = eq(after, UInt<2>(0h2)) node _T_337 = and(_T_335, _T_336) node _T_338 = eq(_T_337, UInt<1>(0h0)) node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(_T_338, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_43 assert(clock, _T_338, UInt<1>(0h1), "") : assert_43 node _T_342 = eq(before, UInt<3>(0h6)) node _T_343 = eq(after, UInt<4>(0h8)) node _T_344 = and(_T_342, _T_343) node _T_345 = eq(_T_344, UInt<1>(0h0)) node _T_346 = asUInt(reset) node _T_347 = eq(_T_346, UInt<1>(0h0)) when _T_347 : node _T_348 = eq(_T_345, UInt<1>(0h0)) when _T_348 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_44 assert(clock, _T_345, UInt<1>(0h1), "") : assert_44 node _T_349 = eq(before, UInt<3>(0h6)) node _T_350 = eq(after, UInt<1>(0h1)) node _T_351 = and(_T_349, _T_350) node _T_352 = eq(_T_351, UInt<1>(0h0)) node _T_353 = asUInt(reset) node _T_354 = eq(_T_353, UInt<1>(0h0)) when _T_354 : node _T_355 = eq(_T_352, UInt<1>(0h0)) when _T_355 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_45 assert(clock, _T_352, UInt<1>(0h1), "") : assert_45 node _T_356 = eq(before, UInt<3>(0h6)) node _T_357 = eq(after, UInt<1>(0h0)) node _T_358 = and(_T_356, _T_357) node _T_359 = eq(_T_358, UInt<1>(0h0)) node _T_360 = asUInt(reset) node _T_361 = eq(_T_360, UInt<1>(0h0)) when _T_361 : node _T_362 = eq(_T_359, UInt<1>(0h0)) when _T_362 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_46 assert(clock, _T_359, UInt<1>(0h1), "") : assert_46 node _T_363 = eq(before, UInt<3>(0h6)) node _T_364 = eq(after, UInt<3>(0h7)) node _T_365 = and(_T_363, _T_364) node _T_366 = eq(_T_365, UInt<1>(0h0)) node _T_367 = asUInt(reset) node _T_368 = eq(_T_367, UInt<1>(0h0)) when _T_368 : node _T_369 = eq(_T_366, UInt<1>(0h0)) when _T_369 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_47 assert(clock, _T_366, UInt<1>(0h1), "") : assert_47 node _T_370 = eq(before, UInt<3>(0h6)) node _T_371 = eq(after, UInt<3>(0h5)) node _T_372 = and(_T_370, _T_371) node _T_373 = eq(_T_372, UInt<1>(0h0)) node _T_374 = asUInt(reset) node _T_375 = eq(_T_374, UInt<1>(0h0)) when _T_375 : node _T_376 = eq(_T_373, UInt<1>(0h0)) when _T_376 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_48 assert(clock, _T_373, UInt<1>(0h1), "") : assert_48 node _T_377 = eq(before, UInt<3>(0h6)) node _T_378 = eq(after, UInt<3>(0h4)) node _T_379 = and(_T_377, _T_378) node _T_380 = eq(_T_379, UInt<1>(0h0)) node _T_381 = asUInt(reset) node _T_382 = eq(_T_381, UInt<1>(0h0)) when _T_382 : node _T_383 = eq(_T_380, UInt<1>(0h0)) when _T_383 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_49 assert(clock, _T_380, UInt<1>(0h1), "") : assert_49 node _T_384 = eq(before, UInt<3>(0h6)) node _T_385 = eq(after, UInt<2>(0h3)) node _T_386 = and(_T_384, _T_385) node _T_387 = eq(_T_386, UInt<1>(0h0)) node _T_388 = asUInt(reset) node _T_389 = eq(_T_388, UInt<1>(0h0)) when _T_389 : node _T_390 = eq(_T_387, UInt<1>(0h0)) when _T_390 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_50 assert(clock, _T_387, UInt<1>(0h1), "") : assert_50 node _T_391 = eq(before, UInt<3>(0h6)) node _T_392 = eq(after, UInt<2>(0h2)) node _T_393 = and(_T_391, _T_392) node _T_394 = eq(before, UInt<3>(0h4)) node _T_395 = eq(after, UInt<4>(0h8)) node _T_396 = and(_T_394, _T_395) node _T_397 = eq(_T_396, UInt<1>(0h0)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_51 assert(clock, _T_397, UInt<1>(0h1), "") : assert_51 node _T_401 = eq(before, UInt<3>(0h4)) node _T_402 = eq(after, UInt<1>(0h1)) node _T_403 = and(_T_401, _T_402) node _T_404 = eq(_T_403, UInt<1>(0h0)) node _T_405 = asUInt(reset) node _T_406 = eq(_T_405, UInt<1>(0h0)) when _T_406 : node _T_407 = eq(_T_404, UInt<1>(0h0)) when _T_407 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_52 assert(clock, _T_404, UInt<1>(0h1), "") : assert_52 node _T_408 = eq(before, UInt<3>(0h4)) node _T_409 = eq(after, UInt<1>(0h0)) node _T_410 = and(_T_408, _T_409) node _T_411 = eq(_T_410, UInt<1>(0h0)) node _T_412 = asUInt(reset) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(_T_411, UInt<1>(0h0)) when _T_414 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_53 assert(clock, _T_411, UInt<1>(0h1), "") : assert_53 node _T_415 = eq(before, UInt<3>(0h4)) node _T_416 = eq(after, UInt<3>(0h7)) node _T_417 = and(_T_415, _T_416) node _T_418 = eq(_T_417, UInt<1>(0h0)) node _T_419 = asUInt(reset) node _T_420 = eq(_T_419, UInt<1>(0h0)) when _T_420 : node _T_421 = eq(_T_418, UInt<1>(0h0)) when _T_421 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_54 assert(clock, _T_418, UInt<1>(0h1), "") : assert_54 node _T_422 = eq(before, UInt<3>(0h4)) node _T_423 = eq(after, UInt<3>(0h5)) node _T_424 = and(_T_422, _T_423) node _T_425 = eq(_T_424, UInt<1>(0h0)) node _T_426 = asUInt(reset) node _T_427 = eq(_T_426, UInt<1>(0h0)) when _T_427 : node _T_428 = eq(_T_425, UInt<1>(0h0)) when _T_428 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_55 assert(clock, _T_425, UInt<1>(0h1), "") : assert_55 node _T_429 = eq(before, UInt<3>(0h4)) node _T_430 = eq(after, UInt<3>(0h6)) node _T_431 = and(_T_429, _T_430) node _T_432 = eq(before, UInt<3>(0h4)) node _T_433 = eq(after, UInt<2>(0h3)) node _T_434 = and(_T_432, _T_433) node _T_435 = eq(_T_434, UInt<1>(0h0)) node _T_436 = asUInt(reset) node _T_437 = eq(_T_436, UInt<1>(0h0)) when _T_437 : node _T_438 = eq(_T_435, UInt<1>(0h0)) when _T_438 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_56 assert(clock, _T_435, UInt<1>(0h1), "") : assert_56 node _T_439 = eq(before, UInt<3>(0h4)) node _T_440 = eq(after, UInt<2>(0h2)) node _T_441 = and(_T_439, _T_440) node _T_442 = eq(before, UInt<2>(0h3)) node _T_443 = eq(after, UInt<4>(0h8)) node _T_444 = and(_T_442, _T_443) node _T_445 = eq(_T_444, UInt<1>(0h0)) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_57 assert(clock, _T_445, UInt<1>(0h1), "") : assert_57 node _T_449 = eq(before, UInt<2>(0h3)) node _T_450 = eq(after, UInt<1>(0h1)) node _T_451 = and(_T_449, _T_450) node _T_452 = eq(_T_451, UInt<1>(0h0)) node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(_T_452, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_58 assert(clock, _T_452, UInt<1>(0h1), "") : assert_58 node _T_456 = eq(before, UInt<2>(0h3)) node _T_457 = eq(after, UInt<1>(0h0)) node _T_458 = and(_T_456, _T_457) node _T_459 = eq(_T_458, UInt<1>(0h0)) node _T_460 = asUInt(reset) node _T_461 = eq(_T_460, UInt<1>(0h0)) when _T_461 : node _T_462 = eq(_T_459, UInt<1>(0h0)) when _T_462 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_59 assert(clock, _T_459, UInt<1>(0h1), "") : assert_59 node _T_463 = eq(before, UInt<2>(0h3)) node _T_464 = eq(after, UInt<3>(0h7)) node _T_465 = and(_T_463, _T_464) node _T_466 = eq(before, UInt<2>(0h3)) node _T_467 = eq(after, UInt<3>(0h5)) node _T_468 = and(_T_466, _T_467) node _T_469 = eq(before, UInt<2>(0h3)) node _T_470 = eq(after, UInt<3>(0h6)) node _T_471 = and(_T_469, _T_470) node _T_472 = eq(before, UInt<2>(0h3)) node _T_473 = eq(after, UInt<3>(0h4)) node _T_474 = and(_T_472, _T_473) node _T_475 = eq(before, UInt<2>(0h3)) node _T_476 = eq(after, UInt<2>(0h2)) node _T_477 = and(_T_475, _T_476) node _T_478 = eq(before, UInt<2>(0h2)) node _T_479 = eq(after, UInt<4>(0h8)) node _T_480 = and(_T_478, _T_479) node _T_481 = eq(_T_480, UInt<1>(0h0)) node _T_482 = asUInt(reset) node _T_483 = eq(_T_482, UInt<1>(0h0)) when _T_483 : node _T_484 = eq(_T_481, UInt<1>(0h0)) when _T_484 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_60 assert(clock, _T_481, UInt<1>(0h1), "") : assert_60 node _T_485 = eq(before, UInt<2>(0h2)) node _T_486 = eq(after, UInt<1>(0h1)) node _T_487 = and(_T_485, _T_486) node _T_488 = eq(_T_487, UInt<1>(0h0)) node _T_489 = asUInt(reset) node _T_490 = eq(_T_489, UInt<1>(0h0)) when _T_490 : node _T_491 = eq(_T_488, UInt<1>(0h0)) when _T_491 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_61 assert(clock, _T_488, UInt<1>(0h1), "") : assert_61 node _T_492 = eq(before, UInt<2>(0h2)) node _T_493 = eq(after, UInt<1>(0h0)) node _T_494 = and(_T_492, _T_493) node _T_495 = eq(_T_494, UInt<1>(0h0)) node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_T_495, UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_62 assert(clock, _T_495, UInt<1>(0h1), "") : assert_62 node _T_499 = eq(before, UInt<2>(0h2)) node _T_500 = eq(after, UInt<3>(0h7)) node _T_501 = and(_T_499, _T_500) node _T_502 = eq(_T_501, UInt<1>(0h0)) node _T_503 = asUInt(reset) node _T_504 = eq(_T_503, UInt<1>(0h0)) when _T_504 : node _T_505 = eq(_T_502, UInt<1>(0h0)) when _T_505 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_63 assert(clock, _T_502, UInt<1>(0h1), "") : assert_63 node _T_506 = eq(before, UInt<2>(0h2)) node _T_507 = eq(after, UInt<3>(0h5)) node _T_508 = and(_T_506, _T_507) node _T_509 = eq(_T_508, UInt<1>(0h0)) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_64 assert(clock, _T_509, UInt<1>(0h1), "") : assert_64 node _T_513 = eq(before, UInt<2>(0h2)) node _T_514 = eq(after, UInt<3>(0h6)) node _T_515 = and(_T_513, _T_514) node _T_516 = eq(before, UInt<2>(0h2)) node _T_517 = eq(after, UInt<3>(0h4)) node _T_518 = and(_T_516, _T_517) node _T_519 = eq(before, UInt<2>(0h2)) node _T_520 = eq(after, UInt<2>(0h3)) node _T_521 = and(_T_519, _T_520) node _T_522 = eq(_T_521, UInt<1>(0h0)) node _T_523 = asUInt(reset) node _T_524 = eq(_T_523, UInt<1>(0h0)) when _T_524 : node _T_525 = eq(_T_522, UInt<1>(0h0)) when _T_525 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_65 assert(clock, _T_522, UInt<1>(0h1), "") : assert_65 node probe_bit = eq(io.sinkc.bits.source, UInt<6>(0h28)) node _last_probe_T = or(probes_done, probe_bit) node _last_probe_T_1 = not(excluded_client) node _last_probe_T_2 = and(meta.clients, _last_probe_T_1) node last_probe = eq(_last_probe_T, _last_probe_T_2) node _probe_toN_T = eq(io.sinkc.bits.param, UInt<3>(0h1)) node _probe_toN_T_1 = eq(io.sinkc.bits.param, UInt<3>(0h2)) node _probe_toN_T_2 = or(_probe_toN_T, _probe_toN_T_1) node _probe_toN_T_3 = eq(io.sinkc.bits.param, UInt<3>(0h5)) node probe_toN = or(_probe_toN_T_2, _probe_toN_T_3) when io.sinkc.valid : node _T_526 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1)) node _T_527 = and(probe_toN, _T_526) node _T_528 = eq(probe_toN, UInt<1>(0h0)) node _T_529 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1)) node _T_530 = and(_T_528, _T_529) node _probes_done_T = or(probes_done, probe_bit) connect probes_done, _probes_done_T node _probes_toN_T = mux(probe_toN, probe_bit, UInt<1>(0h0)) node _probes_toN_T_1 = or(probes_toN, _probes_toN_T) connect probes_toN, _probes_toN_T_1 node _probes_noT_T = neq(io.sinkc.bits.param, UInt<3>(0h3)) node _probes_noT_T_1 = or(probes_noT, _probes_noT_T) connect probes_noT, _probes_noT_T_1 node _w_rprobeackfirst_T = or(w_rprobeackfirst, last_probe) connect w_rprobeackfirst, _w_rprobeackfirst_T node _w_rprobeacklast_T = and(last_probe, io.sinkc.bits.last) node _w_rprobeacklast_T_1 = or(w_rprobeacklast, _w_rprobeacklast_T) connect w_rprobeacklast, _w_rprobeacklast_T_1 node _w_pprobeackfirst_T = or(w_pprobeackfirst, last_probe) connect w_pprobeackfirst, _w_pprobeackfirst_T node _w_pprobeacklast_T = and(last_probe, io.sinkc.bits.last) node _w_pprobeacklast_T_1 = or(w_pprobeacklast, _w_pprobeacklast_T) connect w_pprobeacklast, _w_pprobeacklast_T_1 node _set_pprobeack_T = eq(request.offset, UInt<1>(0h0)) node _set_pprobeack_T_1 = or(io.sinkc.bits.last, _set_pprobeack_T) node set_pprobeack = and(last_probe, _set_pprobeack_T_1) node _w_pprobeack_T = or(w_pprobeack, set_pprobeack) connect w_pprobeack, _w_pprobeack_T node _T_531 = eq(set_pprobeack, UInt<1>(0h0)) node _T_532 = and(_T_531, w_rprobeackfirst) node _T_533 = and(set_pprobeack, w_rprobeackfirst) node _T_534 = neq(meta.state, UInt<2>(0h0)) node _T_535 = eq(io.sinkc.bits.tag, meta.tag) node _T_536 = and(_T_534, _T_535) node _T_537 = and(_T_536, io.sinkc.bits.data) when _T_537 : connect meta.dirty, UInt<1>(0h1) when io.sinkd.valid : node _T_538 = eq(io.sinkd.bits.opcode, UInt<3>(0h4)) node _T_539 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_540 = or(_T_538, _T_539) when _T_540 : connect sink, io.sinkd.bits.sink connect w_grantfirst, UInt<1>(0h1) connect w_grantlast, io.sinkd.bits.last connect bad_grant, io.sinkd.bits.denied node _w_grant_T = eq(request.offset, UInt<1>(0h0)) node _w_grant_T_1 = or(_w_grant_T, io.sinkd.bits.last) connect w_grant, _w_grant_T_1 node _T_541 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_542 = eq(request.offset, UInt<1>(0h0)) node _T_543 = and(_T_541, _T_542) node _T_544 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_545 = neq(request.offset, UInt<1>(0h0)) node _T_546 = and(_T_544, _T_545) node _gotT_T = eq(io.sinkd.bits.param, UInt<2>(0h0)) connect gotT, _gotT_T else : node _T_547 = eq(io.sinkd.bits.opcode, UInt<3>(0h6)) when _T_547 : connect w_releaseack, UInt<1>(0h1) when io.sinke.valid : connect w_grantack, UInt<1>(0h1) wire allocate_as_full : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>} connect allocate_as_full.set, io.allocate.bits.set connect allocate_as_full.put, io.allocate.bits.put connect allocate_as_full.offset, io.allocate.bits.offset connect allocate_as_full.tag, io.allocate.bits.tag connect allocate_as_full.source, io.allocate.bits.source connect allocate_as_full.size, io.allocate.bits.size connect allocate_as_full.param, io.allocate.bits.param connect allocate_as_full.opcode, io.allocate.bits.opcode connect allocate_as_full.control, io.allocate.bits.control connect allocate_as_full.prio, io.allocate.bits.prio node _new_meta_T = and(io.allocate.valid, io.allocate.bits.repeat) node new_meta = mux(_new_meta_T, final_meta_writeback, io.directory.bits) node new_request = mux(io.allocate.valid, allocate_as_full, request) node _new_needT_T = bits(new_request.opcode, 2, 2) node _new_needT_T_1 = eq(_new_needT_T, UInt<1>(0h0)) node _new_needT_T_2 = eq(new_request.opcode, UInt<3>(0h5)) node _new_needT_T_3 = eq(new_request.param, UInt<1>(0h1)) node _new_needT_T_4 = and(_new_needT_T_2, _new_needT_T_3) node _new_needT_T_5 = or(_new_needT_T_1, _new_needT_T_4) node _new_needT_T_6 = eq(new_request.opcode, UInt<3>(0h6)) node _new_needT_T_7 = eq(new_request.opcode, UInt<3>(0h7)) node _new_needT_T_8 = or(_new_needT_T_6, _new_needT_T_7) node _new_needT_T_9 = neq(new_request.param, UInt<2>(0h0)) node _new_needT_T_10 = and(_new_needT_T_8, _new_needT_T_9) node new_needT = or(_new_needT_T_5, _new_needT_T_10) node new_clientBit = eq(new_request.source, UInt<6>(0h28)) node _new_skipProbe_T = eq(new_request.opcode, UInt<3>(0h6)) node _new_skipProbe_T_1 = eq(new_request.opcode, UInt<3>(0h7)) node _new_skipProbe_T_2 = or(_new_skipProbe_T, _new_skipProbe_T_1) node _new_skipProbe_T_3 = eq(new_request.opcode, UInt<3>(0h4)) node _new_skipProbe_T_4 = or(_new_skipProbe_T_2, _new_skipProbe_T_3) node _new_skipProbe_T_5 = eq(new_request.opcode, UInt<3>(0h5)) node _new_skipProbe_T_6 = and(_new_skipProbe_T_5, UInt<1>(0h0)) node _new_skipProbe_T_7 = or(_new_skipProbe_T_4, _new_skipProbe_T_6) node new_skipProbe = mux(_new_skipProbe_T_7, new_clientBit, UInt<1>(0h0)) wire prior : UInt connect prior, UInt<1>(0h0) node prior_c = orr(final_meta_writeback.clients) node _prior_T = eq(UInt<2>(0h1), final_meta_writeback.state) when _prior_T : node _prior_out_T = mux(prior_c, UInt<1>(0h0), UInt<1>(0h1)) connect prior, _prior_out_T else : node _prior_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state) when _prior_T_1 : node _prior_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect prior, _prior_out_T_1 else : node _prior_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state) when _prior_T_2 : node _prior_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _prior_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _prior_out_T_4 = mux(prior_c, _prior_out_T_2, _prior_out_T_3) connect prior, _prior_out_T_4 else : node _prior_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state) when _prior_T_3 : connect prior, UInt<4>(0h8) node _prior_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) when _prior_T_4 : connect prior, UInt<4>(0h8) node _T_548 = and(io.allocate.valid, io.allocate.bits.repeat) when _T_548 : node _T_549 = eq(prior, UInt<4>(0h8)) node _T_550 = eq(prior, UInt<1>(0h1)) node _T_551 = eq(_T_550, UInt<1>(0h0)) node _T_552 = asUInt(reset) node _T_553 = eq(_T_552, UInt<1>(0h0)) when _T_553 : node _T_554 = eq(_T_551, UInt<1>(0h0)) when _T_554 : printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_66 assert(clock, _T_551, UInt<1>(0h1), "") : assert_66 node _T_555 = eq(prior, UInt<1>(0h0)) node _T_556 = eq(_T_555, UInt<1>(0h0)) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_67 assert(clock, _T_556, UInt<1>(0h1), "") : assert_67 node _T_560 = eq(prior, UInt<3>(0h7)) node _T_561 = eq(prior, UInt<3>(0h5)) node _T_562 = eq(prior, UInt<3>(0h4)) node _T_563 = eq(prior, UInt<3>(0h6)) node _T_564 = eq(prior, UInt<2>(0h3)) node _T_565 = eq(prior, UInt<2>(0h2)) when io.allocate.valid : node _T_566 = eq(request_valid, UInt<1>(0h0)) node _T_567 = and(io.schedule.ready, io.schedule.valid) node _T_568 = and(no_wait, _T_567) node _T_569 = or(_T_566, _T_568) node _T_570 = asUInt(reset) node _T_571 = eq(_T_570, UInt<1>(0h0)) when _T_571 : node _T_572 = eq(_T_569, UInt<1>(0h0)) when _T_572 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:533 assert (!request_valid \|\| (no_wait && io.schedule.fire))\n") : printf_68 assert(clock, _T_569, UInt<1>(0h1), "") : assert_68 connect request_valid, UInt<1>(0h1) connect request.set, io.allocate.bits.set connect request.put, io.allocate.bits.put connect request.offset, io.allocate.bits.offset connect request.tag, io.allocate.bits.tag connect request.source, io.allocate.bits.source connect request.size, io.allocate.bits.size connect request.param, io.allocate.bits.param connect request.opcode, io.allocate.bits.opcode connect request.control, io.allocate.bits.control connect request.prio, io.allocate.bits.prio node _T_573 = and(io.allocate.valid, io.allocate.bits.repeat) node _T_574 = or(io.directory.valid, _T_573) when _T_574 : connect meta_valid, UInt<1>(0h1) connect meta, new_meta connect probes_done, UInt<1>(0h0) connect probes_toN, UInt<1>(0h0) connect probes_noT, UInt<1>(0h0) connect gotT, UInt<1>(0h0) connect bad_grant, UInt<1>(0h0) connect s_rprobe, UInt<1>(0h1) connect w_rprobeackfirst, UInt<1>(0h1) connect w_rprobeacklast, UInt<1>(0h1) connect s_release, UInt<1>(0h1) connect w_releaseack, UInt<1>(0h1) connect s_pprobe, UInt<1>(0h1) connect s_acquire, UInt<1>(0h1) connect s_flush, UInt<1>(0h1) connect w_grantfirst, UInt<1>(0h1) connect w_grantlast, UInt<1>(0h1) connect w_grant, UInt<1>(0h1) connect w_pprobeackfirst, UInt<1>(0h1) connect w_pprobeacklast, UInt<1>(0h1) connect w_pprobeack, UInt<1>(0h1) connect s_probeack, UInt<1>(0h1) connect s_grantack, UInt<1>(0h1) connect s_execute, UInt<1>(0h1) connect w_grantack, UInt<1>(0h1) connect s_writeback, UInt<1>(0h1) node _T_575 = and(new_request.prio[2], UInt<1>(0h1)) when _T_575 : connect s_execute, UInt<1>(0h0) node _T_576 = bits(new_request.opcode, 0, 0) node _T_577 = eq(new_meta.dirty, UInt<1>(0h0)) node _T_578 = and(_T_576, _T_577) when _T_578 : connect s_writeback, UInt<1>(0h0) node _T_579 = eq(new_request.param, UInt<3>(0h0)) node _T_580 = eq(new_request.param, UInt<3>(0h4)) node _T_581 = or(_T_579, _T_580) node _T_582 = eq(new_meta.state, UInt<2>(0h2)) node _T_583 = and(_T_581, _T_582) when _T_583 : connect s_writeback, UInt<1>(0h0) node _T_584 = eq(new_request.param, UInt<3>(0h1)) node _T_585 = eq(new_request.param, UInt<3>(0h2)) node _T_586 = or(_T_584, _T_585) node _T_587 = eq(new_request.param, UInt<3>(0h5)) node _T_588 = or(_T_586, _T_587) node _T_589 = and(new_meta.clients, new_clientBit) node _T_590 = neq(_T_589, UInt<1>(0h0)) node _T_591 = and(_T_588, _T_590) when _T_591 : connect s_writeback, UInt<1>(0h0) node _T_592 = asUInt(reset) node _T_593 = eq(_T_592, UInt<1>(0h0)) when _T_593 : node _T_594 = eq(new_meta.hit, UInt<1>(0h0)) when _T_594 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:585 assert (new_meta.hit)\n") : printf_69 assert(clock, new_meta.hit, UInt<1>(0h1), "") : assert_69 else : node _T_595 = and(new_request.control, UInt<1>(0h1)) when _T_595 : connect s_flush, UInt<1>(0h0) when new_meta.hit : connect s_release, UInt<1>(0h0) connect w_releaseack, UInt<1>(0h0) node _T_596 = neq(new_meta.clients, UInt<1>(0h0)) node _T_597 = and(UInt<1>(0h1), _T_596) when _T_597 : connect s_rprobe, UInt<1>(0h0) connect w_rprobeackfirst, UInt<1>(0h0) connect w_rprobeacklast, UInt<1>(0h0) else : connect s_execute, UInt<1>(0h0) node _T_598 = eq(new_meta.hit, UInt<1>(0h0)) node _T_599 = neq(new_meta.state, UInt<2>(0h0)) node _T_600 = and(_T_598, _T_599) when _T_600 : connect s_release, UInt<1>(0h0) connect w_releaseack, UInt<1>(0h0) node _T_601 = neq(new_meta.clients, UInt<1>(0h0)) node _T_602 = and(UInt<1>(0h1), _T_601) when _T_602 : connect s_rprobe, UInt<1>(0h0) connect w_rprobeackfirst, UInt<1>(0h0) connect w_rprobeacklast, UInt<1>(0h0) node _T_603 = eq(new_meta.hit, UInt<1>(0h0)) node _T_604 = eq(new_meta.state, UInt<2>(0h1)) node _T_605 = and(_T_604, new_needT) node _T_606 = or(_T_603, _T_605) when _T_606 : connect s_acquire, UInt<1>(0h0) connect w_grantfirst, UInt<1>(0h0) connect w_grantlast, UInt<1>(0h0) connect w_grant, UInt<1>(0h0) connect s_grantack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_607 = eq(new_meta.state, UInt<2>(0h2)) node _T_608 = or(new_needT, _T_607) node _T_609 = and(new_meta.hit, _T_608) node _T_610 = not(new_skipProbe) node _T_611 = and(new_meta.clients, _T_610) node _T_612 = neq(_T_611, UInt<1>(0h0)) node _T_613 = and(_T_609, _T_612) node _T_614 = and(UInt<1>(0h1), _T_613) when _T_614 : connect s_pprobe, UInt<1>(0h0) connect w_pprobeackfirst, UInt<1>(0h0) connect w_pprobeacklast, UInt<1>(0h0) connect w_pprobeack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_615 = eq(new_request.opcode, UInt<3>(0h6)) node _T_616 = eq(new_request.opcode, UInt<3>(0h7)) node _T_617 = or(_T_615, _T_616) when _T_617 : connect w_grantack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_618 = bits(new_request.opcode, 2, 2) node _T_619 = eq(_T_618, UInt<1>(0h0)) node _T_620 = and(_T_619, new_meta.hit) node _T_621 = eq(new_meta.dirty, UInt<1>(0h0)) node _T_622 = and(_T_620, _T_621) when _T_622 : connect s_writeback, UInt<1>(0h0)	module MSHR_43( // @[MSHR.scala:84:7] input clock, // @[MSHR.scala:84:7] input reset, // @[MSHR.scala:84:7] input io_allocate_valid, // @[MSHR.scala:86:14] input io_allocate_bits_prio_0, // @[MSHR.scala:86:14] input io_allocate_bits_prio_1, // @[MSHR.scala:86:14] input io_allocate_bits_prio_2, // @[MSHR.scala:86:14] input io_allocate_bits_control, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_source, // @[MSHR.scala:86:14] input [8:0] io_allocate_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14] input [10:0] io_allocate_bits_set, // @[MSHR.scala:86:14] input io_allocate_bits_repeat, // @[MSHR.scala:86:14] input io_directory_valid, // @[MSHR.scala:86:14] input io_directory_bits_dirty, // @[MSHR.scala:86:14] input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14] input io_directory_bits_clients, // @[MSHR.scala:86:14] input [8:0] io_directory_bits_tag, // @[MSHR.scala:86:14] input io_directory_bits_hit, // @[MSHR.scala:86:14] input [3:0] io_directory_bits_way, // @[MSHR.scala:86:14] output io_status_valid, // @[MSHR.scala:86:14] output [10:0] io_status_bits_set, // @[MSHR.scala:86:14] output [8:0] io_status_bits_tag, // @[MSHR.scala:86:14] output [3:0] io_status_bits_way, // @[MSHR.scala:86:14] output io_status_bits_blockB, // @[MSHR.scala:86:14] output io_status_bits_nestB, // @[MSHR.scala:86:14] output io_status_bits_blockC, // @[MSHR.scala:86:14] output io_status_bits_nestC, // @[MSHR.scala:86:14] input io_schedule_ready, // @[MSHR.scala:86:14] output io_schedule_valid, // @[MSHR.scala:86:14] output io_schedule_bits_a_valid, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14] output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14] output io_schedule_bits_b_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14] output io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14] output io_schedule_bits_c_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14] output [3:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14] output io_schedule_bits_d_valid, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_0, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14] output [3:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14] output io_schedule_bits_e_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14] output io_schedule_bits_x_valid, // @[MSHR.scala:86:14] output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14] output [3:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14] output io_schedule_bits_reload, // @[MSHR.scala:86:14] input io_sinkc_valid, // @[MSHR.scala:86:14] input io_sinkc_bits_last, // @[MSHR.scala:86:14] input [10:0] io_sinkc_bits_set, // @[MSHR.scala:86:14] input [8:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_sinkc_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14] input io_sinkc_bits_data, // @[MSHR.scala:86:14] input io_sinkd_valid, // @[MSHR.scala:86:14] input io_sinkd_bits_last, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14] input [3:0] io_sinkd_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14] input io_sinkd_bits_denied, // @[MSHR.scala:86:14] input io_sinke_valid, // @[MSHR.scala:86:14] input [3:0] io_sinke_bits_sink, // @[MSHR.scala:86:14] input [10:0] io_nestedwb_set, // @[MSHR.scala:86:14] input [8:0] io_nestedwb_tag, // @[MSHR.scala:86:14] input io_nestedwb_b_toN, // @[MSHR.scala:86:14] input io_nestedwb_b_toB, // @[MSHR.scala:86:14] input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14] input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14] ); wire [8:0] final_meta_writeback_tag; // @[MSHR.scala:215:38] wire final_meta_writeback_clients; // @[MSHR.scala:215:38] wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38] wire final_meta_writeback_dirty; // @[MSHR.scala:215:38] wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_0_0 = io_allocate_bits_prio_0; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7] wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7] wire [8:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7] wire [10:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7] wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7] wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7] wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7] wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7] wire io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7] wire [8:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7] wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7] wire [3:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7] wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7] wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7] wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7] wire [10:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7] wire [8:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7] wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7] wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7] wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7] wire [3:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7] wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7] wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7] wire [3:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7] wire [10:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7] wire [8:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7] wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7] wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7] wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7] wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_a_bits_source = 4'h0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_c_bits_source = 4'h0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_d_bits_sink = 4'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7] wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68] wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80] wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21] wire invalid_clients = 1'h0; // @[MSHR.scala:268:21] wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137] wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11] wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137] wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11] wire [8:0] invalid_tag = 9'h0; // @[MSHR.scala:268:21] wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21] wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70] wire allocate_as_full_prio_0 = io_allocate_bits_prio_0_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34] wire [8:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34] wire [10:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34] wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40] wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93] wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28] wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39] wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105] wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55] wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91] wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41] wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41] wire [8:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41] wire _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51] wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64] wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41] wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41] wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57] wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41] wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43] wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40] wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66] wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41] wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41] wire _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41] wire [8:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41] wire no_wait; // @[MSHR.scala:183:83] wire [10:0] io_status_bits_set_0; // @[MSHR.scala:84:7] wire [8:0] io_status_bits_tag_0; // @[MSHR.scala:84:7] wire [3:0] io_status_bits_way_0; // @[MSHR.scala:84:7] wire io_status_bits_blockB_0; // @[MSHR.scala:84:7] wire io_status_bits_nestB_0; // @[MSHR.scala:84:7] wire io_status_bits_blockC_0; // @[MSHR.scala:84:7] wire io_status_bits_nestC_0; // @[MSHR.scala:84:7] wire io_status_valid_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_0_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7] wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7] wire io_schedule_valid_0; // @[MSHR.scala:84:7] reg request_valid; // @[MSHR.scala:97:30] assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30] reg request_prio_0; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_0_0 = request_prio_0; // @[MSHR.scala:84:7, :98:20] reg request_prio_1; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20] reg request_prio_2; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20] reg request_control; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_opcode; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_param; // @[MSHR.scala:98:20] reg [2:0] request_size; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_source; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20] reg [8:0] request_tag; // @[MSHR.scala:98:20] assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_offset; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_put; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20] reg [10:0] request_set; // @[MSHR.scala:98:20] assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] reg meta_valid; // @[MSHR.scala:99:27] reg meta_dirty; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17] reg [1:0] meta_state; // @[MSHR.scala:100:17] reg meta_clients; // @[MSHR.scala:100:17] wire _meta_no_clients_T = meta_clients; // @[MSHR.scala:100:17, :220:39] wire evict_c = meta_clients; // @[MSHR.scala:100:17, :315:27] wire before_c = meta_clients; // @[MSHR.scala:100:17, :315:27] reg [8:0] meta_tag; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17] reg meta_hit; // @[MSHR.scala:100:17] reg [3:0] meta_way; // @[MSHR.scala:100:17] assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] wire [3:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38] reg s_rprobe; // @[MSHR.scala:121:33] reg w_rprobeackfirst; // @[MSHR.scala:122:33] reg w_rprobeacklast; // @[MSHR.scala:123:33] reg s_release; // @[MSHR.scala:124:33] reg w_releaseack; // @[MSHR.scala:125:33] reg s_pprobe; // @[MSHR.scala:126:33] reg s_acquire; // @[MSHR.scala:127:33] reg s_flush; // @[MSHR.scala:128:33] reg w_grantfirst; // @[MSHR.scala:129:33] reg w_grantlast; // @[MSHR.scala:130:33] reg w_grant; // @[MSHR.scala:131:33] reg w_pprobeackfirst; // @[MSHR.scala:132:33] reg w_pprobeacklast; // @[MSHR.scala:133:33] reg w_pprobeack; // @[MSHR.scala:134:33] reg s_grantack; // @[MSHR.scala:136:33] reg s_execute; // @[MSHR.scala:137:33] reg w_grantack; // @[MSHR.scala:138:33] reg s_writeback; // @[MSHR.scala:139:33] reg [2:0] sink; // @[MSHR.scala:147:17] assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17] reg gotT; // @[MSHR.scala:148:17] reg bad_grant; // @[MSHR.scala:149:22] assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22] reg probes_done; // @[MSHR.scala:150:24] reg probes_toN; // @[MSHR.scala:151:23] reg probes_noT; // @[MSHR.scala:152:23] wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28] wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45] wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62] wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 \| _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}] wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82] wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 \| _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}] wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103] wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}] assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T \| _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}] assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40] wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39] wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}] wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}] wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96] assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}] assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93] assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28] assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28] wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43] wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64] wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T \| _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}] wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85] wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 \| _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}] assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}] assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39] wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33] wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}] wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}] assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}] assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83] wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31] wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}] assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}] assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55] wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31] wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44] assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T \| _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}] assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41] wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32] wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}] assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}] assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64] wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31] wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}] assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}] assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57] wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31] assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}] assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43] wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31] assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}] assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40] wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34] wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}] wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70] wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}] assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 \| _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}] assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66] wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 \| io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49] wire _io_schedule_valid_T_1 = _io_schedule_valid_T \| io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}] wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 \| io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}] wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 \| io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49] wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 \| io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}] assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 \| io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}] assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105] wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71] wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71] wire _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71] wire after_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire prior_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire [8:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71] wire final_meta_writeback_hit; // @[MSHR.scala:215:38] wire req_clientBit = request_source == 6'h28; // @[Parameters.scala:46:9] wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12] wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12] wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _req_needT_T_2; // @[Parameters.scala:270:13] assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13] wire _excluded_client_T_6; // @[Parameters.scala:279:117] assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117] wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42] wire _req_needT_T_3; // @[Parameters.scala:270:42] assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42] wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11] assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11] wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42] wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _req_needT_T_5 = _req_needT_T_1 \| _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _req_needT_T_6; // @[Parameters.scala:271:14] assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14] wire _req_acquire_T; // @[MSHR.scala:219:36] assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14] wire _excluded_client_T_1; // @[Parameters.scala:279:12] assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12] wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52] wire _req_needT_T_8 = _req_needT_T_6 \| _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _req_needT_T_9 = \|request_param; // @[Parameters.scala:271:89] wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire req_needT = _req_needT_T_5 \| _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52] wire req_acquire = _req_acquire_T \| _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}] wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}] wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81] wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}] wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}] wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}] wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65] wire _final_meta_writeback_dirty_T_1 = meta_dirty \| _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}] wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55] wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78] wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78] assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78] wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70] wire _evict_T_2; // @[MSHR.scala:317:26] assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _before_T_1; // @[MSHR.scala:317:26] assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}] wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}] wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43] assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43] wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T \| _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}] wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75] wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 \| _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}] wire _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 & req_clientBit; // @[Parameters.scala:46:9] wire _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}] wire _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}] wire _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54] wire _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}] wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45] wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}] wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 \| _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}] wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40] wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40] assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40] wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65] assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65] wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41] wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}] wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72] wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}] wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70] wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70] wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53] assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53] wire _evict_T_1; // @[MSHR.scala:317:26] assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire _before_T; // @[MSHR.scala:317:26] assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70] wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70] wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55] wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70] wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70] wire _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66] wire _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}] wire _final_meta_writeback_clients_T_12 = meta_hit & _final_meta_writeback_clients_T_11; // @[MSHR.scala:100:17, :245:{40,64}] wire _final_meta_writeback_clients_T_13 = req_acquire & req_clientBit; // @[Parameters.scala:46:9] wire _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 \| _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40] assign final_meta_writeback_tag = request_prio_2 \| request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30] wire _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54] wire _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}] assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 \| ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21] assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21] assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36] assign final_meta_writeback_clients = bad_grant ? meta_hit & _final_meta_writeback_clients_T_16 : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36] wire _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:46:9] wire _honour_BtoT_T_1 = _honour_BtoT_T; // @[MSHR.scala:276:{47,64}] wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}] wire _excluded_client_T = meta_hit & request_prio_0; // @[MSHR.scala:98:20, :100:17, :279:38] wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50] wire _excluded_client_T_3 = _excluded_client_T_1 \| _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}] wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _excluded_client_T_5 = _excluded_client_T_3 \| _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}] wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}] wire _excluded_client_T_9 = _excluded_client_T & _excluded_client_T_8; // @[Parameters.scala:279:106] wire excluded_client = _excluded_client_T_9 & req_clientBit; // @[Parameters.scala:46:9] wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56] wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70] assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}] wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51] wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55] wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52] wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 \| _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}] wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}] assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T \| _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38] assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91] wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42] wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70] wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}] assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}] assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41] wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42] assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}] assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41] wire _io_schedule_bits_b_bits_clients_T = ~excluded_client; // @[MSHR.scala:279:28, :289:53] assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients & _io_schedule_bits_b_bits_clients_T; // @[MSHR.scala:100:17, :289:{51,53}] assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51] assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41] assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41] assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}] assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41] wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42] wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53] wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53] wire _io_schedule_bits_d_bits_param_T_3 = ~(\|request_param); // @[Parameters.scala:271:89] wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53] wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53] wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79] assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41] wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42] assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_clients = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 9'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}] assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41] wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32] wire [3:0] evict; // @[MSHR.scala:314:26] wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32] wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32] wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32] assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32] assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39] wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39] assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39] assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76] wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76] assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76] assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _evict_T_4 = ~(\|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32] assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] before_0; // @[MSHR.scala:314:26] wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32] wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _before_T_3 = ~(\|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11] assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] after; // @[MSHR.scala:314:26] wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26] wire _after_T; // @[MSHR.scala:317:26] assign _after_T = _GEN_9; // @[MSHR.scala:317:26] wire _prior_T; // @[MSHR.scala:317:26] assign _prior_T = _GEN_9; // @[MSHR.scala:317:26] wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32] wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26] wire _after_T_1; // @[MSHR.scala:317:26] assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire _prior_T_1; // @[MSHR.scala:317:26] assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32] wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32] assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32] assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39] wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39] assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39] assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76] wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76] assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76] assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26] wire _after_T_3; // @[MSHR.scala:317:26] assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26] wire _prior_T_3; // @[MSHR.scala:317:26] assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26] assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire probe_bit = io_sinkc_bits_source_0 == 6'h28; // @[Parameters.scala:46:9] wire _GEN_15 = probes_done \| probe_bit; // @[Parameters.scala:46:9] wire _last_probe_T; // @[MSHR.scala:459:33] assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33] wire _probes_done_T; // @[MSHR.scala:467:32] assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32] wire _last_probe_T_1 = ~excluded_client; // @[MSHR.scala:279:28, :289:53, :459:66] wire _last_probe_T_2 = meta_clients & _last_probe_T_1; // @[MSHR.scala:100:17, :459:{64,66}] wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}] wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11] wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43] wire _probe_toN_T_2 = _probe_toN_T \| _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}] wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75] wire probe_toN = _probe_toN_T_2 \| _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}] wire _probes_toN_T = probe_toN & probe_bit; // @[Parameters.scala:46:9] wire _probes_toN_T_1 = probes_toN \| _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}] wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53] wire _probes_noT_T_1 = probes_noT \| _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}] wire _w_rprobeackfirst_T = w_rprobeackfirst \| last_probe; // @[MSHR.scala:122:33, :459:46, :470:42] wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55] wire _w_rprobeacklast_T; // @[MSHR.scala:471:55] assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55] wire _w_pprobeacklast_T; // @[MSHR.scala:473:55] assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55] wire _w_rprobeacklast_T_1 = w_rprobeacklast \| _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}] wire _w_pprobeackfirst_T = w_pprobeackfirst \| last_probe; // @[MSHR.scala:132:33, :459:46, :472:42] wire _w_pprobeacklast_T_1 = w_pprobeacklast \| _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}] wire _set_pprobeack_T = ~(\|request_offset); // @[MSHR.scala:98:20, :475:77] wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 \| _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}] wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}] wire _w_pprobeack_T = w_pprobeack \| set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32] wire _w_grant_T = ~(\|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33] wire _w_grant_T_1 = _w_grant_T \| io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}] wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35] wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40] wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [8:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [3:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_request_prio_0 = io_allocate_valid_0 ? allocate_as_full_prio_0 : request_prio_0; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [8:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [10:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12] wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _new_needT_T_2; // @[Parameters.scala:270:13] assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13] wire _new_skipProbe_T_5; // @[Parameters.scala:279:117] assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117] wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42] wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _new_needT_T_5 = _new_needT_T_1 \| _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _new_needT_T_6; // @[Parameters.scala:271:14] assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14] wire _new_skipProbe_T; // @[Parameters.scala:279:12] assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12] wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52] wire _new_needT_T_8 = _new_needT_T_6 \| _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _new_needT_T_9 = \|new_request_param; // @[Parameters.scala:271:89] wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire new_needT = _new_needT_T_5 \| _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire new_clientBit = new_request_source == 6'h28; // @[Parameters.scala:46:9] wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50] wire _new_skipProbe_T_2 = _new_skipProbe_T \| _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}] wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _new_skipProbe_T_4 = _new_skipProbe_T_2 \| _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}] wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}] wire new_skipProbe = _new_skipProbe_T_7 & new_clientBit; // @[Parameters.scala:46:9] wire [3:0] prior; // @[MSHR.scala:314:26] wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32] wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire _T_574 = io_directory_valid_0 \| _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28]
Generate the Verilog code corresponding to this FIRRTL code module RouteComputer_3 : input clock : Clock input reset : Reset output io : { req : { flip `2` : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}, flip `1` : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}, flip `0` : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}}, resp : { `2` : { vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[6]}}, `1` : { vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[6]}}, `0` : { vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[6]}}}} connect io.req.`0`.ready, UInt<1>(0h1) node addr_lo = cat(io.req.`0`.bits.flow.egress_node, io.req.`0`.bits.flow.egress_node_id) node addr_hi_hi = cat(io.req.`0`.bits.flow.vnet_id, io.req.`0`.bits.flow.ingress_node) node addr_hi = cat(addr_hi_hi, io.req.`0`.bits.flow.ingress_node_id) node _addr_T = cat(addr_hi, addr_lo) node addr = cat(io.req.`0`.bits.src_virt_id, _addr_T) wire decoded_plaInput : UInt<17> node decoded_invInputs = not(decoded_plaInput) wire decoded_plaOutput : UInt<6> node decoded_andMatrixOutputs_andMatrixInput_0 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2 = bits(decoded_invInputs, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_4 = bits(decoded_plaInput, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_5 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_6 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_7 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_lo_lo = cat(decoded_andMatrixOutputs_andMatrixInput_6, decoded_andMatrixOutputs_andMatrixInput_7) node decoded_andMatrixOutputs_lo_hi = cat(decoded_andMatrixOutputs_andMatrixInput_4, decoded_andMatrixOutputs_andMatrixInput_5) node decoded_andMatrixOutputs_lo = cat(decoded_andMatrixOutputs_lo_hi, decoded_andMatrixOutputs_lo_lo) node decoded_andMatrixOutputs_hi_lo = cat(decoded_andMatrixOutputs_andMatrixInput_2, decoded_andMatrixOutputs_andMatrixInput_3) node decoded_andMatrixOutputs_hi_hi = cat(decoded_andMatrixOutputs_andMatrixInput_0, decoded_andMatrixOutputs_andMatrixInput_1) node decoded_andMatrixOutputs_hi = cat(decoded_andMatrixOutputs_hi_hi, decoded_andMatrixOutputs_hi_lo) node _decoded_andMatrixOutputs_T = cat(decoded_andMatrixOutputs_hi, decoded_andMatrixOutputs_lo) node decoded_andMatrixOutputs_21_2 = andr(_decoded_andMatrixOutputs_T) node decoded_andMatrixOutputs_andMatrixInput_0_1 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_1 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_1 = bits(decoded_invInputs, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_1 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_4_1 = bits(decoded_plaInput, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_5_1 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_6_1 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_7_1 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_lo_lo_1 = cat(decoded_andMatrixOutputs_andMatrixInput_6_1, decoded_andMatrixOutputs_andMatrixInput_7_1) node decoded_andMatrixOutputs_lo_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_4_1, decoded_andMatrixOutputs_andMatrixInput_5_1) node decoded_andMatrixOutputs_lo_1 = cat(decoded_andMatrixOutputs_lo_hi_1, decoded_andMatrixOutputs_lo_lo_1) node decoded_andMatrixOutputs_hi_lo_1 = cat(decoded_andMatrixOutputs_andMatrixInput_2_1, decoded_andMatrixOutputs_andMatrixInput_3_1) node decoded_andMatrixOutputs_hi_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_0_1, decoded_andMatrixOutputs_andMatrixInput_1_1) node decoded_andMatrixOutputs_hi_1 = cat(decoded_andMatrixOutputs_hi_hi_1, decoded_andMatrixOutputs_hi_lo_1) node _decoded_andMatrixOutputs_T_1 = cat(decoded_andMatrixOutputs_hi_1, decoded_andMatrixOutputs_lo_1) node decoded_andMatrixOutputs_1_2 = andr(_decoded_andMatrixOutputs_T_1) node decoded_andMatrixOutputs_andMatrixInput_0_2 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_2 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_2 = bits(decoded_plaInput, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_2 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_4_2 = bits(decoded_plaInput, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_5_2 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_6_2 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_7_2 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_lo_lo_2 = cat(decoded_andMatrixOutputs_andMatrixInput_6_2, decoded_andMatrixOutputs_andMatrixInput_7_2) node decoded_andMatrixOutputs_lo_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_4_2, decoded_andMatrixOutputs_andMatrixInput_5_2) node decoded_andMatrixOutputs_lo_2 = cat(decoded_andMatrixOutputs_lo_hi_2, decoded_andMatrixOutputs_lo_lo_2) node decoded_andMatrixOutputs_hi_lo_2 = cat(decoded_andMatrixOutputs_andMatrixInput_2_2, decoded_andMatrixOutputs_andMatrixInput_3_2) node decoded_andMatrixOutputs_hi_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_0_2, decoded_andMatrixOutputs_andMatrixInput_1_2) node decoded_andMatrixOutputs_hi_2 = cat(decoded_andMatrixOutputs_hi_hi_2, decoded_andMatrixOutputs_hi_lo_2) node _decoded_andMatrixOutputs_T_2 = cat(decoded_andMatrixOutputs_hi_2, decoded_andMatrixOutputs_lo_2) node decoded_andMatrixOutputs_6_2 = andr(_decoded_andMatrixOutputs_T_2) node decoded_andMatrixOutputs_andMatrixInput_0_3 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_3 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_3 = bits(decoded_plaInput, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_3 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_4_3 = bits(decoded_plaInput, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_5_3 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_6_3 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_7_3 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_lo_lo_3 = cat(decoded_andMatrixOutputs_andMatrixInput_6_3, decoded_andMatrixOutputs_andMatrixInput_7_3) node decoded_andMatrixOutputs_lo_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_4_3, decoded_andMatrixOutputs_andMatrixInput_5_3) node decoded_andMatrixOutputs_lo_3 = cat(decoded_andMatrixOutputs_lo_hi_3, decoded_andMatrixOutputs_lo_lo_3) node decoded_andMatrixOutputs_hi_lo_3 = cat(decoded_andMatrixOutputs_andMatrixInput_2_3, decoded_andMatrixOutputs_andMatrixInput_3_3) node decoded_andMatrixOutputs_hi_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_0_3, decoded_andMatrixOutputs_andMatrixInput_1_3) node decoded_andMatrixOutputs_hi_3 = cat(decoded_andMatrixOutputs_hi_hi_3, decoded_andMatrixOutputs_hi_lo_3) node _decoded_andMatrixOutputs_T_3 = cat(decoded_andMatrixOutputs_hi_3, decoded_andMatrixOutputs_lo_3) node decoded_andMatrixOutputs_0_2 = andr(_decoded_andMatrixOutputs_T_3) node decoded_andMatrixOutputs_andMatrixInput_0_4 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_4 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_4 = bits(decoded_invInputs, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_3_4 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_4_4 = bits(decoded_plaInput, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_5_4 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_6_4 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_7_4 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8 = bits(decoded_plaInput, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_11 = bits(decoded_invInputs, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_12 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_lo_lo_hi = cat(decoded_andMatrixOutputs_andMatrixInput_10, decoded_andMatrixOutputs_andMatrixInput_11) node decoded_andMatrixOutputs_lo_lo_4 = cat(decoded_andMatrixOutputs_lo_lo_hi, decoded_andMatrixOutputs_andMatrixInput_12) node decoded_andMatrixOutputs_lo_hi_hi = cat(decoded_andMatrixOutputs_andMatrixInput_7_4, decoded_andMatrixOutputs_andMatrixInput_8) node decoded_andMatrixOutputs_lo_hi_4 = cat(decoded_andMatrixOutputs_lo_hi_hi, decoded_andMatrixOutputs_andMatrixInput_9) node decoded_andMatrixOutputs_lo_4 = cat(decoded_andMatrixOutputs_lo_hi_4, decoded_andMatrixOutputs_lo_lo_4) node decoded_andMatrixOutputs_hi_lo_hi = cat(decoded_andMatrixOutputs_andMatrixInput_4_4, decoded_andMatrixOutputs_andMatrixInput_5_4) node decoded_andMatrixOutputs_hi_lo_4 = cat(decoded_andMatrixOutputs_hi_lo_hi, decoded_andMatrixOutputs_andMatrixInput_6_4) node decoded_andMatrixOutputs_hi_hi_lo = cat(decoded_andMatrixOutputs_andMatrixInput_2_4, decoded_andMatrixOutputs_andMatrixInput_3_4) node decoded_andMatrixOutputs_hi_hi_hi = cat(decoded_andMatrixOutputs_andMatrixInput_0_4, decoded_andMatrixOutputs_andMatrixInput_1_4) node decoded_andMatrixOutputs_hi_hi_4 = cat(decoded_andMatrixOutputs_hi_hi_hi, decoded_andMatrixOutputs_hi_hi_lo) node decoded_andMatrixOutputs_hi_4 = cat(decoded_andMatrixOutputs_hi_hi_4, decoded_andMatrixOutputs_hi_lo_4) node _decoded_andMatrixOutputs_T_4 = cat(decoded_andMatrixOutputs_hi_4, decoded_andMatrixOutputs_lo_4) node decoded_andMatrixOutputs_20_2 = andr(_decoded_andMatrixOutputs_T_4) node decoded_andMatrixOutputs_andMatrixInput_0_5 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_5 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_5 = bits(decoded_invInputs, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_3_5 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_4_5 = bits(decoded_plaInput, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_5_5 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_6_5 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_7_5 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8_1 = bits(decoded_plaInput, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9_1 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10_1 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_11_1 = bits(decoded_invInputs, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_12_1 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_lo_lo_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_10_1, decoded_andMatrixOutputs_andMatrixInput_11_1) node decoded_andMatrixOutputs_lo_lo_5 = cat(decoded_andMatrixOutputs_lo_lo_hi_1, decoded_andMatrixOutputs_andMatrixInput_12_1) node decoded_andMatrixOutputs_lo_hi_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_7_5, decoded_andMatrixOutputs_andMatrixInput_8_1) node decoded_andMatrixOutputs_lo_hi_5 = cat(decoded_andMatrixOutputs_lo_hi_hi_1, decoded_andMatrixOutputs_andMatrixInput_9_1) node decoded_andMatrixOutputs_lo_5 = cat(decoded_andMatrixOutputs_lo_hi_5, decoded_andMatrixOutputs_lo_lo_5) node decoded_andMatrixOutputs_hi_lo_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_4_5, decoded_andMatrixOutputs_andMatrixInput_5_5) node decoded_andMatrixOutputs_hi_lo_5 = cat(decoded_andMatrixOutputs_hi_lo_hi_1, decoded_andMatrixOutputs_andMatrixInput_6_5) node decoded_andMatrixOutputs_hi_hi_lo_1 = cat(decoded_andMatrixOutputs_andMatrixInput_2_5, decoded_andMatrixOutputs_andMatrixInput_3_5) node decoded_andMatrixOutputs_hi_hi_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_0_5, decoded_andMatrixOutputs_andMatrixInput_1_5) node decoded_andMatrixOutputs_hi_hi_5 = cat(decoded_andMatrixOutputs_hi_hi_hi_1, decoded_andMatrixOutputs_hi_hi_lo_1) node decoded_andMatrixOutputs_hi_5 = cat(decoded_andMatrixOutputs_hi_hi_5, decoded_andMatrixOutputs_hi_lo_5) node _decoded_andMatrixOutputs_T_5 = cat(decoded_andMatrixOutputs_hi_5, decoded_andMatrixOutputs_lo_5) node decoded_andMatrixOutputs_29_2 = andr(_decoded_andMatrixOutputs_T_5) node decoded_andMatrixOutputs_andMatrixInput_0_6 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_6 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_6 = bits(decoded_plaInput, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_6 = bits(decoded_invInputs, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_6 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_6 = bits(decoded_invInputs, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_6 = bits(decoded_plaInput, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_6 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8_2 = bits(decoded_plaInput, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9_2 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10_2 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_11_2 = bits(decoded_invInputs, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_12_2 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_lo_lo_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_10_2, decoded_andMatrixOutputs_andMatrixInput_11_2) node decoded_andMatrixOutputs_lo_lo_6 = cat(decoded_andMatrixOutputs_lo_lo_hi_2, decoded_andMatrixOutputs_andMatrixInput_12_2) node decoded_andMatrixOutputs_lo_hi_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_7_6, decoded_andMatrixOutputs_andMatrixInput_8_2) node decoded_andMatrixOutputs_lo_hi_6 = cat(decoded_andMatrixOutputs_lo_hi_hi_2, decoded_andMatrixOutputs_andMatrixInput_9_2) node decoded_andMatrixOutputs_lo_6 = cat(decoded_andMatrixOutputs_lo_hi_6, decoded_andMatrixOutputs_lo_lo_6) node decoded_andMatrixOutputs_hi_lo_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_4_6, decoded_andMatrixOutputs_andMatrixInput_5_6) node decoded_andMatrixOutputs_hi_lo_6 = cat(decoded_andMatrixOutputs_hi_lo_hi_2, decoded_andMatrixOutputs_andMatrixInput_6_6) node decoded_andMatrixOutputs_hi_hi_lo_2 = cat(decoded_andMatrixOutputs_andMatrixInput_2_6, decoded_andMatrixOutputs_andMatrixInput_3_6) node decoded_andMatrixOutputs_hi_hi_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_0_6, decoded_andMatrixOutputs_andMatrixInput_1_6) node decoded_andMatrixOutputs_hi_hi_6 = cat(decoded_andMatrixOutputs_hi_hi_hi_2, decoded_andMatrixOutputs_hi_hi_lo_2) node decoded_andMatrixOutputs_hi_6 = cat(decoded_andMatrixOutputs_hi_hi_6, decoded_andMatrixOutputs_hi_lo_6) node _decoded_andMatrixOutputs_T_6 = cat(decoded_andMatrixOutputs_hi_6, decoded_andMatrixOutputs_lo_6) node decoded_andMatrixOutputs_7_2 = andr(_decoded_andMatrixOutputs_T_6) node decoded_andMatrixOutputs_andMatrixInput_0_7 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_7 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_7 = bits(decoded_plaInput, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_7 = bits(decoded_invInputs, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_7 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_7 = bits(decoded_invInputs, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_7 = bits(decoded_plaInput, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_7 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8_3 = bits(decoded_plaInput, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9_3 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10_3 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_11_3 = bits(decoded_invInputs, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_12_3 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_lo_lo_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_10_3, decoded_andMatrixOutputs_andMatrixInput_11_3) node decoded_andMatrixOutputs_lo_lo_7 = cat(decoded_andMatrixOutputs_lo_lo_hi_3, decoded_andMatrixOutputs_andMatrixInput_12_3) node decoded_andMatrixOutputs_lo_hi_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_7_7, decoded_andMatrixOutputs_andMatrixInput_8_3) node decoded_andMatrixOutputs_lo_hi_7 = cat(decoded_andMatrixOutputs_lo_hi_hi_3, decoded_andMatrixOutputs_andMatrixInput_9_3) node decoded_andMatrixOutputs_lo_7 = cat(decoded_andMatrixOutputs_lo_hi_7, decoded_andMatrixOutputs_lo_lo_7) node decoded_andMatrixOutputs_hi_lo_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_4_7, decoded_andMatrixOutputs_andMatrixInput_5_7) node decoded_andMatrixOutputs_hi_lo_7 = cat(decoded_andMatrixOutputs_hi_lo_hi_3, decoded_andMatrixOutputs_andMatrixInput_6_7) node decoded_andMatrixOutputs_hi_hi_lo_3 = cat(decoded_andMatrixOutputs_andMatrixInput_2_7, decoded_andMatrixOutputs_andMatrixInput_3_7) node decoded_andMatrixOutputs_hi_hi_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_0_7, decoded_andMatrixOutputs_andMatrixInput_1_7) node decoded_andMatrixOutputs_hi_hi_7 = cat(decoded_andMatrixOutputs_hi_hi_hi_3, decoded_andMatrixOutputs_hi_hi_lo_3) node decoded_andMatrixOutputs_hi_7 = cat(decoded_andMatrixOutputs_hi_hi_7, decoded_andMatrixOutputs_hi_lo_7) node _decoded_andMatrixOutputs_T_7 = cat(decoded_andMatrixOutputs_hi_7, decoded_andMatrixOutputs_lo_7) node decoded_andMatrixOutputs_26_2 = andr(_decoded_andMatrixOutputs_T_7) node decoded_andMatrixOutputs_andMatrixInput_0_8 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_8 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_8 = bits(decoded_plaInput, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_8 = bits(decoded_invInputs, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_8 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_8 = bits(decoded_invInputs, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_8 = bits(decoded_plaInput, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_7_8 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8_4 = bits(decoded_plaInput, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9_4 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10_4 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_11_4 = bits(decoded_invInputs, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_12_4 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_lo_lo_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_10_4, decoded_andMatrixOutputs_andMatrixInput_11_4) node decoded_andMatrixOutputs_lo_lo_8 = cat(decoded_andMatrixOutputs_lo_lo_hi_4, decoded_andMatrixOutputs_andMatrixInput_12_4) node decoded_andMatrixOutputs_lo_hi_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_7_8, decoded_andMatrixOutputs_andMatrixInput_8_4) node decoded_andMatrixOutputs_lo_hi_8 = cat(decoded_andMatrixOutputs_lo_hi_hi_4, decoded_andMatrixOutputs_andMatrixInput_9_4) node decoded_andMatrixOutputs_lo_8 = cat(decoded_andMatrixOutputs_lo_hi_8, decoded_andMatrixOutputs_lo_lo_8) node decoded_andMatrixOutputs_hi_lo_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_4_8, decoded_andMatrixOutputs_andMatrixInput_5_8) node decoded_andMatrixOutputs_hi_lo_8 = cat(decoded_andMatrixOutputs_hi_lo_hi_4, decoded_andMatrixOutputs_andMatrixInput_6_8) node decoded_andMatrixOutputs_hi_hi_lo_4 = cat(decoded_andMatrixOutputs_andMatrixInput_2_8, decoded_andMatrixOutputs_andMatrixInput_3_8) node decoded_andMatrixOutputs_hi_hi_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_0_8, decoded_andMatrixOutputs_andMatrixInput_1_8) node decoded_andMatrixOutputs_hi_hi_8 = cat(decoded_andMatrixOutputs_hi_hi_hi_4, decoded_andMatrixOutputs_hi_hi_lo_4) node decoded_andMatrixOutputs_hi_8 = cat(decoded_andMatrixOutputs_hi_hi_8, decoded_andMatrixOutputs_hi_lo_8) node _decoded_andMatrixOutputs_T_8 = cat(decoded_andMatrixOutputs_hi_8, decoded_andMatrixOutputs_lo_8) node decoded_andMatrixOutputs_2_2 = andr(_decoded_andMatrixOutputs_T_8) node decoded_andMatrixOutputs_andMatrixInput_0_9 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_9 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_9 = bits(decoded_plaInput, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_9 = bits(decoded_invInputs, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_9 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_9 = bits(decoded_invInputs, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_9 = bits(decoded_plaInput, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_7_9 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8_5 = bits(decoded_plaInput, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9_5 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10_5 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_11_5 = bits(decoded_invInputs, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_12_5 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_lo_lo_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_10_5, decoded_andMatrixOutputs_andMatrixInput_11_5) node decoded_andMatrixOutputs_lo_lo_9 = cat(decoded_andMatrixOutputs_lo_lo_hi_5, decoded_andMatrixOutputs_andMatrixInput_12_5) node decoded_andMatrixOutputs_lo_hi_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_7_9, decoded_andMatrixOutputs_andMatrixInput_8_5) node decoded_andMatrixOutputs_lo_hi_9 = cat(decoded_andMatrixOutputs_lo_hi_hi_5, decoded_andMatrixOutputs_andMatrixInput_9_5) node decoded_andMatrixOutputs_lo_9 = cat(decoded_andMatrixOutputs_lo_hi_9, decoded_andMatrixOutputs_lo_lo_9) node decoded_andMatrixOutputs_hi_lo_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_4_9, decoded_andMatrixOutputs_andMatrixInput_5_9) node decoded_andMatrixOutputs_hi_lo_9 = cat(decoded_andMatrixOutputs_hi_lo_hi_5, decoded_andMatrixOutputs_andMatrixInput_6_9) node decoded_andMatrixOutputs_hi_hi_lo_5 = cat(decoded_andMatrixOutputs_andMatrixInput_2_9, decoded_andMatrixOutputs_andMatrixInput_3_9) node decoded_andMatrixOutputs_hi_hi_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_0_9, decoded_andMatrixOutputs_andMatrixInput_1_9) node decoded_andMatrixOutputs_hi_hi_9 = cat(decoded_andMatrixOutputs_hi_hi_hi_5, decoded_andMatrixOutputs_hi_hi_lo_5) node decoded_andMatrixOutputs_hi_9 = cat(decoded_andMatrixOutputs_hi_hi_9, decoded_andMatrixOutputs_hi_lo_9) node _decoded_andMatrixOutputs_T_9 = cat(decoded_andMatrixOutputs_hi_9, decoded_andMatrixOutputs_lo_9) node decoded_andMatrixOutputs_25_2 = andr(_decoded_andMatrixOutputs_T_9) node decoded_andMatrixOutputs_andMatrixInput_0_10 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_10 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_10 = bits(decoded_invInputs, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_3_10 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_4_10 = bits(decoded_invInputs, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_5_10 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_6_10 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_7_10 = bits(decoded_plaInput, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8_6 = bits(decoded_plaInput, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9_6 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10_6 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_11_6 = bits(decoded_invInputs, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_12_6 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_lo_lo_hi_6 = cat(decoded_andMatrixOutputs_andMatrixInput_10_6, decoded_andMatrixOutputs_andMatrixInput_11_6) node decoded_andMatrixOutputs_lo_lo_10 = cat(decoded_andMatrixOutputs_lo_lo_hi_6, decoded_andMatrixOutputs_andMatrixInput_12_6) node decoded_andMatrixOutputs_lo_hi_hi_6 = cat(decoded_andMatrixOutputs_andMatrixInput_7_10, decoded_andMatrixOutputs_andMatrixInput_8_6) node decoded_andMatrixOutputs_lo_hi_10 = cat(decoded_andMatrixOutputs_lo_hi_hi_6, decoded_andMatrixOutputs_andMatrixInput_9_6) node decoded_andMatrixOutputs_lo_10 = cat(decoded_andMatrixOutputs_lo_hi_10, decoded_andMatrixOutputs_lo_lo_10) node decoded_andMatrixOutputs_hi_lo_hi_6 = cat(decoded_andMatrixOutputs_andMatrixInput_4_10, decoded_andMatrixOutputs_andMatrixInput_5_10) node decoded_andMatrixOutputs_hi_lo_10 = cat(decoded_andMatrixOutputs_hi_lo_hi_6, decoded_andMatrixOutputs_andMatrixInput_6_10) node decoded_andMatrixOutputs_hi_hi_lo_6 = cat(decoded_andMatrixOutputs_andMatrixInput_2_10, decoded_andMatrixOutputs_andMatrixInput_3_10) node decoded_andMatrixOutputs_hi_hi_hi_6 = cat(decoded_andMatrixOutputs_andMatrixInput_0_10, decoded_andMatrixOutputs_andMatrixInput_1_10) node decoded_andMatrixOutputs_hi_hi_10 = cat(decoded_andMatrixOutputs_hi_hi_hi_6, decoded_andMatrixOutputs_hi_hi_lo_6) node decoded_andMatrixOutputs_hi_10 = cat(decoded_andMatrixOutputs_hi_hi_10, decoded_andMatrixOutputs_hi_lo_10) node _decoded_andMatrixOutputs_T_10 = cat(decoded_andMatrixOutputs_hi_10, decoded_andMatrixOutputs_lo_10) node decoded_andMatrixOutputs_5_2 = andr(_decoded_andMatrixOutputs_T_10) node decoded_andMatrixOutputs_andMatrixInput_0_11 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_11 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_11 = bits(decoded_invInputs, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_3_11 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_4_11 = bits(decoded_invInputs, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_5_11 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_6_11 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_7_11 = bits(decoded_plaInput, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8_7 = bits(decoded_plaInput, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9_7 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10_7 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_11_7 = bits(decoded_invInputs, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_12_7 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_lo_lo_hi_7 = cat(decoded_andMatrixOutputs_andMatrixInput_10_7, decoded_andMatrixOutputs_andMatrixInput_11_7) node decoded_andMatrixOutputs_lo_lo_11 = cat(decoded_andMatrixOutputs_lo_lo_hi_7, decoded_andMatrixOutputs_andMatrixInput_12_7) node decoded_andMatrixOutputs_lo_hi_hi_7 = cat(decoded_andMatrixOutputs_andMatrixInput_7_11, decoded_andMatrixOutputs_andMatrixInput_8_7) node decoded_andMatrixOutputs_lo_hi_11 = cat(decoded_andMatrixOutputs_lo_hi_hi_7, decoded_andMatrixOutputs_andMatrixInput_9_7) node decoded_andMatrixOutputs_lo_11 = cat(decoded_andMatrixOutputs_lo_hi_11, decoded_andMatrixOutputs_lo_lo_11) node decoded_andMatrixOutputs_hi_lo_hi_7 = cat(decoded_andMatrixOutputs_andMatrixInput_4_11, decoded_andMatrixOutputs_andMatrixInput_5_11) node decoded_andMatrixOutputs_hi_lo_11 = cat(decoded_andMatrixOutputs_hi_lo_hi_7, decoded_andMatrixOutputs_andMatrixInput_6_11) node decoded_andMatrixOutputs_hi_hi_lo_7 = cat(decoded_andMatrixOutputs_andMatrixInput_2_11, decoded_andMatrixOutputs_andMatrixInput_3_11) node decoded_andMatrixOutputs_hi_hi_hi_7 = cat(decoded_andMatrixOutputs_andMatrixInput_0_11, decoded_andMatrixOutputs_andMatrixInput_1_11) node decoded_andMatrixOutputs_hi_hi_11 = cat(decoded_andMatrixOutputs_hi_hi_hi_7, decoded_andMatrixOutputs_hi_hi_lo_7) node decoded_andMatrixOutputs_hi_11 = cat(decoded_andMatrixOutputs_hi_hi_11, decoded_andMatrixOutputs_hi_lo_11) node _decoded_andMatrixOutputs_T_11 = cat(decoded_andMatrixOutputs_hi_11, decoded_andMatrixOutputs_lo_11) node decoded_andMatrixOutputs_12_2 = andr(_decoded_andMatrixOutputs_T_11) node decoded_andMatrixOutputs_andMatrixInput_0_12 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_12 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_12 = bits(decoded_plaInput, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_12 = bits(decoded_invInputs, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_12 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_12 = bits(decoded_invInputs, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_12 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_12 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_8 = bits(decoded_plaInput, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_8 = bits(decoded_plaInput, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_8 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_8 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12_8 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_lo_lo_hi_8 = cat(decoded_andMatrixOutputs_andMatrixInput_10_8, decoded_andMatrixOutputs_andMatrixInput_11_8) node decoded_andMatrixOutputs_lo_lo_12 = cat(decoded_andMatrixOutputs_lo_lo_hi_8, decoded_andMatrixOutputs_andMatrixInput_12_8) node decoded_andMatrixOutputs_lo_hi_hi_8 = cat(decoded_andMatrixOutputs_andMatrixInput_7_12, decoded_andMatrixOutputs_andMatrixInput_8_8) node decoded_andMatrixOutputs_lo_hi_12 = cat(decoded_andMatrixOutputs_lo_hi_hi_8, decoded_andMatrixOutputs_andMatrixInput_9_8) node decoded_andMatrixOutputs_lo_12 = cat(decoded_andMatrixOutputs_lo_hi_12, decoded_andMatrixOutputs_lo_lo_12) node decoded_andMatrixOutputs_hi_lo_hi_8 = cat(decoded_andMatrixOutputs_andMatrixInput_4_12, decoded_andMatrixOutputs_andMatrixInput_5_12) node decoded_andMatrixOutputs_hi_lo_12 = cat(decoded_andMatrixOutputs_hi_lo_hi_8, decoded_andMatrixOutputs_andMatrixInput_6_12) node decoded_andMatrixOutputs_hi_hi_lo_8 = cat(decoded_andMatrixOutputs_andMatrixInput_2_12, decoded_andMatrixOutputs_andMatrixInput_3_12) node decoded_andMatrixOutputs_hi_hi_hi_8 = cat(decoded_andMatrixOutputs_andMatrixInput_0_12, decoded_andMatrixOutputs_andMatrixInput_1_12) node decoded_andMatrixOutputs_hi_hi_12 = cat(decoded_andMatrixOutputs_hi_hi_hi_8, decoded_andMatrixOutputs_hi_hi_lo_8) node decoded_andMatrixOutputs_hi_12 = cat(decoded_andMatrixOutputs_hi_hi_12, decoded_andMatrixOutputs_hi_lo_12) node _decoded_andMatrixOutputs_T_12 = cat(decoded_andMatrixOutputs_hi_12, decoded_andMatrixOutputs_lo_12) node decoded_andMatrixOutputs_8_2 = andr(_decoded_andMatrixOutputs_T_12) node decoded_andMatrixOutputs_andMatrixInput_0_13 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_13 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_13 = bits(decoded_plaInput, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_13 = bits(decoded_invInputs, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_13 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_13 = bits(decoded_invInputs, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_13 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_13 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_9 = bits(decoded_plaInput, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_9 = bits(decoded_plaInput, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_9 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_9 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12_9 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_lo_lo_hi_9 = cat(decoded_andMatrixOutputs_andMatrixInput_10_9, decoded_andMatrixOutputs_andMatrixInput_11_9) node decoded_andMatrixOutputs_lo_lo_13 = cat(decoded_andMatrixOutputs_lo_lo_hi_9, decoded_andMatrixOutputs_andMatrixInput_12_9) node decoded_andMatrixOutputs_lo_hi_hi_9 = cat(decoded_andMatrixOutputs_andMatrixInput_7_13, decoded_andMatrixOutputs_andMatrixInput_8_9) node decoded_andMatrixOutputs_lo_hi_13 = cat(decoded_andMatrixOutputs_lo_hi_hi_9, decoded_andMatrixOutputs_andMatrixInput_9_9) node decoded_andMatrixOutputs_lo_13 = cat(decoded_andMatrixOutputs_lo_hi_13, decoded_andMatrixOutputs_lo_lo_13) node decoded_andMatrixOutputs_hi_lo_hi_9 = cat(decoded_andMatrixOutputs_andMatrixInput_4_13, decoded_andMatrixOutputs_andMatrixInput_5_13) node decoded_andMatrixOutputs_hi_lo_13 = cat(decoded_andMatrixOutputs_hi_lo_hi_9, decoded_andMatrixOutputs_andMatrixInput_6_13) node decoded_andMatrixOutputs_hi_hi_lo_9 = cat(decoded_andMatrixOutputs_andMatrixInput_2_13, decoded_andMatrixOutputs_andMatrixInput_3_13) node decoded_andMatrixOutputs_hi_hi_hi_9 = cat(decoded_andMatrixOutputs_andMatrixInput_0_13, decoded_andMatrixOutputs_andMatrixInput_1_13) node decoded_andMatrixOutputs_hi_hi_13 = cat(decoded_andMatrixOutputs_hi_hi_hi_9, decoded_andMatrixOutputs_hi_hi_lo_9) node decoded_andMatrixOutputs_hi_13 = cat(decoded_andMatrixOutputs_hi_hi_13, decoded_andMatrixOutputs_hi_lo_13) node _decoded_andMatrixOutputs_T_13 = cat(decoded_andMatrixOutputs_hi_13, decoded_andMatrixOutputs_lo_13) node decoded_andMatrixOutputs_15_2 = andr(_decoded_andMatrixOutputs_T_13) node decoded_andMatrixOutputs_andMatrixInput_0_14 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_14 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_14 = bits(decoded_plaInput, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_3_14 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_4_14 = bits(decoded_invInputs, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_5_14 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_6_14 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_7_14 = bits(decoded_plaInput, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8_10 = bits(decoded_plaInput, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9_10 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10_10 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_11_10 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_lo_lo_hi_10 = cat(decoded_andMatrixOutputs_andMatrixInput_9_10, decoded_andMatrixOutputs_andMatrixInput_10_10) node decoded_andMatrixOutputs_lo_lo_14 = cat(decoded_andMatrixOutputs_lo_lo_hi_10, decoded_andMatrixOutputs_andMatrixInput_11_10) node decoded_andMatrixOutputs_lo_hi_hi_10 = cat(decoded_andMatrixOutputs_andMatrixInput_6_14, decoded_andMatrixOutputs_andMatrixInput_7_14) node decoded_andMatrixOutputs_lo_hi_14 = cat(decoded_andMatrixOutputs_lo_hi_hi_10, decoded_andMatrixOutputs_andMatrixInput_8_10) node decoded_andMatrixOutputs_lo_14 = cat(decoded_andMatrixOutputs_lo_hi_14, decoded_andMatrixOutputs_lo_lo_14) node decoded_andMatrixOutputs_hi_lo_hi_10 = cat(decoded_andMatrixOutputs_andMatrixInput_3_14, decoded_andMatrixOutputs_andMatrixInput_4_14) node decoded_andMatrixOutputs_hi_lo_14 = cat(decoded_andMatrixOutputs_hi_lo_hi_10, decoded_andMatrixOutputs_andMatrixInput_5_14) node decoded_andMatrixOutputs_hi_hi_hi_10 = cat(decoded_andMatrixOutputs_andMatrixInput_0_14, decoded_andMatrixOutputs_andMatrixInput_1_14) node decoded_andMatrixOutputs_hi_hi_14 = cat(decoded_andMatrixOutputs_hi_hi_hi_10, decoded_andMatrixOutputs_andMatrixInput_2_14) node decoded_andMatrixOutputs_hi_14 = cat(decoded_andMatrixOutputs_hi_hi_14, decoded_andMatrixOutputs_hi_lo_14) node _decoded_andMatrixOutputs_T_14 = cat(decoded_andMatrixOutputs_hi_14, decoded_andMatrixOutputs_lo_14) node decoded_andMatrixOutputs_11_2 = andr(_decoded_andMatrixOutputs_T_14) node decoded_andMatrixOutputs_andMatrixInput_0_15 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_15 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_15 = bits(decoded_plaInput, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_3_15 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_4_15 = bits(decoded_invInputs, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_5_15 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_6_15 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_7_15 = bits(decoded_plaInput, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8_11 = bits(decoded_plaInput, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9_11 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10_11 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_11_11 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_lo_lo_hi_11 = cat(decoded_andMatrixOutputs_andMatrixInput_9_11, decoded_andMatrixOutputs_andMatrixInput_10_11) node decoded_andMatrixOutputs_lo_lo_15 = cat(decoded_andMatrixOutputs_lo_lo_hi_11, decoded_andMatrixOutputs_andMatrixInput_11_11) node decoded_andMatrixOutputs_lo_hi_hi_11 = cat(decoded_andMatrixOutputs_andMatrixInput_6_15, decoded_andMatrixOutputs_andMatrixInput_7_15) node decoded_andMatrixOutputs_lo_hi_15 = cat(decoded_andMatrixOutputs_lo_hi_hi_11, decoded_andMatrixOutputs_andMatrixInput_8_11) node decoded_andMatrixOutputs_lo_15 = cat(decoded_andMatrixOutputs_lo_hi_15, decoded_andMatrixOutputs_lo_lo_15) node decoded_andMatrixOutputs_hi_lo_hi_11 = cat(decoded_andMatrixOutputs_andMatrixInput_3_15, decoded_andMatrixOutputs_andMatrixInput_4_15) node decoded_andMatrixOutputs_hi_lo_15 = cat(decoded_andMatrixOutputs_hi_lo_hi_11, decoded_andMatrixOutputs_andMatrixInput_5_15) node decoded_andMatrixOutputs_hi_hi_hi_11 = cat(decoded_andMatrixOutputs_andMatrixInput_0_15, decoded_andMatrixOutputs_andMatrixInput_1_15) node decoded_andMatrixOutputs_hi_hi_15 = cat(decoded_andMatrixOutputs_hi_hi_hi_11, decoded_andMatrixOutputs_andMatrixInput_2_15) node decoded_andMatrixOutputs_hi_15 = cat(decoded_andMatrixOutputs_hi_hi_15, decoded_andMatrixOutputs_hi_lo_15) node _decoded_andMatrixOutputs_T_15 = cat(decoded_andMatrixOutputs_hi_15, decoded_andMatrixOutputs_lo_15) node decoded_andMatrixOutputs_14_2 = andr(_decoded_andMatrixOutputs_T_15) node decoded_andMatrixOutputs_andMatrixInput_0_16 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_16 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_16 = bits(decoded_plaInput, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_3_16 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_4_16 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_5_16 = bits(decoded_plaInput, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_6_16 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_7_16 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_lo_lo_16 = cat(decoded_andMatrixOutputs_andMatrixInput_6_16, decoded_andMatrixOutputs_andMatrixInput_7_16) node decoded_andMatrixOutputs_lo_hi_16 = cat(decoded_andMatrixOutputs_andMatrixInput_4_16, decoded_andMatrixOutputs_andMatrixInput_5_16) node decoded_andMatrixOutputs_lo_16 = cat(decoded_andMatrixOutputs_lo_hi_16, decoded_andMatrixOutputs_lo_lo_16) node decoded_andMatrixOutputs_hi_lo_16 = cat(decoded_andMatrixOutputs_andMatrixInput_2_16, decoded_andMatrixOutputs_andMatrixInput_3_16) node decoded_andMatrixOutputs_hi_hi_16 = cat(decoded_andMatrixOutputs_andMatrixInput_0_16, decoded_andMatrixOutputs_andMatrixInput_1_16) node decoded_andMatrixOutputs_hi_16 = cat(decoded_andMatrixOutputs_hi_hi_16, decoded_andMatrixOutputs_hi_lo_16) node _decoded_andMatrixOutputs_T_16 = cat(decoded_andMatrixOutputs_hi_16, decoded_andMatrixOutputs_lo_16) node decoded_andMatrixOutputs_4_2 = andr(_decoded_andMatrixOutputs_T_16) node decoded_andMatrixOutputs_andMatrixInput_0_17 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_17 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_17 = bits(decoded_plaInput, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_3_17 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_4_17 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_5_17 = bits(decoded_plaInput, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_6_17 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_7_17 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_lo_lo_17 = cat(decoded_andMatrixOutputs_andMatrixInput_6_17, decoded_andMatrixOutputs_andMatrixInput_7_17) node decoded_andMatrixOutputs_lo_hi_17 = cat(decoded_andMatrixOutputs_andMatrixInput_4_17, decoded_andMatrixOutputs_andMatrixInput_5_17) node decoded_andMatrixOutputs_lo_17 = cat(decoded_andMatrixOutputs_lo_hi_17, decoded_andMatrixOutputs_lo_lo_17) node decoded_andMatrixOutputs_hi_lo_17 = cat(decoded_andMatrixOutputs_andMatrixInput_2_17, decoded_andMatrixOutputs_andMatrixInput_3_17) node decoded_andMatrixOutputs_hi_hi_17 = cat(decoded_andMatrixOutputs_andMatrixInput_0_17, decoded_andMatrixOutputs_andMatrixInput_1_17) node decoded_andMatrixOutputs_hi_17 = cat(decoded_andMatrixOutputs_hi_hi_17, decoded_andMatrixOutputs_hi_lo_17) node _decoded_andMatrixOutputs_T_17 = cat(decoded_andMatrixOutputs_hi_17, decoded_andMatrixOutputs_lo_17) node decoded_andMatrixOutputs_23_2 = andr(_decoded_andMatrixOutputs_T_17) node decoded_andMatrixOutputs_andMatrixInput_0_18 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_18 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_18 = bits(decoded_plaInput, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_3_18 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_4_18 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_5_18 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_6_18 = bits(decoded_plaInput, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_7_18 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_lo_lo_18 = cat(decoded_andMatrixOutputs_andMatrixInput_6_18, decoded_andMatrixOutputs_andMatrixInput_7_18) node decoded_andMatrixOutputs_lo_hi_18 = cat(decoded_andMatrixOutputs_andMatrixInput_4_18, decoded_andMatrixOutputs_andMatrixInput_5_18) node decoded_andMatrixOutputs_lo_18 = cat(decoded_andMatrixOutputs_lo_hi_18, decoded_andMatrixOutputs_lo_lo_18) node decoded_andMatrixOutputs_hi_lo_18 = cat(decoded_andMatrixOutputs_andMatrixInput_2_18, decoded_andMatrixOutputs_andMatrixInput_3_18) node decoded_andMatrixOutputs_hi_hi_18 = cat(decoded_andMatrixOutputs_andMatrixInput_0_18, decoded_andMatrixOutputs_andMatrixInput_1_18) node decoded_andMatrixOutputs_hi_18 = cat(decoded_andMatrixOutputs_hi_hi_18, decoded_andMatrixOutputs_hi_lo_18) node _decoded_andMatrixOutputs_T_18 = cat(decoded_andMatrixOutputs_hi_18, decoded_andMatrixOutputs_lo_18) node decoded_andMatrixOutputs_13_2 = andr(_decoded_andMatrixOutputs_T_18) node decoded_andMatrixOutputs_andMatrixInput_0_19 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_1_19 = bits(decoded_invInputs, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_2_19 = bits(decoded_plaInput, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_3_19 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_4_19 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_5_19 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_6_19 = bits(decoded_plaInput, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_7_19 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_lo_lo_19 = cat(decoded_andMatrixOutputs_andMatrixInput_6_19, decoded_andMatrixOutputs_andMatrixInput_7_19) node decoded_andMatrixOutputs_lo_hi_19 = cat(decoded_andMatrixOutputs_andMatrixInput_4_19, decoded_andMatrixOutputs_andMatrixInput_5_19) node decoded_andMatrixOutputs_lo_19 = cat(decoded_andMatrixOutputs_lo_hi_19, decoded_andMatrixOutputs_lo_lo_19) node decoded_andMatrixOutputs_hi_lo_19 = cat(decoded_andMatrixOutputs_andMatrixInput_2_19, decoded_andMatrixOutputs_andMatrixInput_3_19) node decoded_andMatrixOutputs_hi_hi_19 = cat(decoded_andMatrixOutputs_andMatrixInput_0_19, decoded_andMatrixOutputs_andMatrixInput_1_19) node decoded_andMatrixOutputs_hi_19 = cat(decoded_andMatrixOutputs_hi_hi_19, decoded_andMatrixOutputs_hi_lo_19) node _decoded_andMatrixOutputs_T_19 = cat(decoded_andMatrixOutputs_hi_19, decoded_andMatrixOutputs_lo_19) node decoded_andMatrixOutputs_24_2 = andr(_decoded_andMatrixOutputs_T_19) node decoded_andMatrixOutputs_andMatrixInput_0_20 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_20 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_20 = bits(decoded_plaInput, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_3_20 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_4_20 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_5_20 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_6_20 = bits(decoded_plaInput, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_7_20 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_lo_lo_20 = cat(decoded_andMatrixOutputs_andMatrixInput_6_20, decoded_andMatrixOutputs_andMatrixInput_7_20) node decoded_andMatrixOutputs_lo_hi_20 = cat(decoded_andMatrixOutputs_andMatrixInput_4_20, decoded_andMatrixOutputs_andMatrixInput_5_20) node decoded_andMatrixOutputs_lo_20 = cat(decoded_andMatrixOutputs_lo_hi_20, decoded_andMatrixOutputs_lo_lo_20) node decoded_andMatrixOutputs_hi_lo_20 = cat(decoded_andMatrixOutputs_andMatrixInput_2_20, decoded_andMatrixOutputs_andMatrixInput_3_20) node decoded_andMatrixOutputs_hi_hi_20 = cat(decoded_andMatrixOutputs_andMatrixInput_0_20, decoded_andMatrixOutputs_andMatrixInput_1_20) node decoded_andMatrixOutputs_hi_20 = cat(decoded_andMatrixOutputs_hi_hi_20, decoded_andMatrixOutputs_hi_lo_20) node _decoded_andMatrixOutputs_T_20 = cat(decoded_andMatrixOutputs_hi_20, decoded_andMatrixOutputs_lo_20) node decoded_andMatrixOutputs_16_2 = andr(_decoded_andMatrixOutputs_T_20) node decoded_andMatrixOutputs_andMatrixInput_0_21 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_1_21 = bits(decoded_invInputs, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_2_21 = bits(decoded_plaInput, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_3_21 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_4_21 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_5_21 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_6_21 = bits(decoded_plaInput, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_7_21 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_lo_lo_21 = cat(decoded_andMatrixOutputs_andMatrixInput_6_21, decoded_andMatrixOutputs_andMatrixInput_7_21) node decoded_andMatrixOutputs_lo_hi_21 = cat(decoded_andMatrixOutputs_andMatrixInput_4_21, decoded_andMatrixOutputs_andMatrixInput_5_21) node decoded_andMatrixOutputs_lo_21 = cat(decoded_andMatrixOutputs_lo_hi_21, decoded_andMatrixOutputs_lo_lo_21) node decoded_andMatrixOutputs_hi_lo_21 = cat(decoded_andMatrixOutputs_andMatrixInput_2_21, decoded_andMatrixOutputs_andMatrixInput_3_21) node decoded_andMatrixOutputs_hi_hi_21 = cat(decoded_andMatrixOutputs_andMatrixInput_0_21, decoded_andMatrixOutputs_andMatrixInput_1_21) node decoded_andMatrixOutputs_hi_21 = cat(decoded_andMatrixOutputs_hi_hi_21, decoded_andMatrixOutputs_hi_lo_21) node _decoded_andMatrixOutputs_T_21 = cat(decoded_andMatrixOutputs_hi_21, decoded_andMatrixOutputs_lo_21) node decoded_andMatrixOutputs_18_2 = andr(_decoded_andMatrixOutputs_T_21) node decoded_andMatrixOutputs_andMatrixInput_0_22 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_22 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_2_22 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_3_22 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_lo_22 = cat(decoded_andMatrixOutputs_andMatrixInput_2_22, decoded_andMatrixOutputs_andMatrixInput_3_22) node decoded_andMatrixOutputs_hi_22 = cat(decoded_andMatrixOutputs_andMatrixInput_0_22, decoded_andMatrixOutputs_andMatrixInput_1_22) node _decoded_andMatrixOutputs_T_22 = cat(decoded_andMatrixOutputs_hi_22, decoded_andMatrixOutputs_lo_22) node decoded_andMatrixOutputs_9_2 = andr(_decoded_andMatrixOutputs_T_22) node decoded_andMatrixOutputs_andMatrixInput_0_23 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_23 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_2_23 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_3_23 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_lo_23 = cat(decoded_andMatrixOutputs_andMatrixInput_2_23, decoded_andMatrixOutputs_andMatrixInput_3_23) node decoded_andMatrixOutputs_hi_23 = cat(decoded_andMatrixOutputs_andMatrixInput_0_23, decoded_andMatrixOutputs_andMatrixInput_1_23) node _decoded_andMatrixOutputs_T_23 = cat(decoded_andMatrixOutputs_hi_23, decoded_andMatrixOutputs_lo_23) node decoded_andMatrixOutputs_22_2 = andr(_decoded_andMatrixOutputs_T_23) node decoded_andMatrixOutputs_andMatrixInput_0_24 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_24 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_24 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_3_24 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_4_22 = bits(decoded_plaInput, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_5_22 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_6_22 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_7_22 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_lo_lo_22 = cat(decoded_andMatrixOutputs_andMatrixInput_6_22, decoded_andMatrixOutputs_andMatrixInput_7_22) node decoded_andMatrixOutputs_lo_hi_22 = cat(decoded_andMatrixOutputs_andMatrixInput_4_22, decoded_andMatrixOutputs_andMatrixInput_5_22) node decoded_andMatrixOutputs_lo_24 = cat(decoded_andMatrixOutputs_lo_hi_22, decoded_andMatrixOutputs_lo_lo_22) node decoded_andMatrixOutputs_hi_lo_22 = cat(decoded_andMatrixOutputs_andMatrixInput_2_24, decoded_andMatrixOutputs_andMatrixInput_3_24) node decoded_andMatrixOutputs_hi_hi_22 = cat(decoded_andMatrixOutputs_andMatrixInput_0_24, decoded_andMatrixOutputs_andMatrixInput_1_24) node decoded_andMatrixOutputs_hi_24 = cat(decoded_andMatrixOutputs_hi_hi_22, decoded_andMatrixOutputs_hi_lo_22) node _decoded_andMatrixOutputs_T_24 = cat(decoded_andMatrixOutputs_hi_24, decoded_andMatrixOutputs_lo_24) node decoded_andMatrixOutputs_28_2 = andr(_decoded_andMatrixOutputs_T_24) node decoded_andMatrixOutputs_andMatrixInput_0_25 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_25 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_25 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_3_25 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_4_23 = bits(decoded_plaInput, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_5_23 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_6_23 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_7_23 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_lo_lo_23 = cat(decoded_andMatrixOutputs_andMatrixInput_6_23, decoded_andMatrixOutputs_andMatrixInput_7_23) node decoded_andMatrixOutputs_lo_hi_23 = cat(decoded_andMatrixOutputs_andMatrixInput_4_23, decoded_andMatrixOutputs_andMatrixInput_5_23) node decoded_andMatrixOutputs_lo_25 = cat(decoded_andMatrixOutputs_lo_hi_23, decoded_andMatrixOutputs_lo_lo_23) node decoded_andMatrixOutputs_hi_lo_23 = cat(decoded_andMatrixOutputs_andMatrixInput_2_25, decoded_andMatrixOutputs_andMatrixInput_3_25) node decoded_andMatrixOutputs_hi_hi_23 = cat(decoded_andMatrixOutputs_andMatrixInput_0_25, decoded_andMatrixOutputs_andMatrixInput_1_25) node decoded_andMatrixOutputs_hi_25 = cat(decoded_andMatrixOutputs_hi_hi_23, decoded_andMatrixOutputs_hi_lo_23) node _decoded_andMatrixOutputs_T_25 = cat(decoded_andMatrixOutputs_hi_25, decoded_andMatrixOutputs_lo_25) node decoded_andMatrixOutputs_27_2 = andr(_decoded_andMatrixOutputs_T_25) node decoded_andMatrixOutputs_andMatrixInput_0_26 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_26 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_26 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_3_26 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_4_24 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_5_24 = bits(decoded_plaInput, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_6_24 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_7_24 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_lo_lo_24 = cat(decoded_andMatrixOutputs_andMatrixInput_6_24, decoded_andMatrixOutputs_andMatrixInput_7_24) node decoded_andMatrixOutputs_lo_hi_24 = cat(decoded_andMatrixOutputs_andMatrixInput_4_24, decoded_andMatrixOutputs_andMatrixInput_5_24) node decoded_andMatrixOutputs_lo_26 = cat(decoded_andMatrixOutputs_lo_hi_24, decoded_andMatrixOutputs_lo_lo_24) node decoded_andMatrixOutputs_hi_lo_24 = cat(decoded_andMatrixOutputs_andMatrixInput_2_26, decoded_andMatrixOutputs_andMatrixInput_3_26) node decoded_andMatrixOutputs_hi_hi_24 = cat(decoded_andMatrixOutputs_andMatrixInput_0_26, decoded_andMatrixOutputs_andMatrixInput_1_26) node decoded_andMatrixOutputs_hi_26 = cat(decoded_andMatrixOutputs_hi_hi_24, decoded_andMatrixOutputs_hi_lo_24) node _decoded_andMatrixOutputs_T_26 = cat(decoded_andMatrixOutputs_hi_26, decoded_andMatrixOutputs_lo_26) node decoded_andMatrixOutputs_10_2 = andr(_decoded_andMatrixOutputs_T_26) node decoded_andMatrixOutputs_andMatrixInput_0_27 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_1_27 = bits(decoded_invInputs, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_2_27 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_3_27 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_4_25 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_5_25 = bits(decoded_plaInput, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_6_25 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_7_25 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_lo_lo_25 = cat(decoded_andMatrixOutputs_andMatrixInput_6_25, decoded_andMatrixOutputs_andMatrixInput_7_25) node decoded_andMatrixOutputs_lo_hi_25 = cat(decoded_andMatrixOutputs_andMatrixInput_4_25, decoded_andMatrixOutputs_andMatrixInput_5_25) node decoded_andMatrixOutputs_lo_27 = cat(decoded_andMatrixOutputs_lo_hi_25, decoded_andMatrixOutputs_lo_lo_25) node decoded_andMatrixOutputs_hi_lo_25 = cat(decoded_andMatrixOutputs_andMatrixInput_2_27, decoded_andMatrixOutputs_andMatrixInput_3_27) node decoded_andMatrixOutputs_hi_hi_25 = cat(decoded_andMatrixOutputs_andMatrixInput_0_27, decoded_andMatrixOutputs_andMatrixInput_1_27) node decoded_andMatrixOutputs_hi_27 = cat(decoded_andMatrixOutputs_hi_hi_25, decoded_andMatrixOutputs_hi_lo_25) node _decoded_andMatrixOutputs_T_27 = cat(decoded_andMatrixOutputs_hi_27, decoded_andMatrixOutputs_lo_27) node decoded_andMatrixOutputs_3_2 = andr(_decoded_andMatrixOutputs_T_27) node decoded_andMatrixOutputs_andMatrixInput_0_28 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_28 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_28 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_3_28 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_4_26 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_5_26 = bits(decoded_plaInput, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_6_26 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_7_26 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_lo_lo_26 = cat(decoded_andMatrixOutputs_andMatrixInput_6_26, decoded_andMatrixOutputs_andMatrixInput_7_26) node decoded_andMatrixOutputs_lo_hi_26 = cat(decoded_andMatrixOutputs_andMatrixInput_4_26, decoded_andMatrixOutputs_andMatrixInput_5_26) node decoded_andMatrixOutputs_lo_28 = cat(decoded_andMatrixOutputs_lo_hi_26, decoded_andMatrixOutputs_lo_lo_26) node decoded_andMatrixOutputs_hi_lo_26 = cat(decoded_andMatrixOutputs_andMatrixInput_2_28, decoded_andMatrixOutputs_andMatrixInput_3_28) node decoded_andMatrixOutputs_hi_hi_26 = cat(decoded_andMatrixOutputs_andMatrixInput_0_28, decoded_andMatrixOutputs_andMatrixInput_1_28) node decoded_andMatrixOutputs_hi_28 = cat(decoded_andMatrixOutputs_hi_hi_26, decoded_andMatrixOutputs_hi_lo_26) node _decoded_andMatrixOutputs_T_28 = cat(decoded_andMatrixOutputs_hi_28, decoded_andMatrixOutputs_lo_28) node decoded_andMatrixOutputs_17_2 = andr(_decoded_andMatrixOutputs_T_28) node decoded_andMatrixOutputs_andMatrixInput_0_29 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_1_29 = bits(decoded_invInputs, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_2_29 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_3_29 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_4_27 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_5_27 = bits(decoded_plaInput, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_6_27 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_7_27 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_lo_lo_27 = cat(decoded_andMatrixOutputs_andMatrixInput_6_27, decoded_andMatrixOutputs_andMatrixInput_7_27) node decoded_andMatrixOutputs_lo_hi_27 = cat(decoded_andMatrixOutputs_andMatrixInput_4_27, decoded_andMatrixOutputs_andMatrixInput_5_27) node decoded_andMatrixOutputs_lo_29 = cat(decoded_andMatrixOutputs_lo_hi_27, decoded_andMatrixOutputs_lo_lo_27) node decoded_andMatrixOutputs_hi_lo_27 = cat(decoded_andMatrixOutputs_andMatrixInput_2_29, decoded_andMatrixOutputs_andMatrixInput_3_29) node decoded_andMatrixOutputs_hi_hi_27 = cat(decoded_andMatrixOutputs_andMatrixInput_0_29, decoded_andMatrixOutputs_andMatrixInput_1_29) node decoded_andMatrixOutputs_hi_29 = cat(decoded_andMatrixOutputs_hi_hi_27, decoded_andMatrixOutputs_hi_lo_27) node _decoded_andMatrixOutputs_T_29 = cat(decoded_andMatrixOutputs_hi_29, decoded_andMatrixOutputs_lo_29) node decoded_andMatrixOutputs_19_2 = andr(_decoded_andMatrixOutputs_T_29) node decoded_orMatrixOutputs_lo = cat(decoded_andMatrixOutputs_17_2, decoded_andMatrixOutputs_19_2) node decoded_orMatrixOutputs_hi = cat(decoded_andMatrixOutputs_10_2, decoded_andMatrixOutputs_3_2) node _decoded_orMatrixOutputs_T = cat(decoded_orMatrixOutputs_hi, decoded_orMatrixOutputs_lo) node _decoded_orMatrixOutputs_T_1 = orr(_decoded_orMatrixOutputs_T) node decoded_orMatrixOutputs_lo_1 = cat(decoded_andMatrixOutputs_16_2, decoded_andMatrixOutputs_18_2) node decoded_orMatrixOutputs_hi_1 = cat(decoded_andMatrixOutputs_13_2, decoded_andMatrixOutputs_24_2) node _decoded_orMatrixOutputs_T_2 = cat(decoded_orMatrixOutputs_hi_1, decoded_orMatrixOutputs_lo_1) node _decoded_orMatrixOutputs_T_3 = orr(_decoded_orMatrixOutputs_T_2) node _decoded_orMatrixOutputs_T_4 = cat(decoded_andMatrixOutputs_28_2, decoded_andMatrixOutputs_27_2) node _decoded_orMatrixOutputs_T_5 = orr(_decoded_orMatrixOutputs_T_4) node _decoded_orMatrixOutputs_T_6 = cat(decoded_andMatrixOutputs_4_2, decoded_andMatrixOutputs_23_2) node _decoded_orMatrixOutputs_T_7 = orr(_decoded_orMatrixOutputs_T_6) node _decoded_orMatrixOutputs_T_8 = cat(decoded_andMatrixOutputs_9_2, decoded_andMatrixOutputs_22_2) node _decoded_orMatrixOutputs_T_9 = orr(_decoded_orMatrixOutputs_T_8) node decoded_orMatrixOutputs_lo_lo_lo = cat(decoded_andMatrixOutputs_11_2, decoded_andMatrixOutputs_14_2) node decoded_orMatrixOutputs_lo_lo_hi = cat(decoded_andMatrixOutputs_8_2, decoded_andMatrixOutputs_15_2) node decoded_orMatrixOutputs_lo_lo = cat(decoded_orMatrixOutputs_lo_lo_hi, decoded_orMatrixOutputs_lo_lo_lo) node decoded_orMatrixOutputs_lo_hi_lo = cat(decoded_andMatrixOutputs_5_2, decoded_andMatrixOutputs_12_2) node decoded_orMatrixOutputs_lo_hi_hi = cat(decoded_andMatrixOutputs_2_2, decoded_andMatrixOutputs_25_2) node decoded_orMatrixOutputs_lo_hi = cat(decoded_orMatrixOutputs_lo_hi_hi, decoded_orMatrixOutputs_lo_hi_lo) node decoded_orMatrixOutputs_lo_2 = cat(decoded_orMatrixOutputs_lo_hi, decoded_orMatrixOutputs_lo_lo) node decoded_orMatrixOutputs_hi_lo_lo = cat(decoded_andMatrixOutputs_7_2, decoded_andMatrixOutputs_26_2) node decoded_orMatrixOutputs_hi_lo_hi = cat(decoded_andMatrixOutputs_20_2, decoded_andMatrixOutputs_29_2) node decoded_orMatrixOutputs_hi_lo = cat(decoded_orMatrixOutputs_hi_lo_hi, decoded_orMatrixOutputs_hi_lo_lo) node decoded_orMatrixOutputs_hi_hi_lo = cat(decoded_andMatrixOutputs_6_2, decoded_andMatrixOutputs_0_2) node decoded_orMatrixOutputs_hi_hi_hi = cat(decoded_andMatrixOutputs_21_2, decoded_andMatrixOutputs_1_2) node decoded_orMatrixOutputs_hi_hi = cat(decoded_orMatrixOutputs_hi_hi_hi, decoded_orMatrixOutputs_hi_hi_lo) node decoded_orMatrixOutputs_hi_2 = cat(decoded_orMatrixOutputs_hi_hi, decoded_orMatrixOutputs_hi_lo) node _decoded_orMatrixOutputs_T_10 = cat(decoded_orMatrixOutputs_hi_2, decoded_orMatrixOutputs_lo_2) node _decoded_orMatrixOutputs_T_11 = orr(_decoded_orMatrixOutputs_T_10) node decoded_orMatrixOutputs_lo_hi_1 = cat(_decoded_orMatrixOutputs_T_5, _decoded_orMatrixOutputs_T_3) node decoded_orMatrixOutputs_lo_3 = cat(decoded_orMatrixOutputs_lo_hi_1, _decoded_orMatrixOutputs_T_1) node decoded_orMatrixOutputs_hi_hi_1 = cat(_decoded_orMatrixOutputs_T_11, _decoded_orMatrixOutputs_T_9) node decoded_orMatrixOutputs_hi_3 = cat(decoded_orMatrixOutputs_hi_hi_1, _decoded_orMatrixOutputs_T_7) node decoded_orMatrixOutputs = cat(decoded_orMatrixOutputs_hi_3, decoded_orMatrixOutputs_lo_3) node _decoded_invMatrixOutputs_T = bits(decoded_orMatrixOutputs, 0, 0) node _decoded_invMatrixOutputs_T_1 = bits(decoded_orMatrixOutputs, 1, 1) node _decoded_invMatrixOutputs_T_2 = bits(decoded_orMatrixOutputs, 2, 2) node _decoded_invMatrixOutputs_T_3 = bits(decoded_orMatrixOutputs, 3, 3) node _decoded_invMatrixOutputs_T_4 = bits(decoded_orMatrixOutputs, 4, 4) node _decoded_invMatrixOutputs_T_5 = bits(decoded_orMatrixOutputs, 5, 5) node decoded_invMatrixOutputs_lo_hi = cat(_decoded_invMatrixOutputs_T_2, _decoded_invMatrixOutputs_T_1) node decoded_invMatrixOutputs_lo = cat(decoded_invMatrixOutputs_lo_hi, _decoded_invMatrixOutputs_T) node decoded_invMatrixOutputs_hi_hi = cat(_decoded_invMatrixOutputs_T_5, _decoded_invMatrixOutputs_T_4) node decoded_invMatrixOutputs_hi = cat(decoded_invMatrixOutputs_hi_hi, _decoded_invMatrixOutputs_T_3) node decoded_invMatrixOutputs = cat(decoded_invMatrixOutputs_hi, decoded_invMatrixOutputs_lo) connect decoded_plaOutput, decoded_invMatrixOutputs connect decoded_plaInput, addr node _decoded_T = bits(decoded_plaOutput, 3, 0) node _decoded_T_1 = bits(_decoded_T, 1, 0) node _decoded_T_2 = bits(_decoded_T_1, 0, 0) node _decoded_T_3 = bits(_decoded_T_1, 1, 1) node _decoded_T_4 = cat(_decoded_T_2, _decoded_T_3) node _decoded_T_5 = bits(_decoded_T, 3, 2) node _decoded_T_6 = bits(_decoded_T_5, 0, 0) node _decoded_T_7 = bits(_decoded_T_5, 1, 1) node _decoded_T_8 = cat(_decoded_T_6, _decoded_T_7) node _decoded_T_9 = cat(_decoded_T_4, _decoded_T_8) node _decoded_T_10 = bits(decoded_plaOutput, 5, 4) node _decoded_T_11 = bits(_decoded_T_10, 0, 0) node _decoded_T_12 = bits(_decoded_T_10, 1, 1) node _decoded_T_13 = cat(_decoded_T_11, _decoded_T_12) node decoded = cat(_decoded_T_9, _decoded_T_13) node _io_resp_0_vc_sel_0_0_T = bits(decoded, 0, 0) connect io.resp.`0`.vc_sel.`0`[0], _io_resp_0_vc_sel_0_0_T node _io_resp_0_vc_sel_0_1_T = bits(decoded, 1, 1) connect io.resp.`0`.vc_sel.`0`[1], _io_resp_0_vc_sel_0_1_T node _io_resp_0_vc_sel_0_2_T = bits(decoded, 2, 2) connect io.resp.`0`.vc_sel.`0`[2], _io_resp_0_vc_sel_0_2_T node _io_resp_0_vc_sel_0_3_T = bits(decoded, 3, 3) connect io.resp.`0`.vc_sel.`0`[3], _io_resp_0_vc_sel_0_3_T node _io_resp_0_vc_sel_0_4_T = bits(decoded, 4, 4) connect io.resp.`0`.vc_sel.`0`[4], _io_resp_0_vc_sel_0_4_T node _io_resp_0_vc_sel_0_5_T = bits(decoded, 5, 5) connect io.resp.`0`.vc_sel.`0`[5], _io_resp_0_vc_sel_0_5_T connect io.resp.`0`.vc_sel.`1`[0], UInt<1>(0h0) connect io.req.`1`.ready, UInt<1>(0h1) node addr_lo_1 = cat(io.req.`1`.bits.flow.egress_node, io.req.`1`.bits.flow.egress_node_id) node addr_hi_hi_1 = cat(io.req.`1`.bits.flow.vnet_id, io.req.`1`.bits.flow.ingress_node) node addr_hi_1 = cat(addr_hi_hi_1, io.req.`1`.bits.flow.ingress_node_id) node _addr_T_1 = cat(addr_hi_1, addr_lo_1) node addr_1 = cat(io.req.`1`.bits.src_virt_id, _addr_T_1) wire decoded_plaInput_1 : UInt<17> node decoded_invInputs_1 = not(decoded_plaInput_1) wire decoded_plaOutput_1 : UInt<6> node decoded_andMatrixOutputs_andMatrixInput_0_30 = bits(decoded_invInputs_1, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_1_30 = bits(decoded_plaInput_1, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_2_30 = bits(decoded_invInputs_1, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_3_30 = bits(decoded_invInputs_1, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_4_28 = bits(decoded_plaInput_1, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_5_28 = bits(decoded_plaInput_1, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_6_28 = bits(decoded_invInputs_1, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_7_28 = bits(decoded_invInputs_1, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_8_12 = bits(decoded_invInputs_1, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_9_12 = bits(decoded_plaInput_1, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_10_12 = bits(decoded_invInputs_1, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_11_12 = bits(decoded_invInputs_1, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_12_10 = bits(decoded_invInputs_1, 16, 16) node decoded_andMatrixOutputs_lo_lo_hi_12 = cat(decoded_andMatrixOutputs_andMatrixInput_10_12, decoded_andMatrixOutputs_andMatrixInput_11_12) node decoded_andMatrixOutputs_lo_lo_28 = cat(decoded_andMatrixOutputs_lo_lo_hi_12, decoded_andMatrixOutputs_andMatrixInput_12_10) node decoded_andMatrixOutputs_lo_hi_hi_12 = cat(decoded_andMatrixOutputs_andMatrixInput_7_28, decoded_andMatrixOutputs_andMatrixInput_8_12) node decoded_andMatrixOutputs_lo_hi_28 = cat(decoded_andMatrixOutputs_lo_hi_hi_12, decoded_andMatrixOutputs_andMatrixInput_9_12) node decoded_andMatrixOutputs_lo_30 = cat(decoded_andMatrixOutputs_lo_hi_28, decoded_andMatrixOutputs_lo_lo_28) node decoded_andMatrixOutputs_hi_lo_hi_12 = cat(decoded_andMatrixOutputs_andMatrixInput_4_28, decoded_andMatrixOutputs_andMatrixInput_5_28) node decoded_andMatrixOutputs_hi_lo_28 = cat(decoded_andMatrixOutputs_hi_lo_hi_12, decoded_andMatrixOutputs_andMatrixInput_6_28) node decoded_andMatrixOutputs_hi_hi_lo_10 = cat(decoded_andMatrixOutputs_andMatrixInput_2_30, decoded_andMatrixOutputs_andMatrixInput_3_30) node decoded_andMatrixOutputs_hi_hi_hi_12 = cat(decoded_andMatrixOutputs_andMatrixInput_0_30, decoded_andMatrixOutputs_andMatrixInput_1_30) node decoded_andMatrixOutputs_hi_hi_28 = cat(decoded_andMatrixOutputs_hi_hi_hi_12, decoded_andMatrixOutputs_hi_hi_lo_10) node decoded_andMatrixOutputs_hi_30 = cat(decoded_andMatrixOutputs_hi_hi_28, decoded_andMatrixOutputs_hi_lo_28) node _decoded_andMatrixOutputs_T_30 = cat(decoded_andMatrixOutputs_hi_30, decoded_andMatrixOutputs_lo_30) node decoded_andMatrixOutputs_0_2_1 = andr(_decoded_andMatrixOutputs_T_30) node _decoded_orMatrixOutputs_T_12 = orr(decoded_andMatrixOutputs_0_2_1) node decoded_orMatrixOutputs_lo_hi_2 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_4 = cat(decoded_orMatrixOutputs_lo_hi_2, _decoded_orMatrixOutputs_T_12) node decoded_orMatrixOutputs_hi_hi_2 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_4 = cat(decoded_orMatrixOutputs_hi_hi_2, UInt<1>(0h0)) node decoded_orMatrixOutputs_1 = cat(decoded_orMatrixOutputs_hi_4, decoded_orMatrixOutputs_lo_4) node _decoded_invMatrixOutputs_T_6 = bits(decoded_orMatrixOutputs_1, 0, 0) node _decoded_invMatrixOutputs_T_7 = bits(decoded_orMatrixOutputs_1, 1, 1) node _decoded_invMatrixOutputs_T_8 = bits(decoded_orMatrixOutputs_1, 2, 2) node _decoded_invMatrixOutputs_T_9 = bits(decoded_orMatrixOutputs_1, 3, 3) node _decoded_invMatrixOutputs_T_10 = bits(decoded_orMatrixOutputs_1, 4, 4) node _decoded_invMatrixOutputs_T_11 = bits(decoded_orMatrixOutputs_1, 5, 5) node decoded_invMatrixOutputs_lo_hi_1 = cat(_decoded_invMatrixOutputs_T_8, _decoded_invMatrixOutputs_T_7) node decoded_invMatrixOutputs_lo_1 = cat(decoded_invMatrixOutputs_lo_hi_1, _decoded_invMatrixOutputs_T_6) node decoded_invMatrixOutputs_hi_hi_1 = cat(_decoded_invMatrixOutputs_T_11, _decoded_invMatrixOutputs_T_10) node decoded_invMatrixOutputs_hi_1 = cat(decoded_invMatrixOutputs_hi_hi_1, _decoded_invMatrixOutputs_T_9) node decoded_invMatrixOutputs_1 = cat(decoded_invMatrixOutputs_hi_1, decoded_invMatrixOutputs_lo_1) connect decoded_plaOutput_1, decoded_invMatrixOutputs_1 connect decoded_plaInput_1, addr_1 node _decoded_T_14 = bits(decoded_plaOutput_1, 3, 0) node _decoded_T_15 = bits(_decoded_T_14, 1, 0) node _decoded_T_16 = bits(_decoded_T_15, 0, 0) node _decoded_T_17 = bits(_decoded_T_15, 1, 1) node _decoded_T_18 = cat(_decoded_T_16, _decoded_T_17) node _decoded_T_19 = bits(_decoded_T_14, 3, 2) node _decoded_T_20 = bits(_decoded_T_19, 0, 0) node _decoded_T_21 = bits(_decoded_T_19, 1, 1) node _decoded_T_22 = cat(_decoded_T_20, _decoded_T_21) node _decoded_T_23 = cat(_decoded_T_18, _decoded_T_22) node _decoded_T_24 = bits(decoded_plaOutput_1, 5, 4) node _decoded_T_25 = bits(_decoded_T_24, 0, 0) node _decoded_T_26 = bits(_decoded_T_24, 1, 1) node _decoded_T_27 = cat(_decoded_T_25, _decoded_T_26) node decoded_1 = cat(_decoded_T_23, _decoded_T_27) node _io_resp_1_vc_sel_0_0_T = bits(decoded_1, 0, 0) connect io.resp.`1`.vc_sel.`0`[0], _io_resp_1_vc_sel_0_0_T node _io_resp_1_vc_sel_0_1_T = bits(decoded_1, 1, 1) connect io.resp.`1`.vc_sel.`0`[1], _io_resp_1_vc_sel_0_1_T node _io_resp_1_vc_sel_0_2_T = bits(decoded_1, 2, 2) connect io.resp.`1`.vc_sel.`0`[2], _io_resp_1_vc_sel_0_2_T node _io_resp_1_vc_sel_0_3_T = bits(decoded_1, 3, 3) connect io.resp.`1`.vc_sel.`0`[3], _io_resp_1_vc_sel_0_3_T node _io_resp_1_vc_sel_0_4_T = bits(decoded_1, 4, 4) connect io.resp.`1`.vc_sel.`0`[4], _io_resp_1_vc_sel_0_4_T node _io_resp_1_vc_sel_0_5_T = bits(decoded_1, 5, 5) connect io.resp.`1`.vc_sel.`0`[5], _io_resp_1_vc_sel_0_5_T connect io.resp.`1`.vc_sel.`1`[0], UInt<1>(0h0) connect io.req.`2`.ready, UInt<1>(0h1) node addr_lo_2 = cat(io.req.`2`.bits.flow.egress_node, io.req.`2`.bits.flow.egress_node_id) node addr_hi_hi_2 = cat(io.req.`2`.bits.flow.vnet_id, io.req.`2`.bits.flow.ingress_node) node addr_hi_2 = cat(addr_hi_hi_2, io.req.`2`.bits.flow.ingress_node_id) node _addr_T_2 = cat(addr_hi_2, addr_lo_2) node addr_2 = cat(io.req.`2`.bits.src_virt_id, _addr_T_2) wire decoded_plaInput_2 : UInt<17> node decoded_invInputs_2 = not(decoded_plaInput_2) wire decoded_plaOutput_2 : UInt<6> node _decoded_orMatrixOutputs_T_13 = orr(UInt<1>(0h1)) node decoded_orMatrixOutputs_lo_hi_3 = cat(_decoded_orMatrixOutputs_T_13, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_5 = cat(decoded_orMatrixOutputs_lo_hi_3, UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_hi_3 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_5 = cat(decoded_orMatrixOutputs_hi_hi_3, UInt<1>(0h0)) node decoded_orMatrixOutputs_2 = cat(decoded_orMatrixOutputs_hi_5, decoded_orMatrixOutputs_lo_5) node _decoded_invMatrixOutputs_T_12 = bits(decoded_orMatrixOutputs_2, 0, 0) node _decoded_invMatrixOutputs_T_13 = bits(decoded_orMatrixOutputs_2, 1, 1) node _decoded_invMatrixOutputs_T_14 = bits(decoded_orMatrixOutputs_2, 2, 2) node _decoded_invMatrixOutputs_T_15 = bits(decoded_orMatrixOutputs_2, 3, 3) node _decoded_invMatrixOutputs_T_16 = bits(decoded_orMatrixOutputs_2, 4, 4) node _decoded_invMatrixOutputs_T_17 = bits(decoded_orMatrixOutputs_2, 5, 5) node decoded_invMatrixOutputs_lo_hi_2 = cat(_decoded_invMatrixOutputs_T_14, _decoded_invMatrixOutputs_T_13) node decoded_invMatrixOutputs_lo_2 = cat(decoded_invMatrixOutputs_lo_hi_2, _decoded_invMatrixOutputs_T_12) node decoded_invMatrixOutputs_hi_hi_2 = cat(_decoded_invMatrixOutputs_T_17, _decoded_invMatrixOutputs_T_16) node decoded_invMatrixOutputs_hi_2 = cat(decoded_invMatrixOutputs_hi_hi_2, _decoded_invMatrixOutputs_T_15) node decoded_invMatrixOutputs_2 = cat(decoded_invMatrixOutputs_hi_2, decoded_invMatrixOutputs_lo_2) connect decoded_plaOutput_2, decoded_invMatrixOutputs_2 connect decoded_plaInput_2, addr_2 node _decoded_T_28 = bits(decoded_plaOutput_2, 3, 0) node _decoded_T_29 = bits(_decoded_T_28, 1, 0) node _decoded_T_30 = bits(_decoded_T_29, 0, 0) node _decoded_T_31 = bits(_decoded_T_29, 1, 1) node _decoded_T_32 = cat(_decoded_T_30, _decoded_T_31) node _decoded_T_33 = bits(_decoded_T_28, 3, 2) node _decoded_T_34 = bits(_decoded_T_33, 0, 0) node _decoded_T_35 = bits(_decoded_T_33, 1, 1) node _decoded_T_36 = cat(_decoded_T_34, _decoded_T_35) node _decoded_T_37 = cat(_decoded_T_32, _decoded_T_36) node _decoded_T_38 = bits(decoded_plaOutput_2, 5, 4) node _decoded_T_39 = bits(_decoded_T_38, 0, 0) node _decoded_T_40 = bits(_decoded_T_38, 1, 1) node _decoded_T_41 = cat(_decoded_T_39, _decoded_T_40) node decoded_2 = cat(_decoded_T_37, _decoded_T_41) node _io_resp_2_vc_sel_0_0_T = bits(decoded_2, 0, 0) connect io.resp.`2`.vc_sel.`0`[0], _io_resp_2_vc_sel_0_0_T node _io_resp_2_vc_sel_0_1_T = bits(decoded_2, 1, 1) connect io.resp.`2`.vc_sel.`0`[1], _io_resp_2_vc_sel_0_1_T node _io_resp_2_vc_sel_0_2_T = bits(decoded_2, 2, 2) connect io.resp.`2`.vc_sel.`0`[2], _io_resp_2_vc_sel_0_2_T node _io_resp_2_vc_sel_0_3_T = bits(decoded_2, 3, 3) connect io.resp.`2`.vc_sel.`0`[3], _io_resp_2_vc_sel_0_3_T node _io_resp_2_vc_sel_0_4_T = bits(decoded_2, 4, 4) connect io.resp.`2`.vc_sel.`0`[4], _io_resp_2_vc_sel_0_4_T node _io_resp_2_vc_sel_0_5_T = bits(decoded_2, 5, 5) connect io.resp.`2`.vc_sel.`0`[5], _io_resp_2_vc_sel_0_5_T connect io.resp.`2`.vc_sel.`1`[0], UInt<1>(0h0) extmodule plusarg_reader_21 : output out : UInt<20> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "noc_util_sample_rate=%d" parameter WIDTH = 20	module RouteComputer_3( // @[RouteComputer.scala:29:7] input [3:0] io_req_1_bits_flow_egress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_1_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14] input [2:0] io_req_0_bits_src_virt_id, // @[RouteComputer.scala:40:14] input [1:0] io_req_0_bits_flow_vnet_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_0_bits_flow_ingress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_0_bits_flow_ingress_node_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_0_bits_flow_egress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_0_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_0, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_1, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_2, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_3, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_4, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_5, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_0_0, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_0_1, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_0_2, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_0_3, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_0_4, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_0_5 // @[RouteComputer.scala:40:14] ); wire [16:0] decoded_invInputs = ~{io_req_0_bits_src_virt_id, io_req_0_bits_flow_vnet_id, io_req_0_bits_flow_ingress_node, io_req_0_bits_flow_ingress_node_id, io_req_0_bits_flow_egress_node, io_req_0_bits_flow_egress_node_id}; // @[pla.scala:78:21] assign io_resp_1_vc_sel_0_0 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_1_vc_sel_0_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_1_vc_sel_0_2 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_1_vc_sel_0_3 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_1_vc_sel_0_4 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_1_vc_sel_0_5 = &{~(io_req_1_bits_flow_egress_node_id[1]), io_req_1_bits_flow_egress_node[3]}; // @[pla.scala:78:21, :90:45, :98:{53,70}] assign io_resp_0_vc_sel_0_0 = \|{&{decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[2], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[3], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[15]}, &{decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[2], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[3], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[16]}, &{decoded_invInputs[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[2], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[3], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[15]}, &{decoded_invInputs[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[2], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[3], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[16]}, &{decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[5], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[1], decoded_invInputs[8], decoded_invInputs[9], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[3], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[14], decoded_invInputs[15]}, &{decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[5], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[1], decoded_invInputs[8], decoded_invInputs[9], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[3], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[14], decoded_invInputs[16]}, &{decoded_invInputs[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[0], decoded_invInputs[5], decoded_invInputs[6], decoded_invInputs[7], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[3], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[14], decoded_invInputs[15]}, &{decoded_invInputs[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[0], decoded_invInputs[5], decoded_invInputs[6], decoded_invInputs[7], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[3], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[14], decoded_invInputs[16]}, &{decoded_invInputs[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[0], decoded_invInputs[5], decoded_invInputs[6], decoded_invInputs[7], io_req_0_bits_flow_ingress_node[1], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[3], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[14], decoded_invInputs[15]}, &{decoded_invInputs[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[0], decoded_invInputs[5], decoded_invInputs[6], decoded_invInputs[7], io_req_0_bits_flow_ingress_node[1], decoded_invInputs[10], io_req_0_bits_flow_ingress_node[3], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[14], decoded_invInputs[16]}, &{decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[5], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[2], io_req_0_bits_flow_ingress_node[3], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[14], decoded_invInputs[15]}, &{decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[5], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[2], io_req_0_bits_flow_ingress_node[3], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[14], decoded_invInputs[16]}, &{decoded_invInputs[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[2], decoded_invInputs[5], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[2], io_req_0_bits_flow_ingress_node[3], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[15]}, &{decoded_invInputs[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[2], decoded_invInputs[5], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[2], io_req_0_bits_flow_ingress_node[3], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[16]}, &{decoded_invInputs[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[3], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[2], io_req_0_bits_flow_ingress_node[3], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[15]}, &{decoded_invInputs[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[3], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[2], io_req_0_bits_flow_ingress_node[3], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[16]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_0_1 = \|{&{decoded_invInputs[0], decoded_invInputs[13], io_req_0_bits_src_virt_id[0], decoded_invInputs[15]}, &{decoded_invInputs[0], decoded_invInputs[13], io_req_0_bits_src_virt_id[0], decoded_invInputs[16]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_0_2 = \|{&{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[3], decoded_invInputs[10], decoded_invInputs[11], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[13], decoded_invInputs[15]}, &{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[3], decoded_invInputs[10], decoded_invInputs[11], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[13], decoded_invInputs[16]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_0_3 = \|{&{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], decoded_invInputs[10], decoded_invInputs[11], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[13], io_req_0_bits_src_virt_id[0], decoded_invInputs[15]}, &{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], decoded_invInputs[10], decoded_invInputs[11], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[13], io_req_0_bits_src_virt_id[0], decoded_invInputs[16]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_0_4 = \|{&{decoded_invInputs[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[3], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[15]}, &{decoded_invInputs[1], decoded_invInputs[2], io_req_0_bits_flow_egress_node[3], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[15]}, &{decoded_invInputs[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[3], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16]}, &{decoded_invInputs[1], decoded_invInputs[2], io_req_0_bits_flow_egress_node[3], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_0_5 = \|{&{decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_vnet_id[1], io_req_0_bits_src_virt_id[0], decoded_invInputs[15]}, &{decoded_invInputs[1], decoded_invInputs[4], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_vnet_id[1], io_req_0_bits_src_virt_id[0], decoded_invInputs[15]}, &{decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_vnet_id[1], io_req_0_bits_src_virt_id[0], decoded_invInputs[16]}, &{decoded_invInputs[1], decoded_invInputs[4], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_vnet_id[1], io_req_0_bits_src_virt_id[0], decoded_invInputs[16]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PriorityQueueStage_100 : input clock : Clock input reset : Reset output io : { output_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, output_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip cmd : { valid : UInt<1>, bits : UInt<1>}, flip insert_here : UInt<1>, flip cur_input_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}, cur_output_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}} regreset key_reg : UInt<31>, clock, reset, UInt<31>(0h7fffffff) reg value_reg : { symbol : UInt<10>}, clock connect io.output_prev.key, key_reg connect io.output_prev.value, value_reg connect io.output_nxt.key, key_reg connect io.output_nxt.value, value_reg connect io.cur_output_keyval.key, key_reg connect io.cur_output_keyval.value, value_reg when io.cmd.valid : node _T = eq(UInt<1>(0h0), io.cmd.bits) when _T : connect key_reg, io.input_nxt.key connect value_reg, io.input_nxt.value else : node _T_1 = eq(UInt<1>(0h1), io.cmd.bits) when _T_1 : when io.insert_here : connect key_reg, io.cur_input_keyval.key connect value_reg, io.cur_input_keyval.value else : node _T_2 = geq(key_reg, io.cur_input_keyval.key) when _T_2 : connect key_reg, io.input_prev.key connect value_reg, io.input_prev.value else : skip	module PriorityQueueStage_100( // @[ShiftRegisterPriorityQueue.scala:21:7] input clock, // @[ShiftRegisterPriorityQueue.scala:21:7] input reset, // @[ShiftRegisterPriorityQueue.scala:21:7] output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14] ); wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24] assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22] assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30] always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24] else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end else // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end else // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end always @(posedge) assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module BranchDecode_8 : input clock : Clock input reset : Reset output io : { flip inst : UInt<32>, flip pc : UInt<40>, out : { is_ret : UInt<1>, is_call : UInt<1>, target : UInt<40>, cfi_type : UInt<3>, sfb_offset : { valid : UInt<1>, bits : UInt<6>}, shadowable : UInt<1>}} wire bpd_csignals_decoded_plaInput : UInt<32> node bpd_csignals_decoded_invInputs = not(bpd_csignals_decoded_plaInput) wire bpd_csignals_decoded : UInt<5> node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0 = bits(bpd_csignals_decoded_plaInput, 0, 0) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1 = bits(bpd_csignals_decoded_plaInput, 1, 1) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2 = bits(bpd_csignals_decoded_invInputs, 2, 2) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3 = bits(bpd_csignals_decoded_invInputs, 3, 3) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4 = bits(bpd_csignals_decoded_plaInput, 4, 4) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5 = bits(bpd_csignals_decoded_invInputs, 5, 5) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6 = bits(bpd_csignals_decoded_invInputs, 6, 6) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7 = bits(bpd_csignals_decoded_invInputs, 12, 12) node bpd_csignals_decoded_andMatrixOutputs_lo_lo = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7) node bpd_csignals_decoded_andMatrixOutputs_lo_hi = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5) node bpd_csignals_decoded_andMatrixOutputs_lo = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi, bpd_csignals_decoded_andMatrixOutputs_lo_lo) node bpd_csignals_decoded_andMatrixOutputs_hi_lo = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3) node bpd_csignals_decoded_andMatrixOutputs_hi_hi = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1) node bpd_csignals_decoded_andMatrixOutputs_hi = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi, bpd_csignals_decoded_andMatrixOutputs_hi_lo) node _bpd_csignals_decoded_andMatrixOutputs_T = cat(bpd_csignals_decoded_andMatrixOutputs_hi, bpd_csignals_decoded_andMatrixOutputs_lo) node bpd_csignals_decoded_andMatrixOutputs_5_2 = andr(_bpd_csignals_decoded_andMatrixOutputs_T) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_1 = bits(bpd_csignals_decoded_plaInput, 0, 0) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_1 = bits(bpd_csignals_decoded_plaInput, 1, 1) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_1 = bits(bpd_csignals_decoded_invInputs, 2, 2) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_1 = bits(bpd_csignals_decoded_plaInput, 4, 4) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_1 = bits(bpd_csignals_decoded_invInputs, 5, 5) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_1 = bits(bpd_csignals_decoded_invInputs, 6, 6) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_1 = bits(bpd_csignals_decoded_invInputs, 12, 12) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_1 = bits(bpd_csignals_decoded_invInputs, 13, 13) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8 = bits(bpd_csignals_decoded_invInputs, 14, 14) node bpd_csignals_decoded_andMatrixOutputs_lo_lo_1 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_1 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_1) node bpd_csignals_decoded_andMatrixOutputs_lo_1 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_1, bpd_csignals_decoded_andMatrixOutputs_lo_lo_1) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_1 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_1) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_1) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_1 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_1) node bpd_csignals_decoded_andMatrixOutputs_hi_1 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_1, bpd_csignals_decoded_andMatrixOutputs_hi_lo_1) node _bpd_csignals_decoded_andMatrixOutputs_T_1 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_1, bpd_csignals_decoded_andMatrixOutputs_lo_1) node bpd_csignals_decoded_andMatrixOutputs_9_2 = andr(_bpd_csignals_decoded_andMatrixOutputs_T_1) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_2 = bits(bpd_csignals_decoded_plaInput, 0, 0) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_2 = bits(bpd_csignals_decoded_plaInput, 1, 1) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_2 = bits(bpd_csignals_decoded_invInputs, 2, 2) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_2 = bits(bpd_csignals_decoded_plaInput, 4, 4) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_2 = bits(bpd_csignals_decoded_plaInput, 5, 5) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_2 = bits(bpd_csignals_decoded_invInputs, 6, 6) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_2 = bits(bpd_csignals_decoded_invInputs, 12, 12) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_2 = bits(bpd_csignals_decoded_invInputs, 13, 13) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_1 = bits(bpd_csignals_decoded_invInputs, 14, 14) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9 = bits(bpd_csignals_decoded_invInputs, 25, 25) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10 = bits(bpd_csignals_decoded_invInputs, 26, 26) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11 = bits(bpd_csignals_decoded_invInputs, 27, 27) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12 = bits(bpd_csignals_decoded_invInputs, 28, 28) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13 = bits(bpd_csignals_decoded_invInputs, 29, 29) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14 = bits(bpd_csignals_decoded_invInputs, 31, 31) node bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13) node bpd_csignals_decoded_andMatrixOutputs_lo_lo_2 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_2 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo) node bpd_csignals_decoded_andMatrixOutputs_lo_2 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_2, bpd_csignals_decoded_andMatrixOutputs_lo_lo_2) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_2) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_2) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_2 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_2) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_1 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_2) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_2 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_1, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo) node bpd_csignals_decoded_andMatrixOutputs_hi_2 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_2, bpd_csignals_decoded_andMatrixOutputs_hi_lo_2) node _bpd_csignals_decoded_andMatrixOutputs_T_2 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_2, bpd_csignals_decoded_andMatrixOutputs_lo_2) node bpd_csignals_decoded_andMatrixOutputs_14_2 = andr(_bpd_csignals_decoded_andMatrixOutputs_T_2) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_3 = bits(bpd_csignals_decoded_plaInput, 0, 0) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_3 = bits(bpd_csignals_decoded_plaInput, 1, 1) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_3 = bits(bpd_csignals_decoded_invInputs, 2, 2) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_3 = bits(bpd_csignals_decoded_invInputs, 3, 3) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_3 = bits(bpd_csignals_decoded_plaInput, 4, 4) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_3 = bits(bpd_csignals_decoded_plaInput, 5, 5) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_3 = bits(bpd_csignals_decoded_invInputs, 6, 6) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_3 = bits(bpd_csignals_decoded_invInputs, 25, 25) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_2 = bits(bpd_csignals_decoded_invInputs, 26, 26) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_1 = bits(bpd_csignals_decoded_invInputs, 27, 27) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_1 = bits(bpd_csignals_decoded_invInputs, 28, 28) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_1 = bits(bpd_csignals_decoded_invInputs, 29, 29) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_1 = bits(bpd_csignals_decoded_invInputs, 30, 30) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_1 = bits(bpd_csignals_decoded_invInputs, 31, 31) node bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_1 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_1) node bpd_csignals_decoded_andMatrixOutputs_lo_lo_3 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_1) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_1 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_1) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_1 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_2) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_3 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_1, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_1) node bpd_csignals_decoded_andMatrixOutputs_lo_3 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_3, bpd_csignals_decoded_andMatrixOutputs_lo_lo_3) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_1 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_3) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_3 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_3) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_1 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_3) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_2 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_3) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_3 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_2, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_1) node bpd_csignals_decoded_andMatrixOutputs_hi_3 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_3, bpd_csignals_decoded_andMatrixOutputs_hi_lo_3) node _bpd_csignals_decoded_andMatrixOutputs_T_3 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_3, bpd_csignals_decoded_andMatrixOutputs_lo_3) node bpd_csignals_decoded_andMatrixOutputs_0_2 = andr(_bpd_csignals_decoded_andMatrixOutputs_T_3) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_4 = bits(bpd_csignals_decoded_plaInput, 0, 0) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_4 = bits(bpd_csignals_decoded_plaInput, 1, 1) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_4 = bits(bpd_csignals_decoded_invInputs, 2, 2) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_4 = bits(bpd_csignals_decoded_plaInput, 4, 4) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_4 = bits(bpd_csignals_decoded_plaInput, 5, 5) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_4 = bits(bpd_csignals_decoded_invInputs, 6, 6) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_4 = bits(bpd_csignals_decoded_invInputs, 13, 13) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_4 = bits(bpd_csignals_decoded_invInputs, 14, 14) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_3 = bits(bpd_csignals_decoded_invInputs, 25, 25) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_2 = bits(bpd_csignals_decoded_invInputs, 26, 26) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_2 = bits(bpd_csignals_decoded_invInputs, 27, 27) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_2 = bits(bpd_csignals_decoded_invInputs, 28, 28) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_2 = bits(bpd_csignals_decoded_invInputs, 29, 29) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_2 = bits(bpd_csignals_decoded_invInputs, 30, 30) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_1 = bits(bpd_csignals_decoded_invInputs, 31, 31) node bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_2 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_2) node bpd_csignals_decoded_andMatrixOutputs_lo_lo_4 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_1) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_2 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_2) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_2 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_2) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_4 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_2, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_2) node bpd_csignals_decoded_andMatrixOutputs_lo_4 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_4, bpd_csignals_decoded_andMatrixOutputs_lo_lo_4) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_1 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_4) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_2 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_4) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_4 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_2, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_1) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_2 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_4) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_3 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_4) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_4 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_3, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_2) node bpd_csignals_decoded_andMatrixOutputs_hi_4 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_4, bpd_csignals_decoded_andMatrixOutputs_hi_lo_4) node _bpd_csignals_decoded_andMatrixOutputs_T_4 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_4, bpd_csignals_decoded_andMatrixOutputs_lo_4) node bpd_csignals_decoded_andMatrixOutputs_2_2 = andr(_bpd_csignals_decoded_andMatrixOutputs_T_4) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_5 = bits(bpd_csignals_decoded_plaInput, 0, 0) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_5 = bits(bpd_csignals_decoded_plaInput, 1, 1) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_5 = bits(bpd_csignals_decoded_plaInput, 2, 2) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_5 = bits(bpd_csignals_decoded_invInputs, 3, 3) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_5 = bits(bpd_csignals_decoded_plaInput, 4, 4) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_5 = bits(bpd_csignals_decoded_plaInput, 5, 5) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_5 = bits(bpd_csignals_decoded_invInputs, 6, 6) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_5 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_5) node bpd_csignals_decoded_andMatrixOutputs_lo_5 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_5) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_5 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_5) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_5 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_5) node bpd_csignals_decoded_andMatrixOutputs_hi_5 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_5, bpd_csignals_decoded_andMatrixOutputs_hi_lo_5) node _bpd_csignals_decoded_andMatrixOutputs_T_5 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_5, bpd_csignals_decoded_andMatrixOutputs_lo_5) node bpd_csignals_decoded_andMatrixOutputs_12_2 = andr(_bpd_csignals_decoded_andMatrixOutputs_T_5) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_6 = bits(bpd_csignals_decoded_plaInput, 0, 0) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_6 = bits(bpd_csignals_decoded_plaInput, 1, 1) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_6 = bits(bpd_csignals_decoded_invInputs, 2, 2) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_6 = bits(bpd_csignals_decoded_invInputs, 3, 3) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_6 = bits(bpd_csignals_decoded_invInputs, 4, 4) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_6 = bits(bpd_csignals_decoded_plaInput, 5, 5) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_6 = bits(bpd_csignals_decoded_plaInput, 6, 6) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_5 = bits(bpd_csignals_decoded_invInputs, 13, 13) node bpd_csignals_decoded_andMatrixOutputs_lo_lo_5 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_5) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_6 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_6) node bpd_csignals_decoded_andMatrixOutputs_lo_6 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_6, bpd_csignals_decoded_andMatrixOutputs_lo_lo_5) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_6 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_6) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_6 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_6) node bpd_csignals_decoded_andMatrixOutputs_hi_6 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_6, bpd_csignals_decoded_andMatrixOutputs_hi_lo_6) node _bpd_csignals_decoded_andMatrixOutputs_T_6 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_6, bpd_csignals_decoded_andMatrixOutputs_lo_6) node bpd_csignals_decoded_andMatrixOutputs_6_2 = andr(_bpd_csignals_decoded_andMatrixOutputs_T_6) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_7 = bits(bpd_csignals_decoded_plaInput, 0, 0) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_7 = bits(bpd_csignals_decoded_plaInput, 1, 1) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_7 = bits(bpd_csignals_decoded_plaInput, 2, 2) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_7 = bits(bpd_csignals_decoded_invInputs, 3, 3) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_7 = bits(bpd_csignals_decoded_invInputs, 4, 4) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_7 = bits(bpd_csignals_decoded_plaInput, 5, 5) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_7 = bits(bpd_csignals_decoded_plaInput, 6, 6) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_6 = bits(bpd_csignals_decoded_invInputs, 12, 12) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_4 = bits(bpd_csignals_decoded_invInputs, 13, 13) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_3 = bits(bpd_csignals_decoded_invInputs, 14, 14) node bpd_csignals_decoded_andMatrixOutputs_lo_lo_6 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_3) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_3 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_7) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_7 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_6) node bpd_csignals_decoded_andMatrixOutputs_lo_7 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_7, bpd_csignals_decoded_andMatrixOutputs_lo_lo_6) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_7 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_7) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_4 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_7) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_7 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_7) node bpd_csignals_decoded_andMatrixOutputs_hi_7 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_7, bpd_csignals_decoded_andMatrixOutputs_hi_lo_7) node _bpd_csignals_decoded_andMatrixOutputs_T_7 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_7, bpd_csignals_decoded_andMatrixOutputs_lo_7) node bpd_csignals_decoded_andMatrixOutputs_15_2 = andr(_bpd_csignals_decoded_andMatrixOutputs_T_7) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_8 = bits(bpd_csignals_decoded_plaInput, 0, 0) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_8 = bits(bpd_csignals_decoded_plaInput, 1, 1) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_8 = bits(bpd_csignals_decoded_plaInput, 2, 2) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_8 = bits(bpd_csignals_decoded_plaInput, 3, 3) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_8 = bits(bpd_csignals_decoded_invInputs, 4, 4) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_8 = bits(bpd_csignals_decoded_plaInput, 5, 5) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_8 = bits(bpd_csignals_decoded_plaInput, 6, 6) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_8 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_8, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_8) node bpd_csignals_decoded_andMatrixOutputs_lo_8 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_8, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_8) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_8 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_8, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_8) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_8 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_8, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_8) node bpd_csignals_decoded_andMatrixOutputs_hi_8 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_8, bpd_csignals_decoded_andMatrixOutputs_hi_lo_8) node _bpd_csignals_decoded_andMatrixOutputs_T_8 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_8, bpd_csignals_decoded_andMatrixOutputs_lo_8) node bpd_csignals_decoded_andMatrixOutputs_11_2 = andr(_bpd_csignals_decoded_andMatrixOutputs_T_8) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_9 = bits(bpd_csignals_decoded_plaInput, 0, 0) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_9 = bits(bpd_csignals_decoded_plaInput, 1, 1) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_9 = bits(bpd_csignals_decoded_invInputs, 2, 2) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_9 = bits(bpd_csignals_decoded_invInputs, 3, 3) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_9 = bits(bpd_csignals_decoded_plaInput, 4, 4) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_9 = bits(bpd_csignals_decoded_invInputs, 5, 5) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_9 = bits(bpd_csignals_decoded_invInputs, 6, 6) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_7 = bits(bpd_csignals_decoded_plaInput, 12, 12) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_5 = bits(bpd_csignals_decoded_invInputs, 13, 13) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_4 = bits(bpd_csignals_decoded_invInputs, 26, 26) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_3 = bits(bpd_csignals_decoded_invInputs, 27, 27) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_3 = bits(bpd_csignals_decoded_invInputs, 28, 28) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_3 = bits(bpd_csignals_decoded_invInputs, 29, 29) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_3 = bits(bpd_csignals_decoded_invInputs, 30, 30) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_2 = bits(bpd_csignals_decoded_invInputs, 31, 31) node bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_3 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_3) node bpd_csignals_decoded_andMatrixOutputs_lo_lo_7 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_2) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_3 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_3) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_4 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_4) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_9 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_4, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_3) node bpd_csignals_decoded_andMatrixOutputs_lo_9 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_9, bpd_csignals_decoded_andMatrixOutputs_lo_lo_7) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_2 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_9, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_7) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_3 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_9, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_9) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_9 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_3, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_2) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_3 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_9, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_9) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_5 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_9, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_9) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_9 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_5, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_3) node bpd_csignals_decoded_andMatrixOutputs_hi_9 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_9, bpd_csignals_decoded_andMatrixOutputs_hi_lo_9) node _bpd_csignals_decoded_andMatrixOutputs_T_9 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_9, bpd_csignals_decoded_andMatrixOutputs_lo_9) node bpd_csignals_decoded_andMatrixOutputs_3_2 = andr(_bpd_csignals_decoded_andMatrixOutputs_T_9) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_10 = bits(bpd_csignals_decoded_plaInput, 0, 0) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_10 = bits(bpd_csignals_decoded_plaInput, 1, 1) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_10 = bits(bpd_csignals_decoded_invInputs, 2, 2) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_10 = bits(bpd_csignals_decoded_plaInput, 3, 3) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_10 = bits(bpd_csignals_decoded_plaInput, 4, 4) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_10 = bits(bpd_csignals_decoded_invInputs, 6, 6) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_10 = bits(bpd_csignals_decoded_plaInput, 12, 12) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_8 = bits(bpd_csignals_decoded_invInputs, 13, 13) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_6 = bits(bpd_csignals_decoded_invInputs, 25, 25) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_5 = bits(bpd_csignals_decoded_invInputs, 26, 26) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_4 = bits(bpd_csignals_decoded_invInputs, 27, 27) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_4 = bits(bpd_csignals_decoded_invInputs, 28, 28) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_4 = bits(bpd_csignals_decoded_invInputs, 29, 29) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_4 = bits(bpd_csignals_decoded_invInputs, 30, 30) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_3 = bits(bpd_csignals_decoded_invInputs, 31, 31) node bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_4 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_4) node bpd_csignals_decoded_andMatrixOutputs_lo_lo_8 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_3) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_4 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_4) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_5 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_5) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_10 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_5, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_4) node bpd_csignals_decoded_andMatrixOutputs_lo_10 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_10, bpd_csignals_decoded_andMatrixOutputs_lo_lo_8) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_3 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_10, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_8) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_4 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_10, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_10) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_10 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_4, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_3) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_4 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_10, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_10) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_6 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_10, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_10) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_10 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_6, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_4) node bpd_csignals_decoded_andMatrixOutputs_hi_10 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_10, bpd_csignals_decoded_andMatrixOutputs_hi_lo_10) node _bpd_csignals_decoded_andMatrixOutputs_T_10 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_10, bpd_csignals_decoded_andMatrixOutputs_lo_10) node bpd_csignals_decoded_andMatrixOutputs_7_2 = andr(_bpd_csignals_decoded_andMatrixOutputs_T_10) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_11 = bits(bpd_csignals_decoded_plaInput, 0, 0) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_11 = bits(bpd_csignals_decoded_plaInput, 1, 1) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_11 = bits(bpd_csignals_decoded_invInputs, 2, 2) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_11 = bits(bpd_csignals_decoded_invInputs, 3, 3) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_11 = bits(bpd_csignals_decoded_plaInput, 4, 4) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_11 = bits(bpd_csignals_decoded_invInputs, 5, 5) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_11 = bits(bpd_csignals_decoded_invInputs, 6, 6) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_9 = bits(bpd_csignals_decoded_plaInput, 13, 13) node bpd_csignals_decoded_andMatrixOutputs_lo_lo_9 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_11, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_9) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_11 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_11, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_11) node bpd_csignals_decoded_andMatrixOutputs_lo_11 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_11, bpd_csignals_decoded_andMatrixOutputs_lo_lo_9) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_11 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_11, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_11) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_11 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_11, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_11) node bpd_csignals_decoded_andMatrixOutputs_hi_11 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_11, bpd_csignals_decoded_andMatrixOutputs_hi_lo_11) node _bpd_csignals_decoded_andMatrixOutputs_T_11 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_11, bpd_csignals_decoded_andMatrixOutputs_lo_11) node bpd_csignals_decoded_andMatrixOutputs_1_2 = andr(_bpd_csignals_decoded_andMatrixOutputs_T_11) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_12 = bits(bpd_csignals_decoded_plaInput, 0, 0) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_12 = bits(bpd_csignals_decoded_plaInput, 1, 1) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_12 = bits(bpd_csignals_decoded_invInputs, 2, 2) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_12 = bits(bpd_csignals_decoded_invInputs, 3, 3) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_12 = bits(bpd_csignals_decoded_invInputs, 4, 4) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_12 = bits(bpd_csignals_decoded_plaInput, 5, 5) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_12 = bits(bpd_csignals_decoded_plaInput, 6, 6) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_10 = bits(bpd_csignals_decoded_plaInput, 14, 14) node bpd_csignals_decoded_andMatrixOutputs_lo_lo_10 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_12, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_10) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_12 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_12, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_12) node bpd_csignals_decoded_andMatrixOutputs_lo_12 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_12, bpd_csignals_decoded_andMatrixOutputs_lo_lo_10) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_12 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_12, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_12) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_12 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_12, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_12) node bpd_csignals_decoded_andMatrixOutputs_hi_12 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_12, bpd_csignals_decoded_andMatrixOutputs_hi_lo_12) node _bpd_csignals_decoded_andMatrixOutputs_T_12 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_12, bpd_csignals_decoded_andMatrixOutputs_lo_12) node bpd_csignals_decoded_andMatrixOutputs_13_2 = andr(_bpd_csignals_decoded_andMatrixOutputs_T_12) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_13 = bits(bpd_csignals_decoded_plaInput, 0, 0) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_13 = bits(bpd_csignals_decoded_plaInput, 1, 1) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_13 = bits(bpd_csignals_decoded_invInputs, 2, 2) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_13 = bits(bpd_csignals_decoded_invInputs, 3, 3) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_13 = bits(bpd_csignals_decoded_plaInput, 4, 4) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_13 = bits(bpd_csignals_decoded_invInputs, 5, 5) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_13 = bits(bpd_csignals_decoded_invInputs, 6, 6) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_11 = bits(bpd_csignals_decoded_plaInput, 12, 12) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_7 = bits(bpd_csignals_decoded_invInputs, 13, 13) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_6 = bits(bpd_csignals_decoded_plaInput, 14, 14) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_5 = bits(bpd_csignals_decoded_invInputs, 26, 26) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_5 = bits(bpd_csignals_decoded_invInputs, 27, 27) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_5 = bits(bpd_csignals_decoded_invInputs, 28, 28) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_5 = bits(bpd_csignals_decoded_invInputs, 29, 29) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_4 = bits(bpd_csignals_decoded_invInputs, 31, 31) node bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_5 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_5) node bpd_csignals_decoded_andMatrixOutputs_lo_lo_11 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_4) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_5 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_5) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_6 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_6) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_13 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_6, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_5) node bpd_csignals_decoded_andMatrixOutputs_lo_13 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_13, bpd_csignals_decoded_andMatrixOutputs_lo_lo_11) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_4 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_13, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_11) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_5 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_13, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_13) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_13 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_5, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_4) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_5 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_13, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_13) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_7 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_13, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_13) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_13 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_7, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_5) node bpd_csignals_decoded_andMatrixOutputs_hi_13 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_13, bpd_csignals_decoded_andMatrixOutputs_hi_lo_13) node _bpd_csignals_decoded_andMatrixOutputs_T_13 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_13, bpd_csignals_decoded_andMatrixOutputs_lo_13) node bpd_csignals_decoded_andMatrixOutputs_4_2 = andr(_bpd_csignals_decoded_andMatrixOutputs_T_13) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_14 = bits(bpd_csignals_decoded_plaInput, 0, 0) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_14 = bits(bpd_csignals_decoded_plaInput, 1, 1) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_14 = bits(bpd_csignals_decoded_invInputs, 2, 2) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_14 = bits(bpd_csignals_decoded_plaInput, 3, 3) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_14 = bits(bpd_csignals_decoded_plaInput, 4, 4) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_14 = bits(bpd_csignals_decoded_invInputs, 6, 6) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_14 = bits(bpd_csignals_decoded_plaInput, 12, 12) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_12 = bits(bpd_csignals_decoded_invInputs, 13, 13) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_8 = bits(bpd_csignals_decoded_plaInput, 14, 14) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_7 = bits(bpd_csignals_decoded_invInputs, 25, 25) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_6 = bits(bpd_csignals_decoded_invInputs, 26, 26) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_6 = bits(bpd_csignals_decoded_invInputs, 27, 27) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_6 = bits(bpd_csignals_decoded_invInputs, 28, 28) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_6 = bits(bpd_csignals_decoded_invInputs, 29, 29) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_5 = bits(bpd_csignals_decoded_invInputs, 31, 31) node bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_6 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_6) node bpd_csignals_decoded_andMatrixOutputs_lo_lo_12 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_5) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_6 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_6) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_7 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_8, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_7) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_14 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_7, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_6) node bpd_csignals_decoded_andMatrixOutputs_lo_14 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_14, bpd_csignals_decoded_andMatrixOutputs_lo_lo_12) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_5 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_14, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_12) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_6 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_14, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_14) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_14 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_6, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_5) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_6 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_14, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_14) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_8 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_14, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_14) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_14 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_8, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_6) node bpd_csignals_decoded_andMatrixOutputs_hi_14 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_14, bpd_csignals_decoded_andMatrixOutputs_hi_lo_14) node _bpd_csignals_decoded_andMatrixOutputs_T_14 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_14, bpd_csignals_decoded_andMatrixOutputs_lo_14) node bpd_csignals_decoded_andMatrixOutputs_8_2 = andr(_bpd_csignals_decoded_andMatrixOutputs_T_14) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_15 = bits(bpd_csignals_decoded_plaInput, 0, 0) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_15 = bits(bpd_csignals_decoded_plaInput, 1, 1) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_15 = bits(bpd_csignals_decoded_invInputs, 2, 2) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_15 = bits(bpd_csignals_decoded_plaInput, 4, 4) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_15 = bits(bpd_csignals_decoded_plaInput, 5, 5) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_15 = bits(bpd_csignals_decoded_invInputs, 6, 6) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_15 = bits(bpd_csignals_decoded_plaInput, 12, 12) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_13 = bits(bpd_csignals_decoded_invInputs, 13, 13) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_9 = bits(bpd_csignals_decoded_plaInput, 14, 14) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_8 = bits(bpd_csignals_decoded_invInputs, 25, 25) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_7 = bits(bpd_csignals_decoded_invInputs, 26, 26) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_7 = bits(bpd_csignals_decoded_invInputs, 27, 27) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_7 = bits(bpd_csignals_decoded_invInputs, 28, 28) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_7 = bits(bpd_csignals_decoded_invInputs, 29, 29) node bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_6 = bits(bpd_csignals_decoded_invInputs, 31, 31) node bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_7 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_7) node bpd_csignals_decoded_andMatrixOutputs_lo_lo_13 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_6) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_7 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_7) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_8 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_9, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_8) node bpd_csignals_decoded_andMatrixOutputs_lo_hi_15 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_8, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_7) node bpd_csignals_decoded_andMatrixOutputs_lo_15 = cat(bpd_csignals_decoded_andMatrixOutputs_lo_hi_15, bpd_csignals_decoded_andMatrixOutputs_lo_lo_13) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_6 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_15, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_13) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_7 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_15, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_15) node bpd_csignals_decoded_andMatrixOutputs_hi_lo_15 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_7, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_6) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_7 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_15, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_15) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_9 = cat(bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_15, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_15) node bpd_csignals_decoded_andMatrixOutputs_hi_hi_15 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_9, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_7) node bpd_csignals_decoded_andMatrixOutputs_hi_15 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_hi_15, bpd_csignals_decoded_andMatrixOutputs_hi_lo_15) node _bpd_csignals_decoded_andMatrixOutputs_T_15 = cat(bpd_csignals_decoded_andMatrixOutputs_hi_15, bpd_csignals_decoded_andMatrixOutputs_lo_15) node bpd_csignals_decoded_andMatrixOutputs_10_2 = andr(_bpd_csignals_decoded_andMatrixOutputs_T_15) node bpd_csignals_decoded_orMatrixOutputs_lo = cat(bpd_csignals_decoded_andMatrixOutputs_2_2, bpd_csignals_decoded_andMatrixOutputs_10_2) node bpd_csignals_decoded_orMatrixOutputs_hi = cat(bpd_csignals_decoded_andMatrixOutputs_14_2, bpd_csignals_decoded_andMatrixOutputs_0_2) node _bpd_csignals_decoded_orMatrixOutputs_T = cat(bpd_csignals_decoded_orMatrixOutputs_hi, bpd_csignals_decoded_orMatrixOutputs_lo) node _bpd_csignals_decoded_orMatrixOutputs_T_1 = orr(_bpd_csignals_decoded_orMatrixOutputs_T) node bpd_csignals_decoded_orMatrixOutputs_lo_lo = cat(bpd_csignals_decoded_andMatrixOutputs_8_2, bpd_csignals_decoded_andMatrixOutputs_10_2) node bpd_csignals_decoded_orMatrixOutputs_lo_hi_hi = cat(bpd_csignals_decoded_andMatrixOutputs_7_2, bpd_csignals_decoded_andMatrixOutputs_1_2) node bpd_csignals_decoded_orMatrixOutputs_lo_hi = cat(bpd_csignals_decoded_orMatrixOutputs_lo_hi_hi, bpd_csignals_decoded_andMatrixOutputs_4_2) node bpd_csignals_decoded_orMatrixOutputs_lo_1 = cat(bpd_csignals_decoded_orMatrixOutputs_lo_hi, bpd_csignals_decoded_orMatrixOutputs_lo_lo) node bpd_csignals_decoded_orMatrixOutputs_hi_lo_hi = cat(bpd_csignals_decoded_andMatrixOutputs_0_2, bpd_csignals_decoded_andMatrixOutputs_12_2) node bpd_csignals_decoded_orMatrixOutputs_hi_lo = cat(bpd_csignals_decoded_orMatrixOutputs_hi_lo_hi, bpd_csignals_decoded_andMatrixOutputs_3_2) node bpd_csignals_decoded_orMatrixOutputs_hi_hi_hi = cat(bpd_csignals_decoded_andMatrixOutputs_5_2, bpd_csignals_decoded_andMatrixOutputs_9_2) node bpd_csignals_decoded_orMatrixOutputs_hi_hi = cat(bpd_csignals_decoded_orMatrixOutputs_hi_hi_hi, bpd_csignals_decoded_andMatrixOutputs_14_2) node bpd_csignals_decoded_orMatrixOutputs_hi_1 = cat(bpd_csignals_decoded_orMatrixOutputs_hi_hi, bpd_csignals_decoded_orMatrixOutputs_hi_lo) node _bpd_csignals_decoded_orMatrixOutputs_T_2 = cat(bpd_csignals_decoded_orMatrixOutputs_hi_1, bpd_csignals_decoded_orMatrixOutputs_lo_1) node _bpd_csignals_decoded_orMatrixOutputs_T_3 = orr(_bpd_csignals_decoded_orMatrixOutputs_T_2) node _bpd_csignals_decoded_orMatrixOutputs_T_4 = orr(bpd_csignals_decoded_andMatrixOutputs_15_2) node _bpd_csignals_decoded_orMatrixOutputs_T_5 = orr(bpd_csignals_decoded_andMatrixOutputs_11_2) node _bpd_csignals_decoded_orMatrixOutputs_T_6 = cat(bpd_csignals_decoded_andMatrixOutputs_6_2, bpd_csignals_decoded_andMatrixOutputs_13_2) node _bpd_csignals_decoded_orMatrixOutputs_T_7 = orr(_bpd_csignals_decoded_orMatrixOutputs_T_6) node bpd_csignals_decoded_orMatrixOutputs_lo_2 = cat(_bpd_csignals_decoded_orMatrixOutputs_T_3, _bpd_csignals_decoded_orMatrixOutputs_T_1) node bpd_csignals_decoded_orMatrixOutputs_hi_hi_1 = cat(_bpd_csignals_decoded_orMatrixOutputs_T_7, _bpd_csignals_decoded_orMatrixOutputs_T_5) node bpd_csignals_decoded_orMatrixOutputs_hi_2 = cat(bpd_csignals_decoded_orMatrixOutputs_hi_hi_1, _bpd_csignals_decoded_orMatrixOutputs_T_4) node bpd_csignals_decoded_orMatrixOutputs = cat(bpd_csignals_decoded_orMatrixOutputs_hi_2, bpd_csignals_decoded_orMatrixOutputs_lo_2) node _bpd_csignals_decoded_invMatrixOutputs_T = bits(bpd_csignals_decoded_orMatrixOutputs, 0, 0) node _bpd_csignals_decoded_invMatrixOutputs_T_1 = bits(bpd_csignals_decoded_orMatrixOutputs, 1, 1) node _bpd_csignals_decoded_invMatrixOutputs_T_2 = bits(bpd_csignals_decoded_orMatrixOutputs, 2, 2) node _bpd_csignals_decoded_invMatrixOutputs_T_3 = bits(bpd_csignals_decoded_orMatrixOutputs, 3, 3) node _bpd_csignals_decoded_invMatrixOutputs_T_4 = bits(bpd_csignals_decoded_orMatrixOutputs, 4, 4) node bpd_csignals_decoded_invMatrixOutputs_lo = cat(_bpd_csignals_decoded_invMatrixOutputs_T_1, _bpd_csignals_decoded_invMatrixOutputs_T) node bpd_csignals_decoded_invMatrixOutputs_hi_hi = cat(_bpd_csignals_decoded_invMatrixOutputs_T_4, _bpd_csignals_decoded_invMatrixOutputs_T_3) node bpd_csignals_decoded_invMatrixOutputs_hi = cat(bpd_csignals_decoded_invMatrixOutputs_hi_hi, _bpd_csignals_decoded_invMatrixOutputs_T_2) node bpd_csignals_decoded_invMatrixOutputs = cat(bpd_csignals_decoded_invMatrixOutputs_hi, bpd_csignals_decoded_invMatrixOutputs_lo) connect bpd_csignals_decoded, bpd_csignals_decoded_invMatrixOutputs connect bpd_csignals_decoded_plaInput, io.inst node bpd_csignals_0 = bits(bpd_csignals_decoded, 4, 4) node bpd_csignals_1 = bits(bpd_csignals_decoded, 3, 3) node bpd_csignals_2 = bits(bpd_csignals_decoded, 2, 2) node bpd_csignals_3 = bits(bpd_csignals_decoded, 1, 1) node bpd_csignals_4 = bits(bpd_csignals_decoded, 0, 0) node cs_is_br = bits(bpd_csignals_0, 0, 0) node cs_is_jal = bits(bpd_csignals_1, 0, 0) node cs_is_jalr = bits(bpd_csignals_2, 0, 0) node cs_is_shadowable = bits(bpd_csignals_3, 0, 0) node cs_has_rs2 = bits(bpd_csignals_4, 0, 0) node _io_out_is_call_T = or(cs_is_jal, cs_is_jalr) node _io_out_is_call_T_1 = bits(io.inst, 11, 7) node _io_out_is_call_T_2 = eq(_io_out_is_call_T_1, UInt<1>(0h1)) node _io_out_is_call_T_3 = and(_io_out_is_call_T, _io_out_is_call_T_2) connect io.out.is_call, _io_out_is_call_T_3 node _io_out_is_ret_T = bits(io.inst, 19, 15) node _io_out_is_ret_T_1 = and(_io_out_is_ret_T, UInt<5>(0h1b)) node _io_out_is_ret_T_2 = eq(UInt<1>(0h1), _io_out_is_ret_T_1) node _io_out_is_ret_T_3 = and(cs_is_jalr, _io_out_is_ret_T_2) node _io_out_is_ret_T_4 = bits(io.inst, 11, 7) node _io_out_is_ret_T_5 = eq(_io_out_is_ret_T_4, UInt<1>(0h0)) node _io_out_is_ret_T_6 = and(_io_out_is_ret_T_3, _io_out_is_ret_T_5) connect io.out.is_ret, _io_out_is_ret_T_6 node _io_out_target_b_imm32_T = bits(io.inst, 31, 31) node _io_out_target_b_imm32_T_1 = mux(_io_out_target_b_imm32_T, UInt<20>(0hfffff), UInt<20>(0h0)) node _io_out_target_b_imm32_T_2 = bits(io.inst, 7, 7) node _io_out_target_b_imm32_T_3 = bits(io.inst, 30, 25) node _io_out_target_b_imm32_T_4 = bits(io.inst, 11, 8) node io_out_target_b_imm32_lo = cat(_io_out_target_b_imm32_T_4, UInt<1>(0h0)) node io_out_target_b_imm32_hi_hi = cat(_io_out_target_b_imm32_T_1, _io_out_target_b_imm32_T_2) node io_out_target_b_imm32_hi = cat(io_out_target_b_imm32_hi_hi, _io_out_target_b_imm32_T_3) node io_out_target_b_imm32 = cat(io_out_target_b_imm32_hi, io_out_target_b_imm32_lo) node _io_out_target_T = asSInt(io.pc) node _io_out_target_T_1 = asSInt(io_out_target_b_imm32) node _io_out_target_T_2 = add(_io_out_target_T, _io_out_target_T_1) node _io_out_target_T_3 = tail(_io_out_target_T_2, 1) node _io_out_target_T_4 = asSInt(_io_out_target_T_3) node _io_out_target_T_5 = and(_io_out_target_T_4, asSInt(UInt<2>(0h2))) node _io_out_target_T_6 = asSInt(_io_out_target_T_5) node _io_out_target_T_7 = asUInt(_io_out_target_T_6) node _io_out_target_j_imm32_T = bits(io.inst, 31, 31) node _io_out_target_j_imm32_T_1 = mux(_io_out_target_j_imm32_T, UInt<12>(0hfff), UInt<12>(0h0)) node _io_out_target_j_imm32_T_2 = bits(io.inst, 19, 12) node _io_out_target_j_imm32_T_3 = bits(io.inst, 20, 20) node _io_out_target_j_imm32_T_4 = bits(io.inst, 30, 25) node _io_out_target_j_imm32_T_5 = bits(io.inst, 24, 21) node io_out_target_j_imm32_lo_hi = cat(_io_out_target_j_imm32_T_4, _io_out_target_j_imm32_T_5) node io_out_target_j_imm32_lo = cat(io_out_target_j_imm32_lo_hi, UInt<1>(0h0)) node io_out_target_j_imm32_hi_hi = cat(_io_out_target_j_imm32_T_1, _io_out_target_j_imm32_T_2) node io_out_target_j_imm32_hi = cat(io_out_target_j_imm32_hi_hi, _io_out_target_j_imm32_T_3) node io_out_target_j_imm32 = cat(io_out_target_j_imm32_hi, io_out_target_j_imm32_lo) node _io_out_target_T_8 = asSInt(io.pc) node _io_out_target_T_9 = asSInt(io_out_target_j_imm32) node _io_out_target_T_10 = add(_io_out_target_T_8, _io_out_target_T_9) node _io_out_target_T_11 = tail(_io_out_target_T_10, 1) node _io_out_target_T_12 = asSInt(_io_out_target_T_11) node _io_out_target_T_13 = and(_io_out_target_T_12, asSInt(UInt<2>(0h2))) node _io_out_target_T_14 = asSInt(_io_out_target_T_13) node _io_out_target_T_15 = asUInt(_io_out_target_T_14) node _io_out_target_T_16 = mux(cs_is_br, _io_out_target_T_7, _io_out_target_T_15) connect io.out.target, _io_out_target_T_16 node _io_out_cfi_type_T = mux(cs_is_br, UInt<3>(0h1), UInt<3>(0h0)) node _io_out_cfi_type_T_1 = mux(cs_is_jal, UInt<3>(0h2), _io_out_cfi_type_T) node _io_out_cfi_type_T_2 = mux(cs_is_jalr, UInt<3>(0h3), _io_out_cfi_type_T_1) connect io.out.cfi_type, _io_out_cfi_type_T_2 node _br_offset_T = bits(io.inst, 7, 7) node _br_offset_T_1 = bits(io.inst, 30, 25) node _br_offset_T_2 = bits(io.inst, 11, 8) node br_offset_lo = cat(_br_offset_T_2, UInt<1>(0h0)) node br_offset_hi = cat(_br_offset_T, _br_offset_T_1) node br_offset = cat(br_offset_hi, br_offset_lo) node _io_out_sfb_offset_valid_T = bits(io.inst, 31, 31) node _io_out_sfb_offset_valid_T_1 = eq(_io_out_sfb_offset_valid_T, UInt<1>(0h0)) node _io_out_sfb_offset_valid_T_2 = and(cs_is_br, _io_out_sfb_offset_valid_T_1) node _io_out_sfb_offset_valid_T_3 = neq(br_offset, UInt<1>(0h0)) node _io_out_sfb_offset_valid_T_4 = and(_io_out_sfb_offset_valid_T_2, _io_out_sfb_offset_valid_T_3) node _io_out_sfb_offset_valid_T_5 = shr(br_offset, 6) node _io_out_sfb_offset_valid_T_6 = eq(_io_out_sfb_offset_valid_T_5, UInt<1>(0h0)) node _io_out_sfb_offset_valid_T_7 = and(_io_out_sfb_offset_valid_T_4, _io_out_sfb_offset_valid_T_6) connect io.out.sfb_offset.valid, _io_out_sfb_offset_valid_T_7 connect io.out.sfb_offset.bits, br_offset node _io_out_shadowable_T = eq(cs_has_rs2, UInt<1>(0h0)) node _io_out_shadowable_T_1 = bits(io.inst, 19, 15) node _io_out_shadowable_T_2 = bits(io.inst, 11, 7) node _io_out_shadowable_T_3 = eq(_io_out_shadowable_T_1, _io_out_shadowable_T_2) node _io_out_shadowable_T_4 = or(_io_out_shadowable_T, _io_out_shadowable_T_3) node _io_out_shadowable_T_5 = and(io.inst, UInt<32>(0hfe00707f)) node _io_out_shadowable_T_6 = eq(UInt<6>(0h33), _io_out_shadowable_T_5) node _io_out_shadowable_T_7 = bits(io.inst, 19, 15) node _io_out_shadowable_T_8 = eq(_io_out_shadowable_T_7, UInt<1>(0h0)) node _io_out_shadowable_T_9 = and(_io_out_shadowable_T_6, _io_out_shadowable_T_8) node _io_out_shadowable_T_10 = or(_io_out_shadowable_T_4, _io_out_shadowable_T_9) node _io_out_shadowable_T_11 = and(cs_is_shadowable, _io_out_shadowable_T_10) connect io.out.shadowable, _io_out_shadowable_T_11	module BranchDecode_8( // @[decode.scala:623:7] input clock, // @[decode.scala:623:7] input reset, // @[decode.scala:623:7] input [31:0] io_inst, // @[decode.scala:625:14] input [39:0] io_pc, // @[decode.scala:625:14] output io_out_is_ret, // @[decode.scala:625:14] output io_out_is_call, // @[decode.scala:625:14] output [39:0] io_out_target, // @[decode.scala:625:14] output [2:0] io_out_cfi_type, // @[decode.scala:625:14] output io_out_sfb_offset_valid, // @[decode.scala:625:14] output [5:0] io_out_sfb_offset_bits, // @[decode.scala:625:14] output io_out_shadowable // @[decode.scala:625:14] ); wire [31:0] io_inst_0 = io_inst; // @[decode.scala:623:7] wire [39:0] io_pc_0 = io_pc; // @[decode.scala:623:7] wire [31:0] bpd_csignals_decoded_plaInput = io_inst_0; // @[pla.scala:77:22] wire _io_out_is_ret_T_6; // @[decode.scala:695:72] wire [39:0] _io_out_target_T = io_pc_0; // @[decode.scala:623:7] wire [39:0] _io_out_target_T_8 = io_pc_0; // @[decode.scala:623:7] wire _io_out_is_call_T_3; // @[decode.scala:694:47] wire [39:0] _io_out_target_T_16; // @[decode.scala:697:23] wire [2:0] _io_out_cfi_type_T_2; // @[decode.scala:700:8] wire _io_out_sfb_offset_valid_T_7; // @[decode.scala:710:76] wire _io_out_shadowable_T_11; // @[decode.scala:712:41] wire io_out_sfb_offset_valid_0; // @[decode.scala:623:7] wire [5:0] io_out_sfb_offset_bits_0; // @[decode.scala:623:7] wire io_out_is_ret_0; // @[decode.scala:623:7] wire io_out_is_call_0; // @[decode.scala:623:7] wire [39:0] io_out_target_0; // @[decode.scala:623:7] wire [2:0] io_out_cfi_type_0; // @[decode.scala:623:7] wire io_out_shadowable_0; // @[decode.scala:623:7] wire [31:0] bpd_csignals_decoded_invInputs = ~bpd_csignals_decoded_plaInput; // @[pla.scala:77:22, :78:21] wire [4:0] bpd_csignals_decoded_invMatrixOutputs; // @[pla.scala:120:37] wire [4:0] bpd_csignals_decoded; // @[pla.scala:81:23] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_1 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_2 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_3 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_4 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_5 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_6 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_7 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_8 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_9 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_10 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_11 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_12 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_13 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_14 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_15 = bpd_csignals_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_1 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_2 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_3 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_4 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_5 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_6 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_7 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_8 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_9 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_10 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_11 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_12 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_13 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_14 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_15 = bpd_csignals_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_1 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_2 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_3 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_4 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_6 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_9 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_10 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_11 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_12 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_13 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_14 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_15 = bpd_csignals_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3 = bpd_csignals_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_3 = bpd_csignals_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_5 = bpd_csignals_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_6 = bpd_csignals_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_7 = bpd_csignals_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_9 = bpd_csignals_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_11 = bpd_csignals_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_12 = bpd_csignals_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_13 = bpd_csignals_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_1 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_2 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_3 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_4 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_5 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_9 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_10 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_11 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_13 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_14 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_15 = bpd_csignals_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5 = bpd_csignals_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_1 = bpd_csignals_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_9 = bpd_csignals_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_11 = bpd_csignals_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_13 = bpd_csignals_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_1 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_2 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_3 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_4 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_5 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_9 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_10 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_11 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_13 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_14 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_15 = bpd_csignals_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7 = bpd_csignals_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_1 = bpd_csignals_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_2 = bpd_csignals_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_6 = bpd_csignals_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo = {bpd_csignals_decoded_andMatrixOutputs_lo_hi, bpd_csignals_decoded_andMatrixOutputs_lo_lo}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi = {bpd_csignals_decoded_andMatrixOutputs_hi_hi, bpd_csignals_decoded_andMatrixOutputs_hi_lo}; // @[pla.scala:98:53] wire [7:0] _bpd_csignals_decoded_andMatrixOutputs_T = {bpd_csignals_decoded_andMatrixOutputs_hi, bpd_csignals_decoded_andMatrixOutputs_lo}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_5_2 = &_bpd_csignals_decoded_andMatrixOutputs_T; // @[pla.scala:98:{53,70}] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_1 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_2 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_4 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_5 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_4 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_5 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_8 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_7 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_12 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_13 = bpd_csignals_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8 = bpd_csignals_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_1 = bpd_csignals_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_4 = bpd_csignals_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_3 = bpd_csignals_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_1}; // @[pla.scala:91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_1 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_1, bpd_csignals_decoded_andMatrixOutputs_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_1}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_1}; // @[pla.scala:90:45, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_1 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_1}; // @[pla.scala:91:29, :98:53] wire [4:0] bpd_csignals_decoded_andMatrixOutputs_hi_1 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_1, bpd_csignals_decoded_andMatrixOutputs_hi_lo_1}; // @[pla.scala:98:53] wire [8:0] _bpd_csignals_decoded_andMatrixOutputs_T_1 = {bpd_csignals_decoded_andMatrixOutputs_hi_1, bpd_csignals_decoded_andMatrixOutputs_lo_1}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_9_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_1; // @[pla.scala:98:{53,70}] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_2 = bpd_csignals_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_3 = bpd_csignals_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_4 = bpd_csignals_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_5 = bpd_csignals_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_6 = bpd_csignals_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_7 = bpd_csignals_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_8 = bpd_csignals_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_12 = bpd_csignals_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_15 = bpd_csignals_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9 = bpd_csignals_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_3 = bpd_csignals_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_3 = bpd_csignals_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_6 = bpd_csignals_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_7 = bpd_csignals_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_8 = bpd_csignals_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10 = bpd_csignals_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_2 = bpd_csignals_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_2 = bpd_csignals_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_4 = bpd_csignals_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_5 = bpd_csignals_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_5 = bpd_csignals_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_6 = bpd_csignals_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_7 = bpd_csignals_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11 = bpd_csignals_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_1 = bpd_csignals_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_2 = bpd_csignals_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_3 = bpd_csignals_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_4 = bpd_csignals_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_5 = bpd_csignals_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_6 = bpd_csignals_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_7 = bpd_csignals_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12 = bpd_csignals_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_1 = bpd_csignals_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_2 = bpd_csignals_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_3 = bpd_csignals_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_4 = bpd_csignals_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_5 = bpd_csignals_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_6 = bpd_csignals_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_7 = bpd_csignals_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13 = bpd_csignals_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_1 = bpd_csignals_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_2 = bpd_csignals_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_3 = bpd_csignals_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_4 = bpd_csignals_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_5 = bpd_csignals_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_6 = bpd_csignals_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_7 = bpd_csignals_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14 = bpd_csignals_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_1 = bpd_csignals_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_1 = bpd_csignals_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_2 = bpd_csignals_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_3 = bpd_csignals_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_4 = bpd_csignals_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_5 = bpd_csignals_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_6 = bpd_csignals_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13}; // @[pla.scala:91:29, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_2 = {bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9}; // @[pla.scala:91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_2 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo}; // @[pla.scala:98:53] wire [6:0] bpd_csignals_decoded_andMatrixOutputs_lo_2 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_2, bpd_csignals_decoded_andMatrixOutputs_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_2}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_2}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_2 = {bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_2}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_2}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_2 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_1, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo}; // @[pla.scala:98:53] wire [7:0] bpd_csignals_decoded_andMatrixOutputs_hi_2 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_2, bpd_csignals_decoded_andMatrixOutputs_hi_lo_2}; // @[pla.scala:98:53] wire [14:0] _bpd_csignals_decoded_andMatrixOutputs_T_2 = {bpd_csignals_decoded_andMatrixOutputs_hi_2, bpd_csignals_decoded_andMatrixOutputs_lo_2}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_14_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_2; // @[pla.scala:98:{53,70}] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_1 = bpd_csignals_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_2 = bpd_csignals_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_3 = bpd_csignals_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_4 = bpd_csignals_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_1}; // @[pla.scala:91:29, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_3 = {bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_1}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_1}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_2}; // @[pla.scala:91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_3 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_1, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_1}; // @[pla.scala:98:53] wire [6:0] bpd_csignals_decoded_andMatrixOutputs_lo_3 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_3, bpd_csignals_decoded_andMatrixOutputs_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_3}; // @[pla.scala:90:45, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_3 = {bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_1, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_3}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_3}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_2 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_3}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_3 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_2, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_1}; // @[pla.scala:98:53] wire [6:0] bpd_csignals_decoded_andMatrixOutputs_hi_3 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_3, bpd_csignals_decoded_andMatrixOutputs_hi_lo_3}; // @[pla.scala:98:53] wire [13:0] _bpd_csignals_decoded_andMatrixOutputs_T_3 = {bpd_csignals_decoded_andMatrixOutputs_hi_3, bpd_csignals_decoded_andMatrixOutputs_lo_3}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_0_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_3; // @[pla.scala:98:{53,70}] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_2 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_2}; // @[pla.scala:91:29, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_4 = {bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_1}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_2 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_2, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_2}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_2 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_2}; // @[pla.scala:91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_4 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_2, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] bpd_csignals_decoded_andMatrixOutputs_lo_4 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_4, bpd_csignals_decoded_andMatrixOutputs_lo_lo_4}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_1 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_4}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_2 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_4}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_4 = {bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_2, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_2 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_4}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_3 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_4}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_4 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_3, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_2}; // @[pla.scala:98:53] wire [7:0] bpd_csignals_decoded_andMatrixOutputs_hi_4 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_4, bpd_csignals_decoded_andMatrixOutputs_hi_lo_4}; // @[pla.scala:98:53] wire [14:0] _bpd_csignals_decoded_andMatrixOutputs_T_4 = {bpd_csignals_decoded_andMatrixOutputs_hi_4, bpd_csignals_decoded_andMatrixOutputs_lo_4}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_2_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_4; // @[pla.scala:98:{53,70}] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_5 = bpd_csignals_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_7 = bpd_csignals_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_8 = bpd_csignals_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_5}; // @[pla.scala:90:45, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_5 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_5}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_5}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_5 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_5, bpd_csignals_decoded_andMatrixOutputs_hi_lo_5}; // @[pla.scala:98:53] wire [6:0] _bpd_csignals_decoded_andMatrixOutputs_T_5 = {bpd_csignals_decoded_andMatrixOutputs_hi_5, bpd_csignals_decoded_andMatrixOutputs_lo_5}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_12_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_5; // @[pla.scala:98:{53,70}] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_6 = bpd_csignals_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_7 = bpd_csignals_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_8 = bpd_csignals_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_12 = bpd_csignals_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_6 = bpd_csignals_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_7 = bpd_csignals_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_8 = bpd_csignals_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_12 = bpd_csignals_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_6}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_6 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_6, bpd_csignals_decoded_andMatrixOutputs_lo_lo_5}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_6}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_6}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_6 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_6, bpd_csignals_decoded_andMatrixOutputs_hi_lo_6}; // @[pla.scala:98:53] wire [7:0] _bpd_csignals_decoded_andMatrixOutputs_T_6 = {bpd_csignals_decoded_andMatrixOutputs_hi_6, bpd_csignals_decoded_andMatrixOutputs_lo_6}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_6_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_6; // @[pla.scala:98:{53,70}] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_3}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_3 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_7}; // @[pla.scala:90:45, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_7 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_6}; // @[pla.scala:91:29, :98:53] wire [4:0] bpd_csignals_decoded_andMatrixOutputs_lo_7 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_7, bpd_csignals_decoded_andMatrixOutputs_lo_lo_6}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_7 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_7}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_4 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_7}; // @[pla.scala:90:45, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_7 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_7}; // @[pla.scala:90:45, :98:53] wire [4:0] bpd_csignals_decoded_andMatrixOutputs_hi_7 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_7, bpd_csignals_decoded_andMatrixOutputs_hi_lo_7}; // @[pla.scala:98:53] wire [9:0] _bpd_csignals_decoded_andMatrixOutputs_T_7 = {bpd_csignals_decoded_andMatrixOutputs_hi_7, bpd_csignals_decoded_andMatrixOutputs_lo_7}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_15_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_7; // @[pla.scala:98:{53,70}] wire _bpd_csignals_decoded_orMatrixOutputs_T_4 = bpd_csignals_decoded_andMatrixOutputs_15_2; // @[pla.scala:98:70, :114:36] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_8 = bpd_csignals_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_10 = bpd_csignals_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_14 = bpd_csignals_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_8 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_8, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_8 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_8, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_8}; // @[pla.scala:90:45, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_8 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_8, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_8}; // @[pla.scala:90:45, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_8 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_8, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_8}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_8 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_8, bpd_csignals_decoded_andMatrixOutputs_hi_lo_8}; // @[pla.scala:98:53] wire [6:0] _bpd_csignals_decoded_andMatrixOutputs_T_8 = {bpd_csignals_decoded_andMatrixOutputs_hi_8, bpd_csignals_decoded_andMatrixOutputs_lo_8}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_11_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_8; // @[pla.scala:98:{53,70}] wire _bpd_csignals_decoded_orMatrixOutputs_T_5 = bpd_csignals_decoded_andMatrixOutputs_11_2; // @[pla.scala:98:70, :114:36] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_7 = bpd_csignals_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_10 = bpd_csignals_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_11 = bpd_csignals_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_14 = bpd_csignals_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_15 = bpd_csignals_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_3 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_3}; // @[pla.scala:91:29, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_7 = {bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_2}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_3 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_3, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_3}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_4 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_4}; // @[pla.scala:91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_9 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_4, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_3}; // @[pla.scala:98:53] wire [6:0] bpd_csignals_decoded_andMatrixOutputs_lo_9 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_9, bpd_csignals_decoded_andMatrixOutputs_lo_lo_7}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_2 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_9, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_3 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_9, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_9 = {bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_3, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_3 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_9, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_9}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_9, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_9}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_9 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_5, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_3}; // @[pla.scala:98:53] wire [7:0] bpd_csignals_decoded_andMatrixOutputs_hi_9 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_9, bpd_csignals_decoded_andMatrixOutputs_hi_lo_9}; // @[pla.scala:98:53] wire [14:0] _bpd_csignals_decoded_andMatrixOutputs_T_9 = {bpd_csignals_decoded_andMatrixOutputs_hi_9, bpd_csignals_decoded_andMatrixOutputs_lo_9}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_3_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_9; // @[pla.scala:98:{53,70}] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_4 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_4}; // @[pla.scala:91:29, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_8 = {bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_3}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_4 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_4, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_4}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_5}; // @[pla.scala:91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_10 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_5, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_4}; // @[pla.scala:98:53] wire [6:0] bpd_csignals_decoded_andMatrixOutputs_lo_10 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_10, bpd_csignals_decoded_andMatrixOutputs_lo_lo_8}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_3 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_10, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_4 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_10, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_10 = {bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_4, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_4 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_10, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_10, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_10}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_10 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_6, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_4}; // @[pla.scala:98:53] wire [7:0] bpd_csignals_decoded_andMatrixOutputs_hi_10 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_10, bpd_csignals_decoded_andMatrixOutputs_hi_lo_10}; // @[pla.scala:98:53] wire [14:0] _bpd_csignals_decoded_andMatrixOutputs_T_10 = {bpd_csignals_decoded_andMatrixOutputs_hi_10, bpd_csignals_decoded_andMatrixOutputs_lo_10}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_7_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_10; // @[pla.scala:98:{53,70}] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_9 = bpd_csignals_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_9 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_11, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_11 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_11, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_11 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_11, bpd_csignals_decoded_andMatrixOutputs_lo_lo_9}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_11 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_11, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_11}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_11 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_11, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_11}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_11 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_11, bpd_csignals_decoded_andMatrixOutputs_hi_lo_11}; // @[pla.scala:98:53] wire [7:0] _bpd_csignals_decoded_andMatrixOutputs_T_11 = {bpd_csignals_decoded_andMatrixOutputs_hi_11, bpd_csignals_decoded_andMatrixOutputs_lo_11}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_1_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_11; // @[pla.scala:98:{53,70}] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_10 = bpd_csignals_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_6 = bpd_csignals_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_8 = bpd_csignals_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_9 = bpd_csignals_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_10 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_12, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_10}; // @[pla.scala:90:45, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_12 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_12, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_12 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_12, bpd_csignals_decoded_andMatrixOutputs_lo_lo_10}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_12 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_12, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_12}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_12 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_12, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_12}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_12 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_12, bpd_csignals_decoded_andMatrixOutputs_hi_lo_12}; // @[pla.scala:98:53] wire [7:0] _bpd_csignals_decoded_andMatrixOutputs_T_12 = {bpd_csignals_decoded_andMatrixOutputs_hi_12, bpd_csignals_decoded_andMatrixOutputs_lo_12}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_13_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_12; // @[pla.scala:98:{53,70}] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_5}; // @[pla.scala:91:29, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_11 = {bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_4}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_5, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_5}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_6}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_13 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_6, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_5}; // @[pla.scala:98:53] wire [6:0] bpd_csignals_decoded_andMatrixOutputs_lo_13 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_13, bpd_csignals_decoded_andMatrixOutputs_lo_lo_11}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_4 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_13, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_13, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_13 = {bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_5, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_4}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_13, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_13}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_7 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_13, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_13}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_13 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_7, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_5}; // @[pla.scala:98:53] wire [7:0] bpd_csignals_decoded_andMatrixOutputs_hi_13 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_13, bpd_csignals_decoded_andMatrixOutputs_hi_lo_13}; // @[pla.scala:98:53] wire [14:0] _bpd_csignals_decoded_andMatrixOutputs_T_13 = {bpd_csignals_decoded_andMatrixOutputs_hi_13, bpd_csignals_decoded_andMatrixOutputs_lo_13}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_4_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_13; // @[pla.scala:98:{53,70}] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_6}; // @[pla.scala:91:29, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_12 = {bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_5}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_6, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_6}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_7 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_8, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_14 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_7, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_6}; // @[pla.scala:98:53] wire [6:0] bpd_csignals_decoded_andMatrixOutputs_lo_14 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_14, bpd_csignals_decoded_andMatrixOutputs_lo_lo_12}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_5 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_14, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_14, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_14 = {bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_6, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_5}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_14, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_8 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_14, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_14}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_14 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_8, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_6}; // @[pla.scala:98:53] wire [7:0] bpd_csignals_decoded_andMatrixOutputs_hi_14 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_14, bpd_csignals_decoded_andMatrixOutputs_hi_lo_14}; // @[pla.scala:98:53] wire [14:0] _bpd_csignals_decoded_andMatrixOutputs_T_14 = {bpd_csignals_decoded_andMatrixOutputs_hi_14, bpd_csignals_decoded_andMatrixOutputs_lo_14}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_8_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_14; // @[pla.scala:98:{53,70}] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_7 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_12_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_13_7}; // @[pla.scala:91:29, :98:53] wire [2:0] bpd_csignals_decoded_andMatrixOutputs_lo_lo_13 = {bpd_csignals_decoded_andMatrixOutputs_lo_lo_hi_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_14_6}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_7 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_10_7, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_11_7}; // @[pla.scala:91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_8 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_8_9, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_9_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_lo_hi_15 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_hi_8, bpd_csignals_decoded_andMatrixOutputs_lo_hi_lo_7}; // @[pla.scala:98:53] wire [6:0] bpd_csignals_decoded_andMatrixOutputs_lo_15 = {bpd_csignals_decoded_andMatrixOutputs_lo_hi_15, bpd_csignals_decoded_andMatrixOutputs_lo_lo_13}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_6 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_6_15, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_7_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_7 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_4_15, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_5_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_lo_15 = {bpd_csignals_decoded_andMatrixOutputs_hi_lo_hi_7, bpd_csignals_decoded_andMatrixOutputs_hi_lo_lo_6}; // @[pla.scala:98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_7 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_2_15, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_3_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_9 = {bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_0_15, bpd_csignals_decoded_andMatrixOutputs_andMatrixInput_1_15}; // @[pla.scala:90:45, :98:53] wire [3:0] bpd_csignals_decoded_andMatrixOutputs_hi_hi_15 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_hi_9, bpd_csignals_decoded_andMatrixOutputs_hi_hi_lo_7}; // @[pla.scala:98:53] wire [7:0] bpd_csignals_decoded_andMatrixOutputs_hi_15 = {bpd_csignals_decoded_andMatrixOutputs_hi_hi_15, bpd_csignals_decoded_andMatrixOutputs_hi_lo_15}; // @[pla.scala:98:53] wire [14:0] _bpd_csignals_decoded_andMatrixOutputs_T_15 = {bpd_csignals_decoded_andMatrixOutputs_hi_15, bpd_csignals_decoded_andMatrixOutputs_lo_15}; // @[pla.scala:98:53] wire bpd_csignals_decoded_andMatrixOutputs_10_2 = &_bpd_csignals_decoded_andMatrixOutputs_T_15; // @[pla.scala:98:{53,70}] wire [1:0] bpd_csignals_decoded_orMatrixOutputs_lo = {bpd_csignals_decoded_andMatrixOutputs_2_2, bpd_csignals_decoded_andMatrixOutputs_10_2}; // @[pla.scala:98:70, :114:19] wire [1:0] bpd_csignals_decoded_orMatrixOutputs_hi = {bpd_csignals_decoded_andMatrixOutputs_14_2, bpd_csignals_decoded_andMatrixOutputs_0_2}; // @[pla.scala:98:70, :114:19] wire [3:0] _bpd_csignals_decoded_orMatrixOutputs_T = {bpd_csignals_decoded_orMatrixOutputs_hi, bpd_csignals_decoded_orMatrixOutputs_lo}; // @[pla.scala:114:19] wire _bpd_csignals_decoded_orMatrixOutputs_T_1 = \|_bpd_csignals_decoded_orMatrixOutputs_T; // @[pla.scala:114:{19,36}] wire [1:0] bpd_csignals_decoded_orMatrixOutputs_lo_lo = {bpd_csignals_decoded_andMatrixOutputs_8_2, bpd_csignals_decoded_andMatrixOutputs_10_2}; // @[pla.scala:98:70, :114:19] wire [1:0] bpd_csignals_decoded_orMatrixOutputs_lo_hi_hi = {bpd_csignals_decoded_andMatrixOutputs_7_2, bpd_csignals_decoded_andMatrixOutputs_1_2}; // @[pla.scala:98:70, :114:19] wire [2:0] bpd_csignals_decoded_orMatrixOutputs_lo_hi = {bpd_csignals_decoded_orMatrixOutputs_lo_hi_hi, bpd_csignals_decoded_andMatrixOutputs_4_2}; // @[pla.scala:98:70, :114:19] wire [4:0] bpd_csignals_decoded_orMatrixOutputs_lo_1 = {bpd_csignals_decoded_orMatrixOutputs_lo_hi, bpd_csignals_decoded_orMatrixOutputs_lo_lo}; // @[pla.scala:114:19] wire [1:0] bpd_csignals_decoded_orMatrixOutputs_hi_lo_hi = {bpd_csignals_decoded_andMatrixOutputs_0_2, bpd_csignals_decoded_andMatrixOutputs_12_2}; // @[pla.scala:98:70, :114:19] wire [2:0] bpd_csignals_decoded_orMatrixOutputs_hi_lo = {bpd_csignals_decoded_orMatrixOutputs_hi_lo_hi, bpd_csignals_decoded_andMatrixOutputs_3_2}; // @[pla.scala:98:70, :114:19] wire [1:0] bpd_csignals_decoded_orMatrixOutputs_hi_hi_hi = {bpd_csignals_decoded_andMatrixOutputs_5_2, bpd_csignals_decoded_andMatrixOutputs_9_2}; // @[pla.scala:98:70, :114:19] wire [2:0] bpd_csignals_decoded_orMatrixOutputs_hi_hi = {bpd_csignals_decoded_orMatrixOutputs_hi_hi_hi, bpd_csignals_decoded_andMatrixOutputs_14_2}; // @[pla.scala:98:70, :114:19] wire [5:0] bpd_csignals_decoded_orMatrixOutputs_hi_1 = {bpd_csignals_decoded_orMatrixOutputs_hi_hi, bpd_csignals_decoded_orMatrixOutputs_hi_lo}; // @[pla.scala:114:19] wire [10:0] _bpd_csignals_decoded_orMatrixOutputs_T_2 = {bpd_csignals_decoded_orMatrixOutputs_hi_1, bpd_csignals_decoded_orMatrixOutputs_lo_1}; // @[pla.scala:114:19] wire _bpd_csignals_decoded_orMatrixOutputs_T_3 = \|_bpd_csignals_decoded_orMatrixOutputs_T_2; // @[pla.scala:114:{19,36}] wire [1:0] _bpd_csignals_decoded_orMatrixOutputs_T_6 = {bpd_csignals_decoded_andMatrixOutputs_6_2, bpd_csignals_decoded_andMatrixOutputs_13_2}; // @[pla.scala:98:70, :114:19] wire _bpd_csignals_decoded_orMatrixOutputs_T_7 = \|_bpd_csignals_decoded_orMatrixOutputs_T_6; // @[pla.scala:114:{19,36}] wire [1:0] bpd_csignals_decoded_orMatrixOutputs_lo_2 = {_bpd_csignals_decoded_orMatrixOutputs_T_3, _bpd_csignals_decoded_orMatrixOutputs_T_1}; // @[pla.scala:102:36, :114:36] wire [1:0] bpd_csignals_decoded_orMatrixOutputs_hi_hi_1 = {_bpd_csignals_decoded_orMatrixOutputs_T_7, _bpd_csignals_decoded_orMatrixOutputs_T_5}; // @[pla.scala:102:36, :114:36] wire [2:0] bpd_csignals_decoded_orMatrixOutputs_hi_2 = {bpd_csignals_decoded_orMatrixOutputs_hi_hi_1, _bpd_csignals_decoded_orMatrixOutputs_T_4}; // @[pla.scala:102:36, :114:36] wire [4:0] bpd_csignals_decoded_orMatrixOutputs = {bpd_csignals_decoded_orMatrixOutputs_hi_2, bpd_csignals_decoded_orMatrixOutputs_lo_2}; // @[pla.scala:102:36] wire _bpd_csignals_decoded_invMatrixOutputs_T = bpd_csignals_decoded_orMatrixOutputs[0]; // @[pla.scala:102:36, :124:31] wire _bpd_csignals_decoded_invMatrixOutputs_T_1 = bpd_csignals_decoded_orMatrixOutputs[1]; // @[pla.scala:102:36, :124:31] wire _bpd_csignals_decoded_invMatrixOutputs_T_2 = bpd_csignals_decoded_orMatrixOutputs[2]; // @[pla.scala:102:36, :124:31] wire _bpd_csignals_decoded_invMatrixOutputs_T_3 = bpd_csignals_decoded_orMatrixOutputs[3]; // @[pla.scala:102:36, :124:31] wire _bpd_csignals_decoded_invMatrixOutputs_T_4 = bpd_csignals_decoded_orMatrixOutputs[4]; // @[pla.scala:102:36, :124:31] wire [1:0] bpd_csignals_decoded_invMatrixOutputs_lo = {_bpd_csignals_decoded_invMatrixOutputs_T_1, _bpd_csignals_decoded_invMatrixOutputs_T}; // @[pla.scala:120:37, :124:31] wire [1:0] bpd_csignals_decoded_invMatrixOutputs_hi_hi = {_bpd_csignals_decoded_invMatrixOutputs_T_4, _bpd_csignals_decoded_invMatrixOutputs_T_3}; // @[pla.scala:120:37, :124:31] wire [2:0] bpd_csignals_decoded_invMatrixOutputs_hi = {bpd_csignals_decoded_invMatrixOutputs_hi_hi, _bpd_csignals_decoded_invMatrixOutputs_T_2}; // @[pla.scala:120:37, :124:31] assign bpd_csignals_decoded_invMatrixOutputs = {bpd_csignals_decoded_invMatrixOutputs_hi, bpd_csignals_decoded_invMatrixOutputs_lo}; // @[pla.scala:120:37] assign bpd_csignals_decoded = bpd_csignals_decoded_invMatrixOutputs; // @[pla.scala:81:23, :120:37] wire bpd_csignals_0 = bpd_csignals_decoded[4]; // @[pla.scala:81:23] wire cs_is_br = bpd_csignals_0; // @[Decode.scala:50:77] wire bpd_csignals_1 = bpd_csignals_decoded[3]; // @[pla.scala:81:23] wire cs_is_jal = bpd_csignals_1; // @[Decode.scala:50:77] wire bpd_csignals_2 = bpd_csignals_decoded[2]; // @[pla.scala:81:23] wire cs_is_jalr = bpd_csignals_2; // @[Decode.scala:50:77] wire bpd_csignals_3 = bpd_csignals_decoded[1]; // @[pla.scala:81:23] wire cs_is_shadowable = bpd_csignals_3; // @[Decode.scala:50:77] wire bpd_csignals_4 = bpd_csignals_decoded[0]; // @[pla.scala:81:23] wire cs_has_rs2 = bpd_csignals_4; // @[Decode.scala:50:77] wire _io_out_is_call_T = cs_is_jal \| cs_is_jalr; // @[decode.scala:689:34, :690:35, :694:32] wire [4:0] _io_out_is_call_T_1 = io_inst_0[11:7]; // @[decode.scala:623:7] wire [4:0] _io_out_is_ret_T_4 = io_inst_0[11:7]; // @[decode.scala:623:7] wire [4:0] _io_out_shadowable_T_2 = io_inst_0[11:7]; // @[decode.scala:623:7] wire _io_out_is_call_T_2 = _io_out_is_call_T_1 == 5'h1; // @[decode.scala:694:65] assign _io_out_is_call_T_3 = _io_out_is_call_T & _io_out_is_call_T_2; // @[decode.scala:694:{32,47,65}] assign io_out_is_call_0 = _io_out_is_call_T_3; // @[decode.scala:623:7, :694:47] wire [4:0] _io_out_is_ret_T = io_inst_0[19:15]; // @[decode.scala:623:7] wire [4:0] _io_out_shadowable_T_1 = io_inst_0[19:15]; // @[decode.scala:623:7] wire [4:0] _io_out_shadowable_T_7 = io_inst_0[19:15]; // @[decode.scala:623:7] wire [4:0] _io_out_is_ret_T_1 = _io_out_is_ret_T & 5'h1B; // @[decode.scala:695:51] wire _io_out_is_ret_T_2 = _io_out_is_ret_T_1 == 5'h1; // @[decode.scala:695:51] wire _io_out_is_ret_T_3 = cs_is_jalr & _io_out_is_ret_T_2; // @[decode.scala:690:35, :695:{32,51}] wire _io_out_is_ret_T_5 = _io_out_is_ret_T_4 == 5'h0; // @[decode.scala:695:90] assign _io_out_is_ret_T_6 = _io_out_is_ret_T_3 & _io_out_is_ret_T_5; // @[decode.scala:695:{32,72,90}] assign io_out_is_ret_0 = _io_out_is_ret_T_6; // @[decode.scala:623:7, :695:72] wire _io_out_target_b_imm32_T = io_inst_0[31]; // @[decode.scala:623:7] wire _io_out_target_j_imm32_T = io_inst_0[31]; // @[decode.scala:623:7] wire _io_out_sfb_offset_valid_T = io_inst_0[31]; // @[decode.scala:623:7, :710:50] wire [19:0] _io_out_target_b_imm32_T_1 = {20{_io_out_target_b_imm32_T}}; // @[consts.scala:337:{27,35}] wire _io_out_target_b_imm32_T_2 = io_inst_0[7]; // @[decode.scala:623:7] wire _br_offset_T = io_inst_0[7]; // @[decode.scala:623:7, :708:30] wire [5:0] _io_out_target_b_imm32_T_3 = io_inst_0[30:25]; // @[decode.scala:623:7] wire [5:0] _io_out_target_j_imm32_T_4 = io_inst_0[30:25]; // @[decode.scala:623:7] wire [5:0] _br_offset_T_1 = io_inst_0[30:25]; // @[decode.scala:623:7, :708:42] wire [3:0] _io_out_target_b_imm32_T_4 = io_inst_0[11:8]; // @[decode.scala:623:7] wire [3:0] _br_offset_T_2 = io_inst_0[11:8]; // @[decode.scala:623:7, :708:58] wire [4:0] io_out_target_b_imm32_lo = {_io_out_target_b_imm32_T_4, 1'h0}; // @[consts.scala:337:{22,68}] wire [20:0] io_out_target_b_imm32_hi_hi = {_io_out_target_b_imm32_T_1, _io_out_target_b_imm32_T_2}; // @[consts.scala:337:{22,27,46}] wire [26:0] io_out_target_b_imm32_hi = {io_out_target_b_imm32_hi_hi, _io_out_target_b_imm32_T_3}; // @[consts.scala:337:{22,55}] wire [31:0] io_out_target_b_imm32 = {io_out_target_b_imm32_hi, io_out_target_b_imm32_lo}; // @[consts.scala:337:22] wire [31:0] _io_out_target_T_1 = io_out_target_b_imm32; // @[consts.scala:337:22, :338:27] wire [40:0] _io_out_target_T_2 = {_io_out_target_T[39], _io_out_target_T} + {{9{_io_out_target_T_1[31]}}, _io_out_target_T_1}; // @[consts.scala:338:{10,17,27}] wire [39:0] _io_out_target_T_3 = _io_out_target_T_2[39:0]; // @[consts.scala:338:17] wire [39:0] _io_out_target_T_4 = _io_out_target_T_3; // @[consts.scala:338:17] wire [39:0] _io_out_target_T_5 = _io_out_target_T_4 & 40'hFFFFFFFFFE; // @[consts.scala:338:{17,42}] wire [39:0] _io_out_target_T_6 = _io_out_target_T_5; // @[consts.scala:338:42] wire [39:0] _io_out_target_T_7 = _io_out_target_T_6; // @[consts.scala:338:{42,52}] wire [11:0] _io_out_target_j_imm32_T_1 = {12{_io_out_target_j_imm32_T}}; // @[consts.scala:343:{27,35}] wire [7:0] _io_out_target_j_imm32_T_2 = io_inst_0[19:12]; // @[decode.scala:623:7] wire _io_out_target_j_imm32_T_3 = io_inst_0[20]; // @[decode.scala:623:7] wire [3:0] _io_out_target_j_imm32_T_5 = io_inst_0[24:21]; // @[decode.scala:623:7] wire [9:0] io_out_target_j_imm32_lo_hi = {_io_out_target_j_imm32_T_4, _io_out_target_j_imm32_T_5}; // @[consts.scala:343:{22,69,82}] wire [10:0] io_out_target_j_imm32_lo = {io_out_target_j_imm32_lo_hi, 1'h0}; // @[consts.scala:343:22] wire [19:0] io_out_target_j_imm32_hi_hi = {_io_out_target_j_imm32_T_1, _io_out_target_j_imm32_T_2}; // @[consts.scala:343:{22,27,46}] wire [20:0] io_out_target_j_imm32_hi = {io_out_target_j_imm32_hi_hi, _io_out_target_j_imm32_T_3}; // @[consts.scala:343:{22,59}] wire [31:0] io_out_target_j_imm32 = {io_out_target_j_imm32_hi, io_out_target_j_imm32_lo}; // @[consts.scala:343:22] wire [31:0] _io_out_target_T_9 = io_out_target_j_imm32; // @[consts.scala:343:22, :344:27] wire [40:0] _io_out_target_T_10 = {_io_out_target_T_8[39], _io_out_target_T_8} + {{9{_io_out_target_T_9[31]}}, _io_out_target_T_9}; // @[consts.scala:344:{10,17,27}] wire [39:0] _io_out_target_T_11 = _io_out_target_T_10[39:0]; // @[consts.scala:344:17] wire [39:0] _io_out_target_T_12 = _io_out_target_T_11; // @[consts.scala:344:17] wire [39:0] _io_out_target_T_13 = _io_out_target_T_12 & 40'hFFFFFFFFFE; // @[consts.scala:344:{17,42}] wire [39:0] _io_out_target_T_14 = _io_out_target_T_13; // @[consts.scala:344:42] wire [39:0] _io_out_target_T_15 = _io_out_target_T_14; // @[consts.scala:344:{42,52}] assign _io_out_target_T_16 = cs_is_br ? _io_out_target_T_7 : _io_out_target_T_15; // @[decode.scala:688:33, :697:23] assign io_out_target_0 = _io_out_target_T_16; // @[decode.scala:623:7, :697:23] wire [2:0] _io_out_cfi_type_T = {2'h0, cs_is_br}; // @[decode.scala:688:33, :704:8] wire [2:0] _io_out_cfi_type_T_1 = cs_is_jal ? 3'h2 : _io_out_cfi_type_T; // @[decode.scala:689:34, :702:8, :704:8] assign _io_out_cfi_type_T_2 = cs_is_jalr ? 3'h3 : _io_out_cfi_type_T_1; // @[decode.scala:690:35, :700:8, :702:8] assign io_out_cfi_type_0 = _io_out_cfi_type_T_2; // @[decode.scala:623:7, :700:8] wire [4:0] br_offset_lo = {_br_offset_T_2, 1'h0}; // @[decode.scala:708:{22,58}] wire [6:0] br_offset_hi = {_br_offset_T, _br_offset_T_1}; // @[decode.scala:708:{22,30,42}] wire [11:0] br_offset = {br_offset_hi, br_offset_lo}; // @[decode.scala:708:22] wire _io_out_sfb_offset_valid_T_1 = ~_io_out_sfb_offset_valid_T; // @[decode.scala:710:{42,50}] wire _io_out_sfb_offset_valid_T_2 = cs_is_br & _io_out_sfb_offset_valid_T_1; // @[decode.scala:688:33, :710:{39,42}] wire _io_out_sfb_offset_valid_T_3 = \|br_offset; // @[decode.scala:708:22, :710:68] wire _io_out_sfb_offset_valid_T_4 = _io_out_sfb_offset_valid_T_2 & _io_out_sfb_offset_valid_T_3; // @[decode.scala:710:{39,55,68}] wire [5:0] _io_out_sfb_offset_valid_T_5 = br_offset[11:6]; // @[decode.scala:708:22, :710:90] wire _io_out_sfb_offset_valid_T_6 = _io_out_sfb_offset_valid_T_5 == 6'h0; // @[decode.scala:710:{90,117}] assign _io_out_sfb_offset_valid_T_7 = _io_out_sfb_offset_valid_T_4 & _io_out_sfb_offset_valid_T_6; // @[decode.scala:710:{55,76,117}] assign io_out_sfb_offset_valid_0 = _io_out_sfb_offset_valid_T_7; // @[decode.scala:623:7, :710:76] assign io_out_sfb_offset_bits_0 = br_offset[5:0]; // @[decode.scala:623:7, :708:22, :711:27] wire _io_out_shadowable_T = ~cs_has_rs2; // @[decode.scala:692:35, :713:5] wire _io_out_shadowable_T_3 = _io_out_shadowable_T_1 == _io_out_shadowable_T_2; // @[decode.scala:714:22] wire _io_out_shadowable_T_4 = _io_out_shadowable_T \| _io_out_shadowable_T_3; // @[decode.scala:713:{5,17}, :714:22] wire [31:0] _io_out_shadowable_T_5 = io_inst_0 & 32'hFE00707F; // @[decode.scala:623:7, :715:14] wire _io_out_shadowable_T_6 = _io_out_shadowable_T_5 == 32'h33; // @[decode.scala:715:14] wire _io_out_shadowable_T_8 = _io_out_shadowable_T_7 == 5'h0; // @[decode.scala:695:90, :715:41] wire _io_out_shadowable_T_9 = _io_out_shadowable_T_6 & _io_out_shadowable_T_8; // @[decode.scala:715:{14,22,41}] wire _io_out_shadowable_T_10 = _io_out_shadowable_T_4 \| _io_out_shadowable_T_9; // @[decode.scala:713:17, :714:42, :715:22] assign _io_out_shadowable_T_11 = cs_is_shadowable & _io_out_shadowable_T_10; // @[decode.scala:691:41, :712:41, :714:42] assign io_out_shadowable_0 = _io_out_shadowable_T_11; // @[decode.scala:623:7, :712:41] assign io_out_is_ret = io_out_is_ret_0; // @[decode.scala:623:7] assign io_out_is_call = io_out_is_call_0; // @[decode.scala:623:7] assign io_out_target = io_out_target_0; // @[decode.scala:623:7] assign io_out_cfi_type = io_out_cfi_type_0; // @[decode.scala:623:7] assign io_out_sfb_offset_valid = io_out_sfb_offset_valid_0; // @[decode.scala:623:7] assign io_out_sfb_offset_bits = io_out_sfb_offset_bits_0; // @[decode.scala:623:7] assign io_out_shadowable = io_out_shadowable_0; // @[decode.scala:623:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module IntToFP : input clock : Clock input reset : Reset output io : { flip in : { valid : UInt<1>, bits : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<64>}}, out : { valid : UInt<1>, bits : { data : UInt<65>, exc : UInt<5>}}} regreset in_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect in_pipe_v, io.in.valid reg in_pipe_b : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<64>}, clock when io.in.valid : connect in_pipe_b, io.in.bits wire in : { valid : UInt<1>, bits : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<64>}} connect in.valid, in_pipe_v connect in.bits, in_pipe_b wire mux : { data : UInt<65>, exc : UInt<5>} connect mux.exc, UInt<1>(0h0) node _mux_data_T = eq(in.bits.typeTagIn, UInt<1>(0h1)) node _mux_data_T_1 = mux(_mux_data_T, UInt<64>(0hffffffff00000000), UInt<64>(0hffffffffffff0000)) node _mux_data_T_2 = eq(in.bits.typeTagIn, UInt<2>(0h2)) node _mux_data_T_3 = mux(_mux_data_T_2, UInt<1>(0h0), _mux_data_T_1) node _mux_data_T_4 = eq(in.bits.typeTagIn, UInt<2>(0h3)) node _mux_data_T_5 = mux(_mux_data_T_4, UInt<1>(0h0), _mux_data_T_3) node _mux_data_T_6 = or(_mux_data_T_5, in.bits.in1) node mux_data_rawIn_sign = bits(_mux_data_T_6, 63, 63) node mux_data_rawIn_expIn = bits(_mux_data_T_6, 62, 52) node mux_data_rawIn_fractIn = bits(_mux_data_T_6, 51, 0) node mux_data_rawIn_isZeroExpIn = eq(mux_data_rawIn_expIn, UInt<1>(0h0)) node mux_data_rawIn_isZeroFractIn = eq(mux_data_rawIn_fractIn, UInt<1>(0h0)) node _mux_data_rawIn_normDist_T = bits(mux_data_rawIn_fractIn, 0, 0) node _mux_data_rawIn_normDist_T_1 = bits(mux_data_rawIn_fractIn, 1, 1) node _mux_data_rawIn_normDist_T_2 = bits(mux_data_rawIn_fractIn, 2, 2) node _mux_data_rawIn_normDist_T_3 = bits(mux_data_rawIn_fractIn, 3, 3) node _mux_data_rawIn_normDist_T_4 = bits(mux_data_rawIn_fractIn, 4, 4) node _mux_data_rawIn_normDist_T_5 = bits(mux_data_rawIn_fractIn, 5, 5) node _mux_data_rawIn_normDist_T_6 = bits(mux_data_rawIn_fractIn, 6, 6) node _mux_data_rawIn_normDist_T_7 = bits(mux_data_rawIn_fractIn, 7, 7) node _mux_data_rawIn_normDist_T_8 = bits(mux_data_rawIn_fractIn, 8, 8) node _mux_data_rawIn_normDist_T_9 = bits(mux_data_rawIn_fractIn, 9, 9) node _mux_data_rawIn_normDist_T_10 = bits(mux_data_rawIn_fractIn, 10, 10) node _mux_data_rawIn_normDist_T_11 = bits(mux_data_rawIn_fractIn, 11, 11) node _mux_data_rawIn_normDist_T_12 = bits(mux_data_rawIn_fractIn, 12, 12) node _mux_data_rawIn_normDist_T_13 = bits(mux_data_rawIn_fractIn, 13, 13) node _mux_data_rawIn_normDist_T_14 = bits(mux_data_rawIn_fractIn, 14, 14) node _mux_data_rawIn_normDist_T_15 = bits(mux_data_rawIn_fractIn, 15, 15) node _mux_data_rawIn_normDist_T_16 = bits(mux_data_rawIn_fractIn, 16, 16) node _mux_data_rawIn_normDist_T_17 = bits(mux_data_rawIn_fractIn, 17, 17) node _mux_data_rawIn_normDist_T_18 = bits(mux_data_rawIn_fractIn, 18, 18) node _mux_data_rawIn_normDist_T_19 = bits(mux_data_rawIn_fractIn, 19, 19) node _mux_data_rawIn_normDist_T_20 = bits(mux_data_rawIn_fractIn, 20, 20) node _mux_data_rawIn_normDist_T_21 = bits(mux_data_rawIn_fractIn, 21, 21) node _mux_data_rawIn_normDist_T_22 = bits(mux_data_rawIn_fractIn, 22, 22) node _mux_data_rawIn_normDist_T_23 = bits(mux_data_rawIn_fractIn, 23, 23) node _mux_data_rawIn_normDist_T_24 = bits(mux_data_rawIn_fractIn, 24, 24) node _mux_data_rawIn_normDist_T_25 = bits(mux_data_rawIn_fractIn, 25, 25) node _mux_data_rawIn_normDist_T_26 = bits(mux_data_rawIn_fractIn, 26, 26) node _mux_data_rawIn_normDist_T_27 = bits(mux_data_rawIn_fractIn, 27, 27) node _mux_data_rawIn_normDist_T_28 = bits(mux_data_rawIn_fractIn, 28, 28) node _mux_data_rawIn_normDist_T_29 = bits(mux_data_rawIn_fractIn, 29, 29) node _mux_data_rawIn_normDist_T_30 = bits(mux_data_rawIn_fractIn, 30, 30) node _mux_data_rawIn_normDist_T_31 = bits(mux_data_rawIn_fractIn, 31, 31) node _mux_data_rawIn_normDist_T_32 = bits(mux_data_rawIn_fractIn, 32, 32) node _mux_data_rawIn_normDist_T_33 = bits(mux_data_rawIn_fractIn, 33, 33) node _mux_data_rawIn_normDist_T_34 = bits(mux_data_rawIn_fractIn, 34, 34) node _mux_data_rawIn_normDist_T_35 = bits(mux_data_rawIn_fractIn, 35, 35) node _mux_data_rawIn_normDist_T_36 = bits(mux_data_rawIn_fractIn, 36, 36) node _mux_data_rawIn_normDist_T_37 = bits(mux_data_rawIn_fractIn, 37, 37) node _mux_data_rawIn_normDist_T_38 = bits(mux_data_rawIn_fractIn, 38, 38) node _mux_data_rawIn_normDist_T_39 = bits(mux_data_rawIn_fractIn, 39, 39) node _mux_data_rawIn_normDist_T_40 = bits(mux_data_rawIn_fractIn, 40, 40) node _mux_data_rawIn_normDist_T_41 = bits(mux_data_rawIn_fractIn, 41, 41) node _mux_data_rawIn_normDist_T_42 = bits(mux_data_rawIn_fractIn, 42, 42) node _mux_data_rawIn_normDist_T_43 = bits(mux_data_rawIn_fractIn, 43, 43) node _mux_data_rawIn_normDist_T_44 = bits(mux_data_rawIn_fractIn, 44, 44) node _mux_data_rawIn_normDist_T_45 = bits(mux_data_rawIn_fractIn, 45, 45) node _mux_data_rawIn_normDist_T_46 = bits(mux_data_rawIn_fractIn, 46, 46) node _mux_data_rawIn_normDist_T_47 = bits(mux_data_rawIn_fractIn, 47, 47) node _mux_data_rawIn_normDist_T_48 = bits(mux_data_rawIn_fractIn, 48, 48) node _mux_data_rawIn_normDist_T_49 = bits(mux_data_rawIn_fractIn, 49, 49) node _mux_data_rawIn_normDist_T_50 = bits(mux_data_rawIn_fractIn, 50, 50) node _mux_data_rawIn_normDist_T_51 = bits(mux_data_rawIn_fractIn, 51, 51) node _mux_data_rawIn_normDist_T_52 = mux(_mux_data_rawIn_normDist_T_1, UInt<6>(0h32), UInt<6>(0h33)) node _mux_data_rawIn_normDist_T_53 = mux(_mux_data_rawIn_normDist_T_2, UInt<6>(0h31), _mux_data_rawIn_normDist_T_52) node _mux_data_rawIn_normDist_T_54 = mux(_mux_data_rawIn_normDist_T_3, UInt<6>(0h30), _mux_data_rawIn_normDist_T_53) node _mux_data_rawIn_normDist_T_55 = mux(_mux_data_rawIn_normDist_T_4, UInt<6>(0h2f), _mux_data_rawIn_normDist_T_54) node _mux_data_rawIn_normDist_T_56 = mux(_mux_data_rawIn_normDist_T_5, UInt<6>(0h2e), _mux_data_rawIn_normDist_T_55) node _mux_data_rawIn_normDist_T_57 = mux(_mux_data_rawIn_normDist_T_6, UInt<6>(0h2d), _mux_data_rawIn_normDist_T_56) node _mux_data_rawIn_normDist_T_58 = mux(_mux_data_rawIn_normDist_T_7, UInt<6>(0h2c), _mux_data_rawIn_normDist_T_57) node _mux_data_rawIn_normDist_T_59 = mux(_mux_data_rawIn_normDist_T_8, UInt<6>(0h2b), _mux_data_rawIn_normDist_T_58) node _mux_data_rawIn_normDist_T_60 = mux(_mux_data_rawIn_normDist_T_9, UInt<6>(0h2a), _mux_data_rawIn_normDist_T_59) node _mux_data_rawIn_normDist_T_61 = mux(_mux_data_rawIn_normDist_T_10, UInt<6>(0h29), _mux_data_rawIn_normDist_T_60) node _mux_data_rawIn_normDist_T_62 = mux(_mux_data_rawIn_normDist_T_11, UInt<6>(0h28), _mux_data_rawIn_normDist_T_61) node _mux_data_rawIn_normDist_T_63 = mux(_mux_data_rawIn_normDist_T_12, UInt<6>(0h27), _mux_data_rawIn_normDist_T_62) node _mux_data_rawIn_normDist_T_64 = mux(_mux_data_rawIn_normDist_T_13, UInt<6>(0h26), _mux_data_rawIn_normDist_T_63) node _mux_data_rawIn_normDist_T_65 = mux(_mux_data_rawIn_normDist_T_14, UInt<6>(0h25), _mux_data_rawIn_normDist_T_64) node _mux_data_rawIn_normDist_T_66 = mux(_mux_data_rawIn_normDist_T_15, UInt<6>(0h24), _mux_data_rawIn_normDist_T_65) node _mux_data_rawIn_normDist_T_67 = mux(_mux_data_rawIn_normDist_T_16, UInt<6>(0h23), _mux_data_rawIn_normDist_T_66) node _mux_data_rawIn_normDist_T_68 = mux(_mux_data_rawIn_normDist_T_17, UInt<6>(0h22), _mux_data_rawIn_normDist_T_67) node _mux_data_rawIn_normDist_T_69 = mux(_mux_data_rawIn_normDist_T_18, UInt<6>(0h21), _mux_data_rawIn_normDist_T_68) node _mux_data_rawIn_normDist_T_70 = mux(_mux_data_rawIn_normDist_T_19, UInt<6>(0h20), _mux_data_rawIn_normDist_T_69) node _mux_data_rawIn_normDist_T_71 = mux(_mux_data_rawIn_normDist_T_20, UInt<5>(0h1f), _mux_data_rawIn_normDist_T_70) node _mux_data_rawIn_normDist_T_72 = mux(_mux_data_rawIn_normDist_T_21, UInt<5>(0h1e), _mux_data_rawIn_normDist_T_71) node _mux_data_rawIn_normDist_T_73 = mux(_mux_data_rawIn_normDist_T_22, UInt<5>(0h1d), _mux_data_rawIn_normDist_T_72) node _mux_data_rawIn_normDist_T_74 = mux(_mux_data_rawIn_normDist_T_23, UInt<5>(0h1c), _mux_data_rawIn_normDist_T_73) node _mux_data_rawIn_normDist_T_75 = mux(_mux_data_rawIn_normDist_T_24, UInt<5>(0h1b), _mux_data_rawIn_normDist_T_74) node _mux_data_rawIn_normDist_T_76 = mux(_mux_data_rawIn_normDist_T_25, UInt<5>(0h1a), _mux_data_rawIn_normDist_T_75) node _mux_data_rawIn_normDist_T_77 = mux(_mux_data_rawIn_normDist_T_26, UInt<5>(0h19), _mux_data_rawIn_normDist_T_76) node _mux_data_rawIn_normDist_T_78 = mux(_mux_data_rawIn_normDist_T_27, UInt<5>(0h18), _mux_data_rawIn_normDist_T_77) node _mux_data_rawIn_normDist_T_79 = mux(_mux_data_rawIn_normDist_T_28, UInt<5>(0h17), _mux_data_rawIn_normDist_T_78) node _mux_data_rawIn_normDist_T_80 = mux(_mux_data_rawIn_normDist_T_29, UInt<5>(0h16), _mux_data_rawIn_normDist_T_79) node _mux_data_rawIn_normDist_T_81 = mux(_mux_data_rawIn_normDist_T_30, UInt<5>(0h15), _mux_data_rawIn_normDist_T_80) node _mux_data_rawIn_normDist_T_82 = mux(_mux_data_rawIn_normDist_T_31, UInt<5>(0h14), _mux_data_rawIn_normDist_T_81) node _mux_data_rawIn_normDist_T_83 = mux(_mux_data_rawIn_normDist_T_32, UInt<5>(0h13), _mux_data_rawIn_normDist_T_82) node _mux_data_rawIn_normDist_T_84 = mux(_mux_data_rawIn_normDist_T_33, UInt<5>(0h12), _mux_data_rawIn_normDist_T_83) node _mux_data_rawIn_normDist_T_85 = mux(_mux_data_rawIn_normDist_T_34, UInt<5>(0h11), _mux_data_rawIn_normDist_T_84) node _mux_data_rawIn_normDist_T_86 = mux(_mux_data_rawIn_normDist_T_35, UInt<5>(0h10), _mux_data_rawIn_normDist_T_85) node _mux_data_rawIn_normDist_T_87 = mux(_mux_data_rawIn_normDist_T_36, UInt<4>(0hf), _mux_data_rawIn_normDist_T_86) node _mux_data_rawIn_normDist_T_88 = mux(_mux_data_rawIn_normDist_T_37, UInt<4>(0he), _mux_data_rawIn_normDist_T_87) node _mux_data_rawIn_normDist_T_89 = mux(_mux_data_rawIn_normDist_T_38, UInt<4>(0hd), _mux_data_rawIn_normDist_T_88) node _mux_data_rawIn_normDist_T_90 = mux(_mux_data_rawIn_normDist_T_39, UInt<4>(0hc), _mux_data_rawIn_normDist_T_89) node _mux_data_rawIn_normDist_T_91 = mux(_mux_data_rawIn_normDist_T_40, UInt<4>(0hb), _mux_data_rawIn_normDist_T_90) node _mux_data_rawIn_normDist_T_92 = mux(_mux_data_rawIn_normDist_T_41, UInt<4>(0ha), _mux_data_rawIn_normDist_T_91) node _mux_data_rawIn_normDist_T_93 = mux(_mux_data_rawIn_normDist_T_42, UInt<4>(0h9), _mux_data_rawIn_normDist_T_92) node _mux_data_rawIn_normDist_T_94 = mux(_mux_data_rawIn_normDist_T_43, UInt<4>(0h8), _mux_data_rawIn_normDist_T_93) node _mux_data_rawIn_normDist_T_95 = mux(_mux_data_rawIn_normDist_T_44, UInt<3>(0h7), _mux_data_rawIn_normDist_T_94) node _mux_data_rawIn_normDist_T_96 = mux(_mux_data_rawIn_normDist_T_45, UInt<3>(0h6), _mux_data_rawIn_normDist_T_95) node _mux_data_rawIn_normDist_T_97 = mux(_mux_data_rawIn_normDist_T_46, UInt<3>(0h5), _mux_data_rawIn_normDist_T_96) node _mux_data_rawIn_normDist_T_98 = mux(_mux_data_rawIn_normDist_T_47, UInt<3>(0h4), _mux_data_rawIn_normDist_T_97) node _mux_data_rawIn_normDist_T_99 = mux(_mux_data_rawIn_normDist_T_48, UInt<2>(0h3), _mux_data_rawIn_normDist_T_98) node _mux_data_rawIn_normDist_T_100 = mux(_mux_data_rawIn_normDist_T_49, UInt<2>(0h2), _mux_data_rawIn_normDist_T_99) node _mux_data_rawIn_normDist_T_101 = mux(_mux_data_rawIn_normDist_T_50, UInt<1>(0h1), _mux_data_rawIn_normDist_T_100) node mux_data_rawIn_normDist = mux(_mux_data_rawIn_normDist_T_51, UInt<1>(0h0), _mux_data_rawIn_normDist_T_101) node _mux_data_rawIn_subnormFract_T = dshl(mux_data_rawIn_fractIn, mux_data_rawIn_normDist) node _mux_data_rawIn_subnormFract_T_1 = bits(_mux_data_rawIn_subnormFract_T, 50, 0) node mux_data_rawIn_subnormFract = shl(_mux_data_rawIn_subnormFract_T_1, 1) node _mux_data_rawIn_adjustedExp_T = xor(mux_data_rawIn_normDist, UInt<12>(0hfff)) node _mux_data_rawIn_adjustedExp_T_1 = mux(mux_data_rawIn_isZeroExpIn, _mux_data_rawIn_adjustedExp_T, mux_data_rawIn_expIn) node _mux_data_rawIn_adjustedExp_T_2 = mux(mux_data_rawIn_isZeroExpIn, UInt<2>(0h2), UInt<1>(0h1)) node _mux_data_rawIn_adjustedExp_T_3 = or(UInt<11>(0h400), _mux_data_rawIn_adjustedExp_T_2) node _mux_data_rawIn_adjustedExp_T_4 = add(_mux_data_rawIn_adjustedExp_T_1, _mux_data_rawIn_adjustedExp_T_3) node mux_data_rawIn_adjustedExp = tail(_mux_data_rawIn_adjustedExp_T_4, 1) node mux_data_rawIn_isZero = and(mux_data_rawIn_isZeroExpIn, mux_data_rawIn_isZeroFractIn) node _mux_data_rawIn_isSpecial_T = bits(mux_data_rawIn_adjustedExp, 11, 10) node mux_data_rawIn_isSpecial = eq(_mux_data_rawIn_isSpecial_T, UInt<2>(0h3)) wire mux_data_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} node _mux_data_rawIn_out_isNaN_T = eq(mux_data_rawIn_isZeroFractIn, UInt<1>(0h0)) node _mux_data_rawIn_out_isNaN_T_1 = and(mux_data_rawIn_isSpecial, _mux_data_rawIn_out_isNaN_T) connect mux_data_rawIn.isNaN, _mux_data_rawIn_out_isNaN_T_1 node _mux_data_rawIn_out_isInf_T = and(mux_data_rawIn_isSpecial, mux_data_rawIn_isZeroFractIn) connect mux_data_rawIn.isInf, _mux_data_rawIn_out_isInf_T connect mux_data_rawIn.isZero, mux_data_rawIn_isZero connect mux_data_rawIn.sign, mux_data_rawIn_sign node _mux_data_rawIn_out_sExp_T = bits(mux_data_rawIn_adjustedExp, 11, 0) node _mux_data_rawIn_out_sExp_T_1 = cvt(_mux_data_rawIn_out_sExp_T) connect mux_data_rawIn.sExp, _mux_data_rawIn_out_sExp_T_1 node _mux_data_rawIn_out_sig_T = eq(mux_data_rawIn_isZero, UInt<1>(0h0)) node _mux_data_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _mux_data_rawIn_out_sig_T) node _mux_data_rawIn_out_sig_T_2 = mux(mux_data_rawIn_isZeroExpIn, mux_data_rawIn_subnormFract, mux_data_rawIn_fractIn) node _mux_data_rawIn_out_sig_T_3 = cat(_mux_data_rawIn_out_sig_T_1, _mux_data_rawIn_out_sig_T_2) connect mux_data_rawIn.sig, _mux_data_rawIn_out_sig_T_3 node _mux_data_T_7 = bits(mux_data_rawIn.sExp, 11, 9) node _mux_data_T_8 = mux(mux_data_rawIn.isZero, UInt<3>(0h0), _mux_data_T_7) node _mux_data_T_9 = mux(mux_data_rawIn.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _mux_data_T_10 = or(_mux_data_T_8, _mux_data_T_9) node _mux_data_T_11 = cat(mux_data_rawIn.sign, _mux_data_T_10) node _mux_data_T_12 = bits(mux_data_rawIn.sExp, 8, 0) node _mux_data_T_13 = cat(_mux_data_T_11, _mux_data_T_12) node _mux_data_T_14 = bits(mux_data_rawIn.sig, 51, 0) node _mux_data_T_15 = cat(_mux_data_T_13, _mux_data_T_14) node mux_data_rawIn_sign_1 = bits(_mux_data_T_6, 31, 31) node mux_data_rawIn_expIn_1 = bits(_mux_data_T_6, 30, 23) node mux_data_rawIn_fractIn_1 = bits(_mux_data_T_6, 22, 0) node mux_data_rawIn_isZeroExpIn_1 = eq(mux_data_rawIn_expIn_1, UInt<1>(0h0)) node mux_data_rawIn_isZeroFractIn_1 = eq(mux_data_rawIn_fractIn_1, UInt<1>(0h0)) node _mux_data_rawIn_normDist_T_102 = bits(mux_data_rawIn_fractIn_1, 0, 0) node _mux_data_rawIn_normDist_T_103 = bits(mux_data_rawIn_fractIn_1, 1, 1) node _mux_data_rawIn_normDist_T_104 = bits(mux_data_rawIn_fractIn_1, 2, 2) node _mux_data_rawIn_normDist_T_105 = bits(mux_data_rawIn_fractIn_1, 3, 3) node _mux_data_rawIn_normDist_T_106 = bits(mux_data_rawIn_fractIn_1, 4, 4) node _mux_data_rawIn_normDist_T_107 = bits(mux_data_rawIn_fractIn_1, 5, 5) node _mux_data_rawIn_normDist_T_108 = bits(mux_data_rawIn_fractIn_1, 6, 6) node _mux_data_rawIn_normDist_T_109 = bits(mux_data_rawIn_fractIn_1, 7, 7) node _mux_data_rawIn_normDist_T_110 = bits(mux_data_rawIn_fractIn_1, 8, 8) node _mux_data_rawIn_normDist_T_111 = bits(mux_data_rawIn_fractIn_1, 9, 9) node _mux_data_rawIn_normDist_T_112 = bits(mux_data_rawIn_fractIn_1, 10, 10) node _mux_data_rawIn_normDist_T_113 = bits(mux_data_rawIn_fractIn_1, 11, 11) node _mux_data_rawIn_normDist_T_114 = bits(mux_data_rawIn_fractIn_1, 12, 12) node _mux_data_rawIn_normDist_T_115 = bits(mux_data_rawIn_fractIn_1, 13, 13) node _mux_data_rawIn_normDist_T_116 = bits(mux_data_rawIn_fractIn_1, 14, 14) node _mux_data_rawIn_normDist_T_117 = bits(mux_data_rawIn_fractIn_1, 15, 15) node _mux_data_rawIn_normDist_T_118 = bits(mux_data_rawIn_fractIn_1, 16, 16) node _mux_data_rawIn_normDist_T_119 = bits(mux_data_rawIn_fractIn_1, 17, 17) node _mux_data_rawIn_normDist_T_120 = bits(mux_data_rawIn_fractIn_1, 18, 18) node _mux_data_rawIn_normDist_T_121 = bits(mux_data_rawIn_fractIn_1, 19, 19) node _mux_data_rawIn_normDist_T_122 = bits(mux_data_rawIn_fractIn_1, 20, 20) node _mux_data_rawIn_normDist_T_123 = bits(mux_data_rawIn_fractIn_1, 21, 21) node _mux_data_rawIn_normDist_T_124 = bits(mux_data_rawIn_fractIn_1, 22, 22) node _mux_data_rawIn_normDist_T_125 = mux(_mux_data_rawIn_normDist_T_103, UInt<5>(0h15), UInt<5>(0h16)) node _mux_data_rawIn_normDist_T_126 = mux(_mux_data_rawIn_normDist_T_104, UInt<5>(0h14), _mux_data_rawIn_normDist_T_125) node _mux_data_rawIn_normDist_T_127 = mux(_mux_data_rawIn_normDist_T_105, UInt<5>(0h13), _mux_data_rawIn_normDist_T_126) node _mux_data_rawIn_normDist_T_128 = mux(_mux_data_rawIn_normDist_T_106, UInt<5>(0h12), _mux_data_rawIn_normDist_T_127) node _mux_data_rawIn_normDist_T_129 = mux(_mux_data_rawIn_normDist_T_107, UInt<5>(0h11), _mux_data_rawIn_normDist_T_128) node _mux_data_rawIn_normDist_T_130 = mux(_mux_data_rawIn_normDist_T_108, UInt<5>(0h10), _mux_data_rawIn_normDist_T_129) node _mux_data_rawIn_normDist_T_131 = mux(_mux_data_rawIn_normDist_T_109, UInt<4>(0hf), _mux_data_rawIn_normDist_T_130) node _mux_data_rawIn_normDist_T_132 = mux(_mux_data_rawIn_normDist_T_110, UInt<4>(0he), _mux_data_rawIn_normDist_T_131) node _mux_data_rawIn_normDist_T_133 = mux(_mux_data_rawIn_normDist_T_111, UInt<4>(0hd), _mux_data_rawIn_normDist_T_132) node _mux_data_rawIn_normDist_T_134 = mux(_mux_data_rawIn_normDist_T_112, UInt<4>(0hc), _mux_data_rawIn_normDist_T_133) node _mux_data_rawIn_normDist_T_135 = mux(_mux_data_rawIn_normDist_T_113, UInt<4>(0hb), _mux_data_rawIn_normDist_T_134) node _mux_data_rawIn_normDist_T_136 = mux(_mux_data_rawIn_normDist_T_114, UInt<4>(0ha), _mux_data_rawIn_normDist_T_135) node _mux_data_rawIn_normDist_T_137 = mux(_mux_data_rawIn_normDist_T_115, UInt<4>(0h9), _mux_data_rawIn_normDist_T_136) node _mux_data_rawIn_normDist_T_138 = mux(_mux_data_rawIn_normDist_T_116, UInt<4>(0h8), _mux_data_rawIn_normDist_T_137) node _mux_data_rawIn_normDist_T_139 = mux(_mux_data_rawIn_normDist_T_117, UInt<3>(0h7), _mux_data_rawIn_normDist_T_138) node _mux_data_rawIn_normDist_T_140 = mux(_mux_data_rawIn_normDist_T_118, UInt<3>(0h6), _mux_data_rawIn_normDist_T_139) node _mux_data_rawIn_normDist_T_141 = mux(_mux_data_rawIn_normDist_T_119, UInt<3>(0h5), _mux_data_rawIn_normDist_T_140) node _mux_data_rawIn_normDist_T_142 = mux(_mux_data_rawIn_normDist_T_120, UInt<3>(0h4), _mux_data_rawIn_normDist_T_141) node _mux_data_rawIn_normDist_T_143 = mux(_mux_data_rawIn_normDist_T_121, UInt<2>(0h3), _mux_data_rawIn_normDist_T_142) node _mux_data_rawIn_normDist_T_144 = mux(_mux_data_rawIn_normDist_T_122, UInt<2>(0h2), _mux_data_rawIn_normDist_T_143) node _mux_data_rawIn_normDist_T_145 = mux(_mux_data_rawIn_normDist_T_123, UInt<1>(0h1), _mux_data_rawIn_normDist_T_144) node mux_data_rawIn_normDist_1 = mux(_mux_data_rawIn_normDist_T_124, UInt<1>(0h0), _mux_data_rawIn_normDist_T_145) node _mux_data_rawIn_subnormFract_T_2 = dshl(mux_data_rawIn_fractIn_1, mux_data_rawIn_normDist_1) node _mux_data_rawIn_subnormFract_T_3 = bits(_mux_data_rawIn_subnormFract_T_2, 21, 0) node mux_data_rawIn_subnormFract_1 = shl(_mux_data_rawIn_subnormFract_T_3, 1) node _mux_data_rawIn_adjustedExp_T_5 = xor(mux_data_rawIn_normDist_1, UInt<9>(0h1ff)) node _mux_data_rawIn_adjustedExp_T_6 = mux(mux_data_rawIn_isZeroExpIn_1, _mux_data_rawIn_adjustedExp_T_5, mux_data_rawIn_expIn_1) node _mux_data_rawIn_adjustedExp_T_7 = mux(mux_data_rawIn_isZeroExpIn_1, UInt<2>(0h2), UInt<1>(0h1)) node _mux_data_rawIn_adjustedExp_T_8 = or(UInt<8>(0h80), _mux_data_rawIn_adjustedExp_T_7) node _mux_data_rawIn_adjustedExp_T_9 = add(_mux_data_rawIn_adjustedExp_T_6, _mux_data_rawIn_adjustedExp_T_8) node mux_data_rawIn_adjustedExp_1 = tail(_mux_data_rawIn_adjustedExp_T_9, 1) node mux_data_rawIn_isZero_1 = and(mux_data_rawIn_isZeroExpIn_1, mux_data_rawIn_isZeroFractIn_1) node _mux_data_rawIn_isSpecial_T_1 = bits(mux_data_rawIn_adjustedExp_1, 8, 7) node mux_data_rawIn_isSpecial_1 = eq(_mux_data_rawIn_isSpecial_T_1, UInt<2>(0h3)) wire mux_data_rawIn_1 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _mux_data_rawIn_out_isNaN_T_2 = eq(mux_data_rawIn_isZeroFractIn_1, UInt<1>(0h0)) node _mux_data_rawIn_out_isNaN_T_3 = and(mux_data_rawIn_isSpecial_1, _mux_data_rawIn_out_isNaN_T_2) connect mux_data_rawIn_1.isNaN, _mux_data_rawIn_out_isNaN_T_3 node _mux_data_rawIn_out_isInf_T_1 = and(mux_data_rawIn_isSpecial_1, mux_data_rawIn_isZeroFractIn_1) connect mux_data_rawIn_1.isInf, _mux_data_rawIn_out_isInf_T_1 connect mux_data_rawIn_1.isZero, mux_data_rawIn_isZero_1 connect mux_data_rawIn_1.sign, mux_data_rawIn_sign_1 node _mux_data_rawIn_out_sExp_T_2 = bits(mux_data_rawIn_adjustedExp_1, 8, 0) node _mux_data_rawIn_out_sExp_T_3 = cvt(_mux_data_rawIn_out_sExp_T_2) connect mux_data_rawIn_1.sExp, _mux_data_rawIn_out_sExp_T_3 node _mux_data_rawIn_out_sig_T_4 = eq(mux_data_rawIn_isZero_1, UInt<1>(0h0)) node _mux_data_rawIn_out_sig_T_5 = cat(UInt<1>(0h0), _mux_data_rawIn_out_sig_T_4) node _mux_data_rawIn_out_sig_T_6 = mux(mux_data_rawIn_isZeroExpIn_1, mux_data_rawIn_subnormFract_1, mux_data_rawIn_fractIn_1) node _mux_data_rawIn_out_sig_T_7 = cat(_mux_data_rawIn_out_sig_T_5, _mux_data_rawIn_out_sig_T_6) connect mux_data_rawIn_1.sig, _mux_data_rawIn_out_sig_T_7 node _mux_data_T_16 = bits(mux_data_rawIn_1.sExp, 8, 6) node _mux_data_T_17 = mux(mux_data_rawIn_1.isZero, UInt<3>(0h0), _mux_data_T_16) node _mux_data_T_18 = mux(mux_data_rawIn_1.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _mux_data_T_19 = or(_mux_data_T_17, _mux_data_T_18) node _mux_data_T_20 = cat(mux_data_rawIn_1.sign, _mux_data_T_19) node _mux_data_T_21 = bits(mux_data_rawIn_1.sExp, 5, 0) node _mux_data_T_22 = cat(_mux_data_T_20, _mux_data_T_21) node _mux_data_T_23 = bits(mux_data_rawIn_1.sig, 22, 0) node _mux_data_T_24 = cat(_mux_data_T_22, _mux_data_T_23) node mux_data_rawIn_sign_2 = bits(_mux_data_T_6, 15, 15) node mux_data_rawIn_expIn_2 = bits(_mux_data_T_6, 14, 10) node mux_data_rawIn_fractIn_2 = bits(_mux_data_T_6, 9, 0) node mux_data_rawIn_isZeroExpIn_2 = eq(mux_data_rawIn_expIn_2, UInt<1>(0h0)) node mux_data_rawIn_isZeroFractIn_2 = eq(mux_data_rawIn_fractIn_2, UInt<1>(0h0)) node _mux_data_rawIn_normDist_T_146 = bits(mux_data_rawIn_fractIn_2, 0, 0) node _mux_data_rawIn_normDist_T_147 = bits(mux_data_rawIn_fractIn_2, 1, 1) node _mux_data_rawIn_normDist_T_148 = bits(mux_data_rawIn_fractIn_2, 2, 2) node _mux_data_rawIn_normDist_T_149 = bits(mux_data_rawIn_fractIn_2, 3, 3) node _mux_data_rawIn_normDist_T_150 = bits(mux_data_rawIn_fractIn_2, 4, 4) node _mux_data_rawIn_normDist_T_151 = bits(mux_data_rawIn_fractIn_2, 5, 5) node _mux_data_rawIn_normDist_T_152 = bits(mux_data_rawIn_fractIn_2, 6, 6) node _mux_data_rawIn_normDist_T_153 = bits(mux_data_rawIn_fractIn_2, 7, 7) node _mux_data_rawIn_normDist_T_154 = bits(mux_data_rawIn_fractIn_2, 8, 8) node _mux_data_rawIn_normDist_T_155 = bits(mux_data_rawIn_fractIn_2, 9, 9) node _mux_data_rawIn_normDist_T_156 = mux(_mux_data_rawIn_normDist_T_147, UInt<4>(0h8), UInt<4>(0h9)) node _mux_data_rawIn_normDist_T_157 = mux(_mux_data_rawIn_normDist_T_148, UInt<3>(0h7), _mux_data_rawIn_normDist_T_156) node _mux_data_rawIn_normDist_T_158 = mux(_mux_data_rawIn_normDist_T_149, UInt<3>(0h6), _mux_data_rawIn_normDist_T_157) node _mux_data_rawIn_normDist_T_159 = mux(_mux_data_rawIn_normDist_T_150, UInt<3>(0h5), _mux_data_rawIn_normDist_T_158) node _mux_data_rawIn_normDist_T_160 = mux(_mux_data_rawIn_normDist_T_151, UInt<3>(0h4), _mux_data_rawIn_normDist_T_159) node _mux_data_rawIn_normDist_T_161 = mux(_mux_data_rawIn_normDist_T_152, UInt<2>(0h3), _mux_data_rawIn_normDist_T_160) node _mux_data_rawIn_normDist_T_162 = mux(_mux_data_rawIn_normDist_T_153, UInt<2>(0h2), _mux_data_rawIn_normDist_T_161) node _mux_data_rawIn_normDist_T_163 = mux(_mux_data_rawIn_normDist_T_154, UInt<1>(0h1), _mux_data_rawIn_normDist_T_162) node mux_data_rawIn_normDist_2 = mux(_mux_data_rawIn_normDist_T_155, UInt<1>(0h0), _mux_data_rawIn_normDist_T_163) node _mux_data_rawIn_subnormFract_T_4 = dshl(mux_data_rawIn_fractIn_2, mux_data_rawIn_normDist_2) node _mux_data_rawIn_subnormFract_T_5 = bits(_mux_data_rawIn_subnormFract_T_4, 8, 0) node mux_data_rawIn_subnormFract_2 = shl(_mux_data_rawIn_subnormFract_T_5, 1) node _mux_data_rawIn_adjustedExp_T_10 = xor(mux_data_rawIn_normDist_2, UInt<6>(0h3f)) node _mux_data_rawIn_adjustedExp_T_11 = mux(mux_data_rawIn_isZeroExpIn_2, _mux_data_rawIn_adjustedExp_T_10, mux_data_rawIn_expIn_2) node _mux_data_rawIn_adjustedExp_T_12 = mux(mux_data_rawIn_isZeroExpIn_2, UInt<2>(0h2), UInt<1>(0h1)) node _mux_data_rawIn_adjustedExp_T_13 = or(UInt<5>(0h10), _mux_data_rawIn_adjustedExp_T_12) node _mux_data_rawIn_adjustedExp_T_14 = add(_mux_data_rawIn_adjustedExp_T_11, _mux_data_rawIn_adjustedExp_T_13) node mux_data_rawIn_adjustedExp_2 = tail(_mux_data_rawIn_adjustedExp_T_14, 1) node mux_data_rawIn_isZero_2 = and(mux_data_rawIn_isZeroExpIn_2, mux_data_rawIn_isZeroFractIn_2) node _mux_data_rawIn_isSpecial_T_2 = bits(mux_data_rawIn_adjustedExp_2, 5, 4) node mux_data_rawIn_isSpecial_2 = eq(_mux_data_rawIn_isSpecial_T_2, UInt<2>(0h3)) wire mux_data_rawIn_2 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<12>} node _mux_data_rawIn_out_isNaN_T_4 = eq(mux_data_rawIn_isZeroFractIn_2, UInt<1>(0h0)) node _mux_data_rawIn_out_isNaN_T_5 = and(mux_data_rawIn_isSpecial_2, _mux_data_rawIn_out_isNaN_T_4) connect mux_data_rawIn_2.isNaN, _mux_data_rawIn_out_isNaN_T_5 node _mux_data_rawIn_out_isInf_T_2 = and(mux_data_rawIn_isSpecial_2, mux_data_rawIn_isZeroFractIn_2) connect mux_data_rawIn_2.isInf, _mux_data_rawIn_out_isInf_T_2 connect mux_data_rawIn_2.isZero, mux_data_rawIn_isZero_2 connect mux_data_rawIn_2.sign, mux_data_rawIn_sign_2 node _mux_data_rawIn_out_sExp_T_4 = bits(mux_data_rawIn_adjustedExp_2, 5, 0) node _mux_data_rawIn_out_sExp_T_5 = cvt(_mux_data_rawIn_out_sExp_T_4) connect mux_data_rawIn_2.sExp, _mux_data_rawIn_out_sExp_T_5 node _mux_data_rawIn_out_sig_T_8 = eq(mux_data_rawIn_isZero_2, UInt<1>(0h0)) node _mux_data_rawIn_out_sig_T_9 = cat(UInt<1>(0h0), _mux_data_rawIn_out_sig_T_8) node _mux_data_rawIn_out_sig_T_10 = mux(mux_data_rawIn_isZeroExpIn_2, mux_data_rawIn_subnormFract_2, mux_data_rawIn_fractIn_2) node _mux_data_rawIn_out_sig_T_11 = cat(_mux_data_rawIn_out_sig_T_9, _mux_data_rawIn_out_sig_T_10) connect mux_data_rawIn_2.sig, _mux_data_rawIn_out_sig_T_11 node _mux_data_T_25 = bits(mux_data_rawIn_2.sExp, 5, 3) node _mux_data_T_26 = mux(mux_data_rawIn_2.isZero, UInt<3>(0h0), _mux_data_T_25) node _mux_data_T_27 = mux(mux_data_rawIn_2.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _mux_data_T_28 = or(_mux_data_T_26, _mux_data_T_27) node _mux_data_T_29 = cat(mux_data_rawIn_2.sign, _mux_data_T_28) node _mux_data_T_30 = bits(mux_data_rawIn_2.sExp, 2, 0) node _mux_data_T_31 = cat(_mux_data_T_29, _mux_data_T_30) node _mux_data_T_32 = bits(mux_data_rawIn_2.sig, 9, 0) node _mux_data_T_33 = cat(_mux_data_T_31, _mux_data_T_32) node _mux_data_swizzledNaN_T = bits(_mux_data_T_24, 32, 29) node _mux_data_swizzledNaN_T_1 = bits(_mux_data_T_24, 22, 16) node _mux_data_swizzledNaN_T_2 = andr(_mux_data_swizzledNaN_T_1) node _mux_data_swizzledNaN_T_3 = bits(_mux_data_T_24, 27, 24) node _mux_data_swizzledNaN_T_4 = bits(_mux_data_T_33, 15, 15) node _mux_data_swizzledNaN_T_5 = bits(_mux_data_T_24, 22, 16) node _mux_data_swizzledNaN_T_6 = bits(_mux_data_T_33, 16, 16) node _mux_data_swizzledNaN_T_7 = bits(_mux_data_T_33, 14, 0) node mux_data_swizzledNaN_lo_hi = cat(_mux_data_swizzledNaN_T_5, _mux_data_swizzledNaN_T_6) node mux_data_swizzledNaN_lo = cat(mux_data_swizzledNaN_lo_hi, _mux_data_swizzledNaN_T_7) node mux_data_swizzledNaN_hi_lo = cat(_mux_data_swizzledNaN_T_3, _mux_data_swizzledNaN_T_4) node mux_data_swizzledNaN_hi_hi = cat(_mux_data_swizzledNaN_T, _mux_data_swizzledNaN_T_2) node mux_data_swizzledNaN_hi = cat(mux_data_swizzledNaN_hi_hi, mux_data_swizzledNaN_hi_lo) node mux_data_swizzledNaN = cat(mux_data_swizzledNaN_hi, mux_data_swizzledNaN_lo) node _mux_data_T_34 = bits(_mux_data_T_24, 31, 29) node _mux_data_T_35 = andr(_mux_data_T_34) node _mux_data_T_36 = mux(_mux_data_T_35, mux_data_swizzledNaN, _mux_data_T_24) node _mux_data_swizzledNaN_T_8 = bits(_mux_data_T_15, 64, 61) node _mux_data_swizzledNaN_T_9 = bits(_mux_data_T_15, 51, 32) node _mux_data_swizzledNaN_T_10 = andr(_mux_data_swizzledNaN_T_9) node _mux_data_swizzledNaN_T_11 = bits(_mux_data_T_15, 59, 53) node _mux_data_swizzledNaN_T_12 = bits(_mux_data_T_36, 31, 31) node _mux_data_swizzledNaN_T_13 = bits(_mux_data_T_15, 51, 32) node _mux_data_swizzledNaN_T_14 = bits(_mux_data_T_36, 32, 32) node _mux_data_swizzledNaN_T_15 = bits(_mux_data_T_36, 30, 0) node mux_data_swizzledNaN_lo_hi_1 = cat(_mux_data_swizzledNaN_T_13, _mux_data_swizzledNaN_T_14) node mux_data_swizzledNaN_lo_1 = cat(mux_data_swizzledNaN_lo_hi_1, _mux_data_swizzledNaN_T_15) node mux_data_swizzledNaN_hi_lo_1 = cat(_mux_data_swizzledNaN_T_11, _mux_data_swizzledNaN_T_12) node mux_data_swizzledNaN_hi_hi_1 = cat(_mux_data_swizzledNaN_T_8, _mux_data_swizzledNaN_T_10) node mux_data_swizzledNaN_hi_1 = cat(mux_data_swizzledNaN_hi_hi_1, mux_data_swizzledNaN_hi_lo_1) node mux_data_swizzledNaN_1 = cat(mux_data_swizzledNaN_hi_1, mux_data_swizzledNaN_lo_1) node _mux_data_T_37 = bits(_mux_data_T_15, 63, 61) node _mux_data_T_38 = andr(_mux_data_T_37) node _mux_data_T_39 = mux(_mux_data_T_38, mux_data_swizzledNaN_1, _mux_data_T_15) connect mux.data, _mux_data_T_39 node _intValue_res_T = asSInt(in.bits.in1) wire intValue_res : SInt connect intValue_res, _intValue_res_T node intValue_smallInt = bits(in.bits.in1, 31, 0) node _intValue_T = bits(in.bits.typ, 1, 1) node _intValue_T_1 = eq(_intValue_T, UInt<1>(0h0)) when _intValue_T_1 : node _intValue_res_T_1 = bits(in.bits.typ, 0, 0) node _intValue_res_T_2 = cvt(intValue_smallInt) node _intValue_res_T_3 = asSInt(intValue_smallInt) node _intValue_res_T_4 = mux(_intValue_res_T_1, _intValue_res_T_2, _intValue_res_T_3) connect intValue_res, _intValue_res_T_4 node intValue = asUInt(intValue_res) when in.bits.wflags : inst i2fResults_i2f of INToRecFN_i64_e5_s11 node _i2fResults_i2f_io_signedIn_T = bits(in.bits.typ, 0, 0) node _i2fResults_i2f_io_signedIn_T_1 = not(_i2fResults_i2f_io_signedIn_T) connect i2fResults_i2f.io.signedIn, _i2fResults_i2f_io_signedIn_T_1 connect i2fResults_i2f.io.in, intValue connect i2fResults_i2f.io.roundingMode, in.bits.rm connect i2fResults_i2f.io.detectTininess, UInt<1>(0h1) inst i2fResults_i2f_1 of INToRecFN_i64_e8_s24 node _i2fResults_i2f_io_signedIn_T_2 = bits(in.bits.typ, 0, 0) node _i2fResults_i2f_io_signedIn_T_3 = not(_i2fResults_i2f_io_signedIn_T_2) connect i2fResults_i2f_1.io.signedIn, _i2fResults_i2f_io_signedIn_T_3 connect i2fResults_i2f_1.io.in, intValue connect i2fResults_i2f_1.io.roundingMode, in.bits.rm connect i2fResults_i2f_1.io.detectTininess, UInt<1>(0h1) node _i2fResults_maskedNaN_T = not(UInt<33>(0h10800000)) node i2fResults_maskedNaN = and(i2fResults_i2f_1.io.out, _i2fResults_maskedNaN_T) node _i2fResults_T = bits(i2fResults_i2f_1.io.out, 31, 29) node _i2fResults_T_1 = andr(_i2fResults_T) node i2fResults_1_1 = mux(_i2fResults_T_1, i2fResults_maskedNaN, i2fResults_i2f_1.io.out) inst i2fResults_i2f_2 of INToRecFN_i64_e11_s53 node _i2fResults_i2f_io_signedIn_T_4 = bits(in.bits.typ, 0, 0) node _i2fResults_i2f_io_signedIn_T_5 = not(_i2fResults_i2f_io_signedIn_T_4) connect i2fResults_i2f_2.io.signedIn, _i2fResults_i2f_io_signedIn_T_5 connect i2fResults_i2f_2.io.in, intValue connect i2fResults_i2f_2.io.roundingMode, in.bits.rm connect i2fResults_i2f_2.io.detectTininess, UInt<1>(0h1) node _i2fResults_maskedNaN_T_1 = not(UInt<65>(0h1010000000000000)) node i2fResults_maskedNaN_1 = and(i2fResults_i2f_2.io.out, _i2fResults_maskedNaN_T_1) node _i2fResults_T_2 = bits(i2fResults_i2f_2.io.out, 63, 61) node _i2fResults_T_3 = andr(_i2fResults_T_2) node i2fResults_2_1 = mux(_i2fResults_T_3, i2fResults_maskedNaN_1, i2fResults_i2f_2.io.out) node _dataPadded_T = shr(i2fResults_2_1, 17) node dataPadded_0 = cat(_dataPadded_T, i2fResults_i2f.io.out) node _dataPadded_T_1 = shr(i2fResults_2_1, 33) node dataPadded_1 = cat(_dataPadded_T_1, i2fResults_1_1) node _mux_data_T_40 = eq(in.bits.typeTagIn, UInt<1>(0h1)) node _mux_data_T_41 = mux(_mux_data_T_40, dataPadded_1, dataPadded_0) node _mux_data_T_42 = eq(in.bits.typeTagIn, UInt<2>(0h2)) node _mux_data_T_43 = mux(_mux_data_T_42, i2fResults_2_1, _mux_data_T_41) node _mux_data_T_44 = eq(in.bits.typeTagIn, UInt<2>(0h3)) node _mux_data_T_45 = mux(_mux_data_T_44, i2fResults_2_1, _mux_data_T_43) connect mux.data, _mux_data_T_45 node _mux_exc_T = eq(in.bits.typeTagIn, UInt<1>(0h1)) node _mux_exc_T_1 = mux(_mux_exc_T, i2fResults_i2f_1.io.exceptionFlags, i2fResults_i2f.io.exceptionFlags) node _mux_exc_T_2 = eq(in.bits.typeTagIn, UInt<2>(0h2)) node _mux_exc_T_3 = mux(_mux_exc_T_2, i2fResults_i2f_2.io.exceptionFlags, _mux_exc_T_1) node _mux_exc_T_4 = eq(in.bits.typeTagIn, UInt<2>(0h3)) node _mux_exc_T_5 = mux(_mux_exc_T_4, i2fResults_i2f_2.io.exceptionFlags, _mux_exc_T_3) connect mux.exc, _mux_exc_T_5 regreset io_out_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect io_out_pipe_v, in.valid reg io_out_pipe_b : { data : UInt<65>, exc : UInt<5>}, clock when in.valid : connect io_out_pipe_b, mux wire io_out_pipe_out : { valid : UInt<1>, bits : { data : UInt<65>, exc : UInt<5>}} connect io_out_pipe_out.valid, io_out_pipe_v connect io_out_pipe_out.bits, io_out_pipe_b connect io.out, io_out_pipe_out	module IntToFP( // @[FPU.scala:528:7] input clock, // @[FPU.scala:528:7] input reset, // @[FPU.scala:528:7] input io_in_valid, // @[FPU.scala:529:14] input io_in_bits_ldst, // @[FPU.scala:529:14] input io_in_bits_wen, // @[FPU.scala:529:14] input io_in_bits_ren1, // @[FPU.scala:529:14] input io_in_bits_ren2, // @[FPU.scala:529:14] input io_in_bits_ren3, // @[FPU.scala:529:14] input io_in_bits_swap12, // @[FPU.scala:529:14] input io_in_bits_swap23, // @[FPU.scala:529:14] input [1:0] io_in_bits_typeTagIn, // @[FPU.scala:529:14] input [1:0] io_in_bits_typeTagOut, // @[FPU.scala:529:14] input io_in_bits_fromint, // @[FPU.scala:529:14] input io_in_bits_toint, // @[FPU.scala:529:14] input io_in_bits_fastpipe, // @[FPU.scala:529:14] input io_in_bits_fma, // @[FPU.scala:529:14] input io_in_bits_div, // @[FPU.scala:529:14] input io_in_bits_sqrt, // @[FPU.scala:529:14] input io_in_bits_wflags, // @[FPU.scala:529:14] input io_in_bits_vec, // @[FPU.scala:529:14] input [2:0] io_in_bits_rm, // @[FPU.scala:529:14] input [1:0] io_in_bits_typ, // @[FPU.scala:529:14] input [63:0] io_in_bits_in1, // @[FPU.scala:529:14] output [64:0] io_out_bits_data, // @[FPU.scala:529:14] output [4:0] io_out_bits_exc // @[FPU.scala:529:14] ); wire mux_data_rawIn_2_isNaN; // @[rawFloatFromFN.scala:63:19] wire mux_data_rawIn_1_isNaN; // @[rawFloatFromFN.scala:63:19] wire mux_data_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19] wire [64:0] _i2fResults_i2f_2_io_out; // @[FPU.scala:556:23] wire [4:0] _i2fResults_i2f_2_io_exceptionFlags; // @[FPU.scala:556:23] wire [32:0] _i2fResults_i2f_1_io_out; // @[FPU.scala:556:23] wire [4:0] _i2fResults_i2f_1_io_exceptionFlags; // @[FPU.scala:556:23] wire [16:0] _i2fResults_i2f_io_out; // @[FPU.scala:556:23] wire [4:0] _i2fResults_i2f_io_exceptionFlags; // @[FPU.scala:556:23] wire io_in_valid_0 = io_in_valid; // @[FPU.scala:528:7] wire io_in_bits_ldst_0 = io_in_bits_ldst; // @[FPU.scala:528:7] wire io_in_bits_wen_0 = io_in_bits_wen; // @[FPU.scala:528:7] wire io_in_bits_ren1_0 = io_in_bits_ren1; // @[FPU.scala:528:7] wire io_in_bits_ren2_0 = io_in_bits_ren2; // @[FPU.scala:528:7] wire io_in_bits_ren3_0 = io_in_bits_ren3; // @[FPU.scala:528:7] wire io_in_bits_swap12_0 = io_in_bits_swap12; // @[FPU.scala:528:7] wire io_in_bits_swap23_0 = io_in_bits_swap23; // @[FPU.scala:528:7] wire [1:0] io_in_bits_typeTagIn_0 = io_in_bits_typeTagIn; // @[FPU.scala:528:7] wire [1:0] io_in_bits_typeTagOut_0 = io_in_bits_typeTagOut; // @[FPU.scala:528:7] wire io_in_bits_fromint_0 = io_in_bits_fromint; // @[FPU.scala:528:7] wire io_in_bits_toint_0 = io_in_bits_toint; // @[FPU.scala:528:7] wire io_in_bits_fastpipe_0 = io_in_bits_fastpipe; // @[FPU.scala:528:7] wire io_in_bits_fma_0 = io_in_bits_fma; // @[FPU.scala:528:7] wire io_in_bits_div_0 = io_in_bits_div; // @[FPU.scala:528:7] wire io_in_bits_sqrt_0 = io_in_bits_sqrt; // @[FPU.scala:528:7] wire io_in_bits_wflags_0 = io_in_bits_wflags; // @[FPU.scala:528:7] wire io_in_bits_vec_0 = io_in_bits_vec; // @[FPU.scala:528:7] wire [2:0] io_in_bits_rm_0 = io_in_bits_rm; // @[FPU.scala:528:7] wire [1:0] io_in_bits_typ_0 = io_in_bits_typ; // @[FPU.scala:528:7] wire [63:0] io_in_bits_in1_0 = io_in_bits_in1; // @[FPU.scala:528:7] wire [32:0] _i2fResults_maskedNaN_T = 33'h1EF7FFFFF; // @[FPU.scala:413:27] wire [64:0] _i2fResults_maskedNaN_T_1 = 65'h1EFEFFFFFFFFFFFFF; // @[FPU.scala:413:27] wire io_out_pipe_out_valid; // @[Valid.scala:135:21] wire [64:0] io_out_pipe_out_bits_data; // @[Valid.scala:135:21] wire [4:0] io_out_pipe_out_bits_exc; // @[Valid.scala:135:21] wire [64:0] io_out_bits_data_0; // @[FPU.scala:528:7] wire [4:0] io_out_bits_exc_0; // @[FPU.scala:528:7] wire io_out_valid; // @[FPU.scala:528:7] reg in_pipe_v; // @[Valid.scala:141:24] wire in_valid = in_pipe_v; // @[Valid.scala:135:21, :141:24] reg in_pipe_b_ldst; // @[Valid.scala:142:26] wire in_bits_ldst = in_pipe_b_ldst; // @[Valid.scala:135:21, :142:26] reg in_pipe_b_wen; // @[Valid.scala:142:26] wire in_bits_wen = in_pipe_b_wen; // @[Valid.scala:135:21, :142:26] reg in_pipe_b_ren1; // @[Valid.scala:142:26] wire in_bits_ren1 = in_pipe_b_ren1; // @[Valid.scala:135:21, :142:26] reg in_pipe_b_ren2; // @[Valid.scala:142:26] wire in_bits_ren2 = in_pipe_b_ren2; // @[Valid.scala:135:21, :142:26] reg in_pipe_b_ren3; // @[Valid.scala:142:26] wire in_bits_ren3 = in_pipe_b_ren3; // @[Valid.scala:135:21, :142:26] reg in_pipe_b_swap12; // @[Valid.scala:142:26] wire in_bits_swap12 = in_pipe_b_swap12; // @[Valid.scala:135:21, :142:26] reg in_pipe_b_swap23; // @[Valid.scala:142:26] wire in_bits_swap23 = in_pipe_b_swap23; // @[Valid.scala:135:21, :142:26] reg [1:0] in_pipe_b_typeTagIn; // @[Valid.scala:142:26] wire [1:0] in_bits_typeTagIn = in_pipe_b_typeTagIn; // @[Valid.scala:135:21, :142:26] reg [1:0] in_pipe_b_typeTagOut; // @[Valid.scala:142:26] wire [1:0] in_bits_typeTagOut = in_pipe_b_typeTagOut; // @[Valid.scala:135:21, :142:26] reg in_pipe_b_fromint; // @[Valid.scala:142:26] wire in_bits_fromint = in_pipe_b_fromint; // @[Valid.scala:135:21, :142:26] reg in_pipe_b_toint; // @[Valid.scala:142:26] wire in_bits_toint = in_pipe_b_toint; // @[Valid.scala:135:21, :142:26] reg in_pipe_b_fastpipe; // @[Valid.scala:142:26] wire in_bits_fastpipe = in_pipe_b_fastpipe; // @[Valid.scala:135:21, :142:26] reg in_pipe_b_fma; // @[Valid.scala:142:26] wire in_bits_fma = in_pipe_b_fma; // @[Valid.scala:135:21, :142:26] reg in_pipe_b_div; // @[Valid.scala:142:26] wire in_bits_div = in_pipe_b_div; // @[Valid.scala:135:21, :142:26] reg in_pipe_b_sqrt; // @[Valid.scala:142:26] wire in_bits_sqrt = in_pipe_b_sqrt; // @[Valid.scala:135:21, :142:26] reg in_pipe_b_wflags; // @[Valid.scala:142:26] wire in_bits_wflags = in_pipe_b_wflags; // @[Valid.scala:135:21, :142:26] reg in_pipe_b_vec; // @[Valid.scala:142:26] wire in_bits_vec = in_pipe_b_vec; // @[Valid.scala:135:21, :142:26] reg [2:0] in_pipe_b_rm; // @[Valid.scala:142:26] wire [2:0] in_bits_rm = in_pipe_b_rm; // @[Valid.scala:135:21, :142:26] reg [1:0] in_pipe_b_typ; // @[Valid.scala:142:26] wire [1:0] in_bits_typ = in_pipe_b_typ; // @[Valid.scala:135:21, :142:26] reg [63:0] in_pipe_b_in1; // @[Valid.scala:142:26] wire [63:0] in_bits_in1 = in_pipe_b_in1; // @[Valid.scala:135:21, :142:26] wire [63:0] _intValue_res_T = in_bits_in1; // @[Valid.scala:135:21] wire [64:0] mux_data; // @[FPU.scala:537:17] wire [4:0] mux_exc; // @[FPU.scala:537:17] wire _GEN = in_bits_typeTagIn == 2'h1; // @[Valid.scala:135:21] wire _mux_data_T; // @[package.scala:39:86] assign _mux_data_T = _GEN; // @[package.scala:39:86] wire _mux_data_T_40; // @[package.scala:39:86] assign _mux_data_T_40 = _GEN; // @[package.scala:39:86] wire _mux_exc_T; // @[package.scala:39:86] assign _mux_exc_T = _GEN; // @[package.scala:39:86] wire [63:0] _mux_data_T_1 = _mux_data_T ? 64'hFFFFFFFF00000000 : 64'hFFFFFFFFFFFF0000; // @[package.scala:39:{76,86}] wire _GEN_0 = in_bits_typeTagIn == 2'h2; // @[Valid.scala:135:21] wire _mux_data_T_2; // @[package.scala:39:86] assign _mux_data_T_2 = _GEN_0; // @[package.scala:39:86] wire _mux_data_T_42; // @[package.scala:39:86] assign _mux_data_T_42 = _GEN_0; // @[package.scala:39:86] wire _mux_exc_T_2; // @[package.scala:39:86] assign _mux_exc_T_2 = _GEN_0; // @[package.scala:39:86] wire [63:0] _mux_data_T_3 = _mux_data_T_2 ? 64'h0 : _mux_data_T_1; // @[package.scala:39:{76,86}] wire _mux_data_T_4 = &in_bits_typeTagIn; // @[Valid.scala:135:21] wire [63:0] _mux_data_T_5 = _mux_data_T_4 ? 64'h0 : _mux_data_T_3; // @[package.scala:39:{76,86}] wire [63:0] _mux_data_T_6 = _mux_data_T_5 \| in_bits_in1; // @[Valid.scala:135:21] wire mux_data_rawIn_sign = _mux_data_T_6[63]; // @[FPU.scala:431:23] wire mux_data_rawIn_sign_0 = mux_data_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19] wire [10:0] mux_data_rawIn_expIn = _mux_data_T_6[62:52]; // @[FPU.scala:431:23] wire [51:0] mux_data_rawIn_fractIn = _mux_data_T_6[51:0]; // @[FPU.scala:431:23] wire mux_data_rawIn_isZeroExpIn = mux_data_rawIn_expIn == 11'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire mux_data_rawIn_isZeroFractIn = mux_data_rawIn_fractIn == 52'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _mux_data_rawIn_normDist_T = mux_data_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21] wire _mux_data_rawIn_normDist_T_1 = mux_data_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21] wire _mux_data_rawIn_normDist_T_2 = mux_data_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21] wire _mux_data_rawIn_normDist_T_3 = mux_data_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21] wire _mux_data_rawIn_normDist_T_4 = mux_data_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21] wire _mux_data_rawIn_normDist_T_5 = mux_data_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21] wire _mux_data_rawIn_normDist_T_6 = mux_data_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21] wire _mux_data_rawIn_normDist_T_7 = mux_data_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21] wire _mux_data_rawIn_normDist_T_8 = mux_data_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21] wire _mux_data_rawIn_normDist_T_9 = mux_data_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21] wire _mux_data_rawIn_normDist_T_10 = mux_data_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21] wire _mux_data_rawIn_normDist_T_11 = mux_data_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21] wire _mux_data_rawIn_normDist_T_12 = mux_data_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21] wire _mux_data_rawIn_normDist_T_13 = mux_data_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21] wire _mux_data_rawIn_normDist_T_14 = mux_data_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21] wire _mux_data_rawIn_normDist_T_15 = mux_data_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21] wire _mux_data_rawIn_normDist_T_16 = mux_data_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21] wire _mux_data_rawIn_normDist_T_17 = mux_data_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21] wire _mux_data_rawIn_normDist_T_18 = mux_data_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21] wire _mux_data_rawIn_normDist_T_19 = mux_data_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21] wire _mux_data_rawIn_normDist_T_20 = mux_data_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21] wire _mux_data_rawIn_normDist_T_21 = mux_data_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21] wire _mux_data_rawIn_normDist_T_22 = mux_data_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21] wire _mux_data_rawIn_normDist_T_23 = mux_data_rawIn_fractIn[23]; // @[rawFloatFromFN.scala:46:21] wire _mux_data_rawIn_normDist_T_24 = mux_data_rawIn_fractIn[24]; // @[rawFloatFromFN.scala:46:21] wire _mux_data_rawIn_normDist_T_25 = mux_data_rawIn_fractIn[25]; // @[rawFloatFromFN.scala:46:21] wire _mux_data_rawIn_normDist_T_26 = mux_data_rawIn_fractIn[26]; // @[rawFloatFromFN.scala:46:21] wire _mux_data_rawIn_normDist_T_27 = mux_data_rawIn_fractIn[27]; // @[rawFloatFromFN.scala:46:21] wire _mux_data_rawIn_normDist_T_28 = mux_data_rawIn_fractIn[28]; // @[rawFloatFromFN.scala:46:21] wire _mux_data_rawIn_normDist_T_29 = mux_data_rawIn_fractIn[29]; // @[rawFloatFromFN.scala:46:21] wire _mux_data_rawIn_normDist_T_30 = mux_data_rawIn_fractIn[30]; // @[rawFloatFromFN.scala:46:21] wire _mux_data_rawIn_normDist_T_31 = mux_data_rawIn_fractIn[31]; // @[rawFloatFromFN.scala:46:21] wire _mux_data_rawIn_normDist_T_32 = mux_data_rawIn_fractIn[32]; // @[rawFloatFromFN.scala:46:21] wire _mux_data_rawIn_normDist_T_33 = mux_data_rawIn_fractIn[33]; // @[rawFloatFromFN.scala:46:21] wire _mux_data_rawIn_normDist_T_34 = mux_data_rawIn_fractIn[34]; // @[rawFloatFromFN.scala:46:21] wire _mux_data_rawIn_normDist_T_35 = mux_data_rawIn_fractIn[35]; // @[rawFloatFromFN.scala:46:21] wire _mux_data_rawIn_normDist_T_36 = mux_data_rawIn_fractIn[36]; // @[rawFloatFromFN.scala:46:21] wire _mux_data_rawIn_normDist_T_37 = mux_data_rawIn_fractIn[37]; // @[rawFloatFromFN.scala:46:21] wire _mux_data_rawIn_normDist_T_38 = mux_data_rawIn_fractIn[38]; // @[rawFloatFromFN.scala:46:21] wire _mux_data_rawIn_normDist_T_39 = mux_data_rawIn_fractIn[39]; // @[rawFloatFromFN.scala:46:21] wire _mux_data_rawIn_normDist_T_40 = mux_data_rawIn_fractIn[40]; // @[rawFloatFromFN.scala:46:21] wire _mux_data_rawIn_normDist_T_41 = mux_data_rawIn_fractIn[41]; // @[rawFloatFromFN.scala:46:21] wire _mux_data_rawIn_normDist_T_42 = mux_data_rawIn_fractIn[42]; // @[rawFloatFromFN.scala:46:21] wire _mux_data_rawIn_normDist_T_43 = mux_data_rawIn_fractIn[43]; // @[rawFloatFromFN.scala:46:21] wire _mux_data_rawIn_normDist_T_44 = mux_data_rawIn_fractIn[44]; // @[rawFloatFromFN.scala:46:21] wire _mux_data_rawIn_normDist_T_45 = mux_data_rawIn_fractIn[45]; // @[rawFloatFromFN.scala:46:21] wire _mux_data_rawIn_normDist_T_46 = mux_data_rawIn_fractIn[46]; // @[rawFloatFromFN.scala:46:21] wire _mux_data_rawIn_normDist_T_47 = mux_data_rawIn_fractIn[47]; // @[rawFloatFromFN.scala:46:21] wire _mux_data_rawIn_normDist_T_48 = mux_data_rawIn_fractIn[48]; // @[rawFloatFromFN.scala:46:21] wire _mux_data_rawIn_normDist_T_49 = mux_data_rawIn_fractIn[49]; // @[rawFloatFromFN.scala:46:21] wire _mux_data_rawIn_normDist_T_50 = mux_data_rawIn_fractIn[50]; // @[rawFloatFromFN.scala:46:21] wire _mux_data_rawIn_normDist_T_51 = mux_data_rawIn_fractIn[51]; // @[rawFloatFromFN.scala:46:21] wire [5:0] _mux_data_rawIn_normDist_T_52 = {5'h19, ~_mux_data_rawIn_normDist_T_1}; // @[Mux.scala:50:70] wire [5:0] _mux_data_rawIn_normDist_T_53 = _mux_data_rawIn_normDist_T_2 ? 6'h31 : _mux_data_rawIn_normDist_T_52; // @[Mux.scala:50:70] wire [5:0] _mux_data_rawIn_normDist_T_54 = _mux_data_rawIn_normDist_T_3 ? 6'h30 : _mux_data_rawIn_normDist_T_53; // @[Mux.scala:50:70] wire [5:0] _mux_data_rawIn_normDist_T_55 = _mux_data_rawIn_normDist_T_4 ? 6'h2F : _mux_data_rawIn_normDist_T_54; // @[Mux.scala:50:70] wire [5:0] _mux_data_rawIn_normDist_T_56 = _mux_data_rawIn_normDist_T_5 ? 6'h2E : _mux_data_rawIn_normDist_T_55; // @[Mux.scala:50:70] wire [5:0] _mux_data_rawIn_normDist_T_57 = _mux_data_rawIn_normDist_T_6 ? 6'h2D : _mux_data_rawIn_normDist_T_56; // @[Mux.scala:50:70] wire [5:0] _mux_data_rawIn_normDist_T_58 = _mux_data_rawIn_normDist_T_7 ? 6'h2C : _mux_data_rawIn_normDist_T_57; // @[Mux.scala:50:70] wire [5:0] _mux_data_rawIn_normDist_T_59 = _mux_data_rawIn_normDist_T_8 ? 6'h2B : _mux_data_rawIn_normDist_T_58; // @[Mux.scala:50:70] wire [5:0] _mux_data_rawIn_normDist_T_60 = _mux_data_rawIn_normDist_T_9 ? 6'h2A : _mux_data_rawIn_normDist_T_59; // @[Mux.scala:50:70] wire [5:0] _mux_data_rawIn_normDist_T_61 = _mux_data_rawIn_normDist_T_10 ? 6'h29 : _mux_data_rawIn_normDist_T_60; // @[Mux.scala:50:70] wire [5:0] _mux_data_rawIn_normDist_T_62 = _mux_data_rawIn_normDist_T_11 ? 6'h28 : _mux_data_rawIn_normDist_T_61; // @[Mux.scala:50:70] wire [5:0] _mux_data_rawIn_normDist_T_63 = _mux_data_rawIn_normDist_T_12 ? 6'h27 : _mux_data_rawIn_normDist_T_62; // @[Mux.scala:50:70] wire [5:0] _mux_data_rawIn_normDist_T_64 = _mux_data_rawIn_normDist_T_13 ? 6'h26 : _mux_data_rawIn_normDist_T_63; // @[Mux.scala:50:70] wire [5:0] _mux_data_rawIn_normDist_T_65 = _mux_data_rawIn_normDist_T_14 ? 6'h25 : _mux_data_rawIn_normDist_T_64; // @[Mux.scala:50:70] wire [5:0] _mux_data_rawIn_normDist_T_66 = _mux_data_rawIn_normDist_T_15 ? 6'h24 : _mux_data_rawIn_normDist_T_65; // @[Mux.scala:50:70] wire [5:0] _mux_data_rawIn_normDist_T_67 = _mux_data_rawIn_normDist_T_16 ? 6'h23 : _mux_data_rawIn_normDist_T_66; // @[Mux.scala:50:70] wire [5:0] _mux_data_rawIn_normDist_T_68 = _mux_data_rawIn_normDist_T_17 ? 6'h22 : _mux_data_rawIn_normDist_T_67; // @[Mux.scala:50:70] wire [5:0] _mux_data_rawIn_normDist_T_69 = _mux_data_rawIn_normDist_T_18 ? 6'h21 : _mux_data_rawIn_normDist_T_68; // @[Mux.scala:50:70] wire [5:0] _mux_data_rawIn_normDist_T_70 = _mux_data_rawIn_normDist_T_19 ? 6'h20 : _mux_data_rawIn_normDist_T_69; // @[Mux.scala:50:70] wire [5:0] _mux_data_rawIn_normDist_T_71 = _mux_data_rawIn_normDist_T_20 ? 6'h1F : _mux_data_rawIn_normDist_T_70; // @[Mux.scala:50:70] wire [5:0] _mux_data_rawIn_normDist_T_72 = _mux_data_rawIn_normDist_T_21 ? 6'h1E : _mux_data_rawIn_normDist_T_71; // @[Mux.scala:50:70] wire [5:0] _mux_data_rawIn_normDist_T_73 = _mux_data_rawIn_normDist_T_22 ? 6'h1D : _mux_data_rawIn_normDist_T_72; // @[Mux.scala:50:70] wire [5:0] _mux_data_rawIn_normDist_T_74 = _mux_data_rawIn_normDist_T_23 ? 6'h1C : _mux_data_rawIn_normDist_T_73; // @[Mux.scala:50:70] wire [5:0] _mux_data_rawIn_normDist_T_75 = _mux_data_rawIn_normDist_T_24 ? 6'h1B : _mux_data_rawIn_normDist_T_74; // @[Mux.scala:50:70] wire [5:0] _mux_data_rawIn_normDist_T_76 = _mux_data_rawIn_normDist_T_25 ? 6'h1A : _mux_data_rawIn_normDist_T_75; // @[Mux.scala:50:70] wire [5:0] _mux_data_rawIn_normDist_T_77 = _mux_data_rawIn_normDist_T_26 ? 6'h19 : _mux_data_rawIn_normDist_T_76; // @[Mux.scala:50:70] wire [5:0] _mux_data_rawIn_normDist_T_78 = _mux_data_rawIn_normDist_T_27 ? 6'h18 : _mux_data_rawIn_normDist_T_77; // @[Mux.scala:50:70] wire [5:0] _mux_data_rawIn_normDist_T_79 = _mux_data_rawIn_normDist_T_28 ? 6'h17 : _mux_data_rawIn_normDist_T_78; // @[Mux.scala:50:70] wire [5:0] _mux_data_rawIn_normDist_T_80 = _mux_data_rawIn_normDist_T_29 ? 6'h16 : _mux_data_rawIn_normDist_T_79; // @[Mux.scala:50:70] wire [5:0] _mux_data_rawIn_normDist_T_81 = _mux_data_rawIn_normDist_T_30 ? 6'h15 : _mux_data_rawIn_normDist_T_80; // @[Mux.scala:50:70] wire [5:0] _mux_data_rawIn_normDist_T_82 = _mux_data_rawIn_normDist_T_31 ? 6'h14 : _mux_data_rawIn_normDist_T_81; // @[Mux.scala:50:70] wire [5:0] _mux_data_rawIn_normDist_T_83 = _mux_data_rawIn_normDist_T_32 ? 6'h13 : _mux_data_rawIn_normDist_T_82; // @[Mux.scala:50:70] wire [5:0] _mux_data_rawIn_normDist_T_84 = _mux_data_rawIn_normDist_T_33 ? 6'h12 : _mux_data_rawIn_normDist_T_83; // @[Mux.scala:50:70] wire [5:0] _mux_data_rawIn_normDist_T_85 = _mux_data_rawIn_normDist_T_34 ? 6'h11 : _mux_data_rawIn_normDist_T_84; // @[Mux.scala:50:70] wire [5:0] _mux_data_rawIn_normDist_T_86 = _mux_data_rawIn_normDist_T_35 ? 6'h10 : _mux_data_rawIn_normDist_T_85; // @[Mux.scala:50:70] wire [5:0] _mux_data_rawIn_normDist_T_87 = _mux_data_rawIn_normDist_T_36 ? 6'hF : _mux_data_rawIn_normDist_T_86; // @[Mux.scala:50:70] wire [5:0] _mux_data_rawIn_normDist_T_88 = _mux_data_rawIn_normDist_T_37 ? 6'hE : _mux_data_rawIn_normDist_T_87; // @[Mux.scala:50:70] wire [5:0] _mux_data_rawIn_normDist_T_89 = _mux_data_rawIn_normDist_T_38 ? 6'hD : _mux_data_rawIn_normDist_T_88; // @[Mux.scala:50:70] wire [5:0] _mux_data_rawIn_normDist_T_90 = _mux_data_rawIn_normDist_T_39 ? 6'hC : _mux_data_rawIn_normDist_T_89; // @[Mux.scala:50:70] wire [5:0] _mux_data_rawIn_normDist_T_91 = _mux_data_rawIn_normDist_T_40 ? 6'hB : _mux_data_rawIn_normDist_T_90; // @[Mux.scala:50:70] wire [5:0] _mux_data_rawIn_normDist_T_92 = _mux_data_rawIn_normDist_T_41 ? 6'hA : _mux_data_rawIn_normDist_T_91; // @[Mux.scala:50:70] wire [5:0] _mux_data_rawIn_normDist_T_93 = _mux_data_rawIn_normDist_T_42 ? 6'h9 : _mux_data_rawIn_normDist_T_92; // @[Mux.scala:50:70] wire [5:0] _mux_data_rawIn_normDist_T_94 = _mux_data_rawIn_normDist_T_43 ? 6'h8 : _mux_data_rawIn_normDist_T_93; // @[Mux.scala:50:70] wire [5:0] _mux_data_rawIn_normDist_T_95 = _mux_data_rawIn_normDist_T_44 ? 6'h7 : _mux_data_rawIn_normDist_T_94; // @[Mux.scala:50:70] wire [5:0] _mux_data_rawIn_normDist_T_96 = _mux_data_rawIn_normDist_T_45 ? 6'h6 : _mux_data_rawIn_normDist_T_95; // @[Mux.scala:50:70] wire [5:0] _mux_data_rawIn_normDist_T_97 = _mux_data_rawIn_normDist_T_46 ? 6'h5 : _mux_data_rawIn_normDist_T_96; // @[Mux.scala:50:70] wire [5:0] _mux_data_rawIn_normDist_T_98 = _mux_data_rawIn_normDist_T_47 ? 6'h4 : _mux_data_rawIn_normDist_T_97; // @[Mux.scala:50:70] wire [5:0] _mux_data_rawIn_normDist_T_99 = _mux_data_rawIn_normDist_T_48 ? 6'h3 : _mux_data_rawIn_normDist_T_98; // @[Mux.scala:50:70] wire [5:0] _mux_data_rawIn_normDist_T_100 = _mux_data_rawIn_normDist_T_49 ? 6'h2 : _mux_data_rawIn_normDist_T_99; // @[Mux.scala:50:70] wire [5:0] _mux_data_rawIn_normDist_T_101 = _mux_data_rawIn_normDist_T_50 ? 6'h1 : _mux_data_rawIn_normDist_T_100; // @[Mux.scala:50:70] wire [5:0] mux_data_rawIn_normDist = _mux_data_rawIn_normDist_T_51 ? 6'h0 : _mux_data_rawIn_normDist_T_101; // @[Mux.scala:50:70] wire [114:0] _mux_data_rawIn_subnormFract_T = {63'h0, mux_data_rawIn_fractIn} << mux_data_rawIn_normDist; // @[Mux.scala:50:70] wire [50:0] _mux_data_rawIn_subnormFract_T_1 = _mux_data_rawIn_subnormFract_T[50:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [51:0] mux_data_rawIn_subnormFract = {_mux_data_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [11:0] _mux_data_rawIn_adjustedExp_T = {6'h3F, ~mux_data_rawIn_normDist}; // @[Mux.scala:50:70] wire [11:0] _mux_data_rawIn_adjustedExp_T_1 = mux_data_rawIn_isZeroExpIn ? _mux_data_rawIn_adjustedExp_T : {1'h0, mux_data_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _mux_data_rawIn_adjustedExp_T_2 = mux_data_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[package.scala:39:86] wire [10:0] _mux_data_rawIn_adjustedExp_T_3 = {9'h100, _mux_data_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}] wire [12:0] _mux_data_rawIn_adjustedExp_T_4 = {1'h0, _mux_data_rawIn_adjustedExp_T_1} + {2'h0, _mux_data_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [11:0] mux_data_rawIn_adjustedExp = _mux_data_rawIn_adjustedExp_T_4[11:0]; // @[rawFloatFromFN.scala:57:9] wire [11:0] _mux_data_rawIn_out_sExp_T = mux_data_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28] wire mux_data_rawIn_isZero = mux_data_rawIn_isZeroExpIn & mux_data_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire mux_data_rawIn_isZero_0 = mux_data_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _mux_data_rawIn_isSpecial_T = mux_data_rawIn_adjustedExp[11:10]; // @[rawFloatFromFN.scala:57:9, :61:32] wire mux_data_rawIn_isSpecial = &_mux_data_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}] wire _mux_data_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28] wire _mux_data_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28] wire _mux_data_T_9 = mux_data_rawIn_isNaN; // @[recFNFromFN.scala:49:20] wire [12:0] _mux_data_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42] wire [53:0] _mux_data_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27] wire mux_data_rawIn_isInf; // @[rawFloatFromFN.scala:63:19] wire [12:0] mux_data_rawIn_sExp; // @[rawFloatFromFN.scala:63:19] wire [53:0] mux_data_rawIn_sig; // @[rawFloatFromFN.scala:63:19] wire _mux_data_rawIn_out_isNaN_T = ~mux_data_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31] assign _mux_data_rawIn_out_isNaN_T_1 = mux_data_rawIn_isSpecial & _mux_data_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign mux_data_rawIn_isNaN = _mux_data_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28] assign _mux_data_rawIn_out_isInf_T = mux_data_rawIn_isSpecial & mux_data_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign mux_data_rawIn_isInf = _mux_data_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28] assign _mux_data_rawIn_out_sExp_T_1 = {1'h0, _mux_data_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}] assign mux_data_rawIn_sExp = _mux_data_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42] wire _mux_data_rawIn_out_sig_T = ~mux_data_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _mux_data_rawIn_out_sig_T_1 = {1'h0, _mux_data_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}] wire [51:0] _mux_data_rawIn_out_sig_T_2 = mux_data_rawIn_isZeroExpIn ? mux_data_rawIn_subnormFract : mux_data_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _mux_data_rawIn_out_sig_T_3 = {_mux_data_rawIn_out_sig_T_1, _mux_data_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign mux_data_rawIn_sig = _mux_data_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _mux_data_T_7 = mux_data_rawIn_sExp[11:9]; // @[recFNFromFN.scala:48:50] wire [2:0] _mux_data_T_8 = mux_data_rawIn_isZero_0 ? 3'h0 : _mux_data_T_7; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _mux_data_T_10 = {_mux_data_T_8[2:1], _mux_data_T_8[0] \| _mux_data_T_9}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _mux_data_T_11 = {mux_data_rawIn_sign_0, _mux_data_T_10}; // @[recFNFromFN.scala:47:20, :48:76] wire [8:0] _mux_data_T_12 = mux_data_rawIn_sExp[8:0]; // @[recFNFromFN.scala:50:23] wire [12:0] _mux_data_T_13 = {_mux_data_T_11, _mux_data_T_12}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [51:0] _mux_data_T_14 = mux_data_rawIn_sig[51:0]; // @[recFNFromFN.scala:51:22] wire [64:0] _mux_data_T_15 = {_mux_data_T_13, _mux_data_T_14}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire mux_data_rawIn_sign_1 = _mux_data_T_6[31]; // @[FPU.scala:431:23] wire mux_data_rawIn_1_sign = mux_data_rawIn_sign_1; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] mux_data_rawIn_expIn_1 = _mux_data_T_6[30:23]; // @[FPU.scala:431:23] wire [22:0] mux_data_rawIn_fractIn_1 = _mux_data_T_6[22:0]; // @[FPU.scala:431:23] wire mux_data_rawIn_isZeroExpIn_1 = mux_data_rawIn_expIn_1 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire mux_data_rawIn_isZeroFractIn_1 = mux_data_rawIn_fractIn_1 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _mux_data_rawIn_normDist_T_102 = mux_data_rawIn_fractIn_1[0]; // @[rawFloatFromFN.scala:46:21] wire _mux_data_rawIn_normDist_T_103 = mux_data_rawIn_fractIn_1[1]; // @[rawFloatFromFN.scala:46:21] wire _mux_data_rawIn_normDist_T_104 = mux_data_rawIn_fractIn_1[2]; // @[rawFloatFromFN.scala:46:21] wire _mux_data_rawIn_normDist_T_105 = mux_data_rawIn_fractIn_1[3]; // @[rawFloatFromFN.scala:46:21] wire _mux_data_rawIn_normDist_T_106 = mux_data_rawIn_fractIn_1[4]; // @[rawFloatFromFN.scala:46:21] wire _mux_data_rawIn_normDist_T_107 = mux_data_rawIn_fractIn_1[5]; // @[rawFloatFromFN.scala:46:21] wire _mux_data_rawIn_normDist_T_108 = mux_data_rawIn_fractIn_1[6]; // @[rawFloatFromFN.scala:46:21] wire _mux_data_rawIn_normDist_T_109 = mux_data_rawIn_fractIn_1[7]; // @[rawFloatFromFN.scala:46:21] wire _mux_data_rawIn_normDist_T_110 = mux_data_rawIn_fractIn_1[8]; // @[rawFloatFromFN.scala:46:21] wire _mux_data_rawIn_normDist_T_111 = mux_data_rawIn_fractIn_1[9]; // @[rawFloatFromFN.scala:46:21] wire _mux_data_rawIn_normDist_T_112 = mux_data_rawIn_fractIn_1[10]; // @[rawFloatFromFN.scala:46:21] wire _mux_data_rawIn_normDist_T_113 = mux_data_rawIn_fractIn_1[11]; // @[rawFloatFromFN.scala:46:21] wire _mux_data_rawIn_normDist_T_114 = mux_data_rawIn_fractIn_1[12]; // @[rawFloatFromFN.scala:46:21] wire _mux_data_rawIn_normDist_T_115 = mux_data_rawIn_fractIn_1[13]; // @[rawFloatFromFN.scala:46:21] wire _mux_data_rawIn_normDist_T_116 = mux_data_rawIn_fractIn_1[14]; // @[rawFloatFromFN.scala:46:21] wire _mux_data_rawIn_normDist_T_117 = mux_data_rawIn_fractIn_1[15]; // @[rawFloatFromFN.scala:46:21] wire _mux_data_rawIn_normDist_T_118 = mux_data_rawIn_fractIn_1[16]; // @[rawFloatFromFN.scala:46:21] wire _mux_data_rawIn_normDist_T_119 = mux_data_rawIn_fractIn_1[17]; // @[rawFloatFromFN.scala:46:21] wire _mux_data_rawIn_normDist_T_120 = mux_data_rawIn_fractIn_1[18]; // @[rawFloatFromFN.scala:46:21] wire _mux_data_rawIn_normDist_T_121 = mux_data_rawIn_fractIn_1[19]; // @[rawFloatFromFN.scala:46:21] wire _mux_data_rawIn_normDist_T_122 = mux_data_rawIn_fractIn_1[20]; // @[rawFloatFromFN.scala:46:21] wire _mux_data_rawIn_normDist_T_123 = mux_data_rawIn_fractIn_1[21]; // @[rawFloatFromFN.scala:46:21] wire _mux_data_rawIn_normDist_T_124 = mux_data_rawIn_fractIn_1[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _mux_data_rawIn_normDist_T_125 = _mux_data_rawIn_normDist_T_103 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _mux_data_rawIn_normDist_T_126 = _mux_data_rawIn_normDist_T_104 ? 5'h14 : _mux_data_rawIn_normDist_T_125; // @[Mux.scala:50:70] wire [4:0] _mux_data_rawIn_normDist_T_127 = _mux_data_rawIn_normDist_T_105 ? 5'h13 : _mux_data_rawIn_normDist_T_126; // @[Mux.scala:50:70] wire [4:0] _mux_data_rawIn_normDist_T_128 = _mux_data_rawIn_normDist_T_106 ? 5'h12 : _mux_data_rawIn_normDist_T_127; // @[Mux.scala:50:70] wire [4:0] _mux_data_rawIn_normDist_T_129 = _mux_data_rawIn_normDist_T_107 ? 5'h11 : _mux_data_rawIn_normDist_T_128; // @[Mux.scala:50:70] wire [4:0] _mux_data_rawIn_normDist_T_130 = _mux_data_rawIn_normDist_T_108 ? 5'h10 : _mux_data_rawIn_normDist_T_129; // @[Mux.scala:50:70] wire [4:0] _mux_data_rawIn_normDist_T_131 = _mux_data_rawIn_normDist_T_109 ? 5'hF : _mux_data_rawIn_normDist_T_130; // @[Mux.scala:50:70] wire [4:0] _mux_data_rawIn_normDist_T_132 = _mux_data_rawIn_normDist_T_110 ? 5'hE : _mux_data_rawIn_normDist_T_131; // @[Mux.scala:50:70] wire [4:0] _mux_data_rawIn_normDist_T_133 = _mux_data_rawIn_normDist_T_111 ? 5'hD : _mux_data_rawIn_normDist_T_132; // @[Mux.scala:50:70] wire [4:0] _mux_data_rawIn_normDist_T_134 = _mux_data_rawIn_normDist_T_112 ? 5'hC : _mux_data_rawIn_normDist_T_133; // @[Mux.scala:50:70] wire [4:0] _mux_data_rawIn_normDist_T_135 = _mux_data_rawIn_normDist_T_113 ? 5'hB : _mux_data_rawIn_normDist_T_134; // @[Mux.scala:50:70] wire [4:0] _mux_data_rawIn_normDist_T_136 = _mux_data_rawIn_normDist_T_114 ? 5'hA : _mux_data_rawIn_normDist_T_135; // @[Mux.scala:50:70] wire [4:0] _mux_data_rawIn_normDist_T_137 = _mux_data_rawIn_normDist_T_115 ? 5'h9 : _mux_data_rawIn_normDist_T_136; // @[Mux.scala:50:70] wire [4:0] _mux_data_rawIn_normDist_T_138 = _mux_data_rawIn_normDist_T_116 ? 5'h8 : _mux_data_rawIn_normDist_T_137; // @[Mux.scala:50:70] wire [4:0] _mux_data_rawIn_normDist_T_139 = _mux_data_rawIn_normDist_T_117 ? 5'h7 : _mux_data_rawIn_normDist_T_138; // @[Mux.scala:50:70] wire [4:0] _mux_data_rawIn_normDist_T_140 = _mux_data_rawIn_normDist_T_118 ? 5'h6 : _mux_data_rawIn_normDist_T_139; // @[Mux.scala:50:70] wire [4:0] _mux_data_rawIn_normDist_T_141 = _mux_data_rawIn_normDist_T_119 ? 5'h5 : _mux_data_rawIn_normDist_T_140; // @[Mux.scala:50:70] wire [4:0] _mux_data_rawIn_normDist_T_142 = _mux_data_rawIn_normDist_T_120 ? 5'h4 : _mux_data_rawIn_normDist_T_141; // @[Mux.scala:50:70] wire [4:0] _mux_data_rawIn_normDist_T_143 = _mux_data_rawIn_normDist_T_121 ? 5'h3 : _mux_data_rawIn_normDist_T_142; // @[Mux.scala:50:70] wire [4:0] _mux_data_rawIn_normDist_T_144 = _mux_data_rawIn_normDist_T_122 ? 5'h2 : _mux_data_rawIn_normDist_T_143; // @[Mux.scala:50:70] wire [4:0] _mux_data_rawIn_normDist_T_145 = _mux_data_rawIn_normDist_T_123 ? 5'h1 : _mux_data_rawIn_normDist_T_144; // @[Mux.scala:50:70] wire [4:0] mux_data_rawIn_normDist_1 = _mux_data_rawIn_normDist_T_124 ? 5'h0 : _mux_data_rawIn_normDist_T_145; // @[Mux.scala:50:70] wire [53:0] _mux_data_rawIn_subnormFract_T_2 = {31'h0, mux_data_rawIn_fractIn_1} << mux_data_rawIn_normDist_1; // @[Mux.scala:50:70] wire [21:0] _mux_data_rawIn_subnormFract_T_3 = _mux_data_rawIn_subnormFract_T_2[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] mux_data_rawIn_subnormFract_1 = {_mux_data_rawIn_subnormFract_T_3, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _mux_data_rawIn_adjustedExp_T_5 = {4'hF, ~mux_data_rawIn_normDist_1}; // @[Mux.scala:50:70] wire [8:0] _mux_data_rawIn_adjustedExp_T_6 = mux_data_rawIn_isZeroExpIn_1 ? _mux_data_rawIn_adjustedExp_T_5 : {1'h0, mux_data_rawIn_expIn_1}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _mux_data_rawIn_adjustedExp_T_7 = mux_data_rawIn_isZeroExpIn_1 ? 2'h2 : 2'h1; // @[package.scala:39:86] wire [7:0] _mux_data_rawIn_adjustedExp_T_8 = {6'h20, _mux_data_rawIn_adjustedExp_T_7}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _mux_data_rawIn_adjustedExp_T_9 = {1'h0, _mux_data_rawIn_adjustedExp_T_6} + {2'h0, _mux_data_rawIn_adjustedExp_T_8}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [8:0] mux_data_rawIn_adjustedExp_1 = _mux_data_rawIn_adjustedExp_T_9[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _mux_data_rawIn_out_sExp_T_2 = mux_data_rawIn_adjustedExp_1; // @[rawFloatFromFN.scala:57:9, :68:28] wire mux_data_rawIn_isZero_1 = mux_data_rawIn_isZeroExpIn_1 & mux_data_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire mux_data_rawIn_1_isZero = mux_data_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _mux_data_rawIn_isSpecial_T_1 = mux_data_rawIn_adjustedExp_1[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire mux_data_rawIn_isSpecial_1 = &_mux_data_rawIn_isSpecial_T_1; // @[rawFloatFromFN.scala:61:{32,57}] wire _mux_data_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:64:28] wire _mux_data_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:65:28] wire _mux_data_T_18 = mux_data_rawIn_1_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _mux_data_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:68:42] wire [24:0] _mux_data_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:70:27] wire mux_data_rawIn_1_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] mux_data_rawIn_1_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] mux_data_rawIn_1_sig; // @[rawFloatFromFN.scala:63:19] wire _mux_data_rawIn_out_isNaN_T_2 = ~mux_data_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :64:31] assign _mux_data_rawIn_out_isNaN_T_3 = mux_data_rawIn_isSpecial_1 & _mux_data_rawIn_out_isNaN_T_2; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign mux_data_rawIn_1_isNaN = _mux_data_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:63:19, :64:28] assign _mux_data_rawIn_out_isInf_T_1 = mux_data_rawIn_isSpecial_1 & mux_data_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign mux_data_rawIn_1_isInf = _mux_data_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:63:19, :65:28] assign _mux_data_rawIn_out_sExp_T_3 = {1'h0, _mux_data_rawIn_out_sExp_T_2}; // @[rawFloatFromFN.scala:68:{28,42}] assign mux_data_rawIn_1_sExp = _mux_data_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:63:19, :68:42] wire _mux_data_rawIn_out_sig_T_4 = ~mux_data_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _mux_data_rawIn_out_sig_T_5 = {1'h0, _mux_data_rawIn_out_sig_T_4}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _mux_data_rawIn_out_sig_T_6 = mux_data_rawIn_isZeroExpIn_1 ? mux_data_rawIn_subnormFract_1 : mux_data_rawIn_fractIn_1; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _mux_data_rawIn_out_sig_T_7 = {_mux_data_rawIn_out_sig_T_5, _mux_data_rawIn_out_sig_T_6}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign mux_data_rawIn_1_sig = _mux_data_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _mux_data_T_16 = mux_data_rawIn_1_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _mux_data_T_17 = mux_data_rawIn_1_isZero ? 3'h0 : _mux_data_T_16; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _mux_data_T_19 = {_mux_data_T_17[2:1], _mux_data_T_17[0] \| _mux_data_T_18}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _mux_data_T_20 = {mux_data_rawIn_1_sign, _mux_data_T_19}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _mux_data_T_21 = mux_data_rawIn_1_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _mux_data_T_22 = {_mux_data_T_20, _mux_data_T_21}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _mux_data_T_23 = mux_data_rawIn_1_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] _mux_data_T_24 = {_mux_data_T_22, _mux_data_T_23}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire mux_data_rawIn_sign_2 = _mux_data_T_6[15]; // @[FPU.scala:431:23] wire mux_data_rawIn_2_sign = mux_data_rawIn_sign_2; // @[rawFloatFromFN.scala:44:18, :63:19] wire [4:0] mux_data_rawIn_expIn_2 = _mux_data_T_6[14:10]; // @[FPU.scala:431:23] wire [9:0] mux_data_rawIn_fractIn_2 = _mux_data_T_6[9:0]; // @[FPU.scala:431:23] wire mux_data_rawIn_isZeroExpIn_2 = mux_data_rawIn_expIn_2 == 5'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire mux_data_rawIn_isZeroFractIn_2 = mux_data_rawIn_fractIn_2 == 10'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _mux_data_rawIn_normDist_T_146 = mux_data_rawIn_fractIn_2[0]; // @[rawFloatFromFN.scala:46:21] wire _mux_data_rawIn_normDist_T_147 = mux_data_rawIn_fractIn_2[1]; // @[rawFloatFromFN.scala:46:21] wire _mux_data_rawIn_normDist_T_148 = mux_data_rawIn_fractIn_2[2]; // @[rawFloatFromFN.scala:46:21] wire _mux_data_rawIn_normDist_T_149 = mux_data_rawIn_fractIn_2[3]; // @[rawFloatFromFN.scala:46:21] wire _mux_data_rawIn_normDist_T_150 = mux_data_rawIn_fractIn_2[4]; // @[rawFloatFromFN.scala:46:21] wire _mux_data_rawIn_normDist_T_151 = mux_data_rawIn_fractIn_2[5]; // @[rawFloatFromFN.scala:46:21] wire _mux_data_rawIn_normDist_T_152 = mux_data_rawIn_fractIn_2[6]; // @[rawFloatFromFN.scala:46:21] wire _mux_data_rawIn_normDist_T_153 = mux_data_rawIn_fractIn_2[7]; // @[rawFloatFromFN.scala:46:21] wire _mux_data_rawIn_normDist_T_154 = mux_data_rawIn_fractIn_2[8]; // @[rawFloatFromFN.scala:46:21] wire _mux_data_rawIn_normDist_T_155 = mux_data_rawIn_fractIn_2[9]; // @[rawFloatFromFN.scala:46:21] wire [3:0] _mux_data_rawIn_normDist_T_156 = {3'h4, ~_mux_data_rawIn_normDist_T_147}; // @[Mux.scala:50:70] wire [3:0] _mux_data_rawIn_normDist_T_157 = _mux_data_rawIn_normDist_T_148 ? 4'h7 : _mux_data_rawIn_normDist_T_156; // @[Mux.scala:50:70] wire [3:0] _mux_data_rawIn_normDist_T_158 = _mux_data_rawIn_normDist_T_149 ? 4'h6 : _mux_data_rawIn_normDist_T_157; // @[Mux.scala:50:70] wire [3:0] _mux_data_rawIn_normDist_T_159 = _mux_data_rawIn_normDist_T_150 ? 4'h5 : _mux_data_rawIn_normDist_T_158; // @[Mux.scala:50:70] wire [3:0] _mux_data_rawIn_normDist_T_160 = _mux_data_rawIn_normDist_T_151 ? 4'h4 : _mux_data_rawIn_normDist_T_159; // @[Mux.scala:50:70] wire [3:0] _mux_data_rawIn_normDist_T_161 = _mux_data_rawIn_normDist_T_152 ? 4'h3 : _mux_data_rawIn_normDist_T_160; // @[Mux.scala:50:70] wire [3:0] _mux_data_rawIn_normDist_T_162 = _mux_data_rawIn_normDist_T_153 ? 4'h2 : _mux_data_rawIn_normDist_T_161; // @[Mux.scala:50:70] wire [3:0] _mux_data_rawIn_normDist_T_163 = _mux_data_rawIn_normDist_T_154 ? 4'h1 : _mux_data_rawIn_normDist_T_162; // @[Mux.scala:50:70] wire [3:0] mux_data_rawIn_normDist_2 = _mux_data_rawIn_normDist_T_155 ? 4'h0 : _mux_data_rawIn_normDist_T_163; // @[Mux.scala:50:70] wire [24:0] _mux_data_rawIn_subnormFract_T_4 = {15'h0, mux_data_rawIn_fractIn_2} << mux_data_rawIn_normDist_2; // @[Mux.scala:50:70] wire [8:0] _mux_data_rawIn_subnormFract_T_5 = _mux_data_rawIn_subnormFract_T_4[8:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [9:0] mux_data_rawIn_subnormFract_2 = {_mux_data_rawIn_subnormFract_T_5, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [5:0] _mux_data_rawIn_adjustedExp_T_10 = {2'h3, ~mux_data_rawIn_normDist_2}; // @[Mux.scala:50:70] wire [5:0] _mux_data_rawIn_adjustedExp_T_11 = mux_data_rawIn_isZeroExpIn_2 ? _mux_data_rawIn_adjustedExp_T_10 : {1'h0, mux_data_rawIn_expIn_2}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _mux_data_rawIn_adjustedExp_T_12 = mux_data_rawIn_isZeroExpIn_2 ? 2'h2 : 2'h1; // @[package.scala:39:86] wire [4:0] _mux_data_rawIn_adjustedExp_T_13 = {3'h4, _mux_data_rawIn_adjustedExp_T_12}; // @[rawFloatFromFN.scala:58:{9,14}] wire [6:0] _mux_data_rawIn_adjustedExp_T_14 = {1'h0, _mux_data_rawIn_adjustedExp_T_11} + {2'h0, _mux_data_rawIn_adjustedExp_T_13}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [5:0] mux_data_rawIn_adjustedExp_2 = _mux_data_rawIn_adjustedExp_T_14[5:0]; // @[rawFloatFromFN.scala:57:9] wire [5:0] _mux_data_rawIn_out_sExp_T_4 = mux_data_rawIn_adjustedExp_2; // @[rawFloatFromFN.scala:57:9, :68:28] wire mux_data_rawIn_isZero_2 = mux_data_rawIn_isZeroExpIn_2 & mux_data_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire mux_data_rawIn_2_isZero = mux_data_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _mux_data_rawIn_isSpecial_T_2 = mux_data_rawIn_adjustedExp_2[5:4]; // @[rawFloatFromFN.scala:57:9, :61:32] wire mux_data_rawIn_isSpecial_2 = &_mux_data_rawIn_isSpecial_T_2; // @[rawFloatFromFN.scala:61:{32,57}] wire _mux_data_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:64:28] wire _mux_data_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:65:28] wire _mux_data_T_27 = mux_data_rawIn_2_isNaN; // @[recFNFromFN.scala:49:20] wire [6:0] _mux_data_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:68:42] wire [11:0] _mux_data_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:70:27] wire mux_data_rawIn_2_isInf; // @[rawFloatFromFN.scala:63:19] wire [6:0] mux_data_rawIn_2_sExp; // @[rawFloatFromFN.scala:63:19] wire [11:0] mux_data_rawIn_2_sig; // @[rawFloatFromFN.scala:63:19] wire _mux_data_rawIn_out_isNaN_T_4 = ~mux_data_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :64:31] assign _mux_data_rawIn_out_isNaN_T_5 = mux_data_rawIn_isSpecial_2 & _mux_data_rawIn_out_isNaN_T_4; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign mux_data_rawIn_2_isNaN = _mux_data_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:63:19, :64:28] assign _mux_data_rawIn_out_isInf_T_2 = mux_data_rawIn_isSpecial_2 & mux_data_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign mux_data_rawIn_2_isInf = _mux_data_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:63:19, :65:28] assign _mux_data_rawIn_out_sExp_T_5 = {1'h0, _mux_data_rawIn_out_sExp_T_4}; // @[rawFloatFromFN.scala:68:{28,42}] assign mux_data_rawIn_2_sExp = _mux_data_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:63:19, :68:42] wire _mux_data_rawIn_out_sig_T_8 = ~mux_data_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _mux_data_rawIn_out_sig_T_9 = {1'h0, _mux_data_rawIn_out_sig_T_8}; // @[rawFloatFromFN.scala:70:{16,19}] wire [9:0] _mux_data_rawIn_out_sig_T_10 = mux_data_rawIn_isZeroExpIn_2 ? mux_data_rawIn_subnormFract_2 : mux_data_rawIn_fractIn_2; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _mux_data_rawIn_out_sig_T_11 = {_mux_data_rawIn_out_sig_T_9, _mux_data_rawIn_out_sig_T_10}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign mux_data_rawIn_2_sig = _mux_data_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _mux_data_T_25 = mux_data_rawIn_2_sExp[5:3]; // @[recFNFromFN.scala:48:50] wire [2:0] _mux_data_T_26 = mux_data_rawIn_2_isZero ? 3'h0 : _mux_data_T_25; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _mux_data_T_28 = {_mux_data_T_26[2:1], _mux_data_T_26[0] \| _mux_data_T_27}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _mux_data_T_29 = {mux_data_rawIn_2_sign, _mux_data_T_28}; // @[recFNFromFN.scala:47:20, :48:76] wire [2:0] _mux_data_T_30 = mux_data_rawIn_2_sExp[2:0]; // @[recFNFromFN.scala:50:23] wire [6:0] _mux_data_T_31 = {_mux_data_T_29, _mux_data_T_30}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [9:0] _mux_data_T_32 = mux_data_rawIn_2_sig[9:0]; // @[recFNFromFN.scala:51:22] wire [16:0] _mux_data_T_33 = {_mux_data_T_31, _mux_data_T_32}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [3:0] _mux_data_swizzledNaN_T = _mux_data_T_24[32:29]; // @[FPU.scala:337:8] wire [6:0] _mux_data_swizzledNaN_T_1 = _mux_data_T_24[22:16]; // @[FPU.scala:338:8] wire [6:0] _mux_data_swizzledNaN_T_5 = _mux_data_T_24[22:16]; // @[FPU.scala:338:8, :341:8] wire _mux_data_swizzledNaN_T_2 = &_mux_data_swizzledNaN_T_1; // @[FPU.scala:338:{8,42}] wire [3:0] _mux_data_swizzledNaN_T_3 = _mux_data_T_24[27:24]; // @[FPU.scala:339:8] wire _mux_data_swizzledNaN_T_4 = _mux_data_T_33[15]; // @[FPU.scala:340:8] wire _mux_data_swizzledNaN_T_6 = _mux_data_T_33[16]; // @[FPU.scala:342:8] wire [14:0] _mux_data_swizzledNaN_T_7 = _mux_data_T_33[14:0]; // @[FPU.scala:343:8] wire [7:0] mux_data_swizzledNaN_lo_hi = {_mux_data_swizzledNaN_T_5, _mux_data_swizzledNaN_T_6}; // @[FPU.scala:336:26, :341:8, :342:8] wire [22:0] mux_data_swizzledNaN_lo = {mux_data_swizzledNaN_lo_hi, _mux_data_swizzledNaN_T_7}; // @[FPU.scala:336:26, :343:8] wire [4:0] mux_data_swizzledNaN_hi_lo = {_mux_data_swizzledNaN_T_3, _mux_data_swizzledNaN_T_4}; // @[FPU.scala:336:26, :339:8, :340:8] wire [4:0] mux_data_swizzledNaN_hi_hi = {_mux_data_swizzledNaN_T, _mux_data_swizzledNaN_T_2}; // @[FPU.scala:336:26, :337:8, :338:42] wire [9:0] mux_data_swizzledNaN_hi = {mux_data_swizzledNaN_hi_hi, mux_data_swizzledNaN_hi_lo}; // @[FPU.scala:336:26] wire [32:0] mux_data_swizzledNaN = {mux_data_swizzledNaN_hi, mux_data_swizzledNaN_lo}; // @[FPU.scala:336:26] wire [2:0] _mux_data_T_34 = _mux_data_T_24[31:29]; // @[FPU.scala:249:25] wire _mux_data_T_35 = &_mux_data_T_34; // @[FPU.scala:249:{25,56}] wire [32:0] _mux_data_T_36 = _mux_data_T_35 ? mux_data_swizzledNaN : _mux_data_T_24; // @[FPU.scala:249:56, :336:26, :344:8] wire [3:0] _mux_data_swizzledNaN_T_8 = _mux_data_T_15[64:61]; // @[FPU.scala:337:8] wire [19:0] _mux_data_swizzledNaN_T_9 = _mux_data_T_15[51:32]; // @[FPU.scala:338:8] wire [19:0] _mux_data_swizzledNaN_T_13 = _mux_data_T_15[51:32]; // @[FPU.scala:338:8, :341:8] wire _mux_data_swizzledNaN_T_10 = &_mux_data_swizzledNaN_T_9; // @[FPU.scala:338:{8,42}] wire [6:0] _mux_data_swizzledNaN_T_11 = _mux_data_T_15[59:53]; // @[FPU.scala:339:8] wire _mux_data_swizzledNaN_T_12 = _mux_data_T_36[31]; // @[FPU.scala:340:8, :344:8] wire _mux_data_swizzledNaN_T_14 = _mux_data_T_36[32]; // @[FPU.scala:342:8, :344:8] wire [30:0] _mux_data_swizzledNaN_T_15 = _mux_data_T_36[30:0]; // @[FPU.scala:343:8, :344:8] wire [20:0] mux_data_swizzledNaN_lo_hi_1 = {_mux_data_swizzledNaN_T_13, _mux_data_swizzledNaN_T_14}; // @[FPU.scala:336:26, :341:8, :342:8] wire [51:0] mux_data_swizzledNaN_lo_1 = {mux_data_swizzledNaN_lo_hi_1, _mux_data_swizzledNaN_T_15}; // @[FPU.scala:336:26, :343:8] wire [7:0] mux_data_swizzledNaN_hi_lo_1 = {_mux_data_swizzledNaN_T_11, _mux_data_swizzledNaN_T_12}; // @[FPU.scala:336:26, :339:8, :340:8] wire [4:0] mux_data_swizzledNaN_hi_hi_1 = {_mux_data_swizzledNaN_T_8, _mux_data_swizzledNaN_T_10}; // @[FPU.scala:336:26, :337:8, :338:42] wire [12:0] mux_data_swizzledNaN_hi_1 = {mux_data_swizzledNaN_hi_hi_1, mux_data_swizzledNaN_hi_lo_1}; // @[FPU.scala:336:26] wire [64:0] mux_data_swizzledNaN_1 = {mux_data_swizzledNaN_hi_1, mux_data_swizzledNaN_lo_1}; // @[FPU.scala:336:26] wire [2:0] _mux_data_T_37 = _mux_data_T_15[63:61]; // @[FPU.scala:249:25] wire _mux_data_T_38 = &_mux_data_T_37; // @[FPU.scala:249:{25,56}] wire [64:0] _mux_data_T_39 = _mux_data_T_38 ? mux_data_swizzledNaN_1 : _mux_data_T_15; // @[FPU.scala:249:56, :336:26, :344:8] wire [63:0] intValue_res; // @[FPU.scala:542:26] wire [63:0] intValue = intValue_res; // @[FPU.scala:542:26, :549:9] wire [31:0] intValue_smallInt = in_bits_in1[31:0]; // @[Valid.scala:135:21] wire [31:0] _intValue_res_T_3 = intValue_smallInt; // @[FPU.scala:544:33, :546:60] wire _intValue_T = in_bits_typ[1]; // @[Valid.scala:135:21] wire _intValue_T_1 = ~_intValue_T; // @[package.scala:163:13] wire _intValue_res_T_1 = in_bits_typ[0]; // @[Valid.scala:135:21] wire _i2fResults_i2f_io_signedIn_T = in_bits_typ[0]; // @[Valid.scala:135:21] wire _i2fResults_i2f_io_signedIn_T_2 = in_bits_typ[0]; // @[Valid.scala:135:21] wire _i2fResults_i2f_io_signedIn_T_4 = in_bits_typ[0]; // @[Valid.scala:135:21] wire [32:0] _intValue_res_T_2 = {1'h0, intValue_smallInt}; // @[FPU.scala:544:33, :546:45] wire [32:0] _intValue_res_T_4 = _intValue_res_T_1 ? _intValue_res_T_2 : {_intValue_res_T_3[31], _intValue_res_T_3}; // @[FPU.scala:546:{19,31,45,60}] assign intValue_res = _intValue_T_1 ? {{31{_intValue_res_T_4[32]}}, _intValue_res_T_4} : _intValue_res_T; // @[FPU.scala:542:{26,39}, :545:{57,66}, :546:{13,19}] wire _i2fResults_i2f_io_signedIn_T_1 = ~_i2fResults_i2f_io_signedIn_T; // @[FPU.scala:557:{26,38}] wire _i2fResults_i2f_io_signedIn_T_3 = ~_i2fResults_i2f_io_signedIn_T_2; // @[FPU.scala:557:{26,38}] wire [32:0] i2fResults_maskedNaN = _i2fResults_i2f_1_io_out & 33'h1EF7FFFFF; // @[FPU.scala:413:25, :556:23] wire [2:0] _i2fResults_T = _i2fResults_i2f_1_io_out[31:29]; // @[FPU.scala:249:25, :556:23] wire _i2fResults_T_1 = &_i2fResults_T; // @[FPU.scala:249:{25,56}] wire [32:0] i2fResults_1_1 = _i2fResults_T_1 ? i2fResults_maskedNaN : _i2fResults_i2f_1_io_out; // @[FPU.scala:249:56, :413:25, :414:10, :556:23] wire _i2fResults_i2f_io_signedIn_T_5 = ~_i2fResults_i2f_io_signedIn_T_4; // @[FPU.scala:557:{26,38}] wire [64:0] i2fResults_maskedNaN_1 = _i2fResults_i2f_2_io_out & 65'h1EFEFFFFFFFFFFFFF; // @[FPU.scala:413:25, :556:23] wire [2:0] _i2fResults_T_2 = _i2fResults_i2f_2_io_out[63:61]; // @[FPU.scala:249:25, :556:23] wire _i2fResults_T_3 = &_i2fResults_T_2; // @[FPU.scala:249:{25,56}] wire [64:0] i2fResults_2_1 = _i2fResults_T_3 ? i2fResults_maskedNaN_1 : _i2fResults_i2f_2_io_out; // @[FPU.scala:249:56, :413:25, :414:10, :556:23] wire [47:0] _dataPadded_T = i2fResults_2_1[64:17]; // @[FPU.scala:414:10, :565:55] wire [64:0] dataPadded_0 = {_dataPadded_T, _i2fResults_i2f_io_out}; // @[FPU.scala:556:23, :565:{44,55}] wire [31:0] _dataPadded_T_1 = i2fResults_2_1[64:33]; // @[FPU.scala:414:10, :565:55] wire [64:0] dataPadded_1 = {_dataPadded_T_1, i2fResults_1_1}; // @[FPU.scala:414:10, :565:{44,55}] wire [64:0] _mux_data_T_41 = _mux_data_T_40 ? dataPadded_1 : dataPadded_0; // @[package.scala:39:{76,86}] wire [64:0] _mux_data_T_43 = _mux_data_T_42 ? i2fResults_2_1 : _mux_data_T_41; // @[package.scala:39:{76,86}] wire _mux_data_T_44 = &in_bits_typeTagIn; // @[Valid.scala:135:21] wire [64:0] _mux_data_T_45 = _mux_data_T_44 ? i2fResults_2_1 : _mux_data_T_43; // @[package.scala:39:{76,86}] assign mux_data = in_bits_wflags ? _mux_data_T_45 : _mux_data_T_39; // @[Valid.scala:135:21] wire [4:0] _mux_exc_T_1 = _mux_exc_T ? _i2fResults_i2f_1_io_exceptionFlags : _i2fResults_i2f_io_exceptionFlags; // @[package.scala:39:{76,86}] wire [4:0] _mux_exc_T_3 = _mux_exc_T_2 ? _i2fResults_i2f_2_io_exceptionFlags : _mux_exc_T_1; // @[package.scala:39:{76,86}] wire _mux_exc_T_4 = &in_bits_typeTagIn; // @[Valid.scala:135:21] wire [4:0] _mux_exc_T_5 = _mux_exc_T_4 ? _i2fResults_i2f_2_io_exceptionFlags : _mux_exc_T_3; // @[package.scala:39:{76,86}] assign mux_exc = in_bits_wflags ? _mux_exc_T_5 : 5'h0; // @[Valid.scala:135:21] reg io_out_pipe_v; // @[Valid.scala:141:24] assign io_out_pipe_out_valid = io_out_pipe_v; // @[Valid.scala:135:21, :141:24] reg [64:0] io_out_pipe_b_data; // @[Valid.scala:142:26] assign io_out_pipe_out_bits_data = io_out_pipe_b_data; // @[Valid.scala:135:21, :142:26] reg [4:0] io_out_pipe_b_exc; // @[Valid.scala:142:26] assign io_out_pipe_out_bits_exc = io_out_pipe_b_exc; // @[Valid.scala:135:21, :142:26] assign io_out_valid = io_out_pipe_out_valid; // @[Valid.scala:135:21] assign io_out_bits_data_0 = io_out_pipe_out_bits_data; // @[Valid.scala:135:21] assign io_out_bits_exc_0 = io_out_pipe_out_bits_exc; // @[Valid.scala:135:21] always @(posedge clock) begin // @[FPU.scala:528:7] if (reset) begin // @[FPU.scala:528:7] in_pipe_v <= 1'h0; // @[Valid.scala:141:24] io_out_pipe_v <= 1'h0; // @[Valid.scala:141:24] end else begin // @[FPU.scala:528:7] in_pipe_v <= io_in_valid_0; // @[Valid.scala:141:24] io_out_pipe_v <= in_valid; // @[Valid.scala:135:21, :141:24] end if (io_in_valid_0) begin // @[FPU.scala:528:7] in_pipe_b_ldst <= io_in_bits_ldst_0; // @[Valid.scala:142:26] in_pipe_b_wen <= io_in_bits_wen_0; // @[Valid.scala:142:26] in_pipe_b_ren1 <= io_in_bits_ren1_0; // @[Valid.scala:142:26] in_pipe_b_ren2 <= io_in_bits_ren2_0; // @[Valid.scala:142:26] in_pipe_b_ren3 <= io_in_bits_ren3_0; // @[Valid.scala:142:26] in_pipe_b_swap12 <= io_in_bits_swap12_0; // @[Valid.scala:142:26] in_pipe_b_swap23 <= io_in_bits_swap23_0; // @[Valid.scala:142:26] in_pipe_b_typeTagIn <= io_in_bits_typeTagIn_0; // @[Valid.scala:142:26] in_pipe_b_typeTagOut <= io_in_bits_typeTagOut_0; // @[Valid.scala:142:26] in_pipe_b_fromint <= io_in_bits_fromint_0; // @[Valid.scala:142:26] in_pipe_b_toint <= io_in_bits_toint_0; // @[Valid.scala:142:26] in_pipe_b_fastpipe <= io_in_bits_fastpipe_0; // @[Valid.scala:142:26] in_pipe_b_fma <= io_in_bits_fma_0; // @[Valid.scala:142:26] in_pipe_b_div <= io_in_bits_div_0; // @[Valid.scala:142:26] in_pipe_b_sqrt <= io_in_bits_sqrt_0; // @[Valid.scala:142:26] in_pipe_b_wflags <= io_in_bits_wflags_0; // @[Valid.scala:142:26] in_pipe_b_vec <= io_in_bits_vec_0; // @[Valid.scala:142:26] in_pipe_b_rm <= io_in_bits_rm_0; // @[Valid.scala:142:26] in_pipe_b_typ <= io_in_bits_typ_0; // @[Valid.scala:142:26] in_pipe_b_in1 <= io_in_bits_in1_0; // @[Valid.scala:142:26] end if (in_valid) begin // @[Valid.scala:135:21] io_out_pipe_b_data <= mux_data; // @[Valid.scala:142:26] io_out_pipe_b_exc <= mux_exc; // @[Valid.scala:142:26] end always @(posedge) INToRecFN_i64_e5_s11 i2fResults_i2f ( // @[FPU.scala:556:23] .io_signedIn (_i2fResults_i2f_io_signedIn_T_1), // @[FPU.scala:557:26] .io_in (intValue), // @[FPU.scala:549:9] .io_roundingMode (in_bits_rm), // @[Valid.scala:135:21] .io_out (_i2fResults_i2f_io_out), .io_exceptionFlags (_i2fResults_i2f_io_exceptionFlags) ); // @[FPU.scala:556:23] INToRecFN_i64_e8_s24 i2fResults_i2f_1 ( // @[FPU.scala:556:23] .io_signedIn (_i2fResults_i2f_io_signedIn_T_3), // @[FPU.scala:557:26] .io_in (intValue), // @[FPU.scala:549:9] .io_roundingMode (in_bits_rm), // @[Valid.scala:135:21] .io_out (_i2fResults_i2f_1_io_out), .io_exceptionFlags (_i2fResults_i2f_1_io_exceptionFlags) ); // @[FPU.scala:556:23] INToRecFN_i64_e11_s53 i2fResults_i2f_2 ( // @[FPU.scala:556:23] .io_signedIn (_i2fResults_i2f_io_signedIn_T_5), // @[FPU.scala:557:26] .io_in (intValue), // @[FPU.scala:549:9] .io_roundingMode (in_bits_rm), // @[Valid.scala:135:21] .io_out (_i2fResults_i2f_2_io_out), .io_exceptionFlags (_i2fResults_i2f_2_io_exceptionFlags) ); // @[FPU.scala:556:23] assign io_out_bits_data = io_out_bits_data_0; // @[FPU.scala:528:7] assign io_out_bits_exc = io_out_bits_exc_0; // @[FPU.scala:528:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PriorityQueueStage_249 : input clock : Clock input reset : Reset output io : { output_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, output_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip cmd : { valid : UInt<1>, bits : UInt<1>}, flip insert_here : UInt<1>, flip cur_input_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}, cur_output_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}} regreset key_reg : UInt<31>, clock, reset, UInt<31>(0h7fffffff) reg value_reg : { symbol : UInt<10>}, clock connect io.output_prev.key, key_reg connect io.output_prev.value, value_reg connect io.output_nxt.key, key_reg connect io.output_nxt.value, value_reg connect io.cur_output_keyval.key, key_reg connect io.cur_output_keyval.value, value_reg when io.cmd.valid : node _T = eq(UInt<1>(0h0), io.cmd.bits) when _T : connect key_reg, io.input_nxt.key connect value_reg, io.input_nxt.value else : node _T_1 = eq(UInt<1>(0h1), io.cmd.bits) when _T_1 : when io.insert_here : connect key_reg, io.cur_input_keyval.key connect value_reg, io.cur_input_keyval.value else : node _T_2 = geq(key_reg, io.cur_input_keyval.key) when _T_2 : connect key_reg, io.input_prev.key connect value_reg, io.input_prev.value else : skip	module PriorityQueueStage_249( // @[ShiftRegisterPriorityQueue.scala:21:7] input clock, // @[ShiftRegisterPriorityQueue.scala:21:7] input reset, // @[ShiftRegisterPriorityQueue.scala:21:7] output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14] ); wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24] assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22] assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30] always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24] else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end else // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end else // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end always @(posedge) assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_39 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_source_valid of AsyncResetSynchronizerShiftReg_w1_d3_i0_50 connect io_out_source_valid.clock, clock connect io_out_source_valid.reset, reset connect io_out_source_valid.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_source_valid.io.q connect io.out, _io_out_WIRE	module AsyncValidSync_39( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_50 io_out_source_valid ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMasterACDToNoC_3 : input clock : Clock input reset : Reset output io : { flip tilelink : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<6>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}}}, flits : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, egress_id : UInt}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, egress_id : UInt}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, ingress_id : UInt}}}} invalidate io.tilelink.e.bits.sink invalidate io.tilelink.e.valid invalidate io.tilelink.e.ready invalidate io.tilelink.d.bits.corrupt invalidate io.tilelink.d.bits.data invalidate io.tilelink.d.bits.denied invalidate io.tilelink.d.bits.sink invalidate io.tilelink.d.bits.source invalidate io.tilelink.d.bits.size invalidate io.tilelink.d.bits.param invalidate io.tilelink.d.bits.opcode invalidate io.tilelink.d.valid invalidate io.tilelink.d.ready invalidate io.tilelink.c.bits.corrupt invalidate io.tilelink.c.bits.data invalidate io.tilelink.c.bits.address invalidate io.tilelink.c.bits.source invalidate io.tilelink.c.bits.size invalidate io.tilelink.c.bits.param invalidate io.tilelink.c.bits.opcode invalidate io.tilelink.c.valid invalidate io.tilelink.c.ready invalidate io.tilelink.b.bits.corrupt invalidate io.tilelink.b.bits.data invalidate io.tilelink.b.bits.mask invalidate io.tilelink.b.bits.address invalidate io.tilelink.b.bits.source invalidate io.tilelink.b.bits.size invalidate io.tilelink.b.bits.param invalidate io.tilelink.b.bits.opcode invalidate io.tilelink.b.valid invalidate io.tilelink.b.ready invalidate io.tilelink.a.bits.corrupt invalidate io.tilelink.a.bits.data invalidate io.tilelink.a.bits.mask invalidate io.tilelink.a.bits.address invalidate io.tilelink.a.bits.source invalidate io.tilelink.a.bits.size invalidate io.tilelink.a.bits.param invalidate io.tilelink.a.bits.opcode invalidate io.tilelink.a.valid invalidate io.tilelink.a.ready inst a of TLAToNoC_3 connect a.clock, clock connect a.reset, reset inst c of TLCToNoC_3 connect c.clock, clock connect c.reset, reset inst d of TLDFromNoC_3 connect d.clock, clock connect d.reset, reset connect a.io.protocol, io.tilelink.a connect c.io.protocol, io.tilelink.c connect io.tilelink.d.bits, d.io.protocol.bits connect io.tilelink.d.valid, d.io.protocol.valid connect d.io.protocol.ready, io.tilelink.d.ready connect io.flits.a.bits, a.io.flit.bits connect io.flits.a.valid, a.io.flit.valid connect a.io.flit.ready, io.flits.a.ready connect io.flits.c.bits, c.io.flit.bits connect io.flits.c.valid, c.io.flit.valid connect c.io.flit.ready, io.flits.c.ready connect d.io.flit, io.flits.d	module TLMasterACDToNoC_3( // @[Tilelink.scala:72:7] input clock, // @[Tilelink.scala:72:7] input reset, // @[Tilelink.scala:72:7] output io_tilelink_a_ready, // @[Tilelink.scala:79:14] input io_tilelink_a_valid, // @[Tilelink.scala:79:14] input [2:0] io_tilelink_a_bits_opcode, // @[Tilelink.scala:79:14] input [2:0] io_tilelink_a_bits_param, // @[Tilelink.scala:79:14] input [3:0] io_tilelink_a_bits_size, // @[Tilelink.scala:79:14] input [6:0] io_tilelink_a_bits_source, // @[Tilelink.scala:79:14] input [31:0] io_tilelink_a_bits_address, // @[Tilelink.scala:79:14] input [15:0] io_tilelink_a_bits_mask, // @[Tilelink.scala:79:14] input [127:0] io_tilelink_a_bits_data, // @[Tilelink.scala:79:14] input io_tilelink_a_bits_corrupt, // @[Tilelink.scala:79:14] output io_tilelink_c_ready, // @[Tilelink.scala:79:14] input io_tilelink_c_valid, // @[Tilelink.scala:79:14] input [2:0] io_tilelink_c_bits_opcode, // @[Tilelink.scala:79:14] input [2:0] io_tilelink_c_bits_param, // @[Tilelink.scala:79:14] input [3:0] io_tilelink_c_bits_size, // @[Tilelink.scala:79:14] input [6:0] io_tilelink_c_bits_source, // @[Tilelink.scala:79:14] input [31:0] io_tilelink_c_bits_address, // @[Tilelink.scala:79:14] input [127:0] io_tilelink_c_bits_data, // @[Tilelink.scala:79:14] input io_tilelink_c_bits_corrupt, // @[Tilelink.scala:79:14] input io_tilelink_d_ready, // @[Tilelink.scala:79:14] output io_tilelink_d_valid, // @[Tilelink.scala:79:14] output [2:0] io_tilelink_d_bits_opcode, // @[Tilelink.scala:79:14] output [1:0] io_tilelink_d_bits_param, // @[Tilelink.scala:79:14] output [3:0] io_tilelink_d_bits_size, // @[Tilelink.scala:79:14] output [6:0] io_tilelink_d_bits_source, // @[Tilelink.scala:79:14] output [5:0] io_tilelink_d_bits_sink, // @[Tilelink.scala:79:14] output io_tilelink_d_bits_denied, // @[Tilelink.scala:79:14] output [127:0] io_tilelink_d_bits_data, // @[Tilelink.scala:79:14] output io_tilelink_d_bits_corrupt, // @[Tilelink.scala:79:14] input io_flits_a_ready, // @[Tilelink.scala:79:14] output io_flits_a_valid, // @[Tilelink.scala:79:14] output io_flits_a_bits_head, // @[Tilelink.scala:79:14] output io_flits_a_bits_tail, // @[Tilelink.scala:79:14] output [144:0] io_flits_a_bits_payload, // @[Tilelink.scala:79:14] output [4:0] io_flits_a_bits_egress_id, // @[Tilelink.scala:79:14] input io_flits_c_ready, // @[Tilelink.scala:79:14] output io_flits_c_valid, // @[Tilelink.scala:79:14] output io_flits_c_bits_head, // @[Tilelink.scala:79:14] output io_flits_c_bits_tail, // @[Tilelink.scala:79:14] output [144:0] io_flits_c_bits_payload, // @[Tilelink.scala:79:14] output [4:0] io_flits_c_bits_egress_id, // @[Tilelink.scala:79:14] output io_flits_d_ready, // @[Tilelink.scala:79:14] input io_flits_d_valid, // @[Tilelink.scala:79:14] input io_flits_d_bits_head, // @[Tilelink.scala:79:14] input io_flits_d_bits_tail, // @[Tilelink.scala:79:14] input [144:0] io_flits_d_bits_payload // @[Tilelink.scala:79:14] ); wire [128:0] _c_io_flit_bits_payload; // @[Tilelink.scala:89:17] TLAToNoC_3 a ( // @[Tilelink.scala:88:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_a_ready), .io_protocol_valid (io_tilelink_a_valid), .io_protocol_bits_opcode (io_tilelink_a_bits_opcode), .io_protocol_bits_param (io_tilelink_a_bits_param), .io_protocol_bits_size (io_tilelink_a_bits_size), .io_protocol_bits_source (io_tilelink_a_bits_source), .io_protocol_bits_address (io_tilelink_a_bits_address), .io_protocol_bits_mask (io_tilelink_a_bits_mask), .io_protocol_bits_data (io_tilelink_a_bits_data), .io_protocol_bits_corrupt (io_tilelink_a_bits_corrupt), .io_flit_ready (io_flits_a_ready), .io_flit_valid (io_flits_a_valid), .io_flit_bits_head (io_flits_a_bits_head), .io_flit_bits_tail (io_flits_a_bits_tail), .io_flit_bits_payload (io_flits_a_bits_payload), .io_flit_bits_egress_id (io_flits_a_bits_egress_id) ); // @[Tilelink.scala:88:17] TLCToNoC_3 c ( // @[Tilelink.scala:89:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_c_ready), .io_protocol_valid (io_tilelink_c_valid), .io_protocol_bits_opcode (io_tilelink_c_bits_opcode), .io_protocol_bits_param (io_tilelink_c_bits_param), .io_protocol_bits_size (io_tilelink_c_bits_size), .io_protocol_bits_source (io_tilelink_c_bits_source), .io_protocol_bits_address (io_tilelink_c_bits_address), .io_protocol_bits_data (io_tilelink_c_bits_data), .io_protocol_bits_corrupt (io_tilelink_c_bits_corrupt), .io_flit_ready (io_flits_c_ready), .io_flit_valid (io_flits_c_valid), .io_flit_bits_head (io_flits_c_bits_head), .io_flit_bits_tail (io_flits_c_bits_tail), .io_flit_bits_payload (_c_io_flit_bits_payload), .io_flit_bits_egress_id (io_flits_c_bits_egress_id) ); // @[Tilelink.scala:89:17] TLDFromNoC_1 d ( // @[Tilelink.scala:90:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_d_ready), .io_protocol_valid (io_tilelink_d_valid), .io_protocol_bits_opcode (io_tilelink_d_bits_opcode), .io_protocol_bits_param (io_tilelink_d_bits_param), .io_protocol_bits_size (io_tilelink_d_bits_size), .io_protocol_bits_source (io_tilelink_d_bits_source), .io_protocol_bits_sink (io_tilelink_d_bits_sink), .io_protocol_bits_denied (io_tilelink_d_bits_denied), .io_protocol_bits_data (io_tilelink_d_bits_data), .io_protocol_bits_corrupt (io_tilelink_d_bits_corrupt), .io_flit_ready (io_flits_d_ready), .io_flit_valid (io_flits_d_valid), .io_flit_bits_head (io_flits_d_bits_head), .io_flit_bits_tail (io_flits_d_bits_tail), .io_flit_bits_payload (io_flits_d_bits_payload[128:0]) // @[Tilelink.scala:97:14] ); // @[Tilelink.scala:90:17] assign io_flits_c_bits_payload = {16'h0, _c_io_flit_bits_payload}; // @[Tilelink.scala:72:7, :89:17, :96:14] endmodule
Generate the Verilog code corresponding to this FIRRTL code module IssueSlot_5 : input clock : Clock input reset : Reset output io : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, request_hp : UInt<1>, flip grant : UInt<1>, flip brupdate : { b1 : { resolve_mask : UInt<8>, mispredict_mask : UInt<8>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, flip kill : UInt<1>, flip clear : UInt<1>, flip ldspec_miss : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { pdst : UInt<6>, poisoned : UInt<1>}}[2], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<4>}, flip spec_ld_wakeup : { valid : UInt<1>, bits : UInt<6>}[1], flip in_uop : { valid : UInt<1>, bits : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}}, out_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, debug : { p1 : UInt<1>, p2 : UInt<1>, p3 : UInt<1>, ppred : UInt<1>, state : UInt<2>}} wire next_state : UInt wire next_uopc : UInt wire next_lrs1_rtype : UInt wire next_lrs2_rtype : UInt regreset state : UInt<2>, clock, reset, UInt<2>(0h0) regreset p1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset p2 : UInt<1>, clock, reset, UInt<1>(0h0) regreset p3 : UInt<1>, clock, reset, UInt<1>(0h0) regreset ppred : UInt<1>, clock, reset, UInt<1>(0h0) regreset p1_poisoned : UInt<1>, clock, reset, UInt<1>(0h0) regreset p2_poisoned : UInt<1>, clock, reset, UInt<1>(0h0) connect p1_poisoned, UInt<1>(0h0) connect p2_poisoned, UInt<1>(0h0) node next_p1_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned) node next_p2_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned) wire slot_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>} invalidate slot_uop_uop.debug_tsrc invalidate slot_uop_uop.debug_fsrc invalidate slot_uop_uop.bp_xcpt_if invalidate slot_uop_uop.bp_debug_if invalidate slot_uop_uop.xcpt_ma_if invalidate slot_uop_uop.xcpt_ae_if invalidate slot_uop_uop.xcpt_pf_if invalidate slot_uop_uop.fp_single invalidate slot_uop_uop.fp_val invalidate slot_uop_uop.frs3_en invalidate slot_uop_uop.lrs2_rtype invalidate slot_uop_uop.lrs1_rtype invalidate slot_uop_uop.dst_rtype invalidate slot_uop_uop.ldst_val invalidate slot_uop_uop.lrs3 invalidate slot_uop_uop.lrs2 invalidate slot_uop_uop.lrs1 invalidate slot_uop_uop.ldst invalidate slot_uop_uop.ldst_is_rs1 invalidate slot_uop_uop.flush_on_commit invalidate slot_uop_uop.is_unique invalidate slot_uop_uop.is_sys_pc2epc invalidate slot_uop_uop.uses_stq invalidate slot_uop_uop.uses_ldq invalidate slot_uop_uop.is_amo invalidate slot_uop_uop.is_fencei invalidate slot_uop_uop.is_fence invalidate slot_uop_uop.mem_signed invalidate slot_uop_uop.mem_size invalidate slot_uop_uop.mem_cmd invalidate slot_uop_uop.bypassable invalidate slot_uop_uop.exc_cause invalidate slot_uop_uop.exception invalidate slot_uop_uop.stale_pdst invalidate slot_uop_uop.ppred_busy invalidate slot_uop_uop.prs3_busy invalidate slot_uop_uop.prs2_busy invalidate slot_uop_uop.prs1_busy invalidate slot_uop_uop.ppred invalidate slot_uop_uop.prs3 invalidate slot_uop_uop.prs2 invalidate slot_uop_uop.prs1 invalidate slot_uop_uop.pdst invalidate slot_uop_uop.rxq_idx invalidate slot_uop_uop.stq_idx invalidate slot_uop_uop.ldq_idx invalidate slot_uop_uop.rob_idx invalidate slot_uop_uop.csr_addr invalidate slot_uop_uop.imm_packed invalidate slot_uop_uop.taken invalidate slot_uop_uop.pc_lob invalidate slot_uop_uop.edge_inst invalidate slot_uop_uop.ftq_idx invalidate slot_uop_uop.br_tag invalidate slot_uop_uop.br_mask invalidate slot_uop_uop.is_sfb invalidate slot_uop_uop.is_jal invalidate slot_uop_uop.is_jalr invalidate slot_uop_uop.is_br invalidate slot_uop_uop.iw_p2_poisoned invalidate slot_uop_uop.iw_p1_poisoned invalidate slot_uop_uop.iw_state invalidate slot_uop_uop.ctrl.is_std invalidate slot_uop_uop.ctrl.is_sta invalidate slot_uop_uop.ctrl.is_load invalidate slot_uop_uop.ctrl.csr_cmd invalidate slot_uop_uop.ctrl.fcn_dw invalidate slot_uop_uop.ctrl.op_fcn invalidate slot_uop_uop.ctrl.imm_sel invalidate slot_uop_uop.ctrl.op2_sel invalidate slot_uop_uop.ctrl.op1_sel invalidate slot_uop_uop.ctrl.br_type invalidate slot_uop_uop.fu_code invalidate slot_uop_uop.iq_type invalidate slot_uop_uop.debug_pc invalidate slot_uop_uop.is_rvc invalidate slot_uop_uop.debug_inst invalidate slot_uop_uop.inst invalidate slot_uop_uop.uopc connect slot_uop_uop.uopc, UInt<7>(0h0) connect slot_uop_uop.bypassable, UInt<1>(0h0) connect slot_uop_uop.fp_val, UInt<1>(0h0) connect slot_uop_uop.uses_stq, UInt<1>(0h0) connect slot_uop_uop.uses_ldq, UInt<1>(0h0) connect slot_uop_uop.pdst, UInt<1>(0h0) connect slot_uop_uop.dst_rtype, UInt<2>(0h2) wire slot_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>} invalidate slot_uop_cs.is_std invalidate slot_uop_cs.is_sta invalidate slot_uop_cs.is_load invalidate slot_uop_cs.csr_cmd invalidate slot_uop_cs.fcn_dw invalidate slot_uop_cs.op_fcn invalidate slot_uop_cs.imm_sel invalidate slot_uop_cs.op2_sel invalidate slot_uop_cs.op1_sel invalidate slot_uop_cs.br_type connect slot_uop_cs.br_type, UInt<4>(0h0) connect slot_uop_cs.csr_cmd, UInt<3>(0h0) connect slot_uop_cs.is_load, UInt<1>(0h0) connect slot_uop_cs.is_sta, UInt<1>(0h0) connect slot_uop_cs.is_std, UInt<1>(0h0) connect slot_uop_uop.ctrl, slot_uop_cs regreset slot_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, clock, reset, slot_uop_uop node next_uop = mux(io.in_uop.valid, io.in_uop.bits, slot_uop) when io.kill : connect state, UInt<2>(0h0) else : when io.in_uop.valid : connect state, io.in_uop.bits.iw_state else : when io.clear : connect state, UInt<2>(0h0) else : connect state, next_state connect next_state, state connect next_uopc, slot_uop.uopc connect next_lrs1_rtype, slot_uop.lrs1_rtype connect next_lrs2_rtype, slot_uop.lrs2_rtype when io.kill : connect next_state, UInt<2>(0h0) else : node _T = eq(state, UInt<2>(0h1)) node _T_1 = and(io.grant, _T) node _T_2 = eq(state, UInt<2>(0h2)) node _T_3 = and(io.grant, _T_2) node _T_4 = and(_T_3, p1) node _T_5 = and(_T_4, p2) node _T_6 = and(_T_5, ppred) node _T_7 = or(_T_1, _T_6) when _T_7 : node _T_8 = or(p1_poisoned, p2_poisoned) node _T_9 = and(io.ldspec_miss, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) when _T_10 : connect next_state, UInt<2>(0h0) else : node _T_11 = eq(state, UInt<2>(0h2)) node _T_12 = and(io.grant, _T_11) when _T_12 : node _T_13 = or(p1_poisoned, p2_poisoned) node _T_14 = and(io.ldspec_miss, _T_13) node _T_15 = eq(_T_14, UInt<1>(0h0)) when _T_15 : connect next_state, UInt<2>(0h1) when p1 : connect slot_uop.uopc, UInt<7>(0h3) connect next_uopc, UInt<7>(0h3) connect slot_uop.lrs1_rtype, UInt<2>(0h2) connect next_lrs1_rtype, UInt<2>(0h2) else : connect slot_uop.lrs2_rtype, UInt<2>(0h2) connect next_lrs2_rtype, UInt<2>(0h2) when io.in_uop.valid : connect slot_uop, io.in_uop.bits node _T_16 = eq(state, UInt<2>(0h0)) node _T_17 = or(_T_16, io.clear) node _T_18 = or(_T_17, io.kill) node _T_19 = asUInt(reset) node _T_20 = eq(_T_19, UInt<1>(0h0)) when _T_20 : node _T_21 = eq(_T_18, UInt<1>(0h0)) when _T_21 : printf(clock, UInt<1>(0h1), "Assertion failed: trying to overwrite a valid issue slot.\n at issue-slot.scala:156 assert (is_invalid \|\| io.clear \|\| io.kill, \"trying to overwrite a valid issue slot.\")\n") : printf assert(clock, _T_18, UInt<1>(0h1), "") : assert wire next_p1 : UInt<1> connect next_p1, p1 wire next_p2 : UInt<1> connect next_p2, p2 wire next_p3 : UInt<1> connect next_p3, p3 wire next_ppred : UInt<1> connect next_ppred, ppred when io.in_uop.valid : node _p1_T = eq(io.in_uop.bits.prs1_busy, UInt<1>(0h0)) connect p1, _p1_T node _p2_T = eq(io.in_uop.bits.prs2_busy, UInt<1>(0h0)) connect p2, _p2_T node _p3_T = eq(io.in_uop.bits.prs3_busy, UInt<1>(0h0)) connect p3, _p3_T node _ppred_T = eq(io.in_uop.bits.ppred_busy, UInt<1>(0h0)) connect ppred, _ppred_T node _T_22 = and(io.ldspec_miss, next_p1_poisoned) when _T_22 : node _T_23 = neq(next_uop.prs1, UInt<1>(0h0)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs1=x0!\n at issue-slot.scala:176 assert(next_uop.prs1 =/= 0.U, \"Poison bit can't be set for prs1=x0!\")\n") : printf_1 assert(clock, _T_23, UInt<1>(0h1), "") : assert_1 connect p1, UInt<1>(0h0) node _T_27 = and(io.ldspec_miss, next_p2_poisoned) when _T_27 : node _T_28 = neq(next_uop.prs2, UInt<1>(0h0)) node _T_29 = asUInt(reset) node _T_30 = eq(_T_29, UInt<1>(0h0)) when _T_30 : node _T_31 = eq(_T_28, UInt<1>(0h0)) when _T_31 : printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs2=x0!\n at issue-slot.scala:180 assert(next_uop.prs2 =/= 0.U, \"Poison bit can't be set for prs2=x0!\")\n") : printf_2 assert(clock, _T_28, UInt<1>(0h1), "") : assert_2 connect p2, UInt<1>(0h0) node _T_32 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs1) node _T_33 = and(io.wakeup_ports[0].valid, _T_32) when _T_33 : connect p1, UInt<1>(0h1) node _T_34 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs2) node _T_35 = and(io.wakeup_ports[0].valid, _T_34) when _T_35 : connect p2, UInt<1>(0h1) node _T_36 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs3) node _T_37 = and(io.wakeup_ports[0].valid, _T_36) when _T_37 : connect p3, UInt<1>(0h1) node _T_38 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs1) node _T_39 = and(io.wakeup_ports[1].valid, _T_38) when _T_39 : connect p1, UInt<1>(0h1) node _T_40 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs2) node _T_41 = and(io.wakeup_ports[1].valid, _T_40) when _T_41 : connect p2, UInt<1>(0h1) node _T_42 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs3) node _T_43 = and(io.wakeup_ports[1].valid, _T_42) when _T_43 : connect p3, UInt<1>(0h1) node _T_44 = eq(io.pred_wakeup_port.bits, next_uop.ppred) node _T_45 = and(io.pred_wakeup_port.valid, _T_44) when _T_45 : connect ppred, UInt<1>(0h1) node _T_46 = eq(io.spec_ld_wakeup[0].bits, UInt<1>(0h0)) node _T_47 = and(io.spec_ld_wakeup[0].valid, _T_46) node _T_48 = eq(_T_47, UInt<1>(0h0)) node _T_49 = asUInt(reset) node _T_50 = eq(_T_49, UInt<1>(0h0)) when _T_50 : node _T_51 = eq(_T_48, UInt<1>(0h0)) when _T_51 : printf(clock, UInt<1>(0h1), "Assertion failed: Loads to x0 should never speculatively wakeup other instructions\n at issue-slot.scala:203 assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U),\n") : printf_3 assert(clock, _T_48, UInt<1>(0h1), "") : assert_3 node _T_52 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs1) node _T_53 = and(io.spec_ld_wakeup[0].valid, _T_52) node _T_54 = eq(next_uop.lrs1_rtype, UInt<2>(0h0)) node _T_55 = and(_T_53, _T_54) when _T_55 : connect p1, UInt<1>(0h1) connect p1_poisoned, UInt<1>(0h1) node _T_56 = eq(next_p1_poisoned, UInt<1>(0h0)) node _T_57 = asUInt(reset) node _T_58 = eq(_T_57, UInt<1>(0h0)) when _T_58 : node _T_59 = eq(_T_56, UInt<1>(0h0)) when _T_59 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:214 assert (!next_p1_poisoned)\n") : printf_4 assert(clock, _T_56, UInt<1>(0h1), "") : assert_4 node _T_60 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs2) node _T_61 = and(io.spec_ld_wakeup[0].valid, _T_60) node _T_62 = eq(next_uop.lrs2_rtype, UInt<2>(0h0)) node _T_63 = and(_T_61, _T_62) when _T_63 : connect p2, UInt<1>(0h1) connect p2_poisoned, UInt<1>(0h1) node _T_64 = eq(next_p2_poisoned, UInt<1>(0h0)) node _T_65 = asUInt(reset) node _T_66 = eq(_T_65, UInt<1>(0h0)) when _T_66 : node _T_67 = eq(_T_64, UInt<1>(0h0)) when _T_67 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:221 assert (!next_p2_poisoned)\n") : printf_5 assert(clock, _T_64, UInt<1>(0h1), "") : assert_5 node _next_br_mask_T = not(io.brupdate.b1.resolve_mask) node next_br_mask = and(slot_uop.br_mask, _next_br_mask_T) node _T_68 = and(io.brupdate.b1.mispredict_mask, slot_uop.br_mask) node _T_69 = neq(_T_68, UInt<1>(0h0)) when _T_69 : connect next_state, UInt<2>(0h0) node _T_70 = eq(io.in_uop.valid, UInt<1>(0h0)) when _T_70 : connect slot_uop.br_mask, next_br_mask node _io_request_T = neq(state, UInt<2>(0h0)) node _io_request_T_1 = and(_io_request_T, p1) node _io_request_T_2 = and(_io_request_T_1, p2) node _io_request_T_3 = and(_io_request_T_2, p3) node _io_request_T_4 = and(_io_request_T_3, ppred) node _io_request_T_5 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_6 = and(_io_request_T_4, _io_request_T_5) connect io.request, _io_request_T_6 node _high_priority_T = or(slot_uop.is_br, slot_uop.is_jal) node high_priority = or(_high_priority_T, slot_uop.is_jalr) node _io_request_hp_T = and(io.request, high_priority) connect io.request_hp, _io_request_hp_T node _T_71 = eq(state, UInt<2>(0h1)) when _T_71 : node _io_request_T_7 = and(p1, p2) node _io_request_T_8 = and(_io_request_T_7, p3) node _io_request_T_9 = and(_io_request_T_8, ppred) node _io_request_T_10 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_11 = and(_io_request_T_9, _io_request_T_10) connect io.request, _io_request_T_11 else : node _T_72 = eq(state, UInt<2>(0h2)) when _T_72 : node _io_request_T_12 = or(p1, p2) node _io_request_T_13 = and(_io_request_T_12, ppred) node _io_request_T_14 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_15 = and(_io_request_T_13, _io_request_T_14) connect io.request, _io_request_T_15 else : connect io.request, UInt<1>(0h0) node _io_valid_T = neq(state, UInt<2>(0h0)) connect io.valid, _io_valid_T connect io.uop, slot_uop connect io.uop.iw_p1_poisoned, p1_poisoned connect io.uop.iw_p2_poisoned, p2_poisoned node _may_vacate_T = eq(state, UInt<2>(0h1)) node _may_vacate_T_1 = eq(state, UInt<2>(0h2)) node _may_vacate_T_2 = and(_may_vacate_T_1, p1) node _may_vacate_T_3 = and(_may_vacate_T_2, p2) node _may_vacate_T_4 = and(_may_vacate_T_3, ppred) node _may_vacate_T_5 = or(_may_vacate_T, _may_vacate_T_4) node may_vacate = and(io.grant, _may_vacate_T_5) node _squash_grant_T = or(p1_poisoned, p2_poisoned) node squash_grant = and(io.ldspec_miss, _squash_grant_T) node _io_will_be_valid_T = neq(state, UInt<2>(0h0)) node _io_will_be_valid_T_1 = eq(squash_grant, UInt<1>(0h0)) node _io_will_be_valid_T_2 = and(may_vacate, _io_will_be_valid_T_1) node _io_will_be_valid_T_3 = eq(_io_will_be_valid_T_2, UInt<1>(0h0)) node _io_will_be_valid_T_4 = and(_io_will_be_valid_T, _io_will_be_valid_T_3) connect io.will_be_valid, _io_will_be_valid_T_4 connect io.out_uop, slot_uop connect io.out_uop.iw_state, next_state connect io.out_uop.uopc, next_uopc connect io.out_uop.lrs1_rtype, next_lrs1_rtype connect io.out_uop.lrs2_rtype, next_lrs2_rtype connect io.out_uop.br_mask, next_br_mask node _io_out_uop_prs1_busy_T = eq(p1, UInt<1>(0h0)) connect io.out_uop.prs1_busy, _io_out_uop_prs1_busy_T node _io_out_uop_prs2_busy_T = eq(p2, UInt<1>(0h0)) connect io.out_uop.prs2_busy, _io_out_uop_prs2_busy_T node _io_out_uop_prs3_busy_T = eq(p3, UInt<1>(0h0)) connect io.out_uop.prs3_busy, _io_out_uop_prs3_busy_T node _io_out_uop_ppred_busy_T = eq(ppred, UInt<1>(0h0)) connect io.out_uop.ppred_busy, _io_out_uop_ppred_busy_T connect io.out_uop.iw_p1_poisoned, p1_poisoned connect io.out_uop.iw_p2_poisoned, p2_poisoned node _T_73 = eq(state, UInt<2>(0h2)) when _T_73 : node _T_74 = and(p1, p2) node _T_75 = and(_T_74, ppred) when _T_75 : skip else : node _T_76 = and(p1, ppred) when _T_76 : connect io.uop.uopc, slot_uop.uopc connect io.uop.lrs2_rtype, UInt<2>(0h2) else : node _T_77 = and(p2, ppred) when _T_77 : connect io.uop.uopc, UInt<7>(0h3) connect io.uop.lrs1_rtype, UInt<2>(0h2) connect io.debug.p1, p1 connect io.debug.p2, p2 connect io.debug.p3, p3 connect io.debug.ppred, ppred connect io.debug.state, state	module IssueSlot_5( // @[issue-slot.scala:69:7] input clock, // @[issue-slot.scala:69:7] input reset, // @[issue-slot.scala:69:7] output io_valid, // @[issue-slot.scala:73:14] output io_will_be_valid, // @[issue-slot.scala:73:14] output io_request, // @[issue-slot.scala:73:14] output io_request_hp, // @[issue-slot.scala:73:14] input io_grant, // @[issue-slot.scala:73:14] input [7:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14] input [7:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14] input [7:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14] input io_brupdate_b2_valid, // @[issue-slot.scala:73:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14] input io_brupdate_b2_taken, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14] input io_kill, // @[issue-slot.scala:73:14] input io_clear, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14] input [5:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14] input [5:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14] input io_in_uop_valid, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14] input [7:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14] input io_in_uop_bits_taken, // @[issue-slot.scala:73:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ppred, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14] input io_in_uop_bits_exception, // @[issue-slot.scala:73:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14] input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14] output io_out_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14] output io_out_uop_is_br, // @[issue-slot.scala:73:14] output io_out_uop_is_jalr, // @[issue-slot.scala:73:14] output io_out_uop_is_jal, // @[issue-slot.scala:73:14] output io_out_uop_is_sfb, // @[issue-slot.scala:73:14] output [7:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_out_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14] output io_out_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_pdst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_prs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_prs2, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_prs3, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ppred, // @[issue-slot.scala:73:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_out_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14] output io_out_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14] output io_out_uop_mem_signed, // @[issue-slot.scala:73:14] output io_out_uop_is_fence, // @[issue-slot.scala:73:14] output io_out_uop_is_fencei, // @[issue-slot.scala:73:14] output io_out_uop_is_amo, // @[issue-slot.scala:73:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_out_uop_uses_stq, // @[issue-slot.scala:73:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_out_uop_is_unique, // @[issue-slot.scala:73:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14] output io_out_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_out_uop_frs3_en, // @[issue-slot.scala:73:14] output io_out_uop_fp_val, // @[issue-slot.scala:73:14] output io_out_uop_fp_single, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14] output io_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14] output io_uop_is_br, // @[issue-slot.scala:73:14] output io_uop_is_jalr, // @[issue-slot.scala:73:14] output io_uop_is_jal, // @[issue-slot.scala:73:14] output io_uop_is_sfb, // @[issue-slot.scala:73:14] output [7:0] io_uop_br_mask, // @[issue-slot.scala:73:14] output [2:0] io_uop_br_tag, // @[issue-slot.scala:73:14] output [3:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14] output io_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14] output [4:0] io_uop_rob_idx, // @[issue-slot.scala:73:14] output [2:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14] output [2:0] io_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14] output [5:0] io_uop_pdst, // @[issue-slot.scala:73:14] output [5:0] io_uop_prs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_prs2, // @[issue-slot.scala:73:14] output [5:0] io_uop_prs3, // @[issue-slot.scala:73:14] output [3:0] io_uop_ppred, // @[issue-slot.scala:73:14] output io_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_uop_ppred_busy, // @[issue-slot.scala:73:14] output [5:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14] output io_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14] output io_uop_mem_signed, // @[issue-slot.scala:73:14] output io_uop_is_fence, // @[issue-slot.scala:73:14] output io_uop_is_fencei, // @[issue-slot.scala:73:14] output io_uop_is_amo, // @[issue-slot.scala:73:14] output io_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_uop_uses_stq, // @[issue-slot.scala:73:14] output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_uop_is_unique, // @[issue-slot.scala:73:14] output io_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14] output io_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_uop_frs3_en, // @[issue-slot.scala:73:14] output io_uop_fp_val, // @[issue-slot.scala:73:14] output io_uop_fp_single, // @[issue-slot.scala:73:14] output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14] output io_debug_p1, // @[issue-slot.scala:73:14] output io_debug_p2, // @[issue-slot.scala:73:14] output io_debug_p3, // @[issue-slot.scala:73:14] output io_debug_ppred, // @[issue-slot.scala:73:14] output [1:0] io_debug_state // @[issue-slot.scala:73:14] ); wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7] wire [7:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7] wire [7:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7] wire [7:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7] wire [5:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7] wire [5:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7] wire [7:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7] wire io_ldspec_miss = 1'h0; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_bits_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_bits_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7] wire io_spec_ld_wakeup_0_valid = 1'h0; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_uop_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_uop_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire next_p1_poisoned = 1'h0; // @[issue-slot.scala:99:29] wire next_p2_poisoned = 1'h0; // @[issue-slot.scala:100:29] wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire _squash_grant_T = 1'h0; // @[issue-slot.scala:261:53] wire squash_grant = 1'h0; // @[issue-slot.scala:261:37] wire [3:0] io_pred_wakeup_port_bits = 4'h0; // @[issue-slot.scala:69:7] wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_uop_ftq_idx = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_uop_ppred = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [5:0] io_spec_ld_wakeup_0_bits = 6'h0; // @[issue-slot.scala:69:7] wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_pdst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_prs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_prs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_prs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_stale_pdst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire _io_will_be_valid_T_1 = 1'h1; // @[issue-slot.scala:262:51] wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_br_tag = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ldq_idx = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_stq_idx = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_rob_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [7:0] slot_uop_uop_br_mask = 8'h0; // @[consts.scala:269:19] wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire _io_valid_T; // @[issue-slot.scala:79:24] wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32] wire _io_request_hp_T; // @[issue-slot.scala:243:31] wire [6:0] next_uopc; // @[issue-slot.scala:82:29] wire [1:0] next_state; // @[issue-slot.scala:81:29] wire [7:0] next_br_mask; // @[util.scala:85:25] wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28] wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28] wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28] wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28] wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29] wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29] wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [7:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [3:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_out_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7] wire [3:0] io_out_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_out_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [7:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_pdst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_prs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_prs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_prs3_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire io_debug_p1_0; // @[issue-slot.scala:69:7] wire io_debug_p2_0; // @[issue-slot.scala:69:7] wire io_debug_p3_0; // @[issue-slot.scala:69:7] wire io_debug_ppred_0; // @[issue-slot.scala:69:7] wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7] wire io_valid_0; // @[issue-slot.scala:69:7] wire io_will_be_valid_0; // @[issue-slot.scala:69:7] wire io_request_0; // @[issue-slot.scala:69:7] wire io_request_hp_0; // @[issue-slot.scala:69:7] assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29] assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29] assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29] assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29] reg [1:0] state; // @[issue-slot.scala:86:22] assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22] reg p1; // @[issue-slot.scala:87:22] assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22] wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25] reg p2; // @[issue-slot.scala:88:22] assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22] wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25] reg p3; // @[issue-slot.scala:89:22] assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22] wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25] reg ppred; // @[issue-slot.scala:90:22] assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22] wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28] reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25] reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25] assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25] assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_rvc; // @[issue-slot.scala:102:25] assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25] assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25] assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25] assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_iw_p1_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_iw_p2_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_is_br; // @[issue-slot.scala:102:25] assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jalr; // @[issue-slot.scala:102:25] assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jal; // @[issue-slot.scala:102:25] assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sfb; // @[issue-slot.scala:102:25] assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] reg [7:0] slot_uop_br_mask; // @[issue-slot.scala:102:25] assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_br_tag; // @[issue-slot.scala:102:25] assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_edge_inst; // @[issue-slot.scala:102:25] assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25] assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_taken; // @[issue-slot.scala:102:25] assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25] assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25] assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_prs1; // @[issue-slot.scala:102:25] assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_prs2; // @[issue-slot.scala:102:25] assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_prs3; // @[issue-slot.scala:102:25] assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ppred; // @[issue-slot.scala:102:25] assign io_out_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25] assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25] assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs3_busy; // @[issue-slot.scala:102:25] assign io_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ppred_busy; // @[issue-slot.scala:102:25] assign io_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_exception; // @[issue-slot.scala:102:25] assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25] assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bypassable; // @[issue-slot.scala:102:25] assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25] assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_mem_signed; // @[issue-slot.scala:102:25] assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fence; // @[issue-slot.scala:102:25] assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fencei; // @[issue-slot.scala:102:25] assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_amo; // @[issue-slot.scala:102:25] assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_stq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25] assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_unique; // @[issue-slot.scala:102:25] assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25] assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25] assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25] assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25] assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_val; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25] assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25] reg slot_uop_frs3_en; // @[issue-slot.scala:102:25] assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_val; // @[issue-slot.scala:102:25] assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_single; // @[issue-slot.scala:102:25] assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p1_poisoned = ~io_in_uop_valid_0 & slot_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p2_poisoned = ~io_in_uop_valid_0 & slot_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [7:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ppred = io_in_uop_valid_0 ? io_in_uop_bits_ppred_0 : slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs3_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs3_busy_0 : slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ppred_busy = io_in_uop_valid_0 ? io_in_uop_bits_ppred_busy_0 : slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25] wire _T_7 = io_grant_0 & state == 2'h1 \| io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}] wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25] wire _GEN = io_kill_0 \| _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51] wire _GEN_0 = _GEN \| ~(_T_12 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:62, :142:17, :143:23] assign next_uopc = _GEN_0 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51] assign next_lrs1_rtype = _GEN_0 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51] wire _GEN_1 = _GEN \| ~_T_12 \| p1; // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:62, :142:17] assign next_lrs2_rtype = _GEN_1 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17]
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_42 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T node _is_aligned_mask_T = dshl(UInt<2>(0h3), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 1, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<2>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 0, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 1, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h2)) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(UInt<1>(0h1), mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(UInt<1>(0h1), mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_lo = cat(mask_acc_1, mask_acc) node mask_hi = cat(mask_acc_3, mask_acc_2) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_15 : node _T_16 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_17 = and(UInt<1>(0h0), _T_16) node _T_18 = or(UInt<1>(0h0), _T_17) node _T_19 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_20 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_21 = cvt(_T_20) node _T_22 = and(_T_21, asSInt(UInt<7>(0h40))) node _T_23 = asSInt(_T_22) node _T_24 = eq(_T_23, asSInt(UInt<1>(0h0))) node _T_25 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_26 = cvt(_T_25) node _T_27 = and(_T_26, asSInt(UInt<5>(0h14))) node _T_28 = asSInt(_T_27) node _T_29 = eq(_T_28, asSInt(UInt<1>(0h0))) node _T_30 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_31 = cvt(_T_30) node _T_32 = and(_T_31, asSInt(UInt<4>(0h8))) node _T_33 = asSInt(_T_32) node _T_34 = eq(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_36 = cvt(_T_35) node _T_37 = and(_T_36, asSInt(UInt<6>(0h20))) node _T_38 = asSInt(_T_37) node _T_39 = eq(_T_38, asSInt(UInt<1>(0h0))) node _T_40 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_41 = cvt(_T_40) node _T_42 = and(_T_41, asSInt(UInt<8>(0h80))) node _T_43 = asSInt(_T_42) node _T_44 = eq(_T_43, asSInt(UInt<1>(0h0))) node _T_45 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<9>(0h100))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_24, _T_29) node _T_51 = or(_T_50, _T_34) node _T_52 = or(_T_51, _T_39) node _T_53 = or(_T_52, _T_44) node _T_54 = or(_T_53, _T_49) node _T_55 = and(_T_19, _T_54) node _T_56 = or(UInt<1>(0h0), _T_55) node _T_57 = and(_T_18, _T_56) node _T_58 = asUInt(reset) node _T_59 = eq(_T_58, UInt<1>(0h0)) when _T_59 : node _T_60 = eq(_T_57, UInt<1>(0h0)) when _T_60 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_57, UInt<1>(0h1), "") : assert_2 node _T_61 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_62 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_63 = and(_T_61, _T_62) node _T_64 = or(UInt<1>(0h0), _T_63) node _T_65 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_66 = cvt(_T_65) node _T_67 = and(_T_66, asSInt(UInt<7>(0h40))) node _T_68 = asSInt(_T_67) node _T_69 = eq(_T_68, asSInt(UInt<1>(0h0))) node _T_70 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_71 = cvt(_T_70) node _T_72 = and(_T_71, asSInt(UInt<5>(0h14))) node _T_73 = asSInt(_T_72) node _T_74 = eq(_T_73, asSInt(UInt<1>(0h0))) node _T_75 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_76 = cvt(_T_75) node _T_77 = and(_T_76, asSInt(UInt<4>(0h8))) node _T_78 = asSInt(_T_77) node _T_79 = eq(_T_78, asSInt(UInt<1>(0h0))) node _T_80 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_81 = cvt(_T_80) node _T_82 = and(_T_81, asSInt(UInt<6>(0h20))) node _T_83 = asSInt(_T_82) node _T_84 = eq(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_86 = cvt(_T_85) node _T_87 = and(_T_86, asSInt(UInt<8>(0h80))) node _T_88 = asSInt(_T_87) node _T_89 = eq(_T_88, asSInt(UInt<1>(0h0))) node _T_90 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<9>(0h100))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_69, _T_74) node _T_96 = or(_T_95, _T_79) node _T_97 = or(_T_96, _T_84) node _T_98 = or(_T_97, _T_89) node _T_99 = or(_T_98, _T_94) node _T_100 = and(_T_64, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(UInt<1>(0h0), _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_102, UInt<1>(0h1), "") : assert_3 node _T_106 = asUInt(reset) node _T_107 = eq(_T_106, UInt<1>(0h0)) when _T_107 : node _T_108 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_108 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_109 = geq(io.in.a.bits.size, UInt<2>(0h2)) node _T_110 = asUInt(reset) node _T_111 = eq(_T_110, UInt<1>(0h0)) when _T_111 : node _T_112 = eq(_T_109, UInt<1>(0h0)) when _T_112 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_109, UInt<1>(0h1), "") : assert_5 node _T_113 = asUInt(reset) node _T_114 = eq(_T_113, UInt<1>(0h0)) when _T_114 : node _T_115 = eq(is_aligned, UInt<1>(0h0)) when _T_115 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_116 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_117 = asUInt(reset) node _T_118 = eq(_T_117, UInt<1>(0h0)) when _T_118 : node _T_119 = eq(_T_116, UInt<1>(0h0)) when _T_119 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_116, UInt<1>(0h1), "") : assert_7 node _T_120 = not(io.in.a.bits.mask) node _T_121 = eq(_T_120, UInt<1>(0h0)) node _T_122 = asUInt(reset) node _T_123 = eq(_T_122, UInt<1>(0h0)) when _T_123 : node _T_124 = eq(_T_121, UInt<1>(0h0)) when _T_124 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_121, UInt<1>(0h1), "") : assert_8 node _T_125 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_126 = asUInt(reset) node _T_127 = eq(_T_126, UInt<1>(0h0)) when _T_127 : node _T_128 = eq(_T_125, UInt<1>(0h0)) when _T_128 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_125, UInt<1>(0h1), "") : assert_9 node _T_129 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_129 : node _T_130 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_131 = and(UInt<1>(0h0), _T_130) node _T_132 = or(UInt<1>(0h0), _T_131) node _T_133 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_134 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_135 = cvt(_T_134) node _T_136 = and(_T_135, asSInt(UInt<7>(0h40))) node _T_137 = asSInt(_T_136) node _T_138 = eq(_T_137, asSInt(UInt<1>(0h0))) node _T_139 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_140 = cvt(_T_139) node _T_141 = and(_T_140, asSInt(UInt<5>(0h14))) node _T_142 = asSInt(_T_141) node _T_143 = eq(_T_142, asSInt(UInt<1>(0h0))) node _T_144 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_145 = cvt(_T_144) node _T_146 = and(_T_145, asSInt(UInt<4>(0h8))) node _T_147 = asSInt(_T_146) node _T_148 = eq(_T_147, asSInt(UInt<1>(0h0))) node _T_149 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_150 = cvt(_T_149) node _T_151 = and(_T_150, asSInt(UInt<6>(0h20))) node _T_152 = asSInt(_T_151) node _T_153 = eq(_T_152, asSInt(UInt<1>(0h0))) node _T_154 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_155 = cvt(_T_154) node _T_156 = and(_T_155, asSInt(UInt<8>(0h80))) node _T_157 = asSInt(_T_156) node _T_158 = eq(_T_157, asSInt(UInt<1>(0h0))) node _T_159 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_160 = cvt(_T_159) node _T_161 = and(_T_160, asSInt(UInt<9>(0h100))) node _T_162 = asSInt(_T_161) node _T_163 = eq(_T_162, asSInt(UInt<1>(0h0))) node _T_164 = or(_T_138, _T_143) node _T_165 = or(_T_164, _T_148) node _T_166 = or(_T_165, _T_153) node _T_167 = or(_T_166, _T_158) node _T_168 = or(_T_167, _T_163) node _T_169 = and(_T_133, _T_168) node _T_170 = or(UInt<1>(0h0), _T_169) node _T_171 = and(_T_132, _T_170) node _T_172 = asUInt(reset) node _T_173 = eq(_T_172, UInt<1>(0h0)) when _T_173 : node _T_174 = eq(_T_171, UInt<1>(0h0)) when _T_174 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_171, UInt<1>(0h1), "") : assert_10 node _T_175 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_176 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_177 = and(_T_175, _T_176) node _T_178 = or(UInt<1>(0h0), _T_177) node _T_179 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_180 = cvt(_T_179) node _T_181 = and(_T_180, asSInt(UInt<7>(0h40))) node _T_182 = asSInt(_T_181) node _T_183 = eq(_T_182, asSInt(UInt<1>(0h0))) node _T_184 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_185 = cvt(_T_184) node _T_186 = and(_T_185, asSInt(UInt<5>(0h14))) node _T_187 = asSInt(_T_186) node _T_188 = eq(_T_187, asSInt(UInt<1>(0h0))) node _T_189 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_190 = cvt(_T_189) node _T_191 = and(_T_190, asSInt(UInt<4>(0h8))) node _T_192 = asSInt(_T_191) node _T_193 = eq(_T_192, asSInt(UInt<1>(0h0))) node _T_194 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_195 = cvt(_T_194) node _T_196 = and(_T_195, asSInt(UInt<6>(0h20))) node _T_197 = asSInt(_T_196) node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0))) node _T_199 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_200 = cvt(_T_199) node _T_201 = and(_T_200, asSInt(UInt<8>(0h80))) node _T_202 = asSInt(_T_201) node _T_203 = eq(_T_202, asSInt(UInt<1>(0h0))) node _T_204 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_205 = cvt(_T_204) node _T_206 = and(_T_205, asSInt(UInt<9>(0h100))) node _T_207 = asSInt(_T_206) node _T_208 = eq(_T_207, asSInt(UInt<1>(0h0))) node _T_209 = or(_T_183, _T_188) node _T_210 = or(_T_209, _T_193) node _T_211 = or(_T_210, _T_198) node _T_212 = or(_T_211, _T_203) node _T_213 = or(_T_212, _T_208) node _T_214 = and(_T_178, _T_213) node _T_215 = or(UInt<1>(0h0), _T_214) node _T_216 = and(UInt<1>(0h0), _T_215) node _T_217 = asUInt(reset) node _T_218 = eq(_T_217, UInt<1>(0h0)) when _T_218 : node _T_219 = eq(_T_216, UInt<1>(0h0)) when _T_219 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_216, UInt<1>(0h1), "") : assert_11 node _T_220 = asUInt(reset) node _T_221 = eq(_T_220, UInt<1>(0h0)) when _T_221 : node _T_222 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_222 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_223 = geq(io.in.a.bits.size, UInt<2>(0h2)) node _T_224 = asUInt(reset) node _T_225 = eq(_T_224, UInt<1>(0h0)) when _T_225 : node _T_226 = eq(_T_223, UInt<1>(0h0)) when _T_226 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_223, UInt<1>(0h1), "") : assert_13 node _T_227 = asUInt(reset) node _T_228 = eq(_T_227, UInt<1>(0h0)) when _T_228 : node _T_229 = eq(is_aligned, UInt<1>(0h0)) when _T_229 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_230 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_231 = asUInt(reset) node _T_232 = eq(_T_231, UInt<1>(0h0)) when _T_232 : node _T_233 = eq(_T_230, UInt<1>(0h0)) when _T_233 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_230, UInt<1>(0h1), "") : assert_15 node _T_234 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_235 = asUInt(reset) node _T_236 = eq(_T_235, UInt<1>(0h0)) when _T_236 : node _T_237 = eq(_T_234, UInt<1>(0h0)) when _T_237 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_234, UInt<1>(0h1), "") : assert_16 node _T_238 = not(io.in.a.bits.mask) node _T_239 = eq(_T_238, UInt<1>(0h0)) node _T_240 = asUInt(reset) node _T_241 = eq(_T_240, UInt<1>(0h0)) when _T_241 : node _T_242 = eq(_T_239, UInt<1>(0h0)) when _T_242 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_239, UInt<1>(0h1), "") : assert_17 node _T_243 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_244 = asUInt(reset) node _T_245 = eq(_T_244, UInt<1>(0h0)) when _T_245 : node _T_246 = eq(_T_243, UInt<1>(0h0)) when _T_246 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_243, UInt<1>(0h1), "") : assert_18 node _T_247 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_247 : node _T_248 = eq(UInt<2>(0h2), io.in.a.bits.size) node _T_249 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = asUInt(reset) node _T_253 = eq(_T_252, UInt<1>(0h0)) when _T_253 : node _T_254 = eq(_T_251, UInt<1>(0h0)) when _T_254 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_251, UInt<1>(0h1), "") : assert_19 node _T_255 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_256 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_257 = and(_T_255, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_260 = cvt(_T_259) node _T_261 = and(_T_260, asSInt(UInt<7>(0h40))) node _T_262 = asSInt(_T_261) node _T_263 = eq(_T_262, asSInt(UInt<1>(0h0))) node _T_264 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_265 = cvt(_T_264) node _T_266 = and(_T_265, asSInt(UInt<5>(0h14))) node _T_267 = asSInt(_T_266) node _T_268 = eq(_T_267, asSInt(UInt<1>(0h0))) node _T_269 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_270 = cvt(_T_269) node _T_271 = and(_T_270, asSInt(UInt<4>(0h8))) node _T_272 = asSInt(_T_271) node _T_273 = eq(_T_272, asSInt(UInt<1>(0h0))) node _T_274 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_275 = cvt(_T_274) node _T_276 = and(_T_275, asSInt(UInt<6>(0h20))) node _T_277 = asSInt(_T_276) node _T_278 = eq(_T_277, asSInt(UInt<1>(0h0))) node _T_279 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_280 = cvt(_T_279) node _T_281 = and(_T_280, asSInt(UInt<8>(0h80))) node _T_282 = asSInt(_T_281) node _T_283 = eq(_T_282, asSInt(UInt<1>(0h0))) node _T_284 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_285 = cvt(_T_284) node _T_286 = and(_T_285, asSInt(UInt<9>(0h100))) node _T_287 = asSInt(_T_286) node _T_288 = eq(_T_287, asSInt(UInt<1>(0h0))) node _T_289 = or(_T_263, _T_268) node _T_290 = or(_T_289, _T_273) node _T_291 = or(_T_290, _T_278) node _T_292 = or(_T_291, _T_283) node _T_293 = or(_T_292, _T_288) node _T_294 = and(_T_258, _T_293) node _T_295 = or(UInt<1>(0h0), _T_294) node _T_296 = asUInt(reset) node _T_297 = eq(_T_296, UInt<1>(0h0)) when _T_297 : node _T_298 = eq(_T_295, UInt<1>(0h0)) when _T_298 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_295, UInt<1>(0h1), "") : assert_20 node _T_299 = asUInt(reset) node _T_300 = eq(_T_299, UInt<1>(0h0)) when _T_300 : node _T_301 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_301 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_302 = asUInt(reset) node _T_303 = eq(_T_302, UInt<1>(0h0)) when _T_303 : node _T_304 = eq(is_aligned, UInt<1>(0h0)) when _T_304 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_305 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(_T_305, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_305, UInt<1>(0h1), "") : assert_23 node _T_309 = eq(io.in.a.bits.mask, mask) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_309, UInt<1>(0h1), "") : assert_24 node _T_313 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_313, UInt<1>(0h1), "") : assert_25 node _T_317 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_317 : node _T_318 = eq(UInt<2>(0h2), io.in.a.bits.size) node _T_319 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_320 = and(_T_318, _T_319) node _T_321 = or(UInt<1>(0h0), _T_320) node _T_322 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_323 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_324 = and(_T_322, _T_323) node _T_325 = or(UInt<1>(0h0), _T_324) node _T_326 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_327 = cvt(_T_326) node _T_328 = and(_T_327, asSInt(UInt<7>(0h40))) node _T_329 = asSInt(_T_328) node _T_330 = eq(_T_329, asSInt(UInt<1>(0h0))) node _T_331 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_332 = cvt(_T_331) node _T_333 = and(_T_332, asSInt(UInt<5>(0h14))) node _T_334 = asSInt(_T_333) node _T_335 = eq(_T_334, asSInt(UInt<1>(0h0))) node _T_336 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_337 = cvt(_T_336) node _T_338 = and(_T_337, asSInt(UInt<4>(0h8))) node _T_339 = asSInt(_T_338) node _T_340 = eq(_T_339, asSInt(UInt<1>(0h0))) node _T_341 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_342 = cvt(_T_341) node _T_343 = and(_T_342, asSInt(UInt<6>(0h20))) node _T_344 = asSInt(_T_343) node _T_345 = eq(_T_344, asSInt(UInt<1>(0h0))) node _T_346 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_347 = cvt(_T_346) node _T_348 = and(_T_347, asSInt(UInt<8>(0h80))) node _T_349 = asSInt(_T_348) node _T_350 = eq(_T_349, asSInt(UInt<1>(0h0))) node _T_351 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_352 = cvt(_T_351) node _T_353 = and(_T_352, asSInt(UInt<9>(0h100))) node _T_354 = asSInt(_T_353) node _T_355 = eq(_T_354, asSInt(UInt<1>(0h0))) node _T_356 = or(_T_330, _T_335) node _T_357 = or(_T_356, _T_340) node _T_358 = or(_T_357, _T_345) node _T_359 = or(_T_358, _T_350) node _T_360 = or(_T_359, _T_355) node _T_361 = and(_T_325, _T_360) node _T_362 = or(UInt<1>(0h0), _T_361) node _T_363 = and(_T_321, _T_362) node _T_364 = asUInt(reset) node _T_365 = eq(_T_364, UInt<1>(0h0)) when _T_365 : node _T_366 = eq(_T_363, UInt<1>(0h0)) when _T_366 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_363, UInt<1>(0h1), "") : assert_26 node _T_367 = asUInt(reset) node _T_368 = eq(_T_367, UInt<1>(0h0)) when _T_368 : node _T_369 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_369 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_370 = asUInt(reset) node _T_371 = eq(_T_370, UInt<1>(0h0)) when _T_371 : node _T_372 = eq(is_aligned, UInt<1>(0h0)) when _T_372 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_373 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_374 = asUInt(reset) node _T_375 = eq(_T_374, UInt<1>(0h0)) when _T_375 : node _T_376 = eq(_T_373, UInt<1>(0h0)) when _T_376 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_373, UInt<1>(0h1), "") : assert_29 node _T_377 = eq(io.in.a.bits.mask, mask) node _T_378 = asUInt(reset) node _T_379 = eq(_T_378, UInt<1>(0h0)) when _T_379 : node _T_380 = eq(_T_377, UInt<1>(0h0)) when _T_380 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_377, UInt<1>(0h1), "") : assert_30 node _T_381 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_381 : node _T_382 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_383 = and(UInt<1>(0h0), _T_382) node _T_384 = or(UInt<1>(0h0), _T_383) node _T_385 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_386 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_387 = and(_T_385, _T_386) node _T_388 = or(UInt<1>(0h0), _T_387) node _T_389 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_390 = cvt(_T_389) node _T_391 = and(_T_390, asSInt(UInt<7>(0h40))) node _T_392 = asSInt(_T_391) node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0))) node _T_394 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_395 = cvt(_T_394) node _T_396 = and(_T_395, asSInt(UInt<5>(0h14))) node _T_397 = asSInt(_T_396) node _T_398 = eq(_T_397, asSInt(UInt<1>(0h0))) node _T_399 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_400 = cvt(_T_399) node _T_401 = and(_T_400, asSInt(UInt<4>(0h8))) node _T_402 = asSInt(_T_401) node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0))) node _T_404 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_405 = cvt(_T_404) node _T_406 = and(_T_405, asSInt(UInt<6>(0h20))) node _T_407 = asSInt(_T_406) node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0))) node _T_409 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_410 = cvt(_T_409) node _T_411 = and(_T_410, asSInt(UInt<8>(0h80))) node _T_412 = asSInt(_T_411) node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0))) node _T_414 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_415 = cvt(_T_414) node _T_416 = and(_T_415, asSInt(UInt<9>(0h100))) node _T_417 = asSInt(_T_416) node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0))) node _T_419 = or(_T_393, _T_398) node _T_420 = or(_T_419, _T_403) node _T_421 = or(_T_420, _T_408) node _T_422 = or(_T_421, _T_413) node _T_423 = or(_T_422, _T_418) node _T_424 = and(_T_388, _T_423) node _T_425 = or(UInt<1>(0h0), _T_424) node _T_426 = and(_T_384, _T_425) node _T_427 = asUInt(reset) node _T_428 = eq(_T_427, UInt<1>(0h0)) when _T_428 : node _T_429 = eq(_T_426, UInt<1>(0h0)) when _T_429 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_426, UInt<1>(0h1), "") : assert_31 node _T_430 = asUInt(reset) node _T_431 = eq(_T_430, UInt<1>(0h0)) when _T_431 : node _T_432 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_432 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(is_aligned, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_436 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_436, UInt<1>(0h1), "") : assert_34 node _T_440 = not(mask) node _T_441 = and(io.in.a.bits.mask, _T_440) node _T_442 = eq(_T_441, UInt<1>(0h0)) node _T_443 = asUInt(reset) node _T_444 = eq(_T_443, UInt<1>(0h0)) when _T_444 : node _T_445 = eq(_T_442, UInt<1>(0h0)) when _T_445 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_442, UInt<1>(0h1), "") : assert_35 node _T_446 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_446 : node _T_447 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_448 = and(UInt<1>(0h0), _T_447) node _T_449 = or(UInt<1>(0h0), _T_448) node _T_450 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_451 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_452 = cvt(_T_451) node _T_453 = and(_T_452, asSInt(UInt<7>(0h40))) node _T_454 = asSInt(_T_453) node _T_455 = eq(_T_454, asSInt(UInt<1>(0h0))) node _T_456 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_457 = cvt(_T_456) node _T_458 = and(_T_457, asSInt(UInt<5>(0h14))) node _T_459 = asSInt(_T_458) node _T_460 = eq(_T_459, asSInt(UInt<1>(0h0))) node _T_461 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_462 = cvt(_T_461) node _T_463 = and(_T_462, asSInt(UInt<4>(0h8))) node _T_464 = asSInt(_T_463) node _T_465 = eq(_T_464, asSInt(UInt<1>(0h0))) node _T_466 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_467 = cvt(_T_466) node _T_468 = and(_T_467, asSInt(UInt<6>(0h20))) node _T_469 = asSInt(_T_468) node _T_470 = eq(_T_469, asSInt(UInt<1>(0h0))) node _T_471 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_472 = cvt(_T_471) node _T_473 = and(_T_472, asSInt(UInt<8>(0h80))) node _T_474 = asSInt(_T_473) node _T_475 = eq(_T_474, asSInt(UInt<1>(0h0))) node _T_476 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_477 = cvt(_T_476) node _T_478 = and(_T_477, asSInt(UInt<9>(0h100))) node _T_479 = asSInt(_T_478) node _T_480 = eq(_T_479, asSInt(UInt<1>(0h0))) node _T_481 = or(_T_455, _T_460) node _T_482 = or(_T_481, _T_465) node _T_483 = or(_T_482, _T_470) node _T_484 = or(_T_483, _T_475) node _T_485 = or(_T_484, _T_480) node _T_486 = and(_T_450, _T_485) node _T_487 = or(UInt<1>(0h0), _T_486) node _T_488 = and(_T_449, _T_487) node _T_489 = asUInt(reset) node _T_490 = eq(_T_489, UInt<1>(0h0)) when _T_490 : node _T_491 = eq(_T_488, UInt<1>(0h0)) when _T_491 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_488, UInt<1>(0h1), "") : assert_36 node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_495 = asUInt(reset) node _T_496 = eq(_T_495, UInt<1>(0h0)) when _T_496 : node _T_497 = eq(is_aligned, UInt<1>(0h0)) when _T_497 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_498 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_499 = asUInt(reset) node _T_500 = eq(_T_499, UInt<1>(0h0)) when _T_500 : node _T_501 = eq(_T_498, UInt<1>(0h0)) when _T_501 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_498, UInt<1>(0h1), "") : assert_39 node _T_502 = eq(io.in.a.bits.mask, mask) node _T_503 = asUInt(reset) node _T_504 = eq(_T_503, UInt<1>(0h0)) when _T_504 : node _T_505 = eq(_T_502, UInt<1>(0h0)) when _T_505 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_502, UInt<1>(0h1), "") : assert_40 node _T_506 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_506 : node _T_507 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_508 = and(UInt<1>(0h0), _T_507) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_511 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_512 = cvt(_T_511) node _T_513 = and(_T_512, asSInt(UInt<7>(0h40))) node _T_514 = asSInt(_T_513) node _T_515 = eq(_T_514, asSInt(UInt<1>(0h0))) node _T_516 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_517 = cvt(_T_516) node _T_518 = and(_T_517, asSInt(UInt<5>(0h14))) node _T_519 = asSInt(_T_518) node _T_520 = eq(_T_519, asSInt(UInt<1>(0h0))) node _T_521 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_522 = cvt(_T_521) node _T_523 = and(_T_522, asSInt(UInt<4>(0h8))) node _T_524 = asSInt(_T_523) node _T_525 = eq(_T_524, asSInt(UInt<1>(0h0))) node _T_526 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_527 = cvt(_T_526) node _T_528 = and(_T_527, asSInt(UInt<6>(0h20))) node _T_529 = asSInt(_T_528) node _T_530 = eq(_T_529, asSInt(UInt<1>(0h0))) node _T_531 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_532 = cvt(_T_531) node _T_533 = and(_T_532, asSInt(UInt<8>(0h80))) node _T_534 = asSInt(_T_533) node _T_535 = eq(_T_534, asSInt(UInt<1>(0h0))) node _T_536 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_537 = cvt(_T_536) node _T_538 = and(_T_537, asSInt(UInt<9>(0h100))) node _T_539 = asSInt(_T_538) node _T_540 = eq(_T_539, asSInt(UInt<1>(0h0))) node _T_541 = or(_T_515, _T_520) node _T_542 = or(_T_541, _T_525) node _T_543 = or(_T_542, _T_530) node _T_544 = or(_T_543, _T_535) node _T_545 = or(_T_544, _T_540) node _T_546 = and(_T_510, _T_545) node _T_547 = or(UInt<1>(0h0), _T_546) node _T_548 = and(_T_509, _T_547) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_548, UInt<1>(0h1), "") : assert_41 node _T_552 = asUInt(reset) node _T_553 = eq(_T_552, UInt<1>(0h0)) when _T_553 : node _T_554 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_554 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_555 = asUInt(reset) node _T_556 = eq(_T_555, UInt<1>(0h0)) when _T_556 : node _T_557 = eq(is_aligned, UInt<1>(0h0)) when _T_557 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_558 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_559 = asUInt(reset) node _T_560 = eq(_T_559, UInt<1>(0h0)) when _T_560 : node _T_561 = eq(_T_558, UInt<1>(0h0)) when _T_561 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_558, UInt<1>(0h1), "") : assert_44 node _T_562 = eq(io.in.a.bits.mask, mask) node _T_563 = asUInt(reset) node _T_564 = eq(_T_563, UInt<1>(0h0)) when _T_564 : node _T_565 = eq(_T_562, UInt<1>(0h0)) when _T_565 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_562, UInt<1>(0h1), "") : assert_45 node _T_566 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_566 : node _T_567 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_568 = and(UInt<1>(0h0), _T_567) node _T_569 = or(UInt<1>(0h0), _T_568) node _T_570 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_571 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_572 = cvt(_T_571) node _T_573 = and(_T_572, asSInt(UInt<7>(0h40))) node _T_574 = asSInt(_T_573) node _T_575 = eq(_T_574, asSInt(UInt<1>(0h0))) node _T_576 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_577 = cvt(_T_576) node _T_578 = and(_T_577, asSInt(UInt<5>(0h14))) node _T_579 = asSInt(_T_578) node _T_580 = eq(_T_579, asSInt(UInt<1>(0h0))) node _T_581 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_582 = cvt(_T_581) node _T_583 = and(_T_582, asSInt(UInt<4>(0h8))) node _T_584 = asSInt(_T_583) node _T_585 = eq(_T_584, asSInt(UInt<1>(0h0))) node _T_586 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_587 = cvt(_T_586) node _T_588 = and(_T_587, asSInt(UInt<6>(0h20))) node _T_589 = asSInt(_T_588) node _T_590 = eq(_T_589, asSInt(UInt<1>(0h0))) node _T_591 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_592 = cvt(_T_591) node _T_593 = and(_T_592, asSInt(UInt<8>(0h80))) node _T_594 = asSInt(_T_593) node _T_595 = eq(_T_594, asSInt(UInt<1>(0h0))) node _T_596 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_597 = cvt(_T_596) node _T_598 = and(_T_597, asSInt(UInt<9>(0h100))) node _T_599 = asSInt(_T_598) node _T_600 = eq(_T_599, asSInt(UInt<1>(0h0))) node _T_601 = or(_T_575, _T_580) node _T_602 = or(_T_601, _T_585) node _T_603 = or(_T_602, _T_590) node _T_604 = or(_T_603, _T_595) node _T_605 = or(_T_604, _T_600) node _T_606 = and(_T_570, _T_605) node _T_607 = or(UInt<1>(0h0), _T_606) node _T_608 = and(_T_569, _T_607) node _T_609 = asUInt(reset) node _T_610 = eq(_T_609, UInt<1>(0h0)) when _T_610 : node _T_611 = eq(_T_608, UInt<1>(0h0)) when _T_611 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_608, UInt<1>(0h1), "") : assert_46 node _T_612 = asUInt(reset) node _T_613 = eq(_T_612, UInt<1>(0h0)) when _T_613 : node _T_614 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_614 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_615 = asUInt(reset) node _T_616 = eq(_T_615, UInt<1>(0h0)) when _T_616 : node _T_617 = eq(is_aligned, UInt<1>(0h0)) when _T_617 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_618 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_619 = asUInt(reset) node _T_620 = eq(_T_619, UInt<1>(0h0)) when _T_620 : node _T_621 = eq(_T_618, UInt<1>(0h0)) when _T_621 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_618, UInt<1>(0h1), "") : assert_49 node _T_622 = eq(io.in.a.bits.mask, mask) node _T_623 = asUInt(reset) node _T_624 = eq(_T_623, UInt<1>(0h0)) when _T_624 : node _T_625 = eq(_T_622, UInt<1>(0h0)) when _T_625 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_622, UInt<1>(0h1), "") : assert_50 node _T_626 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_626, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_630 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_630, UInt<1>(0h1), "") : assert_52 node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_1 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_634 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_634 : node _T_635 = asUInt(reset) node _T_636 = eq(_T_635, UInt<1>(0h0)) when _T_636 : node _T_637 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_637 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_638 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_639 = asUInt(reset) node _T_640 = eq(_T_639, UInt<1>(0h0)) when _T_640 : node _T_641 = eq(_T_638, UInt<1>(0h0)) when _T_641 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_638, UInt<1>(0h1), "") : assert_54 node _T_642 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_643 = asUInt(reset) node _T_644 = eq(_T_643, UInt<1>(0h0)) when _T_644 : node _T_645 = eq(_T_642, UInt<1>(0h0)) when _T_645 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_642, UInt<1>(0h1), "") : assert_55 node _T_646 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_647 = asUInt(reset) node _T_648 = eq(_T_647, UInt<1>(0h0)) when _T_648 : node _T_649 = eq(_T_646, UInt<1>(0h0)) when _T_649 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_646, UInt<1>(0h1), "") : assert_56 node _T_650 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_651 = asUInt(reset) node _T_652 = eq(_T_651, UInt<1>(0h0)) when _T_652 : node _T_653 = eq(_T_650, UInt<1>(0h0)) when _T_653 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_650, UInt<1>(0h1), "") : assert_57 node _T_654 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_654 : node _T_655 = asUInt(reset) node _T_656 = eq(_T_655, UInt<1>(0h0)) when _T_656 : node _T_657 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_657 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_658 = asUInt(reset) node _T_659 = eq(_T_658, UInt<1>(0h0)) when _T_659 : node _T_660 = eq(sink_ok, UInt<1>(0h0)) when _T_660 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_661 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_662 = asUInt(reset) node _T_663 = eq(_T_662, UInt<1>(0h0)) when _T_663 : node _T_664 = eq(_T_661, UInt<1>(0h0)) when _T_664 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_661, UInt<1>(0h1), "") : assert_60 node _T_665 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_666 = asUInt(reset) node _T_667 = eq(_T_666, UInt<1>(0h0)) when _T_667 : node _T_668 = eq(_T_665, UInt<1>(0h0)) when _T_668 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_665, UInt<1>(0h1), "") : assert_61 node _T_669 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_670 = asUInt(reset) node _T_671 = eq(_T_670, UInt<1>(0h0)) when _T_671 : node _T_672 = eq(_T_669, UInt<1>(0h0)) when _T_672 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_669, UInt<1>(0h1), "") : assert_62 node _T_673 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_674 = asUInt(reset) node _T_675 = eq(_T_674, UInt<1>(0h0)) when _T_675 : node _T_676 = eq(_T_673, UInt<1>(0h0)) when _T_676 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_673, UInt<1>(0h1), "") : assert_63 node _T_677 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_678 = or(UInt<1>(0h1), _T_677) node _T_679 = asUInt(reset) node _T_680 = eq(_T_679, UInt<1>(0h0)) when _T_680 : node _T_681 = eq(_T_678, UInt<1>(0h0)) when _T_681 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_678, UInt<1>(0h1), "") : assert_64 node _T_682 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_682 : node _T_683 = asUInt(reset) node _T_684 = eq(_T_683, UInt<1>(0h0)) when _T_684 : node _T_685 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_685 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_686 = asUInt(reset) node _T_687 = eq(_T_686, UInt<1>(0h0)) when _T_687 : node _T_688 = eq(sink_ok, UInt<1>(0h0)) when _T_688 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_689 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_690 = asUInt(reset) node _T_691 = eq(_T_690, UInt<1>(0h0)) when _T_691 : node _T_692 = eq(_T_689, UInt<1>(0h0)) when _T_692 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_689, UInt<1>(0h1), "") : assert_67 node _T_693 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_694 = asUInt(reset) node _T_695 = eq(_T_694, UInt<1>(0h0)) when _T_695 : node _T_696 = eq(_T_693, UInt<1>(0h0)) when _T_696 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_693, UInt<1>(0h1), "") : assert_68 node _T_697 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_698 = asUInt(reset) node _T_699 = eq(_T_698, UInt<1>(0h0)) when _T_699 : node _T_700 = eq(_T_697, UInt<1>(0h0)) when _T_700 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_697, UInt<1>(0h1), "") : assert_69 node _T_701 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_702 = or(_T_701, io.in.d.bits.corrupt) node _T_703 = asUInt(reset) node _T_704 = eq(_T_703, UInt<1>(0h0)) when _T_704 : node _T_705 = eq(_T_702, UInt<1>(0h0)) when _T_705 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_702, UInt<1>(0h1), "") : assert_70 node _T_706 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_707 = or(UInt<1>(0h1), _T_706) node _T_708 = asUInt(reset) node _T_709 = eq(_T_708, UInt<1>(0h0)) when _T_709 : node _T_710 = eq(_T_707, UInt<1>(0h0)) when _T_710 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_707, UInt<1>(0h1), "") : assert_71 node _T_711 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_711 : node _T_712 = asUInt(reset) node _T_713 = eq(_T_712, UInt<1>(0h0)) when _T_713 : node _T_714 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_714 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_715 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_716 = asUInt(reset) node _T_717 = eq(_T_716, UInt<1>(0h0)) when _T_717 : node _T_718 = eq(_T_715, UInt<1>(0h0)) when _T_718 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_715, UInt<1>(0h1), "") : assert_73 node _T_719 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_720 = asUInt(reset) node _T_721 = eq(_T_720, UInt<1>(0h0)) when _T_721 : node _T_722 = eq(_T_719, UInt<1>(0h0)) when _T_722 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_719, UInt<1>(0h1), "") : assert_74 node _T_723 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_724 = or(UInt<1>(0h1), _T_723) node _T_725 = asUInt(reset) node _T_726 = eq(_T_725, UInt<1>(0h0)) when _T_726 : node _T_727 = eq(_T_724, UInt<1>(0h0)) when _T_727 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_724, UInt<1>(0h1), "") : assert_75 node _T_728 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_728 : node _T_729 = asUInt(reset) node _T_730 = eq(_T_729, UInt<1>(0h0)) when _T_730 : node _T_731 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_731 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_732 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_733 = asUInt(reset) node _T_734 = eq(_T_733, UInt<1>(0h0)) when _T_734 : node _T_735 = eq(_T_732, UInt<1>(0h0)) when _T_735 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_732, UInt<1>(0h1), "") : assert_77 node _T_736 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_737 = or(_T_736, io.in.d.bits.corrupt) node _T_738 = asUInt(reset) node _T_739 = eq(_T_738, UInt<1>(0h0)) when _T_739 : node _T_740 = eq(_T_737, UInt<1>(0h0)) when _T_740 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_737, UInt<1>(0h1), "") : assert_78 node _T_741 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_742 = or(UInt<1>(0h1), _T_741) node _T_743 = asUInt(reset) node _T_744 = eq(_T_743, UInt<1>(0h0)) when _T_744 : node _T_745 = eq(_T_742, UInt<1>(0h0)) when _T_745 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_742, UInt<1>(0h1), "") : assert_79 node _T_746 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_746 : node _T_747 = asUInt(reset) node _T_748 = eq(_T_747, UInt<1>(0h0)) when _T_748 : node _T_749 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_749 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_750 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_751 = asUInt(reset) node _T_752 = eq(_T_751, UInt<1>(0h0)) when _T_752 : node _T_753 = eq(_T_750, UInt<1>(0h0)) when _T_753 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_750, UInt<1>(0h1), "") : assert_81 node _T_754 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_755 = asUInt(reset) node _T_756 = eq(_T_755, UInt<1>(0h0)) when _T_756 : node _T_757 = eq(_T_754, UInt<1>(0h0)) when _T_757 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_754, UInt<1>(0h1), "") : assert_82 node _T_758 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_759 = or(UInt<1>(0h1), _T_758) node _T_760 = asUInt(reset) node _T_761 = eq(_T_760, UInt<1>(0h0)) when _T_761 : node _T_762 = eq(_T_759, UInt<1>(0h0)) when _T_762 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_759, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<32>(0h0) connect _WIRE.bits.mask, UInt<4>(0h0) connect _WIRE.bits.address, UInt<9>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_763 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_764 = asUInt(reset) node _T_765 = eq(_T_764, UInt<1>(0h0)) when _T_765 : node _T_766 = eq(_T_763, UInt<1>(0h0)) when _T_766 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_763, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<32>(0h0) connect _WIRE_2.bits.address, UInt<9>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_767 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_768 = asUInt(reset) node _T_769 = eq(_T_768, UInt<1>(0h0)) when _T_769 : node _T_770 = eq(_T_767, UInt<1>(0h0)) when _T_770 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_767, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_771 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_772 = asUInt(reset) node _T_773 = eq(_T_772, UInt<1>(0h0)) when _T_773 : node _T_774 = eq(_T_771, UInt<1>(0h0)) when _T_774 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_771, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 1, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 2) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_775 = eq(a_first, UInt<1>(0h0)) node _T_776 = and(io.in.a.valid, _T_775) when _T_776 : node _T_777 = eq(io.in.a.bits.opcode, opcode) node _T_778 = asUInt(reset) node _T_779 = eq(_T_778, UInt<1>(0h0)) when _T_779 : node _T_780 = eq(_T_777, UInt<1>(0h0)) when _T_780 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_777, UInt<1>(0h1), "") : assert_87 node _T_781 = eq(io.in.a.bits.param, param) node _T_782 = asUInt(reset) node _T_783 = eq(_T_782, UInt<1>(0h0)) when _T_783 : node _T_784 = eq(_T_781, UInt<1>(0h0)) when _T_784 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_781, UInt<1>(0h1), "") : assert_88 node _T_785 = eq(io.in.a.bits.size, size) node _T_786 = asUInt(reset) node _T_787 = eq(_T_786, UInt<1>(0h0)) when _T_787 : node _T_788 = eq(_T_785, UInt<1>(0h0)) when _T_788 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_785, UInt<1>(0h1), "") : assert_89 node _T_789 = eq(io.in.a.bits.source, source) node _T_790 = asUInt(reset) node _T_791 = eq(_T_790, UInt<1>(0h0)) when _T_791 : node _T_792 = eq(_T_789, UInt<1>(0h0)) when _T_792 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_789, UInt<1>(0h1), "") : assert_90 node _T_793 = eq(io.in.a.bits.address, address) node _T_794 = asUInt(reset) node _T_795 = eq(_T_794, UInt<1>(0h0)) when _T_795 : node _T_796 = eq(_T_793, UInt<1>(0h0)) when _T_796 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_793, UInt<1>(0h1), "") : assert_91 node _T_797 = and(io.in.a.ready, io.in.a.valid) node _T_798 = and(_T_797, a_first) when _T_798 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 1, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 2) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_799 = eq(d_first, UInt<1>(0h0)) node _T_800 = and(io.in.d.valid, _T_799) when _T_800 : node _T_801 = eq(io.in.d.bits.opcode, opcode_1) node _T_802 = asUInt(reset) node _T_803 = eq(_T_802, UInt<1>(0h0)) when _T_803 : node _T_804 = eq(_T_801, UInt<1>(0h0)) when _T_804 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_801, UInt<1>(0h1), "") : assert_92 node _T_805 = eq(io.in.d.bits.param, param_1) node _T_806 = asUInt(reset) node _T_807 = eq(_T_806, UInt<1>(0h0)) when _T_807 : node _T_808 = eq(_T_805, UInt<1>(0h0)) when _T_808 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_805, UInt<1>(0h1), "") : assert_93 node _T_809 = eq(io.in.d.bits.size, size_1) node _T_810 = asUInt(reset) node _T_811 = eq(_T_810, UInt<1>(0h0)) when _T_811 : node _T_812 = eq(_T_809, UInt<1>(0h0)) when _T_812 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_809, UInt<1>(0h1), "") : assert_94 node _T_813 = eq(io.in.d.bits.source, source_1) node _T_814 = asUInt(reset) node _T_815 = eq(_T_814, UInt<1>(0h0)) when _T_815 : node _T_816 = eq(_T_813, UInt<1>(0h0)) when _T_816 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_813, UInt<1>(0h1), "") : assert_95 node _T_817 = eq(io.in.d.bits.sink, sink) node _T_818 = asUInt(reset) node _T_819 = eq(_T_818, UInt<1>(0h0)) when _T_819 : node _T_820 = eq(_T_817, UInt<1>(0h0)) when _T_820 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_817, UInt<1>(0h1), "") : assert_96 node _T_821 = eq(io.in.d.bits.denied, denied) node _T_822 = asUInt(reset) node _T_823 = eq(_T_822, UInt<1>(0h0)) when _T_823 : node _T_824 = eq(_T_821, UInt<1>(0h0)) when _T_824 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_821, UInt<1>(0h1), "") : assert_97 node _T_825 = and(io.in.d.ready, io.in.d.valid) node _T_826 = and(_T_825, d_first) when _T_826 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes : UInt<4>, clock, reset, UInt<4>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 1, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 2) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 1, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 2) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1> connect a_set, UInt<1>(0h0) wire a_set_wo_ready : UInt<1> connect a_set_wo_ready, UInt<1>(0h0) wire a_opcodes_set : UInt<4> connect a_opcodes_set, UInt<4>(0h0) wire a_sizes_set : UInt<4> connect a_sizes_set, UInt<4>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_827 = and(io.in.a.valid, a_first_1) node _T_828 = and(_T_827, UInt<1>(0h1)) when _T_828 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_829 = and(io.in.a.ready, io.in.a.valid) node _T_830 = and(_T_829, a_first_1) node _T_831 = and(_T_830, UInt<1>(0h1)) when _T_831 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_832 = dshr(inflight, io.in.a.bits.source) node _T_833 = bits(_T_832, 0, 0) node _T_834 = eq(_T_833, UInt<1>(0h0)) node _T_835 = asUInt(reset) node _T_836 = eq(_T_835, UInt<1>(0h0)) when _T_836 : node _T_837 = eq(_T_834, UInt<1>(0h0)) when _T_837 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_834, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1> connect d_clr, UInt<1>(0h0) wire d_clr_wo_ready : UInt<1> connect d_clr_wo_ready, UInt<1>(0h0) wire d_opcodes_clr : UInt<4> connect d_opcodes_clr, UInt<4>(0h0) wire d_sizes_clr : UInt<4> connect d_sizes_clr, UInt<4>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_838 = and(io.in.d.valid, d_first_1) node _T_839 = and(_T_838, UInt<1>(0h1)) node _T_840 = eq(d_release_ack, UInt<1>(0h0)) node _T_841 = and(_T_839, _T_840) when _T_841 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_842 = and(io.in.d.ready, io.in.d.valid) node _T_843 = and(_T_842, d_first_1) node _T_844 = and(_T_843, UInt<1>(0h1)) node _T_845 = eq(d_release_ack, UInt<1>(0h0)) node _T_846 = and(_T_844, _T_845) when _T_846 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_847 = and(io.in.d.valid, d_first_1) node _T_848 = and(_T_847, UInt<1>(0h1)) node _T_849 = eq(d_release_ack, UInt<1>(0h0)) node _T_850 = and(_T_848, _T_849) when _T_850 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_851 = dshr(inflight, io.in.d.bits.source) node _T_852 = bits(_T_851, 0, 0) node _T_853 = or(_T_852, same_cycle_resp) node _T_854 = asUInt(reset) node _T_855 = eq(_T_854, UInt<1>(0h0)) when _T_855 : node _T_856 = eq(_T_853, UInt<1>(0h0)) when _T_856 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_853, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_857 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_858 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_859 = or(_T_857, _T_858) node _T_860 = asUInt(reset) node _T_861 = eq(_T_860, UInt<1>(0h0)) when _T_861 : node _T_862 = eq(_T_859, UInt<1>(0h0)) when _T_862 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_859, UInt<1>(0h1), "") : assert_100 node _T_863 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_864 = asUInt(reset) node _T_865 = eq(_T_864, UInt<1>(0h0)) when _T_865 : node _T_866 = eq(_T_863, UInt<1>(0h0)) when _T_866 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_863, UInt<1>(0h1), "") : assert_101 else : node _T_867 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_868 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_869 = or(_T_867, _T_868) node _T_870 = asUInt(reset) node _T_871 = eq(_T_870, UInt<1>(0h0)) when _T_871 : node _T_872 = eq(_T_869, UInt<1>(0h0)) when _T_872 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_869, UInt<1>(0h1), "") : assert_102 node _T_873 = eq(io.in.d.bits.size, a_size_lookup) node _T_874 = asUInt(reset) node _T_875 = eq(_T_874, UInt<1>(0h0)) when _T_875 : node _T_876 = eq(_T_873, UInt<1>(0h0)) when _T_876 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_873, UInt<1>(0h1), "") : assert_103 node _T_877 = and(io.in.d.valid, d_first_1) node _T_878 = and(_T_877, a_first_1) node _T_879 = and(_T_878, io.in.a.valid) node _T_880 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_881 = and(_T_879, _T_880) node _T_882 = eq(d_release_ack, UInt<1>(0h0)) node _T_883 = and(_T_881, _T_882) when _T_883 : node _T_884 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_885 = or(_T_884, io.in.a.ready) node _T_886 = asUInt(reset) node _T_887 = eq(_T_886, UInt<1>(0h0)) when _T_887 : node _T_888 = eq(_T_885, UInt<1>(0h0)) when _T_888 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_885, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_85 node _T_889 = orr(inflight) node _T_890 = eq(_T_889, UInt<1>(0h0)) node _T_891 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_892 = or(_T_890, _T_891) node _T_893 = lt(watchdog, plusarg_reader.out) node _T_894 = or(_T_892, _T_893) node _T_895 = asUInt(reset) node _T_896 = eq(_T_895, UInt<1>(0h0)) when _T_896 : node _T_897 = eq(_T_894, UInt<1>(0h0)) when _T_897 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_894, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_898 = and(io.in.a.ready, io.in.a.valid) node _T_899 = and(io.in.d.ready, io.in.d.valid) node _T_900 = or(_T_898, _T_899) when _T_900 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes_1 : UInt<4>, clock, reset, UInt<4>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<32>(0h0) connect _c_first_WIRE.bits.address, UInt<9>(0h0) connect _c_first_WIRE.bits.source, UInt<1>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<32>(0h0) connect _c_first_WIRE_2.bits.address, UInt<9>(0h0) connect _c_first_WIRE_2.bits.source, UInt<1>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<2>(0h3), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 1, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 2) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 1, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 2) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1> connect c_set, UInt<1>(0h0) wire c_set_wo_ready : UInt<1> connect c_set_wo_ready, UInt<1>(0h0) wire c_opcodes_set : UInt<4> connect c_opcodes_set, UInt<4>(0h0) wire c_sizes_set : UInt<4> connect c_sizes_set, UInt<4>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<32>(0h0) connect _WIRE_6.bits.address, UInt<9>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_901 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<32>(0h0) connect _WIRE_8.bits.address, UInt<9>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_902 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_903 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_904 = and(_T_902, _T_903) node _T_905 = and(_T_901, _T_904) when _T_905 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<9>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<32>(0h0) connect _WIRE_10.bits.address, UInt<9>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_906 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_907 = and(_T_906, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<32>(0h0) connect _WIRE_12.bits.address, UInt<9>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_908 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_909 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_910 = and(_T_908, _T_909) node _T_911 = and(_T_907, _T_910) when _T_911 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<32>(0h0) connect _c_set_WIRE.bits.address, UInt<9>(0h0) connect _c_set_WIRE.bits.source, UInt<1>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<9>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<9>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<9>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<9>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<32>(0h0) connect _WIRE_14.bits.address, UInt<9>(0h0) connect _WIRE_14.bits.source, UInt<1>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_912 = dshr(inflight_1, _WIRE_15.bits.source) node _T_913 = bits(_T_912, 0, 0) node _T_914 = eq(_T_913, UInt<1>(0h0)) node _T_915 = asUInt(reset) node _T_916 = eq(_T_915, UInt<1>(0h0)) when _T_916 : node _T_917 = eq(_T_914, UInt<1>(0h0)) when _T_917 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_914, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<9>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<9>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1> connect d_clr_1, UInt<1>(0h0) wire d_clr_wo_ready_1 : UInt<1> connect d_clr_wo_ready_1, UInt<1>(0h0) wire d_opcodes_clr_1 : UInt<4> connect d_opcodes_clr_1, UInt<4>(0h0) wire d_sizes_clr_1 : UInt<4> connect d_sizes_clr_1, UInt<4>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_918 = and(io.in.d.valid, d_first_2) node _T_919 = and(_T_918, UInt<1>(0h1)) node _T_920 = and(_T_919, d_release_ack_1) when _T_920 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_921 = and(io.in.d.ready, io.in.d.valid) node _T_922 = and(_T_921, d_first_2) node _T_923 = and(_T_922, UInt<1>(0h1)) node _T_924 = and(_T_923, d_release_ack_1) when _T_924 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_925 = and(io.in.d.valid, d_first_2) node _T_926 = and(_T_925, UInt<1>(0h1)) node _T_927 = and(_T_926, d_release_ack_1) when _T_927 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<9>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<9>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<9>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_928 = dshr(inflight_1, io.in.d.bits.source) node _T_929 = bits(_T_928, 0, 0) node _T_930 = or(_T_929, same_cycle_resp_1) node _T_931 = asUInt(reset) node _T_932 = eq(_T_931, UInt<1>(0h0)) when _T_932 : node _T_933 = eq(_T_930, UInt<1>(0h0)) when _T_933 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_930, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<32>(0h0) connect _WIRE_16.bits.address, UInt<9>(0h0) connect _WIRE_16.bits.source, UInt<1>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_934 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_935 = asUInt(reset) node _T_936 = eq(_T_935, UInt<1>(0h0)) when _T_936 : node _T_937 = eq(_T_934, UInt<1>(0h0)) when _T_937 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_934, UInt<1>(0h1), "") : assert_108 else : node _T_938 = eq(io.in.d.bits.size, c_size_lookup) node _T_939 = asUInt(reset) node _T_940 = eq(_T_939, UInt<1>(0h0)) when _T_940 : node _T_941 = eq(_T_938, UInt<1>(0h0)) when _T_941 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_938, UInt<1>(0h1), "") : assert_109 node _T_942 = and(io.in.d.valid, d_first_2) node _T_943 = and(_T_942, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<32>(0h0) connect _WIRE_18.bits.address, UInt<9>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_944 = and(_T_943, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<32>(0h0) connect _WIRE_20.bits.address, UInt<9>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_945 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_946 = and(_T_944, _T_945) node _T_947 = and(_T_946, d_release_ack_1) node _T_948 = eq(c_probe_ack, UInt<1>(0h0)) node _T_949 = and(_T_947, _T_948) when _T_949 : node _T_950 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<32>(0h0) connect _WIRE_22.bits.address, UInt<9>(0h0) connect _WIRE_22.bits.source, UInt<1>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_951 = or(_T_950, _WIRE_23.ready) node _T_952 = asUInt(reset) node _T_953 = eq(_T_952, UInt<1>(0h0)) when _T_953 : node _T_954 = eq(_T_951, UInt<1>(0h0)) when _T_954 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_951, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_86 node _T_955 = orr(inflight_1) node _T_956 = eq(_T_955, UInt<1>(0h0)) node _T_957 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_958 = or(_T_956, _T_957) node _T_959 = lt(watchdog_1, plusarg_reader_1.out) node _T_960 = or(_T_958, _T_959) node _T_961 = asUInt(reset) node _T_962 = eq(_T_961, UInt<1>(0h0)) when _T_962 : node _T_963 = eq(_T_960, UInt<1>(0h0)) when _T_963 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:32:12)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_960, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<32>(0h0) connect _WIRE_24.bits.address, UInt<9>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_964 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_965 = and(io.in.d.ready, io.in.d.valid) node _T_966 = or(_T_964, _T_965) when _T_966 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_42( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [8:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [31:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [8:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [31:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire mask_sizeOH_shiftAmount = 1'h0; // @[OneHot.scala:64:49] wire mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21] wire mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_size = 1'h1; // @[Misc.scala:209:26] wire mask_acc = 1'h1; // @[Misc.scala:215:29] wire mask_acc_1 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_2 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_3 = 1'h1; // @[Misc.scala:215:29] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] is_aligned_mask = 2'h3; // @[package.scala:243:46] wire [1:0] mask_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] _a_first_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46] wire [1:0] _a_first_beats1_decode_T_5 = 2'h3; // @[package.scala:243:46] wire [1:0] _c_first_beats1_decode_T_1 = 2'h3; // @[package.scala:243:76] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_a_bits_size = 2'h2; // @[Monitor.scala:36:7] wire [1:0] _mask_sizeOH_T = 2'h2; // @[Misc.scala:202:34] wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [3:0] io_in_a_bits_mask = 4'hF; // @[Monitor.scala:36:7] wire [3:0] mask = 4'hF; // @[Misc.scala:222:10] wire [31:0] _c_first_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [8:0] _c_first_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_first_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_first_WIRE_2_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_first_WIRE_3_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_set_wo_ready_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_set_wo_ready_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_set_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_set_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_opcodes_set_interm_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_opcodes_set_interm_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_sizes_set_interm_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_sizes_set_interm_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_opcodes_set_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_opcodes_set_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_sizes_set_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_sizes_set_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_probe_ack_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_probe_ack_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_probe_ack_WIRE_2_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_probe_ack_WIRE_3_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _same_cycle_resp_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _same_cycle_resp_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _same_cycle_resp_WIRE_2_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _same_cycle_resp_WIRE_3_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _same_cycle_resp_WIRE_4_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _same_cycle_resp_WIRE_5_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [1:0] _is_aligned_mask_T_1 = 2'h0; // @[package.scala:243:76] wire [1:0] _a_first_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76] wire [1:0] _a_first_beats1_decode_T_4 = 2'h0; // @[package.scala:243:76] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_beats1_decode_T_2 = 2'h0; // @[package.scala:243:46] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [17:0] _c_sizes_set_T_1 = 18'h0; // @[Monitor.scala:768:52] wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79] wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] c_sizes_set = 4'h0; // @[Monitor.scala:741:34] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [1:0] _mask_sizeOH_T_1 = 2'h1; // @[OneHot.scala:65:12] wire [1:0] _mask_sizeOH_T_2 = 2'h1; // @[OneHot.scala:65:27] wire [1:0] mask_sizeOH = 2'h1; // @[Misc.scala:202:81] wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [4:0] _c_first_beats1_decode_T = 5'h3; // @[package.scala:243:71] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] _a_sizes_set_interm_T_1 = 3'h5; // @[Monitor.scala:658:59] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] _a_sizes_set_interm_T = 3'h4; // @[Monitor.scala:658:51] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [4:0] _is_aligned_mask_T = 5'hC; // @[package.scala:243:71] wire [4:0] _a_first_beats1_decode_T = 5'hC; // @[package.scala:243:71] wire [4:0] _a_first_beats1_decode_T_3 = 5'hC; // @[package.scala:243:71] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [8:0] _is_aligned_T = {7'h0, io_in_a_bits_address_0[1:0]}; // @[Monitor.scala:36:7] wire is_aligned = _is_aligned_T == 9'h0; // @[Edges.scala:21:{16,24}] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_1_2 = mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_eq; // @[Misc.scala:214:27, :215:38] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_eq_1; // @[Misc.scala:214:27, :215:38] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_eq_2; // @[Misc.scala:214:27, :215:38] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_eq_3; // @[Misc.scala:214:27, :215:38] wire _source_ok_T_1 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_1; // @[Parameters.scala:1138:31] wire _T_898 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_898; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_898; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [8:0] address; // @[Monitor.scala:391:22] wire _T_966 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_966; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_966; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_966; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [4:0] _GEN = 5'h3 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN; // @[package.scala:243:71] wire [1:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [3:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [1:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [3:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [3:0] _GEN_0 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [3:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_0; // @[Monitor.scala:637:69] wire [3:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_0; // @[Monitor.scala:637:69, :641:65] wire [3:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_0; // @[Monitor.scala:637:69, :680:101] wire [3:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_0; // @[Monitor.scala:637:69, :681:99] wire [3:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_0; // @[Monitor.scala:637:69, :749:69] wire [3:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_0; // @[Monitor.scala:637:69, :750:67] wire [3:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_0; // @[Monitor.scala:637:69, :790:101] wire [3:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_0; // @[Monitor.scala:637:69, :791:99] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [3:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [15:0] _a_size_lookup_T_6 = {12'h0, _a_size_lookup_T_1}; // @[Monitor.scala:637:97, :641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _T_828 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26] assign a_set_wo_ready = _T_828; // @[Monitor.scala:627:34, :651:26] wire _same_cycle_resp_T; // @[Monitor.scala:684:44] assign _same_cycle_resp_T = _T_828; // @[Monitor.scala:651:26, :684:44] assign a_set = _T_898 & a_first_1; // @[Decoupled.scala:51:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = a_set ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:{28,61}] assign a_sizes_set_interm = a_set ? 3'h5 : 3'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:28] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[Monitor.scala:646:40, :659:54] assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}] wire [17:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[Monitor.scala:648:38, :659:54, :660:52] assign a_sizes_set = a_set ? _a_sizes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [3:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_1 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_1; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_1; // @[Monitor.scala:673:46, :783:46] wire _T_877 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [1:0] _GEN_2 = {1'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_3 = 2'h1 << _GEN_2; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_3; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_3; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_3; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_877 & ~d_release_ack & _d_clr_wo_ready_T[0]; // @[OneHot.scala:58:35] wire _T_846 = _T_966 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_846 & _d_clr_T[0]; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_5 = 31'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_846 ? _d_opcodes_clr_T_5[3:0] : 4'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [30:0] _d_sizes_clr_T_5 = 31'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_846 ? _d_sizes_clr_T_5[3:0] : 4'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1:0] _inflight_T = {inflight[1], inflight[0] \| a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [3:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [3:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [3:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [3:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [3:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [1:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:637:97, :749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [3:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [15:0] _c_size_lookup_T_6 = {12'h0, _c_size_lookup_T_1}; // @[Monitor.scala:637:97, :750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [3:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_942 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_942 & d_release_ack_1 & _d_clr_wo_ready_T_1[0]; // @[OneHot.scala:58:35] wire _T_924 = _T_966 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_924 & _d_clr_T_1[0]; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_11 = 31'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_924 ? _d_opcodes_clr_T_11[3:0] : 4'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [30:0] _d_sizes_clr_T_11 = 31'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_924 ? _d_sizes_clr_T_11[3:0] : 4'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [3:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [3:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module SwitchArbiter_24 : input clock : Clock input reset : Reset output io : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}, tail : UInt<1>}}[3], out : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}, tail : UInt<1>}}[1], chosen_oh : UInt<3>[1]} regreset lock_0 : UInt<3>, clock, reset, UInt<3>(0h0) node unassigned_hi = cat(io.in[2].valid, io.in[1].valid) node _unassigned_T = cat(unassigned_hi, io.in[0].valid) node _unassigned_T_1 = not(lock_0) node unassigned = and(_unassigned_T, _unassigned_T_1) regreset mask : UInt<3>, clock, reset, UInt<3>(0h0) wire choices : UInt<3>[1] node _sel_T = not(mask) node _sel_T_1 = and(unassigned, _sel_T) node _sel_T_2 = cat(unassigned, _sel_T_1) node _sel_T_3 = bits(_sel_T_2, 0, 0) node _sel_T_4 = bits(_sel_T_2, 1, 1) node _sel_T_5 = bits(_sel_T_2, 2, 2) node _sel_T_6 = bits(_sel_T_2, 3, 3) node _sel_T_7 = bits(_sel_T_2, 4, 4) node _sel_T_8 = bits(_sel_T_2, 5, 5) node _sel_T_9 = mux(_sel_T_8, UInt<6>(0h20), UInt<6>(0h0)) node _sel_T_10 = mux(_sel_T_7, UInt<6>(0h10), _sel_T_9) node _sel_T_11 = mux(_sel_T_6, UInt<6>(0h8), _sel_T_10) node _sel_T_12 = mux(_sel_T_5, UInt<6>(0h4), _sel_T_11) node _sel_T_13 = mux(_sel_T_4, UInt<6>(0h2), _sel_T_12) node sel = mux(_sel_T_3, UInt<6>(0h1), _sel_T_13) node _choices_0_T = shr(sel, 3) node _choices_0_T_1 = or(sel, _choices_0_T) connect choices[0], _choices_0_T_1 node _T = not(choices[0]) node _T_1 = and(unassigned, _T) node _T_2 = bits(_T_1, 0, 0) node _T_3 = bits(_T_1, 1, 1) node _T_4 = bits(_T_1, 2, 2) node _T_5 = mux(_T_4, UInt<3>(0h4), UInt<3>(0h0)) node _T_6 = mux(_T_3, UInt<3>(0h2), _T_5) node _T_7 = mux(_T_2, UInt<3>(0h1), _T_6) connect io.in[0].ready, UInt<1>(0h0) connect io.in[1].ready, UInt<1>(0h0) connect io.in[2].ready, UInt<1>(0h0) node in_tails_hi = cat(io.in[2].bits.tail, io.in[1].bits.tail) node in_tails = cat(in_tails_hi, io.in[0].bits.tail) node _in_valids_T = eq(UInt<1>(0h0), UInt<1>(0h0)) node _in_valids_T_1 = and(io.in[0].valid, _in_valids_T) node _in_valids_T_2 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _in_valids_T_3 = and(io.in[1].valid, _in_valids_T_2) node _in_valids_T_4 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _in_valids_T_5 = and(io.in[2].valid, _in_valids_T_4) node in_valids_hi = cat(_in_valids_T_5, _in_valids_T_3) node in_valids = cat(in_valids_hi, _in_valids_T_1) node _chosen_T = and(in_valids, lock_0) node _chosen_T_1 = not(UInt<3>(0h0)) node _chosen_T_2 = and(_chosen_T, _chosen_T_1) node _chosen_T_3 = orr(_chosen_T_2) node chosen = mux(_chosen_T_3, lock_0, choices[0]) connect io.chosen_oh[0], chosen node _io_out_0_valid_T = and(in_valids, chosen) node _io_out_0_valid_T_1 = orr(_io_out_0_valid_T) connect io.out[0].valid, _io_out_0_valid_T_1 node _io_out_0_bits_T = bits(chosen, 0, 0) node _io_out_0_bits_T_1 = bits(chosen, 1, 1) node _io_out_0_bits_T_2 = bits(chosen, 2, 2) wire _io_out_0_bits_WIRE : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}, tail : UInt<1>} node _io_out_0_bits_T_3 = mux(_io_out_0_bits_T, io.in[0].bits.tail, UInt<1>(0h0)) node _io_out_0_bits_T_4 = mux(_io_out_0_bits_T_1, io.in[1].bits.tail, UInt<1>(0h0)) node _io_out_0_bits_T_5 = mux(_io_out_0_bits_T_2, io.in[2].bits.tail, UInt<1>(0h0)) node _io_out_0_bits_T_6 = or(_io_out_0_bits_T_3, _io_out_0_bits_T_4) node _io_out_0_bits_T_7 = or(_io_out_0_bits_T_6, _io_out_0_bits_T_5) wire _io_out_0_bits_WIRE_1 : UInt<1> connect _io_out_0_bits_WIRE_1, _io_out_0_bits_T_7 connect _io_out_0_bits_WIRE.tail, _io_out_0_bits_WIRE_1 wire _io_out_0_bits_WIRE_2 : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]} wire _io_out_0_bits_WIRE_3 : UInt<1>[10] node _io_out_0_bits_T_8 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[0], UInt<1>(0h0)) node _io_out_0_bits_T_9 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[0], UInt<1>(0h0)) node _io_out_0_bits_T_10 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`0`[0], UInt<1>(0h0)) node _io_out_0_bits_T_11 = or(_io_out_0_bits_T_8, _io_out_0_bits_T_9) node _io_out_0_bits_T_12 = or(_io_out_0_bits_T_11, _io_out_0_bits_T_10) wire _io_out_0_bits_WIRE_4 : UInt<1> connect _io_out_0_bits_WIRE_4, _io_out_0_bits_T_12 connect _io_out_0_bits_WIRE_3[0], _io_out_0_bits_WIRE_4 node _io_out_0_bits_T_13 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[1], UInt<1>(0h0)) node _io_out_0_bits_T_14 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[1], UInt<1>(0h0)) node _io_out_0_bits_T_15 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`0`[1], UInt<1>(0h0)) node _io_out_0_bits_T_16 = or(_io_out_0_bits_T_13, _io_out_0_bits_T_14) node _io_out_0_bits_T_17 = or(_io_out_0_bits_T_16, _io_out_0_bits_T_15) wire _io_out_0_bits_WIRE_5 : UInt<1> connect _io_out_0_bits_WIRE_5, _io_out_0_bits_T_17 connect _io_out_0_bits_WIRE_3[1], _io_out_0_bits_WIRE_5 node _io_out_0_bits_T_18 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[2], UInt<1>(0h0)) node _io_out_0_bits_T_19 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[2], UInt<1>(0h0)) node _io_out_0_bits_T_20 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`0`[2], UInt<1>(0h0)) node _io_out_0_bits_T_21 = or(_io_out_0_bits_T_18, _io_out_0_bits_T_19) node _io_out_0_bits_T_22 = or(_io_out_0_bits_T_21, _io_out_0_bits_T_20) wire _io_out_0_bits_WIRE_6 : UInt<1> connect _io_out_0_bits_WIRE_6, _io_out_0_bits_T_22 connect _io_out_0_bits_WIRE_3[2], _io_out_0_bits_WIRE_6 node _io_out_0_bits_T_23 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[3], UInt<1>(0h0)) node _io_out_0_bits_T_24 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[3], UInt<1>(0h0)) node _io_out_0_bits_T_25 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`0`[3], UInt<1>(0h0)) node _io_out_0_bits_T_26 = or(_io_out_0_bits_T_23, _io_out_0_bits_T_24) node _io_out_0_bits_T_27 = or(_io_out_0_bits_T_26, _io_out_0_bits_T_25) wire _io_out_0_bits_WIRE_7 : UInt<1> connect _io_out_0_bits_WIRE_7, _io_out_0_bits_T_27 connect _io_out_0_bits_WIRE_3[3], _io_out_0_bits_WIRE_7 node _io_out_0_bits_T_28 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[4], UInt<1>(0h0)) node _io_out_0_bits_T_29 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[4], UInt<1>(0h0)) node _io_out_0_bits_T_30 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`0`[4], UInt<1>(0h0)) node _io_out_0_bits_T_31 = or(_io_out_0_bits_T_28, _io_out_0_bits_T_29) node _io_out_0_bits_T_32 = or(_io_out_0_bits_T_31, _io_out_0_bits_T_30) wire _io_out_0_bits_WIRE_8 : UInt<1> connect _io_out_0_bits_WIRE_8, _io_out_0_bits_T_32 connect _io_out_0_bits_WIRE_3[4], _io_out_0_bits_WIRE_8 node _io_out_0_bits_T_33 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[5], UInt<1>(0h0)) node _io_out_0_bits_T_34 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[5], UInt<1>(0h0)) node _io_out_0_bits_T_35 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`0`[5], UInt<1>(0h0)) node _io_out_0_bits_T_36 = or(_io_out_0_bits_T_33, _io_out_0_bits_T_34) node _io_out_0_bits_T_37 = or(_io_out_0_bits_T_36, _io_out_0_bits_T_35) wire _io_out_0_bits_WIRE_9 : UInt<1> connect _io_out_0_bits_WIRE_9, _io_out_0_bits_T_37 connect _io_out_0_bits_WIRE_3[5], _io_out_0_bits_WIRE_9 node _io_out_0_bits_T_38 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[6], UInt<1>(0h0)) node _io_out_0_bits_T_39 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[6], UInt<1>(0h0)) node _io_out_0_bits_T_40 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`0`[6], UInt<1>(0h0)) node _io_out_0_bits_T_41 = or(_io_out_0_bits_T_38, _io_out_0_bits_T_39) node _io_out_0_bits_T_42 = or(_io_out_0_bits_T_41, _io_out_0_bits_T_40) wire _io_out_0_bits_WIRE_10 : UInt<1> connect _io_out_0_bits_WIRE_10, _io_out_0_bits_T_42 connect _io_out_0_bits_WIRE_3[6], _io_out_0_bits_WIRE_10 node _io_out_0_bits_T_43 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[7], UInt<1>(0h0)) node _io_out_0_bits_T_44 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[7], UInt<1>(0h0)) node _io_out_0_bits_T_45 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`0`[7], UInt<1>(0h0)) node _io_out_0_bits_T_46 = or(_io_out_0_bits_T_43, _io_out_0_bits_T_44) node _io_out_0_bits_T_47 = or(_io_out_0_bits_T_46, _io_out_0_bits_T_45) wire _io_out_0_bits_WIRE_11 : UInt<1> connect _io_out_0_bits_WIRE_11, _io_out_0_bits_T_47 connect _io_out_0_bits_WIRE_3[7], _io_out_0_bits_WIRE_11 node _io_out_0_bits_T_48 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[8], UInt<1>(0h0)) node _io_out_0_bits_T_49 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[8], UInt<1>(0h0)) node _io_out_0_bits_T_50 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`0`[8], UInt<1>(0h0)) node _io_out_0_bits_T_51 = or(_io_out_0_bits_T_48, _io_out_0_bits_T_49) node _io_out_0_bits_T_52 = or(_io_out_0_bits_T_51, _io_out_0_bits_T_50) wire _io_out_0_bits_WIRE_12 : UInt<1> connect _io_out_0_bits_WIRE_12, _io_out_0_bits_T_52 connect _io_out_0_bits_WIRE_3[8], _io_out_0_bits_WIRE_12 node _io_out_0_bits_T_53 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[9], UInt<1>(0h0)) node _io_out_0_bits_T_54 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[9], UInt<1>(0h0)) node _io_out_0_bits_T_55 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`0`[9], UInt<1>(0h0)) node _io_out_0_bits_T_56 = or(_io_out_0_bits_T_53, _io_out_0_bits_T_54) node _io_out_0_bits_T_57 = or(_io_out_0_bits_T_56, _io_out_0_bits_T_55) wire _io_out_0_bits_WIRE_13 : UInt<1> connect _io_out_0_bits_WIRE_13, _io_out_0_bits_T_57 connect _io_out_0_bits_WIRE_3[9], _io_out_0_bits_WIRE_13 connect _io_out_0_bits_WIRE_2.`0`, _io_out_0_bits_WIRE_3 wire _io_out_0_bits_WIRE_14 : UInt<1>[1] node _io_out_0_bits_T_58 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`1`[0], UInt<1>(0h0)) node _io_out_0_bits_T_59 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`1`[0], UInt<1>(0h0)) node _io_out_0_bits_T_60 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`1`[0], UInt<1>(0h0)) node _io_out_0_bits_T_61 = or(_io_out_0_bits_T_58, _io_out_0_bits_T_59) node _io_out_0_bits_T_62 = or(_io_out_0_bits_T_61, _io_out_0_bits_T_60) wire _io_out_0_bits_WIRE_15 : UInt<1> connect _io_out_0_bits_WIRE_15, _io_out_0_bits_T_62 connect _io_out_0_bits_WIRE_14[0], _io_out_0_bits_WIRE_15 connect _io_out_0_bits_WIRE_2.`1`, _io_out_0_bits_WIRE_14 wire _io_out_0_bits_WIRE_16 : UInt<1>[1] node _io_out_0_bits_T_63 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`2`[0], UInt<1>(0h0)) node _io_out_0_bits_T_64 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`2`[0], UInt<1>(0h0)) node _io_out_0_bits_T_65 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`2`[0], UInt<1>(0h0)) node _io_out_0_bits_T_66 = or(_io_out_0_bits_T_63, _io_out_0_bits_T_64) node _io_out_0_bits_T_67 = or(_io_out_0_bits_T_66, _io_out_0_bits_T_65) wire _io_out_0_bits_WIRE_17 : UInt<1> connect _io_out_0_bits_WIRE_17, _io_out_0_bits_T_67 connect _io_out_0_bits_WIRE_16[0], _io_out_0_bits_WIRE_17 connect _io_out_0_bits_WIRE_2.`2`, _io_out_0_bits_WIRE_16 wire _io_out_0_bits_WIRE_18 : UInt<1>[1] node _io_out_0_bits_T_68 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`3`[0], UInt<1>(0h0)) node _io_out_0_bits_T_69 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`3`[0], UInt<1>(0h0)) node _io_out_0_bits_T_70 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`3`[0], UInt<1>(0h0)) node _io_out_0_bits_T_71 = or(_io_out_0_bits_T_68, _io_out_0_bits_T_69) node _io_out_0_bits_T_72 = or(_io_out_0_bits_T_71, _io_out_0_bits_T_70) wire _io_out_0_bits_WIRE_19 : UInt<1> connect _io_out_0_bits_WIRE_19, _io_out_0_bits_T_72 connect _io_out_0_bits_WIRE_18[0], _io_out_0_bits_WIRE_19 connect _io_out_0_bits_WIRE_2.`3`, _io_out_0_bits_WIRE_18 connect _io_out_0_bits_WIRE.vc_sel, _io_out_0_bits_WIRE_2 connect io.out[0].bits, _io_out_0_bits_WIRE node _T_8 = bits(chosen, 0, 0) node _T_9 = and(_T_8, io.out[0].ready) when _T_9 : connect io.in[0].ready, UInt<1>(0h1) node _T_10 = bits(chosen, 1, 1) node _T_11 = and(_T_10, io.out[0].ready) when _T_11 : connect io.in[1].ready, UInt<1>(0h1) node _T_12 = bits(chosen, 2, 2) node _T_13 = and(_T_12, io.out[0].ready) when _T_13 : connect io.in[2].ready, UInt<1>(0h1) node _T_14 = or(UInt<3>(0h0), chosen) node _T_15 = and(io.out[0].ready, io.out[0].valid) when _T_15 : node _lock_0_T = not(in_tails) node _lock_0_T_1 = and(chosen, _lock_0_T) connect lock_0, _lock_0_T_1 node _T_16 = and(io.out[0].ready, io.out[0].valid) when _T_16 : node _mask_T = shr(io.chosen_oh[0], 0) node _mask_T_1 = shr(io.chosen_oh[0], 1) node _mask_T_2 = shr(io.chosen_oh[0], 2) node _mask_T_3 = or(_mask_T, _mask_T_1) node _mask_T_4 = or(_mask_T_3, _mask_T_2) connect mask, _mask_T_4 else : node _mask_T_5 = not(mask) node _mask_T_6 = eq(_mask_T_5, UInt<1>(0h0)) node _mask_T_7 = shl(mask, 1) node _mask_T_8 = or(_mask_T_7, UInt<1>(0h1)) node _mask_T_9 = mux(_mask_T_6, UInt<1>(0h0), _mask_T_8) connect mask, _mask_T_9	module SwitchArbiter_24( // @[SwitchAllocator.scala:17:7] input clock, // @[SwitchAllocator.scala:17:7] input reset, // @[SwitchAllocator.scala:17:7] output io_in_0_ready, // @[SwitchAllocator.scala:18:14] input io_in_0_valid, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_3_0, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_0_0, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_0_1, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_0_2, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_0_3, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_0_4, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_0_5, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_0_6, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_0_7, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_0_8, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_0_9, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_tail, // @[SwitchAllocator.scala:18:14] output io_in_1_ready, // @[SwitchAllocator.scala:18:14] input io_in_1_valid, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_3_0, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_0_0, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_0_1, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_0_2, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_0_3, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_0_4, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_0_5, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_0_6, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_0_7, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_0_8, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_0_9, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_tail, // @[SwitchAllocator.scala:18:14] output io_in_2_ready, // @[SwitchAllocator.scala:18:14] input io_in_2_valid, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_3_0, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_0_0, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_0_1, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_0_2, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_0_3, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_0_4, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_0_5, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_0_6, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_0_7, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_0_8, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_0_9, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_tail, // @[SwitchAllocator.scala:18:14] output io_out_0_valid, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_3_0, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_0_0, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_0_1, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_0_2, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_0_3, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_0_4, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_0_5, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_0_6, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_0_7, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_0_8, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_0_9, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_tail, // @[SwitchAllocator.scala:18:14] output [2:0] io_chosen_oh_0 // @[SwitchAllocator.scala:18:14] ); reg [2:0] lock_0; // @[SwitchAllocator.scala:24:38] wire [2:0] unassigned = {io_in_2_valid, io_in_1_valid, io_in_0_valid} & ~lock_0; // @[SwitchAllocator.scala:24:38, :25:{23,52,54}] reg [2:0] mask; // @[SwitchAllocator.scala:27:21] wire [2:0] _sel_T_1 = unassigned & ~mask; // @[SwitchAllocator.scala:25:52, :27:21, :30:{58,60}] wire [5:0] sel = _sel_T_1[0] ? 6'h1 : _sel_T_1[1] ? 6'h2 : _sel_T_1[2] ? 6'h4 : unassigned[0] ? 6'h8 : unassigned[1] ? 6'h10 : {unassigned[2], 5'h0}; // @[OneHot.scala:85:71] wire [2:0] in_valids = {io_in_2_valid, io_in_1_valid, io_in_0_valid}; // @[SwitchAllocator.scala:41:24] wire [2:0] chosen = (\|(in_valids & lock_0)) ? lock_0 : sel[2:0] \| sel[5:3]; // @[Mux.scala:50:70] wire [2:0] _io_out_0_valid_T = in_valids & chosen; // @[SwitchAllocator.scala:41:24, :42:21, :44:35] wire [1:0] _GEN = chosen[1:0] \| chosen[2:1]; // @[SwitchAllocator.scala:42:21, :58:{55,71}] always @(posedge clock) begin // @[SwitchAllocator.scala:17:7] if (reset) begin // @[SwitchAllocator.scala:17:7] lock_0 <= 3'h0; // @[SwitchAllocator.scala:24:38] mask <= 3'h0; // @[SwitchAllocator.scala:27:21] end else begin // @[SwitchAllocator.scala:17:7] if (\|_io_out_0_valid_T) // @[SwitchAllocator.scala:44:{35,45}] lock_0 <= chosen & ~{io_in_2_bits_tail, io_in_1_bits_tail, io_in_0_bits_tail}; // @[SwitchAllocator.scala:24:38, :39:21, :42:21, :53:{25,27}] mask <= (\|_io_out_0_valid_T) ? {chosen[2], _GEN[1], _GEN[0] \| chosen[2]} : (&mask) ? 3'h0 : {mask[1:0], 1'h1}; // @[SwitchAllocator.scala:17:7, :27:21, :42:21, :44:{35,45}, :57:25, :58:{10,55,71}, :60:{10,16,23,49}] end always @(posedge)
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_304 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x	module OptimizationBarrier_TLBEntryData_304( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_257 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_257( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module FPUDecoder_1 : input clock : Clock input reset : Reset output io : { flip inst : UInt<32>, sigs : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}} wire decoder_decoded_plaInput : UInt<32> node decoder_decoded_invInputs = not(decoder_decoded_plaInput) wire decoder_decoded : UInt<19> node decoder_decoded_andMatrixOutputs_andMatrixInput_0 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2 = bits(decoder_decoded_invInputs, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_3 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_4 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_lo = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3, decoder_decoded_andMatrixOutputs_andMatrixInput_4) node decoder_decoded_andMatrixOutputs_hi_hi = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0, decoder_decoded_andMatrixOutputs_andMatrixInput_1) node decoder_decoded_andMatrixOutputs_hi = cat(decoder_decoded_andMatrixOutputs_hi_hi, decoder_decoded_andMatrixOutputs_andMatrixInput_2) node _decoder_decoded_andMatrixOutputs_T = cat(decoder_decoded_andMatrixOutputs_hi, decoder_decoded_andMatrixOutputs_lo) node decoder_decoded_andMatrixOutputs_72_2 = andr(_decoder_decoded_andMatrixOutputs_T) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_1 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_1 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_1 = bits(decoder_decoded_invInputs, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_1 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_1 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_5 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_6 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_lo_hi = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_1, decoder_decoded_andMatrixOutputs_andMatrixInput_5) node decoder_decoded_andMatrixOutputs_lo_1 = cat(decoder_decoded_andMatrixOutputs_lo_hi, decoder_decoded_andMatrixOutputs_andMatrixInput_6) node decoder_decoded_andMatrixOutputs_hi_lo = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_1, decoder_decoded_andMatrixOutputs_andMatrixInput_3_1) node decoder_decoded_andMatrixOutputs_hi_hi_1 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_1, decoder_decoded_andMatrixOutputs_andMatrixInput_1_1) node decoder_decoded_andMatrixOutputs_hi_1 = cat(decoder_decoded_andMatrixOutputs_hi_hi_1, decoder_decoded_andMatrixOutputs_hi_lo) node _decoder_decoded_andMatrixOutputs_T_1 = cat(decoder_decoded_andMatrixOutputs_hi_1, decoder_decoded_andMatrixOutputs_lo_1) node decoder_decoded_andMatrixOutputs_6_2 = andr(_decoder_decoded_andMatrixOutputs_T_1) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_2 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_2 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_2 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_2 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_2 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_1 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_1 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_8 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_9 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_10 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9, decoder_decoded_andMatrixOutputs_andMatrixInput_10) node decoder_decoded_andMatrixOutputs_lo_hi_hi = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_1, decoder_decoded_andMatrixOutputs_andMatrixInput_7) node decoder_decoded_andMatrixOutputs_lo_hi_1 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi, decoder_decoded_andMatrixOutputs_andMatrixInput_8) node decoder_decoded_andMatrixOutputs_lo_2 = cat(decoder_decoded_andMatrixOutputs_lo_hi_1, decoder_decoded_andMatrixOutputs_lo_lo) node decoder_decoded_andMatrixOutputs_hi_lo_hi = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_2, decoder_decoded_andMatrixOutputs_andMatrixInput_4_2) node decoder_decoded_andMatrixOutputs_hi_lo_1 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi, decoder_decoded_andMatrixOutputs_andMatrixInput_5_1) node decoder_decoded_andMatrixOutputs_hi_hi_hi = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_2, decoder_decoded_andMatrixOutputs_andMatrixInput_1_2) node decoder_decoded_andMatrixOutputs_hi_hi_2 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi, decoder_decoded_andMatrixOutputs_andMatrixInput_2_2) node decoder_decoded_andMatrixOutputs_hi_2 = cat(decoder_decoded_andMatrixOutputs_hi_hi_2, decoder_decoded_andMatrixOutputs_hi_lo_1) node _decoder_decoded_andMatrixOutputs_T_2 = cat(decoder_decoded_andMatrixOutputs_hi_2, decoder_decoded_andMatrixOutputs_lo_2) node decoder_decoded_andMatrixOutputs_16_2 = andr(_decoder_decoded_andMatrixOutputs_T_2) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_3 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_3 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_3 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_3 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_3 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_2 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_2 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_1 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_1 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_1 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_1 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_1 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_1, decoder_decoded_andMatrixOutputs_andMatrixInput_10_1) node decoder_decoded_andMatrixOutputs_lo_hi_hi_1 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_2, decoder_decoded_andMatrixOutputs_andMatrixInput_7_1) node decoder_decoded_andMatrixOutputs_lo_hi_2 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_1, decoder_decoded_andMatrixOutputs_andMatrixInput_8_1) node decoder_decoded_andMatrixOutputs_lo_3 = cat(decoder_decoded_andMatrixOutputs_lo_hi_2, decoder_decoded_andMatrixOutputs_lo_lo_1) node decoder_decoded_andMatrixOutputs_hi_lo_hi_1 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_3, decoder_decoded_andMatrixOutputs_andMatrixInput_4_3) node decoder_decoded_andMatrixOutputs_hi_lo_2 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_1, decoder_decoded_andMatrixOutputs_andMatrixInput_5_2) node decoder_decoded_andMatrixOutputs_hi_hi_hi_1 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_3, decoder_decoded_andMatrixOutputs_andMatrixInput_1_3) node decoder_decoded_andMatrixOutputs_hi_hi_3 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_1, decoder_decoded_andMatrixOutputs_andMatrixInput_2_3) node decoder_decoded_andMatrixOutputs_hi_3 = cat(decoder_decoded_andMatrixOutputs_hi_hi_3, decoder_decoded_andMatrixOutputs_hi_lo_2) node _decoder_decoded_andMatrixOutputs_T_3 = cat(decoder_decoded_andMatrixOutputs_hi_3, decoder_decoded_andMatrixOutputs_lo_3) node decoder_decoded_andMatrixOutputs_19_2 = andr(_decoder_decoded_andMatrixOutputs_T_3) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_4 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_4 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_4 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_4 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_4 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_3 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_3 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_2 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_2 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_2 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_2 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_11 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_2, decoder_decoded_andMatrixOutputs_andMatrixInput_10_2) node decoder_decoded_andMatrixOutputs_lo_lo_2 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi, decoder_decoded_andMatrixOutputs_andMatrixInput_11) node decoder_decoded_andMatrixOutputs_lo_hi_hi_2 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_3, decoder_decoded_andMatrixOutputs_andMatrixInput_7_2) node decoder_decoded_andMatrixOutputs_lo_hi_3 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_2, decoder_decoded_andMatrixOutputs_andMatrixInput_8_2) node decoder_decoded_andMatrixOutputs_lo_4 = cat(decoder_decoded_andMatrixOutputs_lo_hi_3, decoder_decoded_andMatrixOutputs_lo_lo_2) node decoder_decoded_andMatrixOutputs_hi_lo_hi_2 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_4, decoder_decoded_andMatrixOutputs_andMatrixInput_4_4) node decoder_decoded_andMatrixOutputs_hi_lo_3 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_2, decoder_decoded_andMatrixOutputs_andMatrixInput_5_3) node decoder_decoded_andMatrixOutputs_hi_hi_hi_2 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_4, decoder_decoded_andMatrixOutputs_andMatrixInput_1_4) node decoder_decoded_andMatrixOutputs_hi_hi_4 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_2, decoder_decoded_andMatrixOutputs_andMatrixInput_2_4) node decoder_decoded_andMatrixOutputs_hi_4 = cat(decoder_decoded_andMatrixOutputs_hi_hi_4, decoder_decoded_andMatrixOutputs_hi_lo_3) node _decoder_decoded_andMatrixOutputs_T_4 = cat(decoder_decoded_andMatrixOutputs_hi_4, decoder_decoded_andMatrixOutputs_lo_4) node decoder_decoded_andMatrixOutputs_55_2 = andr(_decoder_decoded_andMatrixOutputs_T_4) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_5 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_5 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_5 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_5 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_5 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_4 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_4 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_3 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_3 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_3 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_3 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_1 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_1 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_3, decoder_decoded_andMatrixOutputs_andMatrixInput_10_3) node decoder_decoded_andMatrixOutputs_lo_lo_3 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_1, decoder_decoded_andMatrixOutputs_andMatrixInput_11_1) node decoder_decoded_andMatrixOutputs_lo_hi_hi_3 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_4, decoder_decoded_andMatrixOutputs_andMatrixInput_7_3) node decoder_decoded_andMatrixOutputs_lo_hi_4 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_3, decoder_decoded_andMatrixOutputs_andMatrixInput_8_3) node decoder_decoded_andMatrixOutputs_lo_5 = cat(decoder_decoded_andMatrixOutputs_lo_hi_4, decoder_decoded_andMatrixOutputs_lo_lo_3) node decoder_decoded_andMatrixOutputs_hi_lo_hi_3 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_5, decoder_decoded_andMatrixOutputs_andMatrixInput_4_5) node decoder_decoded_andMatrixOutputs_hi_lo_4 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_3, decoder_decoded_andMatrixOutputs_andMatrixInput_5_4) node decoder_decoded_andMatrixOutputs_hi_hi_hi_3 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_5, decoder_decoded_andMatrixOutputs_andMatrixInput_1_5) node decoder_decoded_andMatrixOutputs_hi_hi_5 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_3, decoder_decoded_andMatrixOutputs_andMatrixInput_2_5) node decoder_decoded_andMatrixOutputs_hi_5 = cat(decoder_decoded_andMatrixOutputs_hi_hi_5, decoder_decoded_andMatrixOutputs_hi_lo_4) node _decoder_decoded_andMatrixOutputs_T_5 = cat(decoder_decoded_andMatrixOutputs_hi_5, decoder_decoded_andMatrixOutputs_lo_5) node decoder_decoded_andMatrixOutputs_18_2 = andr(_decoder_decoded_andMatrixOutputs_T_5) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_6 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_6 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_6 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_6 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_6 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_5 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_5 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_4 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_4 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_4 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_4 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_2 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_2 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_4, decoder_decoded_andMatrixOutputs_andMatrixInput_10_4) node decoder_decoded_andMatrixOutputs_lo_lo_4 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_2, decoder_decoded_andMatrixOutputs_andMatrixInput_11_2) node decoder_decoded_andMatrixOutputs_lo_hi_hi_4 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_5, decoder_decoded_andMatrixOutputs_andMatrixInput_7_4) node decoder_decoded_andMatrixOutputs_lo_hi_5 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_4, decoder_decoded_andMatrixOutputs_andMatrixInput_8_4) node decoder_decoded_andMatrixOutputs_lo_6 = cat(decoder_decoded_andMatrixOutputs_lo_hi_5, decoder_decoded_andMatrixOutputs_lo_lo_4) node decoder_decoded_andMatrixOutputs_hi_lo_hi_4 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_6, decoder_decoded_andMatrixOutputs_andMatrixInput_4_6) node decoder_decoded_andMatrixOutputs_hi_lo_5 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_4, decoder_decoded_andMatrixOutputs_andMatrixInput_5_5) node decoder_decoded_andMatrixOutputs_hi_hi_hi_4 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_6, decoder_decoded_andMatrixOutputs_andMatrixInput_1_6) node decoder_decoded_andMatrixOutputs_hi_hi_6 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_4, decoder_decoded_andMatrixOutputs_andMatrixInput_2_6) node decoder_decoded_andMatrixOutputs_hi_6 = cat(decoder_decoded_andMatrixOutputs_hi_hi_6, decoder_decoded_andMatrixOutputs_hi_lo_5) node _decoder_decoded_andMatrixOutputs_T_6 = cat(decoder_decoded_andMatrixOutputs_hi_6, decoder_decoded_andMatrixOutputs_lo_6) node decoder_decoded_andMatrixOutputs_8_2 = andr(_decoder_decoded_andMatrixOutputs_T_6) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_7 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_7 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_7 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_7 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_7 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_6 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_6 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_5 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_5 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_5 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_5 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_3 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_3 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_5, decoder_decoded_andMatrixOutputs_andMatrixInput_10_5) node decoder_decoded_andMatrixOutputs_lo_lo_5 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_3, decoder_decoded_andMatrixOutputs_andMatrixInput_11_3) node decoder_decoded_andMatrixOutputs_lo_hi_hi_5 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_6, decoder_decoded_andMatrixOutputs_andMatrixInput_7_5) node decoder_decoded_andMatrixOutputs_lo_hi_6 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_5, decoder_decoded_andMatrixOutputs_andMatrixInput_8_5) node decoder_decoded_andMatrixOutputs_lo_7 = cat(decoder_decoded_andMatrixOutputs_lo_hi_6, decoder_decoded_andMatrixOutputs_lo_lo_5) node decoder_decoded_andMatrixOutputs_hi_lo_hi_5 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_7, decoder_decoded_andMatrixOutputs_andMatrixInput_4_7) node decoder_decoded_andMatrixOutputs_hi_lo_6 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_5, decoder_decoded_andMatrixOutputs_andMatrixInput_5_6) node decoder_decoded_andMatrixOutputs_hi_hi_hi_5 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_7, decoder_decoded_andMatrixOutputs_andMatrixInput_1_7) node decoder_decoded_andMatrixOutputs_hi_hi_7 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_5, decoder_decoded_andMatrixOutputs_andMatrixInput_2_7) node decoder_decoded_andMatrixOutputs_hi_7 = cat(decoder_decoded_andMatrixOutputs_hi_hi_7, decoder_decoded_andMatrixOutputs_hi_lo_6) node _decoder_decoded_andMatrixOutputs_T_7 = cat(decoder_decoded_andMatrixOutputs_hi_7, decoder_decoded_andMatrixOutputs_lo_7) node decoder_decoded_andMatrixOutputs_41_2 = andr(_decoder_decoded_andMatrixOutputs_T_7) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_8 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_8 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_8 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_8 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_8 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_7 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_7 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_6 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_6 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_6 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_6 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_4 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_4 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_6, decoder_decoded_andMatrixOutputs_andMatrixInput_10_6) node decoder_decoded_andMatrixOutputs_lo_lo_6 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_4, decoder_decoded_andMatrixOutputs_andMatrixInput_11_4) node decoder_decoded_andMatrixOutputs_lo_hi_hi_6 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_7, decoder_decoded_andMatrixOutputs_andMatrixInput_7_6) node decoder_decoded_andMatrixOutputs_lo_hi_7 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_6, decoder_decoded_andMatrixOutputs_andMatrixInput_8_6) node decoder_decoded_andMatrixOutputs_lo_8 = cat(decoder_decoded_andMatrixOutputs_lo_hi_7, decoder_decoded_andMatrixOutputs_lo_lo_6) node decoder_decoded_andMatrixOutputs_hi_lo_hi_6 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_8, decoder_decoded_andMatrixOutputs_andMatrixInput_4_8) node decoder_decoded_andMatrixOutputs_hi_lo_7 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_6, decoder_decoded_andMatrixOutputs_andMatrixInput_5_7) node decoder_decoded_andMatrixOutputs_hi_hi_hi_6 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_8, decoder_decoded_andMatrixOutputs_andMatrixInput_1_8) node decoder_decoded_andMatrixOutputs_hi_hi_8 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_6, decoder_decoded_andMatrixOutputs_andMatrixInput_2_8) node decoder_decoded_andMatrixOutputs_hi_8 = cat(decoder_decoded_andMatrixOutputs_hi_hi_8, decoder_decoded_andMatrixOutputs_hi_lo_7) node _decoder_decoded_andMatrixOutputs_T_8 = cat(decoder_decoded_andMatrixOutputs_hi_8, decoder_decoded_andMatrixOutputs_lo_8) node decoder_decoded_andMatrixOutputs_74_2 = andr(_decoder_decoded_andMatrixOutputs_T_8) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_9 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_9 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_9 = bits(decoder_decoded_plaInput, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_9 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_9 = bits(decoder_decoded_invInputs, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_8 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_8 = bits(decoder_decoded_plaInput, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_7 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_lo_lo_7 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_8, decoder_decoded_andMatrixOutputs_andMatrixInput_7_7) node decoder_decoded_andMatrixOutputs_lo_hi_8 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_9, decoder_decoded_andMatrixOutputs_andMatrixInput_5_8) node decoder_decoded_andMatrixOutputs_lo_9 = cat(decoder_decoded_andMatrixOutputs_lo_hi_8, decoder_decoded_andMatrixOutputs_lo_lo_7) node decoder_decoded_andMatrixOutputs_hi_lo_8 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_9, decoder_decoded_andMatrixOutputs_andMatrixInput_3_9) node decoder_decoded_andMatrixOutputs_hi_hi_9 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_9, decoder_decoded_andMatrixOutputs_andMatrixInput_1_9) node decoder_decoded_andMatrixOutputs_hi_9 = cat(decoder_decoded_andMatrixOutputs_hi_hi_9, decoder_decoded_andMatrixOutputs_hi_lo_8) node _decoder_decoded_andMatrixOutputs_T_9 = cat(decoder_decoded_andMatrixOutputs_hi_9, decoder_decoded_andMatrixOutputs_lo_9) node decoder_decoded_andMatrixOutputs_71_2 = andr(_decoder_decoded_andMatrixOutputs_T_9) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_10 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_10 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_10 = bits(decoder_decoded_plaInput, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_10 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_10 = bits(decoder_decoded_invInputs, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_9 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_9 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_8 = bits(decoder_decoded_plaInput, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_7 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_lo_lo_8 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_8, decoder_decoded_andMatrixOutputs_andMatrixInput_8_7) node decoder_decoded_andMatrixOutputs_lo_hi_9 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_9, decoder_decoded_andMatrixOutputs_andMatrixInput_6_9) node decoder_decoded_andMatrixOutputs_lo_10 = cat(decoder_decoded_andMatrixOutputs_lo_hi_9, decoder_decoded_andMatrixOutputs_lo_lo_8) node decoder_decoded_andMatrixOutputs_hi_lo_9 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_10, decoder_decoded_andMatrixOutputs_andMatrixInput_4_10) node decoder_decoded_andMatrixOutputs_hi_hi_hi_7 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_10, decoder_decoded_andMatrixOutputs_andMatrixInput_1_10) node decoder_decoded_andMatrixOutputs_hi_hi_10 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_7, decoder_decoded_andMatrixOutputs_andMatrixInput_2_10) node decoder_decoded_andMatrixOutputs_hi_10 = cat(decoder_decoded_andMatrixOutputs_hi_hi_10, decoder_decoded_andMatrixOutputs_hi_lo_9) node _decoder_decoded_andMatrixOutputs_T_10 = cat(decoder_decoded_andMatrixOutputs_hi_10, decoder_decoded_andMatrixOutputs_lo_10) node decoder_decoded_andMatrixOutputs_30_2 = andr(_decoder_decoded_andMatrixOutputs_T_10) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_11 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_11 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_11 = bits(decoder_decoded_plaInput, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_11 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_11 = bits(decoder_decoded_invInputs, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_10 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_10 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_9 = bits(decoder_decoded_plaInput, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_8 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_lo_lo_9 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_9, decoder_decoded_andMatrixOutputs_andMatrixInput_8_8) node decoder_decoded_andMatrixOutputs_lo_hi_10 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_10, decoder_decoded_andMatrixOutputs_andMatrixInput_6_10) node decoder_decoded_andMatrixOutputs_lo_11 = cat(decoder_decoded_andMatrixOutputs_lo_hi_10, decoder_decoded_andMatrixOutputs_lo_lo_9) node decoder_decoded_andMatrixOutputs_hi_lo_10 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_11, decoder_decoded_andMatrixOutputs_andMatrixInput_4_11) node decoder_decoded_andMatrixOutputs_hi_hi_hi_8 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_11, decoder_decoded_andMatrixOutputs_andMatrixInput_1_11) node decoder_decoded_andMatrixOutputs_hi_hi_11 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_8, decoder_decoded_andMatrixOutputs_andMatrixInput_2_11) node decoder_decoded_andMatrixOutputs_hi_11 = cat(decoder_decoded_andMatrixOutputs_hi_hi_11, decoder_decoded_andMatrixOutputs_hi_lo_10) node _decoder_decoded_andMatrixOutputs_T_11 = cat(decoder_decoded_andMatrixOutputs_hi_11, decoder_decoded_andMatrixOutputs_lo_11) node decoder_decoded_andMatrixOutputs_66_2 = andr(_decoder_decoded_andMatrixOutputs_T_11) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_12 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_12 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_12 = bits(decoder_decoded_plaInput, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_12 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_12 = bits(decoder_decoded_invInputs, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_11 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_11 = bits(decoder_decoded_plaInput, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_10 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_lo_lo_10 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_11, decoder_decoded_andMatrixOutputs_andMatrixInput_7_10) node decoder_decoded_andMatrixOutputs_lo_hi_11 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_12, decoder_decoded_andMatrixOutputs_andMatrixInput_5_11) node decoder_decoded_andMatrixOutputs_lo_12 = cat(decoder_decoded_andMatrixOutputs_lo_hi_11, decoder_decoded_andMatrixOutputs_lo_lo_10) node decoder_decoded_andMatrixOutputs_hi_lo_11 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_12, decoder_decoded_andMatrixOutputs_andMatrixInput_3_12) node decoder_decoded_andMatrixOutputs_hi_hi_12 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_12, decoder_decoded_andMatrixOutputs_andMatrixInput_1_12) node decoder_decoded_andMatrixOutputs_hi_12 = cat(decoder_decoded_andMatrixOutputs_hi_hi_12, decoder_decoded_andMatrixOutputs_hi_lo_11) node _decoder_decoded_andMatrixOutputs_T_12 = cat(decoder_decoded_andMatrixOutputs_hi_12, decoder_decoded_andMatrixOutputs_lo_12) node decoder_decoded_andMatrixOutputs_75_2 = andr(_decoder_decoded_andMatrixOutputs_T_12) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_13 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_13 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_13 = bits(decoder_decoded_plaInput, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_13 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_13 = bits(decoder_decoded_invInputs, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_12 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_12 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_11 = bits(decoder_decoded_plaInput, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_9 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_lo_lo_11 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_11, decoder_decoded_andMatrixOutputs_andMatrixInput_8_9) node decoder_decoded_andMatrixOutputs_lo_hi_12 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_12, decoder_decoded_andMatrixOutputs_andMatrixInput_6_12) node decoder_decoded_andMatrixOutputs_lo_13 = cat(decoder_decoded_andMatrixOutputs_lo_hi_12, decoder_decoded_andMatrixOutputs_lo_lo_11) node decoder_decoded_andMatrixOutputs_hi_lo_12 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_13, decoder_decoded_andMatrixOutputs_andMatrixInput_4_13) node decoder_decoded_andMatrixOutputs_hi_hi_hi_9 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_13, decoder_decoded_andMatrixOutputs_andMatrixInput_1_13) node decoder_decoded_andMatrixOutputs_hi_hi_13 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_9, decoder_decoded_andMatrixOutputs_andMatrixInput_2_13) node decoder_decoded_andMatrixOutputs_hi_13 = cat(decoder_decoded_andMatrixOutputs_hi_hi_13, decoder_decoded_andMatrixOutputs_hi_lo_12) node _decoder_decoded_andMatrixOutputs_T_13 = cat(decoder_decoded_andMatrixOutputs_hi_13, decoder_decoded_andMatrixOutputs_lo_13) node decoder_decoded_andMatrixOutputs_37_2 = andr(_decoder_decoded_andMatrixOutputs_T_13) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_14 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_14 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_14 = bits(decoder_decoded_plaInput, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_14 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_14 = bits(decoder_decoded_invInputs, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_13 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_13 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_12 = bits(decoder_decoded_plaInput, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_10 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_lo_lo_12 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_12, decoder_decoded_andMatrixOutputs_andMatrixInput_8_10) node decoder_decoded_andMatrixOutputs_lo_hi_13 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_13, decoder_decoded_andMatrixOutputs_andMatrixInput_6_13) node decoder_decoded_andMatrixOutputs_lo_14 = cat(decoder_decoded_andMatrixOutputs_lo_hi_13, decoder_decoded_andMatrixOutputs_lo_lo_12) node decoder_decoded_andMatrixOutputs_hi_lo_13 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_14, decoder_decoded_andMatrixOutputs_andMatrixInput_4_14) node decoder_decoded_andMatrixOutputs_hi_hi_hi_10 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_14, decoder_decoded_andMatrixOutputs_andMatrixInput_1_14) node decoder_decoded_andMatrixOutputs_hi_hi_14 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_10, decoder_decoded_andMatrixOutputs_andMatrixInput_2_14) node decoder_decoded_andMatrixOutputs_hi_14 = cat(decoder_decoded_andMatrixOutputs_hi_hi_14, decoder_decoded_andMatrixOutputs_hi_lo_13) node _decoder_decoded_andMatrixOutputs_T_14 = cat(decoder_decoded_andMatrixOutputs_hi_14, decoder_decoded_andMatrixOutputs_lo_14) node decoder_decoded_andMatrixOutputs_47_2 = andr(_decoder_decoded_andMatrixOutputs_T_14) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_15 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_15 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_15 = bits(decoder_decoded_plaInput, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_15 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_15 = bits(decoder_decoded_invInputs, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_14 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_14 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_13 = bits(decoder_decoded_invInputs, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_11 = bits(decoder_decoded_plaInput, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_7 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_lo_lo_13 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_11, decoder_decoded_andMatrixOutputs_andMatrixInput_9_7) node decoder_decoded_andMatrixOutputs_lo_hi_hi_7 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_14, decoder_decoded_andMatrixOutputs_andMatrixInput_6_14) node decoder_decoded_andMatrixOutputs_lo_hi_14 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_7, decoder_decoded_andMatrixOutputs_andMatrixInput_7_13) node decoder_decoded_andMatrixOutputs_lo_15 = cat(decoder_decoded_andMatrixOutputs_lo_hi_14, decoder_decoded_andMatrixOutputs_lo_lo_13) node decoder_decoded_andMatrixOutputs_hi_lo_14 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_15, decoder_decoded_andMatrixOutputs_andMatrixInput_4_15) node decoder_decoded_andMatrixOutputs_hi_hi_hi_11 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_15, decoder_decoded_andMatrixOutputs_andMatrixInput_1_15) node decoder_decoded_andMatrixOutputs_hi_hi_15 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_11, decoder_decoded_andMatrixOutputs_andMatrixInput_2_15) node decoder_decoded_andMatrixOutputs_hi_15 = cat(decoder_decoded_andMatrixOutputs_hi_hi_15, decoder_decoded_andMatrixOutputs_hi_lo_14) node _decoder_decoded_andMatrixOutputs_T_15 = cat(decoder_decoded_andMatrixOutputs_hi_15, decoder_decoded_andMatrixOutputs_lo_15) node decoder_decoded_andMatrixOutputs_60_2 = andr(_decoder_decoded_andMatrixOutputs_T_15) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_16 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_16 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_16 = bits(decoder_decoded_plaInput, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_16 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_16 = bits(decoder_decoded_invInputs, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_15 = bits(decoder_decoded_plaInput, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_15 = bits(decoder_decoded_invInputs, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_14 = bits(decoder_decoded_plaInput, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_12 = bits(decoder_decoded_plaInput, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_8 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_lo_lo_14 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_12, decoder_decoded_andMatrixOutputs_andMatrixInput_9_8) node decoder_decoded_andMatrixOutputs_lo_hi_hi_8 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_15, decoder_decoded_andMatrixOutputs_andMatrixInput_6_15) node decoder_decoded_andMatrixOutputs_lo_hi_15 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_8, decoder_decoded_andMatrixOutputs_andMatrixInput_7_14) node decoder_decoded_andMatrixOutputs_lo_16 = cat(decoder_decoded_andMatrixOutputs_lo_hi_15, decoder_decoded_andMatrixOutputs_lo_lo_14) node decoder_decoded_andMatrixOutputs_hi_lo_15 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_16, decoder_decoded_andMatrixOutputs_andMatrixInput_4_16) node decoder_decoded_andMatrixOutputs_hi_hi_hi_12 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_16, decoder_decoded_andMatrixOutputs_andMatrixInput_1_16) node decoder_decoded_andMatrixOutputs_hi_hi_16 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_12, decoder_decoded_andMatrixOutputs_andMatrixInput_2_16) node decoder_decoded_andMatrixOutputs_hi_16 = cat(decoder_decoded_andMatrixOutputs_hi_hi_16, decoder_decoded_andMatrixOutputs_hi_lo_15) node _decoder_decoded_andMatrixOutputs_T_16 = cat(decoder_decoded_andMatrixOutputs_hi_16, decoder_decoded_andMatrixOutputs_lo_16) node decoder_decoded_andMatrixOutputs_15_2 = andr(_decoder_decoded_andMatrixOutputs_T_16) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_17 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_17 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_17 = bits(decoder_decoded_invInputs, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_17 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_17 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_16 = bits(decoder_decoded_plaInput, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_16 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_lo_hi_16 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_17, decoder_decoded_andMatrixOutputs_andMatrixInput_5_16) node decoder_decoded_andMatrixOutputs_lo_17 = cat(decoder_decoded_andMatrixOutputs_lo_hi_16, decoder_decoded_andMatrixOutputs_andMatrixInput_6_16) node decoder_decoded_andMatrixOutputs_hi_lo_16 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_17, decoder_decoded_andMatrixOutputs_andMatrixInput_3_17) node decoder_decoded_andMatrixOutputs_hi_hi_17 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_17, decoder_decoded_andMatrixOutputs_andMatrixInput_1_17) node decoder_decoded_andMatrixOutputs_hi_17 = cat(decoder_decoded_andMatrixOutputs_hi_hi_17, decoder_decoded_andMatrixOutputs_hi_lo_16) node _decoder_decoded_andMatrixOutputs_T_17 = cat(decoder_decoded_andMatrixOutputs_hi_17, decoder_decoded_andMatrixOutputs_lo_17) node decoder_decoded_andMatrixOutputs_29_2 = andr(_decoder_decoded_andMatrixOutputs_T_17) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_18 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_18 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_18 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_18 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_18 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_17 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_17 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_15 = bits(decoder_decoded_plaInput, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_13 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_9 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_7 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_5 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_5 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_9, decoder_decoded_andMatrixOutputs_andMatrixInput_10_7) node decoder_decoded_andMatrixOutputs_lo_lo_15 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_5, decoder_decoded_andMatrixOutputs_andMatrixInput_11_5) node decoder_decoded_andMatrixOutputs_lo_hi_hi_9 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_17, decoder_decoded_andMatrixOutputs_andMatrixInput_7_15) node decoder_decoded_andMatrixOutputs_lo_hi_17 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_9, decoder_decoded_andMatrixOutputs_andMatrixInput_8_13) node decoder_decoded_andMatrixOutputs_lo_18 = cat(decoder_decoded_andMatrixOutputs_lo_hi_17, decoder_decoded_andMatrixOutputs_lo_lo_15) node decoder_decoded_andMatrixOutputs_hi_lo_hi_7 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_18, decoder_decoded_andMatrixOutputs_andMatrixInput_4_18) node decoder_decoded_andMatrixOutputs_hi_lo_17 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_7, decoder_decoded_andMatrixOutputs_andMatrixInput_5_17) node decoder_decoded_andMatrixOutputs_hi_hi_hi_13 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_18, decoder_decoded_andMatrixOutputs_andMatrixInput_1_18) node decoder_decoded_andMatrixOutputs_hi_hi_18 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_13, decoder_decoded_andMatrixOutputs_andMatrixInput_2_18) node decoder_decoded_andMatrixOutputs_hi_18 = cat(decoder_decoded_andMatrixOutputs_hi_hi_18, decoder_decoded_andMatrixOutputs_hi_lo_17) node _decoder_decoded_andMatrixOutputs_T_18 = cat(decoder_decoded_andMatrixOutputs_hi_18, decoder_decoded_andMatrixOutputs_lo_18) node decoder_decoded_andMatrixOutputs_39_2 = andr(_decoder_decoded_andMatrixOutputs_T_18) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_19 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_19 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_19 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_19 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_19 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_18 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_18 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_16 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_14 = bits(decoder_decoded_plaInput, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_10 = bits(decoder_decoded_plaInput, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_8 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_6 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_12 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_6 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_8, decoder_decoded_andMatrixOutputs_andMatrixInput_11_6) node decoder_decoded_andMatrixOutputs_lo_lo_16 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_6, decoder_decoded_andMatrixOutputs_andMatrixInput_12) node decoder_decoded_andMatrixOutputs_lo_hi_hi_10 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_16, decoder_decoded_andMatrixOutputs_andMatrixInput_8_14) node decoder_decoded_andMatrixOutputs_lo_hi_18 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_10, decoder_decoded_andMatrixOutputs_andMatrixInput_9_10) node decoder_decoded_andMatrixOutputs_lo_19 = cat(decoder_decoded_andMatrixOutputs_lo_hi_18, decoder_decoded_andMatrixOutputs_lo_lo_16) node decoder_decoded_andMatrixOutputs_hi_lo_hi_8 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_19, decoder_decoded_andMatrixOutputs_andMatrixInput_5_18) node decoder_decoded_andMatrixOutputs_hi_lo_18 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_8, decoder_decoded_andMatrixOutputs_andMatrixInput_6_18) node decoder_decoded_andMatrixOutputs_hi_hi_lo = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_19, decoder_decoded_andMatrixOutputs_andMatrixInput_3_19) node decoder_decoded_andMatrixOutputs_hi_hi_hi_14 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_19, decoder_decoded_andMatrixOutputs_andMatrixInput_1_19) node decoder_decoded_andMatrixOutputs_hi_hi_19 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_14, decoder_decoded_andMatrixOutputs_hi_hi_lo) node decoder_decoded_andMatrixOutputs_hi_19 = cat(decoder_decoded_andMatrixOutputs_hi_hi_19, decoder_decoded_andMatrixOutputs_hi_lo_18) node _decoder_decoded_andMatrixOutputs_T_19 = cat(decoder_decoded_andMatrixOutputs_hi_19, decoder_decoded_andMatrixOutputs_lo_19) node decoder_decoded_andMatrixOutputs_69_2 = andr(_decoder_decoded_andMatrixOutputs_T_19) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_20 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_20 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_20 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_20 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_20 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_19 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_19 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_17 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_15 = bits(decoder_decoded_plaInput, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_11 = bits(decoder_decoded_plaInput, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_9 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_7 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_1 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_7 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_9, decoder_decoded_andMatrixOutputs_andMatrixInput_11_7) node decoder_decoded_andMatrixOutputs_lo_lo_17 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_7, decoder_decoded_andMatrixOutputs_andMatrixInput_12_1) node decoder_decoded_andMatrixOutputs_lo_hi_hi_11 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_17, decoder_decoded_andMatrixOutputs_andMatrixInput_8_15) node decoder_decoded_andMatrixOutputs_lo_hi_19 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_11, decoder_decoded_andMatrixOutputs_andMatrixInput_9_11) node decoder_decoded_andMatrixOutputs_lo_20 = cat(decoder_decoded_andMatrixOutputs_lo_hi_19, decoder_decoded_andMatrixOutputs_lo_lo_17) node decoder_decoded_andMatrixOutputs_hi_lo_hi_9 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_20, decoder_decoded_andMatrixOutputs_andMatrixInput_5_19) node decoder_decoded_andMatrixOutputs_hi_lo_19 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_9, decoder_decoded_andMatrixOutputs_andMatrixInput_6_19) node decoder_decoded_andMatrixOutputs_hi_hi_lo_1 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_20, decoder_decoded_andMatrixOutputs_andMatrixInput_3_20) node decoder_decoded_andMatrixOutputs_hi_hi_hi_15 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_20, decoder_decoded_andMatrixOutputs_andMatrixInput_1_20) node decoder_decoded_andMatrixOutputs_hi_hi_20 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_15, decoder_decoded_andMatrixOutputs_hi_hi_lo_1) node decoder_decoded_andMatrixOutputs_hi_20 = cat(decoder_decoded_andMatrixOutputs_hi_hi_20, decoder_decoded_andMatrixOutputs_hi_lo_19) node _decoder_decoded_andMatrixOutputs_T_20 = cat(decoder_decoded_andMatrixOutputs_hi_20, decoder_decoded_andMatrixOutputs_lo_20) node decoder_decoded_andMatrixOutputs_42_2 = andr(_decoder_decoded_andMatrixOutputs_T_20) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_21 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_21 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_21 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_21 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_21 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_20 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_20 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_18 = bits(decoder_decoded_invInputs, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_16 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_12 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_10 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_8 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_2 = bits(decoder_decoded_plaInput, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_13 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_lo_lo_hi_8 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_8, decoder_decoded_andMatrixOutputs_andMatrixInput_12_2) node decoder_decoded_andMatrixOutputs_lo_lo_18 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_8, decoder_decoded_andMatrixOutputs_andMatrixInput_13) node decoder_decoded_andMatrixOutputs_lo_hi_lo = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_12, decoder_decoded_andMatrixOutputs_andMatrixInput_10_10) node decoder_decoded_andMatrixOutputs_lo_hi_hi_12 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_18, decoder_decoded_andMatrixOutputs_andMatrixInput_8_16) node decoder_decoded_andMatrixOutputs_lo_hi_20 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_12, decoder_decoded_andMatrixOutputs_lo_hi_lo) node decoder_decoded_andMatrixOutputs_lo_21 = cat(decoder_decoded_andMatrixOutputs_lo_hi_20, decoder_decoded_andMatrixOutputs_lo_lo_18) node decoder_decoded_andMatrixOutputs_hi_lo_hi_10 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_21, decoder_decoded_andMatrixOutputs_andMatrixInput_5_20) node decoder_decoded_andMatrixOutputs_hi_lo_20 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_10, decoder_decoded_andMatrixOutputs_andMatrixInput_6_20) node decoder_decoded_andMatrixOutputs_hi_hi_lo_2 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_21, decoder_decoded_andMatrixOutputs_andMatrixInput_3_21) node decoder_decoded_andMatrixOutputs_hi_hi_hi_16 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_21, decoder_decoded_andMatrixOutputs_andMatrixInput_1_21) node decoder_decoded_andMatrixOutputs_hi_hi_21 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_16, decoder_decoded_andMatrixOutputs_hi_hi_lo_2) node decoder_decoded_andMatrixOutputs_hi_21 = cat(decoder_decoded_andMatrixOutputs_hi_hi_21, decoder_decoded_andMatrixOutputs_hi_lo_20) node _decoder_decoded_andMatrixOutputs_T_21 = cat(decoder_decoded_andMatrixOutputs_hi_21, decoder_decoded_andMatrixOutputs_lo_21) node decoder_decoded_andMatrixOutputs_49_2 = andr(_decoder_decoded_andMatrixOutputs_T_21) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_22 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_22 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_22 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_22 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_22 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_21 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_21 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_19 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_17 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_13 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_11 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_9 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_3 = bits(decoder_decoded_plaInput, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_1 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_lo_lo_hi_9 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_9, decoder_decoded_andMatrixOutputs_andMatrixInput_12_3) node decoder_decoded_andMatrixOutputs_lo_lo_19 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_9, decoder_decoded_andMatrixOutputs_andMatrixInput_13_1) node decoder_decoded_andMatrixOutputs_lo_hi_lo_1 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_13, decoder_decoded_andMatrixOutputs_andMatrixInput_10_11) node decoder_decoded_andMatrixOutputs_lo_hi_hi_13 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_19, decoder_decoded_andMatrixOutputs_andMatrixInput_8_17) node decoder_decoded_andMatrixOutputs_lo_hi_21 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_13, decoder_decoded_andMatrixOutputs_lo_hi_lo_1) node decoder_decoded_andMatrixOutputs_lo_22 = cat(decoder_decoded_andMatrixOutputs_lo_hi_21, decoder_decoded_andMatrixOutputs_lo_lo_19) node decoder_decoded_andMatrixOutputs_hi_lo_hi_11 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_22, decoder_decoded_andMatrixOutputs_andMatrixInput_5_21) node decoder_decoded_andMatrixOutputs_hi_lo_21 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_11, decoder_decoded_andMatrixOutputs_andMatrixInput_6_21) node decoder_decoded_andMatrixOutputs_hi_hi_lo_3 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_22, decoder_decoded_andMatrixOutputs_andMatrixInput_3_22) node decoder_decoded_andMatrixOutputs_hi_hi_hi_17 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_22, decoder_decoded_andMatrixOutputs_andMatrixInput_1_22) node decoder_decoded_andMatrixOutputs_hi_hi_22 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_17, decoder_decoded_andMatrixOutputs_hi_hi_lo_3) node decoder_decoded_andMatrixOutputs_hi_22 = cat(decoder_decoded_andMatrixOutputs_hi_hi_22, decoder_decoded_andMatrixOutputs_hi_lo_21) node _decoder_decoded_andMatrixOutputs_T_22 = cat(decoder_decoded_andMatrixOutputs_hi_22, decoder_decoded_andMatrixOutputs_lo_22) node decoder_decoded_andMatrixOutputs_24_2 = andr(_decoder_decoded_andMatrixOutputs_T_22) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_23 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_23 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_23 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_23 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_23 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_22 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_22 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_20 = bits(decoder_decoded_invInputs, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_18 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_14 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_12 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_10 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_4 = bits(decoder_decoded_plaInput, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_2 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_lo_lo_hi_10 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_10, decoder_decoded_andMatrixOutputs_andMatrixInput_12_4) node decoder_decoded_andMatrixOutputs_lo_lo_20 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_10, decoder_decoded_andMatrixOutputs_andMatrixInput_13_2) node decoder_decoded_andMatrixOutputs_lo_hi_lo_2 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_14, decoder_decoded_andMatrixOutputs_andMatrixInput_10_12) node decoder_decoded_andMatrixOutputs_lo_hi_hi_14 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_20, decoder_decoded_andMatrixOutputs_andMatrixInput_8_18) node decoder_decoded_andMatrixOutputs_lo_hi_22 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_14, decoder_decoded_andMatrixOutputs_lo_hi_lo_2) node decoder_decoded_andMatrixOutputs_lo_23 = cat(decoder_decoded_andMatrixOutputs_lo_hi_22, decoder_decoded_andMatrixOutputs_lo_lo_20) node decoder_decoded_andMatrixOutputs_hi_lo_hi_12 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_23, decoder_decoded_andMatrixOutputs_andMatrixInput_5_22) node decoder_decoded_andMatrixOutputs_hi_lo_22 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_12, decoder_decoded_andMatrixOutputs_andMatrixInput_6_22) node decoder_decoded_andMatrixOutputs_hi_hi_lo_4 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_23, decoder_decoded_andMatrixOutputs_andMatrixInput_3_23) node decoder_decoded_andMatrixOutputs_hi_hi_hi_18 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_23, decoder_decoded_andMatrixOutputs_andMatrixInput_1_23) node decoder_decoded_andMatrixOutputs_hi_hi_23 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_18, decoder_decoded_andMatrixOutputs_hi_hi_lo_4) node decoder_decoded_andMatrixOutputs_hi_23 = cat(decoder_decoded_andMatrixOutputs_hi_hi_23, decoder_decoded_andMatrixOutputs_hi_lo_22) node _decoder_decoded_andMatrixOutputs_T_23 = cat(decoder_decoded_andMatrixOutputs_hi_23, decoder_decoded_andMatrixOutputs_lo_23) node decoder_decoded_andMatrixOutputs_9_2 = andr(_decoder_decoded_andMatrixOutputs_T_23) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_24 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_24 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_24 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_24 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_24 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_23 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_23 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_21 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_19 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_15 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_13 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_11 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_5 = bits(decoder_decoded_plaInput, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_3 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_lo_lo_hi_11 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_11, decoder_decoded_andMatrixOutputs_andMatrixInput_12_5) node decoder_decoded_andMatrixOutputs_lo_lo_21 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_11, decoder_decoded_andMatrixOutputs_andMatrixInput_13_3) node decoder_decoded_andMatrixOutputs_lo_hi_lo_3 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_15, decoder_decoded_andMatrixOutputs_andMatrixInput_10_13) node decoder_decoded_andMatrixOutputs_lo_hi_hi_15 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_21, decoder_decoded_andMatrixOutputs_andMatrixInput_8_19) node decoder_decoded_andMatrixOutputs_lo_hi_23 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_15, decoder_decoded_andMatrixOutputs_lo_hi_lo_3) node decoder_decoded_andMatrixOutputs_lo_24 = cat(decoder_decoded_andMatrixOutputs_lo_hi_23, decoder_decoded_andMatrixOutputs_lo_lo_21) node decoder_decoded_andMatrixOutputs_hi_lo_hi_13 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_24, decoder_decoded_andMatrixOutputs_andMatrixInput_5_23) node decoder_decoded_andMatrixOutputs_hi_lo_23 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_13, decoder_decoded_andMatrixOutputs_andMatrixInput_6_23) node decoder_decoded_andMatrixOutputs_hi_hi_lo_5 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_24, decoder_decoded_andMatrixOutputs_andMatrixInput_3_24) node decoder_decoded_andMatrixOutputs_hi_hi_hi_19 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_24, decoder_decoded_andMatrixOutputs_andMatrixInput_1_24) node decoder_decoded_andMatrixOutputs_hi_hi_24 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_19, decoder_decoded_andMatrixOutputs_hi_hi_lo_5) node decoder_decoded_andMatrixOutputs_hi_24 = cat(decoder_decoded_andMatrixOutputs_hi_hi_24, decoder_decoded_andMatrixOutputs_hi_lo_23) node _decoder_decoded_andMatrixOutputs_T_24 = cat(decoder_decoded_andMatrixOutputs_hi_24, decoder_decoded_andMatrixOutputs_lo_24) node decoder_decoded_andMatrixOutputs_57_2 = andr(_decoder_decoded_andMatrixOutputs_T_24) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_25 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_25 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_25 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_25 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_25 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_24 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_24 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_22 = bits(decoder_decoded_invInputs, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_20 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_16 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_14 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_12 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_6 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_4 = bits(decoder_decoded_plaInput, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_14 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_lo_lo_hi_12 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_6, decoder_decoded_andMatrixOutputs_andMatrixInput_13_4) node decoder_decoded_andMatrixOutputs_lo_lo_22 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_12, decoder_decoded_andMatrixOutputs_andMatrixInput_14) node decoder_decoded_andMatrixOutputs_lo_hi_lo_4 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_14, decoder_decoded_andMatrixOutputs_andMatrixInput_11_12) node decoder_decoded_andMatrixOutputs_lo_hi_hi_16 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_20, decoder_decoded_andMatrixOutputs_andMatrixInput_9_16) node decoder_decoded_andMatrixOutputs_lo_hi_24 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_16, decoder_decoded_andMatrixOutputs_lo_hi_lo_4) node decoder_decoded_andMatrixOutputs_lo_25 = cat(decoder_decoded_andMatrixOutputs_lo_hi_24, decoder_decoded_andMatrixOutputs_lo_lo_22) node decoder_decoded_andMatrixOutputs_hi_lo_lo = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_24, decoder_decoded_andMatrixOutputs_andMatrixInput_7_22) node decoder_decoded_andMatrixOutputs_hi_lo_hi_14 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_25, decoder_decoded_andMatrixOutputs_andMatrixInput_5_24) node decoder_decoded_andMatrixOutputs_hi_lo_24 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_14, decoder_decoded_andMatrixOutputs_hi_lo_lo) node decoder_decoded_andMatrixOutputs_hi_hi_lo_6 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_25, decoder_decoded_andMatrixOutputs_andMatrixInput_3_25) node decoder_decoded_andMatrixOutputs_hi_hi_hi_20 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_25, decoder_decoded_andMatrixOutputs_andMatrixInput_1_25) node decoder_decoded_andMatrixOutputs_hi_hi_25 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_20, decoder_decoded_andMatrixOutputs_hi_hi_lo_6) node decoder_decoded_andMatrixOutputs_hi_25 = cat(decoder_decoded_andMatrixOutputs_hi_hi_25, decoder_decoded_andMatrixOutputs_hi_lo_24) node _decoder_decoded_andMatrixOutputs_T_25 = cat(decoder_decoded_andMatrixOutputs_hi_25, decoder_decoded_andMatrixOutputs_lo_25) node decoder_decoded_andMatrixOutputs_50_2 = andr(_decoder_decoded_andMatrixOutputs_T_25) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_26 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_26 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_26 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_26 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_26 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_25 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_25 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_23 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_21 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_17 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_15 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_13 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_7 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_5 = bits(decoder_decoded_plaInput, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_1 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_lo_lo_hi_13 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_7, decoder_decoded_andMatrixOutputs_andMatrixInput_13_5) node decoder_decoded_andMatrixOutputs_lo_lo_23 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_13, decoder_decoded_andMatrixOutputs_andMatrixInput_14_1) node decoder_decoded_andMatrixOutputs_lo_hi_lo_5 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_15, decoder_decoded_andMatrixOutputs_andMatrixInput_11_13) node decoder_decoded_andMatrixOutputs_lo_hi_hi_17 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_21, decoder_decoded_andMatrixOutputs_andMatrixInput_9_17) node decoder_decoded_andMatrixOutputs_lo_hi_25 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_17, decoder_decoded_andMatrixOutputs_lo_hi_lo_5) node decoder_decoded_andMatrixOutputs_lo_26 = cat(decoder_decoded_andMatrixOutputs_lo_hi_25, decoder_decoded_andMatrixOutputs_lo_lo_23) node decoder_decoded_andMatrixOutputs_hi_lo_lo_1 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_25, decoder_decoded_andMatrixOutputs_andMatrixInput_7_23) node decoder_decoded_andMatrixOutputs_hi_lo_hi_15 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_26, decoder_decoded_andMatrixOutputs_andMatrixInput_5_25) node decoder_decoded_andMatrixOutputs_hi_lo_25 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_15, decoder_decoded_andMatrixOutputs_hi_lo_lo_1) node decoder_decoded_andMatrixOutputs_hi_hi_lo_7 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_26, decoder_decoded_andMatrixOutputs_andMatrixInput_3_26) node decoder_decoded_andMatrixOutputs_hi_hi_hi_21 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_26, decoder_decoded_andMatrixOutputs_andMatrixInput_1_26) node decoder_decoded_andMatrixOutputs_hi_hi_26 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_21, decoder_decoded_andMatrixOutputs_hi_hi_lo_7) node decoder_decoded_andMatrixOutputs_hi_26 = cat(decoder_decoded_andMatrixOutputs_hi_hi_26, decoder_decoded_andMatrixOutputs_hi_lo_25) node _decoder_decoded_andMatrixOutputs_T_26 = cat(decoder_decoded_andMatrixOutputs_hi_26, decoder_decoded_andMatrixOutputs_lo_26) node decoder_decoded_andMatrixOutputs_21_2 = andr(_decoder_decoded_andMatrixOutputs_T_26) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_27 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_27 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_27 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_27 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_27 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_26 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_26 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_24 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_22 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_18 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_16 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_14 = bits(decoder_decoded_plaInput, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_8 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_6 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_14 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_14, decoder_decoded_andMatrixOutputs_andMatrixInput_12_8) node decoder_decoded_andMatrixOutputs_lo_lo_24 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_14, decoder_decoded_andMatrixOutputs_andMatrixInput_13_6) node decoder_decoded_andMatrixOutputs_lo_hi_lo_6 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_18, decoder_decoded_andMatrixOutputs_andMatrixInput_10_16) node decoder_decoded_andMatrixOutputs_lo_hi_hi_18 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_24, decoder_decoded_andMatrixOutputs_andMatrixInput_8_22) node decoder_decoded_andMatrixOutputs_lo_hi_26 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_18, decoder_decoded_andMatrixOutputs_lo_hi_lo_6) node decoder_decoded_andMatrixOutputs_lo_27 = cat(decoder_decoded_andMatrixOutputs_lo_hi_26, decoder_decoded_andMatrixOutputs_lo_lo_24) node decoder_decoded_andMatrixOutputs_hi_lo_hi_16 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_27, decoder_decoded_andMatrixOutputs_andMatrixInput_5_26) node decoder_decoded_andMatrixOutputs_hi_lo_26 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_16, decoder_decoded_andMatrixOutputs_andMatrixInput_6_26) node decoder_decoded_andMatrixOutputs_hi_hi_lo_8 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_27, decoder_decoded_andMatrixOutputs_andMatrixInput_3_27) node decoder_decoded_andMatrixOutputs_hi_hi_hi_22 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_27, decoder_decoded_andMatrixOutputs_andMatrixInput_1_27) node decoder_decoded_andMatrixOutputs_hi_hi_27 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_22, decoder_decoded_andMatrixOutputs_hi_hi_lo_8) node decoder_decoded_andMatrixOutputs_hi_27 = cat(decoder_decoded_andMatrixOutputs_hi_hi_27, decoder_decoded_andMatrixOutputs_hi_lo_26) node _decoder_decoded_andMatrixOutputs_T_27 = cat(decoder_decoded_andMatrixOutputs_hi_27, decoder_decoded_andMatrixOutputs_lo_27) node decoder_decoded_andMatrixOutputs_61_2 = andr(_decoder_decoded_andMatrixOutputs_T_27) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_28 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_28 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_28 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_28 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_28 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_27 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_27 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_25 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_23 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_19 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_17 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_15 = bits(decoder_decoded_plaInput, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_9 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_7 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_15 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_15, decoder_decoded_andMatrixOutputs_andMatrixInput_12_9) node decoder_decoded_andMatrixOutputs_lo_lo_25 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_15, decoder_decoded_andMatrixOutputs_andMatrixInput_13_7) node decoder_decoded_andMatrixOutputs_lo_hi_lo_7 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_19, decoder_decoded_andMatrixOutputs_andMatrixInput_10_17) node decoder_decoded_andMatrixOutputs_lo_hi_hi_19 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_25, decoder_decoded_andMatrixOutputs_andMatrixInput_8_23) node decoder_decoded_andMatrixOutputs_lo_hi_27 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_19, decoder_decoded_andMatrixOutputs_lo_hi_lo_7) node decoder_decoded_andMatrixOutputs_lo_28 = cat(decoder_decoded_andMatrixOutputs_lo_hi_27, decoder_decoded_andMatrixOutputs_lo_lo_25) node decoder_decoded_andMatrixOutputs_hi_lo_hi_17 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_28, decoder_decoded_andMatrixOutputs_andMatrixInput_5_27) node decoder_decoded_andMatrixOutputs_hi_lo_27 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_17, decoder_decoded_andMatrixOutputs_andMatrixInput_6_27) node decoder_decoded_andMatrixOutputs_hi_hi_lo_9 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_28, decoder_decoded_andMatrixOutputs_andMatrixInput_3_28) node decoder_decoded_andMatrixOutputs_hi_hi_hi_23 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_28, decoder_decoded_andMatrixOutputs_andMatrixInput_1_28) node decoder_decoded_andMatrixOutputs_hi_hi_28 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_23, decoder_decoded_andMatrixOutputs_hi_hi_lo_9) node decoder_decoded_andMatrixOutputs_hi_28 = cat(decoder_decoded_andMatrixOutputs_hi_hi_28, decoder_decoded_andMatrixOutputs_hi_lo_27) node _decoder_decoded_andMatrixOutputs_T_28 = cat(decoder_decoded_andMatrixOutputs_hi_28, decoder_decoded_andMatrixOutputs_lo_28) node decoder_decoded_andMatrixOutputs_44_2 = andr(_decoder_decoded_andMatrixOutputs_T_28) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_29 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_29 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_29 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_29 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_29 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_28 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_28 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_26 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_24 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_20 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_18 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_16 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_10 = bits(decoder_decoded_plaInput, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_8 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_2 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_16 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_10, decoder_decoded_andMatrixOutputs_andMatrixInput_13_8) node decoder_decoded_andMatrixOutputs_lo_lo_26 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_16, decoder_decoded_andMatrixOutputs_andMatrixInput_14_2) node decoder_decoded_andMatrixOutputs_lo_hi_lo_8 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_18, decoder_decoded_andMatrixOutputs_andMatrixInput_11_16) node decoder_decoded_andMatrixOutputs_lo_hi_hi_20 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_24, decoder_decoded_andMatrixOutputs_andMatrixInput_9_20) node decoder_decoded_andMatrixOutputs_lo_hi_28 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_20, decoder_decoded_andMatrixOutputs_lo_hi_lo_8) node decoder_decoded_andMatrixOutputs_lo_29 = cat(decoder_decoded_andMatrixOutputs_lo_hi_28, decoder_decoded_andMatrixOutputs_lo_lo_26) node decoder_decoded_andMatrixOutputs_hi_lo_lo_2 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_28, decoder_decoded_andMatrixOutputs_andMatrixInput_7_26) node decoder_decoded_andMatrixOutputs_hi_lo_hi_18 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_29, decoder_decoded_andMatrixOutputs_andMatrixInput_5_28) node decoder_decoded_andMatrixOutputs_hi_lo_28 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_18, decoder_decoded_andMatrixOutputs_hi_lo_lo_2) node decoder_decoded_andMatrixOutputs_hi_hi_lo_10 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_29, decoder_decoded_andMatrixOutputs_andMatrixInput_3_29) node decoder_decoded_andMatrixOutputs_hi_hi_hi_24 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_29, decoder_decoded_andMatrixOutputs_andMatrixInput_1_29) node decoder_decoded_andMatrixOutputs_hi_hi_29 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_24, decoder_decoded_andMatrixOutputs_hi_hi_lo_10) node decoder_decoded_andMatrixOutputs_hi_29 = cat(decoder_decoded_andMatrixOutputs_hi_hi_29, decoder_decoded_andMatrixOutputs_hi_lo_28) node _decoder_decoded_andMatrixOutputs_T_29 = cat(decoder_decoded_andMatrixOutputs_hi_29, decoder_decoded_andMatrixOutputs_lo_29) node decoder_decoded_andMatrixOutputs_43_2 = andr(_decoder_decoded_andMatrixOutputs_T_29) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_30 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_30 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_30 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_30 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_30 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_29 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_29 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_27 = bits(decoder_decoded_invInputs, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_25 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_21 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_19 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_17 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_11 = bits(decoder_decoded_plaInput, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_9 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_3 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_17 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_11, decoder_decoded_andMatrixOutputs_andMatrixInput_13_9) node decoder_decoded_andMatrixOutputs_lo_lo_27 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_17, decoder_decoded_andMatrixOutputs_andMatrixInput_14_3) node decoder_decoded_andMatrixOutputs_lo_hi_lo_9 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_19, decoder_decoded_andMatrixOutputs_andMatrixInput_11_17) node decoder_decoded_andMatrixOutputs_lo_hi_hi_21 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_25, decoder_decoded_andMatrixOutputs_andMatrixInput_9_21) node decoder_decoded_andMatrixOutputs_lo_hi_29 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_21, decoder_decoded_andMatrixOutputs_lo_hi_lo_9) node decoder_decoded_andMatrixOutputs_lo_30 = cat(decoder_decoded_andMatrixOutputs_lo_hi_29, decoder_decoded_andMatrixOutputs_lo_lo_27) node decoder_decoded_andMatrixOutputs_hi_lo_lo_3 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_29, decoder_decoded_andMatrixOutputs_andMatrixInput_7_27) node decoder_decoded_andMatrixOutputs_hi_lo_hi_19 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_30, decoder_decoded_andMatrixOutputs_andMatrixInput_5_29) node decoder_decoded_andMatrixOutputs_hi_lo_29 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_19, decoder_decoded_andMatrixOutputs_hi_lo_lo_3) node decoder_decoded_andMatrixOutputs_hi_hi_lo_11 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_30, decoder_decoded_andMatrixOutputs_andMatrixInput_3_30) node decoder_decoded_andMatrixOutputs_hi_hi_hi_25 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_30, decoder_decoded_andMatrixOutputs_andMatrixInput_1_30) node decoder_decoded_andMatrixOutputs_hi_hi_30 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_25, decoder_decoded_andMatrixOutputs_hi_hi_lo_11) node decoder_decoded_andMatrixOutputs_hi_30 = cat(decoder_decoded_andMatrixOutputs_hi_hi_30, decoder_decoded_andMatrixOutputs_hi_lo_29) node _decoder_decoded_andMatrixOutputs_T_30 = cat(decoder_decoded_andMatrixOutputs_hi_30, decoder_decoded_andMatrixOutputs_lo_30) node decoder_decoded_andMatrixOutputs_73_2 = andr(_decoder_decoded_andMatrixOutputs_T_30) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_31 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_31 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_31 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_31 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_31 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_30 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_30 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_28 = bits(decoder_decoded_invInputs, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_26 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_22 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_20 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_18 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_12 = bits(decoder_decoded_plaInput, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_10 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_4 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_18 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_12, decoder_decoded_andMatrixOutputs_andMatrixInput_13_10) node decoder_decoded_andMatrixOutputs_lo_lo_28 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_18, decoder_decoded_andMatrixOutputs_andMatrixInput_14_4) node decoder_decoded_andMatrixOutputs_lo_hi_lo_10 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_20, decoder_decoded_andMatrixOutputs_andMatrixInput_11_18) node decoder_decoded_andMatrixOutputs_lo_hi_hi_22 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_26, decoder_decoded_andMatrixOutputs_andMatrixInput_9_22) node decoder_decoded_andMatrixOutputs_lo_hi_30 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_22, decoder_decoded_andMatrixOutputs_lo_hi_lo_10) node decoder_decoded_andMatrixOutputs_lo_31 = cat(decoder_decoded_andMatrixOutputs_lo_hi_30, decoder_decoded_andMatrixOutputs_lo_lo_28) node decoder_decoded_andMatrixOutputs_hi_lo_lo_4 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_30, decoder_decoded_andMatrixOutputs_andMatrixInput_7_28) node decoder_decoded_andMatrixOutputs_hi_lo_hi_20 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_31, decoder_decoded_andMatrixOutputs_andMatrixInput_5_30) node decoder_decoded_andMatrixOutputs_hi_lo_30 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_20, decoder_decoded_andMatrixOutputs_hi_lo_lo_4) node decoder_decoded_andMatrixOutputs_hi_hi_lo_12 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_31, decoder_decoded_andMatrixOutputs_andMatrixInput_3_31) node decoder_decoded_andMatrixOutputs_hi_hi_hi_26 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_31, decoder_decoded_andMatrixOutputs_andMatrixInput_1_31) node decoder_decoded_andMatrixOutputs_hi_hi_31 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_26, decoder_decoded_andMatrixOutputs_hi_hi_lo_12) node decoder_decoded_andMatrixOutputs_hi_31 = cat(decoder_decoded_andMatrixOutputs_hi_hi_31, decoder_decoded_andMatrixOutputs_hi_lo_30) node _decoder_decoded_andMatrixOutputs_T_31 = cat(decoder_decoded_andMatrixOutputs_hi_31, decoder_decoded_andMatrixOutputs_lo_31) node decoder_decoded_andMatrixOutputs_23_2 = andr(_decoder_decoded_andMatrixOutputs_T_31) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_32 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_32 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_32 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_32 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_32 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_31 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_31 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_29 = bits(decoder_decoded_invInputs, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_27 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_23 = bits(decoder_decoded_plaInput, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_21 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_19 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_13 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_11 = bits(decoder_decoded_plaInput, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_5 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_lo_lo_hi_19 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_13, decoder_decoded_andMatrixOutputs_andMatrixInput_13_11) node decoder_decoded_andMatrixOutputs_lo_lo_29 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_19, decoder_decoded_andMatrixOutputs_andMatrixInput_14_5) node decoder_decoded_andMatrixOutputs_lo_hi_lo_11 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_21, decoder_decoded_andMatrixOutputs_andMatrixInput_11_19) node decoder_decoded_andMatrixOutputs_lo_hi_hi_23 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_27, decoder_decoded_andMatrixOutputs_andMatrixInput_9_23) node decoder_decoded_andMatrixOutputs_lo_hi_31 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_23, decoder_decoded_andMatrixOutputs_lo_hi_lo_11) node decoder_decoded_andMatrixOutputs_lo_32 = cat(decoder_decoded_andMatrixOutputs_lo_hi_31, decoder_decoded_andMatrixOutputs_lo_lo_29) node decoder_decoded_andMatrixOutputs_hi_lo_lo_5 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_31, decoder_decoded_andMatrixOutputs_andMatrixInput_7_29) node decoder_decoded_andMatrixOutputs_hi_lo_hi_21 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_32, decoder_decoded_andMatrixOutputs_andMatrixInput_5_31) node decoder_decoded_andMatrixOutputs_hi_lo_31 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_21, decoder_decoded_andMatrixOutputs_hi_lo_lo_5) node decoder_decoded_andMatrixOutputs_hi_hi_lo_13 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_32, decoder_decoded_andMatrixOutputs_andMatrixInput_3_32) node decoder_decoded_andMatrixOutputs_hi_hi_hi_27 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_32, decoder_decoded_andMatrixOutputs_andMatrixInput_1_32) node decoder_decoded_andMatrixOutputs_hi_hi_32 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_27, decoder_decoded_andMatrixOutputs_hi_hi_lo_13) node decoder_decoded_andMatrixOutputs_hi_32 = cat(decoder_decoded_andMatrixOutputs_hi_hi_32, decoder_decoded_andMatrixOutputs_hi_lo_31) node _decoder_decoded_andMatrixOutputs_T_32 = cat(decoder_decoded_andMatrixOutputs_hi_32, decoder_decoded_andMatrixOutputs_lo_32) node decoder_decoded_andMatrixOutputs_38_2 = andr(_decoder_decoded_andMatrixOutputs_T_32) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_33 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_33 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_33 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_33 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_33 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_32 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_32 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_30 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_28 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_24 = bits(decoder_decoded_plaInput, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_22 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_20 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_14 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_12 = bits(decoder_decoded_plaInput, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_6 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_lo_lo_hi_20 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_14, decoder_decoded_andMatrixOutputs_andMatrixInput_13_12) node decoder_decoded_andMatrixOutputs_lo_lo_30 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_20, decoder_decoded_andMatrixOutputs_andMatrixInput_14_6) node decoder_decoded_andMatrixOutputs_lo_hi_lo_12 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_22, decoder_decoded_andMatrixOutputs_andMatrixInput_11_20) node decoder_decoded_andMatrixOutputs_lo_hi_hi_24 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_28, decoder_decoded_andMatrixOutputs_andMatrixInput_9_24) node decoder_decoded_andMatrixOutputs_lo_hi_32 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_24, decoder_decoded_andMatrixOutputs_lo_hi_lo_12) node decoder_decoded_andMatrixOutputs_lo_33 = cat(decoder_decoded_andMatrixOutputs_lo_hi_32, decoder_decoded_andMatrixOutputs_lo_lo_30) node decoder_decoded_andMatrixOutputs_hi_lo_lo_6 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_32, decoder_decoded_andMatrixOutputs_andMatrixInput_7_30) node decoder_decoded_andMatrixOutputs_hi_lo_hi_22 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_33, decoder_decoded_andMatrixOutputs_andMatrixInput_5_32) node decoder_decoded_andMatrixOutputs_hi_lo_32 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_22, decoder_decoded_andMatrixOutputs_hi_lo_lo_6) node decoder_decoded_andMatrixOutputs_hi_hi_lo_14 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_33, decoder_decoded_andMatrixOutputs_andMatrixInput_3_33) node decoder_decoded_andMatrixOutputs_hi_hi_hi_28 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_33, decoder_decoded_andMatrixOutputs_andMatrixInput_1_33) node decoder_decoded_andMatrixOutputs_hi_hi_33 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_28, decoder_decoded_andMatrixOutputs_hi_hi_lo_14) node decoder_decoded_andMatrixOutputs_hi_33 = cat(decoder_decoded_andMatrixOutputs_hi_hi_33, decoder_decoded_andMatrixOutputs_hi_lo_32) node _decoder_decoded_andMatrixOutputs_T_33 = cat(decoder_decoded_andMatrixOutputs_hi_33, decoder_decoded_andMatrixOutputs_lo_33) node decoder_decoded_andMatrixOutputs_10_2 = andr(_decoder_decoded_andMatrixOutputs_T_33) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_34 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_34 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_34 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_34 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_34 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_33 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_33 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_31 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_29 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_25 = bits(decoder_decoded_plaInput, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_23 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_21 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_15 = bits(decoder_decoded_plaInput, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_13 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_7 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_21 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_15, decoder_decoded_andMatrixOutputs_andMatrixInput_13_13) node decoder_decoded_andMatrixOutputs_lo_lo_31 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_21, decoder_decoded_andMatrixOutputs_andMatrixInput_14_7) node decoder_decoded_andMatrixOutputs_lo_hi_lo_13 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_23, decoder_decoded_andMatrixOutputs_andMatrixInput_11_21) node decoder_decoded_andMatrixOutputs_lo_hi_hi_25 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_29, decoder_decoded_andMatrixOutputs_andMatrixInput_9_25) node decoder_decoded_andMatrixOutputs_lo_hi_33 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_25, decoder_decoded_andMatrixOutputs_lo_hi_lo_13) node decoder_decoded_andMatrixOutputs_lo_34 = cat(decoder_decoded_andMatrixOutputs_lo_hi_33, decoder_decoded_andMatrixOutputs_lo_lo_31) node decoder_decoded_andMatrixOutputs_hi_lo_lo_7 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_33, decoder_decoded_andMatrixOutputs_andMatrixInput_7_31) node decoder_decoded_andMatrixOutputs_hi_lo_hi_23 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_34, decoder_decoded_andMatrixOutputs_andMatrixInput_5_33) node decoder_decoded_andMatrixOutputs_hi_lo_33 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_23, decoder_decoded_andMatrixOutputs_hi_lo_lo_7) node decoder_decoded_andMatrixOutputs_hi_hi_lo_15 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_34, decoder_decoded_andMatrixOutputs_andMatrixInput_3_34) node decoder_decoded_andMatrixOutputs_hi_hi_hi_29 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_34, decoder_decoded_andMatrixOutputs_andMatrixInput_1_34) node decoder_decoded_andMatrixOutputs_hi_hi_34 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_29, decoder_decoded_andMatrixOutputs_hi_hi_lo_15) node decoder_decoded_andMatrixOutputs_hi_34 = cat(decoder_decoded_andMatrixOutputs_hi_hi_34, decoder_decoded_andMatrixOutputs_hi_lo_33) node _decoder_decoded_andMatrixOutputs_T_34 = cat(decoder_decoded_andMatrixOutputs_hi_34, decoder_decoded_andMatrixOutputs_lo_34) node decoder_decoded_andMatrixOutputs_40_2 = andr(_decoder_decoded_andMatrixOutputs_T_34) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_35 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_35 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_35 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_35 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_35 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_34 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_34 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_32 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_30 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_26 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_24 = bits(decoder_decoded_plaInput, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_22 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_16 = bits(decoder_decoded_plaInput, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_14 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_8 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_22 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_16, decoder_decoded_andMatrixOutputs_andMatrixInput_13_14) node decoder_decoded_andMatrixOutputs_lo_lo_32 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_22, decoder_decoded_andMatrixOutputs_andMatrixInput_14_8) node decoder_decoded_andMatrixOutputs_lo_hi_lo_14 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_24, decoder_decoded_andMatrixOutputs_andMatrixInput_11_22) node decoder_decoded_andMatrixOutputs_lo_hi_hi_26 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_30, decoder_decoded_andMatrixOutputs_andMatrixInput_9_26) node decoder_decoded_andMatrixOutputs_lo_hi_34 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_26, decoder_decoded_andMatrixOutputs_lo_hi_lo_14) node decoder_decoded_andMatrixOutputs_lo_35 = cat(decoder_decoded_andMatrixOutputs_lo_hi_34, decoder_decoded_andMatrixOutputs_lo_lo_32) node decoder_decoded_andMatrixOutputs_hi_lo_lo_8 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_34, decoder_decoded_andMatrixOutputs_andMatrixInput_7_32) node decoder_decoded_andMatrixOutputs_hi_lo_hi_24 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_35, decoder_decoded_andMatrixOutputs_andMatrixInput_5_34) node decoder_decoded_andMatrixOutputs_hi_lo_34 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_24, decoder_decoded_andMatrixOutputs_hi_lo_lo_8) node decoder_decoded_andMatrixOutputs_hi_hi_lo_16 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_35, decoder_decoded_andMatrixOutputs_andMatrixInput_3_35) node decoder_decoded_andMatrixOutputs_hi_hi_hi_30 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_35, decoder_decoded_andMatrixOutputs_andMatrixInput_1_35) node decoder_decoded_andMatrixOutputs_hi_hi_35 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_30, decoder_decoded_andMatrixOutputs_hi_hi_lo_16) node decoder_decoded_andMatrixOutputs_hi_35 = cat(decoder_decoded_andMatrixOutputs_hi_hi_35, decoder_decoded_andMatrixOutputs_hi_lo_34) node _decoder_decoded_andMatrixOutputs_T_35 = cat(decoder_decoded_andMatrixOutputs_hi_35, decoder_decoded_andMatrixOutputs_lo_35) node decoder_decoded_andMatrixOutputs_33_2 = andr(_decoder_decoded_andMatrixOutputs_T_35) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_36 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_36 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_36 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_36 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_36 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_35 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_35 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_33 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_31 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_27 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_25 = bits(decoder_decoded_plaInput, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_23 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_17 = bits(decoder_decoded_plaInput, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_15 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_9 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_23 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_17, decoder_decoded_andMatrixOutputs_andMatrixInput_13_15) node decoder_decoded_andMatrixOutputs_lo_lo_33 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_23, decoder_decoded_andMatrixOutputs_andMatrixInput_14_9) node decoder_decoded_andMatrixOutputs_lo_hi_lo_15 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_25, decoder_decoded_andMatrixOutputs_andMatrixInput_11_23) node decoder_decoded_andMatrixOutputs_lo_hi_hi_27 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_31, decoder_decoded_andMatrixOutputs_andMatrixInput_9_27) node decoder_decoded_andMatrixOutputs_lo_hi_35 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_27, decoder_decoded_andMatrixOutputs_lo_hi_lo_15) node decoder_decoded_andMatrixOutputs_lo_36 = cat(decoder_decoded_andMatrixOutputs_lo_hi_35, decoder_decoded_andMatrixOutputs_lo_lo_33) node decoder_decoded_andMatrixOutputs_hi_lo_lo_9 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_35, decoder_decoded_andMatrixOutputs_andMatrixInput_7_33) node decoder_decoded_andMatrixOutputs_hi_lo_hi_25 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_36, decoder_decoded_andMatrixOutputs_andMatrixInput_5_35) node decoder_decoded_andMatrixOutputs_hi_lo_35 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_25, decoder_decoded_andMatrixOutputs_hi_lo_lo_9) node decoder_decoded_andMatrixOutputs_hi_hi_lo_17 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_36, decoder_decoded_andMatrixOutputs_andMatrixInput_3_36) node decoder_decoded_andMatrixOutputs_hi_hi_hi_31 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_36, decoder_decoded_andMatrixOutputs_andMatrixInput_1_36) node decoder_decoded_andMatrixOutputs_hi_hi_36 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_31, decoder_decoded_andMatrixOutputs_hi_hi_lo_17) node decoder_decoded_andMatrixOutputs_hi_36 = cat(decoder_decoded_andMatrixOutputs_hi_hi_36, decoder_decoded_andMatrixOutputs_hi_lo_35) node _decoder_decoded_andMatrixOutputs_T_36 = cat(decoder_decoded_andMatrixOutputs_hi_36, decoder_decoded_andMatrixOutputs_lo_36) node decoder_decoded_andMatrixOutputs_67_2 = andr(_decoder_decoded_andMatrixOutputs_T_36) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_37 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_37 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_37 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_37 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_37 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_36 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_36 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_34 = bits(decoder_decoded_plaInput, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_32 = bits(decoder_decoded_invInputs, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_28 = bits(decoder_decoded_invInputs, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_26 = bits(decoder_decoded_invInputs, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_24 = bits(decoder_decoded_invInputs, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_18 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_16 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_10 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_15 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_16 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_lo_lo_lo = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_15, decoder_decoded_andMatrixOutputs_andMatrixInput_16) node decoder_decoded_andMatrixOutputs_lo_lo_hi_24 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_13_16, decoder_decoded_andMatrixOutputs_andMatrixInput_14_10) node decoder_decoded_andMatrixOutputs_lo_lo_34 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_24, decoder_decoded_andMatrixOutputs_lo_lo_lo) node decoder_decoded_andMatrixOutputs_lo_hi_lo_16 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_24, decoder_decoded_andMatrixOutputs_andMatrixInput_12_18) node decoder_decoded_andMatrixOutputs_lo_hi_hi_28 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_28, decoder_decoded_andMatrixOutputs_andMatrixInput_10_26) node decoder_decoded_andMatrixOutputs_lo_hi_36 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_28, decoder_decoded_andMatrixOutputs_lo_hi_lo_16) node decoder_decoded_andMatrixOutputs_lo_37 = cat(decoder_decoded_andMatrixOutputs_lo_hi_36, decoder_decoded_andMatrixOutputs_lo_lo_34) node decoder_decoded_andMatrixOutputs_hi_lo_lo_10 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_34, decoder_decoded_andMatrixOutputs_andMatrixInput_8_32) node decoder_decoded_andMatrixOutputs_hi_lo_hi_26 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_36, decoder_decoded_andMatrixOutputs_andMatrixInput_6_36) node decoder_decoded_andMatrixOutputs_hi_lo_36 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_26, decoder_decoded_andMatrixOutputs_hi_lo_lo_10) node decoder_decoded_andMatrixOutputs_hi_hi_lo_18 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_37, decoder_decoded_andMatrixOutputs_andMatrixInput_4_37) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_37, decoder_decoded_andMatrixOutputs_andMatrixInput_1_37) node decoder_decoded_andMatrixOutputs_hi_hi_hi_32 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi, decoder_decoded_andMatrixOutputs_andMatrixInput_2_37) node decoder_decoded_andMatrixOutputs_hi_hi_37 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_32, decoder_decoded_andMatrixOutputs_hi_hi_lo_18) node decoder_decoded_andMatrixOutputs_hi_37 = cat(decoder_decoded_andMatrixOutputs_hi_hi_37, decoder_decoded_andMatrixOutputs_hi_lo_36) node _decoder_decoded_andMatrixOutputs_T_37 = cat(decoder_decoded_andMatrixOutputs_hi_37, decoder_decoded_andMatrixOutputs_lo_37) node decoder_decoded_andMatrixOutputs_59_2 = andr(_decoder_decoded_andMatrixOutputs_T_37) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_38 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_38 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_38 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_38 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_38 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_37 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_37 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_35 = bits(decoder_decoded_plaInput, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_33 = bits(decoder_decoded_invInputs, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_29 = bits(decoder_decoded_invInputs, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_27 = bits(decoder_decoded_invInputs, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_25 = bits(decoder_decoded_invInputs, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_19 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_17 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_11 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_1 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_1 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_17 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_1 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_16_1, decoder_decoded_andMatrixOutputs_andMatrixInput_17) node decoder_decoded_andMatrixOutputs_lo_lo_hi_25 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_11, decoder_decoded_andMatrixOutputs_andMatrixInput_15_1) node decoder_decoded_andMatrixOutputs_lo_lo_35 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_25, decoder_decoded_andMatrixOutputs_lo_lo_lo_1) node decoder_decoded_andMatrixOutputs_lo_hi_lo_17 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_19, decoder_decoded_andMatrixOutputs_andMatrixInput_13_17) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_29, decoder_decoded_andMatrixOutputs_andMatrixInput_10_27) node decoder_decoded_andMatrixOutputs_lo_hi_hi_29 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi, decoder_decoded_andMatrixOutputs_andMatrixInput_11_25) node decoder_decoded_andMatrixOutputs_lo_hi_37 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_29, decoder_decoded_andMatrixOutputs_lo_hi_lo_17) node decoder_decoded_andMatrixOutputs_lo_38 = cat(decoder_decoded_andMatrixOutputs_lo_hi_37, decoder_decoded_andMatrixOutputs_lo_lo_35) node decoder_decoded_andMatrixOutputs_hi_lo_lo_11 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_35, decoder_decoded_andMatrixOutputs_andMatrixInput_8_33) node decoder_decoded_andMatrixOutputs_hi_lo_hi_27 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_37, decoder_decoded_andMatrixOutputs_andMatrixInput_6_37) node decoder_decoded_andMatrixOutputs_hi_lo_37 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_27, decoder_decoded_andMatrixOutputs_hi_lo_lo_11) node decoder_decoded_andMatrixOutputs_hi_hi_lo_19 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_38, decoder_decoded_andMatrixOutputs_andMatrixInput_4_38) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_1 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_38, decoder_decoded_andMatrixOutputs_andMatrixInput_1_38) node decoder_decoded_andMatrixOutputs_hi_hi_hi_33 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_1, decoder_decoded_andMatrixOutputs_andMatrixInput_2_38) node decoder_decoded_andMatrixOutputs_hi_hi_38 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_33, decoder_decoded_andMatrixOutputs_hi_hi_lo_19) node decoder_decoded_andMatrixOutputs_hi_38 = cat(decoder_decoded_andMatrixOutputs_hi_hi_38, decoder_decoded_andMatrixOutputs_hi_lo_37) node _decoder_decoded_andMatrixOutputs_T_38 = cat(decoder_decoded_andMatrixOutputs_hi_38, decoder_decoded_andMatrixOutputs_lo_38) node decoder_decoded_andMatrixOutputs_5_2 = andr(_decoder_decoded_andMatrixOutputs_T_38) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_39 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_39 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_39 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_39 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_39 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_38 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_38 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_36 = bits(decoder_decoded_plaInput, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_34 = bits(decoder_decoded_invInputs, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_30 = bits(decoder_decoded_invInputs, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_28 = bits(decoder_decoded_invInputs, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_26 = bits(decoder_decoded_invInputs, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_20 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_18 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_12 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_2 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_2 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_17_1 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_18 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_2 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_17_1, decoder_decoded_andMatrixOutputs_andMatrixInput_18) node decoder_decoded_andMatrixOutputs_lo_lo_hi_26 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_15_2, decoder_decoded_andMatrixOutputs_andMatrixInput_16_2) node decoder_decoded_andMatrixOutputs_lo_lo_36 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_26, decoder_decoded_andMatrixOutputs_lo_lo_lo_2) node decoder_decoded_andMatrixOutputs_lo_hi_lo_18 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_13_18, decoder_decoded_andMatrixOutputs_andMatrixInput_14_12) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_1 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_28, decoder_decoded_andMatrixOutputs_andMatrixInput_11_26) node decoder_decoded_andMatrixOutputs_lo_hi_hi_30 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_1, decoder_decoded_andMatrixOutputs_andMatrixInput_12_20) node decoder_decoded_andMatrixOutputs_lo_hi_38 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_30, decoder_decoded_andMatrixOutputs_lo_hi_lo_18) node decoder_decoded_andMatrixOutputs_lo_39 = cat(decoder_decoded_andMatrixOutputs_lo_hi_38, decoder_decoded_andMatrixOutputs_lo_lo_36) node decoder_decoded_andMatrixOutputs_hi_lo_lo_12 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_34, decoder_decoded_andMatrixOutputs_andMatrixInput_9_30) node decoder_decoded_andMatrixOutputs_hi_lo_hi_hi = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_38, decoder_decoded_andMatrixOutputs_andMatrixInput_6_38) node decoder_decoded_andMatrixOutputs_hi_lo_hi_28 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_hi, decoder_decoded_andMatrixOutputs_andMatrixInput_7_36) node decoder_decoded_andMatrixOutputs_hi_lo_38 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_28, decoder_decoded_andMatrixOutputs_hi_lo_lo_12) node decoder_decoded_andMatrixOutputs_hi_hi_lo_20 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_39, decoder_decoded_andMatrixOutputs_andMatrixInput_4_39) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_2 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_39, decoder_decoded_andMatrixOutputs_andMatrixInput_1_39) node decoder_decoded_andMatrixOutputs_hi_hi_hi_34 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_2, decoder_decoded_andMatrixOutputs_andMatrixInput_2_39) node decoder_decoded_andMatrixOutputs_hi_hi_39 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_34, decoder_decoded_andMatrixOutputs_hi_hi_lo_20) node decoder_decoded_andMatrixOutputs_hi_39 = cat(decoder_decoded_andMatrixOutputs_hi_hi_39, decoder_decoded_andMatrixOutputs_hi_lo_38) node _decoder_decoded_andMatrixOutputs_T_39 = cat(decoder_decoded_andMatrixOutputs_hi_39, decoder_decoded_andMatrixOutputs_lo_39) node decoder_decoded_andMatrixOutputs_1_2 = andr(_decoder_decoded_andMatrixOutputs_T_39) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_40 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_40 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_40 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_40 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_40 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_39 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_39 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_37 = bits(decoder_decoded_invInputs, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_35 = bits(decoder_decoded_plaInput, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_31 = bits(decoder_decoded_invInputs, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_29 = bits(decoder_decoded_invInputs, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_27 = bits(decoder_decoded_invInputs, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_21 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_19 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_13 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_3 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_3 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_lo_lo_lo_3 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_15_3, decoder_decoded_andMatrixOutputs_andMatrixInput_16_3) node decoder_decoded_andMatrixOutputs_lo_lo_hi_27 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_13_19, decoder_decoded_andMatrixOutputs_andMatrixInput_14_13) node decoder_decoded_andMatrixOutputs_lo_lo_37 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_27, decoder_decoded_andMatrixOutputs_lo_lo_lo_3) node decoder_decoded_andMatrixOutputs_lo_hi_lo_19 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_27, decoder_decoded_andMatrixOutputs_andMatrixInput_12_21) node decoder_decoded_andMatrixOutputs_lo_hi_hi_31 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_31, decoder_decoded_andMatrixOutputs_andMatrixInput_10_29) node decoder_decoded_andMatrixOutputs_lo_hi_39 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_31, decoder_decoded_andMatrixOutputs_lo_hi_lo_19) node decoder_decoded_andMatrixOutputs_lo_40 = cat(decoder_decoded_andMatrixOutputs_lo_hi_39, decoder_decoded_andMatrixOutputs_lo_lo_37) node decoder_decoded_andMatrixOutputs_hi_lo_lo_13 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_37, decoder_decoded_andMatrixOutputs_andMatrixInput_8_35) node decoder_decoded_andMatrixOutputs_hi_lo_hi_29 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_39, decoder_decoded_andMatrixOutputs_andMatrixInput_6_39) node decoder_decoded_andMatrixOutputs_hi_lo_39 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_29, decoder_decoded_andMatrixOutputs_hi_lo_lo_13) node decoder_decoded_andMatrixOutputs_hi_hi_lo_21 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_40, decoder_decoded_andMatrixOutputs_andMatrixInput_4_40) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_3 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_40, decoder_decoded_andMatrixOutputs_andMatrixInput_1_40) node decoder_decoded_andMatrixOutputs_hi_hi_hi_35 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_3, decoder_decoded_andMatrixOutputs_andMatrixInput_2_40) node decoder_decoded_andMatrixOutputs_hi_hi_40 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_35, decoder_decoded_andMatrixOutputs_hi_hi_lo_21) node decoder_decoded_andMatrixOutputs_hi_40 = cat(decoder_decoded_andMatrixOutputs_hi_hi_40, decoder_decoded_andMatrixOutputs_hi_lo_39) node _decoder_decoded_andMatrixOutputs_T_40 = cat(decoder_decoded_andMatrixOutputs_hi_40, decoder_decoded_andMatrixOutputs_lo_40) node decoder_decoded_andMatrixOutputs_3_2 = andr(_decoder_decoded_andMatrixOutputs_T_40) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_41 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_41 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_41 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_41 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_41 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_40 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_40 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_38 = bits(decoder_decoded_invInputs, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_36 = bits(decoder_decoded_plaInput, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_32 = bits(decoder_decoded_invInputs, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_30 = bits(decoder_decoded_invInputs, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_28 = bits(decoder_decoded_invInputs, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_22 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_20 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_14 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_4 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_4 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_17_2 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_4 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_16_4, decoder_decoded_andMatrixOutputs_andMatrixInput_17_2) node decoder_decoded_andMatrixOutputs_lo_lo_hi_28 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_14, decoder_decoded_andMatrixOutputs_andMatrixInput_15_4) node decoder_decoded_andMatrixOutputs_lo_lo_38 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_28, decoder_decoded_andMatrixOutputs_lo_lo_lo_4) node decoder_decoded_andMatrixOutputs_lo_hi_lo_20 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_22, decoder_decoded_andMatrixOutputs_andMatrixInput_13_20) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_2 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_32, decoder_decoded_andMatrixOutputs_andMatrixInput_10_30) node decoder_decoded_andMatrixOutputs_lo_hi_hi_32 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_2, decoder_decoded_andMatrixOutputs_andMatrixInput_11_28) node decoder_decoded_andMatrixOutputs_lo_hi_40 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_32, decoder_decoded_andMatrixOutputs_lo_hi_lo_20) node decoder_decoded_andMatrixOutputs_lo_41 = cat(decoder_decoded_andMatrixOutputs_lo_hi_40, decoder_decoded_andMatrixOutputs_lo_lo_38) node decoder_decoded_andMatrixOutputs_hi_lo_lo_14 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_38, decoder_decoded_andMatrixOutputs_andMatrixInput_8_36) node decoder_decoded_andMatrixOutputs_hi_lo_hi_30 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_40, decoder_decoded_andMatrixOutputs_andMatrixInput_6_40) node decoder_decoded_andMatrixOutputs_hi_lo_40 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_30, decoder_decoded_andMatrixOutputs_hi_lo_lo_14) node decoder_decoded_andMatrixOutputs_hi_hi_lo_22 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_41, decoder_decoded_andMatrixOutputs_andMatrixInput_4_41) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_4 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_41, decoder_decoded_andMatrixOutputs_andMatrixInput_1_41) node decoder_decoded_andMatrixOutputs_hi_hi_hi_36 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_4, decoder_decoded_andMatrixOutputs_andMatrixInput_2_41) node decoder_decoded_andMatrixOutputs_hi_hi_41 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_36, decoder_decoded_andMatrixOutputs_hi_hi_lo_22) node decoder_decoded_andMatrixOutputs_hi_41 = cat(decoder_decoded_andMatrixOutputs_hi_hi_41, decoder_decoded_andMatrixOutputs_hi_lo_40) node _decoder_decoded_andMatrixOutputs_T_41 = cat(decoder_decoded_andMatrixOutputs_hi_41, decoder_decoded_andMatrixOutputs_lo_41) node decoder_decoded_andMatrixOutputs_27_2 = andr(_decoder_decoded_andMatrixOutputs_T_41) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_42 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_42 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_42 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_42 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_42 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_41 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_41 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_39 = bits(decoder_decoded_invInputs, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_37 = bits(decoder_decoded_plaInput, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_33 = bits(decoder_decoded_invInputs, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_31 = bits(decoder_decoded_invInputs, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_29 = bits(decoder_decoded_invInputs, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_23 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_21 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_15 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_5 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_5 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_17_3 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_18_1 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_5 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_17_3, decoder_decoded_andMatrixOutputs_andMatrixInput_18_1) node decoder_decoded_andMatrixOutputs_lo_lo_hi_29 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_15_5, decoder_decoded_andMatrixOutputs_andMatrixInput_16_5) node decoder_decoded_andMatrixOutputs_lo_lo_39 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_29, decoder_decoded_andMatrixOutputs_lo_lo_lo_5) node decoder_decoded_andMatrixOutputs_lo_hi_lo_21 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_13_21, decoder_decoded_andMatrixOutputs_andMatrixInput_14_15) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_3 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_31, decoder_decoded_andMatrixOutputs_andMatrixInput_11_29) node decoder_decoded_andMatrixOutputs_lo_hi_hi_33 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_3, decoder_decoded_andMatrixOutputs_andMatrixInput_12_23) node decoder_decoded_andMatrixOutputs_lo_hi_41 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_33, decoder_decoded_andMatrixOutputs_lo_hi_lo_21) node decoder_decoded_andMatrixOutputs_lo_42 = cat(decoder_decoded_andMatrixOutputs_lo_hi_41, decoder_decoded_andMatrixOutputs_lo_lo_39) node decoder_decoded_andMatrixOutputs_hi_lo_lo_15 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_37, decoder_decoded_andMatrixOutputs_andMatrixInput_9_33) node decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_1 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_41, decoder_decoded_andMatrixOutputs_andMatrixInput_6_41) node decoder_decoded_andMatrixOutputs_hi_lo_hi_31 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_1, decoder_decoded_andMatrixOutputs_andMatrixInput_7_39) node decoder_decoded_andMatrixOutputs_hi_lo_41 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_31, decoder_decoded_andMatrixOutputs_hi_lo_lo_15) node decoder_decoded_andMatrixOutputs_hi_hi_lo_23 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_42, decoder_decoded_andMatrixOutputs_andMatrixInput_4_42) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_5 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_42, decoder_decoded_andMatrixOutputs_andMatrixInput_1_42) node decoder_decoded_andMatrixOutputs_hi_hi_hi_37 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_5, decoder_decoded_andMatrixOutputs_andMatrixInput_2_42) node decoder_decoded_andMatrixOutputs_hi_hi_42 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_37, decoder_decoded_andMatrixOutputs_hi_hi_lo_23) node decoder_decoded_andMatrixOutputs_hi_42 = cat(decoder_decoded_andMatrixOutputs_hi_hi_42, decoder_decoded_andMatrixOutputs_hi_lo_41) node _decoder_decoded_andMatrixOutputs_T_42 = cat(decoder_decoded_andMatrixOutputs_hi_42, decoder_decoded_andMatrixOutputs_lo_42) node decoder_decoded_andMatrixOutputs_53_2 = andr(_decoder_decoded_andMatrixOutputs_T_42) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_43 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_43 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_43 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_43 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_43 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_42 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_42 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_40 = bits(decoder_decoded_invInputs, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_38 = bits(decoder_decoded_invInputs, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_34 = bits(decoder_decoded_invInputs, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_32 = bits(decoder_decoded_invInputs, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_30 = bits(decoder_decoded_plaInput, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_24 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_22 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_16 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_6 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_6 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_lo_lo_lo_6 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_15_6, decoder_decoded_andMatrixOutputs_andMatrixInput_16_6) node decoder_decoded_andMatrixOutputs_lo_lo_hi_30 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_13_22, decoder_decoded_andMatrixOutputs_andMatrixInput_14_16) node decoder_decoded_andMatrixOutputs_lo_lo_40 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_30, decoder_decoded_andMatrixOutputs_lo_lo_lo_6) node decoder_decoded_andMatrixOutputs_lo_hi_lo_22 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_30, decoder_decoded_andMatrixOutputs_andMatrixInput_12_24) node decoder_decoded_andMatrixOutputs_lo_hi_hi_34 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_34, decoder_decoded_andMatrixOutputs_andMatrixInput_10_32) node decoder_decoded_andMatrixOutputs_lo_hi_42 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_34, decoder_decoded_andMatrixOutputs_lo_hi_lo_22) node decoder_decoded_andMatrixOutputs_lo_43 = cat(decoder_decoded_andMatrixOutputs_lo_hi_42, decoder_decoded_andMatrixOutputs_lo_lo_40) node decoder_decoded_andMatrixOutputs_hi_lo_lo_16 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_40, decoder_decoded_andMatrixOutputs_andMatrixInput_8_38) node decoder_decoded_andMatrixOutputs_hi_lo_hi_32 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_42, decoder_decoded_andMatrixOutputs_andMatrixInput_6_42) node decoder_decoded_andMatrixOutputs_hi_lo_42 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_32, decoder_decoded_andMatrixOutputs_hi_lo_lo_16) node decoder_decoded_andMatrixOutputs_hi_hi_lo_24 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_43, decoder_decoded_andMatrixOutputs_andMatrixInput_4_43) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_6 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_43, decoder_decoded_andMatrixOutputs_andMatrixInput_1_43) node decoder_decoded_andMatrixOutputs_hi_hi_hi_38 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_6, decoder_decoded_andMatrixOutputs_andMatrixInput_2_43) node decoder_decoded_andMatrixOutputs_hi_hi_43 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_38, decoder_decoded_andMatrixOutputs_hi_hi_lo_24) node decoder_decoded_andMatrixOutputs_hi_43 = cat(decoder_decoded_andMatrixOutputs_hi_hi_43, decoder_decoded_andMatrixOutputs_hi_lo_42) node _decoder_decoded_andMatrixOutputs_T_43 = cat(decoder_decoded_andMatrixOutputs_hi_43, decoder_decoded_andMatrixOutputs_lo_43) node decoder_decoded_andMatrixOutputs_70_2 = andr(_decoder_decoded_andMatrixOutputs_T_43) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_44 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_44 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_44 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_44 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_44 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_43 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_43 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_41 = bits(decoder_decoded_invInputs, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_39 = bits(decoder_decoded_invInputs, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_35 = bits(decoder_decoded_invInputs, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_33 = bits(decoder_decoded_invInputs, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_31 = bits(decoder_decoded_plaInput, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_25 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_23 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_17 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_7 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_7 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_17_4 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_7 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_16_7, decoder_decoded_andMatrixOutputs_andMatrixInput_17_4) node decoder_decoded_andMatrixOutputs_lo_lo_hi_31 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_17, decoder_decoded_andMatrixOutputs_andMatrixInput_15_7) node decoder_decoded_andMatrixOutputs_lo_lo_41 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_31, decoder_decoded_andMatrixOutputs_lo_lo_lo_7) node decoder_decoded_andMatrixOutputs_lo_hi_lo_23 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_25, decoder_decoded_andMatrixOutputs_andMatrixInput_13_23) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_4 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_35, decoder_decoded_andMatrixOutputs_andMatrixInput_10_33) node decoder_decoded_andMatrixOutputs_lo_hi_hi_35 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_4, decoder_decoded_andMatrixOutputs_andMatrixInput_11_31) node decoder_decoded_andMatrixOutputs_lo_hi_43 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_35, decoder_decoded_andMatrixOutputs_lo_hi_lo_23) node decoder_decoded_andMatrixOutputs_lo_44 = cat(decoder_decoded_andMatrixOutputs_lo_hi_43, decoder_decoded_andMatrixOutputs_lo_lo_41) node decoder_decoded_andMatrixOutputs_hi_lo_lo_17 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_41, decoder_decoded_andMatrixOutputs_andMatrixInput_8_39) node decoder_decoded_andMatrixOutputs_hi_lo_hi_33 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_43, decoder_decoded_andMatrixOutputs_andMatrixInput_6_43) node decoder_decoded_andMatrixOutputs_hi_lo_43 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_33, decoder_decoded_andMatrixOutputs_hi_lo_lo_17) node decoder_decoded_andMatrixOutputs_hi_hi_lo_25 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_44, decoder_decoded_andMatrixOutputs_andMatrixInput_4_44) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_7 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_44, decoder_decoded_andMatrixOutputs_andMatrixInput_1_44) node decoder_decoded_andMatrixOutputs_hi_hi_hi_39 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_7, decoder_decoded_andMatrixOutputs_andMatrixInput_2_44) node decoder_decoded_andMatrixOutputs_hi_hi_44 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_39, decoder_decoded_andMatrixOutputs_hi_hi_lo_25) node decoder_decoded_andMatrixOutputs_hi_44 = cat(decoder_decoded_andMatrixOutputs_hi_hi_44, decoder_decoded_andMatrixOutputs_hi_lo_43) node _decoder_decoded_andMatrixOutputs_T_44 = cat(decoder_decoded_andMatrixOutputs_hi_44, decoder_decoded_andMatrixOutputs_lo_44) node decoder_decoded_andMatrixOutputs_32_2 = andr(_decoder_decoded_andMatrixOutputs_T_44) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_45 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_45 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_45 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_45 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_45 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_44 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_44 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_42 = bits(decoder_decoded_invInputs, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_40 = bits(decoder_decoded_invInputs, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_36 = bits(decoder_decoded_invInputs, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_34 = bits(decoder_decoded_invInputs, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_32 = bits(decoder_decoded_invInputs, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_26 = bits(decoder_decoded_plaInput, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_24 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_18 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_8 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_8 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_17_5 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_18_2 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_8 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_17_5, decoder_decoded_andMatrixOutputs_andMatrixInput_18_2) node decoder_decoded_andMatrixOutputs_lo_lo_hi_32 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_15_8, decoder_decoded_andMatrixOutputs_andMatrixInput_16_8) node decoder_decoded_andMatrixOutputs_lo_lo_42 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_32, decoder_decoded_andMatrixOutputs_lo_lo_lo_8) node decoder_decoded_andMatrixOutputs_lo_hi_lo_24 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_13_24, decoder_decoded_andMatrixOutputs_andMatrixInput_14_18) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_5 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_34, decoder_decoded_andMatrixOutputs_andMatrixInput_11_32) node decoder_decoded_andMatrixOutputs_lo_hi_hi_36 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_5, decoder_decoded_andMatrixOutputs_andMatrixInput_12_26) node decoder_decoded_andMatrixOutputs_lo_hi_44 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_36, decoder_decoded_andMatrixOutputs_lo_hi_lo_24) node decoder_decoded_andMatrixOutputs_lo_45 = cat(decoder_decoded_andMatrixOutputs_lo_hi_44, decoder_decoded_andMatrixOutputs_lo_lo_42) node decoder_decoded_andMatrixOutputs_hi_lo_lo_18 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_40, decoder_decoded_andMatrixOutputs_andMatrixInput_9_36) node decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_2 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_44, decoder_decoded_andMatrixOutputs_andMatrixInput_6_44) node decoder_decoded_andMatrixOutputs_hi_lo_hi_34 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_2, decoder_decoded_andMatrixOutputs_andMatrixInput_7_42) node decoder_decoded_andMatrixOutputs_hi_lo_44 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_34, decoder_decoded_andMatrixOutputs_hi_lo_lo_18) node decoder_decoded_andMatrixOutputs_hi_hi_lo_26 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_45, decoder_decoded_andMatrixOutputs_andMatrixInput_4_45) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_8 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_45, decoder_decoded_andMatrixOutputs_andMatrixInput_1_45) node decoder_decoded_andMatrixOutputs_hi_hi_hi_40 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_8, decoder_decoded_andMatrixOutputs_andMatrixInput_2_45) node decoder_decoded_andMatrixOutputs_hi_hi_45 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_40, decoder_decoded_andMatrixOutputs_hi_hi_lo_26) node decoder_decoded_andMatrixOutputs_hi_45 = cat(decoder_decoded_andMatrixOutputs_hi_hi_45, decoder_decoded_andMatrixOutputs_hi_lo_44) node _decoder_decoded_andMatrixOutputs_T_45 = cat(decoder_decoded_andMatrixOutputs_hi_45, decoder_decoded_andMatrixOutputs_lo_45) node decoder_decoded_andMatrixOutputs_13_2 = andr(_decoder_decoded_andMatrixOutputs_T_45) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_46 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_46 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_46 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_46 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_46 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_45 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_45 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_43 = bits(decoder_decoded_invInputs, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_41 = bits(decoder_decoded_invInputs, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_37 = bits(decoder_decoded_invInputs, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_35 = bits(decoder_decoded_invInputs, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_33 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_27 = bits(decoder_decoded_plaInput, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_25 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_19 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_9 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_9 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_lo_lo_lo_9 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_15_9, decoder_decoded_andMatrixOutputs_andMatrixInput_16_9) node decoder_decoded_andMatrixOutputs_lo_lo_hi_33 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_13_25, decoder_decoded_andMatrixOutputs_andMatrixInput_14_19) node decoder_decoded_andMatrixOutputs_lo_lo_43 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_33, decoder_decoded_andMatrixOutputs_lo_lo_lo_9) node decoder_decoded_andMatrixOutputs_lo_hi_lo_25 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_33, decoder_decoded_andMatrixOutputs_andMatrixInput_12_27) node decoder_decoded_andMatrixOutputs_lo_hi_hi_37 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_37, decoder_decoded_andMatrixOutputs_andMatrixInput_10_35) node decoder_decoded_andMatrixOutputs_lo_hi_45 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_37, decoder_decoded_andMatrixOutputs_lo_hi_lo_25) node decoder_decoded_andMatrixOutputs_lo_46 = cat(decoder_decoded_andMatrixOutputs_lo_hi_45, decoder_decoded_andMatrixOutputs_lo_lo_43) node decoder_decoded_andMatrixOutputs_hi_lo_lo_19 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_43, decoder_decoded_andMatrixOutputs_andMatrixInput_8_41) node decoder_decoded_andMatrixOutputs_hi_lo_hi_35 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_45, decoder_decoded_andMatrixOutputs_andMatrixInput_6_45) node decoder_decoded_andMatrixOutputs_hi_lo_45 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_35, decoder_decoded_andMatrixOutputs_hi_lo_lo_19) node decoder_decoded_andMatrixOutputs_hi_hi_lo_27 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_46, decoder_decoded_andMatrixOutputs_andMatrixInput_4_46) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_9 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_46, decoder_decoded_andMatrixOutputs_andMatrixInput_1_46) node decoder_decoded_andMatrixOutputs_hi_hi_hi_41 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_9, decoder_decoded_andMatrixOutputs_andMatrixInput_2_46) node decoder_decoded_andMatrixOutputs_hi_hi_46 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_41, decoder_decoded_andMatrixOutputs_hi_hi_lo_27) node decoder_decoded_andMatrixOutputs_hi_46 = cat(decoder_decoded_andMatrixOutputs_hi_hi_46, decoder_decoded_andMatrixOutputs_hi_lo_45) node _decoder_decoded_andMatrixOutputs_T_46 = cat(decoder_decoded_andMatrixOutputs_hi_46, decoder_decoded_andMatrixOutputs_lo_46) node decoder_decoded_andMatrixOutputs_52_2 = andr(_decoder_decoded_andMatrixOutputs_T_46) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_47 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_47 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_47 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_47 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_47 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_46 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_46 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_44 = bits(decoder_decoded_invInputs, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_42 = bits(decoder_decoded_invInputs, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_38 = bits(decoder_decoded_invInputs, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_36 = bits(decoder_decoded_invInputs, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_34 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_28 = bits(decoder_decoded_plaInput, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_26 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_20 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_10 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_10 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_17_6 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_10 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_16_10, decoder_decoded_andMatrixOutputs_andMatrixInput_17_6) node decoder_decoded_andMatrixOutputs_lo_lo_hi_34 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_20, decoder_decoded_andMatrixOutputs_andMatrixInput_15_10) node decoder_decoded_andMatrixOutputs_lo_lo_44 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_34, decoder_decoded_andMatrixOutputs_lo_lo_lo_10) node decoder_decoded_andMatrixOutputs_lo_hi_lo_26 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_28, decoder_decoded_andMatrixOutputs_andMatrixInput_13_26) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_6 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_38, decoder_decoded_andMatrixOutputs_andMatrixInput_10_36) node decoder_decoded_andMatrixOutputs_lo_hi_hi_38 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_6, decoder_decoded_andMatrixOutputs_andMatrixInput_11_34) node decoder_decoded_andMatrixOutputs_lo_hi_46 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_38, decoder_decoded_andMatrixOutputs_lo_hi_lo_26) node decoder_decoded_andMatrixOutputs_lo_47 = cat(decoder_decoded_andMatrixOutputs_lo_hi_46, decoder_decoded_andMatrixOutputs_lo_lo_44) node decoder_decoded_andMatrixOutputs_hi_lo_lo_20 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_44, decoder_decoded_andMatrixOutputs_andMatrixInput_8_42) node decoder_decoded_andMatrixOutputs_hi_lo_hi_36 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_46, decoder_decoded_andMatrixOutputs_andMatrixInput_6_46) node decoder_decoded_andMatrixOutputs_hi_lo_46 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_36, decoder_decoded_andMatrixOutputs_hi_lo_lo_20) node decoder_decoded_andMatrixOutputs_hi_hi_lo_28 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_47, decoder_decoded_andMatrixOutputs_andMatrixInput_4_47) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_10 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_47, decoder_decoded_andMatrixOutputs_andMatrixInput_1_47) node decoder_decoded_andMatrixOutputs_hi_hi_hi_42 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_10, decoder_decoded_andMatrixOutputs_andMatrixInput_2_47) node decoder_decoded_andMatrixOutputs_hi_hi_47 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_42, decoder_decoded_andMatrixOutputs_hi_hi_lo_28) node decoder_decoded_andMatrixOutputs_hi_47 = cat(decoder_decoded_andMatrixOutputs_hi_hi_47, decoder_decoded_andMatrixOutputs_hi_lo_46) node _decoder_decoded_andMatrixOutputs_T_47 = cat(decoder_decoded_andMatrixOutputs_hi_47, decoder_decoded_andMatrixOutputs_lo_47) node decoder_decoded_andMatrixOutputs_64_2 = andr(_decoder_decoded_andMatrixOutputs_T_47) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_48 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_48 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_48 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_48 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_48 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_47 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_47 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_45 = bits(decoder_decoded_invInputs, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_43 = bits(decoder_decoded_invInputs, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_39 = bits(decoder_decoded_invInputs, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_37 = bits(decoder_decoded_invInputs, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_35 = bits(decoder_decoded_invInputs, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_29 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_27 = bits(decoder_decoded_plaInput, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_21 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_11 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_11 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_17_7 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_18_3 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_11 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_17_7, decoder_decoded_andMatrixOutputs_andMatrixInput_18_3) node decoder_decoded_andMatrixOutputs_lo_lo_hi_35 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_15_11, decoder_decoded_andMatrixOutputs_andMatrixInput_16_11) node decoder_decoded_andMatrixOutputs_lo_lo_45 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_35, decoder_decoded_andMatrixOutputs_lo_lo_lo_11) node decoder_decoded_andMatrixOutputs_lo_hi_lo_27 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_13_27, decoder_decoded_andMatrixOutputs_andMatrixInput_14_21) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_7 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_37, decoder_decoded_andMatrixOutputs_andMatrixInput_11_35) node decoder_decoded_andMatrixOutputs_lo_hi_hi_39 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_7, decoder_decoded_andMatrixOutputs_andMatrixInput_12_29) node decoder_decoded_andMatrixOutputs_lo_hi_47 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_39, decoder_decoded_andMatrixOutputs_lo_hi_lo_27) node decoder_decoded_andMatrixOutputs_lo_48 = cat(decoder_decoded_andMatrixOutputs_lo_hi_47, decoder_decoded_andMatrixOutputs_lo_lo_45) node decoder_decoded_andMatrixOutputs_hi_lo_lo_21 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_43, decoder_decoded_andMatrixOutputs_andMatrixInput_9_39) node decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_3 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_47, decoder_decoded_andMatrixOutputs_andMatrixInput_6_47) node decoder_decoded_andMatrixOutputs_hi_lo_hi_37 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_3, decoder_decoded_andMatrixOutputs_andMatrixInput_7_45) node decoder_decoded_andMatrixOutputs_hi_lo_47 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_37, decoder_decoded_andMatrixOutputs_hi_lo_lo_21) node decoder_decoded_andMatrixOutputs_hi_hi_lo_29 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_48, decoder_decoded_andMatrixOutputs_andMatrixInput_4_48) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_11 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_48, decoder_decoded_andMatrixOutputs_andMatrixInput_1_48) node decoder_decoded_andMatrixOutputs_hi_hi_hi_43 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_11, decoder_decoded_andMatrixOutputs_andMatrixInput_2_48) node decoder_decoded_andMatrixOutputs_hi_hi_48 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_43, decoder_decoded_andMatrixOutputs_hi_hi_lo_29) node decoder_decoded_andMatrixOutputs_hi_48 = cat(decoder_decoded_andMatrixOutputs_hi_hi_48, decoder_decoded_andMatrixOutputs_hi_lo_47) node _decoder_decoded_andMatrixOutputs_T_48 = cat(decoder_decoded_andMatrixOutputs_hi_48, decoder_decoded_andMatrixOutputs_lo_48) node decoder_decoded_andMatrixOutputs_11_2 = andr(_decoder_decoded_andMatrixOutputs_T_48) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_49 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_49 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_49 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_49 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_49 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_48 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_48 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_46 = bits(decoder_decoded_invInputs, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_44 = bits(decoder_decoded_invInputs, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_40 = bits(decoder_decoded_invInputs, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_38 = bits(decoder_decoded_invInputs, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_36 = bits(decoder_decoded_invInputs, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_30 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_28 = bits(decoder_decoded_plaInput, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_22 = bits(decoder_decoded_plaInput, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_12 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_12 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_17_8 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_12 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_16_12, decoder_decoded_andMatrixOutputs_andMatrixInput_17_8) node decoder_decoded_andMatrixOutputs_lo_lo_hi_36 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_22, decoder_decoded_andMatrixOutputs_andMatrixInput_15_12) node decoder_decoded_andMatrixOutputs_lo_lo_46 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_36, decoder_decoded_andMatrixOutputs_lo_lo_lo_12) node decoder_decoded_andMatrixOutputs_lo_hi_lo_28 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_30, decoder_decoded_andMatrixOutputs_andMatrixInput_13_28) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_8 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_40, decoder_decoded_andMatrixOutputs_andMatrixInput_10_38) node decoder_decoded_andMatrixOutputs_lo_hi_hi_40 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_8, decoder_decoded_andMatrixOutputs_andMatrixInput_11_36) node decoder_decoded_andMatrixOutputs_lo_hi_48 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_40, decoder_decoded_andMatrixOutputs_lo_hi_lo_28) node decoder_decoded_andMatrixOutputs_lo_49 = cat(decoder_decoded_andMatrixOutputs_lo_hi_48, decoder_decoded_andMatrixOutputs_lo_lo_46) node decoder_decoded_andMatrixOutputs_hi_lo_lo_22 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_46, decoder_decoded_andMatrixOutputs_andMatrixInput_8_44) node decoder_decoded_andMatrixOutputs_hi_lo_hi_38 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_48, decoder_decoded_andMatrixOutputs_andMatrixInput_6_48) node decoder_decoded_andMatrixOutputs_hi_lo_48 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_38, decoder_decoded_andMatrixOutputs_hi_lo_lo_22) node decoder_decoded_andMatrixOutputs_hi_hi_lo_30 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_49, decoder_decoded_andMatrixOutputs_andMatrixInput_4_49) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_12 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_49, decoder_decoded_andMatrixOutputs_andMatrixInput_1_49) node decoder_decoded_andMatrixOutputs_hi_hi_hi_44 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_12, decoder_decoded_andMatrixOutputs_andMatrixInput_2_49) node decoder_decoded_andMatrixOutputs_hi_hi_49 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_44, decoder_decoded_andMatrixOutputs_hi_hi_lo_30) node decoder_decoded_andMatrixOutputs_hi_49 = cat(decoder_decoded_andMatrixOutputs_hi_hi_49, decoder_decoded_andMatrixOutputs_hi_lo_48) node _decoder_decoded_andMatrixOutputs_T_49 = cat(decoder_decoded_andMatrixOutputs_hi_49, decoder_decoded_andMatrixOutputs_lo_49) node decoder_decoded_andMatrixOutputs_26_2 = andr(_decoder_decoded_andMatrixOutputs_T_49) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_50 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_50 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_50 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_50 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_50 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_49 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_49 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_47 = bits(decoder_decoded_invInputs, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_45 = bits(decoder_decoded_invInputs, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_41 = bits(decoder_decoded_invInputs, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_39 = bits(decoder_decoded_invInputs, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_37 = bits(decoder_decoded_invInputs, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_31 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_29 = bits(decoder_decoded_plaInput, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_23 = bits(decoder_decoded_plaInput, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_13 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_13 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_17_9 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_13 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_16_13, decoder_decoded_andMatrixOutputs_andMatrixInput_17_9) node decoder_decoded_andMatrixOutputs_lo_lo_hi_37 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_23, decoder_decoded_andMatrixOutputs_andMatrixInput_15_13) node decoder_decoded_andMatrixOutputs_lo_lo_47 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_37, decoder_decoded_andMatrixOutputs_lo_lo_lo_13) node decoder_decoded_andMatrixOutputs_lo_hi_lo_29 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_31, decoder_decoded_andMatrixOutputs_andMatrixInput_13_29) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_9 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_41, decoder_decoded_andMatrixOutputs_andMatrixInput_10_39) node decoder_decoded_andMatrixOutputs_lo_hi_hi_41 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_9, decoder_decoded_andMatrixOutputs_andMatrixInput_11_37) node decoder_decoded_andMatrixOutputs_lo_hi_49 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_41, decoder_decoded_andMatrixOutputs_lo_hi_lo_29) node decoder_decoded_andMatrixOutputs_lo_50 = cat(decoder_decoded_andMatrixOutputs_lo_hi_49, decoder_decoded_andMatrixOutputs_lo_lo_47) node decoder_decoded_andMatrixOutputs_hi_lo_lo_23 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_47, decoder_decoded_andMatrixOutputs_andMatrixInput_8_45) node decoder_decoded_andMatrixOutputs_hi_lo_hi_39 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_49, decoder_decoded_andMatrixOutputs_andMatrixInput_6_49) node decoder_decoded_andMatrixOutputs_hi_lo_49 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_39, decoder_decoded_andMatrixOutputs_hi_lo_lo_23) node decoder_decoded_andMatrixOutputs_hi_hi_lo_31 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_50, decoder_decoded_andMatrixOutputs_andMatrixInput_4_50) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_13 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_50, decoder_decoded_andMatrixOutputs_andMatrixInput_1_50) node decoder_decoded_andMatrixOutputs_hi_hi_hi_45 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_13, decoder_decoded_andMatrixOutputs_andMatrixInput_2_50) node decoder_decoded_andMatrixOutputs_hi_hi_50 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_45, decoder_decoded_andMatrixOutputs_hi_hi_lo_31) node decoder_decoded_andMatrixOutputs_hi_50 = cat(decoder_decoded_andMatrixOutputs_hi_hi_50, decoder_decoded_andMatrixOutputs_hi_lo_49) node _decoder_decoded_andMatrixOutputs_T_50 = cat(decoder_decoded_andMatrixOutputs_hi_50, decoder_decoded_andMatrixOutputs_lo_50) node decoder_decoded_andMatrixOutputs_58_2 = andr(_decoder_decoded_andMatrixOutputs_T_50) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_51 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_51 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_51 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_51 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_51 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_50 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_50 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_48 = bits(decoder_decoded_invInputs, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_46 = bits(decoder_decoded_invInputs, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_42 = bits(decoder_decoded_invInputs, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_40 = bits(decoder_decoded_invInputs, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_38 = bits(decoder_decoded_invInputs, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_32 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_30 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_24 = bits(decoder_decoded_plaInput, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_14 = bits(decoder_decoded_plaInput, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_14 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_17_10 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_18_4 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_14 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_17_10, decoder_decoded_andMatrixOutputs_andMatrixInput_18_4) node decoder_decoded_andMatrixOutputs_lo_lo_hi_38 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_15_14, decoder_decoded_andMatrixOutputs_andMatrixInput_16_14) node decoder_decoded_andMatrixOutputs_lo_lo_48 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_38, decoder_decoded_andMatrixOutputs_lo_lo_lo_14) node decoder_decoded_andMatrixOutputs_lo_hi_lo_30 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_13_30, decoder_decoded_andMatrixOutputs_andMatrixInput_14_24) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_10 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_40, decoder_decoded_andMatrixOutputs_andMatrixInput_11_38) node decoder_decoded_andMatrixOutputs_lo_hi_hi_42 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_10, decoder_decoded_andMatrixOutputs_andMatrixInput_12_32) node decoder_decoded_andMatrixOutputs_lo_hi_50 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_42, decoder_decoded_andMatrixOutputs_lo_hi_lo_30) node decoder_decoded_andMatrixOutputs_lo_51 = cat(decoder_decoded_andMatrixOutputs_lo_hi_50, decoder_decoded_andMatrixOutputs_lo_lo_48) node decoder_decoded_andMatrixOutputs_hi_lo_lo_24 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_46, decoder_decoded_andMatrixOutputs_andMatrixInput_9_42) node decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_4 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_50, decoder_decoded_andMatrixOutputs_andMatrixInput_6_50) node decoder_decoded_andMatrixOutputs_hi_lo_hi_40 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_4, decoder_decoded_andMatrixOutputs_andMatrixInput_7_48) node decoder_decoded_andMatrixOutputs_hi_lo_50 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_40, decoder_decoded_andMatrixOutputs_hi_lo_lo_24) node decoder_decoded_andMatrixOutputs_hi_hi_lo_32 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_51, decoder_decoded_andMatrixOutputs_andMatrixInput_4_51) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_14 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_51, decoder_decoded_andMatrixOutputs_andMatrixInput_1_51) node decoder_decoded_andMatrixOutputs_hi_hi_hi_46 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_14, decoder_decoded_andMatrixOutputs_andMatrixInput_2_51) node decoder_decoded_andMatrixOutputs_hi_hi_51 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_46, decoder_decoded_andMatrixOutputs_hi_hi_lo_32) node decoder_decoded_andMatrixOutputs_hi_51 = cat(decoder_decoded_andMatrixOutputs_hi_hi_51, decoder_decoded_andMatrixOutputs_hi_lo_50) node _decoder_decoded_andMatrixOutputs_T_51 = cat(decoder_decoded_andMatrixOutputs_hi_51, decoder_decoded_andMatrixOutputs_lo_51) node decoder_decoded_andMatrixOutputs_76_2 = andr(_decoder_decoded_andMatrixOutputs_T_51) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_52 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_52 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_52 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_52 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_52 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_51 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_51 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_49 = bits(decoder_decoded_invInputs, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_47 = bits(decoder_decoded_invInputs, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_43 = bits(decoder_decoded_invInputs, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_41 = bits(decoder_decoded_invInputs, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_39 = bits(decoder_decoded_invInputs, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_33 = bits(decoder_decoded_plaInput, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_31 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_25 = bits(decoder_decoded_plaInput, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_15 = bits(decoder_decoded_plaInput, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_15 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_17_11 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_18_5 = bits(decoder_decoded_invInputs, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_15 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_17_11, decoder_decoded_andMatrixOutputs_andMatrixInput_18_5) node decoder_decoded_andMatrixOutputs_lo_lo_hi_39 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_15_15, decoder_decoded_andMatrixOutputs_andMatrixInput_16_15) node decoder_decoded_andMatrixOutputs_lo_lo_49 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_39, decoder_decoded_andMatrixOutputs_lo_lo_lo_15) node decoder_decoded_andMatrixOutputs_lo_hi_lo_31 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_13_31, decoder_decoded_andMatrixOutputs_andMatrixInput_14_25) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_11 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_41, decoder_decoded_andMatrixOutputs_andMatrixInput_11_39) node decoder_decoded_andMatrixOutputs_lo_hi_hi_43 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_11, decoder_decoded_andMatrixOutputs_andMatrixInput_12_33) node decoder_decoded_andMatrixOutputs_lo_hi_51 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_43, decoder_decoded_andMatrixOutputs_lo_hi_lo_31) node decoder_decoded_andMatrixOutputs_lo_52 = cat(decoder_decoded_andMatrixOutputs_lo_hi_51, decoder_decoded_andMatrixOutputs_lo_lo_49) node decoder_decoded_andMatrixOutputs_hi_lo_lo_25 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_47, decoder_decoded_andMatrixOutputs_andMatrixInput_9_43) node decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_5 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_51, decoder_decoded_andMatrixOutputs_andMatrixInput_6_51) node decoder_decoded_andMatrixOutputs_hi_lo_hi_41 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_5, decoder_decoded_andMatrixOutputs_andMatrixInput_7_49) node decoder_decoded_andMatrixOutputs_hi_lo_51 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_41, decoder_decoded_andMatrixOutputs_hi_lo_lo_25) node decoder_decoded_andMatrixOutputs_hi_hi_lo_33 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_52, decoder_decoded_andMatrixOutputs_andMatrixInput_4_52) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_15 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_52, decoder_decoded_andMatrixOutputs_andMatrixInput_1_52) node decoder_decoded_andMatrixOutputs_hi_hi_hi_47 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_15, decoder_decoded_andMatrixOutputs_andMatrixInput_2_52) node decoder_decoded_andMatrixOutputs_hi_hi_52 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_47, decoder_decoded_andMatrixOutputs_hi_hi_lo_33) node decoder_decoded_andMatrixOutputs_hi_52 = cat(decoder_decoded_andMatrixOutputs_hi_hi_52, decoder_decoded_andMatrixOutputs_hi_lo_51) node _decoder_decoded_andMatrixOutputs_T_52 = cat(decoder_decoded_andMatrixOutputs_hi_52, decoder_decoded_andMatrixOutputs_lo_52) node decoder_decoded_andMatrixOutputs_51_2 = andr(_decoder_decoded_andMatrixOutputs_T_52) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_53 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_53 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_53 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_53 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_53 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_52 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_52 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_50 = bits(decoder_decoded_invInputs, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_48 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_44 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_42 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_40 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_34 = bits(decoder_decoded_plaInput, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_32 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_26 = bits(decoder_decoded_plaInput, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_40 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_34, decoder_decoded_andMatrixOutputs_andMatrixInput_13_32) node decoder_decoded_andMatrixOutputs_lo_lo_50 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_40, decoder_decoded_andMatrixOutputs_andMatrixInput_14_26) node decoder_decoded_andMatrixOutputs_lo_hi_lo_32 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_42, decoder_decoded_andMatrixOutputs_andMatrixInput_11_40) node decoder_decoded_andMatrixOutputs_lo_hi_hi_44 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_48, decoder_decoded_andMatrixOutputs_andMatrixInput_9_44) node decoder_decoded_andMatrixOutputs_lo_hi_52 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_44, decoder_decoded_andMatrixOutputs_lo_hi_lo_32) node decoder_decoded_andMatrixOutputs_lo_53 = cat(decoder_decoded_andMatrixOutputs_lo_hi_52, decoder_decoded_andMatrixOutputs_lo_lo_50) node decoder_decoded_andMatrixOutputs_hi_lo_lo_26 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_52, decoder_decoded_andMatrixOutputs_andMatrixInput_7_50) node decoder_decoded_andMatrixOutputs_hi_lo_hi_42 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_53, decoder_decoded_andMatrixOutputs_andMatrixInput_5_52) node decoder_decoded_andMatrixOutputs_hi_lo_52 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_42, decoder_decoded_andMatrixOutputs_hi_lo_lo_26) node decoder_decoded_andMatrixOutputs_hi_hi_lo_34 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_53, decoder_decoded_andMatrixOutputs_andMatrixInput_3_53) node decoder_decoded_andMatrixOutputs_hi_hi_hi_48 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_53, decoder_decoded_andMatrixOutputs_andMatrixInput_1_53) node decoder_decoded_andMatrixOutputs_hi_hi_53 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_48, decoder_decoded_andMatrixOutputs_hi_hi_lo_34) node decoder_decoded_andMatrixOutputs_hi_53 = cat(decoder_decoded_andMatrixOutputs_hi_hi_53, decoder_decoded_andMatrixOutputs_hi_lo_52) node _decoder_decoded_andMatrixOutputs_T_53 = cat(decoder_decoded_andMatrixOutputs_hi_53, decoder_decoded_andMatrixOutputs_lo_53) node decoder_decoded_andMatrixOutputs_2_2 = andr(_decoder_decoded_andMatrixOutputs_T_53) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_54 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_54 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_54 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_54 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_54 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_53 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_53 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_51 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_49 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_45 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_43 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_41 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_35 = bits(decoder_decoded_plaInput, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_33 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_27 = bits(decoder_decoded_plaInput, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_41 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_35, decoder_decoded_andMatrixOutputs_andMatrixInput_13_33) node decoder_decoded_andMatrixOutputs_lo_lo_51 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_41, decoder_decoded_andMatrixOutputs_andMatrixInput_14_27) node decoder_decoded_andMatrixOutputs_lo_hi_lo_33 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_43, decoder_decoded_andMatrixOutputs_andMatrixInput_11_41) node decoder_decoded_andMatrixOutputs_lo_hi_hi_45 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_49, decoder_decoded_andMatrixOutputs_andMatrixInput_9_45) node decoder_decoded_andMatrixOutputs_lo_hi_53 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_45, decoder_decoded_andMatrixOutputs_lo_hi_lo_33) node decoder_decoded_andMatrixOutputs_lo_54 = cat(decoder_decoded_andMatrixOutputs_lo_hi_53, decoder_decoded_andMatrixOutputs_lo_lo_51) node decoder_decoded_andMatrixOutputs_hi_lo_lo_27 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_53, decoder_decoded_andMatrixOutputs_andMatrixInput_7_51) node decoder_decoded_andMatrixOutputs_hi_lo_hi_43 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_54, decoder_decoded_andMatrixOutputs_andMatrixInput_5_53) node decoder_decoded_andMatrixOutputs_hi_lo_53 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_43, decoder_decoded_andMatrixOutputs_hi_lo_lo_27) node decoder_decoded_andMatrixOutputs_hi_hi_lo_35 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_54, decoder_decoded_andMatrixOutputs_andMatrixInput_3_54) node decoder_decoded_andMatrixOutputs_hi_hi_hi_49 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_54, decoder_decoded_andMatrixOutputs_andMatrixInput_1_54) node decoder_decoded_andMatrixOutputs_hi_hi_54 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_49, decoder_decoded_andMatrixOutputs_hi_hi_lo_35) node decoder_decoded_andMatrixOutputs_hi_54 = cat(decoder_decoded_andMatrixOutputs_hi_hi_54, decoder_decoded_andMatrixOutputs_hi_lo_53) node _decoder_decoded_andMatrixOutputs_T_54 = cat(decoder_decoded_andMatrixOutputs_hi_54, decoder_decoded_andMatrixOutputs_lo_54) node decoder_decoded_andMatrixOutputs_31_2 = andr(_decoder_decoded_andMatrixOutputs_T_54) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_55 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_55 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_55 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_55 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_55 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_54 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_54 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_52 = bits(decoder_decoded_invInputs, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_50 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_46 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_44 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_42 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_36 = bits(decoder_decoded_plaInput, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_34 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_28 = bits(decoder_decoded_plaInput, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_42 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_36, decoder_decoded_andMatrixOutputs_andMatrixInput_13_34) node decoder_decoded_andMatrixOutputs_lo_lo_52 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_42, decoder_decoded_andMatrixOutputs_andMatrixInput_14_28) node decoder_decoded_andMatrixOutputs_lo_hi_lo_34 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_44, decoder_decoded_andMatrixOutputs_andMatrixInput_11_42) node decoder_decoded_andMatrixOutputs_lo_hi_hi_46 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_50, decoder_decoded_andMatrixOutputs_andMatrixInput_9_46) node decoder_decoded_andMatrixOutputs_lo_hi_54 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_46, decoder_decoded_andMatrixOutputs_lo_hi_lo_34) node decoder_decoded_andMatrixOutputs_lo_55 = cat(decoder_decoded_andMatrixOutputs_lo_hi_54, decoder_decoded_andMatrixOutputs_lo_lo_52) node decoder_decoded_andMatrixOutputs_hi_lo_lo_28 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_54, decoder_decoded_andMatrixOutputs_andMatrixInput_7_52) node decoder_decoded_andMatrixOutputs_hi_lo_hi_44 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_55, decoder_decoded_andMatrixOutputs_andMatrixInput_5_54) node decoder_decoded_andMatrixOutputs_hi_lo_54 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_44, decoder_decoded_andMatrixOutputs_hi_lo_lo_28) node decoder_decoded_andMatrixOutputs_hi_hi_lo_36 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_55, decoder_decoded_andMatrixOutputs_andMatrixInput_3_55) node decoder_decoded_andMatrixOutputs_hi_hi_hi_50 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_55, decoder_decoded_andMatrixOutputs_andMatrixInput_1_55) node decoder_decoded_andMatrixOutputs_hi_hi_55 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_50, decoder_decoded_andMatrixOutputs_hi_hi_lo_36) node decoder_decoded_andMatrixOutputs_hi_55 = cat(decoder_decoded_andMatrixOutputs_hi_hi_55, decoder_decoded_andMatrixOutputs_hi_lo_54) node _decoder_decoded_andMatrixOutputs_T_55 = cat(decoder_decoded_andMatrixOutputs_hi_55, decoder_decoded_andMatrixOutputs_lo_55) node decoder_decoded_andMatrixOutputs_68_2 = andr(_decoder_decoded_andMatrixOutputs_T_55) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_56 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_56 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_56 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_56 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_56 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_55 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_55 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_53 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_51 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_47 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_45 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_43 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_37 = bits(decoder_decoded_plaInput, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_35 = bits(decoder_decoded_invInputs, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_29 = bits(decoder_decoded_plaInput, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_43 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_37, decoder_decoded_andMatrixOutputs_andMatrixInput_13_35) node decoder_decoded_andMatrixOutputs_lo_lo_53 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_43, decoder_decoded_andMatrixOutputs_andMatrixInput_14_29) node decoder_decoded_andMatrixOutputs_lo_hi_lo_35 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_45, decoder_decoded_andMatrixOutputs_andMatrixInput_11_43) node decoder_decoded_andMatrixOutputs_lo_hi_hi_47 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_51, decoder_decoded_andMatrixOutputs_andMatrixInput_9_47) node decoder_decoded_andMatrixOutputs_lo_hi_55 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_47, decoder_decoded_andMatrixOutputs_lo_hi_lo_35) node decoder_decoded_andMatrixOutputs_lo_56 = cat(decoder_decoded_andMatrixOutputs_lo_hi_55, decoder_decoded_andMatrixOutputs_lo_lo_53) node decoder_decoded_andMatrixOutputs_hi_lo_lo_29 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_55, decoder_decoded_andMatrixOutputs_andMatrixInput_7_53) node decoder_decoded_andMatrixOutputs_hi_lo_hi_45 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_56, decoder_decoded_andMatrixOutputs_andMatrixInput_5_55) node decoder_decoded_andMatrixOutputs_hi_lo_55 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_45, decoder_decoded_andMatrixOutputs_hi_lo_lo_29) node decoder_decoded_andMatrixOutputs_hi_hi_lo_37 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_56, decoder_decoded_andMatrixOutputs_andMatrixInput_3_56) node decoder_decoded_andMatrixOutputs_hi_hi_hi_51 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_56, decoder_decoded_andMatrixOutputs_andMatrixInput_1_56) node decoder_decoded_andMatrixOutputs_hi_hi_56 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_51, decoder_decoded_andMatrixOutputs_hi_hi_lo_37) node decoder_decoded_andMatrixOutputs_hi_56 = cat(decoder_decoded_andMatrixOutputs_hi_hi_56, decoder_decoded_andMatrixOutputs_hi_lo_55) node _decoder_decoded_andMatrixOutputs_T_56 = cat(decoder_decoded_andMatrixOutputs_hi_56, decoder_decoded_andMatrixOutputs_lo_56) node decoder_decoded_andMatrixOutputs_62_2 = andr(_decoder_decoded_andMatrixOutputs_T_56) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_57 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_57 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_57 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_57 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_57 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_56 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_56 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_54 = bits(decoder_decoded_invInputs, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_52 = bits(decoder_decoded_invInputs, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_48 = bits(decoder_decoded_invInputs, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_46 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_44 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_38 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_36 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_30 = bits(decoder_decoded_plaInput, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_44 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_38, decoder_decoded_andMatrixOutputs_andMatrixInput_13_36) node decoder_decoded_andMatrixOutputs_lo_lo_54 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_44, decoder_decoded_andMatrixOutputs_andMatrixInput_14_30) node decoder_decoded_andMatrixOutputs_lo_hi_lo_36 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_46, decoder_decoded_andMatrixOutputs_andMatrixInput_11_44) node decoder_decoded_andMatrixOutputs_lo_hi_hi_48 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_52, decoder_decoded_andMatrixOutputs_andMatrixInput_9_48) node decoder_decoded_andMatrixOutputs_lo_hi_56 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_48, decoder_decoded_andMatrixOutputs_lo_hi_lo_36) node decoder_decoded_andMatrixOutputs_lo_57 = cat(decoder_decoded_andMatrixOutputs_lo_hi_56, decoder_decoded_andMatrixOutputs_lo_lo_54) node decoder_decoded_andMatrixOutputs_hi_lo_lo_30 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_56, decoder_decoded_andMatrixOutputs_andMatrixInput_7_54) node decoder_decoded_andMatrixOutputs_hi_lo_hi_46 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_57, decoder_decoded_andMatrixOutputs_andMatrixInput_5_56) node decoder_decoded_andMatrixOutputs_hi_lo_56 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_46, decoder_decoded_andMatrixOutputs_hi_lo_lo_30) node decoder_decoded_andMatrixOutputs_hi_hi_lo_38 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_57, decoder_decoded_andMatrixOutputs_andMatrixInput_3_57) node decoder_decoded_andMatrixOutputs_hi_hi_hi_52 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_57, decoder_decoded_andMatrixOutputs_andMatrixInput_1_57) node decoder_decoded_andMatrixOutputs_hi_hi_57 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_52, decoder_decoded_andMatrixOutputs_hi_hi_lo_38) node decoder_decoded_andMatrixOutputs_hi_57 = cat(decoder_decoded_andMatrixOutputs_hi_hi_57, decoder_decoded_andMatrixOutputs_hi_lo_56) node _decoder_decoded_andMatrixOutputs_T_57 = cat(decoder_decoded_andMatrixOutputs_hi_57, decoder_decoded_andMatrixOutputs_lo_57) node decoder_decoded_andMatrixOutputs_65_2 = andr(_decoder_decoded_andMatrixOutputs_T_57) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_58 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_58 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_58 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_58 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_58 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_57 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_57 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_55 = bits(decoder_decoded_invInputs, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_53 = bits(decoder_decoded_invInputs, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_49 = bits(decoder_decoded_invInputs, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_47 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_45 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_39 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_37 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_31 = bits(decoder_decoded_plaInput, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_hi_45 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_39, decoder_decoded_andMatrixOutputs_andMatrixInput_13_37) node decoder_decoded_andMatrixOutputs_lo_lo_55 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_45, decoder_decoded_andMatrixOutputs_andMatrixInput_14_31) node decoder_decoded_andMatrixOutputs_lo_hi_lo_37 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_47, decoder_decoded_andMatrixOutputs_andMatrixInput_11_45) node decoder_decoded_andMatrixOutputs_lo_hi_hi_49 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_53, decoder_decoded_andMatrixOutputs_andMatrixInput_9_49) node decoder_decoded_andMatrixOutputs_lo_hi_57 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_49, decoder_decoded_andMatrixOutputs_lo_hi_lo_37) node decoder_decoded_andMatrixOutputs_lo_58 = cat(decoder_decoded_andMatrixOutputs_lo_hi_57, decoder_decoded_andMatrixOutputs_lo_lo_55) node decoder_decoded_andMatrixOutputs_hi_lo_lo_31 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_57, decoder_decoded_andMatrixOutputs_andMatrixInput_7_55) node decoder_decoded_andMatrixOutputs_hi_lo_hi_47 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_58, decoder_decoded_andMatrixOutputs_andMatrixInput_5_57) node decoder_decoded_andMatrixOutputs_hi_lo_57 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_47, decoder_decoded_andMatrixOutputs_hi_lo_lo_31) node decoder_decoded_andMatrixOutputs_hi_hi_lo_39 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_58, decoder_decoded_andMatrixOutputs_andMatrixInput_3_58) node decoder_decoded_andMatrixOutputs_hi_hi_hi_53 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_58, decoder_decoded_andMatrixOutputs_andMatrixInput_1_58) node decoder_decoded_andMatrixOutputs_hi_hi_58 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_53, decoder_decoded_andMatrixOutputs_hi_hi_lo_39) node decoder_decoded_andMatrixOutputs_hi_58 = cat(decoder_decoded_andMatrixOutputs_hi_hi_58, decoder_decoded_andMatrixOutputs_hi_lo_57) node _decoder_decoded_andMatrixOutputs_T_58 = cat(decoder_decoded_andMatrixOutputs_hi_58, decoder_decoded_andMatrixOutputs_lo_58) node decoder_decoded_andMatrixOutputs_45_2 = andr(_decoder_decoded_andMatrixOutputs_T_58) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_59 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_59 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_59 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_59 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_59 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_58 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_58 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_56 = bits(decoder_decoded_invInputs, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_54 = bits(decoder_decoded_invInputs, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_50 = bits(decoder_decoded_invInputs, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_48 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_46 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_40 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_38 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_32 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_16 = bits(decoder_decoded_plaInput, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_16 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_32, decoder_decoded_andMatrixOutputs_andMatrixInput_15_16) node decoder_decoded_andMatrixOutputs_lo_lo_hi_46 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_40, decoder_decoded_andMatrixOutputs_andMatrixInput_13_38) node decoder_decoded_andMatrixOutputs_lo_lo_56 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_46, decoder_decoded_andMatrixOutputs_lo_lo_lo_16) node decoder_decoded_andMatrixOutputs_lo_hi_lo_38 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_48, decoder_decoded_andMatrixOutputs_andMatrixInput_11_46) node decoder_decoded_andMatrixOutputs_lo_hi_hi_50 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_54, decoder_decoded_andMatrixOutputs_andMatrixInput_9_50) node decoder_decoded_andMatrixOutputs_lo_hi_58 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_50, decoder_decoded_andMatrixOutputs_lo_hi_lo_38) node decoder_decoded_andMatrixOutputs_lo_59 = cat(decoder_decoded_andMatrixOutputs_lo_hi_58, decoder_decoded_andMatrixOutputs_lo_lo_56) node decoder_decoded_andMatrixOutputs_hi_lo_lo_32 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_58, decoder_decoded_andMatrixOutputs_andMatrixInput_7_56) node decoder_decoded_andMatrixOutputs_hi_lo_hi_48 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_59, decoder_decoded_andMatrixOutputs_andMatrixInput_5_58) node decoder_decoded_andMatrixOutputs_hi_lo_58 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_48, decoder_decoded_andMatrixOutputs_hi_lo_lo_32) node decoder_decoded_andMatrixOutputs_hi_hi_lo_40 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_59, decoder_decoded_andMatrixOutputs_andMatrixInput_3_59) node decoder_decoded_andMatrixOutputs_hi_hi_hi_54 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_59, decoder_decoded_andMatrixOutputs_andMatrixInput_1_59) node decoder_decoded_andMatrixOutputs_hi_hi_59 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_54, decoder_decoded_andMatrixOutputs_hi_hi_lo_40) node decoder_decoded_andMatrixOutputs_hi_59 = cat(decoder_decoded_andMatrixOutputs_hi_hi_59, decoder_decoded_andMatrixOutputs_hi_lo_58) node _decoder_decoded_andMatrixOutputs_T_59 = cat(decoder_decoded_andMatrixOutputs_hi_59, decoder_decoded_andMatrixOutputs_lo_59) node decoder_decoded_andMatrixOutputs_25_2 = andr(_decoder_decoded_andMatrixOutputs_T_59) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_60 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_60 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_60 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_60 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_60 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_59 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_59 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_57 = bits(decoder_decoded_invInputs, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_55 = bits(decoder_decoded_invInputs, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_51 = bits(decoder_decoded_invInputs, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_49 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_47 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_41 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_39 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_33 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_17 = bits(decoder_decoded_plaInput, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_17 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_33, decoder_decoded_andMatrixOutputs_andMatrixInput_15_17) node decoder_decoded_andMatrixOutputs_lo_lo_hi_47 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_41, decoder_decoded_andMatrixOutputs_andMatrixInput_13_39) node decoder_decoded_andMatrixOutputs_lo_lo_57 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_47, decoder_decoded_andMatrixOutputs_lo_lo_lo_17) node decoder_decoded_andMatrixOutputs_lo_hi_lo_39 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_49, decoder_decoded_andMatrixOutputs_andMatrixInput_11_47) node decoder_decoded_andMatrixOutputs_lo_hi_hi_51 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_55, decoder_decoded_andMatrixOutputs_andMatrixInput_9_51) node decoder_decoded_andMatrixOutputs_lo_hi_59 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_51, decoder_decoded_andMatrixOutputs_lo_hi_lo_39) node decoder_decoded_andMatrixOutputs_lo_60 = cat(decoder_decoded_andMatrixOutputs_lo_hi_59, decoder_decoded_andMatrixOutputs_lo_lo_57) node decoder_decoded_andMatrixOutputs_hi_lo_lo_33 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_59, decoder_decoded_andMatrixOutputs_andMatrixInput_7_57) node decoder_decoded_andMatrixOutputs_hi_lo_hi_49 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_60, decoder_decoded_andMatrixOutputs_andMatrixInput_5_59) node decoder_decoded_andMatrixOutputs_hi_lo_59 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_49, decoder_decoded_andMatrixOutputs_hi_lo_lo_33) node decoder_decoded_andMatrixOutputs_hi_hi_lo_41 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_60, decoder_decoded_andMatrixOutputs_andMatrixInput_3_60) node decoder_decoded_andMatrixOutputs_hi_hi_hi_55 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_60, decoder_decoded_andMatrixOutputs_andMatrixInput_1_60) node decoder_decoded_andMatrixOutputs_hi_hi_60 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_55, decoder_decoded_andMatrixOutputs_hi_hi_lo_41) node decoder_decoded_andMatrixOutputs_hi_60 = cat(decoder_decoded_andMatrixOutputs_hi_hi_60, decoder_decoded_andMatrixOutputs_hi_lo_59) node _decoder_decoded_andMatrixOutputs_T_60 = cat(decoder_decoded_andMatrixOutputs_hi_60, decoder_decoded_andMatrixOutputs_lo_60) node decoder_decoded_andMatrixOutputs_0_2 = andr(_decoder_decoded_andMatrixOutputs_T_60) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_61 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_61 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_61 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_61 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_61 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_60 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_60 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_58 = bits(decoder_decoded_invInputs, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_56 = bits(decoder_decoded_invInputs, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_52 = bits(decoder_decoded_invInputs, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_50 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_48 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_42 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_40 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_34 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_18 = bits(decoder_decoded_plaInput, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_18 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_34, decoder_decoded_andMatrixOutputs_andMatrixInput_15_18) node decoder_decoded_andMatrixOutputs_lo_lo_hi_48 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_42, decoder_decoded_andMatrixOutputs_andMatrixInput_13_40) node decoder_decoded_andMatrixOutputs_lo_lo_58 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_48, decoder_decoded_andMatrixOutputs_lo_lo_lo_18) node decoder_decoded_andMatrixOutputs_lo_hi_lo_40 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_50, decoder_decoded_andMatrixOutputs_andMatrixInput_11_48) node decoder_decoded_andMatrixOutputs_lo_hi_hi_52 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_56, decoder_decoded_andMatrixOutputs_andMatrixInput_9_52) node decoder_decoded_andMatrixOutputs_lo_hi_60 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_52, decoder_decoded_andMatrixOutputs_lo_hi_lo_40) node decoder_decoded_andMatrixOutputs_lo_61 = cat(decoder_decoded_andMatrixOutputs_lo_hi_60, decoder_decoded_andMatrixOutputs_lo_lo_58) node decoder_decoded_andMatrixOutputs_hi_lo_lo_34 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_60, decoder_decoded_andMatrixOutputs_andMatrixInput_7_58) node decoder_decoded_andMatrixOutputs_hi_lo_hi_50 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_61, decoder_decoded_andMatrixOutputs_andMatrixInput_5_60) node decoder_decoded_andMatrixOutputs_hi_lo_60 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_50, decoder_decoded_andMatrixOutputs_hi_lo_lo_34) node decoder_decoded_andMatrixOutputs_hi_hi_lo_42 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_61, decoder_decoded_andMatrixOutputs_andMatrixInput_3_61) node decoder_decoded_andMatrixOutputs_hi_hi_hi_56 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_61, decoder_decoded_andMatrixOutputs_andMatrixInput_1_61) node decoder_decoded_andMatrixOutputs_hi_hi_61 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_56, decoder_decoded_andMatrixOutputs_hi_hi_lo_42) node decoder_decoded_andMatrixOutputs_hi_61 = cat(decoder_decoded_andMatrixOutputs_hi_hi_61, decoder_decoded_andMatrixOutputs_hi_lo_60) node _decoder_decoded_andMatrixOutputs_T_61 = cat(decoder_decoded_andMatrixOutputs_hi_61, decoder_decoded_andMatrixOutputs_lo_61) node decoder_decoded_andMatrixOutputs_4_2 = andr(_decoder_decoded_andMatrixOutputs_T_61) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_62 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_62 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_62 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_62 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_62 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_61 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_61 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_59 = bits(decoder_decoded_invInputs, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_57 = bits(decoder_decoded_invInputs, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_53 = bits(decoder_decoded_invInputs, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_51 = bits(decoder_decoded_plaInput, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_49 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_43 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_41 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_35 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_19 = bits(decoder_decoded_plaInput, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_19 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_35, decoder_decoded_andMatrixOutputs_andMatrixInput_15_19) node decoder_decoded_andMatrixOutputs_lo_lo_hi_49 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_43, decoder_decoded_andMatrixOutputs_andMatrixInput_13_41) node decoder_decoded_andMatrixOutputs_lo_lo_59 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_49, decoder_decoded_andMatrixOutputs_lo_lo_lo_19) node decoder_decoded_andMatrixOutputs_lo_hi_lo_41 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_51, decoder_decoded_andMatrixOutputs_andMatrixInput_11_49) node decoder_decoded_andMatrixOutputs_lo_hi_hi_53 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_57, decoder_decoded_andMatrixOutputs_andMatrixInput_9_53) node decoder_decoded_andMatrixOutputs_lo_hi_61 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_53, decoder_decoded_andMatrixOutputs_lo_hi_lo_41) node decoder_decoded_andMatrixOutputs_lo_62 = cat(decoder_decoded_andMatrixOutputs_lo_hi_61, decoder_decoded_andMatrixOutputs_lo_lo_59) node decoder_decoded_andMatrixOutputs_hi_lo_lo_35 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_61, decoder_decoded_andMatrixOutputs_andMatrixInput_7_59) node decoder_decoded_andMatrixOutputs_hi_lo_hi_51 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_62, decoder_decoded_andMatrixOutputs_andMatrixInput_5_61) node decoder_decoded_andMatrixOutputs_hi_lo_61 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_51, decoder_decoded_andMatrixOutputs_hi_lo_lo_35) node decoder_decoded_andMatrixOutputs_hi_hi_lo_43 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_62, decoder_decoded_andMatrixOutputs_andMatrixInput_3_62) node decoder_decoded_andMatrixOutputs_hi_hi_hi_57 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_62, decoder_decoded_andMatrixOutputs_andMatrixInput_1_62) node decoder_decoded_andMatrixOutputs_hi_hi_62 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_57, decoder_decoded_andMatrixOutputs_hi_hi_lo_43) node decoder_decoded_andMatrixOutputs_hi_62 = cat(decoder_decoded_andMatrixOutputs_hi_hi_62, decoder_decoded_andMatrixOutputs_hi_lo_61) node _decoder_decoded_andMatrixOutputs_T_62 = cat(decoder_decoded_andMatrixOutputs_hi_62, decoder_decoded_andMatrixOutputs_lo_62) node decoder_decoded_andMatrixOutputs_48_2 = andr(_decoder_decoded_andMatrixOutputs_T_62) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_63 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_63 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_63 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_63 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_63 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_62 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_62 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_60 = bits(decoder_decoded_invInputs, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_58 = bits(decoder_decoded_invInputs, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_54 = bits(decoder_decoded_invInputs, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_52 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_50 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_44 = bits(decoder_decoded_plaInput, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_42 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_36 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_20 = bits(decoder_decoded_plaInput, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_20 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_36, decoder_decoded_andMatrixOutputs_andMatrixInput_15_20) node decoder_decoded_andMatrixOutputs_lo_lo_hi_50 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_44, decoder_decoded_andMatrixOutputs_andMatrixInput_13_42) node decoder_decoded_andMatrixOutputs_lo_lo_60 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_50, decoder_decoded_andMatrixOutputs_lo_lo_lo_20) node decoder_decoded_andMatrixOutputs_lo_hi_lo_42 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_52, decoder_decoded_andMatrixOutputs_andMatrixInput_11_50) node decoder_decoded_andMatrixOutputs_lo_hi_hi_54 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_58, decoder_decoded_andMatrixOutputs_andMatrixInput_9_54) node decoder_decoded_andMatrixOutputs_lo_hi_62 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_54, decoder_decoded_andMatrixOutputs_lo_hi_lo_42) node decoder_decoded_andMatrixOutputs_lo_63 = cat(decoder_decoded_andMatrixOutputs_lo_hi_62, decoder_decoded_andMatrixOutputs_lo_lo_60) node decoder_decoded_andMatrixOutputs_hi_lo_lo_36 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_62, decoder_decoded_andMatrixOutputs_andMatrixInput_7_60) node decoder_decoded_andMatrixOutputs_hi_lo_hi_52 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_63, decoder_decoded_andMatrixOutputs_andMatrixInput_5_62) node decoder_decoded_andMatrixOutputs_hi_lo_62 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_52, decoder_decoded_andMatrixOutputs_hi_lo_lo_36) node decoder_decoded_andMatrixOutputs_hi_hi_lo_44 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_63, decoder_decoded_andMatrixOutputs_andMatrixInput_3_63) node decoder_decoded_andMatrixOutputs_hi_hi_hi_58 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_63, decoder_decoded_andMatrixOutputs_andMatrixInput_1_63) node decoder_decoded_andMatrixOutputs_hi_hi_63 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_58, decoder_decoded_andMatrixOutputs_hi_hi_lo_44) node decoder_decoded_andMatrixOutputs_hi_63 = cat(decoder_decoded_andMatrixOutputs_hi_hi_63, decoder_decoded_andMatrixOutputs_hi_lo_62) node _decoder_decoded_andMatrixOutputs_T_63 = cat(decoder_decoded_andMatrixOutputs_hi_63, decoder_decoded_andMatrixOutputs_lo_63) node decoder_decoded_andMatrixOutputs_46_2 = andr(_decoder_decoded_andMatrixOutputs_T_63) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_64 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_64 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_64 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_64 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_64 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_63 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_63 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_61 = bits(decoder_decoded_invInputs, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_59 = bits(decoder_decoded_invInputs, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_55 = bits(decoder_decoded_invInputs, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_53 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_51 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_45 = bits(decoder_decoded_plaInput, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_43 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_37 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_21 = bits(decoder_decoded_plaInput, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_21 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_37, decoder_decoded_andMatrixOutputs_andMatrixInput_15_21) node decoder_decoded_andMatrixOutputs_lo_lo_hi_51 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_12_45, decoder_decoded_andMatrixOutputs_andMatrixInput_13_43) node decoder_decoded_andMatrixOutputs_lo_lo_61 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_51, decoder_decoded_andMatrixOutputs_lo_lo_lo_21) node decoder_decoded_andMatrixOutputs_lo_hi_lo_43 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_53, decoder_decoded_andMatrixOutputs_andMatrixInput_11_51) node decoder_decoded_andMatrixOutputs_lo_hi_hi_55 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_59, decoder_decoded_andMatrixOutputs_andMatrixInput_9_55) node decoder_decoded_andMatrixOutputs_lo_hi_63 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_55, decoder_decoded_andMatrixOutputs_lo_hi_lo_43) node decoder_decoded_andMatrixOutputs_lo_64 = cat(decoder_decoded_andMatrixOutputs_lo_hi_63, decoder_decoded_andMatrixOutputs_lo_lo_61) node decoder_decoded_andMatrixOutputs_hi_lo_lo_37 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_63, decoder_decoded_andMatrixOutputs_andMatrixInput_7_61) node decoder_decoded_andMatrixOutputs_hi_lo_hi_53 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_64, decoder_decoded_andMatrixOutputs_andMatrixInput_5_63) node decoder_decoded_andMatrixOutputs_hi_lo_63 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_53, decoder_decoded_andMatrixOutputs_hi_lo_lo_37) node decoder_decoded_andMatrixOutputs_hi_hi_lo_45 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_64, decoder_decoded_andMatrixOutputs_andMatrixInput_3_64) node decoder_decoded_andMatrixOutputs_hi_hi_hi_59 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_64, decoder_decoded_andMatrixOutputs_andMatrixInput_1_64) node decoder_decoded_andMatrixOutputs_hi_hi_64 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_59, decoder_decoded_andMatrixOutputs_hi_hi_lo_45) node decoder_decoded_andMatrixOutputs_hi_64 = cat(decoder_decoded_andMatrixOutputs_hi_hi_64, decoder_decoded_andMatrixOutputs_hi_lo_63) node _decoder_decoded_andMatrixOutputs_T_64 = cat(decoder_decoded_andMatrixOutputs_hi_64, decoder_decoded_andMatrixOutputs_lo_64) node decoder_decoded_andMatrixOutputs_63_2 = andr(_decoder_decoded_andMatrixOutputs_T_64) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_65 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_65 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_65 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_65 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_65 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_64 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_64 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_62 = bits(decoder_decoded_invInputs, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_60 = bits(decoder_decoded_invInputs, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_56 = bits(decoder_decoded_invInputs, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_54 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_52 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_46 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_44 = bits(decoder_decoded_plaInput, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_38 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_22 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_16 = bits(decoder_decoded_plaInput, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_22 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_15_22, decoder_decoded_andMatrixOutputs_andMatrixInput_16_16) node decoder_decoded_andMatrixOutputs_lo_lo_hi_52 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_13_44, decoder_decoded_andMatrixOutputs_andMatrixInput_14_38) node decoder_decoded_andMatrixOutputs_lo_lo_62 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_52, decoder_decoded_andMatrixOutputs_lo_lo_lo_22) node decoder_decoded_andMatrixOutputs_lo_hi_lo_44 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_52, decoder_decoded_andMatrixOutputs_andMatrixInput_12_46) node decoder_decoded_andMatrixOutputs_lo_hi_hi_56 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_56, decoder_decoded_andMatrixOutputs_andMatrixInput_10_54) node decoder_decoded_andMatrixOutputs_lo_hi_64 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_56, decoder_decoded_andMatrixOutputs_lo_hi_lo_44) node decoder_decoded_andMatrixOutputs_lo_65 = cat(decoder_decoded_andMatrixOutputs_lo_hi_64, decoder_decoded_andMatrixOutputs_lo_lo_62) node decoder_decoded_andMatrixOutputs_hi_lo_lo_38 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_62, decoder_decoded_andMatrixOutputs_andMatrixInput_8_60) node decoder_decoded_andMatrixOutputs_hi_lo_hi_54 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_64, decoder_decoded_andMatrixOutputs_andMatrixInput_6_64) node decoder_decoded_andMatrixOutputs_hi_lo_64 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_54, decoder_decoded_andMatrixOutputs_hi_lo_lo_38) node decoder_decoded_andMatrixOutputs_hi_hi_lo_46 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_65, decoder_decoded_andMatrixOutputs_andMatrixInput_4_65) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_16 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_65, decoder_decoded_andMatrixOutputs_andMatrixInput_1_65) node decoder_decoded_andMatrixOutputs_hi_hi_hi_60 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_16, decoder_decoded_andMatrixOutputs_andMatrixInput_2_65) node decoder_decoded_andMatrixOutputs_hi_hi_65 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_60, decoder_decoded_andMatrixOutputs_hi_hi_lo_46) node decoder_decoded_andMatrixOutputs_hi_65 = cat(decoder_decoded_andMatrixOutputs_hi_hi_65, decoder_decoded_andMatrixOutputs_hi_lo_64) node _decoder_decoded_andMatrixOutputs_T_65 = cat(decoder_decoded_andMatrixOutputs_hi_65, decoder_decoded_andMatrixOutputs_lo_65) node decoder_decoded_andMatrixOutputs_12_2 = andr(_decoder_decoded_andMatrixOutputs_T_65) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_66 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_66 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_66 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_66 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_66 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_65 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_65 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_63 = bits(decoder_decoded_invInputs, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_61 = bits(decoder_decoded_invInputs, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_57 = bits(decoder_decoded_invInputs, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_55 = bits(decoder_decoded_plaInput, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_53 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_47 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_45 = bits(decoder_decoded_plaInput, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_39 = bits(decoder_decoded_invInputs, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_23 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_17 = bits(decoder_decoded_plaInput, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_23 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_15_23, decoder_decoded_andMatrixOutputs_andMatrixInput_16_17) node decoder_decoded_andMatrixOutputs_lo_lo_hi_53 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_13_45, decoder_decoded_andMatrixOutputs_andMatrixInput_14_39) node decoder_decoded_andMatrixOutputs_lo_lo_63 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_53, decoder_decoded_andMatrixOutputs_lo_lo_lo_23) node decoder_decoded_andMatrixOutputs_lo_hi_lo_45 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_53, decoder_decoded_andMatrixOutputs_andMatrixInput_12_47) node decoder_decoded_andMatrixOutputs_lo_hi_hi_57 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_57, decoder_decoded_andMatrixOutputs_andMatrixInput_10_55) node decoder_decoded_andMatrixOutputs_lo_hi_65 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_57, decoder_decoded_andMatrixOutputs_lo_hi_lo_45) node decoder_decoded_andMatrixOutputs_lo_66 = cat(decoder_decoded_andMatrixOutputs_lo_hi_65, decoder_decoded_andMatrixOutputs_lo_lo_63) node decoder_decoded_andMatrixOutputs_hi_lo_lo_39 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_7_63, decoder_decoded_andMatrixOutputs_andMatrixInput_8_61) node decoder_decoded_andMatrixOutputs_hi_lo_hi_55 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_65, decoder_decoded_andMatrixOutputs_andMatrixInput_6_65) node decoder_decoded_andMatrixOutputs_hi_lo_65 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_55, decoder_decoded_andMatrixOutputs_hi_lo_lo_39) node decoder_decoded_andMatrixOutputs_hi_hi_lo_47 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_66, decoder_decoded_andMatrixOutputs_andMatrixInput_4_66) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_17 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_66, decoder_decoded_andMatrixOutputs_andMatrixInput_1_66) node decoder_decoded_andMatrixOutputs_hi_hi_hi_61 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_17, decoder_decoded_andMatrixOutputs_andMatrixInput_2_66) node decoder_decoded_andMatrixOutputs_hi_hi_66 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_61, decoder_decoded_andMatrixOutputs_hi_hi_lo_47) node decoder_decoded_andMatrixOutputs_hi_66 = cat(decoder_decoded_andMatrixOutputs_hi_hi_66, decoder_decoded_andMatrixOutputs_hi_lo_65) node _decoder_decoded_andMatrixOutputs_T_66 = cat(decoder_decoded_andMatrixOutputs_hi_66, decoder_decoded_andMatrixOutputs_lo_66) node decoder_decoded_andMatrixOutputs_56_2 = andr(_decoder_decoded_andMatrixOutputs_T_66) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_67 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_67 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_67 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_67 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_67 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_66 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_66 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_64 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_62 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_58 = bits(decoder_decoded_invInputs, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_56 = bits(decoder_decoded_invInputs, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_54 = bits(decoder_decoded_invInputs, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_48 = bits(decoder_decoded_invInputs, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_46 = bits(decoder_decoded_invInputs, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_40 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_24 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_18 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_17_12 = bits(decoder_decoded_plaInput, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_18_6 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_19 = bits(decoder_decoded_plaInput, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_24 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_18_6, decoder_decoded_andMatrixOutputs_andMatrixInput_19) node decoder_decoded_andMatrixOutputs_lo_lo_hi_hi = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_15_24, decoder_decoded_andMatrixOutputs_andMatrixInput_16_18) node decoder_decoded_andMatrixOutputs_lo_lo_hi_54 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_hi, decoder_decoded_andMatrixOutputs_andMatrixInput_17_12) node decoder_decoded_andMatrixOutputs_lo_lo_64 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_54, decoder_decoded_andMatrixOutputs_lo_lo_lo_24) node decoder_decoded_andMatrixOutputs_lo_hi_lo_46 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_13_46, decoder_decoded_andMatrixOutputs_andMatrixInput_14_40) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_12 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_56, decoder_decoded_andMatrixOutputs_andMatrixInput_11_54) node decoder_decoded_andMatrixOutputs_lo_hi_hi_58 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_12, decoder_decoded_andMatrixOutputs_andMatrixInput_12_48) node decoder_decoded_andMatrixOutputs_lo_hi_66 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_58, decoder_decoded_andMatrixOutputs_lo_hi_lo_46) node decoder_decoded_andMatrixOutputs_lo_67 = cat(decoder_decoded_andMatrixOutputs_lo_hi_66, decoder_decoded_andMatrixOutputs_lo_lo_64) node decoder_decoded_andMatrixOutputs_hi_lo_lo_40 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_62, decoder_decoded_andMatrixOutputs_andMatrixInput_9_58) node decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_6 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_66, decoder_decoded_andMatrixOutputs_andMatrixInput_6_66) node decoder_decoded_andMatrixOutputs_hi_lo_hi_56 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_6, decoder_decoded_andMatrixOutputs_andMatrixInput_7_64) node decoder_decoded_andMatrixOutputs_hi_lo_66 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_56, decoder_decoded_andMatrixOutputs_hi_lo_lo_40) node decoder_decoded_andMatrixOutputs_hi_hi_lo_48 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_67, decoder_decoded_andMatrixOutputs_andMatrixInput_4_67) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_18 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_67, decoder_decoded_andMatrixOutputs_andMatrixInput_1_67) node decoder_decoded_andMatrixOutputs_hi_hi_hi_62 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_18, decoder_decoded_andMatrixOutputs_andMatrixInput_2_67) node decoder_decoded_andMatrixOutputs_hi_hi_67 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_62, decoder_decoded_andMatrixOutputs_hi_hi_lo_48) node decoder_decoded_andMatrixOutputs_hi_67 = cat(decoder_decoded_andMatrixOutputs_hi_hi_67, decoder_decoded_andMatrixOutputs_hi_lo_66) node _decoder_decoded_andMatrixOutputs_T_67 = cat(decoder_decoded_andMatrixOutputs_hi_67, decoder_decoded_andMatrixOutputs_lo_67) node decoder_decoded_andMatrixOutputs_35_2 = andr(_decoder_decoded_andMatrixOutputs_T_67) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_68 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_68 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_68 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_68 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_68 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_67 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_67 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_65 = bits(decoder_decoded_invInputs, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_63 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_59 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_57 = bits(decoder_decoded_invInputs, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_55 = bits(decoder_decoded_invInputs, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_49 = bits(decoder_decoded_invInputs, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_47 = bits(decoder_decoded_invInputs, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_41 = bits(decoder_decoded_invInputs, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_25 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_19 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_17_13 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_18_7 = bits(decoder_decoded_plaInput, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_19_1 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_20 = bits(decoder_decoded_plaInput, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_25 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_19_1, decoder_decoded_andMatrixOutputs_andMatrixInput_20) node decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_1 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_16_19, decoder_decoded_andMatrixOutputs_andMatrixInput_17_13) node decoder_decoded_andMatrixOutputs_lo_lo_hi_55 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_1, decoder_decoded_andMatrixOutputs_andMatrixInput_18_7) node decoder_decoded_andMatrixOutputs_lo_lo_65 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_55, decoder_decoded_andMatrixOutputs_lo_lo_lo_25) node decoder_decoded_andMatrixOutputs_lo_hi_lo_47 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_41, decoder_decoded_andMatrixOutputs_andMatrixInput_15_25) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_13 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_55, decoder_decoded_andMatrixOutputs_andMatrixInput_12_49) node decoder_decoded_andMatrixOutputs_lo_hi_hi_59 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_13, decoder_decoded_andMatrixOutputs_andMatrixInput_13_47) node decoder_decoded_andMatrixOutputs_lo_hi_67 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_59, decoder_decoded_andMatrixOutputs_lo_hi_lo_47) node decoder_decoded_andMatrixOutputs_lo_68 = cat(decoder_decoded_andMatrixOutputs_lo_hi_67, decoder_decoded_andMatrixOutputs_lo_lo_65) node decoder_decoded_andMatrixOutputs_hi_lo_lo_41 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_59, decoder_decoded_andMatrixOutputs_andMatrixInput_10_57) node decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_7 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_67, decoder_decoded_andMatrixOutputs_andMatrixInput_7_65) node decoder_decoded_andMatrixOutputs_hi_lo_hi_57 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_7, decoder_decoded_andMatrixOutputs_andMatrixInput_8_63) node decoder_decoded_andMatrixOutputs_hi_lo_67 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_57, decoder_decoded_andMatrixOutputs_hi_lo_lo_41) node decoder_decoded_andMatrixOutputs_hi_hi_lo_hi = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_68, decoder_decoded_andMatrixOutputs_andMatrixInput_4_68) node decoder_decoded_andMatrixOutputs_hi_hi_lo_49 = cat(decoder_decoded_andMatrixOutputs_hi_hi_lo_hi, decoder_decoded_andMatrixOutputs_andMatrixInput_5_67) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_19 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_68, decoder_decoded_andMatrixOutputs_andMatrixInput_1_68) node decoder_decoded_andMatrixOutputs_hi_hi_hi_63 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_19, decoder_decoded_andMatrixOutputs_andMatrixInput_2_68) node decoder_decoded_andMatrixOutputs_hi_hi_68 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_63, decoder_decoded_andMatrixOutputs_hi_hi_lo_49) node decoder_decoded_andMatrixOutputs_hi_68 = cat(decoder_decoded_andMatrixOutputs_hi_hi_68, decoder_decoded_andMatrixOutputs_hi_lo_67) node _decoder_decoded_andMatrixOutputs_T_68 = cat(decoder_decoded_andMatrixOutputs_hi_68, decoder_decoded_andMatrixOutputs_lo_68) node decoder_decoded_andMatrixOutputs_34_2 = andr(_decoder_decoded_andMatrixOutputs_T_68) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_69 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_69 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_69 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_69 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_69 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_68 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_68 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_66 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_64 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_60 = bits(decoder_decoded_invInputs, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_58 = bits(decoder_decoded_invInputs, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_56 = bits(decoder_decoded_invInputs, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_50 = bits(decoder_decoded_invInputs, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_48 = bits(decoder_decoded_invInputs, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_42 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_26 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_20 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_17_14 = bits(decoder_decoded_plaInput, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_18_8 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_19_2 = bits(decoder_decoded_plaInput, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_26 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_18_8, decoder_decoded_andMatrixOutputs_andMatrixInput_19_2) node decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_2 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_15_26, decoder_decoded_andMatrixOutputs_andMatrixInput_16_20) node decoder_decoded_andMatrixOutputs_lo_lo_hi_56 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_2, decoder_decoded_andMatrixOutputs_andMatrixInput_17_14) node decoder_decoded_andMatrixOutputs_lo_lo_66 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_56, decoder_decoded_andMatrixOutputs_lo_lo_lo_26) node decoder_decoded_andMatrixOutputs_lo_hi_lo_48 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_13_48, decoder_decoded_andMatrixOutputs_andMatrixInput_14_42) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_14 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_10_58, decoder_decoded_andMatrixOutputs_andMatrixInput_11_56) node decoder_decoded_andMatrixOutputs_lo_hi_hi_60 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_14, decoder_decoded_andMatrixOutputs_andMatrixInput_12_50) node decoder_decoded_andMatrixOutputs_lo_hi_68 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_60, decoder_decoded_andMatrixOutputs_lo_hi_lo_48) node decoder_decoded_andMatrixOutputs_lo_69 = cat(decoder_decoded_andMatrixOutputs_lo_hi_68, decoder_decoded_andMatrixOutputs_lo_lo_66) node decoder_decoded_andMatrixOutputs_hi_lo_lo_42 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_8_64, decoder_decoded_andMatrixOutputs_andMatrixInput_9_60) node decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_8 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_5_68, decoder_decoded_andMatrixOutputs_andMatrixInput_6_68) node decoder_decoded_andMatrixOutputs_hi_lo_hi_58 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_8, decoder_decoded_andMatrixOutputs_andMatrixInput_7_66) node decoder_decoded_andMatrixOutputs_hi_lo_68 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_58, decoder_decoded_andMatrixOutputs_hi_lo_lo_42) node decoder_decoded_andMatrixOutputs_hi_hi_lo_50 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_69, decoder_decoded_andMatrixOutputs_andMatrixInput_4_69) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_20 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_69, decoder_decoded_andMatrixOutputs_andMatrixInput_1_69) node decoder_decoded_andMatrixOutputs_hi_hi_hi_64 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_20, decoder_decoded_andMatrixOutputs_andMatrixInput_2_69) node decoder_decoded_andMatrixOutputs_hi_hi_69 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_64, decoder_decoded_andMatrixOutputs_hi_hi_lo_50) node decoder_decoded_andMatrixOutputs_hi_69 = cat(decoder_decoded_andMatrixOutputs_hi_hi_69, decoder_decoded_andMatrixOutputs_hi_lo_68) node _decoder_decoded_andMatrixOutputs_T_69 = cat(decoder_decoded_andMatrixOutputs_hi_69, decoder_decoded_andMatrixOutputs_lo_69) node decoder_decoded_andMatrixOutputs_20_2 = andr(_decoder_decoded_andMatrixOutputs_T_69) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_70 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_70 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_70 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_70 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_70 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_69 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_69 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_67 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_65 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_61 = bits(decoder_decoded_invInputs, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_59 = bits(decoder_decoded_invInputs, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_57 = bits(decoder_decoded_invInputs, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_51 = bits(decoder_decoded_invInputs, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_49 = bits(decoder_decoded_invInputs, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_43 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_27 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_21 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_17_15 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_18_9 = bits(decoder_decoded_plaInput, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_19_3 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_20_1 = bits(decoder_decoded_plaInput, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_27 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_19_3, decoder_decoded_andMatrixOutputs_andMatrixInput_20_1) node decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_3 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_16_21, decoder_decoded_andMatrixOutputs_andMatrixInput_17_15) node decoder_decoded_andMatrixOutputs_lo_lo_hi_57 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_3, decoder_decoded_andMatrixOutputs_andMatrixInput_18_9) node decoder_decoded_andMatrixOutputs_lo_lo_67 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_57, decoder_decoded_andMatrixOutputs_lo_lo_lo_27) node decoder_decoded_andMatrixOutputs_lo_hi_lo_49 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_43, decoder_decoded_andMatrixOutputs_andMatrixInput_15_27) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_15 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_57, decoder_decoded_andMatrixOutputs_andMatrixInput_12_51) node decoder_decoded_andMatrixOutputs_lo_hi_hi_61 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_15, decoder_decoded_andMatrixOutputs_andMatrixInput_13_49) node decoder_decoded_andMatrixOutputs_lo_hi_69 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_61, decoder_decoded_andMatrixOutputs_lo_hi_lo_49) node decoder_decoded_andMatrixOutputs_lo_70 = cat(decoder_decoded_andMatrixOutputs_lo_hi_69, decoder_decoded_andMatrixOutputs_lo_lo_67) node decoder_decoded_andMatrixOutputs_hi_lo_lo_43 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_61, decoder_decoded_andMatrixOutputs_andMatrixInput_10_59) node decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_9 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_69, decoder_decoded_andMatrixOutputs_andMatrixInput_7_67) node decoder_decoded_andMatrixOutputs_hi_lo_hi_59 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_9, decoder_decoded_andMatrixOutputs_andMatrixInput_8_65) node decoder_decoded_andMatrixOutputs_hi_lo_69 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_59, decoder_decoded_andMatrixOutputs_hi_lo_lo_43) node decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_1 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_70, decoder_decoded_andMatrixOutputs_andMatrixInput_4_70) node decoder_decoded_andMatrixOutputs_hi_hi_lo_51 = cat(decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_1, decoder_decoded_andMatrixOutputs_andMatrixInput_5_69) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_21 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_70, decoder_decoded_andMatrixOutputs_andMatrixInput_1_70) node decoder_decoded_andMatrixOutputs_hi_hi_hi_65 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_21, decoder_decoded_andMatrixOutputs_andMatrixInput_2_70) node decoder_decoded_andMatrixOutputs_hi_hi_70 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_65, decoder_decoded_andMatrixOutputs_hi_hi_lo_51) node decoder_decoded_andMatrixOutputs_hi_70 = cat(decoder_decoded_andMatrixOutputs_hi_hi_70, decoder_decoded_andMatrixOutputs_hi_lo_69) node _decoder_decoded_andMatrixOutputs_T_70 = cat(decoder_decoded_andMatrixOutputs_hi_70, decoder_decoded_andMatrixOutputs_lo_70) node decoder_decoded_andMatrixOutputs_7_2 = andr(_decoder_decoded_andMatrixOutputs_T_70) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_71 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_71 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_71 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_71 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_71 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_70 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_70 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_68 = bits(decoder_decoded_plaInput, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_66 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_62 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_60 = bits(decoder_decoded_invInputs, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_58 = bits(decoder_decoded_invInputs, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_52 = bits(decoder_decoded_invInputs, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_50 = bits(decoder_decoded_invInputs, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_44 = bits(decoder_decoded_invInputs, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_28 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_22 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_17_16 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_18_10 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_19_4 = bits(decoder_decoded_plaInput, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_20_2 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_21 = bits(decoder_decoded_plaInput, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_28 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_20_2, decoder_decoded_andMatrixOutputs_andMatrixInput_21) node decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_4 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_17_16, decoder_decoded_andMatrixOutputs_andMatrixInput_18_10) node decoder_decoded_andMatrixOutputs_lo_lo_hi_58 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_4, decoder_decoded_andMatrixOutputs_andMatrixInput_19_4) node decoder_decoded_andMatrixOutputs_lo_lo_68 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_58, decoder_decoded_andMatrixOutputs_lo_lo_lo_28) node decoder_decoded_andMatrixOutputs_lo_hi_lo_hi = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_44, decoder_decoded_andMatrixOutputs_andMatrixInput_15_28) node decoder_decoded_andMatrixOutputs_lo_hi_lo_50 = cat(decoder_decoded_andMatrixOutputs_lo_hi_lo_hi, decoder_decoded_andMatrixOutputs_andMatrixInput_16_22) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_16 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_58, decoder_decoded_andMatrixOutputs_andMatrixInput_12_52) node decoder_decoded_andMatrixOutputs_lo_hi_hi_62 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_16, decoder_decoded_andMatrixOutputs_andMatrixInput_13_50) node decoder_decoded_andMatrixOutputs_lo_hi_70 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_62, decoder_decoded_andMatrixOutputs_lo_hi_lo_50) node decoder_decoded_andMatrixOutputs_lo_71 = cat(decoder_decoded_andMatrixOutputs_lo_hi_70, decoder_decoded_andMatrixOutputs_lo_lo_68) node decoder_decoded_andMatrixOutputs_hi_lo_lo_44 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_62, decoder_decoded_andMatrixOutputs_andMatrixInput_10_60) node decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_10 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_70, decoder_decoded_andMatrixOutputs_andMatrixInput_7_68) node decoder_decoded_andMatrixOutputs_hi_lo_hi_60 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_10, decoder_decoded_andMatrixOutputs_andMatrixInput_8_66) node decoder_decoded_andMatrixOutputs_hi_lo_70 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_60, decoder_decoded_andMatrixOutputs_hi_lo_lo_44) node decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_2 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_71, decoder_decoded_andMatrixOutputs_andMatrixInput_4_71) node decoder_decoded_andMatrixOutputs_hi_hi_lo_52 = cat(decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_2, decoder_decoded_andMatrixOutputs_andMatrixInput_5_70) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_22 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_71, decoder_decoded_andMatrixOutputs_andMatrixInput_1_71) node decoder_decoded_andMatrixOutputs_hi_hi_hi_66 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_22, decoder_decoded_andMatrixOutputs_andMatrixInput_2_71) node decoder_decoded_andMatrixOutputs_hi_hi_71 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_66, decoder_decoded_andMatrixOutputs_hi_hi_lo_52) node decoder_decoded_andMatrixOutputs_hi_71 = cat(decoder_decoded_andMatrixOutputs_hi_hi_71, decoder_decoded_andMatrixOutputs_hi_lo_70) node _decoder_decoded_andMatrixOutputs_T_71 = cat(decoder_decoded_andMatrixOutputs_hi_71, decoder_decoded_andMatrixOutputs_lo_71) node decoder_decoded_andMatrixOutputs_17_2 = andr(_decoder_decoded_andMatrixOutputs_T_71) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_72 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_72 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_72 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_72 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_72 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_71 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_71 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_69 = bits(decoder_decoded_invInputs, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_67 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_63 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_61 = bits(decoder_decoded_invInputs, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_59 = bits(decoder_decoded_invInputs, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_53 = bits(decoder_decoded_invInputs, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_51 = bits(decoder_decoded_invInputs, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_45 = bits(decoder_decoded_invInputs, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_29 = bits(decoder_decoded_plaInput, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_23 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_17_17 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_18_11 = bits(decoder_decoded_plaInput, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_19_5 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_20_3 = bits(decoder_decoded_plaInput, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_29 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_19_5, decoder_decoded_andMatrixOutputs_andMatrixInput_20_3) node decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_5 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_16_23, decoder_decoded_andMatrixOutputs_andMatrixInput_17_17) node decoder_decoded_andMatrixOutputs_lo_lo_hi_59 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_5, decoder_decoded_andMatrixOutputs_andMatrixInput_18_11) node decoder_decoded_andMatrixOutputs_lo_lo_69 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_59, decoder_decoded_andMatrixOutputs_lo_lo_lo_29) node decoder_decoded_andMatrixOutputs_lo_hi_lo_51 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_45, decoder_decoded_andMatrixOutputs_andMatrixInput_15_29) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_17 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_59, decoder_decoded_andMatrixOutputs_andMatrixInput_12_53) node decoder_decoded_andMatrixOutputs_lo_hi_hi_63 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_17, decoder_decoded_andMatrixOutputs_andMatrixInput_13_51) node decoder_decoded_andMatrixOutputs_lo_hi_71 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_63, decoder_decoded_andMatrixOutputs_lo_hi_lo_51) node decoder_decoded_andMatrixOutputs_lo_72 = cat(decoder_decoded_andMatrixOutputs_lo_hi_71, decoder_decoded_andMatrixOutputs_lo_lo_69) node decoder_decoded_andMatrixOutputs_hi_lo_lo_45 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_63, decoder_decoded_andMatrixOutputs_andMatrixInput_10_61) node decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_11 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_71, decoder_decoded_andMatrixOutputs_andMatrixInput_7_69) node decoder_decoded_andMatrixOutputs_hi_lo_hi_61 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_11, decoder_decoded_andMatrixOutputs_andMatrixInput_8_67) node decoder_decoded_andMatrixOutputs_hi_lo_71 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_61, decoder_decoded_andMatrixOutputs_hi_lo_lo_45) node decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_3 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_72, decoder_decoded_andMatrixOutputs_andMatrixInput_4_72) node decoder_decoded_andMatrixOutputs_hi_hi_lo_53 = cat(decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_3, decoder_decoded_andMatrixOutputs_andMatrixInput_5_71) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_23 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_72, decoder_decoded_andMatrixOutputs_andMatrixInput_1_72) node decoder_decoded_andMatrixOutputs_hi_hi_hi_67 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_23, decoder_decoded_andMatrixOutputs_andMatrixInput_2_72) node decoder_decoded_andMatrixOutputs_hi_hi_72 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_67, decoder_decoded_andMatrixOutputs_hi_hi_lo_53) node decoder_decoded_andMatrixOutputs_hi_72 = cat(decoder_decoded_andMatrixOutputs_hi_hi_72, decoder_decoded_andMatrixOutputs_hi_lo_71) node _decoder_decoded_andMatrixOutputs_T_72 = cat(decoder_decoded_andMatrixOutputs_hi_72, decoder_decoded_andMatrixOutputs_lo_72) node decoder_decoded_andMatrixOutputs_36_2 = andr(_decoder_decoded_andMatrixOutputs_T_72) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_73 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_73 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_73 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_73 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_73 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_72 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_72 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_70 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_68 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_64 = bits(decoder_decoded_invInputs, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_62 = bits(decoder_decoded_invInputs, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_60 = bits(decoder_decoded_invInputs, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_54 = bits(decoder_decoded_invInputs, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_52 = bits(decoder_decoded_invInputs, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_46 = bits(decoder_decoded_plaInput, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_30 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_24 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_17_18 = bits(decoder_decoded_invInputs, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_18_12 = bits(decoder_decoded_plaInput, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_19_6 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_20_4 = bits(decoder_decoded_plaInput, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_30 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_19_6, decoder_decoded_andMatrixOutputs_andMatrixInput_20_4) node decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_6 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_16_24, decoder_decoded_andMatrixOutputs_andMatrixInput_17_18) node decoder_decoded_andMatrixOutputs_lo_lo_hi_60 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_6, decoder_decoded_andMatrixOutputs_andMatrixInput_18_12) node decoder_decoded_andMatrixOutputs_lo_lo_70 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_60, decoder_decoded_andMatrixOutputs_lo_lo_lo_30) node decoder_decoded_andMatrixOutputs_lo_hi_lo_52 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_46, decoder_decoded_andMatrixOutputs_andMatrixInput_15_30) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_18 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_60, decoder_decoded_andMatrixOutputs_andMatrixInput_12_54) node decoder_decoded_andMatrixOutputs_lo_hi_hi_64 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_18, decoder_decoded_andMatrixOutputs_andMatrixInput_13_52) node decoder_decoded_andMatrixOutputs_lo_hi_72 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_64, decoder_decoded_andMatrixOutputs_lo_hi_lo_52) node decoder_decoded_andMatrixOutputs_lo_73 = cat(decoder_decoded_andMatrixOutputs_lo_hi_72, decoder_decoded_andMatrixOutputs_lo_lo_70) node decoder_decoded_andMatrixOutputs_hi_lo_lo_46 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_64, decoder_decoded_andMatrixOutputs_andMatrixInput_10_62) node decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_12 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_72, decoder_decoded_andMatrixOutputs_andMatrixInput_7_70) node decoder_decoded_andMatrixOutputs_hi_lo_hi_62 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_12, decoder_decoded_andMatrixOutputs_andMatrixInput_8_68) node decoder_decoded_andMatrixOutputs_hi_lo_72 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_62, decoder_decoded_andMatrixOutputs_hi_lo_lo_46) node decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_4 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_73, decoder_decoded_andMatrixOutputs_andMatrixInput_4_73) node decoder_decoded_andMatrixOutputs_hi_hi_lo_54 = cat(decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_4, decoder_decoded_andMatrixOutputs_andMatrixInput_5_72) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_24 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_73, decoder_decoded_andMatrixOutputs_andMatrixInput_1_73) node decoder_decoded_andMatrixOutputs_hi_hi_hi_68 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_24, decoder_decoded_andMatrixOutputs_andMatrixInput_2_73) node decoder_decoded_andMatrixOutputs_hi_hi_73 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_68, decoder_decoded_andMatrixOutputs_hi_hi_lo_54) node decoder_decoded_andMatrixOutputs_hi_73 = cat(decoder_decoded_andMatrixOutputs_hi_hi_73, decoder_decoded_andMatrixOutputs_hi_lo_72) node _decoder_decoded_andMatrixOutputs_T_73 = cat(decoder_decoded_andMatrixOutputs_hi_73, decoder_decoded_andMatrixOutputs_lo_73) node decoder_decoded_andMatrixOutputs_22_2 = andr(_decoder_decoded_andMatrixOutputs_T_73) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_74 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_74 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_74 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_74 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_74 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_73 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_73 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_71 = bits(decoder_decoded_invInputs, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_69 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_65 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_63 = bits(decoder_decoded_invInputs, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_61 = bits(decoder_decoded_invInputs, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_55 = bits(decoder_decoded_invInputs, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_53 = bits(decoder_decoded_invInputs, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_47 = bits(decoder_decoded_invInputs, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_31 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_25 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_17_19 = bits(decoder_decoded_plaInput, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_18_13 = bits(decoder_decoded_plaInput, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_19_7 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_20_5 = bits(decoder_decoded_plaInput, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_31 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_19_7, decoder_decoded_andMatrixOutputs_andMatrixInput_20_5) node decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_7 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_16_25, decoder_decoded_andMatrixOutputs_andMatrixInput_17_19) node decoder_decoded_andMatrixOutputs_lo_lo_hi_61 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_7, decoder_decoded_andMatrixOutputs_andMatrixInput_18_13) node decoder_decoded_andMatrixOutputs_lo_lo_71 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_61, decoder_decoded_andMatrixOutputs_lo_lo_lo_31) node decoder_decoded_andMatrixOutputs_lo_hi_lo_53 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_47, decoder_decoded_andMatrixOutputs_andMatrixInput_15_31) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_19 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_61, decoder_decoded_andMatrixOutputs_andMatrixInput_12_55) node decoder_decoded_andMatrixOutputs_lo_hi_hi_65 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_19, decoder_decoded_andMatrixOutputs_andMatrixInput_13_53) node decoder_decoded_andMatrixOutputs_lo_hi_73 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_65, decoder_decoded_andMatrixOutputs_lo_hi_lo_53) node decoder_decoded_andMatrixOutputs_lo_74 = cat(decoder_decoded_andMatrixOutputs_lo_hi_73, decoder_decoded_andMatrixOutputs_lo_lo_71) node decoder_decoded_andMatrixOutputs_hi_lo_lo_47 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_65, decoder_decoded_andMatrixOutputs_andMatrixInput_10_63) node decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_13 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_73, decoder_decoded_andMatrixOutputs_andMatrixInput_7_71) node decoder_decoded_andMatrixOutputs_hi_lo_hi_63 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_13, decoder_decoded_andMatrixOutputs_andMatrixInput_8_69) node decoder_decoded_andMatrixOutputs_hi_lo_73 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_63, decoder_decoded_andMatrixOutputs_hi_lo_lo_47) node decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_5 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_74, decoder_decoded_andMatrixOutputs_andMatrixInput_4_74) node decoder_decoded_andMatrixOutputs_hi_hi_lo_55 = cat(decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_5, decoder_decoded_andMatrixOutputs_andMatrixInput_5_73) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_25 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_74, decoder_decoded_andMatrixOutputs_andMatrixInput_1_74) node decoder_decoded_andMatrixOutputs_hi_hi_hi_69 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_25, decoder_decoded_andMatrixOutputs_andMatrixInput_2_74) node decoder_decoded_andMatrixOutputs_hi_hi_74 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_69, decoder_decoded_andMatrixOutputs_hi_hi_lo_55) node decoder_decoded_andMatrixOutputs_hi_74 = cat(decoder_decoded_andMatrixOutputs_hi_hi_74, decoder_decoded_andMatrixOutputs_hi_lo_73) node _decoder_decoded_andMatrixOutputs_T_74 = cat(decoder_decoded_andMatrixOutputs_hi_74, decoder_decoded_andMatrixOutputs_lo_74) node decoder_decoded_andMatrixOutputs_14_2 = andr(_decoder_decoded_andMatrixOutputs_T_74) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_75 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_75 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_75 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_75 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_75 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_74 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_74 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_72 = bits(decoder_decoded_invInputs, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_70 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_66 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_64 = bits(decoder_decoded_invInputs, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_62 = bits(decoder_decoded_invInputs, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_56 = bits(decoder_decoded_invInputs, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_54 = bits(decoder_decoded_invInputs, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_48 = bits(decoder_decoded_invInputs, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_32 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_26 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_17_20 = bits(decoder_decoded_plaInput, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_18_14 = bits(decoder_decoded_plaInput, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_19_8 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_20_6 = bits(decoder_decoded_plaInput, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_32 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_19_8, decoder_decoded_andMatrixOutputs_andMatrixInput_20_6) node decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_8 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_16_26, decoder_decoded_andMatrixOutputs_andMatrixInput_17_20) node decoder_decoded_andMatrixOutputs_lo_lo_hi_62 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_8, decoder_decoded_andMatrixOutputs_andMatrixInput_18_14) node decoder_decoded_andMatrixOutputs_lo_lo_72 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_62, decoder_decoded_andMatrixOutputs_lo_lo_lo_32) node decoder_decoded_andMatrixOutputs_lo_hi_lo_54 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_48, decoder_decoded_andMatrixOutputs_andMatrixInput_15_32) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_20 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_62, decoder_decoded_andMatrixOutputs_andMatrixInput_12_56) node decoder_decoded_andMatrixOutputs_lo_hi_hi_66 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_20, decoder_decoded_andMatrixOutputs_andMatrixInput_13_54) node decoder_decoded_andMatrixOutputs_lo_hi_74 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_66, decoder_decoded_andMatrixOutputs_lo_hi_lo_54) node decoder_decoded_andMatrixOutputs_lo_75 = cat(decoder_decoded_andMatrixOutputs_lo_hi_74, decoder_decoded_andMatrixOutputs_lo_lo_72) node decoder_decoded_andMatrixOutputs_hi_lo_lo_48 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_66, decoder_decoded_andMatrixOutputs_andMatrixInput_10_64) node decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_14 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_74, decoder_decoded_andMatrixOutputs_andMatrixInput_7_72) node decoder_decoded_andMatrixOutputs_hi_lo_hi_64 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_14, decoder_decoded_andMatrixOutputs_andMatrixInput_8_70) node decoder_decoded_andMatrixOutputs_hi_lo_74 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_64, decoder_decoded_andMatrixOutputs_hi_lo_lo_48) node decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_6 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_75, decoder_decoded_andMatrixOutputs_andMatrixInput_4_75) node decoder_decoded_andMatrixOutputs_hi_hi_lo_56 = cat(decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_6, decoder_decoded_andMatrixOutputs_andMatrixInput_5_74) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_26 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_75, decoder_decoded_andMatrixOutputs_andMatrixInput_1_75) node decoder_decoded_andMatrixOutputs_hi_hi_hi_70 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_26, decoder_decoded_andMatrixOutputs_andMatrixInput_2_75) node decoder_decoded_andMatrixOutputs_hi_hi_75 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_70, decoder_decoded_andMatrixOutputs_hi_hi_lo_56) node decoder_decoded_andMatrixOutputs_hi_75 = cat(decoder_decoded_andMatrixOutputs_hi_hi_75, decoder_decoded_andMatrixOutputs_hi_lo_74) node _decoder_decoded_andMatrixOutputs_T_75 = cat(decoder_decoded_andMatrixOutputs_hi_75, decoder_decoded_andMatrixOutputs_lo_75) node decoder_decoded_andMatrixOutputs_28_2 = andr(_decoder_decoded_andMatrixOutputs_T_75) node decoder_decoded_andMatrixOutputs_andMatrixInput_0_76 = bits(decoder_decoded_plaInput, 0, 0) node decoder_decoded_andMatrixOutputs_andMatrixInput_1_76 = bits(decoder_decoded_plaInput, 1, 1) node decoder_decoded_andMatrixOutputs_andMatrixInput_2_76 = bits(decoder_decoded_invInputs, 2, 2) node decoder_decoded_andMatrixOutputs_andMatrixInput_3_76 = bits(decoder_decoded_invInputs, 3, 3) node decoder_decoded_andMatrixOutputs_andMatrixInput_4_76 = bits(decoder_decoded_plaInput, 4, 4) node decoder_decoded_andMatrixOutputs_andMatrixInput_5_75 = bits(decoder_decoded_invInputs, 5, 5) node decoder_decoded_andMatrixOutputs_andMatrixInput_6_75 = bits(decoder_decoded_plaInput, 6, 6) node decoder_decoded_andMatrixOutputs_andMatrixInput_7_73 = bits(decoder_decoded_invInputs, 12, 12) node decoder_decoded_andMatrixOutputs_andMatrixInput_8_71 = bits(decoder_decoded_invInputs, 13, 13) node decoder_decoded_andMatrixOutputs_andMatrixInput_9_67 = bits(decoder_decoded_invInputs, 14, 14) node decoder_decoded_andMatrixOutputs_andMatrixInput_10_65 = bits(decoder_decoded_invInputs, 20, 20) node decoder_decoded_andMatrixOutputs_andMatrixInput_11_63 = bits(decoder_decoded_invInputs, 21, 21) node decoder_decoded_andMatrixOutputs_andMatrixInput_12_57 = bits(decoder_decoded_invInputs, 22, 22) node decoder_decoded_andMatrixOutputs_andMatrixInput_13_55 = bits(decoder_decoded_invInputs, 23, 23) node decoder_decoded_andMatrixOutputs_andMatrixInput_14_49 = bits(decoder_decoded_invInputs, 24, 24) node decoder_decoded_andMatrixOutputs_andMatrixInput_15_33 = bits(decoder_decoded_invInputs, 25, 25) node decoder_decoded_andMatrixOutputs_andMatrixInput_16_27 = bits(decoder_decoded_invInputs, 26, 26) node decoder_decoded_andMatrixOutputs_andMatrixInput_17_21 = bits(decoder_decoded_invInputs, 27, 27) node decoder_decoded_andMatrixOutputs_andMatrixInput_18_15 = bits(decoder_decoded_plaInput, 28, 28) node decoder_decoded_andMatrixOutputs_andMatrixInput_19_9 = bits(decoder_decoded_plaInput, 29, 29) node decoder_decoded_andMatrixOutputs_andMatrixInput_20_7 = bits(decoder_decoded_plaInput, 30, 30) node decoder_decoded_andMatrixOutputs_andMatrixInput_21_1 = bits(decoder_decoded_plaInput, 31, 31) node decoder_decoded_andMatrixOutputs_lo_lo_lo_33 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_20_7, decoder_decoded_andMatrixOutputs_andMatrixInput_21_1) node decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_9 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_17_21, decoder_decoded_andMatrixOutputs_andMatrixInput_18_15) node decoder_decoded_andMatrixOutputs_lo_lo_hi_63 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_9, decoder_decoded_andMatrixOutputs_andMatrixInput_19_9) node decoder_decoded_andMatrixOutputs_lo_lo_73 = cat(decoder_decoded_andMatrixOutputs_lo_lo_hi_63, decoder_decoded_andMatrixOutputs_lo_lo_lo_33) node decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_1 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_14_49, decoder_decoded_andMatrixOutputs_andMatrixInput_15_33) node decoder_decoded_andMatrixOutputs_lo_hi_lo_55 = cat(decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_1, decoder_decoded_andMatrixOutputs_andMatrixInput_16_27) node decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_21 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_11_63, decoder_decoded_andMatrixOutputs_andMatrixInput_12_57) node decoder_decoded_andMatrixOutputs_lo_hi_hi_67 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_21, decoder_decoded_andMatrixOutputs_andMatrixInput_13_55) node decoder_decoded_andMatrixOutputs_lo_hi_75 = cat(decoder_decoded_andMatrixOutputs_lo_hi_hi_67, decoder_decoded_andMatrixOutputs_lo_hi_lo_55) node decoder_decoded_andMatrixOutputs_lo_76 = cat(decoder_decoded_andMatrixOutputs_lo_hi_75, decoder_decoded_andMatrixOutputs_lo_lo_73) node decoder_decoded_andMatrixOutputs_hi_lo_lo_49 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_9_67, decoder_decoded_andMatrixOutputs_andMatrixInput_10_65) node decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_15 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_6_75, decoder_decoded_andMatrixOutputs_andMatrixInput_7_73) node decoder_decoded_andMatrixOutputs_hi_lo_hi_65 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_15, decoder_decoded_andMatrixOutputs_andMatrixInput_8_71) node decoder_decoded_andMatrixOutputs_hi_lo_75 = cat(decoder_decoded_andMatrixOutputs_hi_lo_hi_65, decoder_decoded_andMatrixOutputs_hi_lo_lo_49) node decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_7 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_76, decoder_decoded_andMatrixOutputs_andMatrixInput_4_76) node decoder_decoded_andMatrixOutputs_hi_hi_lo_57 = cat(decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_7, decoder_decoded_andMatrixOutputs_andMatrixInput_5_75) node decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_27 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_76, decoder_decoded_andMatrixOutputs_andMatrixInput_1_76) node decoder_decoded_andMatrixOutputs_hi_hi_hi_71 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_27, decoder_decoded_andMatrixOutputs_andMatrixInput_2_76) node decoder_decoded_andMatrixOutputs_hi_hi_76 = cat(decoder_decoded_andMatrixOutputs_hi_hi_hi_71, decoder_decoded_andMatrixOutputs_hi_hi_lo_57) node decoder_decoded_andMatrixOutputs_hi_76 = cat(decoder_decoded_andMatrixOutputs_hi_hi_76, decoder_decoded_andMatrixOutputs_hi_lo_75) node _decoder_decoded_andMatrixOutputs_T_76 = cat(decoder_decoded_andMatrixOutputs_hi_76, decoder_decoded_andMatrixOutputs_lo_76) node decoder_decoded_andMatrixOutputs_54_2 = andr(_decoder_decoded_andMatrixOutputs_T_76) node decoder_decoded_orMatrixOutputs_lo_lo_lo = cat(decoder_decoded_andMatrixOutputs_65_2, decoder_decoded_andMatrixOutputs_45_2) node decoder_decoded_orMatrixOutputs_lo_lo_hi = cat(decoder_decoded_andMatrixOutputs_68_2, decoder_decoded_andMatrixOutputs_62_2) node decoder_decoded_orMatrixOutputs_lo_lo = cat(decoder_decoded_orMatrixOutputs_lo_lo_hi, decoder_decoded_orMatrixOutputs_lo_lo_lo) node decoder_decoded_orMatrixOutputs_lo_hi_lo = cat(decoder_decoded_andMatrixOutputs_2_2, decoder_decoded_andMatrixOutputs_31_2) node decoder_decoded_orMatrixOutputs_lo_hi_hi = cat(decoder_decoded_andMatrixOutputs_26_2, decoder_decoded_andMatrixOutputs_58_2) node decoder_decoded_orMatrixOutputs_lo_hi = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi, decoder_decoded_orMatrixOutputs_lo_hi_lo) node decoder_decoded_orMatrixOutputs_lo = cat(decoder_decoded_orMatrixOutputs_lo_hi, decoder_decoded_orMatrixOutputs_lo_lo) node decoder_decoded_orMatrixOutputs_hi_lo_lo = cat(decoder_decoded_andMatrixOutputs_70_2, decoder_decoded_andMatrixOutputs_52_2) node decoder_decoded_orMatrixOutputs_hi_lo_hi = cat(decoder_decoded_andMatrixOutputs_59_2, decoder_decoded_andMatrixOutputs_3_2) node decoder_decoded_orMatrixOutputs_hi_lo = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi, decoder_decoded_orMatrixOutputs_hi_lo_lo) node decoder_decoded_orMatrixOutputs_hi_hi_lo = cat(decoder_decoded_andMatrixOutputs_33_2, decoder_decoded_andMatrixOutputs_67_2) node decoder_decoded_orMatrixOutputs_hi_hi_hi_hi = cat(decoder_decoded_andMatrixOutputs_72_2, decoder_decoded_andMatrixOutputs_16_2) node decoder_decoded_orMatrixOutputs_hi_hi_hi = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_hi, decoder_decoded_andMatrixOutputs_19_2) node decoder_decoded_orMatrixOutputs_hi_hi = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi, decoder_decoded_orMatrixOutputs_hi_hi_lo) node decoder_decoded_orMatrixOutputs_hi = cat(decoder_decoded_orMatrixOutputs_hi_hi, decoder_decoded_orMatrixOutputs_hi_lo) node _decoder_decoded_orMatrixOutputs_T = cat(decoder_decoded_orMatrixOutputs_hi, decoder_decoded_orMatrixOutputs_lo) node _decoder_decoded_orMatrixOutputs_T_1 = orr(_decoder_decoded_orMatrixOutputs_T) node _decoder_decoded_orMatrixOutputs_T_2 = cat(decoder_decoded_andMatrixOutputs_26_2, decoder_decoded_andMatrixOutputs_58_2) node _decoder_decoded_orMatrixOutputs_T_3 = orr(_decoder_decoded_orMatrixOutputs_T_2) node _decoder_decoded_orMatrixOutputs_T_4 = cat(decoder_decoded_andMatrixOutputs_69_2, decoder_decoded_andMatrixOutputs_42_2) node _decoder_decoded_orMatrixOutputs_T_5 = orr(_decoder_decoded_orMatrixOutputs_T_4) node decoder_decoded_orMatrixOutputs_lo_1 = cat(decoder_decoded_andMatrixOutputs_41_2, decoder_decoded_andMatrixOutputs_74_2) node decoder_decoded_orMatrixOutputs_hi_hi_1 = cat(decoder_decoded_andMatrixOutputs_72_2, decoder_decoded_andMatrixOutputs_18_2) node decoder_decoded_orMatrixOutputs_hi_1 = cat(decoder_decoded_orMatrixOutputs_hi_hi_1, decoder_decoded_andMatrixOutputs_8_2) node _decoder_decoded_orMatrixOutputs_T_6 = cat(decoder_decoded_orMatrixOutputs_hi_1, decoder_decoded_orMatrixOutputs_lo_1) node _decoder_decoded_orMatrixOutputs_T_7 = orr(_decoder_decoded_orMatrixOutputs_T_6) node decoder_decoded_orMatrixOutputs_lo_lo_1 = cat(decoder_decoded_andMatrixOutputs_32_2, decoder_decoded_andMatrixOutputs_64_2) node decoder_decoded_orMatrixOutputs_lo_hi_1 = cat(decoder_decoded_andMatrixOutputs_5_2, decoder_decoded_andMatrixOutputs_27_2) node decoder_decoded_orMatrixOutputs_lo_2 = cat(decoder_decoded_orMatrixOutputs_lo_hi_1, decoder_decoded_orMatrixOutputs_lo_lo_1) node decoder_decoded_orMatrixOutputs_hi_lo_1 = cat(decoder_decoded_andMatrixOutputs_73_2, decoder_decoded_andMatrixOutputs_23_2) node decoder_decoded_orMatrixOutputs_hi_hi_2 = cat(decoder_decoded_andMatrixOutputs_61_2, decoder_decoded_andMatrixOutputs_44_2) node decoder_decoded_orMatrixOutputs_hi_2 = cat(decoder_decoded_orMatrixOutputs_hi_hi_2, decoder_decoded_orMatrixOutputs_hi_lo_1) node _decoder_decoded_orMatrixOutputs_T_8 = cat(decoder_decoded_orMatrixOutputs_hi_2, decoder_decoded_orMatrixOutputs_lo_2) node _decoder_decoded_orMatrixOutputs_T_9 = orr(_decoder_decoded_orMatrixOutputs_T_8) node decoder_decoded_orMatrixOutputs_lo_lo_2 = cat(decoder_decoded_andMatrixOutputs_35_2, decoder_decoded_andMatrixOutputs_20_2) node decoder_decoded_orMatrixOutputs_lo_hi_hi_1 = cat(decoder_decoded_andMatrixOutputs_62_2, decoder_decoded_andMatrixOutputs_0_2) node decoder_decoded_orMatrixOutputs_lo_hi_2 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_1, decoder_decoded_andMatrixOutputs_4_2) node decoder_decoded_orMatrixOutputs_lo_3 = cat(decoder_decoded_orMatrixOutputs_lo_hi_2, decoder_decoded_orMatrixOutputs_lo_lo_2) node decoder_decoded_orMatrixOutputs_hi_lo_2 = cat(decoder_decoded_andMatrixOutputs_31_2, decoder_decoded_andMatrixOutputs_68_2) node decoder_decoded_orMatrixOutputs_hi_hi_hi_1 = cat(decoder_decoded_andMatrixOutputs_66_2, decoder_decoded_andMatrixOutputs_47_2) node decoder_decoded_orMatrixOutputs_hi_hi_3 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_1, decoder_decoded_andMatrixOutputs_2_2) node decoder_decoded_orMatrixOutputs_hi_3 = cat(decoder_decoded_orMatrixOutputs_hi_hi_3, decoder_decoded_orMatrixOutputs_hi_lo_2) node _decoder_decoded_orMatrixOutputs_T_10 = cat(decoder_decoded_orMatrixOutputs_hi_3, decoder_decoded_orMatrixOutputs_lo_3) node _decoder_decoded_orMatrixOutputs_T_11 = orr(_decoder_decoded_orMatrixOutputs_T_10) node decoder_decoded_orMatrixOutputs_lo_4 = cat(decoder_decoded_andMatrixOutputs_14_2, decoder_decoded_andMatrixOutputs_28_2) node decoder_decoded_orMatrixOutputs_hi_4 = cat(decoder_decoded_andMatrixOutputs_46_2, decoder_decoded_andMatrixOutputs_63_2) node _decoder_decoded_orMatrixOutputs_T_12 = cat(decoder_decoded_orMatrixOutputs_hi_4, decoder_decoded_orMatrixOutputs_lo_4) node _decoder_decoded_orMatrixOutputs_T_13 = orr(_decoder_decoded_orMatrixOutputs_T_12) node decoder_decoded_orMatrixOutputs_lo_lo_3 = cat(decoder_decoded_andMatrixOutputs_12_2, decoder_decoded_andMatrixOutputs_7_2) node decoder_decoded_orMatrixOutputs_lo_hi_hi_2 = cat(decoder_decoded_andMatrixOutputs_1_2, decoder_decoded_andMatrixOutputs_53_2) node decoder_decoded_orMatrixOutputs_lo_hi_3 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_2, decoder_decoded_andMatrixOutputs_76_2) node decoder_decoded_orMatrixOutputs_lo_5 = cat(decoder_decoded_orMatrixOutputs_lo_hi_3, decoder_decoded_orMatrixOutputs_lo_lo_3) node decoder_decoded_orMatrixOutputs_hi_lo_hi_1 = cat(decoder_decoded_andMatrixOutputs_50_2, decoder_decoded_andMatrixOutputs_21_2) node decoder_decoded_orMatrixOutputs_hi_lo_3 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_1, decoder_decoded_andMatrixOutputs_43_2) node decoder_decoded_orMatrixOutputs_hi_hi_hi_2 = cat(decoder_decoded_andMatrixOutputs_6_2, decoder_decoded_andMatrixOutputs_55_2) node decoder_decoded_orMatrixOutputs_hi_hi_4 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_2, decoder_decoded_andMatrixOutputs_60_2) node decoder_decoded_orMatrixOutputs_hi_5 = cat(decoder_decoded_orMatrixOutputs_hi_hi_4, decoder_decoded_orMatrixOutputs_hi_lo_3) node _decoder_decoded_orMatrixOutputs_T_14 = cat(decoder_decoded_orMatrixOutputs_hi_5, decoder_decoded_orMatrixOutputs_lo_5) node _decoder_decoded_orMatrixOutputs_T_15 = orr(_decoder_decoded_orMatrixOutputs_T_14) node decoder_decoded_orMatrixOutputs_lo_lo_hi_1 = cat(decoder_decoded_andMatrixOutputs_36_2, decoder_decoded_andMatrixOutputs_22_2) node decoder_decoded_orMatrixOutputs_lo_lo_4 = cat(decoder_decoded_orMatrixOutputs_lo_lo_hi_1, decoder_decoded_andMatrixOutputs_14_2) node decoder_decoded_orMatrixOutputs_lo_hi_hi_3 = cat(decoder_decoded_andMatrixOutputs_32_2, decoder_decoded_andMatrixOutputs_51_2) node decoder_decoded_orMatrixOutputs_lo_hi_4 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_3, decoder_decoded_andMatrixOutputs_56_2) node decoder_decoded_orMatrixOutputs_lo_6 = cat(decoder_decoded_orMatrixOutputs_lo_hi_4, decoder_decoded_orMatrixOutputs_lo_lo_4) node decoder_decoded_orMatrixOutputs_hi_lo_hi_2 = cat(decoder_decoded_andMatrixOutputs_38_2, decoder_decoded_andMatrixOutputs_10_2) node decoder_decoded_orMatrixOutputs_hi_lo_4 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_2, decoder_decoded_andMatrixOutputs_40_2) node decoder_decoded_orMatrixOutputs_hi_hi_hi_3 = cat(decoder_decoded_andMatrixOutputs_15_2, decoder_decoded_andMatrixOutputs_29_2) node decoder_decoded_orMatrixOutputs_hi_hi_5 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_3, decoder_decoded_andMatrixOutputs_39_2) node decoder_decoded_orMatrixOutputs_hi_6 = cat(decoder_decoded_orMatrixOutputs_hi_hi_5, decoder_decoded_orMatrixOutputs_hi_lo_4) node _decoder_decoded_orMatrixOutputs_T_16 = cat(decoder_decoded_orMatrixOutputs_hi_6, decoder_decoded_orMatrixOutputs_lo_6) node _decoder_decoded_orMatrixOutputs_T_17 = orr(_decoder_decoded_orMatrixOutputs_T_16) node decoder_decoded_orMatrixOutputs_lo_lo_5 = cat(decoder_decoded_andMatrixOutputs_17_2, decoder_decoded_andMatrixOutputs_54_2) node decoder_decoded_orMatrixOutputs_lo_hi_hi_4 = cat(decoder_decoded_andMatrixOutputs_11_2, decoder_decoded_andMatrixOutputs_76_2) node decoder_decoded_orMatrixOutputs_lo_hi_5 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_4, decoder_decoded_andMatrixOutputs_25_2) node decoder_decoded_orMatrixOutputs_lo_7 = cat(decoder_decoded_orMatrixOutputs_lo_hi_5, decoder_decoded_orMatrixOutputs_lo_lo_5) node decoder_decoded_orMatrixOutputs_hi_lo_hi_3 = cat(decoder_decoded_andMatrixOutputs_21_2, decoder_decoded_andMatrixOutputs_43_2) node decoder_decoded_orMatrixOutputs_hi_lo_5 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_3, decoder_decoded_andMatrixOutputs_13_2) node decoder_decoded_orMatrixOutputs_hi_hi_hi_4 = cat(decoder_decoded_andMatrixOutputs_6_2, decoder_decoded_andMatrixOutputs_55_2) node decoder_decoded_orMatrixOutputs_hi_hi_6 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_4, decoder_decoded_andMatrixOutputs_50_2) node decoder_decoded_orMatrixOutputs_hi_7 = cat(decoder_decoded_orMatrixOutputs_hi_hi_6, decoder_decoded_orMatrixOutputs_hi_lo_5) node _decoder_decoded_orMatrixOutputs_T_18 = cat(decoder_decoded_orMatrixOutputs_hi_7, decoder_decoded_orMatrixOutputs_lo_7) node _decoder_decoded_orMatrixOutputs_T_19 = orr(_decoder_decoded_orMatrixOutputs_T_18) node decoder_decoded_orMatrixOutputs_lo_lo_hi_2 = cat(decoder_decoded_andMatrixOutputs_34_2, decoder_decoded_andMatrixOutputs_36_2) node decoder_decoded_orMatrixOutputs_lo_lo_6 = cat(decoder_decoded_orMatrixOutputs_lo_lo_hi_2, decoder_decoded_andMatrixOutputs_22_2) node decoder_decoded_orMatrixOutputs_lo_hi_hi_5 = cat(decoder_decoded_andMatrixOutputs_5_2, decoder_decoded_andMatrixOutputs_51_2) node decoder_decoded_orMatrixOutputs_lo_hi_6 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_5, decoder_decoded_andMatrixOutputs_48_2) node decoder_decoded_orMatrixOutputs_lo_8 = cat(decoder_decoded_orMatrixOutputs_lo_hi_6, decoder_decoded_orMatrixOutputs_lo_lo_6) node decoder_decoded_orMatrixOutputs_hi_lo_hi_4 = cat(decoder_decoded_andMatrixOutputs_38_2, decoder_decoded_andMatrixOutputs_10_2) node decoder_decoded_orMatrixOutputs_hi_lo_6 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_4, decoder_decoded_andMatrixOutputs_40_2) node decoder_decoded_orMatrixOutputs_hi_hi_lo_1 = cat(decoder_decoded_andMatrixOutputs_29_2, decoder_decoded_andMatrixOutputs_39_2) node decoder_decoded_orMatrixOutputs_hi_hi_hi_5 = cat(decoder_decoded_andMatrixOutputs_66_2, decoder_decoded_andMatrixOutputs_47_2) node decoder_decoded_orMatrixOutputs_hi_hi_7 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_5, decoder_decoded_orMatrixOutputs_hi_hi_lo_1) node decoder_decoded_orMatrixOutputs_hi_8 = cat(decoder_decoded_orMatrixOutputs_hi_hi_7, decoder_decoded_orMatrixOutputs_hi_lo_6) node _decoder_decoded_orMatrixOutputs_T_20 = cat(decoder_decoded_orMatrixOutputs_hi_8, decoder_decoded_orMatrixOutputs_lo_8) node _decoder_decoded_orMatrixOutputs_T_21 = orr(_decoder_decoded_orMatrixOutputs_T_20) node _decoder_decoded_orMatrixOutputs_T_22 = cat(decoder_decoded_andMatrixOutputs_41_2, decoder_decoded_andMatrixOutputs_74_2) node _decoder_decoded_orMatrixOutputs_T_23 = orr(_decoder_decoded_orMatrixOutputs_T_22) node _decoder_decoded_orMatrixOutputs_T_24 = cat(decoder_decoded_andMatrixOutputs_66_2, decoder_decoded_andMatrixOutputs_47_2) node _decoder_decoded_orMatrixOutputs_T_25 = orr(_decoder_decoded_orMatrixOutputs_T_24) node _decoder_decoded_orMatrixOutputs_T_26 = orr(decoder_decoded_andMatrixOutputs_72_2) node decoder_decoded_orMatrixOutputs_lo_lo_7 = cat(decoder_decoded_andMatrixOutputs_61_2, decoder_decoded_andMatrixOutputs_44_2) node decoder_decoded_orMatrixOutputs_lo_hi_hi_6 = cat(decoder_decoded_andMatrixOutputs_24_2, decoder_decoded_andMatrixOutputs_9_2) node decoder_decoded_orMatrixOutputs_lo_hi_7 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_6, decoder_decoded_andMatrixOutputs_57_2) node decoder_decoded_orMatrixOutputs_lo_9 = cat(decoder_decoded_orMatrixOutputs_lo_hi_7, decoder_decoded_orMatrixOutputs_lo_lo_7) node decoder_decoded_orMatrixOutputs_hi_lo_hi_5 = cat(decoder_decoded_andMatrixOutputs_66_2, decoder_decoded_andMatrixOutputs_47_2) node decoder_decoded_orMatrixOutputs_hi_lo_7 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_5, decoder_decoded_andMatrixOutputs_49_2) node decoder_decoded_orMatrixOutputs_hi_hi_hi_6 = cat(decoder_decoded_andMatrixOutputs_72_2, decoder_decoded_andMatrixOutputs_16_2) node decoder_decoded_orMatrixOutputs_hi_hi_8 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_6, decoder_decoded_andMatrixOutputs_19_2) node decoder_decoded_orMatrixOutputs_hi_9 = cat(decoder_decoded_orMatrixOutputs_hi_hi_8, decoder_decoded_orMatrixOutputs_hi_lo_7) node _decoder_decoded_orMatrixOutputs_T_27 = cat(decoder_decoded_orMatrixOutputs_hi_9, decoder_decoded_orMatrixOutputs_lo_9) node _decoder_decoded_orMatrixOutputs_T_28 = orr(_decoder_decoded_orMatrixOutputs_T_27) node decoder_decoded_orMatrixOutputs_lo_lo_lo_1 = cat(decoder_decoded_andMatrixOutputs_35_2, decoder_decoded_andMatrixOutputs_20_2) node decoder_decoded_orMatrixOutputs_lo_lo_hi_3 = cat(decoder_decoded_andMatrixOutputs_0_2, decoder_decoded_andMatrixOutputs_4_2) node decoder_decoded_orMatrixOutputs_lo_lo_8 = cat(decoder_decoded_orMatrixOutputs_lo_lo_hi_3, decoder_decoded_orMatrixOutputs_lo_lo_lo_1) node decoder_decoded_orMatrixOutputs_lo_hi_lo_1 = cat(decoder_decoded_andMatrixOutputs_26_2, decoder_decoded_andMatrixOutputs_58_2) node decoder_decoded_orMatrixOutputs_lo_hi_hi_hi = cat(decoder_decoded_andMatrixOutputs_3_2, decoder_decoded_andMatrixOutputs_70_2) node decoder_decoded_orMatrixOutputs_lo_hi_hi_7 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_hi, decoder_decoded_andMatrixOutputs_52_2) node decoder_decoded_orMatrixOutputs_lo_hi_8 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_7, decoder_decoded_orMatrixOutputs_lo_hi_lo_1) node decoder_decoded_orMatrixOutputs_lo_10 = cat(decoder_decoded_orMatrixOutputs_lo_hi_8, decoder_decoded_orMatrixOutputs_lo_lo_8) node decoder_decoded_orMatrixOutputs_hi_lo_lo_1 = cat(decoder_decoded_andMatrixOutputs_44_2, decoder_decoded_andMatrixOutputs_59_2) node decoder_decoded_orMatrixOutputs_hi_lo_hi_hi = cat(decoder_decoded_andMatrixOutputs_9_2, decoder_decoded_andMatrixOutputs_57_2) node decoder_decoded_orMatrixOutputs_hi_lo_hi_6 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_hi, decoder_decoded_andMatrixOutputs_61_2) node decoder_decoded_orMatrixOutputs_hi_lo_8 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_6, decoder_decoded_orMatrixOutputs_hi_lo_lo_1) node decoder_decoded_orMatrixOutputs_hi_hi_lo_2 = cat(decoder_decoded_andMatrixOutputs_49_2, decoder_decoded_andMatrixOutputs_24_2) node decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_1 = cat(decoder_decoded_andMatrixOutputs_72_2, decoder_decoded_andMatrixOutputs_16_2) node decoder_decoded_orMatrixOutputs_hi_hi_hi_7 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_1, decoder_decoded_andMatrixOutputs_19_2) node decoder_decoded_orMatrixOutputs_hi_hi_9 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_7, decoder_decoded_orMatrixOutputs_hi_hi_lo_2) node decoder_decoded_orMatrixOutputs_hi_10 = cat(decoder_decoded_orMatrixOutputs_hi_hi_9, decoder_decoded_orMatrixOutputs_hi_lo_8) node _decoder_decoded_orMatrixOutputs_T_29 = cat(decoder_decoded_orMatrixOutputs_hi_10, decoder_decoded_orMatrixOutputs_lo_10) node _decoder_decoded_orMatrixOutputs_T_30 = orr(_decoder_decoded_orMatrixOutputs_T_29) node decoder_decoded_orMatrixOutputs_lo_lo_lo_2 = cat(decoder_decoded_andMatrixOutputs_14_2, decoder_decoded_andMatrixOutputs_28_2) node decoder_decoded_orMatrixOutputs_lo_lo_hi_4 = cat(decoder_decoded_andMatrixOutputs_46_2, decoder_decoded_andMatrixOutputs_63_2) node decoder_decoded_orMatrixOutputs_lo_lo_9 = cat(decoder_decoded_orMatrixOutputs_lo_lo_hi_4, decoder_decoded_orMatrixOutputs_lo_lo_lo_2) node decoder_decoded_orMatrixOutputs_lo_hi_lo_2 = cat(decoder_decoded_andMatrixOutputs_26_2, decoder_decoded_andMatrixOutputs_58_2) node decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_1 = cat(decoder_decoded_andMatrixOutputs_27_2, decoder_decoded_andMatrixOutputs_32_2) node decoder_decoded_orMatrixOutputs_lo_hi_hi_8 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_1, decoder_decoded_andMatrixOutputs_64_2) node decoder_decoded_orMatrixOutputs_lo_hi_9 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_8, decoder_decoded_orMatrixOutputs_lo_hi_lo_2) node decoder_decoded_orMatrixOutputs_lo_11 = cat(decoder_decoded_orMatrixOutputs_lo_hi_9, decoder_decoded_orMatrixOutputs_lo_lo_9) node decoder_decoded_orMatrixOutputs_hi_lo_lo_2 = cat(decoder_decoded_andMatrixOutputs_23_2, decoder_decoded_andMatrixOutputs_5_2) node decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_1 = cat(decoder_decoded_andMatrixOutputs_61_2, decoder_decoded_andMatrixOutputs_44_2) node decoder_decoded_orMatrixOutputs_hi_lo_hi_7 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_1, decoder_decoded_andMatrixOutputs_73_2) node decoder_decoded_orMatrixOutputs_hi_lo_9 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_7, decoder_decoded_orMatrixOutputs_hi_lo_lo_2) node decoder_decoded_orMatrixOutputs_hi_hi_lo_3 = cat(decoder_decoded_andMatrixOutputs_30_2, decoder_decoded_andMatrixOutputs_37_2) node decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_2 = cat(decoder_decoded_andMatrixOutputs_72_2, decoder_decoded_andMatrixOutputs_16_2) node decoder_decoded_orMatrixOutputs_hi_hi_hi_8 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_2, decoder_decoded_andMatrixOutputs_19_2) node decoder_decoded_orMatrixOutputs_hi_hi_10 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_8, decoder_decoded_orMatrixOutputs_hi_hi_lo_3) node decoder_decoded_orMatrixOutputs_hi_11 = cat(decoder_decoded_orMatrixOutputs_hi_hi_10, decoder_decoded_orMatrixOutputs_hi_lo_9) node _decoder_decoded_orMatrixOutputs_T_31 = cat(decoder_decoded_orMatrixOutputs_hi_11, decoder_decoded_orMatrixOutputs_lo_11) node _decoder_decoded_orMatrixOutputs_T_32 = orr(_decoder_decoded_orMatrixOutputs_T_31) node _decoder_decoded_orMatrixOutputs_T_33 = cat(decoder_decoded_andMatrixOutputs_71_2, decoder_decoded_andMatrixOutputs_75_2) node _decoder_decoded_orMatrixOutputs_T_34 = orr(_decoder_decoded_orMatrixOutputs_T_33) node decoder_decoded_orMatrixOutputs_lo_lo_lo_3 = cat(_decoder_decoded_orMatrixOutputs_T_1, UInt<1>(0h0)) node decoder_decoded_orMatrixOutputs_lo_lo_hi_5 = cat(_decoder_decoded_orMatrixOutputs_T_5, _decoder_decoded_orMatrixOutputs_T_3) node decoder_decoded_orMatrixOutputs_lo_lo_10 = cat(decoder_decoded_orMatrixOutputs_lo_lo_hi_5, decoder_decoded_orMatrixOutputs_lo_lo_lo_3) node decoder_decoded_orMatrixOutputs_lo_hi_lo_3 = cat(_decoder_decoded_orMatrixOutputs_T_9, _decoder_decoded_orMatrixOutputs_T_7) node decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_2 = cat(_decoder_decoded_orMatrixOutputs_T_15, _decoder_decoded_orMatrixOutputs_T_13) node decoder_decoded_orMatrixOutputs_lo_hi_hi_9 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_2, _decoder_decoded_orMatrixOutputs_T_11) node decoder_decoded_orMatrixOutputs_lo_hi_10 = cat(decoder_decoded_orMatrixOutputs_lo_hi_hi_9, decoder_decoded_orMatrixOutputs_lo_hi_lo_3) node decoder_decoded_orMatrixOutputs_lo_12 = cat(decoder_decoded_orMatrixOutputs_lo_hi_10, decoder_decoded_orMatrixOutputs_lo_lo_10) node decoder_decoded_orMatrixOutputs_hi_lo_lo_3 = cat(_decoder_decoded_orMatrixOutputs_T_19, _decoder_decoded_orMatrixOutputs_T_17) node decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_2 = cat(_decoder_decoded_orMatrixOutputs_T_25, _decoder_decoded_orMatrixOutputs_T_23) node decoder_decoded_orMatrixOutputs_hi_lo_hi_8 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_2, _decoder_decoded_orMatrixOutputs_T_21) node decoder_decoded_orMatrixOutputs_hi_lo_10 = cat(decoder_decoded_orMatrixOutputs_hi_lo_hi_8, decoder_decoded_orMatrixOutputs_hi_lo_lo_3) node decoder_decoded_orMatrixOutputs_hi_hi_lo_4 = cat(_decoder_decoded_orMatrixOutputs_T_28, _decoder_decoded_orMatrixOutputs_T_26) node decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_3 = cat(_decoder_decoded_orMatrixOutputs_T_34, _decoder_decoded_orMatrixOutputs_T_32) node decoder_decoded_orMatrixOutputs_hi_hi_hi_9 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_3, _decoder_decoded_orMatrixOutputs_T_30) node decoder_decoded_orMatrixOutputs_hi_hi_11 = cat(decoder_decoded_orMatrixOutputs_hi_hi_hi_9, decoder_decoded_orMatrixOutputs_hi_hi_lo_4) node decoder_decoded_orMatrixOutputs_hi_12 = cat(decoder_decoded_orMatrixOutputs_hi_hi_11, decoder_decoded_orMatrixOutputs_hi_lo_10) node decoder_decoded_orMatrixOutputs = cat(decoder_decoded_orMatrixOutputs_hi_12, decoder_decoded_orMatrixOutputs_lo_12) node _decoder_decoded_invMatrixOutputs_T = bits(decoder_decoded_orMatrixOutputs, 0, 0) node _decoder_decoded_invMatrixOutputs_T_1 = bits(decoder_decoded_orMatrixOutputs, 1, 1) node _decoder_decoded_invMatrixOutputs_T_2 = bits(decoder_decoded_orMatrixOutputs, 2, 2) node _decoder_decoded_invMatrixOutputs_T_3 = bits(decoder_decoded_orMatrixOutputs, 3, 3) node _decoder_decoded_invMatrixOutputs_T_4 = bits(decoder_decoded_orMatrixOutputs, 4, 4) node _decoder_decoded_invMatrixOutputs_T_5 = bits(decoder_decoded_orMatrixOutputs, 5, 5) node _decoder_decoded_invMatrixOutputs_T_6 = bits(decoder_decoded_orMatrixOutputs, 6, 6) node _decoder_decoded_invMatrixOutputs_T_7 = bits(decoder_decoded_orMatrixOutputs, 7, 7) node _decoder_decoded_invMatrixOutputs_T_8 = bits(decoder_decoded_orMatrixOutputs, 8, 8) node _decoder_decoded_invMatrixOutputs_T_9 = bits(decoder_decoded_orMatrixOutputs, 9, 9) node _decoder_decoded_invMatrixOutputs_T_10 = bits(decoder_decoded_orMatrixOutputs, 10, 10) node _decoder_decoded_invMatrixOutputs_T_11 = bits(decoder_decoded_orMatrixOutputs, 11, 11) node _decoder_decoded_invMatrixOutputs_T_12 = bits(decoder_decoded_orMatrixOutputs, 12, 12) node _decoder_decoded_invMatrixOutputs_T_13 = bits(decoder_decoded_orMatrixOutputs, 13, 13) node _decoder_decoded_invMatrixOutputs_T_14 = bits(decoder_decoded_orMatrixOutputs, 14, 14) node _decoder_decoded_invMatrixOutputs_T_15 = bits(decoder_decoded_orMatrixOutputs, 15, 15) node _decoder_decoded_invMatrixOutputs_T_16 = bits(decoder_decoded_orMatrixOutputs, 16, 16) node _decoder_decoded_invMatrixOutputs_T_17 = bits(decoder_decoded_orMatrixOutputs, 17, 17) node _decoder_decoded_invMatrixOutputs_T_18 = bits(decoder_decoded_orMatrixOutputs, 18, 18) node decoder_decoded_invMatrixOutputs_lo_lo_lo = cat(_decoder_decoded_invMatrixOutputs_T_1, _decoder_decoded_invMatrixOutputs_T) node decoder_decoded_invMatrixOutputs_lo_lo_hi = cat(_decoder_decoded_invMatrixOutputs_T_3, _decoder_decoded_invMatrixOutputs_T_2) node decoder_decoded_invMatrixOutputs_lo_lo = cat(decoder_decoded_invMatrixOutputs_lo_lo_hi, decoder_decoded_invMatrixOutputs_lo_lo_lo) node decoder_decoded_invMatrixOutputs_lo_hi_lo = cat(_decoder_decoded_invMatrixOutputs_T_5, _decoder_decoded_invMatrixOutputs_T_4) node decoder_decoded_invMatrixOutputs_lo_hi_hi_hi = cat(_decoder_decoded_invMatrixOutputs_T_8, _decoder_decoded_invMatrixOutputs_T_7) node decoder_decoded_invMatrixOutputs_lo_hi_hi = cat(decoder_decoded_invMatrixOutputs_lo_hi_hi_hi, _decoder_decoded_invMatrixOutputs_T_6) node decoder_decoded_invMatrixOutputs_lo_hi = cat(decoder_decoded_invMatrixOutputs_lo_hi_hi, decoder_decoded_invMatrixOutputs_lo_hi_lo) node decoder_decoded_invMatrixOutputs_lo = cat(decoder_decoded_invMatrixOutputs_lo_hi, decoder_decoded_invMatrixOutputs_lo_lo) node decoder_decoded_invMatrixOutputs_hi_lo_lo = cat(_decoder_decoded_invMatrixOutputs_T_10, _decoder_decoded_invMatrixOutputs_T_9) node decoder_decoded_invMatrixOutputs_hi_lo_hi_hi = cat(_decoder_decoded_invMatrixOutputs_T_13, _decoder_decoded_invMatrixOutputs_T_12) node decoder_decoded_invMatrixOutputs_hi_lo_hi = cat(decoder_decoded_invMatrixOutputs_hi_lo_hi_hi, _decoder_decoded_invMatrixOutputs_T_11) node decoder_decoded_invMatrixOutputs_hi_lo = cat(decoder_decoded_invMatrixOutputs_hi_lo_hi, decoder_decoded_invMatrixOutputs_hi_lo_lo) node decoder_decoded_invMatrixOutputs_hi_hi_lo = cat(_decoder_decoded_invMatrixOutputs_T_15, _decoder_decoded_invMatrixOutputs_T_14) node decoder_decoded_invMatrixOutputs_hi_hi_hi_hi = cat(_decoder_decoded_invMatrixOutputs_T_18, _decoder_decoded_invMatrixOutputs_T_17) node decoder_decoded_invMatrixOutputs_hi_hi_hi = cat(decoder_decoded_invMatrixOutputs_hi_hi_hi_hi, _decoder_decoded_invMatrixOutputs_T_16) node decoder_decoded_invMatrixOutputs_hi_hi = cat(decoder_decoded_invMatrixOutputs_hi_hi_hi, decoder_decoded_invMatrixOutputs_hi_hi_lo) node decoder_decoded_invMatrixOutputs_hi = cat(decoder_decoded_invMatrixOutputs_hi_hi, decoder_decoded_invMatrixOutputs_hi_lo) node decoder_decoded_invMatrixOutputs = cat(decoder_decoded_invMatrixOutputs_hi, decoder_decoded_invMatrixOutputs_lo) connect decoder_decoded, decoder_decoded_invMatrixOutputs connect decoder_decoded_plaInput, io.inst node decoder_0 = bits(decoder_decoded, 18, 18) node decoder_1 = bits(decoder_decoded, 17, 17) node decoder_2 = bits(decoder_decoded, 16, 16) node decoder_3 = bits(decoder_decoded, 15, 15) node decoder_4 = bits(decoder_decoded, 14, 14) node decoder_5 = bits(decoder_decoded, 13, 13) node decoder_6 = bits(decoder_decoded, 12, 12) node decoder_7 = bits(decoder_decoded, 11, 10) node decoder_8 = bits(decoder_decoded, 9, 8) node decoder_9 = bits(decoder_decoded, 7, 7) node decoder_10 = bits(decoder_decoded, 6, 6) node decoder_11 = bits(decoder_decoded, 5, 5) node decoder_12 = bits(decoder_decoded, 4, 4) node decoder_13 = bits(decoder_decoded, 3, 3) node decoder_14 = bits(decoder_decoded, 2, 2) node decoder_15 = bits(decoder_decoded, 1, 1) node decoder_16 = bits(decoder_decoded, 0, 0) connect io.sigs.ldst, decoder_0 connect io.sigs.wen, decoder_1 connect io.sigs.ren1, decoder_2 connect io.sigs.ren2, decoder_3 connect io.sigs.ren3, decoder_4 connect io.sigs.swap12, decoder_5 connect io.sigs.swap23, decoder_6 connect io.sigs.typeTagIn, decoder_7 connect io.sigs.typeTagOut, decoder_8 connect io.sigs.fromint, decoder_9 connect io.sigs.toint, decoder_10 connect io.sigs.fastpipe, decoder_11 connect io.sigs.fma, decoder_12 connect io.sigs.div, decoder_13 connect io.sigs.sqrt, decoder_14 connect io.sigs.wflags, decoder_15 connect io.sigs.vec, decoder_16	module FPUDecoder_1( // @[FPU.scala:55:7] input clock, // @[FPU.scala:55:7] input reset, // @[FPU.scala:55:7] input [31:0] io_inst, // @[FPU.scala:56:14] output io_sigs_ldst, // @[FPU.scala:56:14] output io_sigs_wen, // @[FPU.scala:56:14] output io_sigs_ren1, // @[FPU.scala:56:14] output io_sigs_ren2, // @[FPU.scala:56:14] output io_sigs_ren3, // @[FPU.scala:56:14] output io_sigs_swap12, // @[FPU.scala:56:14] output io_sigs_swap23, // @[FPU.scala:56:14] output [1:0] io_sigs_typeTagIn, // @[FPU.scala:56:14] output [1:0] io_sigs_typeTagOut, // @[FPU.scala:56:14] output io_sigs_fromint, // @[FPU.scala:56:14] output io_sigs_toint, // @[FPU.scala:56:14] output io_sigs_fastpipe, // @[FPU.scala:56:14] output io_sigs_fma, // @[FPU.scala:56:14] output io_sigs_div, // @[FPU.scala:56:14] output io_sigs_sqrt, // @[FPU.scala:56:14] output io_sigs_wflags, // @[FPU.scala:56:14] output io_sigs_vec // @[FPU.scala:56:14] ); wire [31:0] io_inst_0 = io_inst; // @[FPU.scala:55:7] wire [31:0] decoder_decoded_plaInput = io_inst_0; // @[pla.scala:77:22] wire decoder_0; // @[Decode.scala:50:77] wire decoder_1; // @[Decode.scala:50:77] wire decoder_2; // @[Decode.scala:50:77] wire decoder_3; // @[Decode.scala:50:77] wire decoder_4; // @[Decode.scala:50:77] wire decoder_5; // @[Decode.scala:50:77] wire decoder_6; // @[Decode.scala:50:77] wire [1:0] decoder_7; // @[Decode.scala:50:77] wire [1:0] decoder_8; // @[Decode.scala:50:77] wire decoder_9; // @[Decode.scala:50:77] wire decoder_10; // @[Decode.scala:50:77] wire decoder_11; // @[Decode.scala:50:77] wire decoder_12; // @[Decode.scala:50:77] wire decoder_13; // @[Decode.scala:50:77] wire decoder_14; // @[Decode.scala:50:77] wire decoder_15; // @[Decode.scala:50:77] wire decoder_16; // @[Decode.scala:50:77] wire io_sigs_ldst_0; // @[FPU.scala:55:7] wire io_sigs_wen_0; // @[FPU.scala:55:7] wire io_sigs_ren1_0; // @[FPU.scala:55:7] wire io_sigs_ren2_0; // @[FPU.scala:55:7] wire io_sigs_ren3_0; // @[FPU.scala:55:7] wire io_sigs_swap12_0; // @[FPU.scala:55:7] wire io_sigs_swap23_0; // @[FPU.scala:55:7] wire [1:0] io_sigs_typeTagIn_0; // @[FPU.scala:55:7] wire [1:0] io_sigs_typeTagOut_0; // @[FPU.scala:55:7] wire io_sigs_fromint_0; // @[FPU.scala:55:7] wire io_sigs_toint_0; // @[FPU.scala:55:7] wire io_sigs_fastpipe_0; // @[FPU.scala:55:7] wire io_sigs_fma_0; // @[FPU.scala:55:7] wire io_sigs_div_0; // @[FPU.scala:55:7] wire io_sigs_sqrt_0; // @[FPU.scala:55:7] wire io_sigs_wflags_0; // @[FPU.scala:55:7] wire io_sigs_vec_0; // @[FPU.scala:55:7] wire [31:0] decoder_decoded_invInputs = ~decoder_decoded_plaInput; // @[pla.scala:77:22, :78:21] wire [18:0] decoder_decoded_invMatrixOutputs; // @[pla.scala:120:37] wire [18:0] decoder_decoded; // @[pla.scala:81:23] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_1 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_2 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_3 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_4 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_5 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_6 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_7 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_8 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_9 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_10 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_11 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_12 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_13 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_14 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_15 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_16 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_17 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_18 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_19 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_20 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_21 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_22 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_23 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_24 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_25 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_26 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_27 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_28 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_29 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_30 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_31 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_32 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_33 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_34 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_35 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_36 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_37 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_38 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_39 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_40 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_41 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_42 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_43 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_44 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_45 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_46 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_47 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_48 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_49 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_50 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_51 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_52 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_53 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_54 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_55 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_56 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_57 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_58 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_59 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_60 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_61 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_62 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_63 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_64 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_65 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_66 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_67 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_68 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_69 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_70 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_71 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_72 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_73 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_74 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_75 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_76 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_1 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_2 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_3 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_4 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_5 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_6 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_7 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_8 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_9 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_10 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_11 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_12 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_13 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_14 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_15 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_16 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_17 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_18 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_19 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_20 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_21 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_22 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_23 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_24 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_25 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_26 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_27 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_28 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_29 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_30 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_31 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_32 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_33 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_34 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_35 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_36 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_37 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_38 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_39 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_40 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_41 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_42 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_43 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_44 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_45 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_46 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_47 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_48 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_49 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_50 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_51 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_52 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_53 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_54 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_55 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_56 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_57 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_58 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_59 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_60 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_61 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_62 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_63 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_64 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_65 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_66 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_67 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_68 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_69 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_70 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_71 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_72 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_73 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_74 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_75 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_76 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_1 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_9 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_10 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_11 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_12 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_13 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_14 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_15 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_16 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_17 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_1 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_1 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_2 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_3 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_4 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_5 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_6 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_7 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_9 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_12 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_17 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_17 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_18 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_19 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_20 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_21 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_22 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_23 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_24 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_25 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_26 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_27 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_28 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_29 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_30 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_31 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_32 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_33 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_34 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_35 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_36 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_37 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_38 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_39 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_40 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_41 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_42 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_43 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_44 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_45 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_46 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_47 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_48 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_49 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_50 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_51 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_52 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_53 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_54 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_55 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_56 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_57 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_58 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_59 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_60 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_61 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_62 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_63 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_64 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_65 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_66 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_67 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_68 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_69 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_70 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_71 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_72 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_73 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_74 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_75 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_1 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_1 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_2 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_3 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_4 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_5 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_6 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_7 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_17 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_17 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_18 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_19 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_20 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_21 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_22 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_23 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_24 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_25 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_26 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_27 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_28 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_29 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_30 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_31 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_32 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_33 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_34 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_35 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_36 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_37 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_38 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_39 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_40 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_41 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_42 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_43 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_44 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_45 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_46 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_47 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_48 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_49 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_50 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_51 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_52 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_53 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_54 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_55 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_56 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_57 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_58 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_59 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_60 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_61 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_62 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_63 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_64 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_65 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_66 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_67 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_68 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_69 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_70 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_71 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_72 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_73 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_74 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_75 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire [1:0] decoder_decoded_andMatrixOutputs_lo = {decoder_decoded_andMatrixOutputs_andMatrixInput_3, decoder_decoded_andMatrixOutputs_andMatrixInput_4}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi = {decoder_decoded_andMatrixOutputs_andMatrixInput_0, decoder_decoded_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi = {decoder_decoded_andMatrixOutputs_hi_hi, decoder_decoded_andMatrixOutputs_andMatrixInput_2}; // @[pla.scala:91:29, :98:53] wire [4:0] _decoder_decoded_andMatrixOutputs_T = {decoder_decoded_andMatrixOutputs_hi, decoder_decoded_andMatrixOutputs_lo}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_72_2 = &_decoder_decoded_andMatrixOutputs_T; // @[pla.scala:98:{53,70}] wire _decoder_decoded_orMatrixOutputs_T_26 = decoder_decoded_andMatrixOutputs_72_2; // @[pla.scala:98:70, :114:36] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_2 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_3 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_5 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_16 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_12 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_13 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_16 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_17 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_18 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_20 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_21 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_26 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_18 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_19 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_20 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_23 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_33 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_34 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_29 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_30 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_32 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_44 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_45 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_46 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_48 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_49 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_52 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_54 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_40 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_25 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_43 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_28 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_31 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_33 = decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_1 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_2 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_4 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_6 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_16 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_13 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_17 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_14 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_15 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_14 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_15 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_19 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_18 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_22 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_21 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_22 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_23 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_27 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_18 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_21 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_22 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_21 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_24 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_25 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_24 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_31 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_30 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_31 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_46 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_47 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_47 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_46 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_50 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_49 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_53 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_52 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_53 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_42 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_27 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_22 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_23 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_30 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_32 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_27 = decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_1, decoder_decoded_andMatrixOutputs_andMatrixInput_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_1 = {decoder_decoded_andMatrixOutputs_lo_hi, decoder_decoded_andMatrixOutputs_andMatrixInput_6}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_1, decoder_decoded_andMatrixOutputs_andMatrixInput_3_1}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_1, decoder_decoded_andMatrixOutputs_andMatrixInput_1_1}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_1 = {decoder_decoded_andMatrixOutputs_hi_hi_1, decoder_decoded_andMatrixOutputs_hi_lo}; // @[pla.scala:98:53] wire [6:0] _decoder_decoded_andMatrixOutputs_T_1 = {decoder_decoded_andMatrixOutputs_hi_1, decoder_decoded_andMatrixOutputs_lo_1}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_6_2 = &_decoder_decoded_andMatrixOutputs_T_1; // @[pla.scala:98:{53,70}] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_2 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_3 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_4 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_5 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_6 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_7 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_8 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_18 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_19 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_20 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_21 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_22 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_23 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_24 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_25 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_26 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_27 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_28 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_29 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_30 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_31 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_32 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_33 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_34 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_35 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_36 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_37 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_38 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_39 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_40 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_41 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_42 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_43 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_44 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_45 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_46 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_47 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_48 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_49 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_50 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_51 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_52 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_53 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_54 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_55 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_56 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_57 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_58 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_59 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_60 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_61 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_62 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_63 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_64 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_65 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_66 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_67 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_68 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_69 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_70 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_71 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_72 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_73 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_74 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_75 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_76 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_2 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_3 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_4 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_5 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_6 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_7 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_8 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_9 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_10 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_11 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_12 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_13 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_14 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_15 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_16 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_18 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_19 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_20 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_21 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_22 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_23 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_24 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_25 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_26 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_27 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_28 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_29 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_30 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_31 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_32 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_33 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_34 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_35 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_36 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_37 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_38 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_39 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_40 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_41 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_42 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_43 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_44 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_45 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_46 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_47 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_48 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_49 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_50 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_51 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_52 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_53 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_54 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_55 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_56 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_57 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_58 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_59 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_60 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_61 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_62 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_63 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_64 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_65 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_66 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_67 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_68 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_69 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_70 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_71 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_72 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_73 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_74 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_75 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_76 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_2 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_3 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_4 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_5 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_6 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_7 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_8 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_18 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_19 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_20 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_21 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_22 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_23 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_24 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_25 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_26 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_27 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_28 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_29 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_30 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_31 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_32 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_33 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_34 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_35 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_36 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_37 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_38 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_39 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_40 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_41 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_42 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_43 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_44 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_45 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_46 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_47 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_48 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_49 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_50 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_51 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_52 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_53 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_54 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_55 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_56 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_57 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_58 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_59 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_60 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_61 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_62 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_63 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_64 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_65 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_66 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_67 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_68 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_69 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_70 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_71 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_72 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_73 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_74 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_75 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_76 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_1 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_2 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_3 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_4 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_5 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_6 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_9 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_8 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_9 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_1 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_2 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_3 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_4 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_5 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_6 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_7 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_8 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_9 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_10 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_11 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_12 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_13 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_14 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_15 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_38 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_39 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_38 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_39 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_40 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_41 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_42 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_43 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_38 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_39 = decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_1 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_2 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_3 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_4 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_5 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_6 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_7 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_6 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_7 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_1 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_2 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_3 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_1 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_8 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_9 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_8 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_9 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_10 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_5 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_6 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_13 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_14 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_15 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_32 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_33 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_34 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_35 = decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_1 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_1 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_2 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_3 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_4 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_5 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_1 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_6 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_7 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_2 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_3 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_4 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_7 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_8 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_9 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_18 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_2 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_1 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_4 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_2 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_6 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_3 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_8 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_9 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_4 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_5 = decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo = {decoder_decoded_andMatrixOutputs_andMatrixInput_9, decoder_decoded_andMatrixOutputs_andMatrixInput_10}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_1, decoder_decoded_andMatrixOutputs_andMatrixInput_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_1 = {decoder_decoded_andMatrixOutputs_lo_hi_hi, decoder_decoded_andMatrixOutputs_andMatrixInput_8}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_2 = {decoder_decoded_andMatrixOutputs_lo_hi_1, decoder_decoded_andMatrixOutputs_lo_lo}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_2, decoder_decoded_andMatrixOutputs_andMatrixInput_4_2}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_1 = {decoder_decoded_andMatrixOutputs_hi_lo_hi, decoder_decoded_andMatrixOutputs_andMatrixInput_5_1}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_2, decoder_decoded_andMatrixOutputs_andMatrixInput_1_2}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_2 = {decoder_decoded_andMatrixOutputs_hi_hi_hi, decoder_decoded_andMatrixOutputs_andMatrixInput_2_2}; // @[pla.scala:91:29, :98:53] wire [5:0] decoder_decoded_andMatrixOutputs_hi_2 = {decoder_decoded_andMatrixOutputs_hi_hi_2, decoder_decoded_andMatrixOutputs_hi_lo_1}; // @[pla.scala:98:53] wire [10:0] _decoder_decoded_andMatrixOutputs_T_2 = {decoder_decoded_andMatrixOutputs_hi_2, decoder_decoded_andMatrixOutputs_lo_2}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_16_2 = &_decoder_decoded_andMatrixOutputs_T_2; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_1, decoder_decoded_andMatrixOutputs_andMatrixInput_10_1}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_2, decoder_decoded_andMatrixOutputs_andMatrixInput_7_1}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_2 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_1, decoder_decoded_andMatrixOutputs_andMatrixInput_8_1}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_3 = {decoder_decoded_andMatrixOutputs_lo_hi_2, decoder_decoded_andMatrixOutputs_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_3, decoder_decoded_andMatrixOutputs_andMatrixInput_4_3}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_2 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_1, decoder_decoded_andMatrixOutputs_andMatrixInput_5_2}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_3, decoder_decoded_andMatrixOutputs_andMatrixInput_1_3}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_3 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_1, decoder_decoded_andMatrixOutputs_andMatrixInput_2_3}; // @[pla.scala:91:29, :98:53] wire [5:0] decoder_decoded_andMatrixOutputs_hi_3 = {decoder_decoded_andMatrixOutputs_hi_hi_3, decoder_decoded_andMatrixOutputs_hi_lo_2}; // @[pla.scala:98:53] wire [10:0] _decoder_decoded_andMatrixOutputs_T_3 = {decoder_decoded_andMatrixOutputs_hi_3, decoder_decoded_andMatrixOutputs_lo_3}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_19_2 = &_decoder_decoded_andMatrixOutputs_T_3; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_2, decoder_decoded_andMatrixOutputs_andMatrixInput_10_2}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_2 = {decoder_decoded_andMatrixOutputs_lo_lo_hi, decoder_decoded_andMatrixOutputs_andMatrixInput_11}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_2 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_3, decoder_decoded_andMatrixOutputs_andMatrixInput_7_2}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_3 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_2, decoder_decoded_andMatrixOutputs_andMatrixInput_8_2}; // @[pla.scala:91:29, :98:53] wire [5:0] decoder_decoded_andMatrixOutputs_lo_4 = {decoder_decoded_andMatrixOutputs_lo_hi_3, decoder_decoded_andMatrixOutputs_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_2 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_4, decoder_decoded_andMatrixOutputs_andMatrixInput_4_4}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_3 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_2, decoder_decoded_andMatrixOutputs_andMatrixInput_5_3}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_2 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_4, decoder_decoded_andMatrixOutputs_andMatrixInput_1_4}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_4 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_2, decoder_decoded_andMatrixOutputs_andMatrixInput_2_4}; // @[pla.scala:91:29, :98:53] wire [5:0] decoder_decoded_andMatrixOutputs_hi_4 = {decoder_decoded_andMatrixOutputs_hi_hi_4, decoder_decoded_andMatrixOutputs_hi_lo_3}; // @[pla.scala:98:53] wire [11:0] _decoder_decoded_andMatrixOutputs_T_4 = {decoder_decoded_andMatrixOutputs_hi_4, decoder_decoded_andMatrixOutputs_lo_4}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_55_2 = &_decoder_decoded_andMatrixOutputs_T_4; // @[pla.scala:98:{53,70}] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_3 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_4 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_10 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_11 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_12 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_13 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_12 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_13 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_19 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_20 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_19 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_20 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_16 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_17 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_12 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_19 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_20 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_15 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_22 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_23 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_18 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_25 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_26 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_21 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_42 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_43 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_44 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_45 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_44 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_45 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_40 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_47 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_48 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_43 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_50 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_51 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_46 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_47 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_24 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_19 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_26 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_21 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_16 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_17 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_24 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_25 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_26 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_21 = decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_3, decoder_decoded_andMatrixOutputs_andMatrixInput_10_3}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_3 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_1, decoder_decoded_andMatrixOutputs_andMatrixInput_11_1}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_3 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_4, decoder_decoded_andMatrixOutputs_andMatrixInput_7_3}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_4 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_3, decoder_decoded_andMatrixOutputs_andMatrixInput_8_3}; // @[pla.scala:91:29, :98:53] wire [5:0] decoder_decoded_andMatrixOutputs_lo_5 = {decoder_decoded_andMatrixOutputs_lo_hi_4, decoder_decoded_andMatrixOutputs_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_3 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_5, decoder_decoded_andMatrixOutputs_andMatrixInput_4_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_4 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_3, decoder_decoded_andMatrixOutputs_andMatrixInput_5_4}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_3 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_5, decoder_decoded_andMatrixOutputs_andMatrixInput_1_5}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_5 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_3, decoder_decoded_andMatrixOutputs_andMatrixInput_2_5}; // @[pla.scala:91:29, :98:53] wire [5:0] decoder_decoded_andMatrixOutputs_hi_5 = {decoder_decoded_andMatrixOutputs_hi_hi_5, decoder_decoded_andMatrixOutputs_hi_lo_4}; // @[pla.scala:98:53] wire [11:0] _decoder_decoded_andMatrixOutputs_T_5 = {decoder_decoded_andMatrixOutputs_hi_5, decoder_decoded_andMatrixOutputs_lo_5}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_18_2 = &_decoder_decoded_andMatrixOutputs_T_5; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_2 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_4, decoder_decoded_andMatrixOutputs_andMatrixInput_10_4}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_4 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_2, decoder_decoded_andMatrixOutputs_andMatrixInput_11_2}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_4 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_5, decoder_decoded_andMatrixOutputs_andMatrixInput_7_4}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_5 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_4, decoder_decoded_andMatrixOutputs_andMatrixInput_8_4}; // @[pla.scala:91:29, :98:53] wire [5:0] decoder_decoded_andMatrixOutputs_lo_6 = {decoder_decoded_andMatrixOutputs_lo_hi_5, decoder_decoded_andMatrixOutputs_lo_lo_4}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_4 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_6, decoder_decoded_andMatrixOutputs_andMatrixInput_4_6}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_5 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_4, decoder_decoded_andMatrixOutputs_andMatrixInput_5_5}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_4 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_6, decoder_decoded_andMatrixOutputs_andMatrixInput_1_6}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_6 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_4, decoder_decoded_andMatrixOutputs_andMatrixInput_2_6}; // @[pla.scala:91:29, :98:53] wire [5:0] decoder_decoded_andMatrixOutputs_hi_6 = {decoder_decoded_andMatrixOutputs_hi_hi_6, decoder_decoded_andMatrixOutputs_hi_lo_5}; // @[pla.scala:98:53] wire [11:0] _decoder_decoded_andMatrixOutputs_T_6 = {decoder_decoded_andMatrixOutputs_hi_6, decoder_decoded_andMatrixOutputs_lo_6}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_8_2 = &_decoder_decoded_andMatrixOutputs_T_6; // @[pla.scala:98:{53,70}] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_5 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_6 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_8 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_9 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_10 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_11 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_6 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_7 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_16 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_17 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_16 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_17 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_18 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_13 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_14 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_21 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_22 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_23 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_10 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_11 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_2 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_13 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_14 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_5 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_16 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_17 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_8 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_19 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_20 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_11 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_40 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_41 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_42 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_43 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_41 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_42 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_18 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_13 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_20 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_15 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_10 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_18 = decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_3 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_5, decoder_decoded_andMatrixOutputs_andMatrixInput_10_5}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_5 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_3, decoder_decoded_andMatrixOutputs_andMatrixInput_11_3}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_5 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_6, decoder_decoded_andMatrixOutputs_andMatrixInput_7_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_6 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_5, decoder_decoded_andMatrixOutputs_andMatrixInput_8_5}; // @[pla.scala:91:29, :98:53] wire [5:0] decoder_decoded_andMatrixOutputs_lo_7 = {decoder_decoded_andMatrixOutputs_lo_hi_6, decoder_decoded_andMatrixOutputs_lo_lo_5}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_5 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_7, decoder_decoded_andMatrixOutputs_andMatrixInput_4_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_6 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_5, decoder_decoded_andMatrixOutputs_andMatrixInput_5_6}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_5 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_7, decoder_decoded_andMatrixOutputs_andMatrixInput_1_7}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_7 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_5, decoder_decoded_andMatrixOutputs_andMatrixInput_2_7}; // @[pla.scala:91:29, :98:53] wire [5:0] decoder_decoded_andMatrixOutputs_hi_7 = {decoder_decoded_andMatrixOutputs_hi_hi_7, decoder_decoded_andMatrixOutputs_hi_lo_6}; // @[pla.scala:98:53] wire [11:0] _decoder_decoded_andMatrixOutputs_T_7 = {decoder_decoded_andMatrixOutputs_hi_7, decoder_decoded_andMatrixOutputs_lo_7}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_41_2 = &_decoder_decoded_andMatrixOutputs_T_7; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_4 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_6, decoder_decoded_andMatrixOutputs_andMatrixInput_10_6}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_6 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_4, decoder_decoded_andMatrixOutputs_andMatrixInput_11_4}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_6 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_7, decoder_decoded_andMatrixOutputs_andMatrixInput_7_6}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_7 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_6, decoder_decoded_andMatrixOutputs_andMatrixInput_8_6}; // @[pla.scala:91:29, :98:53] wire [5:0] decoder_decoded_andMatrixOutputs_lo_8 = {decoder_decoded_andMatrixOutputs_lo_hi_7, decoder_decoded_andMatrixOutputs_lo_lo_6}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_6 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_8, decoder_decoded_andMatrixOutputs_andMatrixInput_4_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_7 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_6, decoder_decoded_andMatrixOutputs_andMatrixInput_5_7}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_6 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_8, decoder_decoded_andMatrixOutputs_andMatrixInput_1_8}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_8 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_6, decoder_decoded_andMatrixOutputs_andMatrixInput_2_8}; // @[pla.scala:91:29, :98:53] wire [5:0] decoder_decoded_andMatrixOutputs_hi_8 = {decoder_decoded_andMatrixOutputs_hi_hi_8, decoder_decoded_andMatrixOutputs_hi_lo_7}; // @[pla.scala:98:53] wire [11:0] _decoder_decoded_andMatrixOutputs_T_8 = {decoder_decoded_andMatrixOutputs_hi_8, decoder_decoded_andMatrixOutputs_lo_8}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_74_2 = &_decoder_decoded_andMatrixOutputs_T_8; // @[pla.scala:98:{53,70}] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_9 = decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_10 = decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_11 = decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_12 = decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_13 = decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_14 = decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_15 = decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_16 = decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_8 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_9 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_10 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_11 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_12 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_13 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_14 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_15 = decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_8 = decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_8 = decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_9 = decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_14 = decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_68 = decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_7 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_7 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_8 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_10 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_9 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_10 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_7 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_8 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_16 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_17 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_18 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_19 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_20 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_21 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_22 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_23 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_24 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_25 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_26 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_27 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_28 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_29 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_30 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_31 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_48 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_49 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_50 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_51 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_62 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_59 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_64 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_65 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_62 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_63 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_68 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_65 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_66 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_67 = decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_7 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_8, decoder_decoded_andMatrixOutputs_andMatrixInput_7_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_8 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_9, decoder_decoded_andMatrixOutputs_andMatrixInput_5_8}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_9 = {decoder_decoded_andMatrixOutputs_lo_hi_8, decoder_decoded_andMatrixOutputs_lo_lo_7}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_8 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_9, decoder_decoded_andMatrixOutputs_andMatrixInput_3_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_9 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_9, decoder_decoded_andMatrixOutputs_andMatrixInput_1_9}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_9 = {decoder_decoded_andMatrixOutputs_hi_hi_9, decoder_decoded_andMatrixOutputs_hi_lo_8}; // @[pla.scala:98:53] wire [7:0] _decoder_decoded_andMatrixOutputs_T_9 = {decoder_decoded_andMatrixOutputs_hi_9, decoder_decoded_andMatrixOutputs_lo_9}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_71_2 = &_decoder_decoded_andMatrixOutputs_T_9; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_8 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_8, decoder_decoded_andMatrixOutputs_andMatrixInput_8_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_9 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_9, decoder_decoded_andMatrixOutputs_andMatrixInput_6_9}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_10 = {decoder_decoded_andMatrixOutputs_lo_hi_9, decoder_decoded_andMatrixOutputs_lo_lo_8}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_9 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_10, decoder_decoded_andMatrixOutputs_andMatrixInput_4_10}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_7 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_10, decoder_decoded_andMatrixOutputs_andMatrixInput_1_10}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_10 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_7, decoder_decoded_andMatrixOutputs_andMatrixInput_2_10}; // @[pla.scala:90:45, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_10 = {decoder_decoded_andMatrixOutputs_hi_hi_10, decoder_decoded_andMatrixOutputs_hi_lo_9}; // @[pla.scala:98:53] wire [8:0] _decoder_decoded_andMatrixOutputs_T_10 = {decoder_decoded_andMatrixOutputs_hi_10, decoder_decoded_andMatrixOutputs_lo_10}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_30_2 = &_decoder_decoded_andMatrixOutputs_T_10; // @[pla.scala:98:{53,70}] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_10 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_13 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_14 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_15 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_9 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_9, decoder_decoded_andMatrixOutputs_andMatrixInput_8_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_10 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_10, decoder_decoded_andMatrixOutputs_andMatrixInput_6_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_11 = {decoder_decoded_andMatrixOutputs_lo_hi_10, decoder_decoded_andMatrixOutputs_lo_lo_9}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_10 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_11, decoder_decoded_andMatrixOutputs_andMatrixInput_4_11}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_8 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_11, decoder_decoded_andMatrixOutputs_andMatrixInput_1_11}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_11 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_8, decoder_decoded_andMatrixOutputs_andMatrixInput_2_11}; // @[pla.scala:90:45, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_11 = {decoder_decoded_andMatrixOutputs_hi_hi_11, decoder_decoded_andMatrixOutputs_hi_lo_10}; // @[pla.scala:98:53] wire [8:0] _decoder_decoded_andMatrixOutputs_T_11 = {decoder_decoded_andMatrixOutputs_hi_11, decoder_decoded_andMatrixOutputs_lo_11}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_66_2 = &_decoder_decoded_andMatrixOutputs_T_11; // @[pla.scala:98:{53,70}] wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_11 = decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_11 = decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_12 = decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_11 = decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_12 = decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_10 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_11, decoder_decoded_andMatrixOutputs_andMatrixInput_7_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_11 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_12, decoder_decoded_andMatrixOutputs_andMatrixInput_5_11}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_12 = {decoder_decoded_andMatrixOutputs_lo_hi_11, decoder_decoded_andMatrixOutputs_lo_lo_10}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_11 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_12, decoder_decoded_andMatrixOutputs_andMatrixInput_3_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_12 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_12, decoder_decoded_andMatrixOutputs_andMatrixInput_1_12}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_12 = {decoder_decoded_andMatrixOutputs_hi_hi_12, decoder_decoded_andMatrixOutputs_hi_lo_11}; // @[pla.scala:98:53] wire [7:0] _decoder_decoded_andMatrixOutputs_T_12 = {decoder_decoded_andMatrixOutputs_hi_12, decoder_decoded_andMatrixOutputs_lo_12}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_75_2 = &_decoder_decoded_andMatrixOutputs_T_12; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_11 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_11, decoder_decoded_andMatrixOutputs_andMatrixInput_8_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_12 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_12, decoder_decoded_andMatrixOutputs_andMatrixInput_6_12}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_13 = {decoder_decoded_andMatrixOutputs_lo_hi_12, decoder_decoded_andMatrixOutputs_lo_lo_11}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_12 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_13, decoder_decoded_andMatrixOutputs_andMatrixInput_4_13}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_9 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_13, decoder_decoded_andMatrixOutputs_andMatrixInput_1_13}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_13 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_9, decoder_decoded_andMatrixOutputs_andMatrixInput_2_13}; // @[pla.scala:90:45, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_13 = {decoder_decoded_andMatrixOutputs_hi_hi_13, decoder_decoded_andMatrixOutputs_hi_lo_12}; // @[pla.scala:98:53] wire [8:0] _decoder_decoded_andMatrixOutputs_T_13 = {decoder_decoded_andMatrixOutputs_hi_13, decoder_decoded_andMatrixOutputs_lo_13}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_37_2 = &_decoder_decoded_andMatrixOutputs_T_13; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_12 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_12, decoder_decoded_andMatrixOutputs_andMatrixInput_8_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_13 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_13, decoder_decoded_andMatrixOutputs_andMatrixInput_6_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_14 = {decoder_decoded_andMatrixOutputs_lo_hi_13, decoder_decoded_andMatrixOutputs_lo_lo_12}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_13 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_14, decoder_decoded_andMatrixOutputs_andMatrixInput_4_14}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_10 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_14, decoder_decoded_andMatrixOutputs_andMatrixInput_1_14}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_14 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_10, decoder_decoded_andMatrixOutputs_andMatrixInput_2_14}; // @[pla.scala:90:45, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_14 = {decoder_decoded_andMatrixOutputs_hi_hi_14, decoder_decoded_andMatrixOutputs_hi_lo_13}; // @[pla.scala:98:53] wire [8:0] _decoder_decoded_andMatrixOutputs_T_14 = {decoder_decoded_andMatrixOutputs_hi_14, decoder_decoded_andMatrixOutputs_lo_14}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_47_2 = &_decoder_decoded_andMatrixOutputs_T_14; // @[pla.scala:98:{53,70}] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_13 = decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_18 = decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_20 = decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_22 = decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_27 = decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_28 = decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_29 = decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_50 = decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_52 = decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_65 = decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_69 = decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_71 = decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_72 = decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_73 = decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_13 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_11, decoder_decoded_andMatrixOutputs_andMatrixInput_9_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_7 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_14, decoder_decoded_andMatrixOutputs_andMatrixInput_6_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_14 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_7, decoder_decoded_andMatrixOutputs_andMatrixInput_7_13}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_15 = {decoder_decoded_andMatrixOutputs_lo_hi_14, decoder_decoded_andMatrixOutputs_lo_lo_13}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_14 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_15, decoder_decoded_andMatrixOutputs_andMatrixInput_4_15}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_11 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_15, decoder_decoded_andMatrixOutputs_andMatrixInput_1_15}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_15 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_11, decoder_decoded_andMatrixOutputs_andMatrixInput_2_15}; // @[pla.scala:90:45, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_15 = {decoder_decoded_andMatrixOutputs_hi_hi_15, decoder_decoded_andMatrixOutputs_hi_lo_14}; // @[pla.scala:98:53] wire [9:0] _decoder_decoded_andMatrixOutputs_T_15 = {decoder_decoded_andMatrixOutputs_hi_15, decoder_decoded_andMatrixOutputs_lo_15}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_60_2 = &_decoder_decoded_andMatrixOutputs_T_15; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_14 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_12, decoder_decoded_andMatrixOutputs_andMatrixInput_9_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_8 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_15, decoder_decoded_andMatrixOutputs_andMatrixInput_6_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_15 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_8, decoder_decoded_andMatrixOutputs_andMatrixInput_7_14}; // @[pla.scala:90:45, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_16 = {decoder_decoded_andMatrixOutputs_lo_hi_15, decoder_decoded_andMatrixOutputs_lo_lo_14}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_15 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_16, decoder_decoded_andMatrixOutputs_andMatrixInput_4_16}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_12 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_16, decoder_decoded_andMatrixOutputs_andMatrixInput_1_16}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_16 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_12, decoder_decoded_andMatrixOutputs_andMatrixInput_2_16}; // @[pla.scala:90:45, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_16 = {decoder_decoded_andMatrixOutputs_hi_hi_16, decoder_decoded_andMatrixOutputs_hi_lo_15}; // @[pla.scala:98:53] wire [9:0] _decoder_decoded_andMatrixOutputs_T_16 = {decoder_decoded_andMatrixOutputs_hi_16, decoder_decoded_andMatrixOutputs_lo_16}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_15_2 = &_decoder_decoded_andMatrixOutputs_T_16; // @[pla.scala:98:{53,70}] wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_16 = decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_15 = decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_23 = decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_24 = decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_25 = decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_30 = decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_31 = decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_26 = decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_33 = decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_51 = decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_55 = decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_29 = decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_46 = decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_16 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_17, decoder_decoded_andMatrixOutputs_andMatrixInput_5_16}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_17 = {decoder_decoded_andMatrixOutputs_lo_hi_16, decoder_decoded_andMatrixOutputs_andMatrixInput_6_16}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_16 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_17, decoder_decoded_andMatrixOutputs_andMatrixInput_3_17}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_17 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_17, decoder_decoded_andMatrixOutputs_andMatrixInput_1_17}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_17 = {decoder_decoded_andMatrixOutputs_hi_hi_17, decoder_decoded_andMatrixOutputs_hi_lo_16}; // @[pla.scala:98:53] wire [6:0] _decoder_decoded_andMatrixOutputs_T_17 = {decoder_decoded_andMatrixOutputs_hi_17, decoder_decoded_andMatrixOutputs_lo_17}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_29_2 = &_decoder_decoded_andMatrixOutputs_T_17; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_5 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_9, decoder_decoded_andMatrixOutputs_andMatrixInput_10_7}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_15 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_5, decoder_decoded_andMatrixOutputs_andMatrixInput_11_5}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_9 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_17, decoder_decoded_andMatrixOutputs_andMatrixInput_7_15}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_17 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_9, decoder_decoded_andMatrixOutputs_andMatrixInput_8_13}; // @[pla.scala:91:29, :98:53] wire [5:0] decoder_decoded_andMatrixOutputs_lo_18 = {decoder_decoded_andMatrixOutputs_lo_hi_17, decoder_decoded_andMatrixOutputs_lo_lo_15}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_7 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_18, decoder_decoded_andMatrixOutputs_andMatrixInput_4_18}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_17 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_7, decoder_decoded_andMatrixOutputs_andMatrixInput_5_17}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_13 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_18, decoder_decoded_andMatrixOutputs_andMatrixInput_1_18}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_18 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_13, decoder_decoded_andMatrixOutputs_andMatrixInput_2_18}; // @[pla.scala:91:29, :98:53] wire [5:0] decoder_decoded_andMatrixOutputs_hi_18 = {decoder_decoded_andMatrixOutputs_hi_hi_18, decoder_decoded_andMatrixOutputs_hi_lo_17}; // @[pla.scala:98:53] wire [11:0] _decoder_decoded_andMatrixOutputs_T_18 = {decoder_decoded_andMatrixOutputs_hi_18, decoder_decoded_andMatrixOutputs_lo_18}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_39_2 = &_decoder_decoded_andMatrixOutputs_T_18; // @[pla.scala:98:{53,70}] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_14 = decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_15 = decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_24 = decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_25 = decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_28 = decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_29 = decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_24 = decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_25 = decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_10 = decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_11 = decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_22 = decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_23 = decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_14 = decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_15 = decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_44 = decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_45 = decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_44 = decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_45 = decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_19 = decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_20 = decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_15 = decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_6 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_8, decoder_decoded_andMatrixOutputs_andMatrixInput_11_6}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_16 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_6, decoder_decoded_andMatrixOutputs_andMatrixInput_12}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_10 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_16, decoder_decoded_andMatrixOutputs_andMatrixInput_8_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_18 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_10, decoder_decoded_andMatrixOutputs_andMatrixInput_9_10}; // @[pla.scala:90:45, :98:53] wire [5:0] decoder_decoded_andMatrixOutputs_lo_19 = {decoder_decoded_andMatrixOutputs_lo_hi_18, decoder_decoded_andMatrixOutputs_lo_lo_16}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_8 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_19, decoder_decoded_andMatrixOutputs_andMatrixInput_5_18}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_18 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_8, decoder_decoded_andMatrixOutputs_andMatrixInput_6_18}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_19, decoder_decoded_andMatrixOutputs_andMatrixInput_3_19}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_14 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_19, decoder_decoded_andMatrixOutputs_andMatrixInput_1_19}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_19 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_14, decoder_decoded_andMatrixOutputs_hi_hi_lo}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_hi_19 = {decoder_decoded_andMatrixOutputs_hi_hi_19, decoder_decoded_andMatrixOutputs_hi_lo_18}; // @[pla.scala:98:53] wire [12:0] _decoder_decoded_andMatrixOutputs_T_19 = {decoder_decoded_andMatrixOutputs_hi_19, decoder_decoded_andMatrixOutputs_lo_19}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_69_2 = &_decoder_decoded_andMatrixOutputs_T_19; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_7 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_9, decoder_decoded_andMatrixOutputs_andMatrixInput_11_7}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_17 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_7, decoder_decoded_andMatrixOutputs_andMatrixInput_12_1}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_11 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_17, decoder_decoded_andMatrixOutputs_andMatrixInput_8_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_19 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_11, decoder_decoded_andMatrixOutputs_andMatrixInput_9_11}; // @[pla.scala:90:45, :98:53] wire [5:0] decoder_decoded_andMatrixOutputs_lo_20 = {decoder_decoded_andMatrixOutputs_lo_hi_19, decoder_decoded_andMatrixOutputs_lo_lo_17}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_9 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_20, decoder_decoded_andMatrixOutputs_andMatrixInput_5_19}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_19 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_9, decoder_decoded_andMatrixOutputs_andMatrixInput_6_19}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_20, decoder_decoded_andMatrixOutputs_andMatrixInput_3_20}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_15 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_20, decoder_decoded_andMatrixOutputs_andMatrixInput_1_20}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_20 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_15, decoder_decoded_andMatrixOutputs_hi_hi_lo_1}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_hi_20 = {decoder_decoded_andMatrixOutputs_hi_hi_20, decoder_decoded_andMatrixOutputs_hi_lo_19}; // @[pla.scala:98:53] wire [12:0] _decoder_decoded_andMatrixOutputs_T_20 = {decoder_decoded_andMatrixOutputs_hi_20, decoder_decoded_andMatrixOutputs_lo_20}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_42_2 = &_decoder_decoded_andMatrixOutputs_T_20; // @[pla.scala:98:{53,70}] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_2 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_3 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_4 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_5 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_4 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_5 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_14 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_15 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_10 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_11 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_12 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_11 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_12 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_15 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_16 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_17 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_34 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_35 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_36 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_37 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_12 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_7 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_14 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_9 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_19_4 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_11 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_12 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_13 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_14 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_19_9 = decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_8 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_8, decoder_decoded_andMatrixOutputs_andMatrixInput_12_2}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_18 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_8, decoder_decoded_andMatrixOutputs_andMatrixInput_13}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_12, decoder_decoded_andMatrixOutputs_andMatrixInput_10_10}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_12 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_18, decoder_decoded_andMatrixOutputs_andMatrixInput_8_16}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_20 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_12, decoder_decoded_andMatrixOutputs_lo_hi_lo}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_21 = {decoder_decoded_andMatrixOutputs_lo_hi_20, decoder_decoded_andMatrixOutputs_lo_lo_18}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_10 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_21, decoder_decoded_andMatrixOutputs_andMatrixInput_5_20}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_20 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_10, decoder_decoded_andMatrixOutputs_andMatrixInput_6_20}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_2 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_21, decoder_decoded_andMatrixOutputs_andMatrixInput_3_21}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_16 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_21, decoder_decoded_andMatrixOutputs_andMatrixInput_1_21}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_21 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_16, decoder_decoded_andMatrixOutputs_hi_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_hi_21 = {decoder_decoded_andMatrixOutputs_hi_hi_21, decoder_decoded_andMatrixOutputs_hi_lo_20}; // @[pla.scala:98:53] wire [13:0] _decoder_decoded_andMatrixOutputs_T_21 = {decoder_decoded_andMatrixOutputs_hi_21, decoder_decoded_andMatrixOutputs_lo_21}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_49_2 = &_decoder_decoded_andMatrixOutputs_T_21; // @[pla.scala:98:{53,70}] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_19 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_21 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_23 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_24 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_25 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_26 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_30 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_31 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_32 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_33 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_51 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_53 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_64 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_63 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_66 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_67 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_66 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_67 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_70 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_69 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_70 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_71 = decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_9 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_9, decoder_decoded_andMatrixOutputs_andMatrixInput_12_3}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_19 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_9, decoder_decoded_andMatrixOutputs_andMatrixInput_13_1}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_13, decoder_decoded_andMatrixOutputs_andMatrixInput_10_11}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_13 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_19, decoder_decoded_andMatrixOutputs_andMatrixInput_8_17}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_21 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_13, decoder_decoded_andMatrixOutputs_lo_hi_lo_1}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_22 = {decoder_decoded_andMatrixOutputs_lo_hi_21, decoder_decoded_andMatrixOutputs_lo_lo_19}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_11 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_22, decoder_decoded_andMatrixOutputs_andMatrixInput_5_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_21 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_11, decoder_decoded_andMatrixOutputs_andMatrixInput_6_21}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_3 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_22, decoder_decoded_andMatrixOutputs_andMatrixInput_3_22}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_17 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_22, decoder_decoded_andMatrixOutputs_andMatrixInput_1_22}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_22 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_17, decoder_decoded_andMatrixOutputs_hi_hi_lo_3}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_hi_22 = {decoder_decoded_andMatrixOutputs_hi_hi_22, decoder_decoded_andMatrixOutputs_hi_lo_21}; // @[pla.scala:98:53] wire [13:0] _decoder_decoded_andMatrixOutputs_T_22 = {decoder_decoded_andMatrixOutputs_hi_22, decoder_decoded_andMatrixOutputs_lo_22}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_24_2 = &_decoder_decoded_andMatrixOutputs_T_22; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_10 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_10, decoder_decoded_andMatrixOutputs_andMatrixInput_12_4}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_20 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_10, decoder_decoded_andMatrixOutputs_andMatrixInput_13_2}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_2 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_14, decoder_decoded_andMatrixOutputs_andMatrixInput_10_12}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_14 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_20, decoder_decoded_andMatrixOutputs_andMatrixInput_8_18}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_22 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_14, decoder_decoded_andMatrixOutputs_lo_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_23 = {decoder_decoded_andMatrixOutputs_lo_hi_22, decoder_decoded_andMatrixOutputs_lo_lo_20}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_12 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_23, decoder_decoded_andMatrixOutputs_andMatrixInput_5_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_22 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_12, decoder_decoded_andMatrixOutputs_andMatrixInput_6_22}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_4 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_23, decoder_decoded_andMatrixOutputs_andMatrixInput_3_23}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_18 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_23, decoder_decoded_andMatrixOutputs_andMatrixInput_1_23}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_23 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_18, decoder_decoded_andMatrixOutputs_hi_hi_lo_4}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_hi_23 = {decoder_decoded_andMatrixOutputs_hi_hi_23, decoder_decoded_andMatrixOutputs_hi_lo_22}; // @[pla.scala:98:53] wire [13:0] _decoder_decoded_andMatrixOutputs_T_23 = {decoder_decoded_andMatrixOutputs_hi_23, decoder_decoded_andMatrixOutputs_lo_23}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_9_2 = &_decoder_decoded_andMatrixOutputs_T_23; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_11 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_11, decoder_decoded_andMatrixOutputs_andMatrixInput_12_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_21 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_11, decoder_decoded_andMatrixOutputs_andMatrixInput_13_3}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_3 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_15, decoder_decoded_andMatrixOutputs_andMatrixInput_10_13}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_15 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_21, decoder_decoded_andMatrixOutputs_andMatrixInput_8_19}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_23 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_15, decoder_decoded_andMatrixOutputs_lo_hi_lo_3}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_24 = {decoder_decoded_andMatrixOutputs_lo_hi_23, decoder_decoded_andMatrixOutputs_lo_lo_21}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_13 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_24, decoder_decoded_andMatrixOutputs_andMatrixInput_5_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_23 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_13, decoder_decoded_andMatrixOutputs_andMatrixInput_6_23}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_5 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_24, decoder_decoded_andMatrixOutputs_andMatrixInput_3_24}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_19 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_24, decoder_decoded_andMatrixOutputs_andMatrixInput_1_24}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_24 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_19, decoder_decoded_andMatrixOutputs_hi_hi_lo_5}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_hi_24 = {decoder_decoded_andMatrixOutputs_hi_hi_24, decoder_decoded_andMatrixOutputs_hi_lo_23}; // @[pla.scala:98:53] wire [13:0] _decoder_decoded_andMatrixOutputs_T_24 = {decoder_decoded_andMatrixOutputs_hi_24, decoder_decoded_andMatrixOutputs_lo_24}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_57_2 = &_decoder_decoded_andMatrixOutputs_T_24; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_12 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_6, decoder_decoded_andMatrixOutputs_andMatrixInput_13_4}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_22 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_12, decoder_decoded_andMatrixOutputs_andMatrixInput_14}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_4 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_14, decoder_decoded_andMatrixOutputs_andMatrixInput_11_12}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_16 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_20, decoder_decoded_andMatrixOutputs_andMatrixInput_9_16}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_24 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_16, decoder_decoded_andMatrixOutputs_lo_hi_lo_4}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_25 = {decoder_decoded_andMatrixOutputs_lo_hi_24, decoder_decoded_andMatrixOutputs_lo_lo_22}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_24, decoder_decoded_andMatrixOutputs_andMatrixInput_7_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_14 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_25, decoder_decoded_andMatrixOutputs_andMatrixInput_5_24}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_24 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_14, decoder_decoded_andMatrixOutputs_hi_lo_lo}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_6 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_25, decoder_decoded_andMatrixOutputs_andMatrixInput_3_25}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_20 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_25, decoder_decoded_andMatrixOutputs_andMatrixInput_1_25}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_25 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_20, decoder_decoded_andMatrixOutputs_hi_hi_lo_6}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_25 = {decoder_decoded_andMatrixOutputs_hi_hi_25, decoder_decoded_andMatrixOutputs_hi_lo_24}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_25 = {decoder_decoded_andMatrixOutputs_hi_25, decoder_decoded_andMatrixOutputs_lo_25}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_50_2 = &_decoder_decoded_andMatrixOutputs_T_25; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_13 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_7, decoder_decoded_andMatrixOutputs_andMatrixInput_13_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_23 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_13, decoder_decoded_andMatrixOutputs_andMatrixInput_14_1}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_5 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_15, decoder_decoded_andMatrixOutputs_andMatrixInput_11_13}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_17 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_21, decoder_decoded_andMatrixOutputs_andMatrixInput_9_17}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_25 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_17, decoder_decoded_andMatrixOutputs_lo_hi_lo_5}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_26 = {decoder_decoded_andMatrixOutputs_lo_hi_25, decoder_decoded_andMatrixOutputs_lo_lo_23}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_25, decoder_decoded_andMatrixOutputs_andMatrixInput_7_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_15 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_26, decoder_decoded_andMatrixOutputs_andMatrixInput_5_25}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_25 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_15, decoder_decoded_andMatrixOutputs_hi_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_7 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_26, decoder_decoded_andMatrixOutputs_andMatrixInput_3_26}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_21 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_26, decoder_decoded_andMatrixOutputs_andMatrixInput_1_26}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_26 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_21, decoder_decoded_andMatrixOutputs_hi_hi_lo_7}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_26 = {decoder_decoded_andMatrixOutputs_hi_hi_26, decoder_decoded_andMatrixOutputs_hi_lo_25}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_26 = {decoder_decoded_andMatrixOutputs_hi_26, decoder_decoded_andMatrixOutputs_lo_26}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_21_2 = &_decoder_decoded_andMatrixOutputs_T_26; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_14 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_14, decoder_decoded_andMatrixOutputs_andMatrixInput_12_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_24 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_14, decoder_decoded_andMatrixOutputs_andMatrixInput_13_6}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_6 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_18, decoder_decoded_andMatrixOutputs_andMatrixInput_10_16}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_18 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_24, decoder_decoded_andMatrixOutputs_andMatrixInput_8_22}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_26 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_18, decoder_decoded_andMatrixOutputs_lo_hi_lo_6}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_27 = {decoder_decoded_andMatrixOutputs_lo_hi_26, decoder_decoded_andMatrixOutputs_lo_lo_24}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_16 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_27, decoder_decoded_andMatrixOutputs_andMatrixInput_5_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_26 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_16, decoder_decoded_andMatrixOutputs_andMatrixInput_6_26}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_8 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_27, decoder_decoded_andMatrixOutputs_andMatrixInput_3_27}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_22 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_27, decoder_decoded_andMatrixOutputs_andMatrixInput_1_27}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_27 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_22, decoder_decoded_andMatrixOutputs_hi_hi_lo_8}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_hi_27 = {decoder_decoded_andMatrixOutputs_hi_hi_27, decoder_decoded_andMatrixOutputs_hi_lo_26}; // @[pla.scala:98:53] wire [13:0] _decoder_decoded_andMatrixOutputs_T_27 = {decoder_decoded_andMatrixOutputs_hi_27, decoder_decoded_andMatrixOutputs_lo_27}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_61_2 = &_decoder_decoded_andMatrixOutputs_T_27; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_15 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_15, decoder_decoded_andMatrixOutputs_andMatrixInput_12_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_25 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_15, decoder_decoded_andMatrixOutputs_andMatrixInput_13_7}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_7 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_19, decoder_decoded_andMatrixOutputs_andMatrixInput_10_17}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_19 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_25, decoder_decoded_andMatrixOutputs_andMatrixInput_8_23}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_27 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_19, decoder_decoded_andMatrixOutputs_lo_hi_lo_7}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_28 = {decoder_decoded_andMatrixOutputs_lo_hi_27, decoder_decoded_andMatrixOutputs_lo_lo_25}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_17 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_28, decoder_decoded_andMatrixOutputs_andMatrixInput_5_27}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_27 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_17, decoder_decoded_andMatrixOutputs_andMatrixInput_6_27}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_9 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_28, decoder_decoded_andMatrixOutputs_andMatrixInput_3_28}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_23 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_28, decoder_decoded_andMatrixOutputs_andMatrixInput_1_28}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_28 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_23, decoder_decoded_andMatrixOutputs_hi_hi_lo_9}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_hi_28 = {decoder_decoded_andMatrixOutputs_hi_hi_28, decoder_decoded_andMatrixOutputs_hi_lo_27}; // @[pla.scala:98:53] wire [13:0] _decoder_decoded_andMatrixOutputs_T_28 = {decoder_decoded_andMatrixOutputs_hi_28, decoder_decoded_andMatrixOutputs_lo_28}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_44_2 = &_decoder_decoded_andMatrixOutputs_T_28; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_16 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_10, decoder_decoded_andMatrixOutputs_andMatrixInput_13_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_26 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_16, decoder_decoded_andMatrixOutputs_andMatrixInput_14_2}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_8 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_18, decoder_decoded_andMatrixOutputs_andMatrixInput_11_16}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_20 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_24, decoder_decoded_andMatrixOutputs_andMatrixInput_9_20}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_28 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_20, decoder_decoded_andMatrixOutputs_lo_hi_lo_8}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_29 = {decoder_decoded_andMatrixOutputs_lo_hi_28, decoder_decoded_andMatrixOutputs_lo_lo_26}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_2 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_28, decoder_decoded_andMatrixOutputs_andMatrixInput_7_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_18 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_29, decoder_decoded_andMatrixOutputs_andMatrixInput_5_28}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_28 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_18, decoder_decoded_andMatrixOutputs_hi_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_10 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_29, decoder_decoded_andMatrixOutputs_andMatrixInput_3_29}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_24 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_29, decoder_decoded_andMatrixOutputs_andMatrixInput_1_29}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_29 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_24, decoder_decoded_andMatrixOutputs_hi_hi_lo_10}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_29 = {decoder_decoded_andMatrixOutputs_hi_hi_29, decoder_decoded_andMatrixOutputs_hi_lo_28}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_29 = {decoder_decoded_andMatrixOutputs_hi_29, decoder_decoded_andMatrixOutputs_lo_29}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_43_2 = &_decoder_decoded_andMatrixOutputs_T_29; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_17 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_11, decoder_decoded_andMatrixOutputs_andMatrixInput_13_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_27 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_17, decoder_decoded_andMatrixOutputs_andMatrixInput_14_3}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_9 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_19, decoder_decoded_andMatrixOutputs_andMatrixInput_11_17}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_21 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_25, decoder_decoded_andMatrixOutputs_andMatrixInput_9_21}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_29 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_21, decoder_decoded_andMatrixOutputs_lo_hi_lo_9}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_30 = {decoder_decoded_andMatrixOutputs_lo_hi_29, decoder_decoded_andMatrixOutputs_lo_lo_27}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_3 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_29, decoder_decoded_andMatrixOutputs_andMatrixInput_7_27}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_19 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_30, decoder_decoded_andMatrixOutputs_andMatrixInput_5_29}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_29 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_19, decoder_decoded_andMatrixOutputs_hi_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_11 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_30, decoder_decoded_andMatrixOutputs_andMatrixInput_3_30}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_25 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_30, decoder_decoded_andMatrixOutputs_andMatrixInput_1_30}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_30 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_25, decoder_decoded_andMatrixOutputs_hi_hi_lo_11}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_30 = {decoder_decoded_andMatrixOutputs_hi_hi_30, decoder_decoded_andMatrixOutputs_hi_lo_29}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_30 = {decoder_decoded_andMatrixOutputs_hi_30, decoder_decoded_andMatrixOutputs_lo_30}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_73_2 = &_decoder_decoded_andMatrixOutputs_T_30; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_18 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_12, decoder_decoded_andMatrixOutputs_andMatrixInput_13_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_28 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_18, decoder_decoded_andMatrixOutputs_andMatrixInput_14_4}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_10 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_20, decoder_decoded_andMatrixOutputs_andMatrixInput_11_18}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_22 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_26, decoder_decoded_andMatrixOutputs_andMatrixInput_9_22}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_30 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_22, decoder_decoded_andMatrixOutputs_lo_hi_lo_10}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_31 = {decoder_decoded_andMatrixOutputs_lo_hi_30, decoder_decoded_andMatrixOutputs_lo_lo_28}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_4 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_30, decoder_decoded_andMatrixOutputs_andMatrixInput_7_28}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_20 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_31, decoder_decoded_andMatrixOutputs_andMatrixInput_5_30}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_30 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_20, decoder_decoded_andMatrixOutputs_hi_lo_lo_4}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_12 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_31, decoder_decoded_andMatrixOutputs_andMatrixInput_3_31}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_26 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_31, decoder_decoded_andMatrixOutputs_andMatrixInput_1_31}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_31 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_26, decoder_decoded_andMatrixOutputs_hi_hi_lo_12}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_31 = {decoder_decoded_andMatrixOutputs_hi_hi_31, decoder_decoded_andMatrixOutputs_hi_lo_30}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_31 = {decoder_decoded_andMatrixOutputs_hi_31, decoder_decoded_andMatrixOutputs_lo_31}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_23_2 = &_decoder_decoded_andMatrixOutputs_T_31; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_19 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_13, decoder_decoded_andMatrixOutputs_andMatrixInput_13_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_29 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_19, decoder_decoded_andMatrixOutputs_andMatrixInput_14_5}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_11 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_21, decoder_decoded_andMatrixOutputs_andMatrixInput_11_19}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_23 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_27, decoder_decoded_andMatrixOutputs_andMatrixInput_9_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_31 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_23, decoder_decoded_andMatrixOutputs_lo_hi_lo_11}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_32 = {decoder_decoded_andMatrixOutputs_lo_hi_31, decoder_decoded_andMatrixOutputs_lo_lo_29}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_5 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_31, decoder_decoded_andMatrixOutputs_andMatrixInput_7_29}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_21 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_32, decoder_decoded_andMatrixOutputs_andMatrixInput_5_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_31 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_21, decoder_decoded_andMatrixOutputs_hi_lo_lo_5}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_13 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_32, decoder_decoded_andMatrixOutputs_andMatrixInput_3_32}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_27 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_32, decoder_decoded_andMatrixOutputs_andMatrixInput_1_32}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_32 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_27, decoder_decoded_andMatrixOutputs_hi_hi_lo_13}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_32 = {decoder_decoded_andMatrixOutputs_hi_hi_32, decoder_decoded_andMatrixOutputs_hi_lo_31}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_32 = {decoder_decoded_andMatrixOutputs_hi_32, decoder_decoded_andMatrixOutputs_lo_32}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_38_2 = &_decoder_decoded_andMatrixOutputs_T_32; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_20 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_14, decoder_decoded_andMatrixOutputs_andMatrixInput_13_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_30 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_20, decoder_decoded_andMatrixOutputs_andMatrixInput_14_6}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_12 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_22, decoder_decoded_andMatrixOutputs_andMatrixInput_11_20}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_24 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_28, decoder_decoded_andMatrixOutputs_andMatrixInput_9_24}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_32 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_24, decoder_decoded_andMatrixOutputs_lo_hi_lo_12}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_33 = {decoder_decoded_andMatrixOutputs_lo_hi_32, decoder_decoded_andMatrixOutputs_lo_lo_30}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_6 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_32, decoder_decoded_andMatrixOutputs_andMatrixInput_7_30}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_22 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_33, decoder_decoded_andMatrixOutputs_andMatrixInput_5_32}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_32 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_22, decoder_decoded_andMatrixOutputs_hi_lo_lo_6}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_14 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_33, decoder_decoded_andMatrixOutputs_andMatrixInput_3_33}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_28 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_33, decoder_decoded_andMatrixOutputs_andMatrixInput_1_33}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_33 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_28, decoder_decoded_andMatrixOutputs_hi_hi_lo_14}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_33 = {decoder_decoded_andMatrixOutputs_hi_hi_33, decoder_decoded_andMatrixOutputs_hi_lo_32}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_33 = {decoder_decoded_andMatrixOutputs_hi_33, decoder_decoded_andMatrixOutputs_lo_33}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_10_2 = &_decoder_decoded_andMatrixOutputs_T_33; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_21 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_15, decoder_decoded_andMatrixOutputs_andMatrixInput_13_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_31 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_21, decoder_decoded_andMatrixOutputs_andMatrixInput_14_7}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_13 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_23, decoder_decoded_andMatrixOutputs_andMatrixInput_11_21}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_25 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_29, decoder_decoded_andMatrixOutputs_andMatrixInput_9_25}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_33 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_25, decoder_decoded_andMatrixOutputs_lo_hi_lo_13}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_34 = {decoder_decoded_andMatrixOutputs_lo_hi_33, decoder_decoded_andMatrixOutputs_lo_lo_31}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_7 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_33, decoder_decoded_andMatrixOutputs_andMatrixInput_7_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_23 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_34, decoder_decoded_andMatrixOutputs_andMatrixInput_5_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_33 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_23, decoder_decoded_andMatrixOutputs_hi_lo_lo_7}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_15 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_34, decoder_decoded_andMatrixOutputs_andMatrixInput_3_34}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_29 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_34, decoder_decoded_andMatrixOutputs_andMatrixInput_1_34}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_34 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_29, decoder_decoded_andMatrixOutputs_hi_hi_lo_15}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_34 = {decoder_decoded_andMatrixOutputs_hi_hi_34, decoder_decoded_andMatrixOutputs_hi_lo_33}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_34 = {decoder_decoded_andMatrixOutputs_hi_34, decoder_decoded_andMatrixOutputs_lo_34}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_40_2 = &_decoder_decoded_andMatrixOutputs_T_34; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_22 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_16, decoder_decoded_andMatrixOutputs_andMatrixInput_13_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_32 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_22, decoder_decoded_andMatrixOutputs_andMatrixInput_14_8}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_14 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_24, decoder_decoded_andMatrixOutputs_andMatrixInput_11_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_26 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_30, decoder_decoded_andMatrixOutputs_andMatrixInput_9_26}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_34 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_26, decoder_decoded_andMatrixOutputs_lo_hi_lo_14}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_35 = {decoder_decoded_andMatrixOutputs_lo_hi_34, decoder_decoded_andMatrixOutputs_lo_lo_32}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_8 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_34, decoder_decoded_andMatrixOutputs_andMatrixInput_7_32}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_24 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_35, decoder_decoded_andMatrixOutputs_andMatrixInput_5_34}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_34 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_24, decoder_decoded_andMatrixOutputs_hi_lo_lo_8}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_16 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_35, decoder_decoded_andMatrixOutputs_andMatrixInput_3_35}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_30 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_35, decoder_decoded_andMatrixOutputs_andMatrixInput_1_35}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_35 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_30, decoder_decoded_andMatrixOutputs_hi_hi_lo_16}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_35 = {decoder_decoded_andMatrixOutputs_hi_hi_35, decoder_decoded_andMatrixOutputs_hi_lo_34}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_35 = {decoder_decoded_andMatrixOutputs_hi_35, decoder_decoded_andMatrixOutputs_lo_35}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_33_2 = &_decoder_decoded_andMatrixOutputs_T_35; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_23 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_17, decoder_decoded_andMatrixOutputs_andMatrixInput_13_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_33 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_23, decoder_decoded_andMatrixOutputs_andMatrixInput_14_9}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_15 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_25, decoder_decoded_andMatrixOutputs_andMatrixInput_11_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_27 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_31, decoder_decoded_andMatrixOutputs_andMatrixInput_9_27}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_35 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_27, decoder_decoded_andMatrixOutputs_lo_hi_lo_15}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_36 = {decoder_decoded_andMatrixOutputs_lo_hi_35, decoder_decoded_andMatrixOutputs_lo_lo_33}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_9 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_35, decoder_decoded_andMatrixOutputs_andMatrixInput_7_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_25 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_36, decoder_decoded_andMatrixOutputs_andMatrixInput_5_35}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_35 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_25, decoder_decoded_andMatrixOutputs_hi_lo_lo_9}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_17 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_36, decoder_decoded_andMatrixOutputs_andMatrixInput_3_36}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_31 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_36, decoder_decoded_andMatrixOutputs_andMatrixInput_1_36}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_36 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_31, decoder_decoded_andMatrixOutputs_hi_hi_lo_17}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_36 = {decoder_decoded_andMatrixOutputs_hi_hi_36, decoder_decoded_andMatrixOutputs_hi_lo_35}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_36 = {decoder_decoded_andMatrixOutputs_hi_36, decoder_decoded_andMatrixOutputs_lo_36}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_67_2 = &_decoder_decoded_andMatrixOutputs_T_36; // @[pla.scala:98:{53,70}] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_34 = decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_35 = decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_36 = decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_32 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_33 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_34 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_40 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_43 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_44 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_43 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_44 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_45 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_46 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_47 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_56 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_55 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_58 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_59 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_58 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_59 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_62 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_61 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_62 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_63 = decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_28 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_29 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_30 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_31 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_32 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_33 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_38 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_39 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_36 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_41 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_42 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_39 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_40 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_41 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_42 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_43 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_54 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_55 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_56 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_57 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_58 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_59 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_60 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_61 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_62 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_63 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_54 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_49 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_56 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_57 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_52 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_53 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_60 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_55 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_56 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_57 = decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_26 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_27 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_28 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_29 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_30 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_31 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_34 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_35 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_34 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_37 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_38 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_37 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_38 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_39 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_40 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_41 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_52 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_53 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_54 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_55 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_56 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_57 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_58 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_59 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_60 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_61 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_48 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_47 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_50 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_51 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_50 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_51 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_54 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_53 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_54 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_55 = decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_24 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_25 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_26 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_27 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_28 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_29 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_32 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_33 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_32 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_35 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_36 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_35 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_36 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_37 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_38 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_11_39 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_48 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_49 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_50 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_51 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_52 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_53 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_54 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_55 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_56 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_57 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_46 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_41 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_48 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_49 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_44 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_45 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_52 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_47 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_48 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_49 = decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_1 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_1 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_3 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_4 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_3 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_6 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_7 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_5 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_9 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_10 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_7 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_12 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_13 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_10 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_17_11 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_36 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_37 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_32 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_33 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_34 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_35 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_36 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_37 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_22 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_23 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_6 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_19_1 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_18_8 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_19_3 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_20_2 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_19_5 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_19_6 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_19_7 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_19_8 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_20_7 = decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo = {decoder_decoded_andMatrixOutputs_andMatrixInput_15, decoder_decoded_andMatrixOutputs_andMatrixInput_16}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_24 = {decoder_decoded_andMatrixOutputs_andMatrixInput_13_16, decoder_decoded_andMatrixOutputs_andMatrixInput_14_10}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_34 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_24, decoder_decoded_andMatrixOutputs_lo_lo_lo}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_16 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_24, decoder_decoded_andMatrixOutputs_andMatrixInput_12_18}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_28 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_28, decoder_decoded_andMatrixOutputs_andMatrixInput_10_26}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_36 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_28, decoder_decoded_andMatrixOutputs_lo_hi_lo_16}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_37 = {decoder_decoded_andMatrixOutputs_lo_hi_36, decoder_decoded_andMatrixOutputs_lo_lo_34}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_10 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_34, decoder_decoded_andMatrixOutputs_andMatrixInput_8_32}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_26 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_36, decoder_decoded_andMatrixOutputs_andMatrixInput_6_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_36 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_26, decoder_decoded_andMatrixOutputs_hi_lo_lo_10}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_18 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_37, decoder_decoded_andMatrixOutputs_andMatrixInput_4_37}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_37, decoder_decoded_andMatrixOutputs_andMatrixInput_1_37}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_32 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi, decoder_decoded_andMatrixOutputs_andMatrixInput_2_37}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_37 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_32, decoder_decoded_andMatrixOutputs_hi_hi_lo_18}; // @[pla.scala:98:53] wire [8:0] decoder_decoded_andMatrixOutputs_hi_37 = {decoder_decoded_andMatrixOutputs_hi_hi_37, decoder_decoded_andMatrixOutputs_hi_lo_36}; // @[pla.scala:98:53] wire [16:0] _decoder_decoded_andMatrixOutputs_T_37 = {decoder_decoded_andMatrixOutputs_hi_37, decoder_decoded_andMatrixOutputs_lo_37}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_59_2 = &_decoder_decoded_andMatrixOutputs_T_37; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_16_1, decoder_decoded_andMatrixOutputs_andMatrixInput_17}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_25 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_11, decoder_decoded_andMatrixOutputs_andMatrixInput_15_1}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_35 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_25, decoder_decoded_andMatrixOutputs_lo_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_17 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_19, decoder_decoded_andMatrixOutputs_andMatrixInput_13_17}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_29, decoder_decoded_andMatrixOutputs_andMatrixInput_10_27}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_29 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi, decoder_decoded_andMatrixOutputs_andMatrixInput_11_25}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_37 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_29, decoder_decoded_andMatrixOutputs_lo_hi_lo_17}; // @[pla.scala:98:53] wire [8:0] decoder_decoded_andMatrixOutputs_lo_38 = {decoder_decoded_andMatrixOutputs_lo_hi_37, decoder_decoded_andMatrixOutputs_lo_lo_35}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_11 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_35, decoder_decoded_andMatrixOutputs_andMatrixInput_8_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_27 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_37, decoder_decoded_andMatrixOutputs_andMatrixInput_6_37}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_37 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_27, decoder_decoded_andMatrixOutputs_hi_lo_lo_11}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_19 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_38, decoder_decoded_andMatrixOutputs_andMatrixInput_4_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_38, decoder_decoded_andMatrixOutputs_andMatrixInput_1_38}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_33 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_1, decoder_decoded_andMatrixOutputs_andMatrixInput_2_38}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_38 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_33, decoder_decoded_andMatrixOutputs_hi_hi_lo_19}; // @[pla.scala:98:53] wire [8:0] decoder_decoded_andMatrixOutputs_hi_38 = {decoder_decoded_andMatrixOutputs_hi_hi_38, decoder_decoded_andMatrixOutputs_hi_lo_37}; // @[pla.scala:98:53] wire [17:0] _decoder_decoded_andMatrixOutputs_T_38 = {decoder_decoded_andMatrixOutputs_hi_38, decoder_decoded_andMatrixOutputs_lo_38}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_5_2 = &_decoder_decoded_andMatrixOutputs_T_38; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_2 = {decoder_decoded_andMatrixOutputs_andMatrixInput_17_1, decoder_decoded_andMatrixOutputs_andMatrixInput_18}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_26 = {decoder_decoded_andMatrixOutputs_andMatrixInput_15_2, decoder_decoded_andMatrixOutputs_andMatrixInput_16_2}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_36 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_26, decoder_decoded_andMatrixOutputs_lo_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_18 = {decoder_decoded_andMatrixOutputs_andMatrixInput_13_18, decoder_decoded_andMatrixOutputs_andMatrixInput_14_12}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_28, decoder_decoded_andMatrixOutputs_andMatrixInput_11_26}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_30 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_1, decoder_decoded_andMatrixOutputs_andMatrixInput_12_20}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_38 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_30, decoder_decoded_andMatrixOutputs_lo_hi_lo_18}; // @[pla.scala:98:53] wire [8:0] decoder_decoded_andMatrixOutputs_lo_39 = {decoder_decoded_andMatrixOutputs_lo_hi_38, decoder_decoded_andMatrixOutputs_lo_lo_36}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_12 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_34, decoder_decoded_andMatrixOutputs_andMatrixInput_9_30}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_38, decoder_decoded_andMatrixOutputs_andMatrixInput_6_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_28 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi, decoder_decoded_andMatrixOutputs_andMatrixInput_7_36}; // @[pla.scala:90:45, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_lo_38 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_28, decoder_decoded_andMatrixOutputs_hi_lo_lo_12}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_20 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_39, decoder_decoded_andMatrixOutputs_andMatrixInput_4_39}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_2 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_39, decoder_decoded_andMatrixOutputs_andMatrixInput_1_39}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_34 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_2, decoder_decoded_andMatrixOutputs_andMatrixInput_2_39}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_39 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_34, decoder_decoded_andMatrixOutputs_hi_hi_lo_20}; // @[pla.scala:98:53] wire [9:0] decoder_decoded_andMatrixOutputs_hi_39 = {decoder_decoded_andMatrixOutputs_hi_hi_39, decoder_decoded_andMatrixOutputs_hi_lo_38}; // @[pla.scala:98:53] wire [18:0] _decoder_decoded_andMatrixOutputs_T_39 = {decoder_decoded_andMatrixOutputs_hi_39, decoder_decoded_andMatrixOutputs_lo_39}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_1_2 = &_decoder_decoded_andMatrixOutputs_T_39; // @[pla.scala:98:{53,70}] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_37 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_38 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_39 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_40 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_41 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_42 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_45 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_46 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_47 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_48 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_7_49 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_58 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_57 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_60 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_61 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_60 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_61 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_9_64 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_63 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_64 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_10_65 = decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_35 = decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_36 = decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_8_37 = decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_3 = {decoder_decoded_andMatrixOutputs_andMatrixInput_15_3, decoder_decoded_andMatrixOutputs_andMatrixInput_16_3}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_27 = {decoder_decoded_andMatrixOutputs_andMatrixInput_13_19, decoder_decoded_andMatrixOutputs_andMatrixInput_14_13}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_37 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_27, decoder_decoded_andMatrixOutputs_lo_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_19 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_27, decoder_decoded_andMatrixOutputs_andMatrixInput_12_21}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_31 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_31, decoder_decoded_andMatrixOutputs_andMatrixInput_10_29}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_39 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_31, decoder_decoded_andMatrixOutputs_lo_hi_lo_19}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_40 = {decoder_decoded_andMatrixOutputs_lo_hi_39, decoder_decoded_andMatrixOutputs_lo_lo_37}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_13 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_37, decoder_decoded_andMatrixOutputs_andMatrixInput_8_35}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_29 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_39, decoder_decoded_andMatrixOutputs_andMatrixInput_6_39}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_39 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_29, decoder_decoded_andMatrixOutputs_hi_lo_lo_13}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_21 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_40, decoder_decoded_andMatrixOutputs_andMatrixInput_4_40}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_3 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_40, decoder_decoded_andMatrixOutputs_andMatrixInput_1_40}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_35 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_3, decoder_decoded_andMatrixOutputs_andMatrixInput_2_40}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_40 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_35, decoder_decoded_andMatrixOutputs_hi_hi_lo_21}; // @[pla.scala:98:53] wire [8:0] decoder_decoded_andMatrixOutputs_hi_40 = {decoder_decoded_andMatrixOutputs_hi_hi_40, decoder_decoded_andMatrixOutputs_hi_lo_39}; // @[pla.scala:98:53] wire [16:0] _decoder_decoded_andMatrixOutputs_T_40 = {decoder_decoded_andMatrixOutputs_hi_40, decoder_decoded_andMatrixOutputs_lo_40}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_3_2 = &_decoder_decoded_andMatrixOutputs_T_40; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_4 = {decoder_decoded_andMatrixOutputs_andMatrixInput_16_4, decoder_decoded_andMatrixOutputs_andMatrixInput_17_2}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_28 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_14, decoder_decoded_andMatrixOutputs_andMatrixInput_15_4}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_38 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_28, decoder_decoded_andMatrixOutputs_lo_lo_lo_4}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_20 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_22, decoder_decoded_andMatrixOutputs_andMatrixInput_13_20}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_2 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_32, decoder_decoded_andMatrixOutputs_andMatrixInput_10_30}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_32 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_2, decoder_decoded_andMatrixOutputs_andMatrixInput_11_28}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_40 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_32, decoder_decoded_andMatrixOutputs_lo_hi_lo_20}; // @[pla.scala:98:53] wire [8:0] decoder_decoded_andMatrixOutputs_lo_41 = {decoder_decoded_andMatrixOutputs_lo_hi_40, decoder_decoded_andMatrixOutputs_lo_lo_38}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_14 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_38, decoder_decoded_andMatrixOutputs_andMatrixInput_8_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_30 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_40, decoder_decoded_andMatrixOutputs_andMatrixInput_6_40}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_40 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_30, decoder_decoded_andMatrixOutputs_hi_lo_lo_14}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_22 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_41, decoder_decoded_andMatrixOutputs_andMatrixInput_4_41}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_4 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_41, decoder_decoded_andMatrixOutputs_andMatrixInput_1_41}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_36 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_4, decoder_decoded_andMatrixOutputs_andMatrixInput_2_41}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_41 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_36, decoder_decoded_andMatrixOutputs_hi_hi_lo_22}; // @[pla.scala:98:53] wire [8:0] decoder_decoded_andMatrixOutputs_hi_41 = {decoder_decoded_andMatrixOutputs_hi_hi_41, decoder_decoded_andMatrixOutputs_hi_lo_40}; // @[pla.scala:98:53] wire [17:0] _decoder_decoded_andMatrixOutputs_T_41 = {decoder_decoded_andMatrixOutputs_hi_41, decoder_decoded_andMatrixOutputs_lo_41}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_27_2 = &_decoder_decoded_andMatrixOutputs_T_41; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_5 = {decoder_decoded_andMatrixOutputs_andMatrixInput_17_3, decoder_decoded_andMatrixOutputs_andMatrixInput_18_1}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_29 = {decoder_decoded_andMatrixOutputs_andMatrixInput_15_5, decoder_decoded_andMatrixOutputs_andMatrixInput_16_5}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_39 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_29, decoder_decoded_andMatrixOutputs_lo_lo_lo_5}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_21 = {decoder_decoded_andMatrixOutputs_andMatrixInput_13_21, decoder_decoded_andMatrixOutputs_andMatrixInput_14_15}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_3 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_31, decoder_decoded_andMatrixOutputs_andMatrixInput_11_29}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_33 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_3, decoder_decoded_andMatrixOutputs_andMatrixInput_12_23}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_41 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_33, decoder_decoded_andMatrixOutputs_lo_hi_lo_21}; // @[pla.scala:98:53] wire [8:0] decoder_decoded_andMatrixOutputs_lo_42 = {decoder_decoded_andMatrixOutputs_lo_hi_41, decoder_decoded_andMatrixOutputs_lo_lo_39}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_15 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_37, decoder_decoded_andMatrixOutputs_andMatrixInput_9_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_41, decoder_decoded_andMatrixOutputs_andMatrixInput_6_41}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_31 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_1, decoder_decoded_andMatrixOutputs_andMatrixInput_7_39}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_lo_41 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_31, decoder_decoded_andMatrixOutputs_hi_lo_lo_15}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_23 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_42, decoder_decoded_andMatrixOutputs_andMatrixInput_4_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_5 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_42, decoder_decoded_andMatrixOutputs_andMatrixInput_1_42}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_37 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_5, decoder_decoded_andMatrixOutputs_andMatrixInput_2_42}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_42 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_37, decoder_decoded_andMatrixOutputs_hi_hi_lo_23}; // @[pla.scala:98:53] wire [9:0] decoder_decoded_andMatrixOutputs_hi_42 = {decoder_decoded_andMatrixOutputs_hi_hi_42, decoder_decoded_andMatrixOutputs_hi_lo_41}; // @[pla.scala:98:53] wire [18:0] _decoder_decoded_andMatrixOutputs_T_42 = {decoder_decoded_andMatrixOutputs_hi_42, decoder_decoded_andMatrixOutputs_lo_42}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_53_2 = &_decoder_decoded_andMatrixOutputs_T_42; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_6 = {decoder_decoded_andMatrixOutputs_andMatrixInput_15_6, decoder_decoded_andMatrixOutputs_andMatrixInput_16_6}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_30 = {decoder_decoded_andMatrixOutputs_andMatrixInput_13_22, decoder_decoded_andMatrixOutputs_andMatrixInput_14_16}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_40 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_30, decoder_decoded_andMatrixOutputs_lo_lo_lo_6}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_22 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_30, decoder_decoded_andMatrixOutputs_andMatrixInput_12_24}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_34 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_34, decoder_decoded_andMatrixOutputs_andMatrixInput_10_32}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_42 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_34, decoder_decoded_andMatrixOutputs_lo_hi_lo_22}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_43 = {decoder_decoded_andMatrixOutputs_lo_hi_42, decoder_decoded_andMatrixOutputs_lo_lo_40}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_16 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_40, decoder_decoded_andMatrixOutputs_andMatrixInput_8_38}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_32 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_42, decoder_decoded_andMatrixOutputs_andMatrixInput_6_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_42 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_32, decoder_decoded_andMatrixOutputs_hi_lo_lo_16}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_24 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_43, decoder_decoded_andMatrixOutputs_andMatrixInput_4_43}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_6 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_43, decoder_decoded_andMatrixOutputs_andMatrixInput_1_43}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_38 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_6, decoder_decoded_andMatrixOutputs_andMatrixInput_2_43}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_43 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_38, decoder_decoded_andMatrixOutputs_hi_hi_lo_24}; // @[pla.scala:98:53] wire [8:0] decoder_decoded_andMatrixOutputs_hi_43 = {decoder_decoded_andMatrixOutputs_hi_hi_43, decoder_decoded_andMatrixOutputs_hi_lo_42}; // @[pla.scala:98:53] wire [16:0] _decoder_decoded_andMatrixOutputs_T_43 = {decoder_decoded_andMatrixOutputs_hi_43, decoder_decoded_andMatrixOutputs_lo_43}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_70_2 = &_decoder_decoded_andMatrixOutputs_T_43; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_7 = {decoder_decoded_andMatrixOutputs_andMatrixInput_16_7, decoder_decoded_andMatrixOutputs_andMatrixInput_17_4}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_31 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_17, decoder_decoded_andMatrixOutputs_andMatrixInput_15_7}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_41 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_31, decoder_decoded_andMatrixOutputs_lo_lo_lo_7}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_23 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_25, decoder_decoded_andMatrixOutputs_andMatrixInput_13_23}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_4 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_35, decoder_decoded_andMatrixOutputs_andMatrixInput_10_33}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_35 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_4, decoder_decoded_andMatrixOutputs_andMatrixInput_11_31}; // @[pla.scala:90:45, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_43 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_35, decoder_decoded_andMatrixOutputs_lo_hi_lo_23}; // @[pla.scala:98:53] wire [8:0] decoder_decoded_andMatrixOutputs_lo_44 = {decoder_decoded_andMatrixOutputs_lo_hi_43, decoder_decoded_andMatrixOutputs_lo_lo_41}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_17 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_41, decoder_decoded_andMatrixOutputs_andMatrixInput_8_39}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_33 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_43, decoder_decoded_andMatrixOutputs_andMatrixInput_6_43}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_43 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_33, decoder_decoded_andMatrixOutputs_hi_lo_lo_17}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_25 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_44, decoder_decoded_andMatrixOutputs_andMatrixInput_4_44}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_7 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_44, decoder_decoded_andMatrixOutputs_andMatrixInput_1_44}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_39 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_7, decoder_decoded_andMatrixOutputs_andMatrixInput_2_44}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_44 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_39, decoder_decoded_andMatrixOutputs_hi_hi_lo_25}; // @[pla.scala:98:53] wire [8:0] decoder_decoded_andMatrixOutputs_hi_44 = {decoder_decoded_andMatrixOutputs_hi_hi_44, decoder_decoded_andMatrixOutputs_hi_lo_43}; // @[pla.scala:98:53] wire [17:0] _decoder_decoded_andMatrixOutputs_T_44 = {decoder_decoded_andMatrixOutputs_hi_44, decoder_decoded_andMatrixOutputs_lo_44}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_32_2 = &_decoder_decoded_andMatrixOutputs_T_44; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_8 = {decoder_decoded_andMatrixOutputs_andMatrixInput_17_5, decoder_decoded_andMatrixOutputs_andMatrixInput_18_2}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_32 = {decoder_decoded_andMatrixOutputs_andMatrixInput_15_8, decoder_decoded_andMatrixOutputs_andMatrixInput_16_8}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_42 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_32, decoder_decoded_andMatrixOutputs_lo_lo_lo_8}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_24 = {decoder_decoded_andMatrixOutputs_andMatrixInput_13_24, decoder_decoded_andMatrixOutputs_andMatrixInput_14_18}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_5 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_34, decoder_decoded_andMatrixOutputs_andMatrixInput_11_32}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_36 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_5, decoder_decoded_andMatrixOutputs_andMatrixInput_12_26}; // @[pla.scala:90:45, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_44 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_36, decoder_decoded_andMatrixOutputs_lo_hi_lo_24}; // @[pla.scala:98:53] wire [8:0] decoder_decoded_andMatrixOutputs_lo_45 = {decoder_decoded_andMatrixOutputs_lo_hi_44, decoder_decoded_andMatrixOutputs_lo_lo_42}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_18 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_40, decoder_decoded_andMatrixOutputs_andMatrixInput_9_36}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_2 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_44, decoder_decoded_andMatrixOutputs_andMatrixInput_6_44}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_34 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_2, decoder_decoded_andMatrixOutputs_andMatrixInput_7_42}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_lo_44 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_34, decoder_decoded_andMatrixOutputs_hi_lo_lo_18}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_26 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_45, decoder_decoded_andMatrixOutputs_andMatrixInput_4_45}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_8 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_45, decoder_decoded_andMatrixOutputs_andMatrixInput_1_45}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_40 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_8, decoder_decoded_andMatrixOutputs_andMatrixInput_2_45}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_45 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_40, decoder_decoded_andMatrixOutputs_hi_hi_lo_26}; // @[pla.scala:98:53] wire [9:0] decoder_decoded_andMatrixOutputs_hi_45 = {decoder_decoded_andMatrixOutputs_hi_hi_45, decoder_decoded_andMatrixOutputs_hi_lo_44}; // @[pla.scala:98:53] wire [18:0] _decoder_decoded_andMatrixOutputs_T_45 = {decoder_decoded_andMatrixOutputs_hi_45, decoder_decoded_andMatrixOutputs_lo_45}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_13_2 = &_decoder_decoded_andMatrixOutputs_T_45; // @[pla.scala:98:{53,70}] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_27 = decoder_decoded_plaInput[26]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_12_28 = decoder_decoded_plaInput[26]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_13_27 = decoder_decoded_plaInput[26]; // @[pla.scala:77:22, :90:45] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_9 = {decoder_decoded_andMatrixOutputs_andMatrixInput_15_9, decoder_decoded_andMatrixOutputs_andMatrixInput_16_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_33 = {decoder_decoded_andMatrixOutputs_andMatrixInput_13_25, decoder_decoded_andMatrixOutputs_andMatrixInput_14_19}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_43 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_33, decoder_decoded_andMatrixOutputs_lo_lo_lo_9}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_25 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_33, decoder_decoded_andMatrixOutputs_andMatrixInput_12_27}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_37 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_37, decoder_decoded_andMatrixOutputs_andMatrixInput_10_35}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_45 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_37, decoder_decoded_andMatrixOutputs_lo_hi_lo_25}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_46 = {decoder_decoded_andMatrixOutputs_lo_hi_45, decoder_decoded_andMatrixOutputs_lo_lo_43}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_19 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_43, decoder_decoded_andMatrixOutputs_andMatrixInput_8_41}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_35 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_45, decoder_decoded_andMatrixOutputs_andMatrixInput_6_45}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_45 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_35, decoder_decoded_andMatrixOutputs_hi_lo_lo_19}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_27 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_46, decoder_decoded_andMatrixOutputs_andMatrixInput_4_46}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_9 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_46, decoder_decoded_andMatrixOutputs_andMatrixInput_1_46}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_41 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_9, decoder_decoded_andMatrixOutputs_andMatrixInput_2_46}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_46 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_41, decoder_decoded_andMatrixOutputs_hi_hi_lo_27}; // @[pla.scala:98:53] wire [8:0] decoder_decoded_andMatrixOutputs_hi_46 = {decoder_decoded_andMatrixOutputs_hi_hi_46, decoder_decoded_andMatrixOutputs_hi_lo_45}; // @[pla.scala:98:53] wire [16:0] _decoder_decoded_andMatrixOutputs_T_46 = {decoder_decoded_andMatrixOutputs_hi_46, decoder_decoded_andMatrixOutputs_lo_46}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_52_2 = &_decoder_decoded_andMatrixOutputs_T_46; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_10 = {decoder_decoded_andMatrixOutputs_andMatrixInput_16_10, decoder_decoded_andMatrixOutputs_andMatrixInput_17_6}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_34 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_20, decoder_decoded_andMatrixOutputs_andMatrixInput_15_10}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_44 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_34, decoder_decoded_andMatrixOutputs_lo_lo_lo_10}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_26 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_28, decoder_decoded_andMatrixOutputs_andMatrixInput_13_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_6 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_38, decoder_decoded_andMatrixOutputs_andMatrixInput_10_36}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_38 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_6, decoder_decoded_andMatrixOutputs_andMatrixInput_11_34}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_46 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_38, decoder_decoded_andMatrixOutputs_lo_hi_lo_26}; // @[pla.scala:98:53] wire [8:0] decoder_decoded_andMatrixOutputs_lo_47 = {decoder_decoded_andMatrixOutputs_lo_hi_46, decoder_decoded_andMatrixOutputs_lo_lo_44}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_20 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_44, decoder_decoded_andMatrixOutputs_andMatrixInput_8_42}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_36 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_46, decoder_decoded_andMatrixOutputs_andMatrixInput_6_46}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_46 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_36, decoder_decoded_andMatrixOutputs_hi_lo_lo_20}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_28 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_47, decoder_decoded_andMatrixOutputs_andMatrixInput_4_47}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_10 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_47, decoder_decoded_andMatrixOutputs_andMatrixInput_1_47}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_42 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_10, decoder_decoded_andMatrixOutputs_andMatrixInput_2_47}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_47 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_42, decoder_decoded_andMatrixOutputs_hi_hi_lo_28}; // @[pla.scala:98:53] wire [8:0] decoder_decoded_andMatrixOutputs_hi_47 = {decoder_decoded_andMatrixOutputs_hi_hi_47, decoder_decoded_andMatrixOutputs_hi_lo_46}; // @[pla.scala:98:53] wire [17:0] _decoder_decoded_andMatrixOutputs_T_47 = {decoder_decoded_andMatrixOutputs_hi_47, decoder_decoded_andMatrixOutputs_lo_47}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_64_2 = &_decoder_decoded_andMatrixOutputs_T_47; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_11 = {decoder_decoded_andMatrixOutputs_andMatrixInput_17_7, decoder_decoded_andMatrixOutputs_andMatrixInput_18_3}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_35 = {decoder_decoded_andMatrixOutputs_andMatrixInput_15_11, decoder_decoded_andMatrixOutputs_andMatrixInput_16_11}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_45 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_35, decoder_decoded_andMatrixOutputs_lo_lo_lo_11}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_27 = {decoder_decoded_andMatrixOutputs_andMatrixInput_13_27, decoder_decoded_andMatrixOutputs_andMatrixInput_14_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_7 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_37, decoder_decoded_andMatrixOutputs_andMatrixInput_11_35}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_39 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_7, decoder_decoded_andMatrixOutputs_andMatrixInput_12_29}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_47 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_39, decoder_decoded_andMatrixOutputs_lo_hi_lo_27}; // @[pla.scala:98:53] wire [8:0] decoder_decoded_andMatrixOutputs_lo_48 = {decoder_decoded_andMatrixOutputs_lo_hi_47, decoder_decoded_andMatrixOutputs_lo_lo_45}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_21 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_43, decoder_decoded_andMatrixOutputs_andMatrixInput_9_39}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_3 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_47, decoder_decoded_andMatrixOutputs_andMatrixInput_6_47}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_37 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_3, decoder_decoded_andMatrixOutputs_andMatrixInput_7_45}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_lo_47 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_37, decoder_decoded_andMatrixOutputs_hi_lo_lo_21}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_29 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_48, decoder_decoded_andMatrixOutputs_andMatrixInput_4_48}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_11 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_48, decoder_decoded_andMatrixOutputs_andMatrixInput_1_48}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_43 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_11, decoder_decoded_andMatrixOutputs_andMatrixInput_2_48}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_48 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_43, decoder_decoded_andMatrixOutputs_hi_hi_lo_29}; // @[pla.scala:98:53] wire [9:0] decoder_decoded_andMatrixOutputs_hi_48 = {decoder_decoded_andMatrixOutputs_hi_hi_48, decoder_decoded_andMatrixOutputs_hi_lo_47}; // @[pla.scala:98:53] wire [18:0] _decoder_decoded_andMatrixOutputs_T_48 = {decoder_decoded_andMatrixOutputs_hi_48, decoder_decoded_andMatrixOutputs_lo_48}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_11_2 = &_decoder_decoded_andMatrixOutputs_T_48; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_12 = {decoder_decoded_andMatrixOutputs_andMatrixInput_16_12, decoder_decoded_andMatrixOutputs_andMatrixInput_17_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_36 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_22, decoder_decoded_andMatrixOutputs_andMatrixInput_15_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_46 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_36, decoder_decoded_andMatrixOutputs_lo_lo_lo_12}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_28 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_30, decoder_decoded_andMatrixOutputs_andMatrixInput_13_28}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_8 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_40, decoder_decoded_andMatrixOutputs_andMatrixInput_10_38}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_40 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_8, decoder_decoded_andMatrixOutputs_andMatrixInput_11_36}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_48 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_40, decoder_decoded_andMatrixOutputs_lo_hi_lo_28}; // @[pla.scala:98:53] wire [8:0] decoder_decoded_andMatrixOutputs_lo_49 = {decoder_decoded_andMatrixOutputs_lo_hi_48, decoder_decoded_andMatrixOutputs_lo_lo_46}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_22 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_46, decoder_decoded_andMatrixOutputs_andMatrixInput_8_44}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_38 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_48, decoder_decoded_andMatrixOutputs_andMatrixInput_6_48}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_48 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_38, decoder_decoded_andMatrixOutputs_hi_lo_lo_22}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_30 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_49, decoder_decoded_andMatrixOutputs_andMatrixInput_4_49}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_12 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_49, decoder_decoded_andMatrixOutputs_andMatrixInput_1_49}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_44 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_12, decoder_decoded_andMatrixOutputs_andMatrixInput_2_49}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_49 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_44, decoder_decoded_andMatrixOutputs_hi_hi_lo_30}; // @[pla.scala:98:53] wire [8:0] decoder_decoded_andMatrixOutputs_hi_49 = {decoder_decoded_andMatrixOutputs_hi_hi_49, decoder_decoded_andMatrixOutputs_hi_lo_48}; // @[pla.scala:98:53] wire [17:0] _decoder_decoded_andMatrixOutputs_T_49 = {decoder_decoded_andMatrixOutputs_hi_49, decoder_decoded_andMatrixOutputs_lo_49}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_26_2 = &_decoder_decoded_andMatrixOutputs_T_49; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_13 = {decoder_decoded_andMatrixOutputs_andMatrixInput_16_13, decoder_decoded_andMatrixOutputs_andMatrixInput_17_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_37 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_23, decoder_decoded_andMatrixOutputs_andMatrixInput_15_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_47 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_37, decoder_decoded_andMatrixOutputs_lo_lo_lo_13}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_29 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_31, decoder_decoded_andMatrixOutputs_andMatrixInput_13_29}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_9 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_41, decoder_decoded_andMatrixOutputs_andMatrixInput_10_39}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_41 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_9, decoder_decoded_andMatrixOutputs_andMatrixInput_11_37}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_49 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_41, decoder_decoded_andMatrixOutputs_lo_hi_lo_29}; // @[pla.scala:98:53] wire [8:0] decoder_decoded_andMatrixOutputs_lo_50 = {decoder_decoded_andMatrixOutputs_lo_hi_49, decoder_decoded_andMatrixOutputs_lo_lo_47}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_23 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_47, decoder_decoded_andMatrixOutputs_andMatrixInput_8_45}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_39 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_49, decoder_decoded_andMatrixOutputs_andMatrixInput_6_49}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_49 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_39, decoder_decoded_andMatrixOutputs_hi_lo_lo_23}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_31 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_50, decoder_decoded_andMatrixOutputs_andMatrixInput_4_50}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_13 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_50, decoder_decoded_andMatrixOutputs_andMatrixInput_1_50}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_45 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_13, decoder_decoded_andMatrixOutputs_andMatrixInput_2_50}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_50 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_45, decoder_decoded_andMatrixOutputs_hi_hi_lo_31}; // @[pla.scala:98:53] wire [8:0] decoder_decoded_andMatrixOutputs_hi_50 = {decoder_decoded_andMatrixOutputs_hi_hi_50, decoder_decoded_andMatrixOutputs_hi_lo_49}; // @[pla.scala:98:53] wire [17:0] _decoder_decoded_andMatrixOutputs_T_50 = {decoder_decoded_andMatrixOutputs_hi_50, decoder_decoded_andMatrixOutputs_lo_50}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_58_2 = &_decoder_decoded_andMatrixOutputs_T_50; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_14 = {decoder_decoded_andMatrixOutputs_andMatrixInput_17_10, decoder_decoded_andMatrixOutputs_andMatrixInput_18_4}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_38 = {decoder_decoded_andMatrixOutputs_andMatrixInput_15_14, decoder_decoded_andMatrixOutputs_andMatrixInput_16_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_48 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_38, decoder_decoded_andMatrixOutputs_lo_lo_lo_14}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_30 = {decoder_decoded_andMatrixOutputs_andMatrixInput_13_30, decoder_decoded_andMatrixOutputs_andMatrixInput_14_24}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_10 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_40, decoder_decoded_andMatrixOutputs_andMatrixInput_11_38}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_42 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_10, decoder_decoded_andMatrixOutputs_andMatrixInput_12_32}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_50 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_42, decoder_decoded_andMatrixOutputs_lo_hi_lo_30}; // @[pla.scala:98:53] wire [8:0] decoder_decoded_andMatrixOutputs_lo_51 = {decoder_decoded_andMatrixOutputs_lo_hi_50, decoder_decoded_andMatrixOutputs_lo_lo_48}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_24 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_46, decoder_decoded_andMatrixOutputs_andMatrixInput_9_42}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_4 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_50, decoder_decoded_andMatrixOutputs_andMatrixInput_6_50}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_40 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_4, decoder_decoded_andMatrixOutputs_andMatrixInput_7_48}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_lo_50 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_40, decoder_decoded_andMatrixOutputs_hi_lo_lo_24}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_32 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_51, decoder_decoded_andMatrixOutputs_andMatrixInput_4_51}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_14 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_51, decoder_decoded_andMatrixOutputs_andMatrixInput_1_51}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_46 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_14, decoder_decoded_andMatrixOutputs_andMatrixInput_2_51}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_51 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_46, decoder_decoded_andMatrixOutputs_hi_hi_lo_32}; // @[pla.scala:98:53] wire [9:0] decoder_decoded_andMatrixOutputs_hi_51 = {decoder_decoded_andMatrixOutputs_hi_hi_51, decoder_decoded_andMatrixOutputs_hi_lo_50}; // @[pla.scala:98:53] wire [18:0] _decoder_decoded_andMatrixOutputs_T_51 = {decoder_decoded_andMatrixOutputs_hi_51, decoder_decoded_andMatrixOutputs_lo_51}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_76_2 = &_decoder_decoded_andMatrixOutputs_T_51; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_15 = {decoder_decoded_andMatrixOutputs_andMatrixInput_17_11, decoder_decoded_andMatrixOutputs_andMatrixInput_18_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_39 = {decoder_decoded_andMatrixOutputs_andMatrixInput_15_15, decoder_decoded_andMatrixOutputs_andMatrixInput_16_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_49 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_39, decoder_decoded_andMatrixOutputs_lo_lo_lo_15}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_31 = {decoder_decoded_andMatrixOutputs_andMatrixInput_13_31, decoder_decoded_andMatrixOutputs_andMatrixInput_14_25}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_11 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_41, decoder_decoded_andMatrixOutputs_andMatrixInput_11_39}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_43 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_11, decoder_decoded_andMatrixOutputs_andMatrixInput_12_33}; // @[pla.scala:90:45, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_51 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_43, decoder_decoded_andMatrixOutputs_lo_hi_lo_31}; // @[pla.scala:98:53] wire [8:0] decoder_decoded_andMatrixOutputs_lo_52 = {decoder_decoded_andMatrixOutputs_lo_hi_51, decoder_decoded_andMatrixOutputs_lo_lo_49}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_25 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_47, decoder_decoded_andMatrixOutputs_andMatrixInput_9_43}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_5 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_51, decoder_decoded_andMatrixOutputs_andMatrixInput_6_51}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_41 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_5, decoder_decoded_andMatrixOutputs_andMatrixInput_7_49}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_lo_51 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_41, decoder_decoded_andMatrixOutputs_hi_lo_lo_25}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_33 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_52, decoder_decoded_andMatrixOutputs_andMatrixInput_4_52}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_15 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_52, decoder_decoded_andMatrixOutputs_andMatrixInput_1_52}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_47 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_15, decoder_decoded_andMatrixOutputs_andMatrixInput_2_52}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_52 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_47, decoder_decoded_andMatrixOutputs_hi_hi_lo_33}; // @[pla.scala:98:53] wire [9:0] decoder_decoded_andMatrixOutputs_hi_52 = {decoder_decoded_andMatrixOutputs_hi_hi_52, decoder_decoded_andMatrixOutputs_hi_lo_51}; // @[pla.scala:98:53] wire [18:0] _decoder_decoded_andMatrixOutputs_T_52 = {decoder_decoded_andMatrixOutputs_hi_52, decoder_decoded_andMatrixOutputs_lo_52}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_51_2 = &_decoder_decoded_andMatrixOutputs_T_52; // @[pla.scala:98:{53,70}] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_26 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_27 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_28 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_29 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_30 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_14_31 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_16 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_17 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_18 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_19 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_20 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_15_21 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_16 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_16_17 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_19 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_20 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_19_2 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_20_1 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_21 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_20_3 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_20_4 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_20_5 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_20_6 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire decoder_decoded_andMatrixOutputs_andMatrixInput_21_1 = decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_40 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_34, decoder_decoded_andMatrixOutputs_andMatrixInput_13_32}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_50 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_40, decoder_decoded_andMatrixOutputs_andMatrixInput_14_26}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_32 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_42, decoder_decoded_andMatrixOutputs_andMatrixInput_11_40}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_44 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_48, decoder_decoded_andMatrixOutputs_andMatrixInput_9_44}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_52 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_44, decoder_decoded_andMatrixOutputs_lo_hi_lo_32}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_53 = {decoder_decoded_andMatrixOutputs_lo_hi_52, decoder_decoded_andMatrixOutputs_lo_lo_50}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_26 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_52, decoder_decoded_andMatrixOutputs_andMatrixInput_7_50}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_42 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_53, decoder_decoded_andMatrixOutputs_andMatrixInput_5_52}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_52 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_42, decoder_decoded_andMatrixOutputs_hi_lo_lo_26}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_34 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_53, decoder_decoded_andMatrixOutputs_andMatrixInput_3_53}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_48 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_53, decoder_decoded_andMatrixOutputs_andMatrixInput_1_53}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_53 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_48, decoder_decoded_andMatrixOutputs_hi_hi_lo_34}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_53 = {decoder_decoded_andMatrixOutputs_hi_hi_53, decoder_decoded_andMatrixOutputs_hi_lo_52}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_53 = {decoder_decoded_andMatrixOutputs_hi_53, decoder_decoded_andMatrixOutputs_lo_53}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_2_2 = &_decoder_decoded_andMatrixOutputs_T_53; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_41 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_35, decoder_decoded_andMatrixOutputs_andMatrixInput_13_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_51 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_41, decoder_decoded_andMatrixOutputs_andMatrixInput_14_27}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_33 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_43, decoder_decoded_andMatrixOutputs_andMatrixInput_11_41}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_45 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_49, decoder_decoded_andMatrixOutputs_andMatrixInput_9_45}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_53 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_45, decoder_decoded_andMatrixOutputs_lo_hi_lo_33}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_54 = {decoder_decoded_andMatrixOutputs_lo_hi_53, decoder_decoded_andMatrixOutputs_lo_lo_51}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_27 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_53, decoder_decoded_andMatrixOutputs_andMatrixInput_7_51}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_43 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_54, decoder_decoded_andMatrixOutputs_andMatrixInput_5_53}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_53 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_43, decoder_decoded_andMatrixOutputs_hi_lo_lo_27}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_35 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_54, decoder_decoded_andMatrixOutputs_andMatrixInput_3_54}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_49 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_54, decoder_decoded_andMatrixOutputs_andMatrixInput_1_54}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_54 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_49, decoder_decoded_andMatrixOutputs_hi_hi_lo_35}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_54 = {decoder_decoded_andMatrixOutputs_hi_hi_54, decoder_decoded_andMatrixOutputs_hi_lo_53}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_54 = {decoder_decoded_andMatrixOutputs_hi_54, decoder_decoded_andMatrixOutputs_lo_54}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_31_2 = &_decoder_decoded_andMatrixOutputs_T_54; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_42 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_36, decoder_decoded_andMatrixOutputs_andMatrixInput_13_34}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_52 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_42, decoder_decoded_andMatrixOutputs_andMatrixInput_14_28}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_34 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_44, decoder_decoded_andMatrixOutputs_andMatrixInput_11_42}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_46 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_50, decoder_decoded_andMatrixOutputs_andMatrixInput_9_46}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_54 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_46, decoder_decoded_andMatrixOutputs_lo_hi_lo_34}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_55 = {decoder_decoded_andMatrixOutputs_lo_hi_54, decoder_decoded_andMatrixOutputs_lo_lo_52}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_28 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_54, decoder_decoded_andMatrixOutputs_andMatrixInput_7_52}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_44 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_55, decoder_decoded_andMatrixOutputs_andMatrixInput_5_54}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_54 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_44, decoder_decoded_andMatrixOutputs_hi_lo_lo_28}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_36 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_55, decoder_decoded_andMatrixOutputs_andMatrixInput_3_55}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_50 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_55, decoder_decoded_andMatrixOutputs_andMatrixInput_1_55}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_55 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_50, decoder_decoded_andMatrixOutputs_hi_hi_lo_36}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_55 = {decoder_decoded_andMatrixOutputs_hi_hi_55, decoder_decoded_andMatrixOutputs_hi_lo_54}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_55 = {decoder_decoded_andMatrixOutputs_hi_55, decoder_decoded_andMatrixOutputs_lo_55}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_68_2 = &_decoder_decoded_andMatrixOutputs_T_55; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_43 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_37, decoder_decoded_andMatrixOutputs_andMatrixInput_13_35}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_53 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_43, decoder_decoded_andMatrixOutputs_andMatrixInput_14_29}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_35 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_45, decoder_decoded_andMatrixOutputs_andMatrixInput_11_43}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_47 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_51, decoder_decoded_andMatrixOutputs_andMatrixInput_9_47}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_55 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_47, decoder_decoded_andMatrixOutputs_lo_hi_lo_35}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_56 = {decoder_decoded_andMatrixOutputs_lo_hi_55, decoder_decoded_andMatrixOutputs_lo_lo_53}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_29 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_55, decoder_decoded_andMatrixOutputs_andMatrixInput_7_53}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_45 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_56, decoder_decoded_andMatrixOutputs_andMatrixInput_5_55}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_55 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_45, decoder_decoded_andMatrixOutputs_hi_lo_lo_29}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_37 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_56, decoder_decoded_andMatrixOutputs_andMatrixInput_3_56}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_51 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_56, decoder_decoded_andMatrixOutputs_andMatrixInput_1_56}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_56 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_51, decoder_decoded_andMatrixOutputs_hi_hi_lo_37}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_56 = {decoder_decoded_andMatrixOutputs_hi_hi_56, decoder_decoded_andMatrixOutputs_hi_lo_55}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_56 = {decoder_decoded_andMatrixOutputs_hi_56, decoder_decoded_andMatrixOutputs_lo_56}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_62_2 = &_decoder_decoded_andMatrixOutputs_T_56; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_44 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_38, decoder_decoded_andMatrixOutputs_andMatrixInput_13_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_54 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_44, decoder_decoded_andMatrixOutputs_andMatrixInput_14_30}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_36 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_46, decoder_decoded_andMatrixOutputs_andMatrixInput_11_44}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_48 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_52, decoder_decoded_andMatrixOutputs_andMatrixInput_9_48}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_56 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_48, decoder_decoded_andMatrixOutputs_lo_hi_lo_36}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_57 = {decoder_decoded_andMatrixOutputs_lo_hi_56, decoder_decoded_andMatrixOutputs_lo_lo_54}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_30 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_56, decoder_decoded_andMatrixOutputs_andMatrixInput_7_54}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_46 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_57, decoder_decoded_andMatrixOutputs_andMatrixInput_5_56}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_56 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_46, decoder_decoded_andMatrixOutputs_hi_lo_lo_30}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_38 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_57, decoder_decoded_andMatrixOutputs_andMatrixInput_3_57}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_52 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_57, decoder_decoded_andMatrixOutputs_andMatrixInput_1_57}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_57 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_52, decoder_decoded_andMatrixOutputs_hi_hi_lo_38}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_57 = {decoder_decoded_andMatrixOutputs_hi_hi_57, decoder_decoded_andMatrixOutputs_hi_lo_56}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_57 = {decoder_decoded_andMatrixOutputs_hi_57, decoder_decoded_andMatrixOutputs_lo_57}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_65_2 = &_decoder_decoded_andMatrixOutputs_T_57; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_45 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_39, decoder_decoded_andMatrixOutputs_andMatrixInput_13_37}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_55 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_45, decoder_decoded_andMatrixOutputs_andMatrixInput_14_31}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_37 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_47, decoder_decoded_andMatrixOutputs_andMatrixInput_11_45}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_49 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_53, decoder_decoded_andMatrixOutputs_andMatrixInput_9_49}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_57 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_49, decoder_decoded_andMatrixOutputs_lo_hi_lo_37}; // @[pla.scala:98:53] wire [6:0] decoder_decoded_andMatrixOutputs_lo_58 = {decoder_decoded_andMatrixOutputs_lo_hi_57, decoder_decoded_andMatrixOutputs_lo_lo_55}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_31 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_57, decoder_decoded_andMatrixOutputs_andMatrixInput_7_55}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_47 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_58, decoder_decoded_andMatrixOutputs_andMatrixInput_5_57}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_57 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_47, decoder_decoded_andMatrixOutputs_hi_lo_lo_31}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_39 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_58, decoder_decoded_andMatrixOutputs_andMatrixInput_3_58}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_53 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_58, decoder_decoded_andMatrixOutputs_andMatrixInput_1_58}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_58 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_53, decoder_decoded_andMatrixOutputs_hi_hi_lo_39}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_58 = {decoder_decoded_andMatrixOutputs_hi_hi_58, decoder_decoded_andMatrixOutputs_hi_lo_57}; // @[pla.scala:98:53] wire [14:0] _decoder_decoded_andMatrixOutputs_T_58 = {decoder_decoded_andMatrixOutputs_hi_58, decoder_decoded_andMatrixOutputs_lo_58}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_45_2 = &_decoder_decoded_andMatrixOutputs_T_58; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_16 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_32, decoder_decoded_andMatrixOutputs_andMatrixInput_15_16}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_46 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_40, decoder_decoded_andMatrixOutputs_andMatrixInput_13_38}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_56 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_46, decoder_decoded_andMatrixOutputs_lo_lo_lo_16}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_38 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_48, decoder_decoded_andMatrixOutputs_andMatrixInput_11_46}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_50 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_54, decoder_decoded_andMatrixOutputs_andMatrixInput_9_50}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_58 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_50, decoder_decoded_andMatrixOutputs_lo_hi_lo_38}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_59 = {decoder_decoded_andMatrixOutputs_lo_hi_58, decoder_decoded_andMatrixOutputs_lo_lo_56}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_32 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_58, decoder_decoded_andMatrixOutputs_andMatrixInput_7_56}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_48 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_59, decoder_decoded_andMatrixOutputs_andMatrixInput_5_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_58 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_48, decoder_decoded_andMatrixOutputs_hi_lo_lo_32}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_40 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_59, decoder_decoded_andMatrixOutputs_andMatrixInput_3_59}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_54 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_59, decoder_decoded_andMatrixOutputs_andMatrixInput_1_59}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_59 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_54, decoder_decoded_andMatrixOutputs_hi_hi_lo_40}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_59 = {decoder_decoded_andMatrixOutputs_hi_hi_59, decoder_decoded_andMatrixOutputs_hi_lo_58}; // @[pla.scala:98:53] wire [15:0] _decoder_decoded_andMatrixOutputs_T_59 = {decoder_decoded_andMatrixOutputs_hi_59, decoder_decoded_andMatrixOutputs_lo_59}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_25_2 = &_decoder_decoded_andMatrixOutputs_T_59; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_17 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_33, decoder_decoded_andMatrixOutputs_andMatrixInput_15_17}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_47 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_41, decoder_decoded_andMatrixOutputs_andMatrixInput_13_39}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_57 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_47, decoder_decoded_andMatrixOutputs_lo_lo_lo_17}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_39 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_49, decoder_decoded_andMatrixOutputs_andMatrixInput_11_47}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_51 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_55, decoder_decoded_andMatrixOutputs_andMatrixInput_9_51}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_59 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_51, decoder_decoded_andMatrixOutputs_lo_hi_lo_39}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_60 = {decoder_decoded_andMatrixOutputs_lo_hi_59, decoder_decoded_andMatrixOutputs_lo_lo_57}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_33 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_59, decoder_decoded_andMatrixOutputs_andMatrixInput_7_57}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_49 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_60, decoder_decoded_andMatrixOutputs_andMatrixInput_5_59}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_59 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_49, decoder_decoded_andMatrixOutputs_hi_lo_lo_33}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_41 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_60, decoder_decoded_andMatrixOutputs_andMatrixInput_3_60}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_55 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_60, decoder_decoded_andMatrixOutputs_andMatrixInput_1_60}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_60 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_55, decoder_decoded_andMatrixOutputs_hi_hi_lo_41}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_60 = {decoder_decoded_andMatrixOutputs_hi_hi_60, decoder_decoded_andMatrixOutputs_hi_lo_59}; // @[pla.scala:98:53] wire [15:0] _decoder_decoded_andMatrixOutputs_T_60 = {decoder_decoded_andMatrixOutputs_hi_60, decoder_decoded_andMatrixOutputs_lo_60}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_0_2 = &_decoder_decoded_andMatrixOutputs_T_60; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_18 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_34, decoder_decoded_andMatrixOutputs_andMatrixInput_15_18}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_48 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_42, decoder_decoded_andMatrixOutputs_andMatrixInput_13_40}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_58 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_48, decoder_decoded_andMatrixOutputs_lo_lo_lo_18}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_40 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_50, decoder_decoded_andMatrixOutputs_andMatrixInput_11_48}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_52 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_56, decoder_decoded_andMatrixOutputs_andMatrixInput_9_52}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_60 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_52, decoder_decoded_andMatrixOutputs_lo_hi_lo_40}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_61 = {decoder_decoded_andMatrixOutputs_lo_hi_60, decoder_decoded_andMatrixOutputs_lo_lo_58}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_34 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_60, decoder_decoded_andMatrixOutputs_andMatrixInput_7_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_50 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_61, decoder_decoded_andMatrixOutputs_andMatrixInput_5_60}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_60 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_50, decoder_decoded_andMatrixOutputs_hi_lo_lo_34}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_42 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_61, decoder_decoded_andMatrixOutputs_andMatrixInput_3_61}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_56 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_61, decoder_decoded_andMatrixOutputs_andMatrixInput_1_61}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_61 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_56, decoder_decoded_andMatrixOutputs_hi_hi_lo_42}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_61 = {decoder_decoded_andMatrixOutputs_hi_hi_61, decoder_decoded_andMatrixOutputs_hi_lo_60}; // @[pla.scala:98:53] wire [15:0] _decoder_decoded_andMatrixOutputs_T_61 = {decoder_decoded_andMatrixOutputs_hi_61, decoder_decoded_andMatrixOutputs_lo_61}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_4_2 = &_decoder_decoded_andMatrixOutputs_T_61; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_19 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_35, decoder_decoded_andMatrixOutputs_andMatrixInput_15_19}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_49 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_43, decoder_decoded_andMatrixOutputs_andMatrixInput_13_41}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_59 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_49, decoder_decoded_andMatrixOutputs_lo_lo_lo_19}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_41 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_51, decoder_decoded_andMatrixOutputs_andMatrixInput_11_49}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_53 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_57, decoder_decoded_andMatrixOutputs_andMatrixInput_9_53}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_61 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_53, decoder_decoded_andMatrixOutputs_lo_hi_lo_41}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_62 = {decoder_decoded_andMatrixOutputs_lo_hi_61, decoder_decoded_andMatrixOutputs_lo_lo_59}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_35 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_61, decoder_decoded_andMatrixOutputs_andMatrixInput_7_59}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_51 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_62, decoder_decoded_andMatrixOutputs_andMatrixInput_5_61}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_61 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_51, decoder_decoded_andMatrixOutputs_hi_lo_lo_35}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_43 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_62, decoder_decoded_andMatrixOutputs_andMatrixInput_3_62}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_57 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_62, decoder_decoded_andMatrixOutputs_andMatrixInput_1_62}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_62 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_57, decoder_decoded_andMatrixOutputs_hi_hi_lo_43}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_62 = {decoder_decoded_andMatrixOutputs_hi_hi_62, decoder_decoded_andMatrixOutputs_hi_lo_61}; // @[pla.scala:98:53] wire [15:0] _decoder_decoded_andMatrixOutputs_T_62 = {decoder_decoded_andMatrixOutputs_hi_62, decoder_decoded_andMatrixOutputs_lo_62}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_48_2 = &_decoder_decoded_andMatrixOutputs_T_62; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_20 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_36, decoder_decoded_andMatrixOutputs_andMatrixInput_15_20}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_50 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_44, decoder_decoded_andMatrixOutputs_andMatrixInput_13_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_60 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_50, decoder_decoded_andMatrixOutputs_lo_lo_lo_20}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_42 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_52, decoder_decoded_andMatrixOutputs_andMatrixInput_11_50}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_54 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_58, decoder_decoded_andMatrixOutputs_andMatrixInput_9_54}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_62 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_54, decoder_decoded_andMatrixOutputs_lo_hi_lo_42}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_63 = {decoder_decoded_andMatrixOutputs_lo_hi_62, decoder_decoded_andMatrixOutputs_lo_lo_60}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_36 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_62, decoder_decoded_andMatrixOutputs_andMatrixInput_7_60}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_52 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_63, decoder_decoded_andMatrixOutputs_andMatrixInput_5_62}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_62 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_52, decoder_decoded_andMatrixOutputs_hi_lo_lo_36}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_44 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_63, decoder_decoded_andMatrixOutputs_andMatrixInput_3_63}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_58 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_63, decoder_decoded_andMatrixOutputs_andMatrixInput_1_63}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_63 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_58, decoder_decoded_andMatrixOutputs_hi_hi_lo_44}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_63 = {decoder_decoded_andMatrixOutputs_hi_hi_63, decoder_decoded_andMatrixOutputs_hi_lo_62}; // @[pla.scala:98:53] wire [15:0] _decoder_decoded_andMatrixOutputs_T_63 = {decoder_decoded_andMatrixOutputs_hi_63, decoder_decoded_andMatrixOutputs_lo_63}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_46_2 = &_decoder_decoded_andMatrixOutputs_T_63; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_21 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_37, decoder_decoded_andMatrixOutputs_andMatrixInput_15_21}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_51 = {decoder_decoded_andMatrixOutputs_andMatrixInput_12_45, decoder_decoded_andMatrixOutputs_andMatrixInput_13_43}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_61 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_51, decoder_decoded_andMatrixOutputs_lo_lo_lo_21}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_43 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_53, decoder_decoded_andMatrixOutputs_andMatrixInput_11_51}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_55 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_59, decoder_decoded_andMatrixOutputs_andMatrixInput_9_55}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_63 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_55, decoder_decoded_andMatrixOutputs_lo_hi_lo_43}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_64 = {decoder_decoded_andMatrixOutputs_lo_hi_63, decoder_decoded_andMatrixOutputs_lo_lo_61}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_37 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_63, decoder_decoded_andMatrixOutputs_andMatrixInput_7_61}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_53 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_64, decoder_decoded_andMatrixOutputs_andMatrixInput_5_63}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_63 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_53, decoder_decoded_andMatrixOutputs_hi_lo_lo_37}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_45 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_64, decoder_decoded_andMatrixOutputs_andMatrixInput_3_64}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_59 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_64, decoder_decoded_andMatrixOutputs_andMatrixInput_1_64}; // @[pla.scala:90:45, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_hi_64 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_59, decoder_decoded_andMatrixOutputs_hi_hi_lo_45}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_hi_64 = {decoder_decoded_andMatrixOutputs_hi_hi_64, decoder_decoded_andMatrixOutputs_hi_lo_63}; // @[pla.scala:98:53] wire [15:0] _decoder_decoded_andMatrixOutputs_T_64 = {decoder_decoded_andMatrixOutputs_hi_64, decoder_decoded_andMatrixOutputs_lo_64}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_63_2 = &_decoder_decoded_andMatrixOutputs_T_64; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_22 = {decoder_decoded_andMatrixOutputs_andMatrixInput_15_22, decoder_decoded_andMatrixOutputs_andMatrixInput_16_16}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_52 = {decoder_decoded_andMatrixOutputs_andMatrixInput_13_44, decoder_decoded_andMatrixOutputs_andMatrixInput_14_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_62 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_52, decoder_decoded_andMatrixOutputs_lo_lo_lo_22}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_44 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_52, decoder_decoded_andMatrixOutputs_andMatrixInput_12_46}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_56 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_56, decoder_decoded_andMatrixOutputs_andMatrixInput_10_54}; // @[pla.scala:91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_64 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_56, decoder_decoded_andMatrixOutputs_lo_hi_lo_44}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_65 = {decoder_decoded_andMatrixOutputs_lo_hi_64, decoder_decoded_andMatrixOutputs_lo_lo_62}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_38 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_62, decoder_decoded_andMatrixOutputs_andMatrixInput_8_60}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_54 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_64, decoder_decoded_andMatrixOutputs_andMatrixInput_6_64}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_64 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_54, decoder_decoded_andMatrixOutputs_hi_lo_lo_38}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_46 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_65, decoder_decoded_andMatrixOutputs_andMatrixInput_4_65}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_16 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_65, decoder_decoded_andMatrixOutputs_andMatrixInput_1_65}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_60 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_16, decoder_decoded_andMatrixOutputs_andMatrixInput_2_65}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_65 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_60, decoder_decoded_andMatrixOutputs_hi_hi_lo_46}; // @[pla.scala:98:53] wire [8:0] decoder_decoded_andMatrixOutputs_hi_65 = {decoder_decoded_andMatrixOutputs_hi_hi_65, decoder_decoded_andMatrixOutputs_hi_lo_64}; // @[pla.scala:98:53] wire [16:0] _decoder_decoded_andMatrixOutputs_T_65 = {decoder_decoded_andMatrixOutputs_hi_65, decoder_decoded_andMatrixOutputs_lo_65}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_12_2 = &_decoder_decoded_andMatrixOutputs_T_65; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_23 = {decoder_decoded_andMatrixOutputs_andMatrixInput_15_23, decoder_decoded_andMatrixOutputs_andMatrixInput_16_17}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_53 = {decoder_decoded_andMatrixOutputs_andMatrixInput_13_45, decoder_decoded_andMatrixOutputs_andMatrixInput_14_39}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_lo_63 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_53, decoder_decoded_andMatrixOutputs_lo_lo_lo_23}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_45 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_53, decoder_decoded_andMatrixOutputs_andMatrixInput_12_47}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_57 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_57, decoder_decoded_andMatrixOutputs_andMatrixInput_10_55}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_lo_hi_65 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_57, decoder_decoded_andMatrixOutputs_lo_hi_lo_45}; // @[pla.scala:98:53] wire [7:0] decoder_decoded_andMatrixOutputs_lo_66 = {decoder_decoded_andMatrixOutputs_lo_hi_65, decoder_decoded_andMatrixOutputs_lo_lo_63}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_39 = {decoder_decoded_andMatrixOutputs_andMatrixInput_7_63, decoder_decoded_andMatrixOutputs_andMatrixInput_8_61}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_55 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_65, decoder_decoded_andMatrixOutputs_andMatrixInput_6_65}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoder_decoded_andMatrixOutputs_hi_lo_65 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_55, decoder_decoded_andMatrixOutputs_hi_lo_lo_39}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_47 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_66, decoder_decoded_andMatrixOutputs_andMatrixInput_4_66}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_17 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_66, decoder_decoded_andMatrixOutputs_andMatrixInput_1_66}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_61 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_17, decoder_decoded_andMatrixOutputs_andMatrixInput_2_66}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_66 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_61, decoder_decoded_andMatrixOutputs_hi_hi_lo_47}; // @[pla.scala:98:53] wire [8:0] decoder_decoded_andMatrixOutputs_hi_66 = {decoder_decoded_andMatrixOutputs_hi_hi_66, decoder_decoded_andMatrixOutputs_hi_lo_65}; // @[pla.scala:98:53] wire [16:0] _decoder_decoded_andMatrixOutputs_T_66 = {decoder_decoded_andMatrixOutputs_hi_66, decoder_decoded_andMatrixOutputs_lo_66}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_56_2 = &_decoder_decoded_andMatrixOutputs_T_66; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_24 = {decoder_decoded_andMatrixOutputs_andMatrixInput_18_6, decoder_decoded_andMatrixOutputs_andMatrixInput_19}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_hi = {decoder_decoded_andMatrixOutputs_andMatrixInput_15_24, decoder_decoded_andMatrixOutputs_andMatrixInput_16_18}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_54 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_hi, decoder_decoded_andMatrixOutputs_andMatrixInput_17_12}; // @[pla.scala:90:45, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_lo_64 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_54, decoder_decoded_andMatrixOutputs_lo_lo_lo_24}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_46 = {decoder_decoded_andMatrixOutputs_andMatrixInput_13_46, decoder_decoded_andMatrixOutputs_andMatrixInput_14_40}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_12 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_56, decoder_decoded_andMatrixOutputs_andMatrixInput_11_54}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_58 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_12, decoder_decoded_andMatrixOutputs_andMatrixInput_12_48}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_66 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_58, decoder_decoded_andMatrixOutputs_lo_hi_lo_46}; // @[pla.scala:98:53] wire [9:0] decoder_decoded_andMatrixOutputs_lo_67 = {decoder_decoded_andMatrixOutputs_lo_hi_66, decoder_decoded_andMatrixOutputs_lo_lo_64}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_40 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_62, decoder_decoded_andMatrixOutputs_andMatrixInput_9_58}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_6 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_66, decoder_decoded_andMatrixOutputs_andMatrixInput_6_66}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_56 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_6, decoder_decoded_andMatrixOutputs_andMatrixInput_7_64}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_lo_66 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_56, decoder_decoded_andMatrixOutputs_hi_lo_lo_40}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_48 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_67, decoder_decoded_andMatrixOutputs_andMatrixInput_4_67}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_18 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_67, decoder_decoded_andMatrixOutputs_andMatrixInput_1_67}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_62 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_18, decoder_decoded_andMatrixOutputs_andMatrixInput_2_67}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_67 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_62, decoder_decoded_andMatrixOutputs_hi_hi_lo_48}; // @[pla.scala:98:53] wire [9:0] decoder_decoded_andMatrixOutputs_hi_67 = {decoder_decoded_andMatrixOutputs_hi_hi_67, decoder_decoded_andMatrixOutputs_hi_lo_66}; // @[pla.scala:98:53] wire [19:0] _decoder_decoded_andMatrixOutputs_T_67 = {decoder_decoded_andMatrixOutputs_hi_67, decoder_decoded_andMatrixOutputs_lo_67}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_35_2 = &_decoder_decoded_andMatrixOutputs_T_67; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_25 = {decoder_decoded_andMatrixOutputs_andMatrixInput_19_1, decoder_decoded_andMatrixOutputs_andMatrixInput_20}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_16_19, decoder_decoded_andMatrixOutputs_andMatrixInput_17_13}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_55 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_1, decoder_decoded_andMatrixOutputs_andMatrixInput_18_7}; // @[pla.scala:90:45, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_lo_65 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_55, decoder_decoded_andMatrixOutputs_lo_lo_lo_25}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_47 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_41, decoder_decoded_andMatrixOutputs_andMatrixInput_15_25}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_13 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_55, decoder_decoded_andMatrixOutputs_andMatrixInput_12_49}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_59 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_13, decoder_decoded_andMatrixOutputs_andMatrixInput_13_47}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_67 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_59, decoder_decoded_andMatrixOutputs_lo_hi_lo_47}; // @[pla.scala:98:53] wire [9:0] decoder_decoded_andMatrixOutputs_lo_68 = {decoder_decoded_andMatrixOutputs_lo_hi_67, decoder_decoded_andMatrixOutputs_lo_lo_65}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_41 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_59, decoder_decoded_andMatrixOutputs_andMatrixInput_10_57}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_7 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_67, decoder_decoded_andMatrixOutputs_andMatrixInput_7_65}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_57 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_7, decoder_decoded_andMatrixOutputs_andMatrixInput_8_63}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_lo_67 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_57, decoder_decoded_andMatrixOutputs_hi_lo_lo_41}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_hi = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_68, decoder_decoded_andMatrixOutputs_andMatrixInput_4_68}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_49 = {decoder_decoded_andMatrixOutputs_hi_hi_lo_hi, decoder_decoded_andMatrixOutputs_andMatrixInput_5_67}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_19 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_68, decoder_decoded_andMatrixOutputs_andMatrixInput_1_68}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_63 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_19, decoder_decoded_andMatrixOutputs_andMatrixInput_2_68}; // @[pla.scala:91:29, :98:53] wire [5:0] decoder_decoded_andMatrixOutputs_hi_hi_68 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_63, decoder_decoded_andMatrixOutputs_hi_hi_lo_49}; // @[pla.scala:98:53] wire [10:0] decoder_decoded_andMatrixOutputs_hi_68 = {decoder_decoded_andMatrixOutputs_hi_hi_68, decoder_decoded_andMatrixOutputs_hi_lo_67}; // @[pla.scala:98:53] wire [20:0] _decoder_decoded_andMatrixOutputs_T_68 = {decoder_decoded_andMatrixOutputs_hi_68, decoder_decoded_andMatrixOutputs_lo_68}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_34_2 = &_decoder_decoded_andMatrixOutputs_T_68; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_26 = {decoder_decoded_andMatrixOutputs_andMatrixInput_18_8, decoder_decoded_andMatrixOutputs_andMatrixInput_19_2}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_2 = {decoder_decoded_andMatrixOutputs_andMatrixInput_15_26, decoder_decoded_andMatrixOutputs_andMatrixInput_16_20}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_56 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_2, decoder_decoded_andMatrixOutputs_andMatrixInput_17_14}; // @[pla.scala:90:45, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_lo_66 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_56, decoder_decoded_andMatrixOutputs_lo_lo_lo_26}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_48 = {decoder_decoded_andMatrixOutputs_andMatrixInput_13_48, decoder_decoded_andMatrixOutputs_andMatrixInput_14_42}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_14 = {decoder_decoded_andMatrixOutputs_andMatrixInput_10_58, decoder_decoded_andMatrixOutputs_andMatrixInput_11_56}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_60 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_14, decoder_decoded_andMatrixOutputs_andMatrixInput_12_50}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_68 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_60, decoder_decoded_andMatrixOutputs_lo_hi_lo_48}; // @[pla.scala:98:53] wire [9:0] decoder_decoded_andMatrixOutputs_lo_69 = {decoder_decoded_andMatrixOutputs_lo_hi_68, decoder_decoded_andMatrixOutputs_lo_lo_66}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_42 = {decoder_decoded_andMatrixOutputs_andMatrixInput_8_64, decoder_decoded_andMatrixOutputs_andMatrixInput_9_60}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_8 = {decoder_decoded_andMatrixOutputs_andMatrixInput_5_68, decoder_decoded_andMatrixOutputs_andMatrixInput_6_68}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_58 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_8, decoder_decoded_andMatrixOutputs_andMatrixInput_7_66}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_lo_68 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_58, decoder_decoded_andMatrixOutputs_hi_lo_lo_42}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_50 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_69, decoder_decoded_andMatrixOutputs_andMatrixInput_4_69}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_20 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_69, decoder_decoded_andMatrixOutputs_andMatrixInput_1_69}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_64 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_20, decoder_decoded_andMatrixOutputs_andMatrixInput_2_69}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_hi_69 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_64, decoder_decoded_andMatrixOutputs_hi_hi_lo_50}; // @[pla.scala:98:53] wire [9:0] decoder_decoded_andMatrixOutputs_hi_69 = {decoder_decoded_andMatrixOutputs_hi_hi_69, decoder_decoded_andMatrixOutputs_hi_lo_68}; // @[pla.scala:98:53] wire [19:0] _decoder_decoded_andMatrixOutputs_T_69 = {decoder_decoded_andMatrixOutputs_hi_69, decoder_decoded_andMatrixOutputs_lo_69}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_20_2 = &_decoder_decoded_andMatrixOutputs_T_69; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_27 = {decoder_decoded_andMatrixOutputs_andMatrixInput_19_3, decoder_decoded_andMatrixOutputs_andMatrixInput_20_1}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_3 = {decoder_decoded_andMatrixOutputs_andMatrixInput_16_21, decoder_decoded_andMatrixOutputs_andMatrixInput_17_15}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_57 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_3, decoder_decoded_andMatrixOutputs_andMatrixInput_18_9}; // @[pla.scala:90:45, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_lo_67 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_57, decoder_decoded_andMatrixOutputs_lo_lo_lo_27}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_49 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_43, decoder_decoded_andMatrixOutputs_andMatrixInput_15_27}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_15 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_57, decoder_decoded_andMatrixOutputs_andMatrixInput_12_51}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_61 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_15, decoder_decoded_andMatrixOutputs_andMatrixInput_13_49}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_69 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_61, decoder_decoded_andMatrixOutputs_lo_hi_lo_49}; // @[pla.scala:98:53] wire [9:0] decoder_decoded_andMatrixOutputs_lo_70 = {decoder_decoded_andMatrixOutputs_lo_hi_69, decoder_decoded_andMatrixOutputs_lo_lo_67}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_43 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_61, decoder_decoded_andMatrixOutputs_andMatrixInput_10_59}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_9 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_69, decoder_decoded_andMatrixOutputs_andMatrixInput_7_67}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_59 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_9, decoder_decoded_andMatrixOutputs_andMatrixInput_8_65}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_lo_69 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_59, decoder_decoded_andMatrixOutputs_hi_lo_lo_43}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_70, decoder_decoded_andMatrixOutputs_andMatrixInput_4_70}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_51 = {decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_1, decoder_decoded_andMatrixOutputs_andMatrixInput_5_69}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_21 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_70, decoder_decoded_andMatrixOutputs_andMatrixInput_1_70}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_65 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_21, decoder_decoded_andMatrixOutputs_andMatrixInput_2_70}; // @[pla.scala:91:29, :98:53] wire [5:0] decoder_decoded_andMatrixOutputs_hi_hi_70 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_65, decoder_decoded_andMatrixOutputs_hi_hi_lo_51}; // @[pla.scala:98:53] wire [10:0] decoder_decoded_andMatrixOutputs_hi_70 = {decoder_decoded_andMatrixOutputs_hi_hi_70, decoder_decoded_andMatrixOutputs_hi_lo_69}; // @[pla.scala:98:53] wire [20:0] _decoder_decoded_andMatrixOutputs_T_70 = {decoder_decoded_andMatrixOutputs_hi_70, decoder_decoded_andMatrixOutputs_lo_70}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_7_2 = &_decoder_decoded_andMatrixOutputs_T_70; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_28 = {decoder_decoded_andMatrixOutputs_andMatrixInput_20_2, decoder_decoded_andMatrixOutputs_andMatrixInput_21}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_4 = {decoder_decoded_andMatrixOutputs_andMatrixInput_17_16, decoder_decoded_andMatrixOutputs_andMatrixInput_18_10}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_58 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_4, decoder_decoded_andMatrixOutputs_andMatrixInput_19_4}; // @[pla.scala:90:45, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_lo_68 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_58, decoder_decoded_andMatrixOutputs_lo_lo_lo_28}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_hi = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_44, decoder_decoded_andMatrixOutputs_andMatrixInput_15_28}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_50 = {decoder_decoded_andMatrixOutputs_lo_hi_lo_hi, decoder_decoded_andMatrixOutputs_andMatrixInput_16_22}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_16 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_58, decoder_decoded_andMatrixOutputs_andMatrixInput_12_52}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_62 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_16, decoder_decoded_andMatrixOutputs_andMatrixInput_13_50}; // @[pla.scala:91:29, :98:53] wire [5:0] decoder_decoded_andMatrixOutputs_lo_hi_70 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_62, decoder_decoded_andMatrixOutputs_lo_hi_lo_50}; // @[pla.scala:98:53] wire [10:0] decoder_decoded_andMatrixOutputs_lo_71 = {decoder_decoded_andMatrixOutputs_lo_hi_70, decoder_decoded_andMatrixOutputs_lo_lo_68}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_44 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_62, decoder_decoded_andMatrixOutputs_andMatrixInput_10_60}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_10 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_70, decoder_decoded_andMatrixOutputs_andMatrixInput_7_68}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_60 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_10, decoder_decoded_andMatrixOutputs_andMatrixInput_8_66}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_lo_70 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_60, decoder_decoded_andMatrixOutputs_hi_lo_lo_44}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_2 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_71, decoder_decoded_andMatrixOutputs_andMatrixInput_4_71}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_52 = {decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_2, decoder_decoded_andMatrixOutputs_andMatrixInput_5_70}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_22 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_71, decoder_decoded_andMatrixOutputs_andMatrixInput_1_71}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_66 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_22, decoder_decoded_andMatrixOutputs_andMatrixInput_2_71}; // @[pla.scala:91:29, :98:53] wire [5:0] decoder_decoded_andMatrixOutputs_hi_hi_71 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_66, decoder_decoded_andMatrixOutputs_hi_hi_lo_52}; // @[pla.scala:98:53] wire [10:0] decoder_decoded_andMatrixOutputs_hi_71 = {decoder_decoded_andMatrixOutputs_hi_hi_71, decoder_decoded_andMatrixOutputs_hi_lo_70}; // @[pla.scala:98:53] wire [21:0] _decoder_decoded_andMatrixOutputs_T_71 = {decoder_decoded_andMatrixOutputs_hi_71, decoder_decoded_andMatrixOutputs_lo_71}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_17_2 = &_decoder_decoded_andMatrixOutputs_T_71; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_29 = {decoder_decoded_andMatrixOutputs_andMatrixInput_19_5, decoder_decoded_andMatrixOutputs_andMatrixInput_20_3}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_5 = {decoder_decoded_andMatrixOutputs_andMatrixInput_16_23, decoder_decoded_andMatrixOutputs_andMatrixInput_17_17}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_59 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_5, decoder_decoded_andMatrixOutputs_andMatrixInput_18_11}; // @[pla.scala:90:45, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_lo_69 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_59, decoder_decoded_andMatrixOutputs_lo_lo_lo_29}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_51 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_45, decoder_decoded_andMatrixOutputs_andMatrixInput_15_29}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_17 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_59, decoder_decoded_andMatrixOutputs_andMatrixInput_12_53}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_63 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_17, decoder_decoded_andMatrixOutputs_andMatrixInput_13_51}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_71 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_63, decoder_decoded_andMatrixOutputs_lo_hi_lo_51}; // @[pla.scala:98:53] wire [9:0] decoder_decoded_andMatrixOutputs_lo_72 = {decoder_decoded_andMatrixOutputs_lo_hi_71, decoder_decoded_andMatrixOutputs_lo_lo_69}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_45 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_63, decoder_decoded_andMatrixOutputs_andMatrixInput_10_61}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_11 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_71, decoder_decoded_andMatrixOutputs_andMatrixInput_7_69}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_61 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_11, decoder_decoded_andMatrixOutputs_andMatrixInput_8_67}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_lo_71 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_61, decoder_decoded_andMatrixOutputs_hi_lo_lo_45}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_3 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_72, decoder_decoded_andMatrixOutputs_andMatrixInput_4_72}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_53 = {decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_3, decoder_decoded_andMatrixOutputs_andMatrixInput_5_71}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_23 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_72, decoder_decoded_andMatrixOutputs_andMatrixInput_1_72}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_67 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_23, decoder_decoded_andMatrixOutputs_andMatrixInput_2_72}; // @[pla.scala:91:29, :98:53] wire [5:0] decoder_decoded_andMatrixOutputs_hi_hi_72 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_67, decoder_decoded_andMatrixOutputs_hi_hi_lo_53}; // @[pla.scala:98:53] wire [10:0] decoder_decoded_andMatrixOutputs_hi_72 = {decoder_decoded_andMatrixOutputs_hi_hi_72, decoder_decoded_andMatrixOutputs_hi_lo_71}; // @[pla.scala:98:53] wire [20:0] _decoder_decoded_andMatrixOutputs_T_72 = {decoder_decoded_andMatrixOutputs_hi_72, decoder_decoded_andMatrixOutputs_lo_72}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_36_2 = &_decoder_decoded_andMatrixOutputs_T_72; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_30 = {decoder_decoded_andMatrixOutputs_andMatrixInput_19_6, decoder_decoded_andMatrixOutputs_andMatrixInput_20_4}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_6 = {decoder_decoded_andMatrixOutputs_andMatrixInput_16_24, decoder_decoded_andMatrixOutputs_andMatrixInput_17_18}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_60 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_6, decoder_decoded_andMatrixOutputs_andMatrixInput_18_12}; // @[pla.scala:90:45, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_lo_70 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_60, decoder_decoded_andMatrixOutputs_lo_lo_lo_30}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_52 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_46, decoder_decoded_andMatrixOutputs_andMatrixInput_15_30}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_18 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_60, decoder_decoded_andMatrixOutputs_andMatrixInput_12_54}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_64 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_18, decoder_decoded_andMatrixOutputs_andMatrixInput_13_52}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_72 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_64, decoder_decoded_andMatrixOutputs_lo_hi_lo_52}; // @[pla.scala:98:53] wire [9:0] decoder_decoded_andMatrixOutputs_lo_73 = {decoder_decoded_andMatrixOutputs_lo_hi_72, decoder_decoded_andMatrixOutputs_lo_lo_70}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_46 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_64, decoder_decoded_andMatrixOutputs_andMatrixInput_10_62}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_12 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_72, decoder_decoded_andMatrixOutputs_andMatrixInput_7_70}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_62 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_12, decoder_decoded_andMatrixOutputs_andMatrixInput_8_68}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_lo_72 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_62, decoder_decoded_andMatrixOutputs_hi_lo_lo_46}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_4 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_73, decoder_decoded_andMatrixOutputs_andMatrixInput_4_73}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_54 = {decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_4, decoder_decoded_andMatrixOutputs_andMatrixInput_5_72}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_24 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_73, decoder_decoded_andMatrixOutputs_andMatrixInput_1_73}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_68 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_24, decoder_decoded_andMatrixOutputs_andMatrixInput_2_73}; // @[pla.scala:91:29, :98:53] wire [5:0] decoder_decoded_andMatrixOutputs_hi_hi_73 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_68, decoder_decoded_andMatrixOutputs_hi_hi_lo_54}; // @[pla.scala:98:53] wire [10:0] decoder_decoded_andMatrixOutputs_hi_73 = {decoder_decoded_andMatrixOutputs_hi_hi_73, decoder_decoded_andMatrixOutputs_hi_lo_72}; // @[pla.scala:98:53] wire [20:0] _decoder_decoded_andMatrixOutputs_T_73 = {decoder_decoded_andMatrixOutputs_hi_73, decoder_decoded_andMatrixOutputs_lo_73}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_22_2 = &_decoder_decoded_andMatrixOutputs_T_73; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_31 = {decoder_decoded_andMatrixOutputs_andMatrixInput_19_7, decoder_decoded_andMatrixOutputs_andMatrixInput_20_5}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_7 = {decoder_decoded_andMatrixOutputs_andMatrixInput_16_25, decoder_decoded_andMatrixOutputs_andMatrixInput_17_19}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_61 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_7, decoder_decoded_andMatrixOutputs_andMatrixInput_18_13}; // @[pla.scala:90:45, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_lo_71 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_61, decoder_decoded_andMatrixOutputs_lo_lo_lo_31}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_53 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_47, decoder_decoded_andMatrixOutputs_andMatrixInput_15_31}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_19 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_61, decoder_decoded_andMatrixOutputs_andMatrixInput_12_55}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_65 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_19, decoder_decoded_andMatrixOutputs_andMatrixInput_13_53}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_73 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_65, decoder_decoded_andMatrixOutputs_lo_hi_lo_53}; // @[pla.scala:98:53] wire [9:0] decoder_decoded_andMatrixOutputs_lo_74 = {decoder_decoded_andMatrixOutputs_lo_hi_73, decoder_decoded_andMatrixOutputs_lo_lo_71}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_47 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_65, decoder_decoded_andMatrixOutputs_andMatrixInput_10_63}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_13 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_73, decoder_decoded_andMatrixOutputs_andMatrixInput_7_71}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_63 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_13, decoder_decoded_andMatrixOutputs_andMatrixInput_8_69}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_lo_73 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_63, decoder_decoded_andMatrixOutputs_hi_lo_lo_47}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_5 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_74, decoder_decoded_andMatrixOutputs_andMatrixInput_4_74}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_55 = {decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_5, decoder_decoded_andMatrixOutputs_andMatrixInput_5_73}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_25 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_74, decoder_decoded_andMatrixOutputs_andMatrixInput_1_74}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_69 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_25, decoder_decoded_andMatrixOutputs_andMatrixInput_2_74}; // @[pla.scala:91:29, :98:53] wire [5:0] decoder_decoded_andMatrixOutputs_hi_hi_74 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_69, decoder_decoded_andMatrixOutputs_hi_hi_lo_55}; // @[pla.scala:98:53] wire [10:0] decoder_decoded_andMatrixOutputs_hi_74 = {decoder_decoded_andMatrixOutputs_hi_hi_74, decoder_decoded_andMatrixOutputs_hi_lo_73}; // @[pla.scala:98:53] wire [20:0] _decoder_decoded_andMatrixOutputs_T_74 = {decoder_decoded_andMatrixOutputs_hi_74, decoder_decoded_andMatrixOutputs_lo_74}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_14_2 = &_decoder_decoded_andMatrixOutputs_T_74; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_32 = {decoder_decoded_andMatrixOutputs_andMatrixInput_19_8, decoder_decoded_andMatrixOutputs_andMatrixInput_20_6}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_8 = {decoder_decoded_andMatrixOutputs_andMatrixInput_16_26, decoder_decoded_andMatrixOutputs_andMatrixInput_17_20}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_62 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_8, decoder_decoded_andMatrixOutputs_andMatrixInput_18_14}; // @[pla.scala:90:45, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_lo_72 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_62, decoder_decoded_andMatrixOutputs_lo_lo_lo_32}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_54 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_48, decoder_decoded_andMatrixOutputs_andMatrixInput_15_32}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_20 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_62, decoder_decoded_andMatrixOutputs_andMatrixInput_12_56}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_66 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_20, decoder_decoded_andMatrixOutputs_andMatrixInput_13_54}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_hi_74 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_66, decoder_decoded_andMatrixOutputs_lo_hi_lo_54}; // @[pla.scala:98:53] wire [9:0] decoder_decoded_andMatrixOutputs_lo_75 = {decoder_decoded_andMatrixOutputs_lo_hi_74, decoder_decoded_andMatrixOutputs_lo_lo_72}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_48 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_66, decoder_decoded_andMatrixOutputs_andMatrixInput_10_64}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_14 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_74, decoder_decoded_andMatrixOutputs_andMatrixInput_7_72}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_64 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_14, decoder_decoded_andMatrixOutputs_andMatrixInput_8_70}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_lo_74 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_64, decoder_decoded_andMatrixOutputs_hi_lo_lo_48}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_6 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_75, decoder_decoded_andMatrixOutputs_andMatrixInput_4_75}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_56 = {decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_6, decoder_decoded_andMatrixOutputs_andMatrixInput_5_74}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_26 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_75, decoder_decoded_andMatrixOutputs_andMatrixInput_1_75}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_70 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_26, decoder_decoded_andMatrixOutputs_andMatrixInput_2_75}; // @[pla.scala:91:29, :98:53] wire [5:0] decoder_decoded_andMatrixOutputs_hi_hi_75 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_70, decoder_decoded_andMatrixOutputs_hi_hi_lo_56}; // @[pla.scala:98:53] wire [10:0] decoder_decoded_andMatrixOutputs_hi_75 = {decoder_decoded_andMatrixOutputs_hi_hi_75, decoder_decoded_andMatrixOutputs_hi_lo_74}; // @[pla.scala:98:53] wire [20:0] _decoder_decoded_andMatrixOutputs_T_75 = {decoder_decoded_andMatrixOutputs_hi_75, decoder_decoded_andMatrixOutputs_lo_75}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_28_2 = &_decoder_decoded_andMatrixOutputs_T_75; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_lo_33 = {decoder_decoded_andMatrixOutputs_andMatrixInput_20_7, decoder_decoded_andMatrixOutputs_andMatrixInput_21_1}; // @[pla.scala:90:45, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_9 = {decoder_decoded_andMatrixOutputs_andMatrixInput_17_21, decoder_decoded_andMatrixOutputs_andMatrixInput_18_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_lo_hi_63 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_9, decoder_decoded_andMatrixOutputs_andMatrixInput_19_9}; // @[pla.scala:90:45, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_lo_lo_73 = {decoder_decoded_andMatrixOutputs_lo_lo_hi_63, decoder_decoded_andMatrixOutputs_lo_lo_lo_33}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_14_49, decoder_decoded_andMatrixOutputs_andMatrixInput_15_33}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_lo_55 = {decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_1, decoder_decoded_andMatrixOutputs_andMatrixInput_16_27}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_21 = {decoder_decoded_andMatrixOutputs_andMatrixInput_11_63, decoder_decoded_andMatrixOutputs_andMatrixInput_12_57}; // @[pla.scala:91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_lo_hi_hi_67 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_21, decoder_decoded_andMatrixOutputs_andMatrixInput_13_55}; // @[pla.scala:91:29, :98:53] wire [5:0] decoder_decoded_andMatrixOutputs_lo_hi_75 = {decoder_decoded_andMatrixOutputs_lo_hi_hi_67, decoder_decoded_andMatrixOutputs_lo_hi_lo_55}; // @[pla.scala:98:53] wire [10:0] decoder_decoded_andMatrixOutputs_lo_76 = {decoder_decoded_andMatrixOutputs_lo_hi_75, decoder_decoded_andMatrixOutputs_lo_lo_73}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_lo_49 = {decoder_decoded_andMatrixOutputs_andMatrixInput_9_67, decoder_decoded_andMatrixOutputs_andMatrixInput_10_65}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_15 = {decoder_decoded_andMatrixOutputs_andMatrixInput_6_75, decoder_decoded_andMatrixOutputs_andMatrixInput_7_73}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_lo_hi_65 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_15, decoder_decoded_andMatrixOutputs_andMatrixInput_8_71}; // @[pla.scala:91:29, :98:53] wire [4:0] decoder_decoded_andMatrixOutputs_hi_lo_75 = {decoder_decoded_andMatrixOutputs_hi_lo_hi_65, decoder_decoded_andMatrixOutputs_hi_lo_lo_49}; // @[pla.scala:98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_7 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_76, decoder_decoded_andMatrixOutputs_andMatrixInput_4_76}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_lo_57 = {decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_7, decoder_decoded_andMatrixOutputs_andMatrixInput_5_75}; // @[pla.scala:91:29, :98:53] wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_27 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_76, decoder_decoded_andMatrixOutputs_andMatrixInput_1_76}; // @[pla.scala:90:45, :98:53] wire [2:0] decoder_decoded_andMatrixOutputs_hi_hi_hi_71 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_27, decoder_decoded_andMatrixOutputs_andMatrixInput_2_76}; // @[pla.scala:91:29, :98:53] wire [5:0] decoder_decoded_andMatrixOutputs_hi_hi_76 = {decoder_decoded_andMatrixOutputs_hi_hi_hi_71, decoder_decoded_andMatrixOutputs_hi_hi_lo_57}; // @[pla.scala:98:53] wire [10:0] decoder_decoded_andMatrixOutputs_hi_76 = {decoder_decoded_andMatrixOutputs_hi_hi_76, decoder_decoded_andMatrixOutputs_hi_lo_75}; // @[pla.scala:98:53] wire [21:0] _decoder_decoded_andMatrixOutputs_T_76 = {decoder_decoded_andMatrixOutputs_hi_76, decoder_decoded_andMatrixOutputs_lo_76}; // @[pla.scala:98:53] wire decoder_decoded_andMatrixOutputs_54_2 = &_decoder_decoded_andMatrixOutputs_T_76; // @[pla.scala:98:{53,70}] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_lo = {decoder_decoded_andMatrixOutputs_65_2, decoder_decoded_andMatrixOutputs_45_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_hi = {decoder_decoded_andMatrixOutputs_68_2, decoder_decoded_andMatrixOutputs_62_2}; // @[pla.scala:98:70, :114:19] wire [3:0] decoder_decoded_orMatrixOutputs_lo_lo = {decoder_decoded_orMatrixOutputs_lo_lo_hi, decoder_decoded_orMatrixOutputs_lo_lo_lo}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_lo = {decoder_decoded_andMatrixOutputs_2_2, decoder_decoded_andMatrixOutputs_31_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN = {decoder_decoded_andMatrixOutputs_26_2, decoder_decoded_andMatrixOutputs_58_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_hi_hi = _GEN; // @[pla.scala:114:19] wire [1:0] _decoder_decoded_orMatrixOutputs_T_2; // @[pla.scala:114:19] assign _decoder_decoded_orMatrixOutputs_T_2 = _GEN; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_1; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_hi_lo_1 = _GEN; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_2; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_hi_lo_2 = _GEN; // @[pla.scala:114:19] wire [3:0] decoder_decoded_orMatrixOutputs_lo_hi = {decoder_decoded_orMatrixOutputs_lo_hi_hi, decoder_decoded_orMatrixOutputs_lo_hi_lo}; // @[pla.scala:114:19] wire [7:0] decoder_decoded_orMatrixOutputs_lo = {decoder_decoded_orMatrixOutputs_lo_hi, decoder_decoded_orMatrixOutputs_lo_lo}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_lo = {decoder_decoded_andMatrixOutputs_70_2, decoder_decoded_andMatrixOutputs_52_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_hi = {decoder_decoded_andMatrixOutputs_59_2, decoder_decoded_andMatrixOutputs_3_2}; // @[pla.scala:98:70, :114:19] wire [3:0] decoder_decoded_orMatrixOutputs_hi_lo = {decoder_decoded_orMatrixOutputs_hi_lo_hi, decoder_decoded_orMatrixOutputs_hi_lo_lo}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_lo = {decoder_decoded_andMatrixOutputs_33_2, decoder_decoded_andMatrixOutputs_67_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_0 = {decoder_decoded_andMatrixOutputs_72_2, decoder_decoded_andMatrixOutputs_16_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_hi; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_hi_hi_hi = _GEN_0; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_6; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_hi_hi_6 = _GEN_0; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_1; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_1 = _GEN_0; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_2; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_2 = _GEN_0; // @[pla.scala:114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_hi = {decoder_decoded_orMatrixOutputs_hi_hi_hi_hi, decoder_decoded_andMatrixOutputs_19_2}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_hi_hi = {decoder_decoded_orMatrixOutputs_hi_hi_hi, decoder_decoded_orMatrixOutputs_hi_hi_lo}; // @[pla.scala:114:19] wire [8:0] decoder_decoded_orMatrixOutputs_hi = {decoder_decoded_orMatrixOutputs_hi_hi, decoder_decoded_orMatrixOutputs_hi_lo}; // @[pla.scala:114:19] wire [16:0] _decoder_decoded_orMatrixOutputs_T = {decoder_decoded_orMatrixOutputs_hi, decoder_decoded_orMatrixOutputs_lo}; // @[pla.scala:114:19] wire _decoder_decoded_orMatrixOutputs_T_1 = \|_decoder_decoded_orMatrixOutputs_T; // @[pla.scala:114:{19,36}] wire _decoder_decoded_orMatrixOutputs_T_3 = \|_decoder_decoded_orMatrixOutputs_T_2; // @[pla.scala:114:{19,36}] wire [1:0] _decoder_decoded_orMatrixOutputs_T_4 = {decoder_decoded_andMatrixOutputs_69_2, decoder_decoded_andMatrixOutputs_42_2}; // @[pla.scala:98:70, :114:19] wire _decoder_decoded_orMatrixOutputs_T_5 = \|_decoder_decoded_orMatrixOutputs_T_4; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_1 = {decoder_decoded_andMatrixOutputs_41_2, decoder_decoded_andMatrixOutputs_74_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_1; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_1 = _GEN_1; // @[pla.scala:114:19] wire [1:0] _decoder_decoded_orMatrixOutputs_T_22; // @[pla.scala:114:19] assign _decoder_decoded_orMatrixOutputs_T_22 = _GEN_1; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_1 = {decoder_decoded_andMatrixOutputs_72_2, decoder_decoded_andMatrixOutputs_18_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_1 = {decoder_decoded_orMatrixOutputs_hi_hi_1, decoder_decoded_andMatrixOutputs_8_2}; // @[pla.scala:98:70, :114:19] wire [4:0] _decoder_decoded_orMatrixOutputs_T_6 = {decoder_decoded_orMatrixOutputs_hi_1, decoder_decoded_orMatrixOutputs_lo_1}; // @[pla.scala:114:19] wire _decoder_decoded_orMatrixOutputs_T_7 = \|_decoder_decoded_orMatrixOutputs_T_6; // @[pla.scala:114:{19,36}] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_1 = {decoder_decoded_andMatrixOutputs_32_2, decoder_decoded_andMatrixOutputs_64_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_1 = {decoder_decoded_andMatrixOutputs_5_2, decoder_decoded_andMatrixOutputs_27_2}; // @[pla.scala:98:70, :114:19] wire [3:0] decoder_decoded_orMatrixOutputs_lo_2 = {decoder_decoded_orMatrixOutputs_lo_hi_1, decoder_decoded_orMatrixOutputs_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_1 = {decoder_decoded_andMatrixOutputs_73_2, decoder_decoded_andMatrixOutputs_23_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_2 = {decoder_decoded_andMatrixOutputs_61_2, decoder_decoded_andMatrixOutputs_44_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_2; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_hi_2 = _GEN_2; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_7; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_lo_7 = _GEN_2; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_1; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_1 = _GEN_2; // @[pla.scala:114:19] wire [3:0] decoder_decoded_orMatrixOutputs_hi_2 = {decoder_decoded_orMatrixOutputs_hi_hi_2, decoder_decoded_orMatrixOutputs_hi_lo_1}; // @[pla.scala:114:19] wire [7:0] _decoder_decoded_orMatrixOutputs_T_8 = {decoder_decoded_orMatrixOutputs_hi_2, decoder_decoded_orMatrixOutputs_lo_2}; // @[pla.scala:114:19] wire _decoder_decoded_orMatrixOutputs_T_9 = \|_decoder_decoded_orMatrixOutputs_T_8; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_3 = {decoder_decoded_andMatrixOutputs_35_2, decoder_decoded_andMatrixOutputs_20_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_2; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_lo_2 = _GEN_3; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_lo_1; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_lo_lo_1 = _GEN_3; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_1 = {decoder_decoded_andMatrixOutputs_62_2, decoder_decoded_andMatrixOutputs_0_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_hi_2 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_1, decoder_decoded_andMatrixOutputs_4_2}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_lo_3 = {decoder_decoded_orMatrixOutputs_lo_hi_2, decoder_decoded_orMatrixOutputs_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_2 = {decoder_decoded_andMatrixOutputs_31_2, decoder_decoded_andMatrixOutputs_68_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_4 = {decoder_decoded_andMatrixOutputs_66_2, decoder_decoded_andMatrixOutputs_47_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_1; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_hi_hi_1 = _GEN_4; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_5; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_hi_hi_5 = _GEN_4; // @[pla.scala:114:19] wire [1:0] _decoder_decoded_orMatrixOutputs_T_24; // @[pla.scala:114:19] assign _decoder_decoded_orMatrixOutputs_T_24 = _GEN_4; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_5; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_lo_hi_5 = _GEN_4; // @[pla.scala:114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_3 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_1, decoder_decoded_andMatrixOutputs_2_2}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_hi_3 = {decoder_decoded_orMatrixOutputs_hi_hi_3, decoder_decoded_orMatrixOutputs_hi_lo_2}; // @[pla.scala:114:19] wire [9:0] _decoder_decoded_orMatrixOutputs_T_10 = {decoder_decoded_orMatrixOutputs_hi_3, decoder_decoded_orMatrixOutputs_lo_3}; // @[pla.scala:114:19] wire _decoder_decoded_orMatrixOutputs_T_11 = \|_decoder_decoded_orMatrixOutputs_T_10; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_5 = {decoder_decoded_andMatrixOutputs_14_2, decoder_decoded_andMatrixOutputs_28_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_4; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_4 = _GEN_5; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_lo_2; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_lo_lo_2 = _GEN_5; // @[pla.scala:114:19] wire [1:0] _GEN_6 = {decoder_decoded_andMatrixOutputs_46_2, decoder_decoded_andMatrixOutputs_63_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_4; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_4 = _GEN_6; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_4; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_lo_lo_hi_4 = _GEN_6; // @[pla.scala:114:19] wire [3:0] _decoder_decoded_orMatrixOutputs_T_12 = {decoder_decoded_orMatrixOutputs_hi_4, decoder_decoded_orMatrixOutputs_lo_4}; // @[pla.scala:114:19] wire _decoder_decoded_orMatrixOutputs_T_13 = \|_decoder_decoded_orMatrixOutputs_T_12; // @[pla.scala:114:{19,36}] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_3 = {decoder_decoded_andMatrixOutputs_12_2, decoder_decoded_andMatrixOutputs_7_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_2 = {decoder_decoded_andMatrixOutputs_1_2, decoder_decoded_andMatrixOutputs_53_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_hi_3 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_2, decoder_decoded_andMatrixOutputs_76_2}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_lo_5 = {decoder_decoded_orMatrixOutputs_lo_hi_3, decoder_decoded_orMatrixOutputs_lo_lo_3}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_1 = {decoder_decoded_andMatrixOutputs_50_2, decoder_decoded_andMatrixOutputs_21_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_lo_3 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_1, decoder_decoded_andMatrixOutputs_43_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_7 = {decoder_decoded_andMatrixOutputs_6_2, decoder_decoded_andMatrixOutputs_55_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_2; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_hi_hi_2 = _GEN_7; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_4; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_hi_hi_4 = _GEN_7; // @[pla.scala:114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_4 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_2, decoder_decoded_andMatrixOutputs_60_2}; // @[pla.scala:98:70, :114:19] wire [5:0] decoder_decoded_orMatrixOutputs_hi_5 = {decoder_decoded_orMatrixOutputs_hi_hi_4, decoder_decoded_orMatrixOutputs_hi_lo_3}; // @[pla.scala:114:19] wire [10:0] _decoder_decoded_orMatrixOutputs_T_14 = {decoder_decoded_orMatrixOutputs_hi_5, decoder_decoded_orMatrixOutputs_lo_5}; // @[pla.scala:114:19] wire _decoder_decoded_orMatrixOutputs_T_15 = \|_decoder_decoded_orMatrixOutputs_T_14; // @[pla.scala:114:{19,36}] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_1 = {decoder_decoded_andMatrixOutputs_36_2, decoder_decoded_andMatrixOutputs_22_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_lo_4 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_1, decoder_decoded_andMatrixOutputs_14_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_3 = {decoder_decoded_andMatrixOutputs_32_2, decoder_decoded_andMatrixOutputs_51_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_hi_4 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_3, decoder_decoded_andMatrixOutputs_56_2}; // @[pla.scala:98:70, :114:19] wire [5:0] decoder_decoded_orMatrixOutputs_lo_6 = {decoder_decoded_orMatrixOutputs_lo_hi_4, decoder_decoded_orMatrixOutputs_lo_lo_4}; // @[pla.scala:114:19] wire [1:0] _GEN_8 = {decoder_decoded_andMatrixOutputs_38_2, decoder_decoded_andMatrixOutputs_10_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_2; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_lo_hi_2 = _GEN_8; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_4; // @[pla.scala:114:19] assign decoder_decoded_orMatrixOutputs_hi_lo_hi_4 = _GEN_8; // @[pla.scala:114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_lo_4 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_2, decoder_decoded_andMatrixOutputs_40_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_3 = {decoder_decoded_andMatrixOutputs_15_2, decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_5 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_3, decoder_decoded_andMatrixOutputs_39_2}; // @[pla.scala:98:70, :114:19] wire [5:0] decoder_decoded_orMatrixOutputs_hi_6 = {decoder_decoded_orMatrixOutputs_hi_hi_5, decoder_decoded_orMatrixOutputs_hi_lo_4}; // @[pla.scala:114:19] wire [11:0] _decoder_decoded_orMatrixOutputs_T_16 = {decoder_decoded_orMatrixOutputs_hi_6, decoder_decoded_orMatrixOutputs_lo_6}; // @[pla.scala:114:19] wire _decoder_decoded_orMatrixOutputs_T_17 = \|_decoder_decoded_orMatrixOutputs_T_16; // @[pla.scala:114:{19,36}] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_5 = {decoder_decoded_andMatrixOutputs_17_2, decoder_decoded_andMatrixOutputs_54_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_4 = {decoder_decoded_andMatrixOutputs_11_2, decoder_decoded_andMatrixOutputs_76_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_hi_5 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_4, decoder_decoded_andMatrixOutputs_25_2}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_lo_7 = {decoder_decoded_orMatrixOutputs_lo_hi_5, decoder_decoded_orMatrixOutputs_lo_lo_5}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_3 = {decoder_decoded_andMatrixOutputs_21_2, decoder_decoded_andMatrixOutputs_43_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_lo_5 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_3, decoder_decoded_andMatrixOutputs_13_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_6 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_4, decoder_decoded_andMatrixOutputs_50_2}; // @[pla.scala:98:70, :114:19] wire [5:0] decoder_decoded_orMatrixOutputs_hi_7 = {decoder_decoded_orMatrixOutputs_hi_hi_6, decoder_decoded_orMatrixOutputs_hi_lo_5}; // @[pla.scala:114:19] wire [10:0] _decoder_decoded_orMatrixOutputs_T_18 = {decoder_decoded_orMatrixOutputs_hi_7, decoder_decoded_orMatrixOutputs_lo_7}; // @[pla.scala:114:19] wire _decoder_decoded_orMatrixOutputs_T_19 = \|_decoder_decoded_orMatrixOutputs_T_18; // @[pla.scala:114:{19,36}] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_2 = {decoder_decoded_andMatrixOutputs_34_2, decoder_decoded_andMatrixOutputs_36_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_lo_6 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_2, decoder_decoded_andMatrixOutputs_22_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_5 = {decoder_decoded_andMatrixOutputs_5_2, decoder_decoded_andMatrixOutputs_51_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_hi_6 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_5, decoder_decoded_andMatrixOutputs_48_2}; // @[pla.scala:98:70, :114:19] wire [5:0] decoder_decoded_orMatrixOutputs_lo_8 = {decoder_decoded_orMatrixOutputs_lo_hi_6, decoder_decoded_orMatrixOutputs_lo_lo_6}; // @[pla.scala:114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_lo_6 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_4, decoder_decoded_andMatrixOutputs_40_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_1 = {decoder_decoded_andMatrixOutputs_29_2, decoder_decoded_andMatrixOutputs_39_2}; // @[pla.scala:98:70, :114:19] wire [3:0] decoder_decoded_orMatrixOutputs_hi_hi_7 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_5, decoder_decoded_orMatrixOutputs_hi_hi_lo_1}; // @[pla.scala:114:19] wire [6:0] decoder_decoded_orMatrixOutputs_hi_8 = {decoder_decoded_orMatrixOutputs_hi_hi_7, decoder_decoded_orMatrixOutputs_hi_lo_6}; // @[pla.scala:114:19] wire [12:0] _decoder_decoded_orMatrixOutputs_T_20 = {decoder_decoded_orMatrixOutputs_hi_8, decoder_decoded_orMatrixOutputs_lo_8}; // @[pla.scala:114:19] wire _decoder_decoded_orMatrixOutputs_T_21 = \|_decoder_decoded_orMatrixOutputs_T_20; // @[pla.scala:114:{19,36}] wire _decoder_decoded_orMatrixOutputs_T_23 = \|_decoder_decoded_orMatrixOutputs_T_22; // @[pla.scala:114:{19,36}] wire _decoder_decoded_orMatrixOutputs_T_25 = \|_decoder_decoded_orMatrixOutputs_T_24; // @[pla.scala:114:{19,36}] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_6 = {decoder_decoded_andMatrixOutputs_24_2, decoder_decoded_andMatrixOutputs_9_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_hi_7 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_6, decoder_decoded_andMatrixOutputs_57_2}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_lo_9 = {decoder_decoded_orMatrixOutputs_lo_hi_7, decoder_decoded_orMatrixOutputs_lo_lo_7}; // @[pla.scala:114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_lo_7 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_5, decoder_decoded_andMatrixOutputs_49_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_8 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_6, decoder_decoded_andMatrixOutputs_19_2}; // @[pla.scala:98:70, :114:19] wire [5:0] decoder_decoded_orMatrixOutputs_hi_9 = {decoder_decoded_orMatrixOutputs_hi_hi_8, decoder_decoded_orMatrixOutputs_hi_lo_7}; // @[pla.scala:114:19] wire [10:0] _decoder_decoded_orMatrixOutputs_T_27 = {decoder_decoded_orMatrixOutputs_hi_9, decoder_decoded_orMatrixOutputs_lo_9}; // @[pla.scala:114:19] wire _decoder_decoded_orMatrixOutputs_T_28 = \|_decoder_decoded_orMatrixOutputs_T_27; // @[pla.scala:114:{19,36}] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_3 = {decoder_decoded_andMatrixOutputs_0_2, decoder_decoded_andMatrixOutputs_4_2}; // @[pla.scala:98:70, :114:19] wire [3:0] decoder_decoded_orMatrixOutputs_lo_lo_8 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_3, decoder_decoded_orMatrixOutputs_lo_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_hi = {decoder_decoded_andMatrixOutputs_3_2, decoder_decoded_andMatrixOutputs_70_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_7 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_hi, decoder_decoded_andMatrixOutputs_52_2}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_lo_hi_8 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_7, decoder_decoded_orMatrixOutputs_lo_hi_lo_1}; // @[pla.scala:114:19] wire [8:0] decoder_decoded_orMatrixOutputs_lo_10 = {decoder_decoded_orMatrixOutputs_lo_hi_8, decoder_decoded_orMatrixOutputs_lo_lo_8}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_lo_1 = {decoder_decoded_andMatrixOutputs_44_2, decoder_decoded_andMatrixOutputs_59_2}; // @[pla.scala:98:70, :114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_hi = {decoder_decoded_andMatrixOutputs_9_2, decoder_decoded_andMatrixOutputs_57_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_6 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_hi, decoder_decoded_andMatrixOutputs_61_2}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_hi_lo_8 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_6, decoder_decoded_orMatrixOutputs_hi_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_2 = {decoder_decoded_andMatrixOutputs_49_2, decoder_decoded_andMatrixOutputs_24_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_7 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_1, decoder_decoded_andMatrixOutputs_19_2}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_hi_hi_9 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_7, decoder_decoded_orMatrixOutputs_hi_hi_lo_2}; // @[pla.scala:114:19] wire [9:0] decoder_decoded_orMatrixOutputs_hi_10 = {decoder_decoded_orMatrixOutputs_hi_hi_9, decoder_decoded_orMatrixOutputs_hi_lo_8}; // @[pla.scala:114:19] wire [18:0] _decoder_decoded_orMatrixOutputs_T_29 = {decoder_decoded_orMatrixOutputs_hi_10, decoder_decoded_orMatrixOutputs_lo_10}; // @[pla.scala:114:19] wire _decoder_decoded_orMatrixOutputs_T_30 = \|_decoder_decoded_orMatrixOutputs_T_29; // @[pla.scala:114:{19,36}] wire [3:0] decoder_decoded_orMatrixOutputs_lo_lo_9 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_4, decoder_decoded_orMatrixOutputs_lo_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_1 = {decoder_decoded_andMatrixOutputs_27_2, decoder_decoded_andMatrixOutputs_32_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_8 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_1, decoder_decoded_andMatrixOutputs_64_2}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_lo_hi_9 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_8, decoder_decoded_orMatrixOutputs_lo_hi_lo_2}; // @[pla.scala:114:19] wire [8:0] decoder_decoded_orMatrixOutputs_lo_11 = {decoder_decoded_orMatrixOutputs_lo_hi_9, decoder_decoded_orMatrixOutputs_lo_lo_9}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_lo_2 = {decoder_decoded_andMatrixOutputs_23_2, decoder_decoded_andMatrixOutputs_5_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_7 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_1, decoder_decoded_andMatrixOutputs_73_2}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_hi_lo_9 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_7, decoder_decoded_orMatrixOutputs_hi_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_3 = {decoder_decoded_andMatrixOutputs_30_2, decoder_decoded_andMatrixOutputs_37_2}; // @[pla.scala:98:70, :114:19] wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_8 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_2, decoder_decoded_andMatrixOutputs_19_2}; // @[pla.scala:98:70, :114:19] wire [4:0] decoder_decoded_orMatrixOutputs_hi_hi_10 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_8, decoder_decoded_orMatrixOutputs_hi_hi_lo_3}; // @[pla.scala:114:19] wire [9:0] decoder_decoded_orMatrixOutputs_hi_11 = {decoder_decoded_orMatrixOutputs_hi_hi_10, decoder_decoded_orMatrixOutputs_hi_lo_9}; // @[pla.scala:114:19] wire [18:0] _decoder_decoded_orMatrixOutputs_T_31 = {decoder_decoded_orMatrixOutputs_hi_11, decoder_decoded_orMatrixOutputs_lo_11}; // @[pla.scala:114:19] wire _decoder_decoded_orMatrixOutputs_T_32 = \|_decoder_decoded_orMatrixOutputs_T_31; // @[pla.scala:114:{19,36}] wire [1:0] _decoder_decoded_orMatrixOutputs_T_33 = {decoder_decoded_andMatrixOutputs_71_2, decoder_decoded_andMatrixOutputs_75_2}; // @[pla.scala:98:70, :114:19] wire _decoder_decoded_orMatrixOutputs_T_34 = \|_decoder_decoded_orMatrixOutputs_T_33; // @[pla.scala:114:{19,36}] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_lo_3 = {_decoder_decoded_orMatrixOutputs_T_1, 1'h0}; // @[pla.scala:102:36, :114:36] wire [1:0] decoder_decoded_orMatrixOutputs_lo_lo_hi_5 = {_decoder_decoded_orMatrixOutputs_T_5, _decoder_decoded_orMatrixOutputs_T_3}; // @[pla.scala:102:36, :114:36] wire [3:0] decoder_decoded_orMatrixOutputs_lo_lo_10 = {decoder_decoded_orMatrixOutputs_lo_lo_hi_5, decoder_decoded_orMatrixOutputs_lo_lo_lo_3}; // @[pla.scala:102:36] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_lo_3 = {_decoder_decoded_orMatrixOutputs_T_9, _decoder_decoded_orMatrixOutputs_T_7}; // @[pla.scala:102:36, :114:36] wire [1:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_2 = {_decoder_decoded_orMatrixOutputs_T_15, _decoder_decoded_orMatrixOutputs_T_13}; // @[pla.scala:102:36, :114:36] wire [2:0] decoder_decoded_orMatrixOutputs_lo_hi_hi_9 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_2, _decoder_decoded_orMatrixOutputs_T_11}; // @[pla.scala:102:36, :114:36] wire [4:0] decoder_decoded_orMatrixOutputs_lo_hi_10 = {decoder_decoded_orMatrixOutputs_lo_hi_hi_9, decoder_decoded_orMatrixOutputs_lo_hi_lo_3}; // @[pla.scala:102:36] wire [8:0] decoder_decoded_orMatrixOutputs_lo_12 = {decoder_decoded_orMatrixOutputs_lo_hi_10, decoder_decoded_orMatrixOutputs_lo_lo_10}; // @[pla.scala:102:36] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_lo_3 = {_decoder_decoded_orMatrixOutputs_T_19, _decoder_decoded_orMatrixOutputs_T_17}; // @[pla.scala:102:36, :114:36] wire [1:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_2 = {_decoder_decoded_orMatrixOutputs_T_25, _decoder_decoded_orMatrixOutputs_T_23}; // @[pla.scala:102:36, :114:36] wire [2:0] decoder_decoded_orMatrixOutputs_hi_lo_hi_8 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_2, _decoder_decoded_orMatrixOutputs_T_21}; // @[pla.scala:102:36, :114:36] wire [4:0] decoder_decoded_orMatrixOutputs_hi_lo_10 = {decoder_decoded_orMatrixOutputs_hi_lo_hi_8, decoder_decoded_orMatrixOutputs_hi_lo_lo_3}; // @[pla.scala:102:36] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_lo_4 = {_decoder_decoded_orMatrixOutputs_T_28, _decoder_decoded_orMatrixOutputs_T_26}; // @[pla.scala:102:36, :114:36] wire [1:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_3 = {_decoder_decoded_orMatrixOutputs_T_34, _decoder_decoded_orMatrixOutputs_T_32}; // @[pla.scala:102:36, :114:36] wire [2:0] decoder_decoded_orMatrixOutputs_hi_hi_hi_9 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_3, _decoder_decoded_orMatrixOutputs_T_30}; // @[pla.scala:102:36, :114:36] wire [4:0] decoder_decoded_orMatrixOutputs_hi_hi_11 = {decoder_decoded_orMatrixOutputs_hi_hi_hi_9, decoder_decoded_orMatrixOutputs_hi_hi_lo_4}; // @[pla.scala:102:36] wire [9:0] decoder_decoded_orMatrixOutputs_hi_12 = {decoder_decoded_orMatrixOutputs_hi_hi_11, decoder_decoded_orMatrixOutputs_hi_lo_10}; // @[pla.scala:102:36] wire [18:0] decoder_decoded_orMatrixOutputs = {decoder_decoded_orMatrixOutputs_hi_12, decoder_decoded_orMatrixOutputs_lo_12}; // @[pla.scala:102:36] wire _decoder_decoded_invMatrixOutputs_T = decoder_decoded_orMatrixOutputs[0]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_1 = decoder_decoded_orMatrixOutputs[1]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_2 = decoder_decoded_orMatrixOutputs[2]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_3 = decoder_decoded_orMatrixOutputs[3]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_4 = decoder_decoded_orMatrixOutputs[4]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_5 = decoder_decoded_orMatrixOutputs[5]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_6 = decoder_decoded_orMatrixOutputs[6]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_7 = decoder_decoded_orMatrixOutputs[7]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_8 = decoder_decoded_orMatrixOutputs[8]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_9 = decoder_decoded_orMatrixOutputs[9]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_10 = decoder_decoded_orMatrixOutputs[10]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_11 = decoder_decoded_orMatrixOutputs[11]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_12 = decoder_decoded_orMatrixOutputs[12]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_13 = decoder_decoded_orMatrixOutputs[13]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_14 = decoder_decoded_orMatrixOutputs[14]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_15 = decoder_decoded_orMatrixOutputs[15]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_16 = decoder_decoded_orMatrixOutputs[16]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_17 = decoder_decoded_orMatrixOutputs[17]; // @[pla.scala:102:36, :124:31] wire _decoder_decoded_invMatrixOutputs_T_18 = decoder_decoded_orMatrixOutputs[18]; // @[pla.scala:102:36, :124:31] wire [1:0] decoder_decoded_invMatrixOutputs_lo_lo_lo = {_decoder_decoded_invMatrixOutputs_T_1, _decoder_decoded_invMatrixOutputs_T}; // @[pla.scala:120:37, :124:31] wire [1:0] decoder_decoded_invMatrixOutputs_lo_lo_hi = {_decoder_decoded_invMatrixOutputs_T_3, _decoder_decoded_invMatrixOutputs_T_2}; // @[pla.scala:120:37, :124:31] wire [3:0] decoder_decoded_invMatrixOutputs_lo_lo = {decoder_decoded_invMatrixOutputs_lo_lo_hi, decoder_decoded_invMatrixOutputs_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoder_decoded_invMatrixOutputs_lo_hi_lo = {_decoder_decoded_invMatrixOutputs_T_5, _decoder_decoded_invMatrixOutputs_T_4}; // @[pla.scala:120:37, :124:31] wire [1:0] decoder_decoded_invMatrixOutputs_lo_hi_hi_hi = {_decoder_decoded_invMatrixOutputs_T_8, _decoder_decoded_invMatrixOutputs_T_7}; // @[pla.scala:120:37, :124:31] wire [2:0] decoder_decoded_invMatrixOutputs_lo_hi_hi = {decoder_decoded_invMatrixOutputs_lo_hi_hi_hi, _decoder_decoded_invMatrixOutputs_T_6}; // @[pla.scala:120:37, :124:31] wire [4:0] decoder_decoded_invMatrixOutputs_lo_hi = {decoder_decoded_invMatrixOutputs_lo_hi_hi, decoder_decoded_invMatrixOutputs_lo_hi_lo}; // @[pla.scala:120:37] wire [8:0] decoder_decoded_invMatrixOutputs_lo = {decoder_decoded_invMatrixOutputs_lo_hi, decoder_decoded_invMatrixOutputs_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoder_decoded_invMatrixOutputs_hi_lo_lo = {_decoder_decoded_invMatrixOutputs_T_10, _decoder_decoded_invMatrixOutputs_T_9}; // @[pla.scala:120:37, :124:31] wire [1:0] decoder_decoded_invMatrixOutputs_hi_lo_hi_hi = {_decoder_decoded_invMatrixOutputs_T_13, _decoder_decoded_invMatrixOutputs_T_12}; // @[pla.scala:120:37, :124:31] wire [2:0] decoder_decoded_invMatrixOutputs_hi_lo_hi = {decoder_decoded_invMatrixOutputs_hi_lo_hi_hi, _decoder_decoded_invMatrixOutputs_T_11}; // @[pla.scala:120:37, :124:31] wire [4:0] decoder_decoded_invMatrixOutputs_hi_lo = {decoder_decoded_invMatrixOutputs_hi_lo_hi, decoder_decoded_invMatrixOutputs_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoder_decoded_invMatrixOutputs_hi_hi_lo = {_decoder_decoded_invMatrixOutputs_T_15, _decoder_decoded_invMatrixOutputs_T_14}; // @[pla.scala:120:37, :124:31] wire [1:0] decoder_decoded_invMatrixOutputs_hi_hi_hi_hi = {_decoder_decoded_invMatrixOutputs_T_18, _decoder_decoded_invMatrixOutputs_T_17}; // @[pla.scala:120:37, :124:31] wire [2:0] decoder_decoded_invMatrixOutputs_hi_hi_hi = {decoder_decoded_invMatrixOutputs_hi_hi_hi_hi, _decoder_decoded_invMatrixOutputs_T_16}; // @[pla.scala:120:37, :124:31] wire [4:0] decoder_decoded_invMatrixOutputs_hi_hi = {decoder_decoded_invMatrixOutputs_hi_hi_hi, decoder_decoded_invMatrixOutputs_hi_hi_lo}; // @[pla.scala:120:37] wire [9:0] decoder_decoded_invMatrixOutputs_hi = {decoder_decoded_invMatrixOutputs_hi_hi, decoder_decoded_invMatrixOutputs_hi_lo}; // @[pla.scala:120:37] assign decoder_decoded_invMatrixOutputs = {decoder_decoded_invMatrixOutputs_hi, decoder_decoded_invMatrixOutputs_lo}; // @[pla.scala:120:37] assign decoder_decoded = decoder_decoded_invMatrixOutputs; // @[pla.scala:81:23, :120:37] assign decoder_0 = decoder_decoded[18]; // @[pla.scala:81:23] assign io_sigs_ldst_0 = decoder_0; // @[FPU.scala:55:7] assign decoder_1 = decoder_decoded[17]; // @[pla.scala:81:23] assign io_sigs_wen_0 = decoder_1; // @[FPU.scala:55:7] assign decoder_2 = decoder_decoded[16]; // @[pla.scala:81:23] assign io_sigs_ren1_0 = decoder_2; // @[FPU.scala:55:7] assign decoder_3 = decoder_decoded[15]; // @[pla.scala:81:23] assign io_sigs_ren2_0 = decoder_3; // @[FPU.scala:55:7] assign decoder_4 = decoder_decoded[14]; // @[pla.scala:81:23] assign io_sigs_ren3_0 = decoder_4; // @[FPU.scala:55:7] assign decoder_5 = decoder_decoded[13]; // @[pla.scala:81:23] assign io_sigs_swap12_0 = decoder_5; // @[FPU.scala:55:7] assign decoder_6 = decoder_decoded[12]; // @[pla.scala:81:23] assign io_sigs_swap23_0 = decoder_6; // @[FPU.scala:55:7] assign decoder_7 = decoder_decoded[11:10]; // @[pla.scala:81:23] assign io_sigs_typeTagIn_0 = decoder_7; // @[FPU.scala:55:7] assign decoder_8 = decoder_decoded[9:8]; // @[pla.scala:81:23] assign io_sigs_typeTagOut_0 = decoder_8; // @[FPU.scala:55:7] assign decoder_9 = decoder_decoded[7]; // @[pla.scala:81:23] assign io_sigs_fromint_0 = decoder_9; // @[FPU.scala:55:7] assign decoder_10 = decoder_decoded[6]; // @[pla.scala:81:23] assign io_sigs_toint_0 = decoder_10; // @[FPU.scala:55:7] assign decoder_11 = decoder_decoded[5]; // @[pla.scala:81:23] assign io_sigs_fastpipe_0 = decoder_11; // @[FPU.scala:55:7] assign decoder_12 = decoder_decoded[4]; // @[pla.scala:81:23] assign io_sigs_fma_0 = decoder_12; // @[FPU.scala:55:7] assign decoder_13 = decoder_decoded[3]; // @[pla.scala:81:23] assign io_sigs_div_0 = decoder_13; // @[FPU.scala:55:7] assign decoder_14 = decoder_decoded[2]; // @[pla.scala:81:23] assign io_sigs_sqrt_0 = decoder_14; // @[FPU.scala:55:7] assign decoder_15 = decoder_decoded[1]; // @[pla.scala:81:23] assign io_sigs_wflags_0 = decoder_15; // @[FPU.scala:55:7] assign decoder_16 = decoder_decoded[0]; // @[pla.scala:81:23] assign io_sigs_vec_0 = decoder_16; // @[FPU.scala:55:7] assign io_sigs_ldst = io_sigs_ldst_0; // @[FPU.scala:55:7] assign io_sigs_wen = io_sigs_wen_0; // @[FPU.scala:55:7] assign io_sigs_ren1 = io_sigs_ren1_0; // @[FPU.scala:55:7] assign io_sigs_ren2 = io_sigs_ren2_0; // @[FPU.scala:55:7] assign io_sigs_ren3 = io_sigs_ren3_0; // @[FPU.scala:55:7] assign io_sigs_swap12 = io_sigs_swap12_0; // @[FPU.scala:55:7] assign io_sigs_swap23 = io_sigs_swap23_0; // @[FPU.scala:55:7] assign io_sigs_typeTagIn = io_sigs_typeTagIn_0; // @[FPU.scala:55:7] assign io_sigs_typeTagOut = io_sigs_typeTagOut_0; // @[FPU.scala:55:7] assign io_sigs_fromint = io_sigs_fromint_0; // @[FPU.scala:55:7] assign io_sigs_toint = io_sigs_toint_0; // @[FPU.scala:55:7] assign io_sigs_fastpipe = io_sigs_fastpipe_0; // @[FPU.scala:55:7] assign io_sigs_fma = io_sigs_fma_0; // @[FPU.scala:55:7] assign io_sigs_div = io_sigs_div_0; // @[FPU.scala:55:7] assign io_sigs_sqrt = io_sigs_sqrt_0; // @[FPU.scala:55:7] assign io_sigs_wflags = io_sigs_wflags_0; // @[FPU.scala:55:7] assign io_sigs_vec = io_sigs_vec_0; // @[FPU.scala:55:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_12 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T = shr(io.in.a.bits.source, 2) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_6 = shr(io.in.a.bits.source, 2) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h1)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_12 = shr(io.in.a.bits.source, 2) node _source_ok_T_13 = eq(_source_ok_T_12, UInt<2>(0h2)) node _source_ok_T_14 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_15 = and(_source_ok_T_13, _source_ok_T_14) node _source_ok_T_16 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_17 = and(_source_ok_T_15, _source_ok_T_16) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_18 = shr(io.in.a.bits.source, 2) node _source_ok_T_19 = eq(_source_ok_T_18, UInt<2>(0h3)) node _source_ok_T_20 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_21 = and(_source_ok_T_19, _source_ok_T_20) node _source_ok_T_22 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_23 = and(_source_ok_T_21, _source_ok_T_22) wire _source_ok_WIRE : UInt<1>[4] connect _source_ok_WIRE[0], _source_ok_T_5 connect _source_ok_WIRE[1], _source_ok_T_11 connect _source_ok_WIRE[2], _source_ok_T_17 connect _source_ok_WIRE[3], _source_ok_T_23 node _source_ok_T_24 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_25 = or(_source_ok_T_24, _source_ok_WIRE[2]) node source_ok = or(_source_ok_T_25, _source_ok_WIRE[3]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_4 = shr(io.in.a.bits.source, 2) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<2>(0h3)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_17 = shr(io.in.a.bits.source, 2) node _T_18 = eq(_T_17, UInt<1>(0h1)) node _T_19 = leq(UInt<1>(0h0), uncommonBits_1) node _T_20 = and(_T_18, _T_19) node _T_21 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_22 = and(_T_20, _T_21) node _T_23 = eq(_T_22, UInt<1>(0h0)) node _T_24 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_25 = cvt(_T_24) node _T_26 = and(_T_25, asSInt(UInt<1>(0h0))) node _T_27 = asSInt(_T_26) node _T_28 = eq(_T_27, asSInt(UInt<1>(0h0))) node _T_29 = or(_T_23, _T_28) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_30 = shr(io.in.a.bits.source, 2) node _T_31 = eq(_T_30, UInt<2>(0h2)) node _T_32 = leq(UInt<1>(0h0), uncommonBits_2) node _T_33 = and(_T_31, _T_32) node _T_34 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_35 = and(_T_33, _T_34) node _T_36 = eq(_T_35, UInt<1>(0h0)) node _T_37 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_38 = cvt(_T_37) node _T_39 = and(_T_38, asSInt(UInt<1>(0h0))) node _T_40 = asSInt(_T_39) node _T_41 = eq(_T_40, asSInt(UInt<1>(0h0))) node _T_42 = or(_T_36, _T_41) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_43 = shr(io.in.a.bits.source, 2) node _T_44 = eq(_T_43, UInt<2>(0h3)) node _T_45 = leq(UInt<1>(0h0), uncommonBits_3) node _T_46 = and(_T_44, _T_45) node _T_47 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_48 = and(_T_46, _T_47) node _T_49 = eq(_T_48, UInt<1>(0h0)) node _T_50 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_51 = cvt(_T_50) node _T_52 = and(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = asSInt(_T_52) node _T_54 = eq(_T_53, asSInt(UInt<1>(0h0))) node _T_55 = or(_T_49, _T_54) node _T_56 = and(_T_16, _T_29) node _T_57 = and(_T_56, _T_42) node _T_58 = and(_T_57, _T_55) node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_T_58, UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_58, UInt<1>(0h1), "") : assert_1 node _T_62 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_62 : node _T_63 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_64 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_65 = and(_T_63, _T_64) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_66 = shr(io.in.a.bits.source, 2) node _T_67 = eq(_T_66, UInt<1>(0h0)) node _T_68 = leq(UInt<1>(0h0), uncommonBits_4) node _T_69 = and(_T_67, _T_68) node _T_70 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_71 = and(_T_69, _T_70) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_72 = shr(io.in.a.bits.source, 2) node _T_73 = eq(_T_72, UInt<1>(0h1)) node _T_74 = leq(UInt<1>(0h0), uncommonBits_5) node _T_75 = and(_T_73, _T_74) node _T_76 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_77 = and(_T_75, _T_76) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_78 = shr(io.in.a.bits.source, 2) node _T_79 = eq(_T_78, UInt<2>(0h2)) node _T_80 = leq(UInt<1>(0h0), uncommonBits_6) node _T_81 = and(_T_79, _T_80) node _T_82 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_83 = and(_T_81, _T_82) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_84 = shr(io.in.a.bits.source, 2) node _T_85 = eq(_T_84, UInt<2>(0h3)) node _T_86 = leq(UInt<1>(0h0), uncommonBits_7) node _T_87 = and(_T_85, _T_86) node _T_88 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_89 = and(_T_87, _T_88) node _T_90 = or(_T_71, _T_77) node _T_91 = or(_T_90, _T_83) node _T_92 = or(_T_91, _T_89) node _T_93 = and(_T_65, _T_92) node _T_94 = or(UInt<1>(0h0), _T_93) node _T_95 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_96 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_97 = cvt(_T_96) node _T_98 = and(_T_97, asSInt(UInt<14>(0h2000))) node _T_99 = asSInt(_T_98) node _T_100 = eq(_T_99, asSInt(UInt<1>(0h0))) node _T_101 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_102 = cvt(_T_101) node _T_103 = and(_T_102, asSInt(UInt<13>(0h1000))) node _T_104 = asSInt(_T_103) node _T_105 = eq(_T_104, asSInt(UInt<1>(0h0))) node _T_106 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_107 = cvt(_T_106) node _T_108 = and(_T_107, asSInt(UInt<17>(0h10000))) node _T_109 = asSInt(_T_108) node _T_110 = eq(_T_109, asSInt(UInt<1>(0h0))) node _T_111 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_112 = cvt(_T_111) node _T_113 = and(_T_112, asSInt(UInt<18>(0h2f000))) node _T_114 = asSInt(_T_113) node _T_115 = eq(_T_114, asSInt(UInt<1>(0h0))) node _T_116 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_117 = cvt(_T_116) node _T_118 = and(_T_117, asSInt(UInt<17>(0h10000))) node _T_119 = asSInt(_T_118) node _T_120 = eq(_T_119, asSInt(UInt<1>(0h0))) node _T_121 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_122 = cvt(_T_121) node _T_123 = and(_T_122, asSInt(UInt<27>(0h4000000))) node _T_124 = asSInt(_T_123) node _T_125 = eq(_T_124, asSInt(UInt<1>(0h0))) node _T_126 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_127 = cvt(_T_126) node _T_128 = and(_T_127, asSInt(UInt<13>(0h1000))) node _T_129 = asSInt(_T_128) node _T_130 = eq(_T_129, asSInt(UInt<1>(0h0))) node _T_131 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_132 = cvt(_T_131) node _T_133 = and(_T_132, asSInt(UInt<19>(0h40000))) node _T_134 = asSInt(_T_133) node _T_135 = eq(_T_134, asSInt(UInt<1>(0h0))) node _T_136 = or(_T_100, _T_105) node _T_137 = or(_T_136, _T_110) node _T_138 = or(_T_137, _T_115) node _T_139 = or(_T_138, _T_120) node _T_140 = or(_T_139, _T_125) node _T_141 = or(_T_140, _T_130) node _T_142 = or(_T_141, _T_135) node _T_143 = and(_T_95, _T_142) node _T_144 = or(UInt<1>(0h0), _T_143) node _T_145 = and(_T_94, _T_144) node _T_146 = asUInt(reset) node _T_147 = eq(_T_146, UInt<1>(0h0)) when _T_147 : node _T_148 = eq(_T_145, UInt<1>(0h0)) when _T_148 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_145, UInt<1>(0h1), "") : assert_2 node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _T_152 = or(UInt<1>(0h0), _T_151) node _T_153 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_154 = cvt(_T_153) node _T_155 = and(_T_154, asSInt(UInt<14>(0h2000))) node _T_156 = asSInt(_T_155) node _T_157 = eq(_T_156, asSInt(UInt<1>(0h0))) node _T_158 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_159 = cvt(_T_158) node _T_160 = and(_T_159, asSInt(UInt<13>(0h1000))) node _T_161 = asSInt(_T_160) node _T_162 = eq(_T_161, asSInt(UInt<1>(0h0))) node _T_163 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_164 = cvt(_T_163) node _T_165 = and(_T_164, asSInt(UInt<17>(0h10000))) node _T_166 = asSInt(_T_165) node _T_167 = eq(_T_166, asSInt(UInt<1>(0h0))) node _T_168 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_169 = cvt(_T_168) node _T_170 = and(_T_169, asSInt(UInt<18>(0h2f000))) node _T_171 = asSInt(_T_170) node _T_172 = eq(_T_171, asSInt(UInt<1>(0h0))) node _T_173 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_174 = cvt(_T_173) node _T_175 = and(_T_174, asSInt(UInt<17>(0h10000))) node _T_176 = asSInt(_T_175) node _T_177 = eq(_T_176, asSInt(UInt<1>(0h0))) node _T_178 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_179 = cvt(_T_178) node _T_180 = and(_T_179, asSInt(UInt<27>(0h4000000))) node _T_181 = asSInt(_T_180) node _T_182 = eq(_T_181, asSInt(UInt<1>(0h0))) node _T_183 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_184 = cvt(_T_183) node _T_185 = and(_T_184, asSInt(UInt<13>(0h1000))) node _T_186 = asSInt(_T_185) node _T_187 = eq(_T_186, asSInt(UInt<1>(0h0))) node _T_188 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_189 = cvt(_T_188) node _T_190 = and(_T_189, asSInt(UInt<19>(0h40000))) node _T_191 = asSInt(_T_190) node _T_192 = eq(_T_191, asSInt(UInt<1>(0h0))) node _T_193 = or(_T_157, _T_162) node _T_194 = or(_T_193, _T_167) node _T_195 = or(_T_194, _T_172) node _T_196 = or(_T_195, _T_177) node _T_197 = or(_T_196, _T_182) node _T_198 = or(_T_197, _T_187) node _T_199 = or(_T_198, _T_192) node _T_200 = and(_T_152, _T_199) node _T_201 = or(UInt<1>(0h0), _T_200) node _T_202 = and(UInt<1>(0h0), _T_201) node _T_203 = asUInt(reset) node _T_204 = eq(_T_203, UInt<1>(0h0)) when _T_204 : node _T_205 = eq(_T_202, UInt<1>(0h0)) when _T_205 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_202, UInt<1>(0h1), "") : assert_3 node _T_206 = asUInt(reset) node _T_207 = eq(_T_206, UInt<1>(0h0)) when _T_207 : node _T_208 = eq(source_ok, UInt<1>(0h0)) when _T_208 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_209 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_210 = asUInt(reset) node _T_211 = eq(_T_210, UInt<1>(0h0)) when _T_211 : node _T_212 = eq(_T_209, UInt<1>(0h0)) when _T_212 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_209, UInt<1>(0h1), "") : assert_5 node _T_213 = asUInt(reset) node _T_214 = eq(_T_213, UInt<1>(0h0)) when _T_214 : node _T_215 = eq(is_aligned, UInt<1>(0h0)) when _T_215 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_216 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_217 = asUInt(reset) node _T_218 = eq(_T_217, UInt<1>(0h0)) when _T_218 : node _T_219 = eq(_T_216, UInt<1>(0h0)) when _T_219 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_216, UInt<1>(0h1), "") : assert_7 node _T_220 = not(io.in.a.bits.mask) node _T_221 = eq(_T_220, UInt<1>(0h0)) node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_T_221, UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_221, UInt<1>(0h1), "") : assert_8 node _T_225 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_226 = asUInt(reset) node _T_227 = eq(_T_226, UInt<1>(0h0)) when _T_227 : node _T_228 = eq(_T_225, UInt<1>(0h0)) when _T_228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_225, UInt<1>(0h1), "") : assert_9 node _T_229 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_229 : node _T_230 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_231 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_232 = and(_T_230, _T_231) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_233 = shr(io.in.a.bits.source, 2) node _T_234 = eq(_T_233, UInt<1>(0h0)) node _T_235 = leq(UInt<1>(0h0), uncommonBits_8) node _T_236 = and(_T_234, _T_235) node _T_237 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_238 = and(_T_236, _T_237) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_239 = shr(io.in.a.bits.source, 2) node _T_240 = eq(_T_239, UInt<1>(0h1)) node _T_241 = leq(UInt<1>(0h0), uncommonBits_9) node _T_242 = and(_T_240, _T_241) node _T_243 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_244 = and(_T_242, _T_243) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_245 = shr(io.in.a.bits.source, 2) node _T_246 = eq(_T_245, UInt<2>(0h2)) node _T_247 = leq(UInt<1>(0h0), uncommonBits_10) node _T_248 = and(_T_246, _T_247) node _T_249 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_250 = and(_T_248, _T_249) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_251 = shr(io.in.a.bits.source, 2) node _T_252 = eq(_T_251, UInt<2>(0h3)) node _T_253 = leq(UInt<1>(0h0), uncommonBits_11) node _T_254 = and(_T_252, _T_253) node _T_255 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_256 = and(_T_254, _T_255) node _T_257 = or(_T_238, _T_244) node _T_258 = or(_T_257, _T_250) node _T_259 = or(_T_258, _T_256) node _T_260 = and(_T_232, _T_259) node _T_261 = or(UInt<1>(0h0), _T_260) node _T_262 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_263 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_264 = cvt(_T_263) node _T_265 = and(_T_264, asSInt(UInt<14>(0h2000))) node _T_266 = asSInt(_T_265) node _T_267 = eq(_T_266, asSInt(UInt<1>(0h0))) node _T_268 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_269 = cvt(_T_268) node _T_270 = and(_T_269, asSInt(UInt<13>(0h1000))) node _T_271 = asSInt(_T_270) node _T_272 = eq(_T_271, asSInt(UInt<1>(0h0))) node _T_273 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_274 = cvt(_T_273) node _T_275 = and(_T_274, asSInt(UInt<17>(0h10000))) node _T_276 = asSInt(_T_275) node _T_277 = eq(_T_276, asSInt(UInt<1>(0h0))) node _T_278 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_279 = cvt(_T_278) node _T_280 = and(_T_279, asSInt(UInt<18>(0h2f000))) node _T_281 = asSInt(_T_280) node _T_282 = eq(_T_281, asSInt(UInt<1>(0h0))) node _T_283 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_284 = cvt(_T_283) node _T_285 = and(_T_284, asSInt(UInt<17>(0h10000))) node _T_286 = asSInt(_T_285) node _T_287 = eq(_T_286, asSInt(UInt<1>(0h0))) node _T_288 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_289 = cvt(_T_288) node _T_290 = and(_T_289, asSInt(UInt<27>(0h4000000))) node _T_291 = asSInt(_T_290) node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0))) node _T_293 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_294 = cvt(_T_293) node _T_295 = and(_T_294, asSInt(UInt<13>(0h1000))) node _T_296 = asSInt(_T_295) node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0))) node _T_298 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_299 = cvt(_T_298) node _T_300 = and(_T_299, asSInt(UInt<19>(0h40000))) node _T_301 = asSInt(_T_300) node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0))) node _T_303 = or(_T_267, _T_272) node _T_304 = or(_T_303, _T_277) node _T_305 = or(_T_304, _T_282) node _T_306 = or(_T_305, _T_287) node _T_307 = or(_T_306, _T_292) node _T_308 = or(_T_307, _T_297) node _T_309 = or(_T_308, _T_302) node _T_310 = and(_T_262, _T_309) node _T_311 = or(UInt<1>(0h0), _T_310) node _T_312 = and(_T_261, _T_311) node _T_313 = asUInt(reset) node _T_314 = eq(_T_313, UInt<1>(0h0)) when _T_314 : node _T_315 = eq(_T_312, UInt<1>(0h0)) when _T_315 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_312, UInt<1>(0h1), "") : assert_10 node _T_316 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_317 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_318 = and(_T_316, _T_317) node _T_319 = or(UInt<1>(0h0), _T_318) node _T_320 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_321 = cvt(_T_320) node _T_322 = and(_T_321, asSInt(UInt<14>(0h2000))) node _T_323 = asSInt(_T_322) node _T_324 = eq(_T_323, asSInt(UInt<1>(0h0))) node _T_325 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_326 = cvt(_T_325) node _T_327 = and(_T_326, asSInt(UInt<13>(0h1000))) node _T_328 = asSInt(_T_327) node _T_329 = eq(_T_328, asSInt(UInt<1>(0h0))) node _T_330 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<17>(0h10000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_336 = cvt(_T_335) node _T_337 = and(_T_336, asSInt(UInt<18>(0h2f000))) node _T_338 = asSInt(_T_337) node _T_339 = eq(_T_338, asSInt(UInt<1>(0h0))) node _T_340 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_341 = cvt(_T_340) node _T_342 = and(_T_341, asSInt(UInt<17>(0h10000))) node _T_343 = asSInt(_T_342) node _T_344 = eq(_T_343, asSInt(UInt<1>(0h0))) node _T_345 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_346 = cvt(_T_345) node _T_347 = and(_T_346, asSInt(UInt<27>(0h4000000))) node _T_348 = asSInt(_T_347) node _T_349 = eq(_T_348, asSInt(UInt<1>(0h0))) node _T_350 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_351 = cvt(_T_350) node _T_352 = and(_T_351, asSInt(UInt<13>(0h1000))) node _T_353 = asSInt(_T_352) node _T_354 = eq(_T_353, asSInt(UInt<1>(0h0))) node _T_355 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_356 = cvt(_T_355) node _T_357 = and(_T_356, asSInt(UInt<19>(0h40000))) node _T_358 = asSInt(_T_357) node _T_359 = eq(_T_358, asSInt(UInt<1>(0h0))) node _T_360 = or(_T_324, _T_329) node _T_361 = or(_T_360, _T_334) node _T_362 = or(_T_361, _T_339) node _T_363 = or(_T_362, _T_344) node _T_364 = or(_T_363, _T_349) node _T_365 = or(_T_364, _T_354) node _T_366 = or(_T_365, _T_359) node _T_367 = and(_T_319, _T_366) node _T_368 = or(UInt<1>(0h0), _T_367) node _T_369 = and(UInt<1>(0h0), _T_368) node _T_370 = asUInt(reset) node _T_371 = eq(_T_370, UInt<1>(0h0)) when _T_371 : node _T_372 = eq(_T_369, UInt<1>(0h0)) when _T_372 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_369, UInt<1>(0h1), "") : assert_11 node _T_373 = asUInt(reset) node _T_374 = eq(_T_373, UInt<1>(0h0)) when _T_374 : node _T_375 = eq(source_ok, UInt<1>(0h0)) when _T_375 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_376 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_377 = asUInt(reset) node _T_378 = eq(_T_377, UInt<1>(0h0)) when _T_378 : node _T_379 = eq(_T_376, UInt<1>(0h0)) when _T_379 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_376, UInt<1>(0h1), "") : assert_13 node _T_380 = asUInt(reset) node _T_381 = eq(_T_380, UInt<1>(0h0)) when _T_381 : node _T_382 = eq(is_aligned, UInt<1>(0h0)) when _T_382 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_383 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_384 = asUInt(reset) node _T_385 = eq(_T_384, UInt<1>(0h0)) when _T_385 : node _T_386 = eq(_T_383, UInt<1>(0h0)) when _T_386 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_383, UInt<1>(0h1), "") : assert_15 node _T_387 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_388 = asUInt(reset) node _T_389 = eq(_T_388, UInt<1>(0h0)) when _T_389 : node _T_390 = eq(_T_387, UInt<1>(0h0)) when _T_390 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_387, UInt<1>(0h1), "") : assert_16 node _T_391 = not(io.in.a.bits.mask) node _T_392 = eq(_T_391, UInt<1>(0h0)) node _T_393 = asUInt(reset) node _T_394 = eq(_T_393, UInt<1>(0h0)) when _T_394 : node _T_395 = eq(_T_392, UInt<1>(0h0)) when _T_395 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_392, UInt<1>(0h1), "") : assert_17 node _T_396 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_397 = asUInt(reset) node _T_398 = eq(_T_397, UInt<1>(0h0)) when _T_398 : node _T_399 = eq(_T_396, UInt<1>(0h0)) when _T_399 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_396, UInt<1>(0h1), "") : assert_18 node _T_400 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_400 : node _T_401 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_402 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_403 = and(_T_401, _T_402) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_404 = shr(io.in.a.bits.source, 2) node _T_405 = eq(_T_404, UInt<1>(0h0)) node _T_406 = leq(UInt<1>(0h0), uncommonBits_12) node _T_407 = and(_T_405, _T_406) node _T_408 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_409 = and(_T_407, _T_408) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_410 = shr(io.in.a.bits.source, 2) node _T_411 = eq(_T_410, UInt<1>(0h1)) node _T_412 = leq(UInt<1>(0h0), uncommonBits_13) node _T_413 = and(_T_411, _T_412) node _T_414 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_415 = and(_T_413, _T_414) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_416 = shr(io.in.a.bits.source, 2) node _T_417 = eq(_T_416, UInt<2>(0h2)) node _T_418 = leq(UInt<1>(0h0), uncommonBits_14) node _T_419 = and(_T_417, _T_418) node _T_420 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_421 = and(_T_419, _T_420) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_422 = shr(io.in.a.bits.source, 2) node _T_423 = eq(_T_422, UInt<2>(0h3)) node _T_424 = leq(UInt<1>(0h0), uncommonBits_15) node _T_425 = and(_T_423, _T_424) node _T_426 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_427 = and(_T_425, _T_426) node _T_428 = or(_T_409, _T_415) node _T_429 = or(_T_428, _T_421) node _T_430 = or(_T_429, _T_427) node _T_431 = and(_T_403, _T_430) node _T_432 = or(UInt<1>(0h0), _T_431) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_432, UInt<1>(0h1), "") : assert_19 node _T_436 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_437 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_438 = and(_T_436, _T_437) node _T_439 = or(UInt<1>(0h0), _T_438) node _T_440 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_441 = cvt(_T_440) node _T_442 = and(_T_441, asSInt(UInt<13>(0h1000))) node _T_443 = asSInt(_T_442) node _T_444 = eq(_T_443, asSInt(UInt<1>(0h0))) node _T_445 = and(_T_439, _T_444) node _T_446 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_447 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_448 = and(_T_446, _T_447) node _T_449 = or(UInt<1>(0h0), _T_448) node _T_450 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_451 = cvt(_T_450) node _T_452 = and(_T_451, asSInt(UInt<14>(0h2000))) node _T_453 = asSInt(_T_452) node _T_454 = eq(_T_453, asSInt(UInt<1>(0h0))) node _T_455 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_456 = cvt(_T_455) node _T_457 = and(_T_456, asSInt(UInt<17>(0h10000))) node _T_458 = asSInt(_T_457) node _T_459 = eq(_T_458, asSInt(UInt<1>(0h0))) node _T_460 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_461 = cvt(_T_460) node _T_462 = and(_T_461, asSInt(UInt<18>(0h2f000))) node _T_463 = asSInt(_T_462) node _T_464 = eq(_T_463, asSInt(UInt<1>(0h0))) node _T_465 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_466 = cvt(_T_465) node _T_467 = and(_T_466, asSInt(UInt<17>(0h10000))) node _T_468 = asSInt(_T_467) node _T_469 = eq(_T_468, asSInt(UInt<1>(0h0))) node _T_470 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_471 = cvt(_T_470) node _T_472 = and(_T_471, asSInt(UInt<27>(0h4000000))) node _T_473 = asSInt(_T_472) node _T_474 = eq(_T_473, asSInt(UInt<1>(0h0))) node _T_475 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_476 = cvt(_T_475) node _T_477 = and(_T_476, asSInt(UInt<13>(0h1000))) node _T_478 = asSInt(_T_477) node _T_479 = eq(_T_478, asSInt(UInt<1>(0h0))) node _T_480 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_481 = cvt(_T_480) node _T_482 = and(_T_481, asSInt(UInt<19>(0h40000))) node _T_483 = asSInt(_T_482) node _T_484 = eq(_T_483, asSInt(UInt<1>(0h0))) node _T_485 = or(_T_454, _T_459) node _T_486 = or(_T_485, _T_464) node _T_487 = or(_T_486, _T_469) node _T_488 = or(_T_487, _T_474) node _T_489 = or(_T_488, _T_479) node _T_490 = or(_T_489, _T_484) node _T_491 = and(_T_449, _T_490) node _T_492 = or(UInt<1>(0h0), _T_445) node _T_493 = or(_T_492, _T_491) node _T_494 = asUInt(reset) node _T_495 = eq(_T_494, UInt<1>(0h0)) when _T_495 : node _T_496 = eq(_T_493, UInt<1>(0h0)) when _T_496 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_493, UInt<1>(0h1), "") : assert_20 node _T_497 = asUInt(reset) node _T_498 = eq(_T_497, UInt<1>(0h0)) when _T_498 : node _T_499 = eq(source_ok, UInt<1>(0h0)) when _T_499 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(is_aligned, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_503 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_504 = asUInt(reset) node _T_505 = eq(_T_504, UInt<1>(0h0)) when _T_505 : node _T_506 = eq(_T_503, UInt<1>(0h0)) when _T_506 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_503, UInt<1>(0h1), "") : assert_23 node _T_507 = eq(io.in.a.bits.mask, mask) node _T_508 = asUInt(reset) node _T_509 = eq(_T_508, UInt<1>(0h0)) when _T_509 : node _T_510 = eq(_T_507, UInt<1>(0h0)) when _T_510 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_507, UInt<1>(0h1), "") : assert_24 node _T_511 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_512 = asUInt(reset) node _T_513 = eq(_T_512, UInt<1>(0h0)) when _T_513 : node _T_514 = eq(_T_511, UInt<1>(0h0)) when _T_514 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_511, UInt<1>(0h1), "") : assert_25 node _T_515 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_515 : node _T_516 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_517 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_518 = and(_T_516, _T_517) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_519 = shr(io.in.a.bits.source, 2) node _T_520 = eq(_T_519, UInt<1>(0h0)) node _T_521 = leq(UInt<1>(0h0), uncommonBits_16) node _T_522 = and(_T_520, _T_521) node _T_523 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_524 = and(_T_522, _T_523) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_525 = shr(io.in.a.bits.source, 2) node _T_526 = eq(_T_525, UInt<1>(0h1)) node _T_527 = leq(UInt<1>(0h0), uncommonBits_17) node _T_528 = and(_T_526, _T_527) node _T_529 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_530 = and(_T_528, _T_529) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_531 = shr(io.in.a.bits.source, 2) node _T_532 = eq(_T_531, UInt<2>(0h2)) node _T_533 = leq(UInt<1>(0h0), uncommonBits_18) node _T_534 = and(_T_532, _T_533) node _T_535 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_536 = and(_T_534, _T_535) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_537 = shr(io.in.a.bits.source, 2) node _T_538 = eq(_T_537, UInt<2>(0h3)) node _T_539 = leq(UInt<1>(0h0), uncommonBits_19) node _T_540 = and(_T_538, _T_539) node _T_541 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_542 = and(_T_540, _T_541) node _T_543 = or(_T_524, _T_530) node _T_544 = or(_T_543, _T_536) node _T_545 = or(_T_544, _T_542) node _T_546 = and(_T_518, _T_545) node _T_547 = or(UInt<1>(0h0), _T_546) node _T_548 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_549 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_550 = and(_T_548, _T_549) node _T_551 = or(UInt<1>(0h0), _T_550) node _T_552 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_553 = cvt(_T_552) node _T_554 = and(_T_553, asSInt(UInt<13>(0h1000))) node _T_555 = asSInt(_T_554) node _T_556 = eq(_T_555, asSInt(UInt<1>(0h0))) node _T_557 = and(_T_551, _T_556) node _T_558 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_559 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_560 = and(_T_558, _T_559) node _T_561 = or(UInt<1>(0h0), _T_560) node _T_562 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_563 = cvt(_T_562) node _T_564 = and(_T_563, asSInt(UInt<14>(0h2000))) node _T_565 = asSInt(_T_564) node _T_566 = eq(_T_565, asSInt(UInt<1>(0h0))) node _T_567 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_568 = cvt(_T_567) node _T_569 = and(_T_568, asSInt(UInt<18>(0h2f000))) node _T_570 = asSInt(_T_569) node _T_571 = eq(_T_570, asSInt(UInt<1>(0h0))) node _T_572 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_573 = cvt(_T_572) node _T_574 = and(_T_573, asSInt(UInt<17>(0h10000))) node _T_575 = asSInt(_T_574) node _T_576 = eq(_T_575, asSInt(UInt<1>(0h0))) node _T_577 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_578 = cvt(_T_577) node _T_579 = and(_T_578, asSInt(UInt<27>(0h4000000))) node _T_580 = asSInt(_T_579) node _T_581 = eq(_T_580, asSInt(UInt<1>(0h0))) node _T_582 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_583 = cvt(_T_582) node _T_584 = and(_T_583, asSInt(UInt<13>(0h1000))) node _T_585 = asSInt(_T_584) node _T_586 = eq(_T_585, asSInt(UInt<1>(0h0))) node _T_587 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_588 = cvt(_T_587) node _T_589 = and(_T_588, asSInt(UInt<19>(0h40000))) node _T_590 = asSInt(_T_589) node _T_591 = eq(_T_590, asSInt(UInt<1>(0h0))) node _T_592 = or(_T_566, _T_571) node _T_593 = or(_T_592, _T_576) node _T_594 = or(_T_593, _T_581) node _T_595 = or(_T_594, _T_586) node _T_596 = or(_T_595, _T_591) node _T_597 = and(_T_561, _T_596) node _T_598 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_599 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_600 = cvt(_T_599) node _T_601 = and(_T_600, asSInt(UInt<17>(0h10000))) node _T_602 = asSInt(_T_601) node _T_603 = eq(_T_602, asSInt(UInt<1>(0h0))) node _T_604 = and(_T_598, _T_603) node _T_605 = or(UInt<1>(0h0), _T_557) node _T_606 = or(_T_605, _T_597) node _T_607 = or(_T_606, _T_604) node _T_608 = and(_T_547, _T_607) node _T_609 = asUInt(reset) node _T_610 = eq(_T_609, UInt<1>(0h0)) when _T_610 : node _T_611 = eq(_T_608, UInt<1>(0h0)) when _T_611 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_608, UInt<1>(0h1), "") : assert_26 node _T_612 = asUInt(reset) node _T_613 = eq(_T_612, UInt<1>(0h0)) when _T_613 : node _T_614 = eq(source_ok, UInt<1>(0h0)) when _T_614 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_615 = asUInt(reset) node _T_616 = eq(_T_615, UInt<1>(0h0)) when _T_616 : node _T_617 = eq(is_aligned, UInt<1>(0h0)) when _T_617 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_618 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_619 = asUInt(reset) node _T_620 = eq(_T_619, UInt<1>(0h0)) when _T_620 : node _T_621 = eq(_T_618, UInt<1>(0h0)) when _T_621 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_618, UInt<1>(0h1), "") : assert_29 node _T_622 = eq(io.in.a.bits.mask, mask) node _T_623 = asUInt(reset) node _T_624 = eq(_T_623, UInt<1>(0h0)) when _T_624 : node _T_625 = eq(_T_622, UInt<1>(0h0)) when _T_625 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_622, UInt<1>(0h1), "") : assert_30 node _T_626 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_626 : node _T_627 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_628 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_629 = and(_T_627, _T_628) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_630 = shr(io.in.a.bits.source, 2) node _T_631 = eq(_T_630, UInt<1>(0h0)) node _T_632 = leq(UInt<1>(0h0), uncommonBits_20) node _T_633 = and(_T_631, _T_632) node _T_634 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_635 = and(_T_633, _T_634) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_636 = shr(io.in.a.bits.source, 2) node _T_637 = eq(_T_636, UInt<1>(0h1)) node _T_638 = leq(UInt<1>(0h0), uncommonBits_21) node _T_639 = and(_T_637, _T_638) node _T_640 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_641 = and(_T_639, _T_640) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_642 = shr(io.in.a.bits.source, 2) node _T_643 = eq(_T_642, UInt<2>(0h2)) node _T_644 = leq(UInt<1>(0h0), uncommonBits_22) node _T_645 = and(_T_643, _T_644) node _T_646 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_647 = and(_T_645, _T_646) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_648 = shr(io.in.a.bits.source, 2) node _T_649 = eq(_T_648, UInt<2>(0h3)) node _T_650 = leq(UInt<1>(0h0), uncommonBits_23) node _T_651 = and(_T_649, _T_650) node _T_652 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_653 = and(_T_651, _T_652) node _T_654 = or(_T_635, _T_641) node _T_655 = or(_T_654, _T_647) node _T_656 = or(_T_655, _T_653) node _T_657 = and(_T_629, _T_656) node _T_658 = or(UInt<1>(0h0), _T_657) node _T_659 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_660 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_661 = and(_T_659, _T_660) node _T_662 = or(UInt<1>(0h0), _T_661) node _T_663 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_664 = cvt(_T_663) node _T_665 = and(_T_664, asSInt(UInt<13>(0h1000))) node _T_666 = asSInt(_T_665) node _T_667 = eq(_T_666, asSInt(UInt<1>(0h0))) node _T_668 = and(_T_662, _T_667) node _T_669 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_670 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_671 = and(_T_669, _T_670) node _T_672 = or(UInt<1>(0h0), _T_671) node _T_673 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_674 = cvt(_T_673) node _T_675 = and(_T_674, asSInt(UInt<14>(0h2000))) node _T_676 = asSInt(_T_675) node _T_677 = eq(_T_676, asSInt(UInt<1>(0h0))) node _T_678 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_679 = cvt(_T_678) node _T_680 = and(_T_679, asSInt(UInt<18>(0h2f000))) node _T_681 = asSInt(_T_680) node _T_682 = eq(_T_681, asSInt(UInt<1>(0h0))) node _T_683 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_684 = cvt(_T_683) node _T_685 = and(_T_684, asSInt(UInt<17>(0h10000))) node _T_686 = asSInt(_T_685) node _T_687 = eq(_T_686, asSInt(UInt<1>(0h0))) node _T_688 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_689 = cvt(_T_688) node _T_690 = and(_T_689, asSInt(UInt<27>(0h4000000))) node _T_691 = asSInt(_T_690) node _T_692 = eq(_T_691, asSInt(UInt<1>(0h0))) node _T_693 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_694 = cvt(_T_693) node _T_695 = and(_T_694, asSInt(UInt<13>(0h1000))) node _T_696 = asSInt(_T_695) node _T_697 = eq(_T_696, asSInt(UInt<1>(0h0))) node _T_698 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_699 = cvt(_T_698) node _T_700 = and(_T_699, asSInt(UInt<19>(0h40000))) node _T_701 = asSInt(_T_700) node _T_702 = eq(_T_701, asSInt(UInt<1>(0h0))) node _T_703 = or(_T_677, _T_682) node _T_704 = or(_T_703, _T_687) node _T_705 = or(_T_704, _T_692) node _T_706 = or(_T_705, _T_697) node _T_707 = or(_T_706, _T_702) node _T_708 = and(_T_672, _T_707) node _T_709 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_710 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_711 = cvt(_T_710) node _T_712 = and(_T_711, asSInt(UInt<17>(0h10000))) node _T_713 = asSInt(_T_712) node _T_714 = eq(_T_713, asSInt(UInt<1>(0h0))) node _T_715 = and(_T_709, _T_714) node _T_716 = or(UInt<1>(0h0), _T_668) node _T_717 = or(_T_716, _T_708) node _T_718 = or(_T_717, _T_715) node _T_719 = and(_T_658, _T_718) node _T_720 = asUInt(reset) node _T_721 = eq(_T_720, UInt<1>(0h0)) when _T_721 : node _T_722 = eq(_T_719, UInt<1>(0h0)) when _T_722 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_719, UInt<1>(0h1), "") : assert_31 node _T_723 = asUInt(reset) node _T_724 = eq(_T_723, UInt<1>(0h0)) when _T_724 : node _T_725 = eq(source_ok, UInt<1>(0h0)) when _T_725 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_726 = asUInt(reset) node _T_727 = eq(_T_726, UInt<1>(0h0)) when _T_727 : node _T_728 = eq(is_aligned, UInt<1>(0h0)) when _T_728 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_729 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_730 = asUInt(reset) node _T_731 = eq(_T_730, UInt<1>(0h0)) when _T_731 : node _T_732 = eq(_T_729, UInt<1>(0h0)) when _T_732 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_729, UInt<1>(0h1), "") : assert_34 node _T_733 = not(mask) node _T_734 = and(io.in.a.bits.mask, _T_733) node _T_735 = eq(_T_734, UInt<1>(0h0)) node _T_736 = asUInt(reset) node _T_737 = eq(_T_736, UInt<1>(0h0)) when _T_737 : node _T_738 = eq(_T_735, UInt<1>(0h0)) when _T_738 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_735, UInt<1>(0h1), "") : assert_35 node _T_739 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_739 : node _T_740 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_741 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_742 = and(_T_740, _T_741) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_743 = shr(io.in.a.bits.source, 2) node _T_744 = eq(_T_743, UInt<1>(0h0)) node _T_745 = leq(UInt<1>(0h0), uncommonBits_24) node _T_746 = and(_T_744, _T_745) node _T_747 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_748 = and(_T_746, _T_747) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_749 = shr(io.in.a.bits.source, 2) node _T_750 = eq(_T_749, UInt<1>(0h1)) node _T_751 = leq(UInt<1>(0h0), uncommonBits_25) node _T_752 = and(_T_750, _T_751) node _T_753 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_754 = and(_T_752, _T_753) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_755 = shr(io.in.a.bits.source, 2) node _T_756 = eq(_T_755, UInt<2>(0h2)) node _T_757 = leq(UInt<1>(0h0), uncommonBits_26) node _T_758 = and(_T_756, _T_757) node _T_759 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_760 = and(_T_758, _T_759) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_761 = shr(io.in.a.bits.source, 2) node _T_762 = eq(_T_761, UInt<2>(0h3)) node _T_763 = leq(UInt<1>(0h0), uncommonBits_27) node _T_764 = and(_T_762, _T_763) node _T_765 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_766 = and(_T_764, _T_765) node _T_767 = or(_T_748, _T_754) node _T_768 = or(_T_767, _T_760) node _T_769 = or(_T_768, _T_766) node _T_770 = and(_T_742, _T_769) node _T_771 = or(UInt<1>(0h0), _T_770) node _T_772 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_773 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_774 = and(_T_772, _T_773) node _T_775 = or(UInt<1>(0h0), _T_774) node _T_776 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_777 = cvt(_T_776) node _T_778 = and(_T_777, asSInt(UInt<14>(0h2000))) node _T_779 = asSInt(_T_778) node _T_780 = eq(_T_779, asSInt(UInt<1>(0h0))) node _T_781 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_782 = cvt(_T_781) node _T_783 = and(_T_782, asSInt(UInt<13>(0h1000))) node _T_784 = asSInt(_T_783) node _T_785 = eq(_T_784, asSInt(UInt<1>(0h0))) node _T_786 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_787 = cvt(_T_786) node _T_788 = and(_T_787, asSInt(UInt<18>(0h2f000))) node _T_789 = asSInt(_T_788) node _T_790 = eq(_T_789, asSInt(UInt<1>(0h0))) node _T_791 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_792 = cvt(_T_791) node _T_793 = and(_T_792, asSInt(UInt<17>(0h10000))) node _T_794 = asSInt(_T_793) node _T_795 = eq(_T_794, asSInt(UInt<1>(0h0))) node _T_796 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_797 = cvt(_T_796) node _T_798 = and(_T_797, asSInt(UInt<27>(0h4000000))) node _T_799 = asSInt(_T_798) node _T_800 = eq(_T_799, asSInt(UInt<1>(0h0))) node _T_801 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_802 = cvt(_T_801) node _T_803 = and(_T_802, asSInt(UInt<13>(0h1000))) node _T_804 = asSInt(_T_803) node _T_805 = eq(_T_804, asSInt(UInt<1>(0h0))) node _T_806 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_807 = cvt(_T_806) node _T_808 = and(_T_807, asSInt(UInt<19>(0h40000))) node _T_809 = asSInt(_T_808) node _T_810 = eq(_T_809, asSInt(UInt<1>(0h0))) node _T_811 = or(_T_780, _T_785) node _T_812 = or(_T_811, _T_790) node _T_813 = or(_T_812, _T_795) node _T_814 = or(_T_813, _T_800) node _T_815 = or(_T_814, _T_805) node _T_816 = or(_T_815, _T_810) node _T_817 = and(_T_775, _T_816) node _T_818 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_819 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_820 = cvt(_T_819) node _T_821 = and(_T_820, asSInt(UInt<17>(0h10000))) node _T_822 = asSInt(_T_821) node _T_823 = eq(_T_822, asSInt(UInt<1>(0h0))) node _T_824 = and(_T_818, _T_823) node _T_825 = or(UInt<1>(0h0), _T_817) node _T_826 = or(_T_825, _T_824) node _T_827 = and(_T_771, _T_826) node _T_828 = asUInt(reset) node _T_829 = eq(_T_828, UInt<1>(0h0)) when _T_829 : node _T_830 = eq(_T_827, UInt<1>(0h0)) when _T_830 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_827, UInt<1>(0h1), "") : assert_36 node _T_831 = asUInt(reset) node _T_832 = eq(_T_831, UInt<1>(0h0)) when _T_832 : node _T_833 = eq(source_ok, UInt<1>(0h0)) when _T_833 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_834 = asUInt(reset) node _T_835 = eq(_T_834, UInt<1>(0h0)) when _T_835 : node _T_836 = eq(is_aligned, UInt<1>(0h0)) when _T_836 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_837 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_838 = asUInt(reset) node _T_839 = eq(_T_838, UInt<1>(0h0)) when _T_839 : node _T_840 = eq(_T_837, UInt<1>(0h0)) when _T_840 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_837, UInt<1>(0h1), "") : assert_39 node _T_841 = eq(io.in.a.bits.mask, mask) node _T_842 = asUInt(reset) node _T_843 = eq(_T_842, UInt<1>(0h0)) when _T_843 : node _T_844 = eq(_T_841, UInt<1>(0h0)) when _T_844 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_841, UInt<1>(0h1), "") : assert_40 node _T_845 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_845 : node _T_846 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_847 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_848 = and(_T_846, _T_847) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_849 = shr(io.in.a.bits.source, 2) node _T_850 = eq(_T_849, UInt<1>(0h0)) node _T_851 = leq(UInt<1>(0h0), uncommonBits_28) node _T_852 = and(_T_850, _T_851) node _T_853 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_854 = and(_T_852, _T_853) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_855 = shr(io.in.a.bits.source, 2) node _T_856 = eq(_T_855, UInt<1>(0h1)) node _T_857 = leq(UInt<1>(0h0), uncommonBits_29) node _T_858 = and(_T_856, _T_857) node _T_859 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_860 = and(_T_858, _T_859) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_861 = shr(io.in.a.bits.source, 2) node _T_862 = eq(_T_861, UInt<2>(0h2)) node _T_863 = leq(UInt<1>(0h0), uncommonBits_30) node _T_864 = and(_T_862, _T_863) node _T_865 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_866 = and(_T_864, _T_865) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_867 = shr(io.in.a.bits.source, 2) node _T_868 = eq(_T_867, UInt<2>(0h3)) node _T_869 = leq(UInt<1>(0h0), uncommonBits_31) node _T_870 = and(_T_868, _T_869) node _T_871 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_872 = and(_T_870, _T_871) node _T_873 = or(_T_854, _T_860) node _T_874 = or(_T_873, _T_866) node _T_875 = or(_T_874, _T_872) node _T_876 = and(_T_848, _T_875) node _T_877 = or(UInt<1>(0h0), _T_876) node _T_878 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_879 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_880 = and(_T_878, _T_879) node _T_881 = or(UInt<1>(0h0), _T_880) node _T_882 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_883 = cvt(_T_882) node _T_884 = and(_T_883, asSInt(UInt<14>(0h2000))) node _T_885 = asSInt(_T_884) node _T_886 = eq(_T_885, asSInt(UInt<1>(0h0))) node _T_887 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_888 = cvt(_T_887) node _T_889 = and(_T_888, asSInt(UInt<13>(0h1000))) node _T_890 = asSInt(_T_889) node _T_891 = eq(_T_890, asSInt(UInt<1>(0h0))) node _T_892 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_893 = cvt(_T_892) node _T_894 = and(_T_893, asSInt(UInt<18>(0h2f000))) node _T_895 = asSInt(_T_894) node _T_896 = eq(_T_895, asSInt(UInt<1>(0h0))) node _T_897 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_898 = cvt(_T_897) node _T_899 = and(_T_898, asSInt(UInt<17>(0h10000))) node _T_900 = asSInt(_T_899) node _T_901 = eq(_T_900, asSInt(UInt<1>(0h0))) node _T_902 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_903 = cvt(_T_902) node _T_904 = and(_T_903, asSInt(UInt<27>(0h4000000))) node _T_905 = asSInt(_T_904) node _T_906 = eq(_T_905, asSInt(UInt<1>(0h0))) node _T_907 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_908 = cvt(_T_907) node _T_909 = and(_T_908, asSInt(UInt<13>(0h1000))) node _T_910 = asSInt(_T_909) node _T_911 = eq(_T_910, asSInt(UInt<1>(0h0))) node _T_912 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_913 = cvt(_T_912) node _T_914 = and(_T_913, asSInt(UInt<19>(0h40000))) node _T_915 = asSInt(_T_914) node _T_916 = eq(_T_915, asSInt(UInt<1>(0h0))) node _T_917 = or(_T_886, _T_891) node _T_918 = or(_T_917, _T_896) node _T_919 = or(_T_918, _T_901) node _T_920 = or(_T_919, _T_906) node _T_921 = or(_T_920, _T_911) node _T_922 = or(_T_921, _T_916) node _T_923 = and(_T_881, _T_922) node _T_924 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_925 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_926 = cvt(_T_925) node _T_927 = and(_T_926, asSInt(UInt<17>(0h10000))) node _T_928 = asSInt(_T_927) node _T_929 = eq(_T_928, asSInt(UInt<1>(0h0))) node _T_930 = and(_T_924, _T_929) node _T_931 = or(UInt<1>(0h0), _T_923) node _T_932 = or(_T_931, _T_930) node _T_933 = and(_T_877, _T_932) node _T_934 = asUInt(reset) node _T_935 = eq(_T_934, UInt<1>(0h0)) when _T_935 : node _T_936 = eq(_T_933, UInt<1>(0h0)) when _T_936 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_933, UInt<1>(0h1), "") : assert_41 node _T_937 = asUInt(reset) node _T_938 = eq(_T_937, UInt<1>(0h0)) when _T_938 : node _T_939 = eq(source_ok, UInt<1>(0h0)) when _T_939 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_940 = asUInt(reset) node _T_941 = eq(_T_940, UInt<1>(0h0)) when _T_941 : node _T_942 = eq(is_aligned, UInt<1>(0h0)) when _T_942 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_943 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_944 = asUInt(reset) node _T_945 = eq(_T_944, UInt<1>(0h0)) when _T_945 : node _T_946 = eq(_T_943, UInt<1>(0h0)) when _T_946 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_943, UInt<1>(0h1), "") : assert_44 node _T_947 = eq(io.in.a.bits.mask, mask) node _T_948 = asUInt(reset) node _T_949 = eq(_T_948, UInt<1>(0h0)) when _T_949 : node _T_950 = eq(_T_947, UInt<1>(0h0)) when _T_950 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_947, UInt<1>(0h1), "") : assert_45 node _T_951 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_951 : node _T_952 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_953 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_954 = and(_T_952, _T_953) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_955 = shr(io.in.a.bits.source, 2) node _T_956 = eq(_T_955, UInt<1>(0h0)) node _T_957 = leq(UInt<1>(0h0), uncommonBits_32) node _T_958 = and(_T_956, _T_957) node _T_959 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_960 = and(_T_958, _T_959) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_961 = shr(io.in.a.bits.source, 2) node _T_962 = eq(_T_961, UInt<1>(0h1)) node _T_963 = leq(UInt<1>(0h0), uncommonBits_33) node _T_964 = and(_T_962, _T_963) node _T_965 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_966 = and(_T_964, _T_965) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_967 = shr(io.in.a.bits.source, 2) node _T_968 = eq(_T_967, UInt<2>(0h2)) node _T_969 = leq(UInt<1>(0h0), uncommonBits_34) node _T_970 = and(_T_968, _T_969) node _T_971 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_972 = and(_T_970, _T_971) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_973 = shr(io.in.a.bits.source, 2) node _T_974 = eq(_T_973, UInt<2>(0h3)) node _T_975 = leq(UInt<1>(0h0), uncommonBits_35) node _T_976 = and(_T_974, _T_975) node _T_977 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_978 = and(_T_976, _T_977) node _T_979 = or(_T_960, _T_966) node _T_980 = or(_T_979, _T_972) node _T_981 = or(_T_980, _T_978) node _T_982 = and(_T_954, _T_981) node _T_983 = or(UInt<1>(0h0), _T_982) node _T_984 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_985 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_986 = and(_T_984, _T_985) node _T_987 = or(UInt<1>(0h0), _T_986) node _T_988 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_989 = cvt(_T_988) node _T_990 = and(_T_989, asSInt(UInt<13>(0h1000))) node _T_991 = asSInt(_T_990) node _T_992 = eq(_T_991, asSInt(UInt<1>(0h0))) node _T_993 = and(_T_987, _T_992) node _T_994 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_995 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_996 = cvt(_T_995) node _T_997 = and(_T_996, asSInt(UInt<14>(0h2000))) node _T_998 = asSInt(_T_997) node _T_999 = eq(_T_998, asSInt(UInt<1>(0h0))) node _T_1000 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1001 = cvt(_T_1000) node _T_1002 = and(_T_1001, asSInt(UInt<17>(0h10000))) node _T_1003 = asSInt(_T_1002) node _T_1004 = eq(_T_1003, asSInt(UInt<1>(0h0))) node _T_1005 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1006 = cvt(_T_1005) node _T_1007 = and(_T_1006, asSInt(UInt<18>(0h2f000))) node _T_1008 = asSInt(_T_1007) node _T_1009 = eq(_T_1008, asSInt(UInt<1>(0h0))) node _T_1010 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1011 = cvt(_T_1010) node _T_1012 = and(_T_1011, asSInt(UInt<17>(0h10000))) node _T_1013 = asSInt(_T_1012) node _T_1014 = eq(_T_1013, asSInt(UInt<1>(0h0))) node _T_1015 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1016 = cvt(_T_1015) node _T_1017 = and(_T_1016, asSInt(UInt<27>(0h4000000))) node _T_1018 = asSInt(_T_1017) node _T_1019 = eq(_T_1018, asSInt(UInt<1>(0h0))) node _T_1020 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1021 = cvt(_T_1020) node _T_1022 = and(_T_1021, asSInt(UInt<13>(0h1000))) node _T_1023 = asSInt(_T_1022) node _T_1024 = eq(_T_1023, asSInt(UInt<1>(0h0))) node _T_1025 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_1026 = cvt(_T_1025) node _T_1027 = and(_T_1026, asSInt(UInt<19>(0h40000))) node _T_1028 = asSInt(_T_1027) node _T_1029 = eq(_T_1028, asSInt(UInt<1>(0h0))) node _T_1030 = or(_T_999, _T_1004) node _T_1031 = or(_T_1030, _T_1009) node _T_1032 = or(_T_1031, _T_1014) node _T_1033 = or(_T_1032, _T_1019) node _T_1034 = or(_T_1033, _T_1024) node _T_1035 = or(_T_1034, _T_1029) node _T_1036 = and(_T_994, _T_1035) node _T_1037 = or(UInt<1>(0h0), _T_993) node _T_1038 = or(_T_1037, _T_1036) node _T_1039 = and(_T_983, _T_1038) node _T_1040 = asUInt(reset) node _T_1041 = eq(_T_1040, UInt<1>(0h0)) when _T_1041 : node _T_1042 = eq(_T_1039, UInt<1>(0h0)) when _T_1042 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1039, UInt<1>(0h1), "") : assert_46 node _T_1043 = asUInt(reset) node _T_1044 = eq(_T_1043, UInt<1>(0h0)) when _T_1044 : node _T_1045 = eq(source_ok, UInt<1>(0h0)) when _T_1045 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1046 = asUInt(reset) node _T_1047 = eq(_T_1046, UInt<1>(0h0)) when _T_1047 : node _T_1048 = eq(is_aligned, UInt<1>(0h0)) when _T_1048 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1049 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_T_1049, UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1049, UInt<1>(0h1), "") : assert_49 node _T_1053 = eq(io.in.a.bits.mask, mask) node _T_1054 = asUInt(reset) node _T_1055 = eq(_T_1054, UInt<1>(0h0)) when _T_1055 : node _T_1056 = eq(_T_1053, UInt<1>(0h0)) when _T_1056 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1053, UInt<1>(0h1), "") : assert_50 node _T_1057 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1058 = asUInt(reset) node _T_1059 = eq(_T_1058, UInt<1>(0h0)) when _T_1059 : node _T_1060 = eq(_T_1057, UInt<1>(0h0)) when _T_1060 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1057, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1061 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1062 = asUInt(reset) node _T_1063 = eq(_T_1062, UInt<1>(0h0)) when _T_1063 : node _T_1064 = eq(_T_1061, UInt<1>(0h0)) when _T_1064 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1061, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_26 = shr(io.in.d.bits.source, 2) node _source_ok_T_27 = eq(_source_ok_T_26, UInt<1>(0h0)) node _source_ok_T_28 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_29 = and(_source_ok_T_27, _source_ok_T_28) node _source_ok_T_30 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_31 = and(_source_ok_T_29, _source_ok_T_30) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_32 = shr(io.in.d.bits.source, 2) node _source_ok_T_33 = eq(_source_ok_T_32, UInt<1>(0h1)) node _source_ok_T_34 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_35 = and(_source_ok_T_33, _source_ok_T_34) node _source_ok_T_36 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_37 = and(_source_ok_T_35, _source_ok_T_36) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_38 = shr(io.in.d.bits.source, 2) node _source_ok_T_39 = eq(_source_ok_T_38, UInt<2>(0h2)) node _source_ok_T_40 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_41 = and(_source_ok_T_39, _source_ok_T_40) node _source_ok_T_42 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_43 = and(_source_ok_T_41, _source_ok_T_42) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_44 = shr(io.in.d.bits.source, 2) node _source_ok_T_45 = eq(_source_ok_T_44, UInt<2>(0h3)) node _source_ok_T_46 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_47 = and(_source_ok_T_45, _source_ok_T_46) node _source_ok_T_48 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_49 = and(_source_ok_T_47, _source_ok_T_48) wire _source_ok_WIRE_1 : UInt<1>[4] connect _source_ok_WIRE_1[0], _source_ok_T_31 connect _source_ok_WIRE_1[1], _source_ok_T_37 connect _source_ok_WIRE_1[2], _source_ok_T_43 connect _source_ok_WIRE_1[3], _source_ok_T_49 node _source_ok_T_50 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_51 = or(_source_ok_T_50, _source_ok_WIRE_1[2]) node source_ok_1 = or(_source_ok_T_51, _source_ok_WIRE_1[3]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_1065 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1065 : node _T_1066 = asUInt(reset) node _T_1067 = eq(_T_1066, UInt<1>(0h0)) when _T_1067 : node _T_1068 = eq(source_ok_1, UInt<1>(0h0)) when _T_1068 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1069 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1070 = asUInt(reset) node _T_1071 = eq(_T_1070, UInt<1>(0h0)) when _T_1071 : node _T_1072 = eq(_T_1069, UInt<1>(0h0)) when _T_1072 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1069, UInt<1>(0h1), "") : assert_54 node _T_1073 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1074 = asUInt(reset) node _T_1075 = eq(_T_1074, UInt<1>(0h0)) when _T_1075 : node _T_1076 = eq(_T_1073, UInt<1>(0h0)) when _T_1076 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1073, UInt<1>(0h1), "") : assert_55 node _T_1077 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1078 = asUInt(reset) node _T_1079 = eq(_T_1078, UInt<1>(0h0)) when _T_1079 : node _T_1080 = eq(_T_1077, UInt<1>(0h0)) when _T_1080 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1077, UInt<1>(0h1), "") : assert_56 node _T_1081 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1082 = asUInt(reset) node _T_1083 = eq(_T_1082, UInt<1>(0h0)) when _T_1083 : node _T_1084 = eq(_T_1081, UInt<1>(0h0)) when _T_1084 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1081, UInt<1>(0h1), "") : assert_57 node _T_1085 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1085 : node _T_1086 = asUInt(reset) node _T_1087 = eq(_T_1086, UInt<1>(0h0)) when _T_1087 : node _T_1088 = eq(source_ok_1, UInt<1>(0h0)) when _T_1088 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1089 = asUInt(reset) node _T_1090 = eq(_T_1089, UInt<1>(0h0)) when _T_1090 : node _T_1091 = eq(sink_ok, UInt<1>(0h0)) when _T_1091 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1092 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1093 = asUInt(reset) node _T_1094 = eq(_T_1093, UInt<1>(0h0)) when _T_1094 : node _T_1095 = eq(_T_1092, UInt<1>(0h0)) when _T_1095 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1092, UInt<1>(0h1), "") : assert_60 node _T_1096 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1097 = asUInt(reset) node _T_1098 = eq(_T_1097, UInt<1>(0h0)) when _T_1098 : node _T_1099 = eq(_T_1096, UInt<1>(0h0)) when _T_1099 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1096, UInt<1>(0h1), "") : assert_61 node _T_1100 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1101 = asUInt(reset) node _T_1102 = eq(_T_1101, UInt<1>(0h0)) when _T_1102 : node _T_1103 = eq(_T_1100, UInt<1>(0h0)) when _T_1103 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1100, UInt<1>(0h1), "") : assert_62 node _T_1104 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1105 = asUInt(reset) node _T_1106 = eq(_T_1105, UInt<1>(0h0)) when _T_1106 : node _T_1107 = eq(_T_1104, UInt<1>(0h0)) when _T_1107 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1104, UInt<1>(0h1), "") : assert_63 node _T_1108 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1109 = or(UInt<1>(0h1), _T_1108) node _T_1110 = asUInt(reset) node _T_1111 = eq(_T_1110, UInt<1>(0h0)) when _T_1111 : node _T_1112 = eq(_T_1109, UInt<1>(0h0)) when _T_1112 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1109, UInt<1>(0h1), "") : assert_64 node _T_1113 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1113 : node _T_1114 = asUInt(reset) node _T_1115 = eq(_T_1114, UInt<1>(0h0)) when _T_1115 : node _T_1116 = eq(source_ok_1, UInt<1>(0h0)) when _T_1116 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1117 = asUInt(reset) node _T_1118 = eq(_T_1117, UInt<1>(0h0)) when _T_1118 : node _T_1119 = eq(sink_ok, UInt<1>(0h0)) when _T_1119 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1120 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1121 = asUInt(reset) node _T_1122 = eq(_T_1121, UInt<1>(0h0)) when _T_1122 : node _T_1123 = eq(_T_1120, UInt<1>(0h0)) when _T_1123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1120, UInt<1>(0h1), "") : assert_67 node _T_1124 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1125 = asUInt(reset) node _T_1126 = eq(_T_1125, UInt<1>(0h0)) when _T_1126 : node _T_1127 = eq(_T_1124, UInt<1>(0h0)) when _T_1127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1124, UInt<1>(0h1), "") : assert_68 node _T_1128 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1129 = asUInt(reset) node _T_1130 = eq(_T_1129, UInt<1>(0h0)) when _T_1130 : node _T_1131 = eq(_T_1128, UInt<1>(0h0)) when _T_1131 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1128, UInt<1>(0h1), "") : assert_69 node _T_1132 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1133 = or(_T_1132, io.in.d.bits.corrupt) node _T_1134 = asUInt(reset) node _T_1135 = eq(_T_1134, UInt<1>(0h0)) when _T_1135 : node _T_1136 = eq(_T_1133, UInt<1>(0h0)) when _T_1136 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1133, UInt<1>(0h1), "") : assert_70 node _T_1137 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1138 = or(UInt<1>(0h1), _T_1137) node _T_1139 = asUInt(reset) node _T_1140 = eq(_T_1139, UInt<1>(0h0)) when _T_1140 : node _T_1141 = eq(_T_1138, UInt<1>(0h0)) when _T_1141 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1138, UInt<1>(0h1), "") : assert_71 node _T_1142 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1142 : node _T_1143 = asUInt(reset) node _T_1144 = eq(_T_1143, UInt<1>(0h0)) when _T_1144 : node _T_1145 = eq(source_ok_1, UInt<1>(0h0)) when _T_1145 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1146 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1147 = asUInt(reset) node _T_1148 = eq(_T_1147, UInt<1>(0h0)) when _T_1148 : node _T_1149 = eq(_T_1146, UInt<1>(0h0)) when _T_1149 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1146, UInt<1>(0h1), "") : assert_73 node _T_1150 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1151 = asUInt(reset) node _T_1152 = eq(_T_1151, UInt<1>(0h0)) when _T_1152 : node _T_1153 = eq(_T_1150, UInt<1>(0h0)) when _T_1153 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1150, UInt<1>(0h1), "") : assert_74 node _T_1154 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1155 = or(UInt<1>(0h1), _T_1154) node _T_1156 = asUInt(reset) node _T_1157 = eq(_T_1156, UInt<1>(0h0)) when _T_1157 : node _T_1158 = eq(_T_1155, UInt<1>(0h0)) when _T_1158 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1155, UInt<1>(0h1), "") : assert_75 node _T_1159 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1159 : node _T_1160 = asUInt(reset) node _T_1161 = eq(_T_1160, UInt<1>(0h0)) when _T_1161 : node _T_1162 = eq(source_ok_1, UInt<1>(0h0)) when _T_1162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1163 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1164 = asUInt(reset) node _T_1165 = eq(_T_1164, UInt<1>(0h0)) when _T_1165 : node _T_1166 = eq(_T_1163, UInt<1>(0h0)) when _T_1166 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1163, UInt<1>(0h1), "") : assert_77 node _T_1167 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1168 = or(_T_1167, io.in.d.bits.corrupt) node _T_1169 = asUInt(reset) node _T_1170 = eq(_T_1169, UInt<1>(0h0)) when _T_1170 : node _T_1171 = eq(_T_1168, UInt<1>(0h0)) when _T_1171 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1168, UInt<1>(0h1), "") : assert_78 node _T_1172 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1173 = or(UInt<1>(0h1), _T_1172) node _T_1174 = asUInt(reset) node _T_1175 = eq(_T_1174, UInt<1>(0h0)) when _T_1175 : node _T_1176 = eq(_T_1173, UInt<1>(0h0)) when _T_1176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1173, UInt<1>(0h1), "") : assert_79 node _T_1177 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1177 : node _T_1178 = asUInt(reset) node _T_1179 = eq(_T_1178, UInt<1>(0h0)) when _T_1179 : node _T_1180 = eq(source_ok_1, UInt<1>(0h0)) when _T_1180 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1181 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1182 = asUInt(reset) node _T_1183 = eq(_T_1182, UInt<1>(0h0)) when _T_1183 : node _T_1184 = eq(_T_1181, UInt<1>(0h0)) when _T_1184 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1181, UInt<1>(0h1), "") : assert_81 node _T_1185 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1186 = asUInt(reset) node _T_1187 = eq(_T_1186, UInt<1>(0h0)) when _T_1187 : node _T_1188 = eq(_T_1185, UInt<1>(0h0)) when _T_1188 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1185, UInt<1>(0h1), "") : assert_82 node _T_1189 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1190 = or(UInt<1>(0h1), _T_1189) node _T_1191 = asUInt(reset) node _T_1192 = eq(_T_1191, UInt<1>(0h0)) when _T_1192 : node _T_1193 = eq(_T_1190, UInt<1>(0h0)) when _T_1193 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1190, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<4>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1194 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_1195 = asUInt(reset) node _T_1196 = eq(_T_1195, UInt<1>(0h0)) when _T_1196 : node _T_1197 = eq(_T_1194, UInt<1>(0h0)) when _T_1197 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1194, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<4>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_1198 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_1199 = asUInt(reset) node _T_1200 = eq(_T_1199, UInt<1>(0h0)) when _T_1200 : node _T_1201 = eq(_T_1198, UInt<1>(0h0)) when _T_1201 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1198, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1202 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1203 = asUInt(reset) node _T_1204 = eq(_T_1203, UInt<1>(0h0)) when _T_1204 : node _T_1205 = eq(_T_1202, UInt<1>(0h0)) when _T_1205 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1202, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1206 = eq(a_first, UInt<1>(0h0)) node _T_1207 = and(io.in.a.valid, _T_1206) when _T_1207 : node _T_1208 = eq(io.in.a.bits.opcode, opcode) node _T_1209 = asUInt(reset) node _T_1210 = eq(_T_1209, UInt<1>(0h0)) when _T_1210 : node _T_1211 = eq(_T_1208, UInt<1>(0h0)) when _T_1211 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1208, UInt<1>(0h1), "") : assert_87 node _T_1212 = eq(io.in.a.bits.param, param) node _T_1213 = asUInt(reset) node _T_1214 = eq(_T_1213, UInt<1>(0h0)) when _T_1214 : node _T_1215 = eq(_T_1212, UInt<1>(0h0)) when _T_1215 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1212, UInt<1>(0h1), "") : assert_88 node _T_1216 = eq(io.in.a.bits.size, size) node _T_1217 = asUInt(reset) node _T_1218 = eq(_T_1217, UInt<1>(0h0)) when _T_1218 : node _T_1219 = eq(_T_1216, UInt<1>(0h0)) when _T_1219 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1216, UInt<1>(0h1), "") : assert_89 node _T_1220 = eq(io.in.a.bits.source, source) node _T_1221 = asUInt(reset) node _T_1222 = eq(_T_1221, UInt<1>(0h0)) when _T_1222 : node _T_1223 = eq(_T_1220, UInt<1>(0h0)) when _T_1223 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1220, UInt<1>(0h1), "") : assert_90 node _T_1224 = eq(io.in.a.bits.address, address) node _T_1225 = asUInt(reset) node _T_1226 = eq(_T_1225, UInt<1>(0h0)) when _T_1226 : node _T_1227 = eq(_T_1224, UInt<1>(0h0)) when _T_1227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1224, UInt<1>(0h1), "") : assert_91 node _T_1228 = and(io.in.a.ready, io.in.a.valid) node _T_1229 = and(_T_1228, a_first) when _T_1229 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1230 = eq(d_first, UInt<1>(0h0)) node _T_1231 = and(io.in.d.valid, _T_1230) when _T_1231 : node _T_1232 = eq(io.in.d.bits.opcode, opcode_1) node _T_1233 = asUInt(reset) node _T_1234 = eq(_T_1233, UInt<1>(0h0)) when _T_1234 : node _T_1235 = eq(_T_1232, UInt<1>(0h0)) when _T_1235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1232, UInt<1>(0h1), "") : assert_92 node _T_1236 = eq(io.in.d.bits.param, param_1) node _T_1237 = asUInt(reset) node _T_1238 = eq(_T_1237, UInt<1>(0h0)) when _T_1238 : node _T_1239 = eq(_T_1236, UInt<1>(0h0)) when _T_1239 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1236, UInt<1>(0h1), "") : assert_93 node _T_1240 = eq(io.in.d.bits.size, size_1) node _T_1241 = asUInt(reset) node _T_1242 = eq(_T_1241, UInt<1>(0h0)) when _T_1242 : node _T_1243 = eq(_T_1240, UInt<1>(0h0)) when _T_1243 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1240, UInt<1>(0h1), "") : assert_94 node _T_1244 = eq(io.in.d.bits.source, source_1) node _T_1245 = asUInt(reset) node _T_1246 = eq(_T_1245, UInt<1>(0h0)) when _T_1246 : node _T_1247 = eq(_T_1244, UInt<1>(0h0)) when _T_1247 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1244, UInt<1>(0h1), "") : assert_95 node _T_1248 = eq(io.in.d.bits.sink, sink) node _T_1249 = asUInt(reset) node _T_1250 = eq(_T_1249, UInt<1>(0h0)) when _T_1250 : node _T_1251 = eq(_T_1248, UInt<1>(0h0)) when _T_1251 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1248, UInt<1>(0h1), "") : assert_96 node _T_1252 = eq(io.in.d.bits.denied, denied) node _T_1253 = asUInt(reset) node _T_1254 = eq(_T_1253, UInt<1>(0h0)) when _T_1254 : node _T_1255 = eq(_T_1252, UInt<1>(0h0)) when _T_1255 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1252, UInt<1>(0h1), "") : assert_97 node _T_1256 = and(io.in.d.ready, io.in.d.valid) node _T_1257 = and(_T_1256, d_first) when _T_1257 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<16>, clock, reset, UInt<16>(0h0) regreset inflight_opcodes : UInt<64>, clock, reset, UInt<64>(0h0) regreset inflight_sizes : UInt<128>, clock, reset, UInt<128>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<16> connect a_set, UInt<16>(0h0) wire a_set_wo_ready : UInt<16> connect a_set_wo_ready, UInt<16>(0h0) wire a_opcodes_set : UInt<64> connect a_opcodes_set, UInt<64>(0h0) wire a_sizes_set : UInt<128> connect a_sizes_set, UInt<128>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1258 = and(io.in.a.valid, a_first_1) node _T_1259 = and(_T_1258, UInt<1>(0h1)) when _T_1259 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1260 = and(io.in.a.ready, io.in.a.valid) node _T_1261 = and(_T_1260, a_first_1) node _T_1262 = and(_T_1261, UInt<1>(0h1)) when _T_1262 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1263 = dshr(inflight, io.in.a.bits.source) node _T_1264 = bits(_T_1263, 0, 0) node _T_1265 = eq(_T_1264, UInt<1>(0h0)) node _T_1266 = asUInt(reset) node _T_1267 = eq(_T_1266, UInt<1>(0h0)) when _T_1267 : node _T_1268 = eq(_T_1265, UInt<1>(0h0)) when _T_1268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1265, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<16> connect d_clr, UInt<16>(0h0) wire d_clr_wo_ready : UInt<16> connect d_clr_wo_ready, UInt<16>(0h0) wire d_opcodes_clr : UInt<64> connect d_opcodes_clr, UInt<64>(0h0) wire d_sizes_clr : UInt<128> connect d_sizes_clr, UInt<128>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1269 = and(io.in.d.valid, d_first_1) node _T_1270 = and(_T_1269, UInt<1>(0h1)) node _T_1271 = eq(d_release_ack, UInt<1>(0h0)) node _T_1272 = and(_T_1270, _T_1271) when _T_1272 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1273 = and(io.in.d.ready, io.in.d.valid) node _T_1274 = and(_T_1273, d_first_1) node _T_1275 = and(_T_1274, UInt<1>(0h1)) node _T_1276 = eq(d_release_ack, UInt<1>(0h0)) node _T_1277 = and(_T_1275, _T_1276) when _T_1277 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1278 = and(io.in.d.valid, d_first_1) node _T_1279 = and(_T_1278, UInt<1>(0h1)) node _T_1280 = eq(d_release_ack, UInt<1>(0h0)) node _T_1281 = and(_T_1279, _T_1280) when _T_1281 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1282 = dshr(inflight, io.in.d.bits.source) node _T_1283 = bits(_T_1282, 0, 0) node _T_1284 = or(_T_1283, same_cycle_resp) node _T_1285 = asUInt(reset) node _T_1286 = eq(_T_1285, UInt<1>(0h0)) when _T_1286 : node _T_1287 = eq(_T_1284, UInt<1>(0h0)) when _T_1287 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1284, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1288 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1289 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1290 = or(_T_1288, _T_1289) node _T_1291 = asUInt(reset) node _T_1292 = eq(_T_1291, UInt<1>(0h0)) when _T_1292 : node _T_1293 = eq(_T_1290, UInt<1>(0h0)) when _T_1293 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1290, UInt<1>(0h1), "") : assert_100 node _T_1294 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1295 = asUInt(reset) node _T_1296 = eq(_T_1295, UInt<1>(0h0)) when _T_1296 : node _T_1297 = eq(_T_1294, UInt<1>(0h0)) when _T_1297 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1294, UInt<1>(0h1), "") : assert_101 else : node _T_1298 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1299 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1300 = or(_T_1298, _T_1299) node _T_1301 = asUInt(reset) node _T_1302 = eq(_T_1301, UInt<1>(0h0)) when _T_1302 : node _T_1303 = eq(_T_1300, UInt<1>(0h0)) when _T_1303 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1300, UInt<1>(0h1), "") : assert_102 node _T_1304 = eq(io.in.d.bits.size, a_size_lookup) node _T_1305 = asUInt(reset) node _T_1306 = eq(_T_1305, UInt<1>(0h0)) when _T_1306 : node _T_1307 = eq(_T_1304, UInt<1>(0h0)) when _T_1307 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1304, UInt<1>(0h1), "") : assert_103 node _T_1308 = and(io.in.d.valid, d_first_1) node _T_1309 = and(_T_1308, a_first_1) node _T_1310 = and(_T_1309, io.in.a.valid) node _T_1311 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1312 = and(_T_1310, _T_1311) node _T_1313 = eq(d_release_ack, UInt<1>(0h0)) node _T_1314 = and(_T_1312, _T_1313) when _T_1314 : node _T_1315 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1316 = or(_T_1315, io.in.a.ready) node _T_1317 = asUInt(reset) node _T_1318 = eq(_T_1317, UInt<1>(0h0)) when _T_1318 : node _T_1319 = eq(_T_1316, UInt<1>(0h0)) when _T_1319 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1316, UInt<1>(0h1), "") : assert_104 node _T_1320 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1321 = orr(a_set_wo_ready) node _T_1322 = eq(_T_1321, UInt<1>(0h0)) node _T_1323 = or(_T_1320, _T_1322) node _T_1324 = asUInt(reset) node _T_1325 = eq(_T_1324, UInt<1>(0h0)) when _T_1325 : node _T_1326 = eq(_T_1323, UInt<1>(0h0)) when _T_1326 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1323, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_24 node _T_1327 = orr(inflight) node _T_1328 = eq(_T_1327, UInt<1>(0h0)) node _T_1329 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1330 = or(_T_1328, _T_1329) node _T_1331 = lt(watchdog, plusarg_reader.out) node _T_1332 = or(_T_1330, _T_1331) node _T_1333 = asUInt(reset) node _T_1334 = eq(_T_1333, UInt<1>(0h0)) when _T_1334 : node _T_1335 = eq(_T_1332, UInt<1>(0h0)) when _T_1335 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1332, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1336 = and(io.in.a.ready, io.in.a.valid) node _T_1337 = and(io.in.d.ready, io.in.d.valid) node _T_1338 = or(_T_1336, _T_1337) when _T_1338 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<16>, clock, reset, UInt<16>(0h0) regreset inflight_opcodes_1 : UInt<64>, clock, reset, UInt<64>(0h0) regreset inflight_sizes_1 : UInt<128>, clock, reset, UInt<128>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<4>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<4>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<16> connect c_set, UInt<16>(0h0) wire c_set_wo_ready : UInt<16> connect c_set_wo_ready, UInt<16>(0h0) wire c_opcodes_set : UInt<64> connect c_opcodes_set, UInt<64>(0h0) wire c_sizes_set : UInt<128> connect c_sizes_set, UInt<128>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<4>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1339 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<4>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1340 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1341 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1342 = and(_T_1340, _T_1341) node _T_1343 = and(_T_1339, _T_1342) when _T_1343 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<4>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1344 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1345 = and(_T_1344, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<4>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1346 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1347 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1348 = and(_T_1346, _T_1347) node _T_1349 = and(_T_1345, _T_1348) when _T_1349 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<4>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<4>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1350 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1351 = bits(_T_1350, 0, 0) node _T_1352 = eq(_T_1351, UInt<1>(0h0)) node _T_1353 = asUInt(reset) node _T_1354 = eq(_T_1353, UInt<1>(0h0)) when _T_1354 : node _T_1355 = eq(_T_1352, UInt<1>(0h0)) when _T_1355 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1352, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<16> connect d_clr_1, UInt<16>(0h0) wire d_clr_wo_ready_1 : UInt<16> connect d_clr_wo_ready_1, UInt<16>(0h0) wire d_opcodes_clr_1 : UInt<64> connect d_opcodes_clr_1, UInt<64>(0h0) wire d_sizes_clr_1 : UInt<128> connect d_sizes_clr_1, UInt<128>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1356 = and(io.in.d.valid, d_first_2) node _T_1357 = and(_T_1356, UInt<1>(0h1)) node _T_1358 = and(_T_1357, d_release_ack_1) when _T_1358 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1359 = and(io.in.d.ready, io.in.d.valid) node _T_1360 = and(_T_1359, d_first_2) node _T_1361 = and(_T_1360, UInt<1>(0h1)) node _T_1362 = and(_T_1361, d_release_ack_1) when _T_1362 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1363 = and(io.in.d.valid, d_first_2) node _T_1364 = and(_T_1363, UInt<1>(0h1)) node _T_1365 = and(_T_1364, d_release_ack_1) when _T_1365 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1366 = dshr(inflight_1, io.in.d.bits.source) node _T_1367 = bits(_T_1366, 0, 0) node _T_1368 = or(_T_1367, same_cycle_resp_1) node _T_1369 = asUInt(reset) node _T_1370 = eq(_T_1369, UInt<1>(0h0)) when _T_1370 : node _T_1371 = eq(_T_1368, UInt<1>(0h0)) when _T_1371 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1368, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<4>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1372 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1373 = asUInt(reset) node _T_1374 = eq(_T_1373, UInt<1>(0h0)) when _T_1374 : node _T_1375 = eq(_T_1372, UInt<1>(0h0)) when _T_1375 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1372, UInt<1>(0h1), "") : assert_109 else : node _T_1376 = eq(io.in.d.bits.size, c_size_lookup) node _T_1377 = asUInt(reset) node _T_1378 = eq(_T_1377, UInt<1>(0h0)) when _T_1378 : node _T_1379 = eq(_T_1376, UInt<1>(0h0)) when _T_1379 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1376, UInt<1>(0h1), "") : assert_110 node _T_1380 = and(io.in.d.valid, d_first_2) node _T_1381 = and(_T_1380, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<4>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1382 = and(_T_1381, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<4>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1383 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1384 = and(_T_1382, _T_1383) node _T_1385 = and(_T_1384, d_release_ack_1) node _T_1386 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1387 = and(_T_1385, _T_1386) when _T_1387 : node _T_1388 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<4>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1389 = or(_T_1388, _WIRE_23.ready) node _T_1390 = asUInt(reset) node _T_1391 = eq(_T_1390, UInt<1>(0h0)) when _T_1391 : node _T_1392 = eq(_T_1389, UInt<1>(0h0)) when _T_1392 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1389, UInt<1>(0h1), "") : assert_111 node _T_1393 = orr(c_set_wo_ready) when _T_1393 : node _T_1394 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1395 = asUInt(reset) node _T_1396 = eq(_T_1395, UInt<1>(0h0)) when _T_1396 : node _T_1397 = eq(_T_1394, UInt<1>(0h0)) when _T_1397 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1394, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_25 node _T_1398 = orr(inflight_1) node _T_1399 = eq(_T_1398, UInt<1>(0h0)) node _T_1400 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1401 = or(_T_1399, _T_1400) node _T_1402 = lt(watchdog_1, plusarg_reader_1.out) node _T_1403 = or(_T_1401, _T_1402) node _T_1404 = asUInt(reset) node _T_1405 = eq(_T_1404, UInt<1>(0h0)) when _T_1405 : node _T_1406 = eq(_T_1403, UInt<1>(0h0)) when _T_1406 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1403, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<4>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1407 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1408 = and(io.in.d.ready, io.in.d.valid) node _T_1409 = or(_T_1407, _T_1408) when _T_1409 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_12( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_4 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_10 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_14 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_16 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_20 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_22 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_28 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_30 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_34 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_36 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_40 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_42 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_46 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_48 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] c_opcodes_set = 64'h0; // @[Monitor.scala:740:34] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_wo_ready_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_4_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_5_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [131:0] _c_sizes_set_T_1 = 132'h0; // @[Monitor.scala:768:52] wire [6:0] _c_opcodes_set_T = 7'h0; // @[Monitor.scala:767:79] wire [6:0] _c_sizes_set_T = 7'h0; // @[Monitor.scala:768:77] wire [130:0] _c_opcodes_set_T_1 = 131'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [15:0] _c_set_wo_ready_T = 16'h1; // @[OneHot.scala:58:35] wire [15:0] _c_set_T = 16'h1; // @[OneHot.scala:58:35] wire [127:0] c_sizes_set = 128'h0; // @[Monitor.scala:741:34] wire [15:0] c_set = 16'h0; // @[Monitor.scala:738:34] wire [15:0] c_set_wo_ready = 16'h0; // @[Monitor.scala:739:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [3:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] _source_ok_T = io_in_a_bits_source_0[3:2]; // @[Monitor.scala:36:7] wire [1:0] _source_ok_T_6 = io_in_a_bits_source_0[3:2]; // @[Monitor.scala:36:7] wire [1:0] _source_ok_T_12 = io_in_a_bits_source_0[3:2]; // @[Monitor.scala:36:7] wire [1:0] _source_ok_T_18 = io_in_a_bits_source_0[3:2]; // @[Monitor.scala:36:7] wire _source_ok_T_1 = _source_ok_T == 2'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_3 = _source_ok_T_1; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_5 = _source_ok_T_3; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_7 = _source_ok_T_6 == 2'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_9 = _source_ok_T_7; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_11 = _source_ok_T_9; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_13 = _source_ok_T_12 == 2'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_15 = _source_ok_T_13; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_17 = _source_ok_T_15; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_17; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_19 = &_source_ok_T_18; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_21 = _source_ok_T_19; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_23 = _source_ok_T_21; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_23; // @[Parameters.scala:1138:31] wire _source_ok_T_24 = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_25 = _source_ok_T_24 \| _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_25 \| _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] _source_ok_T_26 = io_in_d_bits_source_0[3:2]; // @[Monitor.scala:36:7] wire [1:0] _source_ok_T_32 = io_in_d_bits_source_0[3:2]; // @[Monitor.scala:36:7] wire [1:0] _source_ok_T_38 = io_in_d_bits_source_0[3:2]; // @[Monitor.scala:36:7] wire [1:0] _source_ok_T_44 = io_in_d_bits_source_0[3:2]; // @[Monitor.scala:36:7] wire _source_ok_T_27 = _source_ok_T_26 == 2'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_29 = _source_ok_T_27; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_31 = _source_ok_T_29; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_0 = _source_ok_T_31; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_33 = _source_ok_T_32 == 2'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_35 = _source_ok_T_33; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_37 = _source_ok_T_35; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_37; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_39 = _source_ok_T_38 == 2'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_41 = _source_ok_T_39; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_43 = _source_ok_T_41; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_43; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_45 = &_source_ok_T_44; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_47 = _source_ok_T_45; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_49 = _source_ok_T_47; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_49; // @[Parameters.scala:1138:31] wire _source_ok_T_50 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_51 = _source_ok_T_50 \| _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_51 \| _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _T_1336 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1336; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1336; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [3:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1409 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1409; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1409; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1409; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [3:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [15:0] inflight; // @[Monitor.scala:614:27] reg [63:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [127:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [15:0] a_set; // @[Monitor.scala:626:34] wire [15:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [63:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [127:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [6:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [6:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [6:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [6:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [6:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [63:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [63:0] _a_opcode_lookup_T_6 = {60'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [63:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[63:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [6:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [6:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [6:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [6:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [6:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [127:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [127:0] _a_size_lookup_T_6 = {120'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [127:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[127:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [15:0] _GEN_3 = {12'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35] wire [15:0] _GEN_4 = 16'h1 << _GEN_3; // @[OneHot.scala:58:35] wire [15:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35] wire [15:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_4; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T : 16'h0; // @[OneHot.scala:58:35] wire _T_1262 = _T_1336 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1262 ? _a_set_T : 16'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1262 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1262 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [6:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [130:0] _a_opcodes_set_T_1 = {127'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1262 ? _a_opcodes_set_T_1[63:0] : 64'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [6:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [131:0] _a_sizes_set_T_1 = {127'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1262 ? _a_sizes_set_T_1[127:0] : 128'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [15:0] d_clr; // @[Monitor.scala:664:34] wire [15:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [63:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [127:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_5; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_5; // @[Monitor.scala:673:46, :783:46] wire _T_1308 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [15:0] _GEN_6 = {12'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35] wire [15:0] _GEN_7 = 16'h1 << _GEN_6; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1308 & ~d_release_ack ? _d_clr_wo_ready_T : 16'h0; // @[OneHot.scala:58:35] wire _T_1277 = _T_1409 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1277 ? _d_clr_T : 16'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_5 = 143'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1277 ? _d_opcodes_clr_T_5[63:0] : 64'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [142:0] _d_sizes_clr_T_5 = 143'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1277 ? _d_sizes_clr_T_5[127:0] : 128'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [15:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [15:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [15:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [63:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [63:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [63:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [127:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [127:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [127:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [15:0] inflight_1; // @[Monitor.scala:726:35] wire [15:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [63:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [63:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [127:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [127:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [63:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [63:0] _c_opcode_lookup_T_6 = {60'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [63:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[63:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [127:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [127:0] _c_size_lookup_T_6 = {120'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [127:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[127:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [15:0] d_clr_1; // @[Monitor.scala:774:34] wire [15:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [63:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [127:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1380 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1380 & d_release_ack_1 ? _d_clr_wo_ready_T_1 : 16'h0; // @[OneHot.scala:58:35] wire _T_1362 = _T_1409 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1362 ? _d_clr_T_1 : 16'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_11 = 143'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1362 ? _d_opcodes_clr_T_11[63:0] : 64'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [142:0] _d_sizes_clr_T_11 = 143'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1362 ? _d_sizes_clr_T_11[127:0] : 128'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 4'h0; // @[Monitor.scala:36:7, :795:113] wire [15:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [15:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [63:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [63:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [127:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [127:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module Router_36 : input clock : Clock input reset : Reset output auto : { debug_out : { va_stall : UInt[3], sa_stall : UInt[3]}, egress_nodes_out_2 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, egress_nodes_out_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, egress_nodes_out_0 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, flip ingress_nodes_in_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip ingress_nodes_in_0 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, source_nodes_out : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>}, flip dest_nodes_in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>}} wire destNodesIn : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>} invalidate destNodesIn.vc_free invalidate destNodesIn.credit_return invalidate destNodesIn.flit[0].bits.virt_channel_id invalidate destNodesIn.flit[0].bits.flow.egress_node_id invalidate destNodesIn.flit[0].bits.flow.egress_node invalidate destNodesIn.flit[0].bits.flow.ingress_node_id invalidate destNodesIn.flit[0].bits.flow.ingress_node invalidate destNodesIn.flit[0].bits.flow.vnet_id invalidate destNodesIn.flit[0].bits.payload invalidate destNodesIn.flit[0].bits.tail invalidate destNodesIn.flit[0].bits.head invalidate destNodesIn.flit[0].valid inst monitor of NoCMonitor_79 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.vc_free, destNodesIn.vc_free connect monitor.io.in.credit_return, destNodesIn.credit_return connect monitor.io.in.flit[0].bits.virt_channel_id, destNodesIn.flit[0].bits.virt_channel_id connect monitor.io.in.flit[0].bits.flow.egress_node_id, destNodesIn.flit[0].bits.flow.egress_node_id connect monitor.io.in.flit[0].bits.flow.egress_node, destNodesIn.flit[0].bits.flow.egress_node connect monitor.io.in.flit[0].bits.flow.ingress_node_id, destNodesIn.flit[0].bits.flow.ingress_node_id connect monitor.io.in.flit[0].bits.flow.ingress_node, destNodesIn.flit[0].bits.flow.ingress_node connect monitor.io.in.flit[0].bits.flow.vnet_id, destNodesIn.flit[0].bits.flow.vnet_id connect monitor.io.in.flit[0].bits.payload, destNodesIn.flit[0].bits.payload connect monitor.io.in.flit[0].bits.tail, destNodesIn.flit[0].bits.tail connect monitor.io.in.flit[0].bits.head, destNodesIn.flit[0].bits.head connect monitor.io.in.flit[0].valid, destNodesIn.flit[0].valid wire sourceNodesOut : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>} invalidate sourceNodesOut.vc_free invalidate sourceNodesOut.credit_return invalidate sourceNodesOut.flit[0].bits.virt_channel_id invalidate sourceNodesOut.flit[0].bits.flow.egress_node_id invalidate sourceNodesOut.flit[0].bits.flow.egress_node invalidate sourceNodesOut.flit[0].bits.flow.ingress_node_id invalidate sourceNodesOut.flit[0].bits.flow.ingress_node invalidate sourceNodesOut.flit[0].bits.flow.vnet_id invalidate sourceNodesOut.flit[0].bits.payload invalidate sourceNodesOut.flit[0].bits.tail invalidate sourceNodesOut.flit[0].bits.head invalidate sourceNodesOut.flit[0].valid wire ingressNodesIn : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} invalidate ingressNodesIn.flit.bits.egress_id invalidate ingressNodesIn.flit.bits.payload invalidate ingressNodesIn.flit.bits.tail invalidate ingressNodesIn.flit.bits.head invalidate ingressNodesIn.flit.valid invalidate ingressNodesIn.flit.ready wire ingressNodesIn_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} invalidate ingressNodesIn_1.flit.bits.egress_id invalidate ingressNodesIn_1.flit.bits.payload invalidate ingressNodesIn_1.flit.bits.tail invalidate ingressNodesIn_1.flit.bits.head invalidate ingressNodesIn_1.flit.valid invalidate ingressNodesIn_1.flit.ready wire egressNodesOut : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}} invalidate egressNodesOut.flit.bits.ingress_id invalidate egressNodesOut.flit.bits.payload invalidate egressNodesOut.flit.bits.tail invalidate egressNodesOut.flit.bits.head invalidate egressNodesOut.flit.valid invalidate egressNodesOut.flit.ready wire egressNodesOut_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}} invalidate egressNodesOut_1.flit.bits.ingress_id invalidate egressNodesOut_1.flit.bits.payload invalidate egressNodesOut_1.flit.bits.tail invalidate egressNodesOut_1.flit.bits.head invalidate egressNodesOut_1.flit.valid invalidate egressNodesOut_1.flit.ready wire egressNodesOut_2 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}} invalidate egressNodesOut_2.flit.bits.ingress_id invalidate egressNodesOut_2.flit.bits.payload invalidate egressNodesOut_2.flit.bits.tail invalidate egressNodesOut_2.flit.bits.head invalidate egressNodesOut_2.flit.valid invalidate egressNodesOut_2.flit.ready wire debugNodeOut : { va_stall : UInt[3], sa_stall : UInt[3]} invalidate debugNodeOut.sa_stall[0] invalidate debugNodeOut.sa_stall[1] invalidate debugNodeOut.sa_stall[2] invalidate debugNodeOut.va_stall[0] invalidate debugNodeOut.va_stall[1] invalidate debugNodeOut.va_stall[2] connect destNodesIn, auto.dest_nodes_in connect auto.source_nodes_out, sourceNodesOut connect ingressNodesIn, auto.ingress_nodes_in_0 connect ingressNodesIn_1, auto.ingress_nodes_in_1 connect auto.egress_nodes_out_0, egressNodesOut connect auto.egress_nodes_out_1, egressNodesOut_1 connect auto.egress_nodes_out_2, egressNodesOut_2 connect auto.debug_out, debugNodeOut inst input_unit_0_from_16 of InputUnit_79 connect input_unit_0_from_16.clock, clock connect input_unit_0_from_16.reset, reset inst ingress_unit_1_from_15 of IngressUnit_52 connect ingress_unit_1_from_15.clock, clock connect ingress_unit_1_from_15.reset, reset inst ingress_unit_2_from_16 of IngressUnit_53 connect ingress_unit_2_from_16.clock, clock connect ingress_unit_2_from_16.reset, reset inst output_unit_0_to_16 of OutputUnit_79 connect output_unit_0_to_16.clock, clock connect output_unit_0_to_16.reset, reset inst egress_unit_1_to_20 of EgressUnit_53 connect egress_unit_1_to_20.clock, clock connect egress_unit_1_to_20.reset, reset inst egress_unit_2_to_21 of EgressUnit_54 connect egress_unit_2_to_21.clock, clock connect egress_unit_2_to_21.reset, reset inst egress_unit_3_to_22 of EgressUnit_55 connect egress_unit_3_to_22.clock, clock connect egress_unit_3_to_22.reset, reset inst switch of Switch_36 connect switch.clock, clock connect switch.reset, reset inst switch_allocator of SwitchAllocator_36 connect switch_allocator.clock, clock connect switch_allocator.reset, reset inst vc_allocator of RotatingSingleVCAllocator_36 connect vc_allocator.clock, clock connect vc_allocator.reset, reset inst route_computer of RouteComputer_36 connect route_computer.clock, clock connect route_computer.reset, reset node _fires_count_T = and(vc_allocator.io.req.`0`.ready, vc_allocator.io.req.`0`.valid) node _fires_count_T_1 = and(vc_allocator.io.req.`1`.ready, vc_allocator.io.req.`1`.valid) node _fires_count_T_2 = and(vc_allocator.io.req.`2`.ready, vc_allocator.io.req.`2`.valid) node _fires_count_T_3 = add(_fires_count_T_1, _fires_count_T_2) node _fires_count_T_4 = bits(_fires_count_T_3, 1, 0) node _fires_count_T_5 = add(_fires_count_T, _fires_count_T_4) node _fires_count_T_6 = bits(_fires_count_T_5, 1, 0) wire fires_count : UInt connect fires_count, _fires_count_T_6 connect input_unit_0_from_16.io.in, destNodesIn connect ingress_unit_1_from_15.io.in, ingressNodesIn.flit connect ingress_unit_2_from_16.io.in, ingressNodesIn_1.flit connect output_unit_0_to_16.io.out.vc_free, sourceNodesOut.vc_free connect output_unit_0_to_16.io.out.credit_return, sourceNodesOut.credit_return connect sourceNodesOut.flit, output_unit_0_to_16.io.out.flit connect egressNodesOut.flit.bits, egress_unit_1_to_20.io.out.bits connect egressNodesOut.flit.valid, egress_unit_1_to_20.io.out.valid connect egress_unit_1_to_20.io.out.ready, egressNodesOut.flit.ready connect egressNodesOut_1.flit.bits, egress_unit_2_to_21.io.out.bits connect egressNodesOut_1.flit.valid, egress_unit_2_to_21.io.out.valid connect egress_unit_2_to_21.io.out.ready, egressNodesOut_1.flit.ready connect egressNodesOut_2.flit.bits, egress_unit_3_to_22.io.out.bits connect egressNodesOut_2.flit.valid, egress_unit_3_to_22.io.out.valid connect egress_unit_3_to_22.io.out.ready, egressNodesOut_2.flit.ready connect route_computer.io.req.`0`, input_unit_0_from_16.io.router_req connect route_computer.io.req.`1`, ingress_unit_1_from_15.io.router_req connect route_computer.io.req.`2`, ingress_unit_2_from_16.io.router_req connect input_unit_0_from_16.io.router_resp, route_computer.io.resp.`0` connect ingress_unit_1_from_15.io.router_resp, route_computer.io.resp.`1` connect ingress_unit_2_from_16.io.router_resp, route_computer.io.resp.`2` connect vc_allocator.io.req.`0`, input_unit_0_from_16.io.vcalloc_req connect vc_allocator.io.req.`1`, ingress_unit_1_from_15.io.vcalloc_req connect vc_allocator.io.req.`2`, ingress_unit_2_from_16.io.vcalloc_req connect input_unit_0_from_16.io.vcalloc_resp, vc_allocator.io.resp.`0` connect ingress_unit_1_from_15.io.vcalloc_resp, vc_allocator.io.resp.`1` connect ingress_unit_2_from_16.io.vcalloc_resp, vc_allocator.io.resp.`2` connect output_unit_0_to_16.io.allocs, vc_allocator.io.out_allocs.`0` connect egress_unit_1_to_20.io.allocs, vc_allocator.io.out_allocs.`1` connect egress_unit_2_to_21.io.allocs, vc_allocator.io.out_allocs.`2` connect egress_unit_3_to_22.io.allocs, vc_allocator.io.out_allocs.`3` connect vc_allocator.io.channel_status.`0`[0].flow.egress_node_id, output_unit_0_to_16.io.channel_status[0].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[0].flow.egress_node, output_unit_0_to_16.io.channel_status[0].flow.egress_node connect vc_allocator.io.channel_status.`0`[0].flow.ingress_node_id, output_unit_0_to_16.io.channel_status[0].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[0].flow.ingress_node, output_unit_0_to_16.io.channel_status[0].flow.ingress_node connect vc_allocator.io.channel_status.`0`[0].flow.vnet_id, output_unit_0_to_16.io.channel_status[0].flow.vnet_id connect vc_allocator.io.channel_status.`0`[0].occupied, output_unit_0_to_16.io.channel_status[0].occupied connect vc_allocator.io.channel_status.`0`[1].flow.egress_node_id, output_unit_0_to_16.io.channel_status[1].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[1].flow.egress_node, output_unit_0_to_16.io.channel_status[1].flow.egress_node connect vc_allocator.io.channel_status.`0`[1].flow.ingress_node_id, output_unit_0_to_16.io.channel_status[1].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[1].flow.ingress_node, output_unit_0_to_16.io.channel_status[1].flow.ingress_node connect vc_allocator.io.channel_status.`0`[1].flow.vnet_id, output_unit_0_to_16.io.channel_status[1].flow.vnet_id connect vc_allocator.io.channel_status.`0`[1].occupied, output_unit_0_to_16.io.channel_status[1].occupied connect vc_allocator.io.channel_status.`0`[2].flow.egress_node_id, output_unit_0_to_16.io.channel_status[2].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[2].flow.egress_node, output_unit_0_to_16.io.channel_status[2].flow.egress_node connect vc_allocator.io.channel_status.`0`[2].flow.ingress_node_id, output_unit_0_to_16.io.channel_status[2].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[2].flow.ingress_node, output_unit_0_to_16.io.channel_status[2].flow.ingress_node connect vc_allocator.io.channel_status.`0`[2].flow.vnet_id, output_unit_0_to_16.io.channel_status[2].flow.vnet_id connect vc_allocator.io.channel_status.`0`[2].occupied, output_unit_0_to_16.io.channel_status[2].occupied connect vc_allocator.io.channel_status.`0`[3].flow.egress_node_id, output_unit_0_to_16.io.channel_status[3].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[3].flow.egress_node, output_unit_0_to_16.io.channel_status[3].flow.egress_node connect vc_allocator.io.channel_status.`0`[3].flow.ingress_node_id, output_unit_0_to_16.io.channel_status[3].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[3].flow.ingress_node, output_unit_0_to_16.io.channel_status[3].flow.ingress_node connect vc_allocator.io.channel_status.`0`[3].flow.vnet_id, output_unit_0_to_16.io.channel_status[3].flow.vnet_id connect vc_allocator.io.channel_status.`0`[3].occupied, output_unit_0_to_16.io.channel_status[3].occupied connect vc_allocator.io.channel_status.`0`[4].flow.egress_node_id, output_unit_0_to_16.io.channel_status[4].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[4].flow.egress_node, output_unit_0_to_16.io.channel_status[4].flow.egress_node connect vc_allocator.io.channel_status.`0`[4].flow.ingress_node_id, output_unit_0_to_16.io.channel_status[4].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[4].flow.ingress_node, output_unit_0_to_16.io.channel_status[4].flow.ingress_node connect vc_allocator.io.channel_status.`0`[4].flow.vnet_id, output_unit_0_to_16.io.channel_status[4].flow.vnet_id connect vc_allocator.io.channel_status.`0`[4].occupied, output_unit_0_to_16.io.channel_status[4].occupied connect vc_allocator.io.channel_status.`1`[0].flow.egress_node_id, egress_unit_1_to_20.io.channel_status[0].flow.egress_node_id connect vc_allocator.io.channel_status.`1`[0].flow.egress_node, egress_unit_1_to_20.io.channel_status[0].flow.egress_node connect vc_allocator.io.channel_status.`1`[0].flow.ingress_node_id, egress_unit_1_to_20.io.channel_status[0].flow.ingress_node_id connect vc_allocator.io.channel_status.`1`[0].flow.ingress_node, egress_unit_1_to_20.io.channel_status[0].flow.ingress_node connect vc_allocator.io.channel_status.`1`[0].flow.vnet_id, egress_unit_1_to_20.io.channel_status[0].flow.vnet_id connect vc_allocator.io.channel_status.`1`[0].occupied, egress_unit_1_to_20.io.channel_status[0].occupied connect vc_allocator.io.channel_status.`2`[0].flow.egress_node_id, egress_unit_2_to_21.io.channel_status[0].flow.egress_node_id connect vc_allocator.io.channel_status.`2`[0].flow.egress_node, egress_unit_2_to_21.io.channel_status[0].flow.egress_node connect vc_allocator.io.channel_status.`2`[0].flow.ingress_node_id, egress_unit_2_to_21.io.channel_status[0].flow.ingress_node_id connect vc_allocator.io.channel_status.`2`[0].flow.ingress_node, egress_unit_2_to_21.io.channel_status[0].flow.ingress_node connect vc_allocator.io.channel_status.`2`[0].flow.vnet_id, egress_unit_2_to_21.io.channel_status[0].flow.vnet_id connect vc_allocator.io.channel_status.`2`[0].occupied, egress_unit_2_to_21.io.channel_status[0].occupied connect vc_allocator.io.channel_status.`3`[0].flow.egress_node_id, egress_unit_3_to_22.io.channel_status[0].flow.egress_node_id connect vc_allocator.io.channel_status.`3`[0].flow.egress_node, egress_unit_3_to_22.io.channel_status[0].flow.egress_node connect vc_allocator.io.channel_status.`3`[0].flow.ingress_node_id, egress_unit_3_to_22.io.channel_status[0].flow.ingress_node_id connect vc_allocator.io.channel_status.`3`[0].flow.ingress_node, egress_unit_3_to_22.io.channel_status[0].flow.ingress_node connect vc_allocator.io.channel_status.`3`[0].flow.vnet_id, egress_unit_3_to_22.io.channel_status[0].flow.vnet_id connect vc_allocator.io.channel_status.`3`[0].occupied, egress_unit_3_to_22.io.channel_status[0].occupied connect input_unit_0_from_16.io.out_credit_available.`0`[0], output_unit_0_to_16.io.credit_available[0] connect input_unit_0_from_16.io.out_credit_available.`0`[1], output_unit_0_to_16.io.credit_available[1] connect input_unit_0_from_16.io.out_credit_available.`0`[2], output_unit_0_to_16.io.credit_available[2] connect input_unit_0_from_16.io.out_credit_available.`0`[3], output_unit_0_to_16.io.credit_available[3] connect input_unit_0_from_16.io.out_credit_available.`0`[4], output_unit_0_to_16.io.credit_available[4] connect input_unit_0_from_16.io.out_credit_available.`1`[0], egress_unit_1_to_20.io.credit_available[0] connect input_unit_0_from_16.io.out_credit_available.`2`[0], egress_unit_2_to_21.io.credit_available[0] connect input_unit_0_from_16.io.out_credit_available.`3`[0], egress_unit_3_to_22.io.credit_available[0] connect ingress_unit_1_from_15.io.out_credit_available.`0`[0], output_unit_0_to_16.io.credit_available[0] connect ingress_unit_1_from_15.io.out_credit_available.`0`[1], output_unit_0_to_16.io.credit_available[1] connect ingress_unit_1_from_15.io.out_credit_available.`0`[2], output_unit_0_to_16.io.credit_available[2] connect ingress_unit_1_from_15.io.out_credit_available.`0`[3], output_unit_0_to_16.io.credit_available[3] connect ingress_unit_1_from_15.io.out_credit_available.`0`[4], output_unit_0_to_16.io.credit_available[4] connect ingress_unit_1_from_15.io.out_credit_available.`1`[0], egress_unit_1_to_20.io.credit_available[0] connect ingress_unit_1_from_15.io.out_credit_available.`2`[0], egress_unit_2_to_21.io.credit_available[0] connect ingress_unit_1_from_15.io.out_credit_available.`3`[0], egress_unit_3_to_22.io.credit_available[0] connect ingress_unit_2_from_16.io.out_credit_available.`0`[0], output_unit_0_to_16.io.credit_available[0] connect ingress_unit_2_from_16.io.out_credit_available.`0`[1], output_unit_0_to_16.io.credit_available[1] connect ingress_unit_2_from_16.io.out_credit_available.`0`[2], output_unit_0_to_16.io.credit_available[2] connect ingress_unit_2_from_16.io.out_credit_available.`0`[3], output_unit_0_to_16.io.credit_available[3] connect ingress_unit_2_from_16.io.out_credit_available.`0`[4], output_unit_0_to_16.io.credit_available[4] connect ingress_unit_2_from_16.io.out_credit_available.`1`[0], egress_unit_1_to_20.io.credit_available[0] connect ingress_unit_2_from_16.io.out_credit_available.`2`[0], egress_unit_2_to_21.io.credit_available[0] connect ingress_unit_2_from_16.io.out_credit_available.`3`[0], egress_unit_3_to_22.io.credit_available[0] connect switch_allocator.io.req.`0`[0], input_unit_0_from_16.io.salloc_req[0] connect switch_allocator.io.req.`1`[0], ingress_unit_1_from_15.io.salloc_req[0] connect switch_allocator.io.req.`2`[0], ingress_unit_2_from_16.io.salloc_req[0] connect output_unit_0_to_16.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`0`[0].tail connect output_unit_0_to_16.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`0`[0].alloc connect output_unit_0_to_16.io.credit_alloc[1].tail, switch_allocator.io.credit_alloc.`0`[1].tail connect output_unit_0_to_16.io.credit_alloc[1].alloc, switch_allocator.io.credit_alloc.`0`[1].alloc connect output_unit_0_to_16.io.credit_alloc[2].tail, switch_allocator.io.credit_alloc.`0`[2].tail connect output_unit_0_to_16.io.credit_alloc[2].alloc, switch_allocator.io.credit_alloc.`0`[2].alloc connect output_unit_0_to_16.io.credit_alloc[3].tail, switch_allocator.io.credit_alloc.`0`[3].tail connect output_unit_0_to_16.io.credit_alloc[3].alloc, switch_allocator.io.credit_alloc.`0`[3].alloc connect output_unit_0_to_16.io.credit_alloc[4].tail, switch_allocator.io.credit_alloc.`0`[4].tail connect output_unit_0_to_16.io.credit_alloc[4].alloc, switch_allocator.io.credit_alloc.`0`[4].alloc connect egress_unit_1_to_20.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`1`[0].tail connect egress_unit_1_to_20.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`1`[0].alloc connect egress_unit_2_to_21.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`2`[0].tail connect egress_unit_2_to_21.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`2`[0].alloc connect egress_unit_3_to_22.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`3`[0].tail connect egress_unit_3_to_22.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`3`[0].alloc connect switch.io.in.`0`[0], input_unit_0_from_16.io.out[0] connect switch.io.in.`1`[0], ingress_unit_1_from_15.io.out[0] connect switch.io.in.`2`[0], ingress_unit_2_from_16.io.out[0] connect output_unit_0_to_16.io.in, switch.io.out.`0` connect egress_unit_1_to_20.io.in, switch.io.out.`1` connect egress_unit_2_to_21.io.in, switch.io.out.`2` connect egress_unit_3_to_22.io.in, switch.io.out.`3` reg REG : { `3` : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `2` : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `1` : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `0` : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1]}, clock connect REG, switch_allocator.io.switch_sel connect switch.io.sel.`0`[0].`0`[0], REG.`0`[0].`0`[0] connect switch.io.sel.`0`[0].`1`[0], REG.`0`[0].`1`[0] connect switch.io.sel.`0`[0].`2`[0], REG.`0`[0].`2`[0] connect switch.io.sel.`1`[0].`0`[0], REG.`1`[0].`0`[0] connect switch.io.sel.`1`[0].`1`[0], REG.`1`[0].`1`[0] connect switch.io.sel.`1`[0].`2`[0], REG.`1`[0].`2`[0] connect switch.io.sel.`2`[0].`0`[0], REG.`2`[0].`0`[0] connect switch.io.sel.`2`[0].`1`[0], REG.`2`[0].`1`[0] connect switch.io.sel.`2`[0].`2`[0], REG.`2`[0].`2`[0] connect switch.io.sel.`3`[0].`0`[0], REG.`3`[0].`0`[0] connect switch.io.sel.`3`[0].`1`[0], REG.`3`[0].`1`[0] connect switch.io.sel.`3`[0].`2`[0], REG.`3`[0].`2`[0] connect input_unit_0_from_16.io.block, UInt<1>(0h0) connect ingress_unit_1_from_15.io.block, UInt<1>(0h0) connect ingress_unit_2_from_16.io.block, UInt<1>(0h0) connect debugNodeOut.va_stall[0], input_unit_0_from_16.io.debug.va_stall connect debugNodeOut.va_stall[1], ingress_unit_1_from_15.io.debug.va_stall connect debugNodeOut.va_stall[2], ingress_unit_2_from_16.io.debug.va_stall connect debugNodeOut.sa_stall[0], input_unit_0_from_16.io.debug.sa_stall connect debugNodeOut.sa_stall[1], ingress_unit_1_from_15.io.debug.sa_stall connect debugNodeOut.sa_stall[2], ingress_unit_2_from_16.io.debug.sa_stall regreset debug_tsc : UInt<64>, clock, reset, UInt<64>(0h0) node _debug_tsc_T = add(debug_tsc, UInt<1>(0h1)) node _debug_tsc_T_1 = tail(_debug_tsc_T, 1) connect debug_tsc, _debug_tsc_T_1 regreset debug_sample : UInt<64>, clock, reset, UInt<64>(0h0) node _debug_sample_T = add(debug_sample, UInt<1>(0h1)) node _debug_sample_T_1 = tail(_debug_sample_T, 1) connect debug_sample, _debug_sample_T_1 inst plusarg_reader of plusarg_reader_84 node _T = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_1 = tail(_T, 1) node _T_2 = eq(debug_sample, _T_1) when _T_2 : connect debug_sample, UInt<1>(0h0) regreset util_ctr : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T = add(util_ctr, destNodesIn.flit[0].valid) node _util_ctr_T_1 = tail(_util_ctr_T, 1) connect util_ctr, _util_ctr_T_1 node _fired_T = or(fired, destNodesIn.flit[0].valid) connect fired, _fired_T node _T_3 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_4 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_5 = tail(_T_4, 1) node _T_6 = eq(debug_sample, _T_5) node _T_7 = and(_T_3, _T_6) node _T_8 = and(_T_7, fired) when _T_8 : node _T_9 = asUInt(reset) node _T_10 = eq(_T_9, UInt<1>(0h0)) when _T_10 : printf(clock, UInt<1>(0h1), "nocsample %d 16 7 %d\n", debug_tsc, util_ctr) : printf connect fired, destNodesIn.flit[0].valid node _T_11 = and(ingressNodesIn.flit.ready, ingressNodesIn.flit.valid) regreset util_ctr_1 : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T_2 = add(util_ctr_1, _T_11) node _util_ctr_T_3 = tail(_util_ctr_T_2, 1) connect util_ctr_1, _util_ctr_T_3 node _fired_T_1 = or(fired_1, _T_11) connect fired_1, _fired_T_1 node _T_12 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_13 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_14 = tail(_T_13, 1) node _T_15 = eq(debug_sample, _T_14) node _T_16 = and(_T_12, _T_15) node _T_17 = and(_T_16, fired_1) when _T_17 : node _T_18 = asUInt(reset) node _T_19 = eq(_T_18, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "nocsample %d i15 7 %d\n", debug_tsc, util_ctr_1) : printf_1 connect fired_1, _T_11 node _T_20 = and(ingressNodesIn_1.flit.ready, ingressNodesIn_1.flit.valid) regreset util_ctr_2 : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T_4 = add(util_ctr_2, _T_20) node _util_ctr_T_5 = tail(_util_ctr_T_4, 1) connect util_ctr_2, _util_ctr_T_5 node _fired_T_2 = or(fired_2, _T_20) connect fired_2, _fired_T_2 node _T_21 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_22 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_23 = tail(_T_22, 1) node _T_24 = eq(debug_sample, _T_23) node _T_25 = and(_T_21, _T_24) node _T_26 = and(_T_25, fired_2) when _T_26 : node _T_27 = asUInt(reset) node _T_28 = eq(_T_27, UInt<1>(0h0)) when _T_28 : printf(clock, UInt<1>(0h1), "nocsample %d i16 7 %d\n", debug_tsc, util_ctr_2) : printf_2 connect fired_2, _T_20 node _T_29 = and(egressNodesOut.flit.ready, egressNodesOut.flit.valid) regreset util_ctr_3 : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired_3 : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T_6 = add(util_ctr_3, _T_29) node _util_ctr_T_7 = tail(_util_ctr_T_6, 1) connect util_ctr_3, _util_ctr_T_7 node _fired_T_3 = or(fired_3, _T_29) connect fired_3, _fired_T_3 node _T_30 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_31 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_32 = tail(_T_31, 1) node _T_33 = eq(debug_sample, _T_32) node _T_34 = and(_T_30, _T_33) node _T_35 = and(_T_34, fired_3) when _T_35 : node _T_36 = asUInt(reset) node _T_37 = eq(_T_36, UInt<1>(0h0)) when _T_37 : printf(clock, UInt<1>(0h1), "nocsample %d 7 e20 %d\n", debug_tsc, util_ctr_3) : printf_3 connect fired_3, _T_29 node _T_38 = and(egressNodesOut_1.flit.ready, egressNodesOut_1.flit.valid) regreset util_ctr_4 : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired_4 : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T_8 = add(util_ctr_4, _T_38) node _util_ctr_T_9 = tail(_util_ctr_T_8, 1) connect util_ctr_4, _util_ctr_T_9 node _fired_T_4 = or(fired_4, _T_38) connect fired_4, _fired_T_4 node _T_39 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_40 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_41 = tail(_T_40, 1) node _T_42 = eq(debug_sample, _T_41) node _T_43 = and(_T_39, _T_42) node _T_44 = and(_T_43, fired_4) when _T_44 : node _T_45 = asUInt(reset) node _T_46 = eq(_T_45, UInt<1>(0h0)) when _T_46 : printf(clock, UInt<1>(0h1), "nocsample %d 7 e21 %d\n", debug_tsc, util_ctr_4) : printf_4 connect fired_4, _T_38 node _T_47 = and(egressNodesOut_2.flit.ready, egressNodesOut_2.flit.valid) regreset util_ctr_5 : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired_5 : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T_10 = add(util_ctr_5, _T_47) node _util_ctr_T_11 = tail(_util_ctr_T_10, 1) connect util_ctr_5, _util_ctr_T_11 node _fired_T_5 = or(fired_5, _T_47) connect fired_5, _fired_T_5 node _T_48 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_49 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_50 = tail(_T_49, 1) node _T_51 = eq(debug_sample, _T_50) node _T_52 = and(_T_48, _T_51) node _T_53 = and(_T_52, fired_5) when _T_53 : node _T_54 = asUInt(reset) node _T_55 = eq(_T_54, UInt<1>(0h0)) when _T_55 : printf(clock, UInt<1>(0h1), "nocsample %d 7 e22 %d\n", debug_tsc, util_ctr_5) : printf_5 connect fired_5, _T_47	module Router_36( // @[Router.scala:89:25] input clock, // @[Router.scala:89:25] input reset, // @[Router.scala:89:25] output [2:0] auto_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25] input auto_egress_nodes_out_2_flit_ready, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_2_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_2_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_2_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input auto_egress_nodes_out_1_flit_ready, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_1_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_1_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input auto_egress_nodes_out_0_flit_ready, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_0_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_0_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_egress_nodes_out_0_flit_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_ingress_nodes_in_1_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_1_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_1_flit_bits_head, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_ingress_nodes_in_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_source_nodes_out_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_source_nodes_out_credit_return, // @[LazyModuleImp.scala:107:25] input [4:0] auto_source_nodes_out_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_dest_nodes_in_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_dest_nodes_in_credit_return, // @[LazyModuleImp.scala:107:25] output [4:0] auto_dest_nodes_in_vc_free // @[LazyModuleImp.scala:107:25] ); wire [19:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire _vc_allocator_io_req_2_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_0_ready; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_3_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_2_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_1_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_3_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_2_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_1_0; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_3_0_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_2_0_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_0_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_1_alloc; // @[Router.scala:133:30] wire _switch_allocator_io_req_2_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_0_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_3_0_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_3_0_tail; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_0_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_0_tail; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_0_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_0_tail; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_1_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_3_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_3_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_2_0; // @[Router.scala:132:34] wire _switch_io_out_3_0_valid; // @[Router.scala:131:24] wire _switch_io_out_3_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_3_0_bits_tail; // @[Router.scala:131:24] wire [72:0] _switch_io_out_3_0_bits_payload; // @[Router.scala:131:24] wire _switch_io_out_2_0_valid; // @[Router.scala:131:24] wire _switch_io_out_2_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_2_0_bits_tail; // @[Router.scala:131:24] wire [72:0] _switch_io_out_2_0_bits_payload; // @[Router.scala:131:24] wire _switch_io_out_1_0_valid; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_tail; // @[Router.scala:131:24] wire [72:0] _switch_io_out_1_0_bits_payload; // @[Router.scala:131:24] wire _switch_io_out_0_0_valid; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_tail; // @[Router.scala:131:24] wire [72:0] _switch_io_out_0_0_bits_payload; // @[Router.scala:131:24] wire [2:0] _switch_io_out_0_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_0_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_0_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_0_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_0_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [2:0] _switch_io_out_0_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _egress_unit_3_to_22_io_credit_available_0; // @[Router.scala:125:13] wire _egress_unit_3_to_22_io_channel_status_0_occupied; // @[Router.scala:125:13] wire _egress_unit_3_to_22_io_out_valid; // @[Router.scala:125:13] wire _egress_unit_2_to_21_io_credit_available_0; // @[Router.scala:125:13] wire _egress_unit_2_to_21_io_channel_status_0_occupied; // @[Router.scala:125:13] wire _egress_unit_2_to_21_io_out_valid; // @[Router.scala:125:13] wire _egress_unit_1_to_20_io_credit_available_0; // @[Router.scala:125:13] wire _egress_unit_1_to_20_io_channel_status_0_occupied; // @[Router.scala:125:13] wire _egress_unit_1_to_20_io_out_valid; // @[Router.scala:125:13] wire _output_unit_0_to_16_io_credit_available_1; // @[Router.scala:122:13] wire _output_unit_0_to_16_io_channel_status_1_occupied; // @[Router.scala:122:13] wire _ingress_unit_2_from_16_io_vcalloc_req_valid; // @[Router.scala:116:13] wire _ingress_unit_2_from_16_io_vcalloc_req_bits_vc_sel_3_0; // @[Router.scala:116:13] wire _ingress_unit_2_from_16_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:116:13] wire _ingress_unit_2_from_16_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:116:13] wire _ingress_unit_2_from_16_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:116:13] wire _ingress_unit_2_from_16_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:116:13] wire _ingress_unit_2_from_16_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:116:13] wire _ingress_unit_2_from_16_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:116:13] wire _ingress_unit_2_from_16_io_vcalloc_req_bits_vc_sel_0_4; // @[Router.scala:116:13] wire _ingress_unit_2_from_16_io_salloc_req_0_valid; // @[Router.scala:116:13] wire _ingress_unit_2_from_16_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:116:13] wire _ingress_unit_2_from_16_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:116:13] wire _ingress_unit_2_from_16_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:116:13] wire _ingress_unit_2_from_16_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:116:13] wire _ingress_unit_2_from_16_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:116:13] wire _ingress_unit_2_from_16_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:116:13] wire _ingress_unit_2_from_16_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:116:13] wire _ingress_unit_2_from_16_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:116:13] wire _ingress_unit_2_from_16_io_salloc_req_0_bits_tail; // @[Router.scala:116:13] wire _ingress_unit_2_from_16_io_out_0_valid; // @[Router.scala:116:13] wire _ingress_unit_2_from_16_io_out_0_bits_flit_head; // @[Router.scala:116:13] wire _ingress_unit_2_from_16_io_out_0_bits_flit_tail; // @[Router.scala:116:13] wire [72:0] _ingress_unit_2_from_16_io_out_0_bits_flit_payload; // @[Router.scala:116:13] wire [2:0] _ingress_unit_2_from_16_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:116:13] wire [4:0] _ingress_unit_2_from_16_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:116:13] wire [1:0] _ingress_unit_2_from_16_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:116:13] wire [4:0] _ingress_unit_2_from_16_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:116:13] wire [1:0] _ingress_unit_2_from_16_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:116:13] wire [2:0] _ingress_unit_2_from_16_io_out_0_bits_out_virt_channel; // @[Router.scala:116:13] wire _ingress_unit_2_from_16_io_in_ready; // @[Router.scala:116:13] wire _input_unit_0_from_16_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_vcalloc_req_bits_vc_sel_3_0; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_0_from_16_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [72:0] _input_unit_0_from_16_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_16_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [4:0] _input_unit_0_from_16_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_16_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_0_from_16_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_16_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [1:0] fires_count = {1'h0, _vc_allocator_io_req_2_ready & _ingress_unit_2_from_16_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_0_ready & _input_unit_0_from_16_io_vcalloc_req_valid}; // @[Decoupled.scala:51:35] reg REG_3_0_2_0; // @[Router.scala:178:14] reg REG_3_0_0_0; // @[Router.scala:178:14] reg REG_2_0_2_0; // @[Router.scala:178:14] reg REG_2_0_0_0; // @[Router.scala:178:14] reg REG_1_0_2_0; // @[Router.scala:178:14] reg REG_1_0_0_0; // @[Router.scala:178:14] reg REG_0_0_2_0; // @[Router.scala:178:14] reg [63:0] debug_tsc; // @[Router.scala:195:28] reg [63:0] debug_sample; // @[Router.scala:197:31] wire _GEN = debug_sample == {44'h0, _plusarg_reader_out - 20'h1}; // @[PlusArg.scala:80:11] reg [63:0] util_ctr; // @[Router.scala:203:29] reg fired; // @[Router.scala:204:26] wire _GEN_0 = (\|_plusarg_reader_out) & _GEN; // @[PlusArg.scala:80:11] wire _GEN_1 = _GEN_0 & fired; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_2; // @[Router.scala:203:29] reg fired_2; // @[Router.scala:204:26] wire _GEN_2 = _GEN_0 & fired_2; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_3; // @[Router.scala:203:29] reg fired_3; // @[Router.scala:204:26] wire _GEN_3 = _GEN_0 & fired_3; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_4; // @[Router.scala:203:29] reg fired_4; // @[Router.scala:204:26] wire _GEN_4 = _GEN_0 & fired_4; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_5; // @[Router.scala:203:29] reg fired_5; // @[Router.scala:204:26] wire _GEN_5 = _GEN_0 & fired_5; // @[Router.scala:204:26, :207:{33,71}]
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_32 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_source_valid_0 of AsyncResetSynchronizerShiftReg_w1_d3_i0_32 connect io_out_source_valid_0.clock, clock connect io_out_source_valid_0.reset, reset connect io_out_source_valid_0.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_source_valid_0.io.q connect io.out, _io_out_WIRE	module AsyncValidSync_32( // @[AsyncQueue.scala:58:7] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in = 1'h1; // @[ShiftReg.scala:45:23] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_32 io_out_source_valid_0 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_98 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_sink_extend of AsyncResetSynchronizerShiftReg_w1_d3_i0_102 connect io_out_sink_extend.clock, clock connect io_out_sink_extend.reset, reset connect io_out_sink_extend.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_sink_extend.io.q connect io.out, _io_out_WIRE	module AsyncValidSync_98( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_102 io_out_sink_extend ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_100 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_sink_valid_0 of AsyncResetSynchronizerShiftReg_w1_d3_i0_117 connect io_out_sink_valid_0.clock, clock connect io_out_sink_valid_0.reset, reset connect io_out_sink_valid_0.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_sink_valid_0.io.q connect io.out, _io_out_WIRE	module AsyncValidSync_100( // @[AsyncQueue.scala:58:7] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in = 1'h1; // @[ShiftReg.scala:45:23] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_117 io_out_sink_valid_0 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module ICache : input clock : Clock input reset : Reset output auto : { master_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>}}, flip s1_paddr : UInt<32>, flip s2_vaddr : UInt<32>, flip s1_kill : UInt<1>, flip s2_kill : UInt<1>, flip s2_cacheable : UInt<1>, flip s2_prefetch : UInt<1>, resp : { valid : UInt<1>, bits : { data : UInt<32>, replay : UInt<1>, ae : UInt<1>}}, flip invalidate : UInt<1>, errors : { bus : { valid : UInt<1>, bits : UInt<32>}}, perf : { acquire : UInt<1>}, flip clock_enabled : UInt<1>, keep_clock_enabled : UInt<1>} wire masterNodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate masterNodeOut.d.bits.corrupt invalidate masterNodeOut.d.bits.data invalidate masterNodeOut.d.bits.denied invalidate masterNodeOut.d.bits.sink invalidate masterNodeOut.d.bits.source invalidate masterNodeOut.d.bits.size invalidate masterNodeOut.d.bits.param invalidate masterNodeOut.d.bits.opcode invalidate masterNodeOut.d.valid invalidate masterNodeOut.d.ready invalidate masterNodeOut.a.bits.corrupt invalidate masterNodeOut.a.bits.data invalidate masterNodeOut.a.bits.mask invalidate masterNodeOut.a.bits.address invalidate masterNodeOut.a.bits.source invalidate masterNodeOut.a.bits.size invalidate masterNodeOut.a.bits.param invalidate masterNodeOut.a.bits.opcode invalidate masterNodeOut.a.valid invalidate masterNodeOut.a.ready connect auto.master_out, masterNodeOut regreset scratchpadOn : UInt<1>, clock, reset, UInt<1>(0h0) regreset s1_slaveValid : UInt<1>, clock, reset, UInt<1>(0h0) connect s1_slaveValid, UInt<1>(0h0) regreset s2_slaveValid : UInt<1>, clock, reset, UInt<1>(0h0) connect s2_slaveValid, s1_slaveValid reg s3_slaveValid : UInt<1>, clock connect s3_slaveValid, UInt<1>(0h0) node s0_valid = and(io.req.ready, io.req.valid) regreset s1_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg s1_vaddr : UInt<32>, clock when s0_valid : connect s1_vaddr, io.req.bits.addr wire s1_tag_hit : UInt<1>[1] node _s1_hit_T = mux(s1_slaveValid, UInt<1>(0h1), UInt<1>(0h0)) node s1_hit = or(s1_tag_hit[0], _s1_hit_T) node _s2_valid_T = eq(io.s1_kill, UInt<1>(0h0)) node _s2_valid_T_1 = and(s1_valid, _s2_valid_T) regreset s2_valid : UInt<1>, clock, reset, UInt<1>(0h0) connect s2_valid, _s2_valid_T_1 reg s2_hit : UInt<1>, clock connect s2_hit, s1_hit reg invalidated : UInt<1>, clock regreset refill_valid : UInt<1>, clock, reset, UInt<1>(0h0) regreset send_hint : UInt<1>, clock, reset, UInt<1>(0h0) node _refill_fire_T = and(masterNodeOut.a.ready, masterNodeOut.a.valid) node _refill_fire_T_1 = eq(send_hint, UInt<1>(0h0)) node refill_fire = and(_refill_fire_T, _refill_fire_T_1) regreset hint_outstanding : UInt<1>, clock, reset, UInt<1>(0h0) node _s2_miss_T = eq(s2_hit, UInt<1>(0h0)) node _s2_miss_T_1 = and(s2_valid, _s2_miss_T) node _s2_miss_T_2 = eq(io.s2_kill, UInt<1>(0h0)) node s2_miss = and(_s2_miss_T_1, _s2_miss_T_2) node _s1_can_request_refill_T = or(s2_miss, refill_valid) node s1_can_request_refill = eq(_s1_can_request_refill_T, UInt<1>(0h0)) reg s2_request_refill_REG : UInt<1>, clock connect s2_request_refill_REG, s1_can_request_refill node s2_request_refill = and(s2_miss, s2_request_refill_REG) node _refill_paddr_T = and(s1_valid, s1_can_request_refill) reg refill_paddr : UInt<32>, clock when _refill_paddr_T : connect refill_paddr, io.s1_paddr node _refill_vaddr_T = and(s1_valid, s1_can_request_refill) reg refill_vaddr : UInt<32>, clock when _refill_vaddr_T : connect refill_vaddr, s1_vaddr node refill_tag = shr(refill_paddr, 12) node refill_idx = bits(refill_paddr, 11, 6) node _refill_one_beat_T = and(masterNodeOut.d.ready, masterNodeOut.d.valid) node refill_one_beat_opdata = bits(masterNodeOut.d.bits.opcode, 0, 0) node refill_one_beat = and(_refill_one_beat_T, refill_one_beat_opdata) node _io_req_ready_T = or(refill_one_beat, UInt<1>(0h0)) node _io_req_ready_T_1 = or(_io_req_ready_T, s3_slaveValid) node _io_req_ready_T_2 = eq(_io_req_ready_T_1, UInt<1>(0h0)) connect io.req.ready, _io_req_ready_T_2 connect s1_valid, s0_valid node _T = and(masterNodeOut.d.ready, masterNodeOut.d.valid) node _r_beats1_decode_T = dshl(UInt<12>(0hfff), masterNodeOut.d.bits.size) node _r_beats1_decode_T_1 = bits(_r_beats1_decode_T, 11, 0) node _r_beats1_decode_T_2 = not(_r_beats1_decode_T_1) node r_beats1_decode = shr(_r_beats1_decode_T_2, 3) node r_beats1_opdata = bits(masterNodeOut.d.bits.opcode, 0, 0) node r_beats1 = mux(r_beats1_opdata, r_beats1_decode, UInt<1>(0h0)) regreset r_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _r_counter1_T = sub(r_counter, UInt<1>(0h1)) node r_counter1 = tail(_r_counter1_T, 1) node r_1 = eq(r_counter, UInt<1>(0h0)) node _r_last_T = eq(r_counter, UInt<1>(0h1)) node _r_last_T_1 = eq(r_beats1, UInt<1>(0h0)) node r_2 = or(_r_last_T, _r_last_T_1) node d_done = and(r_2, _T) node _r_count_T = not(r_counter1) node refill_cnt = and(r_beats1, _r_count_T) when _T : node _r_counter_T = mux(r_1, r_beats1, r_counter1) connect r_counter, _r_counter_T node refill_done = and(refill_one_beat, d_done) node _masterNodeOut_d_ready_T = eq(s3_slaveValid, UInt<1>(0h0)) connect masterNodeOut.d.ready, _masterNodeOut_d_ready_T smem rockettile_icache_tag_array : UInt<21>[1] [64] node _tag_rdata_T = bits(io.req.bits.addr, 11, 6) node _tag_rdata_T_1 = eq(refill_done, UInt<1>(0h0)) node _tag_rdata_T_2 = and(_tag_rdata_T_1, s0_valid) wire _tag_rdata_WIRE : UInt<6> invalidate _tag_rdata_WIRE when _tag_rdata_T_2 : connect _tag_rdata_WIRE, _tag_rdata_T read mport tag_rdata = rockettile_icache_tag_array[_tag_rdata_WIRE], clock reg accruedRefillError : UInt<1>, clock node _refillError_T = gt(refill_cnt, UInt<1>(0h0)) node _refillError_T_1 = and(_refillError_T, accruedRefillError) node refillError = or(masterNodeOut.d.bits.corrupt, _refillError_T_1) when refill_done : node enc_tag = cat(refillError, refill_tag) wire _WIRE : UInt<21>[1] connect _WIRE[0], enc_tag node _T_1 = eq(UInt<1>(0h0), UInt<1>(0h0)) write mport MPORT = rockettile_icache_tag_array[refill_idx], clock when _T_1 : connect MPORT[0], _WIRE[0] node _io_errors_bus_valid_T = and(masterNodeOut.d.ready, masterNodeOut.d.valid) node _io_errors_bus_valid_T_1 = or(masterNodeOut.d.bits.denied, masterNodeOut.d.bits.corrupt) node _io_errors_bus_valid_T_2 = and(_io_errors_bus_valid_T, _io_errors_bus_valid_T_1) connect io.errors.bus.valid, _io_errors_bus_valid_T_2 node _io_errors_bus_bits_T = shr(refill_paddr, 6) node _io_errors_bus_bits_T_1 = shl(_io_errors_bus_bits_T, 6) connect io.errors.bus.bits, _io_errors_bus_bits_T_1 regreset vb_array : UInt<64>, clock, reset, UInt<64>(0h0) when refill_one_beat : connect accruedRefillError, refillError node _vb_array_T = cat(UInt<1>(0h0), refill_idx) node _vb_array_T_1 = eq(invalidated, UInt<1>(0h0)) node _vb_array_T_2 = and(refill_done, _vb_array_T_1) node _vb_array_T_3 = dshl(UInt<1>(0h1), _vb_array_T) node _vb_array_T_4 = or(vb_array, _vb_array_T_3) node _vb_array_T_5 = not(vb_array) node _vb_array_T_6 = or(_vb_array_T_5, _vb_array_T_3) node _vb_array_T_7 = not(_vb_array_T_6) node _vb_array_T_8 = mux(_vb_array_T_2, _vb_array_T_4, _vb_array_T_7) connect vb_array, _vb_array_T_8 wire invalidate : UInt<1> connect invalidate, io.invalidate when invalidate : connect vb_array, UInt<1>(0h0) connect invalidated, UInt<1>(0h1) wire s1_tag_disparity : UInt<1>[1] wire s1_tl_error : UInt<1>[1] wire s1_dout : UInt<32>[1] invalidate s1_dout[0] reg s1s3_slaveAddr : UInt<12>, clock reg s1s3_slaveData : UInt<32>, clock node s1_idx = bits(io.s1_paddr, 11, 6) node s1_tag = shr(io.s1_paddr, 12) node _scratchpadHit_T = lt(UInt<1>(0h0), UInt<1>(0h0)) node _scratchpadHit_T_1 = bits(s1s3_slaveAddr, 11, 6) node _scratchpadHit_T_2 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _scratchpadHit_T_3 = and(UInt<1>(0h0), _scratchpadHit_T_2) node _scratchpadHit_T_4 = bits(io.s1_paddr, 11, 6) node _scratchpadHit_T_5 = and(UInt<1>(0h0), UInt<1>(0h0)) node _scratchpadHit_T_6 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _scratchpadHit_T_7 = and(_scratchpadHit_T_5, _scratchpadHit_T_6) node _scratchpadHit_T_8 = mux(s1_slaveValid, _scratchpadHit_T_3, _scratchpadHit_T_7) node scratchpadHit = and(_scratchpadHit_T, _scratchpadHit_T_8) node _s1_vb_T = cat(UInt<1>(0h0), s1_idx) node _s1_vb_T_1 = dshr(vb_array, _s1_vb_T) node _s1_vb_T_2 = bits(_s1_vb_T_1, 0, 0) node _s1_vb_T_3 = eq(s1_slaveValid, UInt<1>(0h0)) node s1_vb = and(_s1_vb_T_2, _s1_vb_T_3) node tl_error = bits(tag_rdata[0], 20, 20) node tag = bits(tag_rdata[0], 19, 0) node _tagMatch_T = eq(tag, s1_tag) node tagMatch = and(s1_vb, _tagMatch_T) node _s1_tag_disparity_0_T = or(UInt<1>(0h0), UInt<1>(0h0)) node _s1_tag_disparity_0_T_1 = and(s1_vb, _s1_tag_disparity_0_T) connect s1_tag_disparity[0], _s1_tag_disparity_0_T_1 node _s1_tl_error_0_T = bits(tl_error, 0, 0) node _s1_tl_error_0_T_1 = and(tagMatch, _s1_tl_error_0_T) connect s1_tl_error[0], _s1_tl_error_0_T_1 node _s1_tag_hit_0_T = or(tagMatch, scratchpadHit) connect s1_tag_hit[0], _s1_tag_hit_0_T node _T_2 = or(s1_valid, s1_slaveValid) node _T_3 = eq(_T_2, UInt<1>(0h0)) node _T_4 = eq(s1_tag_disparity[0], UInt<1>(0h0)) node _T_5 = and(s1_tag_hit[0], _T_4) node _T_6 = leq(_T_5, UInt<1>(0h1)) node _T_7 = or(_T_3, _T_6) node _T_8 = asUInt(reset) node _T_9 = eq(_T_8, UInt<1>(0h0)) when _T_9 : node _T_10 = eq(_T_7, UInt<1>(0h0)) when _T_10 : printf(clock, UInt<1>(0h1), "Assertion failed\n at ICache.scala:521 assert(!(s1_valid \|\| s1_slaveValid) \|\| PopCount(s1_tag_hit zip s1_tag_disparity map { case (h, d) => h && !d }) <= 1.U)\n") : printf assert(clock, _T_7, UInt<1>(0h1), "") : assert smem rockettile_icache_data_arrays_0 : UInt<32>[1] [512] smem rockettile_icache_data_arrays_1 : UInt<32>[1] [512] node _s0_ren_T = bits(io.req.bits.addr, 2, 2) node _s0_ren_T_1 = eq(_s0_ren_T, UInt<1>(0h0)) node _s0_ren_T_2 = and(s0_valid, _s0_ren_T_1) node _s0_ren_T_3 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _s0_ren_T_4 = and(UInt<1>(0h0), _s0_ren_T_3) node s0_ren = or(_s0_ren_T_2, _s0_ren_T_4) node _wen_T = eq(invalidated, UInt<1>(0h0)) node _wen_T_1 = and(refill_one_beat, _wen_T) node _wen_T_2 = bits(s1s3_slaveAddr, 2, 2) node _wen_T_3 = eq(_wen_T_2, UInt<1>(0h0)) node _wen_T_4 = and(s3_slaveValid, _wen_T_3) node wen = or(_wen_T_1, _wen_T_4) node _mem_idx_T = shl(refill_idx, 3) node _mem_idx_T_1 = or(_mem_idx_T, refill_cnt) node _mem_idx_T_2 = bits(s1s3_slaveAddr, 11, 3) node _mem_idx_T_3 = bits(io.req.bits.addr, 11, 3) node _mem_idx_T_4 = mux(UInt<1>(0h0), UInt<9>(0h0), _mem_idx_T_3) node _mem_idx_T_5 = mux(s3_slaveValid, _mem_idx_T_2, _mem_idx_T_4) node mem_idx = mux(refill_one_beat, _mem_idx_T_1, _mem_idx_T_5) when wen : node _data_T = bits(masterNodeOut.d.bits.data, 31, 0) node data = mux(s3_slaveValid, s1s3_slaveData, _data_T) node way = mux(s3_slaveValid, UInt<1>(0h0), UInt<1>(0h0)) wire _WIRE_1 : UInt<32>[1] connect _WIRE_1[0], data node _T_11 = eq(way, UInt<1>(0h0)) write mport MPORT_1 = rockettile_icache_data_arrays_0[mem_idx], clock when _T_11 : connect MPORT_1[0], _WIRE_1[0] node _dout_T = eq(wen, UInt<1>(0h0)) node _dout_T_1 = and(_dout_T, s0_ren) wire _dout_WIRE : UInt<9> invalidate _dout_WIRE when _dout_T_1 : connect _dout_WIRE, mem_idx read mport dout = rockettile_icache_data_arrays_0[_dout_WIRE], clock node _T_12 = mux(s1_slaveValid, s1s3_slaveAddr, io.s1_paddr) node _T_13 = bits(_T_12, 2, 2) node _T_14 = eq(_T_13, UInt<1>(0h0)) when _T_14 : connect s1_dout, dout node _s0_ren_T_5 = bits(io.req.bits.addr, 2, 2) node _s0_ren_T_6 = eq(_s0_ren_T_5, UInt<1>(0h1)) node _s0_ren_T_7 = and(s0_valid, _s0_ren_T_6) node _s0_ren_T_8 = eq(UInt<1>(0h0), UInt<1>(0h1)) node _s0_ren_T_9 = and(UInt<1>(0h0), _s0_ren_T_8) node s0_ren_1 = or(_s0_ren_T_7, _s0_ren_T_9) node _wen_T_5 = eq(invalidated, UInt<1>(0h0)) node _wen_T_6 = and(refill_one_beat, _wen_T_5) node _wen_T_7 = bits(s1s3_slaveAddr, 2, 2) node _wen_T_8 = eq(_wen_T_7, UInt<1>(0h1)) node _wen_T_9 = and(s3_slaveValid, _wen_T_8) node wen_1 = or(_wen_T_6, _wen_T_9) node _mem_idx_T_6 = shl(refill_idx, 3) node _mem_idx_T_7 = or(_mem_idx_T_6, refill_cnt) node _mem_idx_T_8 = bits(s1s3_slaveAddr, 11, 3) node _mem_idx_T_9 = bits(io.req.bits.addr, 11, 3) node _mem_idx_T_10 = mux(UInt<1>(0h0), UInt<9>(0h0), _mem_idx_T_9) node _mem_idx_T_11 = mux(s3_slaveValid, _mem_idx_T_8, _mem_idx_T_10) node mem_idx_1 = mux(refill_one_beat, _mem_idx_T_7, _mem_idx_T_11) when wen_1 : node _data_T_1 = bits(masterNodeOut.d.bits.data, 63, 32) node data_1 = mux(s3_slaveValid, s1s3_slaveData, _data_T_1) node way_1 = mux(s3_slaveValid, UInt<1>(0h0), UInt<1>(0h0)) wire _WIRE_2 : UInt<32>[1] connect _WIRE_2[0], data_1 node _T_15 = eq(way_1, UInt<1>(0h0)) write mport MPORT_2 = rockettile_icache_data_arrays_1[mem_idx_1], clock when _T_15 : connect MPORT_2[0], _WIRE_2[0] node _dout_T_2 = eq(wen_1, UInt<1>(0h0)) node _dout_T_3 = and(_dout_T_2, s0_ren_1) wire _dout_WIRE_1 : UInt<9> invalidate _dout_WIRE_1 when _dout_T_3 : connect _dout_WIRE_1, mem_idx_1 read mport dout_1 = rockettile_icache_data_arrays_1[_dout_WIRE_1], clock node _T_16 = mux(s1_slaveValid, s1s3_slaveAddr, io.s1_paddr) node _T_17 = bits(_T_16, 2, 2) node _T_18 = eq(_T_17, UInt<1>(0h1)) when _T_18 : connect s1_dout, dout_1 wire s1s2_full_word_write : UInt<1> connect s1s2_full_word_write, UInt<1>(0h0) node s1_dont_read = and(s1_slaveValid, s1s2_full_word_write) node s1_clk_en = or(s1_valid, s1_slaveValid) wire _s2_tag_hit_WIRE : UInt<1>[1] connect _s2_tag_hit_WIRE[0], UInt<1>(0h0) node _s2_tag_hit_T = mux(s1_dont_read, _s2_tag_hit_WIRE, s1_tag_hit) reg s2_tag_hit : UInt<1>[1], clock when s1_clk_en : connect s2_tag_hit, _s2_tag_hit_T node _s2_scratchpad_word_addr_T = mux(s2_slaveValid, s1s3_slaveAddr, io.s2_vaddr) node _s2_scratchpad_word_addr_T_1 = bits(_s2_scratchpad_word_addr_T, 11, 2) node s2_scratchpad_word_addr_hi = cat(UInt<1>(0h0), _s2_scratchpad_word_addr_T_1) node s2_scratchpad_word_addr = cat(s2_scratchpad_word_addr_hi, UInt<2>(0h0)) reg s2_dout : UInt<32>[1], clock when s1_clk_en : connect s2_dout, s1_dout reg s2_tag_disparity_r : UInt<1>[1], clock when s1_clk_en : connect s2_tag_disparity_r, s1_tag_disparity node s2_tag_disparity = orr(s2_tag_disparity_r[0]) node _s2_tl_error_T = orr(s1_tl_error[0]) reg s2_tl_error : UInt<1>, clock when s1_clk_en : connect s2_tl_error, _s2_tl_error_T node _s2_disparity_T = or(UInt<1>(0h0), UInt<1>(0h0)) node s2_disparity = or(s2_tag_disparity, _s2_disparity_T) node _s1_scratchpad_hit_T = bits(s1s3_slaveAddr, 11, 6) node _s1_scratchpad_hit_T_1 = bits(io.s1_paddr, 11, 6) node _s1_scratchpad_hit_T_2 = and(UInt<1>(0h0), UInt<1>(0h0)) node s1_scratchpad_hit = mux(s1_slaveValid, UInt<1>(0h0), _s1_scratchpad_hit_T_2) reg s2_scratchpad_hit : UInt<1>, clock when s1_clk_en : connect s2_scratchpad_hit, s1_scratchpad_hit node _s2_report_uncorrectable_error_T = and(s2_scratchpad_hit, UInt<1>(0h0)) node _s2_report_uncorrectable_error_T_1 = eq(s1s2_full_word_write, UInt<1>(0h0)) node _s2_report_uncorrectable_error_T_2 = and(s2_slaveValid, _s2_report_uncorrectable_error_T_1) node _s2_report_uncorrectable_error_T_3 = or(s2_valid, _s2_report_uncorrectable_error_T_2) node s2_report_uncorrectable_error = and(_s2_report_uncorrectable_error_T, _s2_report_uncorrectable_error_T_3) node _T_19 = and(s2_valid, s2_disparity) when _T_19 : connect invalidate, UInt<1>(0h1) connect io.resp.bits.data, s2_dout[0] connect io.resp.bits.ae, s2_tl_error connect io.resp.bits.replay, s2_disparity node _io_resp_valid_T = and(s2_valid, s2_hit) connect io.resp.valid, _io_resp_valid_T connect masterNodeOut.a.valid, s2_request_refill node _masterNodeOut_a_bits_T = shr(refill_paddr, 6) node _masterNodeOut_a_bits_T_1 = shl(_masterNodeOut_a_bits_T, 6) node _masterNodeOut_a_bits_legal_T = leq(UInt<1>(0h0), UInt<3>(0h6)) node _masterNodeOut_a_bits_legal_T_1 = leq(UInt<3>(0h6), UInt<4>(0hc)) node _masterNodeOut_a_bits_legal_T_2 = and(_masterNodeOut_a_bits_legal_T, _masterNodeOut_a_bits_legal_T_1) node _masterNodeOut_a_bits_legal_T_3 = or(UInt<1>(0h0), _masterNodeOut_a_bits_legal_T_2) node _masterNodeOut_a_bits_legal_T_4 = xor(_masterNodeOut_a_bits_T_1, UInt<14>(0h3000)) node _masterNodeOut_a_bits_legal_T_5 = cvt(_masterNodeOut_a_bits_legal_T_4) node _masterNodeOut_a_bits_legal_T_6 = and(_masterNodeOut_a_bits_legal_T_5, asSInt(UInt<33>(0h8a113000))) node _masterNodeOut_a_bits_legal_T_7 = asSInt(_masterNodeOut_a_bits_legal_T_6) node _masterNodeOut_a_bits_legal_T_8 = eq(_masterNodeOut_a_bits_legal_T_7, asSInt(UInt<1>(0h0))) node _masterNodeOut_a_bits_legal_T_9 = and(_masterNodeOut_a_bits_legal_T_3, _masterNodeOut_a_bits_legal_T_8) node _masterNodeOut_a_bits_legal_T_10 = leq(UInt<1>(0h0), UInt<3>(0h6)) node _masterNodeOut_a_bits_legal_T_11 = leq(UInt<3>(0h6), UInt<3>(0h6)) node _masterNodeOut_a_bits_legal_T_12 = and(_masterNodeOut_a_bits_legal_T_10, _masterNodeOut_a_bits_legal_T_11) node _masterNodeOut_a_bits_legal_T_13 = or(UInt<1>(0h0), _masterNodeOut_a_bits_legal_T_12) node _masterNodeOut_a_bits_legal_T_14 = xor(_masterNodeOut_a_bits_T_1, UInt<1>(0h0)) node _masterNodeOut_a_bits_legal_T_15 = cvt(_masterNodeOut_a_bits_legal_T_14) node _masterNodeOut_a_bits_legal_T_16 = and(_masterNodeOut_a_bits_legal_T_15, asSInt(UInt<33>(0h8a112000))) node _masterNodeOut_a_bits_legal_T_17 = asSInt(_masterNodeOut_a_bits_legal_T_16) node _masterNodeOut_a_bits_legal_T_18 = eq(_masterNodeOut_a_bits_legal_T_17, asSInt(UInt<1>(0h0))) node _masterNodeOut_a_bits_legal_T_19 = xor(_masterNodeOut_a_bits_T_1, UInt<17>(0h10000)) node _masterNodeOut_a_bits_legal_T_20 = cvt(_masterNodeOut_a_bits_legal_T_19) node _masterNodeOut_a_bits_legal_T_21 = and(_masterNodeOut_a_bits_legal_T_20, asSInt(UInt<33>(0h8a110000))) node _masterNodeOut_a_bits_legal_T_22 = asSInt(_masterNodeOut_a_bits_legal_T_21) node _masterNodeOut_a_bits_legal_T_23 = eq(_masterNodeOut_a_bits_legal_T_22, asSInt(UInt<1>(0h0))) node _masterNodeOut_a_bits_legal_T_24 = xor(_masterNodeOut_a_bits_T_1, UInt<21>(0h100000)) node _masterNodeOut_a_bits_legal_T_25 = cvt(_masterNodeOut_a_bits_legal_T_24) node _masterNodeOut_a_bits_legal_T_26 = and(_masterNodeOut_a_bits_legal_T_25, asSInt(UInt<33>(0h8a103000))) node _masterNodeOut_a_bits_legal_T_27 = asSInt(_masterNodeOut_a_bits_legal_T_26) node _masterNodeOut_a_bits_legal_T_28 = eq(_masterNodeOut_a_bits_legal_T_27, asSInt(UInt<1>(0h0))) node _masterNodeOut_a_bits_legal_T_29 = xor(_masterNodeOut_a_bits_T_1, UInt<26>(0h2000000)) node _masterNodeOut_a_bits_legal_T_30 = cvt(_masterNodeOut_a_bits_legal_T_29) node _masterNodeOut_a_bits_legal_T_31 = and(_masterNodeOut_a_bits_legal_T_30, asSInt(UInt<33>(0h8a110000))) node _masterNodeOut_a_bits_legal_T_32 = asSInt(_masterNodeOut_a_bits_legal_T_31) node _masterNodeOut_a_bits_legal_T_33 = eq(_masterNodeOut_a_bits_legal_T_32, asSInt(UInt<1>(0h0))) node _masterNodeOut_a_bits_legal_T_34 = xor(_masterNodeOut_a_bits_T_1, UInt<28>(0h8000000)) node _masterNodeOut_a_bits_legal_T_35 = cvt(_masterNodeOut_a_bits_legal_T_34) node _masterNodeOut_a_bits_legal_T_36 = and(_masterNodeOut_a_bits_legal_T_35, asSInt(UInt<33>(0h88000000))) node _masterNodeOut_a_bits_legal_T_37 = asSInt(_masterNodeOut_a_bits_legal_T_36) node _masterNodeOut_a_bits_legal_T_38 = eq(_masterNodeOut_a_bits_legal_T_37, asSInt(UInt<1>(0h0))) node _masterNodeOut_a_bits_legal_T_39 = xor(_masterNodeOut_a_bits_T_1, UInt<32>(0h80000000)) node _masterNodeOut_a_bits_legal_T_40 = cvt(_masterNodeOut_a_bits_legal_T_39) node _masterNodeOut_a_bits_legal_T_41 = and(_masterNodeOut_a_bits_legal_T_40, asSInt(UInt<33>(0h8a110000))) node _masterNodeOut_a_bits_legal_T_42 = asSInt(_masterNodeOut_a_bits_legal_T_41) node _masterNodeOut_a_bits_legal_T_43 = eq(_masterNodeOut_a_bits_legal_T_42, asSInt(UInt<1>(0h0))) node _masterNodeOut_a_bits_legal_T_44 = or(_masterNodeOut_a_bits_legal_T_18, _masterNodeOut_a_bits_legal_T_23) node _masterNodeOut_a_bits_legal_T_45 = or(_masterNodeOut_a_bits_legal_T_44, _masterNodeOut_a_bits_legal_T_28) node _masterNodeOut_a_bits_legal_T_46 = or(_masterNodeOut_a_bits_legal_T_45, _masterNodeOut_a_bits_legal_T_33) node _masterNodeOut_a_bits_legal_T_47 = or(_masterNodeOut_a_bits_legal_T_46, _masterNodeOut_a_bits_legal_T_38) node _masterNodeOut_a_bits_legal_T_48 = or(_masterNodeOut_a_bits_legal_T_47, _masterNodeOut_a_bits_legal_T_43) node _masterNodeOut_a_bits_legal_T_49 = and(_masterNodeOut_a_bits_legal_T_13, _masterNodeOut_a_bits_legal_T_48) node _masterNodeOut_a_bits_legal_T_50 = or(UInt<1>(0h0), _masterNodeOut_a_bits_legal_T_9) node masterNodeOut_a_bits_legal = or(_masterNodeOut_a_bits_legal_T_50, _masterNodeOut_a_bits_legal_T_49) wire masterNodeOut_a_bits_a : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} connect masterNodeOut_a_bits_a.opcode, UInt<3>(0h4) connect masterNodeOut_a_bits_a.param, UInt<1>(0h0) connect masterNodeOut_a_bits_a.size, UInt<3>(0h6) connect masterNodeOut_a_bits_a.source, UInt<1>(0h0) connect masterNodeOut_a_bits_a.address, _masterNodeOut_a_bits_T_1 node _masterNodeOut_a_bits_a_mask_sizeOH_T = or(UInt<3>(0h6), UInt<3>(0h0)) node masterNodeOut_a_bits_a_mask_sizeOH_shiftAmount = bits(_masterNodeOut_a_bits_a_mask_sizeOH_T, 1, 0) node _masterNodeOut_a_bits_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), masterNodeOut_a_bits_a_mask_sizeOH_shiftAmount) node _masterNodeOut_a_bits_a_mask_sizeOH_T_2 = bits(_masterNodeOut_a_bits_a_mask_sizeOH_T_1, 2, 0) node masterNodeOut_a_bits_a_mask_sizeOH = or(_masterNodeOut_a_bits_a_mask_sizeOH_T_2, UInt<1>(0h1)) node masterNodeOut_a_bits_a_mask_sub_sub_sub_0_1 = geq(UInt<3>(0h6), UInt<2>(0h3)) node masterNodeOut_a_bits_a_mask_sub_sub_size = bits(masterNodeOut_a_bits_a_mask_sizeOH, 2, 2) node masterNodeOut_a_bits_a_mask_sub_sub_bit = bits(_masterNodeOut_a_bits_T_1, 2, 2) node masterNodeOut_a_bits_a_mask_sub_sub_nbit = eq(masterNodeOut_a_bits_a_mask_sub_sub_bit, UInt<1>(0h0)) node masterNodeOut_a_bits_a_mask_sub_sub_0_2 = and(UInt<1>(0h1), masterNodeOut_a_bits_a_mask_sub_sub_nbit) node _masterNodeOut_a_bits_a_mask_sub_sub_acc_T = and(masterNodeOut_a_bits_a_mask_sub_sub_size, masterNodeOut_a_bits_a_mask_sub_sub_0_2) node masterNodeOut_a_bits_a_mask_sub_sub_0_1 = or(masterNodeOut_a_bits_a_mask_sub_sub_sub_0_1, _masterNodeOut_a_bits_a_mask_sub_sub_acc_T) node masterNodeOut_a_bits_a_mask_sub_sub_1_2 = and(UInt<1>(0h1), masterNodeOut_a_bits_a_mask_sub_sub_bit) node _masterNodeOut_a_bits_a_mask_sub_sub_acc_T_1 = and(masterNodeOut_a_bits_a_mask_sub_sub_size, masterNodeOut_a_bits_a_mask_sub_sub_1_2) node masterNodeOut_a_bits_a_mask_sub_sub_1_1 = or(masterNodeOut_a_bits_a_mask_sub_sub_sub_0_1, _masterNodeOut_a_bits_a_mask_sub_sub_acc_T_1) node masterNodeOut_a_bits_a_mask_sub_size = bits(masterNodeOut_a_bits_a_mask_sizeOH, 1, 1) node masterNodeOut_a_bits_a_mask_sub_bit = bits(_masterNodeOut_a_bits_T_1, 1, 1) node masterNodeOut_a_bits_a_mask_sub_nbit = eq(masterNodeOut_a_bits_a_mask_sub_bit, UInt<1>(0h0)) node masterNodeOut_a_bits_a_mask_sub_0_2 = and(masterNodeOut_a_bits_a_mask_sub_sub_0_2, masterNodeOut_a_bits_a_mask_sub_nbit) node _masterNodeOut_a_bits_a_mask_sub_acc_T = and(masterNodeOut_a_bits_a_mask_sub_size, masterNodeOut_a_bits_a_mask_sub_0_2) node masterNodeOut_a_bits_a_mask_sub_0_1 = or(masterNodeOut_a_bits_a_mask_sub_sub_0_1, _masterNodeOut_a_bits_a_mask_sub_acc_T) node masterNodeOut_a_bits_a_mask_sub_1_2 = and(masterNodeOut_a_bits_a_mask_sub_sub_0_2, masterNodeOut_a_bits_a_mask_sub_bit) node _masterNodeOut_a_bits_a_mask_sub_acc_T_1 = and(masterNodeOut_a_bits_a_mask_sub_size, masterNodeOut_a_bits_a_mask_sub_1_2) node masterNodeOut_a_bits_a_mask_sub_1_1 = or(masterNodeOut_a_bits_a_mask_sub_sub_0_1, _masterNodeOut_a_bits_a_mask_sub_acc_T_1) node masterNodeOut_a_bits_a_mask_sub_2_2 = and(masterNodeOut_a_bits_a_mask_sub_sub_1_2, masterNodeOut_a_bits_a_mask_sub_nbit) node _masterNodeOut_a_bits_a_mask_sub_acc_T_2 = and(masterNodeOut_a_bits_a_mask_sub_size, masterNodeOut_a_bits_a_mask_sub_2_2) node masterNodeOut_a_bits_a_mask_sub_2_1 = or(masterNodeOut_a_bits_a_mask_sub_sub_1_1, _masterNodeOut_a_bits_a_mask_sub_acc_T_2) node masterNodeOut_a_bits_a_mask_sub_3_2 = and(masterNodeOut_a_bits_a_mask_sub_sub_1_2, masterNodeOut_a_bits_a_mask_sub_bit) node _masterNodeOut_a_bits_a_mask_sub_acc_T_3 = and(masterNodeOut_a_bits_a_mask_sub_size, masterNodeOut_a_bits_a_mask_sub_3_2) node masterNodeOut_a_bits_a_mask_sub_3_1 = or(masterNodeOut_a_bits_a_mask_sub_sub_1_1, _masterNodeOut_a_bits_a_mask_sub_acc_T_3) node masterNodeOut_a_bits_a_mask_size = bits(masterNodeOut_a_bits_a_mask_sizeOH, 0, 0) node masterNodeOut_a_bits_a_mask_bit = bits(_masterNodeOut_a_bits_T_1, 0, 0) node masterNodeOut_a_bits_a_mask_nbit = eq(masterNodeOut_a_bits_a_mask_bit, UInt<1>(0h0)) node masterNodeOut_a_bits_a_mask_eq = and(masterNodeOut_a_bits_a_mask_sub_0_2, masterNodeOut_a_bits_a_mask_nbit) node _masterNodeOut_a_bits_a_mask_acc_T = and(masterNodeOut_a_bits_a_mask_size, masterNodeOut_a_bits_a_mask_eq) node masterNodeOut_a_bits_a_mask_acc = or(masterNodeOut_a_bits_a_mask_sub_0_1, _masterNodeOut_a_bits_a_mask_acc_T) node masterNodeOut_a_bits_a_mask_eq_1 = and(masterNodeOut_a_bits_a_mask_sub_0_2, masterNodeOut_a_bits_a_mask_bit) node _masterNodeOut_a_bits_a_mask_acc_T_1 = and(masterNodeOut_a_bits_a_mask_size, masterNodeOut_a_bits_a_mask_eq_1) node masterNodeOut_a_bits_a_mask_acc_1 = or(masterNodeOut_a_bits_a_mask_sub_0_1, _masterNodeOut_a_bits_a_mask_acc_T_1) node masterNodeOut_a_bits_a_mask_eq_2 = and(masterNodeOut_a_bits_a_mask_sub_1_2, masterNodeOut_a_bits_a_mask_nbit) node _masterNodeOut_a_bits_a_mask_acc_T_2 = and(masterNodeOut_a_bits_a_mask_size, masterNodeOut_a_bits_a_mask_eq_2) node masterNodeOut_a_bits_a_mask_acc_2 = or(masterNodeOut_a_bits_a_mask_sub_1_1, _masterNodeOut_a_bits_a_mask_acc_T_2) node masterNodeOut_a_bits_a_mask_eq_3 = and(masterNodeOut_a_bits_a_mask_sub_1_2, masterNodeOut_a_bits_a_mask_bit) node _masterNodeOut_a_bits_a_mask_acc_T_3 = and(masterNodeOut_a_bits_a_mask_size, masterNodeOut_a_bits_a_mask_eq_3) node masterNodeOut_a_bits_a_mask_acc_3 = or(masterNodeOut_a_bits_a_mask_sub_1_1, _masterNodeOut_a_bits_a_mask_acc_T_3) node masterNodeOut_a_bits_a_mask_eq_4 = and(masterNodeOut_a_bits_a_mask_sub_2_2, masterNodeOut_a_bits_a_mask_nbit) node _masterNodeOut_a_bits_a_mask_acc_T_4 = and(masterNodeOut_a_bits_a_mask_size, masterNodeOut_a_bits_a_mask_eq_4) node masterNodeOut_a_bits_a_mask_acc_4 = or(masterNodeOut_a_bits_a_mask_sub_2_1, _masterNodeOut_a_bits_a_mask_acc_T_4) node masterNodeOut_a_bits_a_mask_eq_5 = and(masterNodeOut_a_bits_a_mask_sub_2_2, masterNodeOut_a_bits_a_mask_bit) node _masterNodeOut_a_bits_a_mask_acc_T_5 = and(masterNodeOut_a_bits_a_mask_size, masterNodeOut_a_bits_a_mask_eq_5) node masterNodeOut_a_bits_a_mask_acc_5 = or(masterNodeOut_a_bits_a_mask_sub_2_1, _masterNodeOut_a_bits_a_mask_acc_T_5) node masterNodeOut_a_bits_a_mask_eq_6 = and(masterNodeOut_a_bits_a_mask_sub_3_2, masterNodeOut_a_bits_a_mask_nbit) node _masterNodeOut_a_bits_a_mask_acc_T_6 = and(masterNodeOut_a_bits_a_mask_size, masterNodeOut_a_bits_a_mask_eq_6) node masterNodeOut_a_bits_a_mask_acc_6 = or(masterNodeOut_a_bits_a_mask_sub_3_1, _masterNodeOut_a_bits_a_mask_acc_T_6) node masterNodeOut_a_bits_a_mask_eq_7 = and(masterNodeOut_a_bits_a_mask_sub_3_2, masterNodeOut_a_bits_a_mask_bit) node _masterNodeOut_a_bits_a_mask_acc_T_7 = and(masterNodeOut_a_bits_a_mask_size, masterNodeOut_a_bits_a_mask_eq_7) node masterNodeOut_a_bits_a_mask_acc_7 = or(masterNodeOut_a_bits_a_mask_sub_3_1, _masterNodeOut_a_bits_a_mask_acc_T_7) node masterNodeOut_a_bits_a_mask_lo_lo = cat(masterNodeOut_a_bits_a_mask_acc_1, masterNodeOut_a_bits_a_mask_acc) node masterNodeOut_a_bits_a_mask_lo_hi = cat(masterNodeOut_a_bits_a_mask_acc_3, masterNodeOut_a_bits_a_mask_acc_2) node masterNodeOut_a_bits_a_mask_lo = cat(masterNodeOut_a_bits_a_mask_lo_hi, masterNodeOut_a_bits_a_mask_lo_lo) node masterNodeOut_a_bits_a_mask_hi_lo = cat(masterNodeOut_a_bits_a_mask_acc_5, masterNodeOut_a_bits_a_mask_acc_4) node masterNodeOut_a_bits_a_mask_hi_hi = cat(masterNodeOut_a_bits_a_mask_acc_7, masterNodeOut_a_bits_a_mask_acc_6) node masterNodeOut_a_bits_a_mask_hi = cat(masterNodeOut_a_bits_a_mask_hi_hi, masterNodeOut_a_bits_a_mask_hi_lo) node _masterNodeOut_a_bits_a_mask_T = cat(masterNodeOut_a_bits_a_mask_hi, masterNodeOut_a_bits_a_mask_lo) connect masterNodeOut_a_bits_a.mask, _masterNodeOut_a_bits_a_mask_T invalidate masterNodeOut_a_bits_a.data connect masterNodeOut_a_bits_a.corrupt, UInt<1>(0h0) connect masterNodeOut.a.bits, masterNodeOut_a_bits_a wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits.corrupt, UInt<1>(0h0) connect _WIRE_3.bits.data, UInt<64>(0h0) connect _WIRE_3.bits.mask, UInt<8>(0h0) connect _WIRE_3.bits.address, UInt<32>(0h0) connect _WIRE_3.bits.source, UInt<1>(0h0) connect _WIRE_3.bits.size, UInt<4>(0h0) connect _WIRE_3.bits.param, UInt<2>(0h0) connect _WIRE_3.bits.opcode, UInt<3>(0h0) connect _WIRE_3.valid, UInt<1>(0h0) connect _WIRE_3.ready, UInt<1>(0h0) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits, _WIRE_3.bits connect _WIRE_4.valid, _WIRE_3.valid connect _WIRE_4.ready, _WIRE_3.ready connect _WIRE_4.ready, UInt<1>(0h1) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits.corrupt, UInt<1>(0h0) connect _WIRE_5.bits.data, UInt<64>(0h0) connect _WIRE_5.bits.address, UInt<32>(0h0) connect _WIRE_5.bits.source, UInt<1>(0h0) connect _WIRE_5.bits.size, UInt<4>(0h0) connect _WIRE_5.bits.param, UInt<3>(0h0) connect _WIRE_5.bits.opcode, UInt<3>(0h0) connect _WIRE_5.valid, UInt<1>(0h0) connect _WIRE_5.ready, UInt<1>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits, _WIRE_5.bits connect _WIRE_6.valid, _WIRE_5.valid connect _WIRE_6.ready, _WIRE_5.ready connect _WIRE_6.valid, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_7.bits.sink, UInt<1>(0h0) connect _WIRE_7.valid, UInt<1>(0h0) connect _WIRE_7.ready, UInt<1>(0h0) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits, _WIRE_7.bits connect _WIRE_8.valid, _WIRE_7.valid connect _WIRE_8.ready, _WIRE_7.ready connect _WIRE_8.valid, UInt<1>(0h0) node _T_20 = and(masterNodeOut.a.valid, UInt<1>(0h0)) node _T_21 = eq(_T_20, UInt<1>(0h0)) node _T_22 = asUInt(reset) node _T_23 = eq(_T_22, UInt<1>(0h0)) when _T_23 : node _T_24 = eq(_T_21, UInt<1>(0h0)) when _T_24 : printf(clock, UInt<1>(0h1), "Assertion failed\n at ICache.scala:826 assert(!(tl_out.a.valid && addrMaybeInScratchpad(tl_out.a.bits.address)))\n") : printf_1 assert(clock, _T_21, UInt<1>(0h1), "") : assert_1 node _T_25 = eq(refill_valid, UInt<1>(0h0)) when _T_25 : connect invalidated, UInt<1>(0h0) when refill_fire : connect refill_valid, UInt<1>(0h1) when refill_done : connect refill_valid, UInt<1>(0h0) connect io.perf.acquire, refill_fire node _io_keep_clock_enabled_T = or(UInt<1>(0h0), s1_valid) node _io_keep_clock_enabled_T_1 = or(_io_keep_clock_enabled_T, s2_valid) node _io_keep_clock_enabled_T_2 = or(_io_keep_clock_enabled_T_1, refill_valid) node _io_keep_clock_enabled_T_3 = or(_io_keep_clock_enabled_T_2, send_hint) node _io_keep_clock_enabled_T_4 = or(_io_keep_clock_enabled_T_3, hint_outstanding) connect io.keep_clock_enabled, _io_keep_clock_enabled_T_4 node _T_26 = eq(send_hint, UInt<1>(0h0)) node _T_27 = eq(masterNodeOut.a.ready, UInt<1>(0h0)) node _T_28 = and(masterNodeOut.a.valid, _T_27) node _T_29 = and(_T_26, _T_28) node _T_30 = and(invalidate, refill_valid) node _T_31 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_32 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = and(_T_31, _T_32) node _T_34 = eq(s2_slaveValid, UInt<1>(0h0)) node _T_35 = eq(s2_tag_disparity, UInt<1>(0h0)) node _T_36 = eq(s2_scratchpad_hit, UInt<1>(0h0)) node _T_37 = and(_T_34, s2_scratchpad_hit) node _T_38 = and(_T_34, _T_36) node _T_39 = and(s2_slaveValid, s2_scratchpad_hit) node _T_40 = and(s2_slaveValid, _T_36) node _T_41 = and(_T_35, _T_37) node _T_42 = and(_T_35, _T_38) node _T_43 = and(_T_35, _T_39) node _T_44 = and(_T_35, _T_40) node _T_45 = and(_T_34, s2_scratchpad_hit) node _T_46 = and(_T_34, _T_36) node _T_47 = and(s2_slaveValid, s2_scratchpad_hit) node _T_48 = and(s2_slaveValid, _T_36) node _T_49 = and(s2_tag_disparity, _T_45) node _T_50 = and(s2_tag_disparity, _T_46) node _T_51 = and(s2_tag_disparity, _T_47) node _T_52 = and(s2_tag_disparity, _T_48) node _T_53 = and(_T_33, _T_41) node _T_54 = and(_T_33, _T_42) node _T_55 = and(_T_33, _T_43) node _T_56 = and(_T_33, _T_44) node _T_57 = and(_T_33, _T_49) node _T_58 = and(_T_33, _T_50) node _T_59 = and(_T_33, _T_51) node _T_60 = and(_T_33, _T_52) node _T_61 = and(_T_34, s2_scratchpad_hit) node _T_62 = and(_T_34, _T_36) node _T_63 = and(s2_slaveValid, s2_scratchpad_hit) node _T_64 = and(s2_slaveValid, _T_36) node _T_65 = and(_T_35, _T_61) node _T_66 = and(_T_35, _T_62) node _T_67 = and(_T_35, _T_63) node _T_68 = and(_T_35, _T_64) node _T_69 = and(_T_34, s2_scratchpad_hit) node _T_70 = and(_T_34, _T_36) node _T_71 = and(s2_slaveValid, s2_scratchpad_hit) node _T_72 = and(s2_slaveValid, _T_36) node _T_73 = and(s2_tag_disparity, _T_69) node _T_74 = and(s2_tag_disparity, _T_70) node _T_75 = and(s2_tag_disparity, _T_71) node _T_76 = and(s2_tag_disparity, _T_72) node _T_77 = and(UInt<1>(0h0), _T_65) node _T_78 = and(UInt<1>(0h0), _T_66) node _T_79 = and(UInt<1>(0h0), _T_67) node _T_80 = and(UInt<1>(0h0), _T_68) node _T_81 = and(UInt<1>(0h0), _T_73) node _T_82 = and(UInt<1>(0h0), _T_74) node _T_83 = and(UInt<1>(0h0), _T_75) node _T_84 = and(UInt<1>(0h0), _T_76) node _T_85 = and(_T_34, s2_scratchpad_hit) node _T_86 = and(_T_34, _T_36) node _T_87 = and(s2_slaveValid, s2_scratchpad_hit) node _T_88 = and(s2_slaveValid, _T_36) node _T_89 = and(_T_35, _T_85) node _T_90 = and(_T_35, _T_86) node _T_91 = and(_T_35, _T_87) node _T_92 = and(_T_35, _T_88) node _T_93 = and(_T_34, s2_scratchpad_hit) node _T_94 = and(_T_34, _T_36) node _T_95 = and(s2_slaveValid, s2_scratchpad_hit) node _T_96 = and(s2_slaveValid, _T_36) node _T_97 = and(s2_tag_disparity, _T_93) node _T_98 = and(s2_tag_disparity, _T_94) node _T_99 = and(s2_tag_disparity, _T_95) node _T_100 = and(s2_tag_disparity, _T_96) node _T_101 = and(UInt<1>(0h0), _T_89) node _T_102 = and(UInt<1>(0h0), _T_90) node _T_103 = and(UInt<1>(0h0), _T_91) node _T_104 = and(UInt<1>(0h0), _T_92) node _T_105 = and(UInt<1>(0h0), _T_97) node _T_106 = and(UInt<1>(0h0), _T_98) node _T_107 = and(UInt<1>(0h0), _T_99) node _T_108 = and(UInt<1>(0h0), _T_100) node _T_109 = and(s2_valid, _T_53) node _T_110 = and(s2_valid, _T_54) node _T_111 = and(s2_valid, _T_55) node _T_112 = and(s2_valid, _T_56) node _T_113 = and(s2_valid, _T_57) node _T_114 = and(s2_valid, _T_58) node _T_115 = and(s2_valid, _T_59) node _T_116 = and(s2_valid, _T_60) node _T_117 = and(s2_valid, _T_77) node _T_118 = and(s2_valid, _T_78) node _T_119 = and(s2_valid, _T_79) node _T_120 = and(s2_valid, _T_80) node _T_121 = and(s2_valid, _T_81) node _T_122 = and(s2_valid, _T_82) node _T_123 = and(s2_valid, _T_83) node _T_124 = and(s2_valid, _T_84) node _T_125 = and(s2_valid, _T_101) node _T_126 = and(s2_valid, _T_102) node _T_127 = and(s2_valid, _T_103) node _T_128 = and(s2_valid, _T_104) node _T_129 = and(s2_valid, _T_105) node _T_130 = and(s2_valid, _T_106) node _T_131 = and(s2_valid, _T_107) node _T_132 = and(s2_valid, _T_108)	module ICache( // @[ICache.scala:251:7] input clock, // @[ICache.scala:251:7] input reset, // @[ICache.scala:251:7] input auto_master_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_master_out_a_valid, // @[LazyModuleImp.scala:107:25] output [31:0] auto_master_out_a_bits_address, // @[LazyModuleImp.scala:107:25] input auto_master_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_master_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_master_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_master_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input auto_master_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_master_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_master_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_master_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input io_req_valid, // @[ICache.scala:256:14] input [31:0] io_req_bits_addr, // @[ICache.scala:256:14] input [31:0] io_s1_paddr, // @[ICache.scala:256:14] input [31:0] io_s2_vaddr, // @[ICache.scala:256:14] input io_s1_kill, // @[ICache.scala:256:14] input io_s2_kill, // @[ICache.scala:256:14] input io_s2_cacheable, // @[ICache.scala:256:14] input io_s2_prefetch, // @[ICache.scala:256:14] output io_resp_valid, // @[ICache.scala:256:14] output [31:0] io_resp_bits_data, // @[ICache.scala:256:14] output io_resp_bits_ae, // @[ICache.scala:256:14] input io_invalidate, // @[ICache.scala:256:14] output io_errors_bus_valid, // @[ICache.scala:256:14] output [31:0] io_errors_bus_bits, // @[ICache.scala:256:14] output io_perf_acquire // @[ICache.scala:256:14] ); wire [31:0] _rockettile_icache_data_arrays_1_0_RW0_rdata; // @[DescribedSRAM.scala:17:26] wire [31:0] _rockettile_icache_data_arrays_0_0_RW0_rdata; // @[DescribedSRAM.scala:17:26] wire [20:0] _rockettile_icache_tag_array_0_RW0_rdata; // @[DescribedSRAM.scala:17:26] wire auto_master_out_a_ready_0 = auto_master_out_a_ready; // @[ICache.scala:251:7] wire auto_master_out_d_valid_0 = auto_master_out_d_valid; // @[ICache.scala:251:7] wire [2:0] auto_master_out_d_bits_opcode_0 = auto_master_out_d_bits_opcode; // @[ICache.scala:251:7] wire [1:0] auto_master_out_d_bits_param_0 = auto_master_out_d_bits_param; // @[ICache.scala:251:7] wire [3:0] auto_master_out_d_bits_size_0 = auto_master_out_d_bits_size; // @[ICache.scala:251:7] wire auto_master_out_d_bits_sink_0 = auto_master_out_d_bits_sink; // @[ICache.scala:251:7] wire auto_master_out_d_bits_denied_0 = auto_master_out_d_bits_denied; // @[ICache.scala:251:7] wire [63:0] auto_master_out_d_bits_data_0 = auto_master_out_d_bits_data; // @[ICache.scala:251:7] wire auto_master_out_d_bits_corrupt_0 = auto_master_out_d_bits_corrupt; // @[ICache.scala:251:7] wire io_req_valid_0 = io_req_valid; // @[ICache.scala:251:7] wire [31:0] io_req_bits_addr_0 = io_req_bits_addr; // @[ICache.scala:251:7] wire [31:0] io_s1_paddr_0 = io_s1_paddr; // @[ICache.scala:251:7] wire [31:0] io_s2_vaddr_0 = io_s2_vaddr; // @[ICache.scala:251:7] wire io_s1_kill_0 = io_s1_kill; // @[ICache.scala:251:7] wire io_s2_kill_0 = io_s2_kill; // @[ICache.scala:251:7] wire io_s2_cacheable_0 = io_s2_cacheable; // @[ICache.scala:251:7] wire io_s2_prefetch_0 = io_s2_prefetch; // @[ICache.scala:251:7] wire io_invalidate_0 = io_invalidate; // @[ICache.scala:251:7] wire [5:0] _scratchpadHit_T_1 = 6'h0; // @[ICache.scala:327:40, :442:57] wire [5:0] _s1_scratchpad_hit_T = 6'h0; // @[ICache.scala:327:40, :442:57] wire [8:0] _mem_idx_T_2 = 9'h0; // @[ICache.scala:430:58, :565:31] wire [8:0] _mem_idx_T_8 = 9'h0; // @[ICache.scala:430:58, :565:31] wire [2:0] _masterNodeOut_a_bits_a_mask_sizeOH_T = 3'h6; // @[Misc.scala:202:34] wire [1:0] masterNodeOut_a_bits_a_mask_sizeOH_shiftAmount = 2'h2; // @[OneHot.scala:64:49] wire [3:0] _masterNodeOut_a_bits_a_mask_sizeOH_T_1 = 4'h4; // @[OneHot.scala:65:12] wire [2:0] masterNodeOut_a_bits_a_mask_sizeOH = 3'h5; // @[Misc.scala:202:81] wire [1:0] masterNodeOut_a_bits_a_mask_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] masterNodeOut_a_bits_a_mask_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] masterNodeOut_a_bits_a_mask_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] masterNodeOut_a_bits_a_mask_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [3:0] masterNodeOut_a_bits_a_mask_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] masterNodeOut_a_bits_a_mask_hi = 4'hF; // @[Misc.scala:222:10] wire [63:0] auto_master_out_a_bits_data = 64'h0; // @[ICache.scala:251:7] wire [63:0] masterNodeOut_a_bits_data = 64'h0; // @[MixedNode.scala:542:17] wire [63:0] masterNodeOut_a_bits_a_data = 64'h0; // @[Edges.scala:460:17] wire [7:0] auto_master_out_a_bits_mask = 8'hFF; // @[Misc.scala:222:10] wire [7:0] masterNodeOut_a_bits_mask = 8'hFF; // @[Misc.scala:222:10] wire [7:0] masterNodeOut_a_bits_a_mask = 8'hFF; // @[Misc.scala:222:10] wire [7:0] _masterNodeOut_a_bits_a_mask_T = 8'hFF; // @[Misc.scala:222:10] wire [3:0] auto_master_out_a_bits_size = 4'h6; // @[ICache.scala:251:7] wire [3:0] masterNodeOut_a_bits_size = 4'h6; // @[MixedNode.scala:542:17] wire [3:0] masterNodeOut_a_bits_a_size = 4'h6; // @[Edges.scala:460:17] wire [2:0] auto_master_out_a_bits_param = 3'h0; // @[ICache.scala:251:7] wire [2:0] masterNodeOut_a_bits_param = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] masterNodeOut_a_bits_a_param = 3'h0; // @[Edges.scala:460:17] wire [2:0] auto_master_out_a_bits_opcode = 3'h4; // @[ICache.scala:251:7] wire [2:0] masterNodeOut_a_bits_opcode = 3'h4; // @[MixedNode.scala:542:17] wire [2:0] masterNodeOut_a_bits_a_opcode = 3'h4; // @[Edges.scala:460:17] wire [2:0] _masterNodeOut_a_bits_a_mask_sizeOH_T_2 = 3'h4; // @[OneHot.scala:65:27] wire auto_master_out_a_bits_source = 1'h0; // @[ICache.scala:251:7] wire auto_master_out_a_bits_corrupt = 1'h0; // @[ICache.scala:251:7] wire auto_master_out_d_bits_source = 1'h0; // @[ICache.scala:251:7] wire io_resp_bits_replay = 1'h0; // @[ICache.scala:251:7] wire masterNodeOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire masterNodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire masterNodeOut_d_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire _s1_hit_T = 1'h0; // @[ICache.scala:361:46] wire s1_tag_disparity_0 = 1'h0; // @[ICache.scala:465:30] wire _scratchpadHit_T = 1'h0; // @[ICache.scala:316:43] wire _scratchpadHit_T_3 = 1'h0; // @[ICache.scala:503:58] wire _scratchpadHit_T_5 = 1'h0; // @[ICache.scala:302:66] wire _scratchpadHit_T_7 = 1'h0; // @[ICache.scala:507:39] wire _scratchpadHit_T_8 = 1'h0; // @[ICache.scala:498:10] wire scratchpadHit = 1'h0; // @[ICache.scala:497:49] wire _s1_tag_disparity_0_T = 1'h0; // @[ECC.scala:15:27] wire _s1_tag_disparity_0_T_1 = 1'h0; // @[ICache.scala:516:34] wire _s0_ren_T_4 = 1'h0; // @[ICache.scala:567:70] wire _wen_T_2 = 1'h0; // @[package.scala:163:13] wire _wen_T_4 = 1'h0; // @[ICache.scala:570:67] wire way = 1'h0; // @[ICache.scala:585:20] wire _s0_ren_T_8 = 1'h0; // @[ICache.scala:564:111] wire _s0_ren_T_9 = 1'h0; // @[ICache.scala:567:70] wire _wen_T_7 = 1'h0; // @[package.scala:163:13] wire _wen_T_9 = 1'h0; // @[ICache.scala:570:67] wire way_1 = 1'h0; // @[ICache.scala:585:20] wire s1s2_full_word_write = 1'h0; // @[ICache.scala:600:41] wire s1_dont_read = 1'h0; // @[ICache.scala:601:36] wire _s2_tag_hit_WIRE_0 = 1'h0; // @[ICache.scala:605:60] wire s2_tag_disparity = 1'h0; // @[ICache.scala:614:72] wire _s2_disparity_T = 1'h0; // @[ECC.scala:15:27] wire s2_disparity = 1'h0; // @[ICache.scala:619:39] wire _s1_scratchpad_hit_T_2 = 1'h0; // @[ICache.scala:302:66] wire s1_scratchpad_hit = 1'h0; // @[ICache.scala:621:30] wire _s2_report_uncorrectable_error_T = 1'h0; // @[ICache.scala:632:57] wire _s2_report_uncorrectable_error_T_2 = 1'h0; // @[ICache.scala:632:121] wire s2_report_uncorrectable_error = 1'h0; // @[ICache.scala:632:90] wire masterNodeOut_a_bits_a_source = 1'h0; // @[Edges.scala:460:17] wire masterNodeOut_a_bits_a_corrupt = 1'h0; // @[Edges.scala:460:17] wire masterNodeOut_a_bits_a_mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _masterNodeOut_a_bits_a_mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _masterNodeOut_a_bits_a_mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire _masterNodeOut_a_bits_a_mask_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _masterNodeOut_a_bits_a_mask_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire auto_master_out_d_ready = 1'h1; // @[ICache.scala:251:7] wire io_clock_enabled = 1'h1; // @[ICache.scala:251:7] wire masterNodeOut_d_ready = 1'h1; // @[MixedNode.scala:542:17] wire _refill_fire_T_1 = 1'h1; // @[ICache.scala:374:38] wire _masterNodeOut_d_ready_T = 1'h1; // @[ICache.scala:401:21] wire _scratchpadHit_T_2 = 1'h1; // @[ICache.scala:503:91] wire _scratchpadHit_T_6 = 1'h1; // @[ICache.scala:507:69] wire _s1_vb_T_3 = 1'h1; // @[ICache.scala:508:74] wire _s0_ren_T_3 = 1'h1; // @[ICache.scala:564:111] wire _s2_report_uncorrectable_error_T_1 = 1'h1; // @[ICache.scala:632:124] wire _masterNodeOut_a_bits_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _masterNodeOut_a_bits_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _masterNodeOut_a_bits_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _masterNodeOut_a_bits_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _masterNodeOut_a_bits_legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _masterNodeOut_a_bits_legal_T_11 = 1'h1; // @[Parameters.scala:92:38] wire _masterNodeOut_a_bits_legal_T_12 = 1'h1; // @[Parameters.scala:92:33] wire _masterNodeOut_a_bits_legal_T_13 = 1'h1; // @[Parameters.scala:684:29] wire masterNodeOut_a_bits_a_mask_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21] wire masterNodeOut_a_bits_a_mask_sub_sub_size = 1'h1; // @[Misc.scala:209:26] wire masterNodeOut_a_bits_a_mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_sub_2_1 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_sub_3_1 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_size = 1'h1; // @[Misc.scala:209:26] wire masterNodeOut_a_bits_a_mask_acc = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_acc_1 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_acc_2 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_acc_3 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_acc_4 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_acc_5 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_acc_6 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_bits_a_mask_acc_7 = 1'h1; // @[Misc.scala:215:29] wire masterNodeOut_a_ready = auto_master_out_a_ready_0; // @[ICache.scala:251:7] wire masterNodeOut_a_valid; // @[MixedNode.scala:542:17] wire [31:0] masterNodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire masterNodeOut_d_valid = auto_master_out_d_valid_0; // @[ICache.scala:251:7] wire [2:0] masterNodeOut_d_bits_opcode = auto_master_out_d_bits_opcode_0; // @[ICache.scala:251:7] wire [1:0] masterNodeOut_d_bits_param = auto_master_out_d_bits_param_0; // @[ICache.scala:251:7] wire [3:0] masterNodeOut_d_bits_size = auto_master_out_d_bits_size_0; // @[ICache.scala:251:7] wire masterNodeOut_d_bits_sink = auto_master_out_d_bits_sink_0; // @[ICache.scala:251:7] wire masterNodeOut_d_bits_denied = auto_master_out_d_bits_denied_0; // @[ICache.scala:251:7] wire [63:0] masterNodeOut_d_bits_data = auto_master_out_d_bits_data_0; // @[ICache.scala:251:7] wire masterNodeOut_d_bits_corrupt = auto_master_out_d_bits_corrupt_0; // @[ICache.scala:251:7] wire _io_req_ready_T_2; // @[ICache.scala:394:19] wire [31:0] _s2_scratchpad_word_addr_T = io_s2_vaddr_0; // @[ICache.scala:251:7, :611:52] wire _io_resp_valid_T; // @[ICache.scala:659:33] wire _io_errors_bus_valid_T_2; // @[ICache.scala:441:40] wire invalidate = io_invalidate_0; // @[ICache.scala:251:7, :456:31] wire [31:0] _io_errors_bus_bits_T_1; // @[ICache.scala:442:57] wire refill_fire; // @[ICache.scala:374:35] wire _io_keep_clock_enabled_T_4; // @[ICache.scala:837:55] wire [31:0] auto_master_out_a_bits_address_0; // @[ICache.scala:251:7] wire auto_master_out_a_valid_0; // @[ICache.scala:251:7] wire io_req_ready; // @[ICache.scala:251:7] wire [31:0] io_resp_bits_data_0; // @[ICache.scala:251:7] wire io_resp_bits_ae_0; // @[ICache.scala:251:7] wire io_resp_valid_0; // @[ICache.scala:251:7] wire io_errors_bus_valid_0; // @[ICache.scala:251:7] wire [31:0] io_errors_bus_bits_0; // @[ICache.scala:251:7] wire io_perf_acquire_0; // @[ICache.scala:251:7] wire io_keep_clock_enabled; // @[ICache.scala:251:7] wire s2_request_refill; // @[ICache.scala:385:35] assign auto_master_out_a_valid_0 = masterNodeOut_a_valid; // @[ICache.scala:251:7] wire [31:0] masterNodeOut_a_bits_a_address; // @[Edges.scala:460:17] assign auto_master_out_a_bits_address_0 = masterNodeOut_a_bits_address; // @[ICache.scala:251:7] wire _refill_one_beat_T = masterNodeOut_d_valid; // @[Decoupled.scala:51:35] wire _io_errors_bus_valid_T = masterNodeOut_d_valid; // @[Decoupled.scala:51:35] wire s0_valid = io_req_ready & io_req_valid_0; // @[Decoupled.scala:51:35] reg s1_valid; // @[ICache.scala:341:25] wire s1_clk_en = s1_valid; // @[ICache.scala:341:25, :604:28] wire _io_keep_clock_enabled_T = s1_valid; // @[ICache.scala:341:25, :836:117] reg [31:0] s1_vaddr; // @[ICache.scala:343:27] wire _s1_tag_hit_0_T; // @[ICache.scala:519:31] wire s1_tag_hit_0; // @[ICache.scala:345:24] wire s1_hit = s1_tag_hit_0; // @[ICache.scala:345:24, :361:40] wire _s2_tag_hit_T_0 = s1_tag_hit_0; // @[ICache.scala:345:24, :605:33] wire _s2_valid_T = ~io_s1_kill_0; // @[ICache.scala:251:7, :363:38] wire _s2_valid_T_1 = s1_valid & _s2_valid_T; // @[ICache.scala:341:25, :363:{35,38}] reg s2_valid; // @[ICache.scala:363:25] wire _s2_report_uncorrectable_error_T_3 = s2_valid; // @[ICache.scala:363:25, :632:103] reg s2_hit; // @[ICache.scala:364:23] reg invalidated; // @[ICache.scala:367:24] reg refill_valid; // @[ICache.scala:368:29] wire _refill_fire_T = masterNodeOut_a_ready & masterNodeOut_a_valid; // @[Decoupled.scala:51:35] assign refill_fire = _refill_fire_T; // @[Decoupled.scala:51:35] assign io_perf_acquire_0 = refill_fire; // @[ICache.scala:251:7, :374:35] wire _s2_miss_T = ~s2_hit; // @[ICache.scala:364:23, :378:29] wire _s2_miss_T_1 = s2_valid & _s2_miss_T; // @[ICache.scala:363:25, :378:{26,29}] wire _s2_miss_T_2 = ~io_s2_kill_0; // @[ICache.scala:251:7, :378:40] wire s2_miss = _s2_miss_T_1 & _s2_miss_T_2; // @[ICache.scala:378:{26,37,40}] wire _s1_can_request_refill_T = s2_miss \| refill_valid; // @[ICache.scala:368:29, :378:37, :380:41] wire s1_can_request_refill = ~_s1_can_request_refill_T; // @[ICache.scala:380:{31,41}] reg s2_request_refill_REG; // @[ICache.scala:385:45] assign s2_request_refill = s2_miss & s2_request_refill_REG; // @[ICache.scala:378:37, :385:{35,45}] assign masterNodeOut_a_valid = s2_request_refill; // @[ICache.scala:385:35] wire _GEN = s1_valid & s1_can_request_refill; // @[ICache.scala:341:25, :380:31, :386:54] wire _refill_paddr_T; // @[ICache.scala:386:54] assign _refill_paddr_T = _GEN; // @[ICache.scala:386:54] wire _refill_vaddr_T; // @[ICache.scala:387:51] assign _refill_vaddr_T = _GEN; // @[ICache.scala:386:54, :387:51] reg [31:0] refill_paddr; // @[ICache.scala:386:31] reg [31:0] refill_vaddr; // @[ICache.scala:387:31] wire [19:0] refill_tag = refill_paddr[31:12]; // @[ICache.scala:386:31, :388:33] wire [5:0] refill_idx = refill_paddr[11:6]; // @[ICache.scala:386:31, :859:21] wire refill_one_beat_opdata = masterNodeOut_d_bits_opcode[0]; // @[Edges.scala:106:36] wire r_beats1_opdata = masterNodeOut_d_bits_opcode[0]; // @[Edges.scala:106:36] wire refill_one_beat = _refill_one_beat_T & refill_one_beat_opdata; // @[Decoupled.scala:51:35] wire _io_req_ready_T = refill_one_beat; // @[ICache.scala:391:39, :394:37] wire _io_req_ready_T_1 = _io_req_ready_T; // @[ICache.scala:394:{37,54}] assign _io_req_ready_T_2 = ~_io_req_ready_T_1; // @[ICache.scala:394:{19,54}] assign io_req_ready = _io_req_ready_T_2; // @[ICache.scala:251:7, :394:19] wire [26:0] _r_beats1_decode_T = 27'hFFF << masterNodeOut_d_bits_size; // @[package.scala:243:71] wire [11:0] _r_beats1_decode_T_1 = _r_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _r_beats1_decode_T_2 = ~_r_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] r_beats1_decode = _r_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire [8:0] r_beats1 = r_beats1_opdata ? r_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] r_counter; // @[Edges.scala:229:27] wire [9:0] _r_counter1_T = {1'h0, r_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] r_counter1 = _r_counter1_T[8:0]; // @[Edges.scala:230:28] wire r_1 = r_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _r_last_T = r_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _r_last_T_1 = r_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire r_2 = _r_last_T \| _r_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_done = r_2 & masterNodeOut_d_valid; // @[Edges.scala:232:33, :233:22] wire [8:0] _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] refill_cnt = r_beats1 & _r_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _r_counter_T = r_1 ? r_beats1 : r_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire refill_done = refill_one_beat & d_done; // @[Edges.scala:233:22] wire [5:0] _tag_rdata_WIRE; // @[ICache.scala:426:33] wire _tag_rdata_T_2; // @[ICache.scala:426:83] wire [5:0] _tag_rdata_T = io_req_bits_addr_0[11:6]; // @[ICache.scala:251:7, :426:42] assign _tag_rdata_WIRE = _tag_rdata_T; // @[ICache.scala:426:{33,42}] wire _tag_rdata_T_1 = ~refill_done; // @[ICache.scala:399:37, :426:70] assign _tag_rdata_T_2 = _tag_rdata_T_1 & s0_valid; // @[Decoupled.scala:51:35] reg accruedRefillError; // @[ICache.scala:428:31] wire _refillError_T = \|refill_cnt; // @[Edges.scala:234:25] wire _refillError_T_1 = _refillError_T & accruedRefillError; // @[ICache.scala:428:31, :430:{58,64}] wire refillError = masterNodeOut_d_bits_corrupt \| _refillError_T_1; // @[ICache.scala:430:{43,64}] wire [20:0] enc_tag = {refillError, refill_tag}; // @[ICache.scala:388:33, :430:43, :435:34] wire _io_errors_bus_valid_T_1 = masterNodeOut_d_bits_denied \| masterNodeOut_d_bits_corrupt; // @[ICache.scala:441:65] assign _io_errors_bus_valid_T_2 = _io_errors_bus_valid_T & _io_errors_bus_valid_T_1; // @[Decoupled.scala:51:35] assign io_errors_bus_valid_0 = _io_errors_bus_valid_T_2; // @[ICache.scala:251:7, :441:40] wire [25:0] _io_errors_bus_bits_T = refill_paddr[31:6]; // @[ICache.scala:386:31, :442:40] wire [25:0] _masterNodeOut_a_bits_T = refill_paddr[31:6]; // @[ICache.scala:386:31, :442:40, :769:47] assign _io_errors_bus_bits_T_1 = {_io_errors_bus_bits_T, 6'h0}; // @[ICache.scala:442:{40,57}] assign io_errors_bus_bits_0 = _io_errors_bus_bits_T_1; // @[ICache.scala:251:7, :442:57] reg [63:0] vb_array; // @[ICache.scala:448:25] wire [6:0] _vb_array_T = {1'h0, refill_idx}; // @[ICache.scala:452:36, :859:21] wire _vb_array_T_1 = ~invalidated; // @[ICache.scala:367:24, :452:75] wire _vb_array_T_2 = refill_done & _vb_array_T_1; // @[ICache.scala:399:37, :452:{72,75}] wire [127:0] _vb_array_T_3 = 128'h1 << _vb_array_T; // @[ICache.scala:452:{32,36}] wire [127:0] _vb_array_T_4 = {64'h0, vb_array} \| _vb_array_T_3; // @[ICache.scala:448:25, :452:32] wire [63:0] _vb_array_T_5 = ~vb_array; // @[ICache.scala:448:25, :452:32] wire [127:0] _vb_array_T_6 = {64'h0, _vb_array_T_5} \| _vb_array_T_3; // @[ICache.scala:452:32] wire [127:0] _vb_array_T_7 = ~_vb_array_T_6; // @[ICache.scala:452:32] wire [127:0] _vb_array_T_8 = _vb_array_T_2 ? _vb_array_T_4 : _vb_array_T_7; // @[ICache.scala:452:{32,72}] wire _s1_tl_error_0_T_1; // @[ICache.scala:518:32] wire s1_tl_error_0; // @[ICache.scala:469:25] wire _s2_tl_error_T = s1_tl_error_0; // @[ICache.scala:469:25, :615:50] wire [31:0] s1_dout_0; // @[ICache.scala:473:21] wire [5:0] s1_idx = io_s1_paddr_0[11:6]; // @[ICache.scala:251:7, :859:21] wire [5:0] _scratchpadHit_T_4 = io_s1_paddr_0[11:6]; // @[ICache.scala:251:7, :302:90, :859:21] wire [5:0] _s1_scratchpad_hit_T_1 = io_s1_paddr_0[11:6]; // @[ICache.scala:251:7, :302:90, :859:21] wire [19:0] s1_tag = io_s1_paddr_0[31:12]; // @[ICache.scala:251:7, :493:30] wire [6:0] _s1_vb_T = {1'h0, s1_idx}; // @[ICache.scala:508:29, :859:21] wire [63:0] _s1_vb_T_1 = vb_array >> _s1_vb_T; // @[ICache.scala:448:25, :508:{25,29}] wire _s1_vb_T_2 = _s1_vb_T_1[0]; // @[ICache.scala:508:25] wire s1_vb = _s1_vb_T_2; // @[ICache.scala:508:{25,71}] wire tl_error = _rockettile_icache_tag_array_0_RW0_rdata[20]; // @[package.scala:163:13] wire _s1_tl_error_0_T = tl_error; // @[package.scala:163:13] wire [19:0] tag = _rockettile_icache_tag_array_0_RW0_rdata[19:0]; // @[package.scala:163:13] wire _tagMatch_T = tag == s1_tag; // @[package.scala:163:13] wire tagMatch = s1_vb & _tagMatch_T; // @[ICache.scala:508:71, :514:{26,33}] assign _s1_tag_hit_0_T = tagMatch; // @[ICache.scala:514:26, :519:31] assign _s1_tl_error_0_T_1 = tagMatch & _s1_tl_error_0_T; // @[ICache.scala:514:26, :518:{32,44}] assign s1_tl_error_0 = _s1_tl_error_0_T_1; // @[ICache.scala:469:25, :518:32] assign s1_tag_hit_0 = _s1_tag_hit_0_T; // @[ICache.scala:345:24, :519:31] wire wen; // @[ICache.scala:570:49] wire [8:0] mem_idx; // @[ICache.scala:574:10] wire [8:0] _dout_WIRE; // @[ICache.scala:590:31] wire _dout_T_1; // @[ICache.scala:590:46] wire wen_1; // @[ICache.scala:570:49] wire [8:0] mem_idx_1; // @[ICache.scala:574:10] wire [8:0] _dout_WIRE_1; // @[ICache.scala:590:31] wire _dout_T_3; // @[ICache.scala:590:46] wire _s0_ren_T = io_req_bits_addr_0[2]; // @[package.scala:163:13] wire _s0_ren_T_5 = io_req_bits_addr_0[2]; // @[package.scala:163:13] wire _s0_ren_T_1 = ~_s0_ren_T; // @[package.scala:163:13] wire _s0_ren_T_2 = s0_valid & _s0_ren_T_1; // @[Decoupled.scala:51:35] wire s0_ren = _s0_ren_T_2; // @[ICache.scala:567:{28,52}] wire _wen_T = ~invalidated; // @[ICache.scala:367:24, :452:75, :570:35] wire _wen_T_1 = refill_one_beat & _wen_T; // @[ICache.scala:391:39, :570:{32,35}] assign wen = _wen_T_1; // @[ICache.scala:570:{32,49}] wire _wen_T_3 = ~_wen_T_2; // @[package.scala:163:13] wire [8:0] _GEN_0 = {refill_idx, 3'h0}; // @[ICache.scala:574:40, :859:21] wire [8:0] _mem_idx_T; // @[ICache.scala:574:40] assign _mem_idx_T = _GEN_0; // @[ICache.scala:574:40] wire [8:0] _mem_idx_T_6; // @[ICache.scala:574:40] assign _mem_idx_T_6 = _GEN_0; // @[ICache.scala:574:40] wire [8:0] _mem_idx_T_1 = _mem_idx_T \| refill_cnt; // @[Edges.scala:234:25] wire [8:0] _mem_idx_T_3 = io_req_bits_addr_0[11:3]; // @[ICache.scala:251:7, :565:31] wire [8:0] _mem_idx_T_9 = io_req_bits_addr_0[11:3]; // @[ICache.scala:251:7, :565:31] wire [8:0] _mem_idx_T_4 = _mem_idx_T_3; // @[ICache.scala:565:31, :578:22] wire [8:0] _mem_idx_T_5 = _mem_idx_T_4; // @[ICache.scala:576:22, :578:22] assign mem_idx = refill_one_beat ? _mem_idx_T_1 : _mem_idx_T_5; // @[ICache.scala:391:39, :574:{10,67}, :576:22] assign _dout_WIRE = mem_idx; // @[ICache.scala:574:10, :590:31] wire [31:0] _data_T = masterNodeOut_d_bits_data[31:0]; // @[ICache.scala:583:71] wire [31:0] data = _data_T; // @[ICache.scala:583:{21,71}] wire _dout_T = ~wen; // @[ICache.scala:570:49, :590:41] assign _dout_T_1 = _dout_T & s0_ren; // @[ICache.scala:567:52, :590:{41,46}] wire _s0_ren_T_6 = _s0_ren_T_5; // @[package.scala:163:13] wire _s0_ren_T_7 = s0_valid & _s0_ren_T_6; // @[Decoupled.scala:51:35] wire s0_ren_1 = _s0_ren_T_7; // @[ICache.scala:567:{28,52}] wire _wen_T_5 = ~invalidated; // @[ICache.scala:367:24, :452:75, :570:35] wire _wen_T_6 = refill_one_beat & _wen_T_5; // @[ICache.scala:391:39, :570:{32,35}] assign wen_1 = _wen_T_6; // @[ICache.scala:570:{32,49}] wire _wen_T_8 = _wen_T_7; // @[package.scala:163:13] wire [8:0] _mem_idx_T_7 = _mem_idx_T_6 \| refill_cnt; // @[Edges.scala:234:25] wire [8:0] _mem_idx_T_10 = _mem_idx_T_9; // @[ICache.scala:565:31, :578:22] wire [8:0] _mem_idx_T_11 = _mem_idx_T_10; // @[ICache.scala:576:22, :578:22] assign mem_idx_1 = refill_one_beat ? _mem_idx_T_7 : _mem_idx_T_11; // @[ICache.scala:391:39, :574:{10,67}, :576:22] assign _dout_WIRE_1 = mem_idx_1; // @[ICache.scala:574:10, :590:31] wire [31:0] _data_T_1 = masterNodeOut_d_bits_data[63:32]; // @[ICache.scala:583:71] wire [31:0] data_1 = _data_T_1; // @[ICache.scala:583:{21,71}] wire _dout_T_2 = ~wen_1; // @[ICache.scala:570:49, :590:41] assign _dout_T_3 = _dout_T_2 & s0_ren_1; // @[ICache.scala:567:52, :590:{41,46}] assign s1_dout_0 = io_s1_paddr_0[2] ? _rockettile_icache_data_arrays_1_0_RW0_rdata : _rockettile_icache_data_arrays_0_0_RW0_rdata; // @[package.scala:163:13] reg s2_tag_hit_0; // @[ICache.scala:605:29] wire [9:0] _s2_scratchpad_word_addr_T_1 = _s2_scratchpad_word_addr_T[11:2]; // @[ICache.scala:611:{52,96}] wire [10:0] s2_scratchpad_word_addr_hi = {1'h0, _s2_scratchpad_word_addr_T_1}; // @[ICache.scala:611:{36,96}] wire [12:0] s2_scratchpad_word_addr = {s2_scratchpad_word_addr_hi, 2'h0}; // @[ICache.scala:611:36] reg [31:0] s2_dout_0; // @[ICache.scala:612:26] assign io_resp_bits_data_0 = s2_dout_0; // @[ICache.scala:251:7, :612:26] reg s2_tl_error; // @[ICache.scala:615:30] assign io_resp_bits_ae_0 = s2_tl_error; // @[ICache.scala:251:7, :615:30] assign _io_resp_valid_T = s2_valid & s2_hit; // @[ICache.scala:363:25, :364:23, :659:33] assign io_resp_valid_0 = _io_resp_valid_T; // @[ICache.scala:251:7, :659:33] wire [31:0] _masterNodeOut_a_bits_T_1 = {_masterNodeOut_a_bits_T, 6'h0}; // @[ICache.scala:442:57, :769:{47,64}] wire [31:0] _masterNodeOut_a_bits_legal_T_14 = _masterNodeOut_a_bits_T_1; // @[ICache.scala:769:64] assign masterNodeOut_a_bits_a_address = _masterNodeOut_a_bits_T_1; // @[Edges.scala:460:17] wire [31:0] _masterNodeOut_a_bits_legal_T_4 = {_masterNodeOut_a_bits_T_1[31:14], _masterNodeOut_a_bits_T_1[13:0] ^ 14'h3000}; // @[ICache.scala:769:64] wire [32:0] _masterNodeOut_a_bits_legal_T_5 = {1'h0, _masterNodeOut_a_bits_legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [32:0] _masterNodeOut_a_bits_legal_T_6 = _masterNodeOut_a_bits_legal_T_5 & 33'h8A113000; // @[Parameters.scala:137:{41,46}] wire [32:0] _masterNodeOut_a_bits_legal_T_7 = _masterNodeOut_a_bits_legal_T_6; // @[Parameters.scala:137:46] wire _masterNodeOut_a_bits_legal_T_8 = _masterNodeOut_a_bits_legal_T_7 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _masterNodeOut_a_bits_legal_T_9 = _masterNodeOut_a_bits_legal_T_8; // @[Parameters.scala:684:54] wire _masterNodeOut_a_bits_legal_T_50 = _masterNodeOut_a_bits_legal_T_9; // @[Parameters.scala:684:54, :686:26] wire [32:0] _masterNodeOut_a_bits_legal_T_15 = {1'h0, _masterNodeOut_a_bits_legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [32:0] _masterNodeOut_a_bits_legal_T_16 = _masterNodeOut_a_bits_legal_T_15 & 33'h8A112000; // @[Parameters.scala:137:{41,46}] wire [32:0] _masterNodeOut_a_bits_legal_T_17 = _masterNodeOut_a_bits_legal_T_16; // @[Parameters.scala:137:46] wire _masterNodeOut_a_bits_legal_T_18 = _masterNodeOut_a_bits_legal_T_17 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _masterNodeOut_a_bits_legal_T_19 = {_masterNodeOut_a_bits_T_1[31:17], _masterNodeOut_a_bits_T_1[16:0] ^ 17'h10000}; // @[ICache.scala:769:64] wire [32:0] _masterNodeOut_a_bits_legal_T_20 = {1'h0, _masterNodeOut_a_bits_legal_T_19}; // @[Parameters.scala:137:{31,41}] wire [32:0] _masterNodeOut_a_bits_legal_T_21 = _masterNodeOut_a_bits_legal_T_20 & 33'h8A110000; // @[Parameters.scala:137:{41,46}] wire [32:0] _masterNodeOut_a_bits_legal_T_22 = _masterNodeOut_a_bits_legal_T_21; // @[Parameters.scala:137:46] wire _masterNodeOut_a_bits_legal_T_23 = _masterNodeOut_a_bits_legal_T_22 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _masterNodeOut_a_bits_legal_T_24 = {_masterNodeOut_a_bits_T_1[31:21], _masterNodeOut_a_bits_T_1[20:0] ^ 21'h100000}; // @[ICache.scala:769:64] wire [32:0] _masterNodeOut_a_bits_legal_T_25 = {1'h0, _masterNodeOut_a_bits_legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [32:0] _masterNodeOut_a_bits_legal_T_26 = _masterNodeOut_a_bits_legal_T_25 & 33'h8A103000; // @[Parameters.scala:137:{41,46}] wire [32:0] _masterNodeOut_a_bits_legal_T_27 = _masterNodeOut_a_bits_legal_T_26; // @[Parameters.scala:137:46] wire _masterNodeOut_a_bits_legal_T_28 = _masterNodeOut_a_bits_legal_T_27 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _masterNodeOut_a_bits_legal_T_29 = {_masterNodeOut_a_bits_T_1[31:26], _masterNodeOut_a_bits_T_1[25:0] ^ 26'h2000000}; // @[ICache.scala:769:64] wire [32:0] _masterNodeOut_a_bits_legal_T_30 = {1'h0, _masterNodeOut_a_bits_legal_T_29}; // @[Parameters.scala:137:{31,41}] wire [32:0] _masterNodeOut_a_bits_legal_T_31 = _masterNodeOut_a_bits_legal_T_30 & 33'h8A110000; // @[Parameters.scala:137:{41,46}] wire [32:0] _masterNodeOut_a_bits_legal_T_32 = _masterNodeOut_a_bits_legal_T_31; // @[Parameters.scala:137:46] wire _masterNodeOut_a_bits_legal_T_33 = _masterNodeOut_a_bits_legal_T_32 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _masterNodeOut_a_bits_legal_T_34 = {_masterNodeOut_a_bits_T_1[31:28], _masterNodeOut_a_bits_T_1[27:0] ^ 28'h8000000}; // @[ICache.scala:769:64] wire [32:0] _masterNodeOut_a_bits_legal_T_35 = {1'h0, _masterNodeOut_a_bits_legal_T_34}; // @[Parameters.scala:137:{31,41}] wire [32:0] _masterNodeOut_a_bits_legal_T_36 = _masterNodeOut_a_bits_legal_T_35 & 33'h88000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _masterNodeOut_a_bits_legal_T_37 = _masterNodeOut_a_bits_legal_T_36; // @[Parameters.scala:137:46] wire _masterNodeOut_a_bits_legal_T_38 = _masterNodeOut_a_bits_legal_T_37 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _masterNodeOut_a_bits_legal_T_39 = _masterNodeOut_a_bits_T_1 ^ 32'h80000000; // @[ICache.scala:769:64] wire [32:0] _masterNodeOut_a_bits_legal_T_40 = {1'h0, _masterNodeOut_a_bits_legal_T_39}; // @[Parameters.scala:137:{31,41}] wire [32:0] _masterNodeOut_a_bits_legal_T_41 = _masterNodeOut_a_bits_legal_T_40 & 33'h8A110000; // @[Parameters.scala:137:{41,46}] wire [32:0] _masterNodeOut_a_bits_legal_T_42 = _masterNodeOut_a_bits_legal_T_41; // @[Parameters.scala:137:46] wire _masterNodeOut_a_bits_legal_T_43 = _masterNodeOut_a_bits_legal_T_42 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _masterNodeOut_a_bits_legal_T_44 = _masterNodeOut_a_bits_legal_T_18 \| _masterNodeOut_a_bits_legal_T_23; // @[Parameters.scala:685:42] wire _masterNodeOut_a_bits_legal_T_45 = _masterNodeOut_a_bits_legal_T_44 \| _masterNodeOut_a_bits_legal_T_28; // @[Parameters.scala:685:42] wire _masterNodeOut_a_bits_legal_T_46 = _masterNodeOut_a_bits_legal_T_45 \| _masterNodeOut_a_bits_legal_T_33; // @[Parameters.scala:685:42] wire _masterNodeOut_a_bits_legal_T_47 = _masterNodeOut_a_bits_legal_T_46 \| _masterNodeOut_a_bits_legal_T_38; // @[Parameters.scala:685:42] wire _masterNodeOut_a_bits_legal_T_48 = _masterNodeOut_a_bits_legal_T_47 \| _masterNodeOut_a_bits_legal_T_43; // @[Parameters.scala:685:42] wire _masterNodeOut_a_bits_legal_T_49 = _masterNodeOut_a_bits_legal_T_48; // @[Parameters.scala:684:54, :685:42] wire masterNodeOut_a_bits_legal = _masterNodeOut_a_bits_legal_T_50 \| _masterNodeOut_a_bits_legal_T_49; // @[Parameters.scala:684:54, :686:26] assign masterNodeOut_a_bits_address = masterNodeOut_a_bits_a_address; // @[Edges.scala:460:17] wire masterNodeOut_a_bits_a_mask_sub_sub_bit = _masterNodeOut_a_bits_T_1[2]; // @[Misc.scala:210:26] wire masterNodeOut_a_bits_a_mask_sub_sub_1_2 = masterNodeOut_a_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire masterNodeOut_a_bits_a_mask_sub_sub_nbit = ~masterNodeOut_a_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire masterNodeOut_a_bits_a_mask_sub_sub_0_2 = masterNodeOut_a_bits_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _masterNodeOut_a_bits_a_mask_sub_sub_acc_T = masterNodeOut_a_bits_a_mask_sub_sub_0_2; // @[Misc.scala:214:27, :215:38] wire _masterNodeOut_a_bits_a_mask_sub_sub_acc_T_1 = masterNodeOut_a_bits_a_mask_sub_sub_1_2; // @[Misc.scala:214:27, :215:38] wire masterNodeOut_a_bits_a_mask_sub_bit = _masterNodeOut_a_bits_T_1[1]; // @[Misc.scala:210:26] wire masterNodeOut_a_bits_a_mask_sub_nbit = ~masterNodeOut_a_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire masterNodeOut_a_bits_a_mask_sub_0_2 = masterNodeOut_a_bits_a_mask_sub_sub_0_2 & masterNodeOut_a_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire masterNodeOut_a_bits_a_mask_sub_1_2 = masterNodeOut_a_bits_a_mask_sub_sub_0_2 & masterNodeOut_a_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire masterNodeOut_a_bits_a_mask_sub_2_2 = masterNodeOut_a_bits_a_mask_sub_sub_1_2 & masterNodeOut_a_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire masterNodeOut_a_bits_a_mask_sub_3_2 = masterNodeOut_a_bits_a_mask_sub_sub_1_2 & masterNodeOut_a_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire masterNodeOut_a_bits_a_mask_bit = _masterNodeOut_a_bits_T_1[0]; // @[Misc.scala:210:26] wire masterNodeOut_a_bits_a_mask_nbit = ~masterNodeOut_a_bits_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire masterNodeOut_a_bits_a_mask_eq = masterNodeOut_a_bits_a_mask_sub_0_2 & masterNodeOut_a_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _masterNodeOut_a_bits_a_mask_acc_T = masterNodeOut_a_bits_a_mask_eq; // @[Misc.scala:214:27, :215:38] wire masterNodeOut_a_bits_a_mask_eq_1 = masterNodeOut_a_bits_a_mask_sub_0_2 & masterNodeOut_a_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _masterNodeOut_a_bits_a_mask_acc_T_1 = masterNodeOut_a_bits_a_mask_eq_1; // @[Misc.scala:214:27, :215:38] wire masterNodeOut_a_bits_a_mask_eq_2 = masterNodeOut_a_bits_a_mask_sub_1_2 & masterNodeOut_a_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _masterNodeOut_a_bits_a_mask_acc_T_2 = masterNodeOut_a_bits_a_mask_eq_2; // @[Misc.scala:214:27, :215:38] wire masterNodeOut_a_bits_a_mask_eq_3 = masterNodeOut_a_bits_a_mask_sub_1_2 & masterNodeOut_a_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _masterNodeOut_a_bits_a_mask_acc_T_3 = masterNodeOut_a_bits_a_mask_eq_3; // @[Misc.scala:214:27, :215:38] wire masterNodeOut_a_bits_a_mask_eq_4 = masterNodeOut_a_bits_a_mask_sub_2_2 & masterNodeOut_a_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _masterNodeOut_a_bits_a_mask_acc_T_4 = masterNodeOut_a_bits_a_mask_eq_4; // @[Misc.scala:214:27, :215:38] wire masterNodeOut_a_bits_a_mask_eq_5 = masterNodeOut_a_bits_a_mask_sub_2_2 & masterNodeOut_a_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _masterNodeOut_a_bits_a_mask_acc_T_5 = masterNodeOut_a_bits_a_mask_eq_5; // @[Misc.scala:214:27, :215:38] wire masterNodeOut_a_bits_a_mask_eq_6 = masterNodeOut_a_bits_a_mask_sub_3_2 & masterNodeOut_a_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _masterNodeOut_a_bits_a_mask_acc_T_6 = masterNodeOut_a_bits_a_mask_eq_6; // @[Misc.scala:214:27, :215:38] wire masterNodeOut_a_bits_a_mask_eq_7 = masterNodeOut_a_bits_a_mask_sub_3_2 & masterNodeOut_a_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _masterNodeOut_a_bits_a_mask_acc_T_7 = masterNodeOut_a_bits_a_mask_eq_7; // @[Misc.scala:214:27, :215:38] wire _io_keep_clock_enabled_T_1 = _io_keep_clock_enabled_T \| s2_valid; // @[ICache.scala:363:25, :836:117, :837:14] wire _io_keep_clock_enabled_T_2 = _io_keep_clock_enabled_T_1 \| refill_valid; // @[ICache.scala:368:29, :837:{14,26}] wire _io_keep_clock_enabled_T_3 = _io_keep_clock_enabled_T_2; // @[ICache.scala:837:{26,42}] assign _io_keep_clock_enabled_T_4 = _io_keep_clock_enabled_T_3; // @[ICache.scala:837:{42,55}] assign io_keep_clock_enabled = _io_keep_clock_enabled_T_4; // @[ICache.scala:251:7, :837:55] always @(posedge clock) begin // @[ICache.scala:251:7] if (reset) begin // @[ICache.scala:251:7] s1_valid <= 1'h0; // @[ICache.scala:341:25] s2_valid <= 1'h0; // @[ICache.scala:363:25] refill_valid <= 1'h0; // @[ICache.scala:368:29] r_counter <= 9'h0; // @[Edges.scala:229:27] vb_array <= 64'h0; // @[ICache.scala:448:25] end else begin // @[ICache.scala:251:7] s1_valid <= s0_valid; // @[Decoupled.scala:51:35] s2_valid <= _s2_valid_T_1; // @[ICache.scala:363:{25,35}] refill_valid <= ~refill_done & (refill_fire \| refill_valid); // @[ICache.scala:368:29, :374:35, :399:37, :830:{22,37}, :831:{22,37}] if (masterNodeOut_d_valid) // @[MixedNode.scala:542:17] r_counter <= _r_counter_T; // @[Edges.scala:229:27, :236:21] if (invalidate) // @[ICache.scala:456:31] vb_array <= 64'h0; // @[ICache.scala:448:25] else if (refill_one_beat) // @[ICache.scala:391:39] vb_array <= _vb_array_T_8[63:0]; // @[ICache.scala:448:25, :452:{14,32}] end if (s0_valid) // @[Decoupled.scala:51:35] s1_vaddr <= io_req_bits_addr_0; // @[ICache.scala:251:7, :343:27] s2_hit <= s1_hit; // @[ICache.scala:361:40, :364:23] invalidated <= refill_valid & (invalidate \| invalidated); // @[ICache.scala:367:24, :368:29, :456:31, :457:21, :459:17, :829:{24,38}] s2_request_refill_REG <= s1_can_request_refill; // @[ICache.scala:380:31, :385:45] if (_refill_paddr_T) // @[ICache.scala:386:54] refill_paddr <= io_s1_paddr_0; // @[ICache.scala:251:7, :386:31] if (_refill_vaddr_T) // @[ICache.scala:387:51] refill_vaddr <= s1_vaddr; // @[ICache.scala:343:27, :387:31] if (refill_one_beat) // @[ICache.scala:391:39] accruedRefillError <= refillError; // @[ICache.scala:428:31, :430:43] if (s1_clk_en) begin // @[ICache.scala:604:28] s2_tag_hit_0 <= _s2_tag_hit_T_0; // @[ICache.scala:605:{29,33}] s2_dout_0 <= s1_dout_0; // @[ICache.scala:473:21, :612:26] s2_tl_error <= _s2_tl_error_T; // @[ICache.scala:615:{30,50}] end always @(posedge) rockettile_icache_tag_array_0 rockettile_icache_tag_array_0 ( // @[DescribedSRAM.scala:17:26] .RW0_addr (refill_done ? refill_idx : _tag_rdata_WIRE), // @[DescribedSRAM.scala:17:26] .RW0_en (_tag_rdata_T_2 \| refill_done), // @[DescribedSRAM.scala:17:26] .RW0_clk (clock), .RW0_wmode (refill_done), // @[ICache.scala:399:37] .RW0_wdata (enc_tag), // @[ICache.scala:435:34] .RW0_rdata (_rockettile_icache_tag_array_0_RW0_rdata) ); // @[DescribedSRAM.scala:17:26] rockettile_icache_data_arrays_0_0 rockettile_icache_data_arrays_0_0 ( // @[DescribedSRAM.scala:17:26] .RW0_addr (wen ? mem_idx : _dout_WIRE), // @[DescribedSRAM.scala:17:26] .RW0_en (_dout_T_1 \| wen), // @[DescribedSRAM.scala:17:26] .RW0_clk (clock), .RW0_wmode (wen), // @[ICache.scala:570:49] .RW0_wdata (data), // @[ICache.scala:583:21] .RW0_rdata (_rockettile_icache_data_arrays_0_0_RW0_rdata) ); // @[DescribedSRAM.scala:17:26] rockettile_icache_data_arrays_1_0 rockettile_icache_data_arrays_1_0 ( // @[DescribedSRAM.scala:17:26] .RW0_addr (wen_1 ? mem_idx_1 : _dout_WIRE_1), // @[DescribedSRAM.scala:17:26] .RW0_en (_dout_T_3 \| wen_1), // @[DescribedSRAM.scala:17:26] .RW0_clk (clock), .RW0_wmode (wen_1), // @[ICache.scala:570:49] .RW0_wdata (data_1), // @[ICache.scala:583:21] .RW0_rdata (_rockettile_icache_data_arrays_1_0_RW0_rdata) ); // @[DescribedSRAM.scala:17:26] assign auto_master_out_a_valid = auto_master_out_a_valid_0; // @[ICache.scala:251:7] assign auto_master_out_a_bits_address = auto_master_out_a_bits_address_0; // @[ICache.scala:251:7] assign io_resp_valid = io_resp_valid_0; // @[ICache.scala:251:7] assign io_resp_bits_data = io_resp_bits_data_0; // @[ICache.scala:251:7] assign io_resp_bits_ae = io_resp_bits_ae_0; // @[ICache.scala:251:7] assign io_errors_bus_valid = io_errors_bus_valid_0; // @[ICache.scala:251:7] assign io_errors_bus_bits = io_errors_bus_bits_0; // @[ICache.scala:251:7] assign io_perf_acquire = io_perf_acquire_0; // @[ICache.scala:251:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_65 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 10, 0) node _source_ok_T = shr(io.in.a.bits.source, 11) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<11>(0h40f)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits = bits(_uncommonBits_T, 10, 0) node _T_4 = shr(io.in.a.bits.source, 11) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<11>(0h40f)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 10, 0) node _T_24 = shr(io.in.a.bits.source, 11) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<11>(0h40f)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<13>(0h1000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 10, 0) node _T_86 = shr(io.in.a.bits.source, 11) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<11>(0h40f)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<13>(0h1000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<13>(0h1000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 10, 0) node _T_152 = shr(io.in.a.bits.source, 11) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<11>(0h40f)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<13>(0h1000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 10, 0) node _T_199 = shr(io.in.a.bits.source, 11) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<11>(0h40f)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_208 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_209 = and(_T_207, _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<13>(0h1000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = and(_T_210, _T_215) node _T_217 = or(UInt<1>(0h0), _T_216) node _T_218 = and(_T_206, _T_217) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_218, UInt<1>(0h1), "") : assert_26 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(is_aligned, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_228, UInt<1>(0h1), "") : assert_29 node _T_232 = eq(io.in.a.bits.mask, mask) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_236 : node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_239 = and(_T_237, _T_238) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 10, 0) node _T_240 = shr(io.in.a.bits.source, 11) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = leq(UInt<1>(0h0), uncommonBits_5) node _T_243 = and(_T_241, _T_242) node _T_244 = leq(uncommonBits_5, UInt<11>(0h40f)) node _T_245 = and(_T_243, _T_244) node _T_246 = and(_T_239, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_253 = cvt(_T_252) node _T_254 = and(_T_253, asSInt(UInt<13>(0h1000))) node _T_255 = asSInt(_T_254) node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) node _T_257 = and(_T_251, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = and(_T_247, _T_258) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_259, UInt<1>(0h1), "") : assert_31 node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(is_aligned, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_269, UInt<1>(0h1), "") : assert_34 node _T_273 = not(mask) node _T_274 = and(io.in.a.bits.mask, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_275, UInt<1>(0h1), "") : assert_35 node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_279 : node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_282 = and(_T_280, _T_281) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 10, 0) node _T_283 = shr(io.in.a.bits.source, 11) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = leq(UInt<1>(0h0), uncommonBits_6) node _T_286 = and(_T_284, _T_285) node _T_287 = leq(uncommonBits_6, UInt<11>(0h40f)) node _T_288 = and(_T_286, _T_287) node _T_289 = and(_T_282, _T_288) node _T_290 = or(UInt<1>(0h0), _T_289) node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_292 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<13>(0h1000))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = and(_T_291, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = and(_T_290, _T_298) node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_T_299, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_299, UInt<1>(0h1), "") : assert_36 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(is_aligned, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_309, UInt<1>(0h1), "") : assert_39 node _T_313 = eq(io.in.a.bits.mask, mask) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_313, UInt<1>(0h1), "") : assert_40 node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_317 : node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 10, 0) node _T_321 = shr(io.in.a.bits.source, 11) node _T_322 = eq(_T_321, UInt<1>(0h0)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_7) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_7, UInt<11>(0h40f)) node _T_326 = and(_T_324, _T_325) node _T_327 = and(_T_320, _T_326) node _T_328 = or(UInt<1>(0h0), _T_327) node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<13>(0h1000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = and(_T_329, _T_334) node _T_336 = or(UInt<1>(0h0), _T_335) node _T_337 = and(_T_328, _T_336) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_337, UInt<1>(0h1), "") : assert_41 node _T_341 = asUInt(reset) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(is_aligned, UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_347, UInt<1>(0h1), "") : assert_44 node _T_351 = eq(io.in.a.bits.mask, mask) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_351, UInt<1>(0h1), "") : assert_45 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 10, 0) node _T_359 = shr(io.in.a.bits.source, 11) node _T_360 = eq(_T_359, UInt<1>(0h0)) node _T_361 = leq(UInt<1>(0h0), uncommonBits_8) node _T_362 = and(_T_360, _T_361) node _T_363 = leq(uncommonBits_8, UInt<11>(0h40f)) node _T_364 = and(_T_362, _T_363) node _T_365 = and(_T_358, _T_364) node _T_366 = or(UInt<1>(0h0), _T_365) node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_369 = cvt(_T_368) node _T_370 = and(_T_369, asSInt(UInt<13>(0h1000))) node _T_371 = asSInt(_T_370) node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0))) node _T_373 = and(_T_367, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = and(_T_366, _T_374) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_375, UInt<1>(0h1), "") : assert_46 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(is_aligned, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_385, UInt<1>(0h1), "") : assert_49 node _T_389 = eq(io.in.a.bits.mask, mask) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_389, UInt<1>(0h1), "") : assert_50 node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_393, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_397, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<11>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 10, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 11) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<11>(0h40f)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_401 : node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_405, UInt<1>(0h1), "") : assert_54 node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_409, UInt<1>(0h1), "") : assert_55 node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_413, UInt<1>(0h1), "") : assert_56 node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(_T_417, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_417, UInt<1>(0h1), "") : assert_57 node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_421 : node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(sink_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_428, UInt<1>(0h1), "") : assert_60 node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_432, UInt<1>(0h1), "") : assert_61 node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_436, UInt<1>(0h1), "") : assert_62 node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(_T_440, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_440, UInt<1>(0h1), "") : assert_63 node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_445 = or(UInt<1>(0h0), _T_444) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_445, UInt<1>(0h1), "") : assert_64 node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_449 : node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(sink_ok, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_457 = asUInt(reset) node _T_458 = eq(_T_457, UInt<1>(0h0)) when _T_458 : node _T_459 = eq(_T_456, UInt<1>(0h0)) when _T_459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_456, UInt<1>(0h1), "") : assert_67 node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_T_460, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_460, UInt<1>(0h1), "") : assert_68 node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_464, UInt<1>(0h1), "") : assert_69 node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_469 = or(_T_468, io.in.d.bits.corrupt) node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_T_469, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_469, UInt<1>(0h1), "") : assert_70 node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_474 = or(UInt<1>(0h0), _T_473) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_474, UInt<1>(0h1), "") : assert_71 node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_478 : node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_482, UInt<1>(0h1), "") : assert_73 node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_486, UInt<1>(0h1), "") : assert_74 node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_491, UInt<1>(0h1), "") : assert_75 node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_495 : node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_499, UInt<1>(0h1), "") : assert_77 node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_504 = or(_T_503, io.in.d.bits.corrupt) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_504, UInt<1>(0h1), "") : assert_78 node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_509, UInt<1>(0h1), "") : assert_79 node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_513 : node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_517, UInt<1>(0h1), "") : assert_81 node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_521, UInt<1>(0h1), "") : assert_82 node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_526 = or(UInt<1>(0h0), _T_525) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_526, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<21>(0h0) connect _WIRE.bits.source, UInt<11>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_530, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<21>(0h0) connect _WIRE_2.bits.source, UInt<11>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_534, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_538, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_542 = eq(a_first, UInt<1>(0h0)) node _T_543 = and(io.in.a.valid, _T_542) when _T_543 : node _T_544 = eq(io.in.a.bits.opcode, opcode) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_544, UInt<1>(0h1), "") : assert_87 node _T_548 = eq(io.in.a.bits.param, param) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_548, UInt<1>(0h1), "") : assert_88 node _T_552 = eq(io.in.a.bits.size, size) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_552, UInt<1>(0h1), "") : assert_89 node _T_556 = eq(io.in.a.bits.source, source) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_556, UInt<1>(0h1), "") : assert_90 node _T_560 = eq(io.in.a.bits.address, address) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_560, UInt<1>(0h1), "") : assert_91 node _T_564 = and(io.in.a.ready, io.in.a.valid) node _T_565 = and(_T_564, a_first) when _T_565 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_566 = eq(d_first, UInt<1>(0h0)) node _T_567 = and(io.in.d.valid, _T_566) when _T_567 : node _T_568 = eq(io.in.d.bits.opcode, opcode_1) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_568, UInt<1>(0h1), "") : assert_92 node _T_572 = eq(io.in.d.bits.param, param_1) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_572, UInt<1>(0h1), "") : assert_93 node _T_576 = eq(io.in.d.bits.size, size_1) node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(_T_576, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_576, UInt<1>(0h1), "") : assert_94 node _T_580 = eq(io.in.d.bits.source, source_1) node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(_T_580, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_580, UInt<1>(0h1), "") : assert_95 node _T_584 = eq(io.in.d.bits.sink, sink) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_584, UInt<1>(0h1), "") : assert_96 node _T_588 = eq(io.in.d.bits.denied, denied) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_588, UInt<1>(0h1), "") : assert_97 node _T_592 = and(io.in.d.ready, io.in.d.valid) node _T_593 = and(_T_592, d_first) when _T_593 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<1040>, clock, reset, UInt<1040>(0h0) regreset inflight_opcodes : UInt<4160>, clock, reset, UInt<4160>(0h0) regreset inflight_sizes : UInt<4160>, clock, reset, UInt<4160>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1040> connect a_set, UInt<1040>(0h0) wire a_set_wo_ready : UInt<1040> connect a_set_wo_ready, UInt<1040>(0h0) wire a_opcodes_set : UInt<4160> connect a_opcodes_set, UInt<4160>(0h0) wire a_sizes_set : UInt<4160> connect a_sizes_set, UInt<4160>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_594 = and(io.in.a.valid, a_first_1) node _T_595 = and(_T_594, UInt<1>(0h1)) when _T_595 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_596 = and(io.in.a.ready, io.in.a.valid) node _T_597 = and(_T_596, a_first_1) node _T_598 = and(_T_597, UInt<1>(0h1)) when _T_598 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_599 = dshr(inflight, io.in.a.bits.source) node _T_600 = bits(_T_599, 0, 0) node _T_601 = eq(_T_600, UInt<1>(0h0)) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_601, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1040> connect d_clr, UInt<1040>(0h0) wire d_clr_wo_ready : UInt<1040> connect d_clr_wo_ready, UInt<1040>(0h0) wire d_opcodes_clr : UInt<4160> connect d_opcodes_clr, UInt<4160>(0h0) wire d_sizes_clr : UInt<4160> connect d_sizes_clr, UInt<4160>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_605 = and(io.in.d.valid, d_first_1) node _T_606 = and(_T_605, UInt<1>(0h1)) node _T_607 = eq(d_release_ack, UInt<1>(0h0)) node _T_608 = and(_T_606, _T_607) when _T_608 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_609 = and(io.in.d.ready, io.in.d.valid) node _T_610 = and(_T_609, d_first_1) node _T_611 = and(_T_610, UInt<1>(0h1)) node _T_612 = eq(d_release_ack, UInt<1>(0h0)) node _T_613 = and(_T_611, _T_612) when _T_613 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_614 = and(io.in.d.valid, d_first_1) node _T_615 = and(_T_614, UInt<1>(0h1)) node _T_616 = eq(d_release_ack, UInt<1>(0h0)) node _T_617 = and(_T_615, _T_616) when _T_617 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_618 = dshr(inflight, io.in.d.bits.source) node _T_619 = bits(_T_618, 0, 0) node _T_620 = or(_T_619, same_cycle_resp) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_620, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_626 = or(_T_624, _T_625) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_626, UInt<1>(0h1), "") : assert_100 node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_630, UInt<1>(0h1), "") : assert_101 else : node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_636 = or(_T_634, _T_635) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_636, UInt<1>(0h1), "") : assert_102 node _T_640 = eq(io.in.d.bits.size, a_size_lookup) node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(_T_640, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_640, UInt<1>(0h1), "") : assert_103 node _T_644 = and(io.in.d.valid, d_first_1) node _T_645 = and(_T_644, a_first_1) node _T_646 = and(_T_645, io.in.a.valid) node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_648 = and(_T_646, _T_647) node _T_649 = eq(d_release_ack, UInt<1>(0h0)) node _T_650 = and(_T_648, _T_649) when _T_650 : node _T_651 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_652 = or(_T_651, io.in.a.ready) node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(_T_652, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_652, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_133 node _T_656 = orr(inflight) node _T_657 = eq(_T_656, UInt<1>(0h0)) node _T_658 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_659 = or(_T_657, _T_658) node _T_660 = lt(watchdog, plusarg_reader.out) node _T_661 = or(_T_659, _T_660) node _T_662 = asUInt(reset) node _T_663 = eq(_T_662, UInt<1>(0h0)) when _T_663 : node _T_664 = eq(_T_661, UInt<1>(0h0)) when _T_664 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_661, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_665 = and(io.in.a.ready, io.in.a.valid) node _T_666 = and(io.in.d.ready, io.in.d.valid) node _T_667 = or(_T_665, _T_666) when _T_667 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<1040>, clock, reset, UInt<1040>(0h0) regreset inflight_opcodes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0) regreset inflight_sizes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<21>(0h0) connect _c_first_WIRE.bits.source, UInt<11>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<21>(0h0) connect _c_first_WIRE_2.bits.source, UInt<11>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1040> connect c_set, UInt<1040>(0h0) wire c_set_wo_ready : UInt<1040> connect c_set_wo_ready, UInt<1040>(0h0) wire c_opcodes_set : UInt<4160> connect c_opcodes_set, UInt<4160>(0h0) wire c_sizes_set : UInt<4160> connect c_sizes_set, UInt<4160>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<21>(0h0) connect _WIRE_6.bits.source, UInt<11>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_668 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<21>(0h0) connect _WIRE_8.bits.source, UInt<11>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_669 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_670 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_671 = and(_T_669, _T_670) node _T_672 = and(_T_668, _T_671) when _T_672 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<21>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<11>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<21>(0h0) connect _WIRE_10.bits.source, UInt<11>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_673 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_674 = and(_T_673, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<21>(0h0) connect _WIRE_12.bits.source, UInt<11>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_675 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_676 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_677 = and(_T_675, _T_676) node _T_678 = and(_T_674, _T_677) when _T_678 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<21>(0h0) connect _c_set_WIRE.bits.source, UInt<11>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<21>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<11>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<21>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<11>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<21>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<11>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<21>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<11>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<21>(0h0) connect _WIRE_14.bits.source, UInt<11>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_679 = dshr(inflight_1, _WIRE_15.bits.source) node _T_680 = bits(_T_679, 0, 0) node _T_681 = eq(_T_680, UInt<1>(0h0)) node _T_682 = asUInt(reset) node _T_683 = eq(_T_682, UInt<1>(0h0)) when _T_683 : node _T_684 = eq(_T_681, UInt<1>(0h0)) when _T_684 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_681, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<21>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<11>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<21>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<11>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1040> connect d_clr_1, UInt<1040>(0h0) wire d_clr_wo_ready_1 : UInt<1040> connect d_clr_wo_ready_1, UInt<1040>(0h0) wire d_opcodes_clr_1 : UInt<4160> connect d_opcodes_clr_1, UInt<4160>(0h0) wire d_sizes_clr_1 : UInt<4160> connect d_sizes_clr_1, UInt<4160>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_685 = and(io.in.d.valid, d_first_2) node _T_686 = and(_T_685, UInt<1>(0h1)) node _T_687 = and(_T_686, d_release_ack_1) when _T_687 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_688 = and(io.in.d.ready, io.in.d.valid) node _T_689 = and(_T_688, d_first_2) node _T_690 = and(_T_689, UInt<1>(0h1)) node _T_691 = and(_T_690, d_release_ack_1) when _T_691 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_692 = and(io.in.d.valid, d_first_2) node _T_693 = and(_T_692, UInt<1>(0h1)) node _T_694 = and(_T_693, d_release_ack_1) when _T_694 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_695 = dshr(inflight_1, io.in.d.bits.source) node _T_696 = bits(_T_695, 0, 0) node _T_697 = or(_T_696, same_cycle_resp_1) node _T_698 = asUInt(reset) node _T_699 = eq(_T_698, UInt<1>(0h0)) when _T_699 : node _T_700 = eq(_T_697, UInt<1>(0h0)) when _T_700 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_697, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<21>(0h0) connect _WIRE_16.bits.source, UInt<11>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_701 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_702 = asUInt(reset) node _T_703 = eq(_T_702, UInt<1>(0h0)) when _T_703 : node _T_704 = eq(_T_701, UInt<1>(0h0)) when _T_704 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_701, UInt<1>(0h1), "") : assert_108 else : node _T_705 = eq(io.in.d.bits.size, c_size_lookup) node _T_706 = asUInt(reset) node _T_707 = eq(_T_706, UInt<1>(0h0)) when _T_707 : node _T_708 = eq(_T_705, UInt<1>(0h0)) when _T_708 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_705, UInt<1>(0h1), "") : assert_109 node _T_709 = and(io.in.d.valid, d_first_2) node _T_710 = and(_T_709, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<21>(0h0) connect _WIRE_18.bits.source, UInt<11>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_711 = and(_T_710, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<21>(0h0) connect _WIRE_20.bits.source, UInt<11>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_712 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_713 = and(_T_711, _T_712) node _T_714 = and(_T_713, d_release_ack_1) node _T_715 = eq(c_probe_ack, UInt<1>(0h0)) node _T_716 = and(_T_714, _T_715) when _T_716 : node _T_717 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<21>(0h0) connect _WIRE_22.bits.source, UInt<11>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_718 = or(_T_717, _WIRE_23.ready) node _T_719 = asUInt(reset) node _T_720 = eq(_T_719, UInt<1>(0h0)) when _T_720 : node _T_721 = eq(_T_718, UInt<1>(0h0)) when _T_721 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_718, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_134 node _T_722 = orr(inflight_1) node _T_723 = eq(_T_722, UInt<1>(0h0)) node _T_724 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_725 = or(_T_723, _T_724) node _T_726 = lt(watchdog_1, plusarg_reader_1.out) node _T_727 = or(_T_725, _T_726) node _T_728 = asUInt(reset) node _T_729 = eq(_T_728, UInt<1>(0h0)) when _T_729 : node _T_730 = eq(_T_727, UInt<1>(0h0)) when _T_730 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:25)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_727, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<21>(0h0) connect _WIRE_24.bits.source, UInt<11>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_731 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_732 = and(io.in.d.ready, io.in.d.valid) node _T_733 = or(_T_731, _T_732) when _T_733 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_65( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_d_bits_source // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [20:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [10:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data = 64'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_wo_ready_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_wo_ready_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_4_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_5_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_first_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_first_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_wo_ready_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_wo_ready_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_opcodes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_opcodes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_sizes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_sizes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _c_probe_ack_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _c_probe_ack_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [10:0] _same_cycle_resp_WIRE_4_bits_source = 11'h0; // @[Bundles.scala:265:74] wire [10:0] _same_cycle_resp_WIRE_5_bits_source = 11'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [16385:0] _c_sizes_set_T_1 = 16386'h0; // @[Monitor.scala:768:52] wire [13:0] _c_opcodes_set_T = 14'h0; // @[Monitor.scala:767:79] wire [13:0] _c_sizes_set_T = 14'h0; // @[Monitor.scala:768:77] wire [16386:0] _c_opcodes_set_T_1 = 16387'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [2047:0] _c_set_wo_ready_T = 2048'h1; // @[OneHot.scala:58:35] wire [2047:0] _c_set_T = 2048'h1; // @[OneHot.scala:58:35] wire [4159:0] c_opcodes_set = 4160'h0; // @[Monitor.scala:740:34] wire [4159:0] c_sizes_set = 4160'h0; // @[Monitor.scala:741:34] wire [1039:0] c_set = 1040'h0; // @[Monitor.scala:738:34] wire [1039:0] c_set_wo_ready = 1040'h0; // @[Monitor.scala:739:34] wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76] wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [10:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [10:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [20:0] _is_aligned_T = {18'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 21'h0; // @[Edges.scala:21:{16,24}] wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [10:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [10:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [10:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 11'h410; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_665 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_665; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_665; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [10:0] source; // @[Monitor.scala:390:22] reg [20:0] address; // @[Monitor.scala:391:22] wire _T_733 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_733; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [10:0] source_1; // @[Monitor.scala:541:22] reg [1039:0] inflight; // @[Monitor.scala:614:27] reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [1039:0] a_set; // @[Monitor.scala:626:34] wire [1039:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [4159:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [4159:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [13:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [13:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [13:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [13:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [13:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [13:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [13:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [13:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [13:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [4159:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [4159:0] _a_opcode_lookup_T_6 = {4156'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [4159:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [4159:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [4159:0] _a_size_lookup_T_6 = {4156'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [4159:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[4159:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [2047:0] _GEN_2 = 2048'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [2047:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_665 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [13:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [13:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [13:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [16386:0] _a_opcodes_set_T_1 = {16383'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [16385:0] _a_sizes_set_T_1 = {16383'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [1039:0] d_clr; // @[Monitor.scala:664:34] wire [1039:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [4159:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [4159:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [2047:0] _GEN_5 = 2048'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [2047:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_733 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [16398:0] _d_opcodes_clr_T_5 = 16399'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [16398:0] _d_sizes_clr_T_5 = 16399'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1039:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [1039:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1039:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [4159:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [4159:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [4159:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [4159:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [4159:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [4159:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1039:0] inflight_1; // @[Monitor.scala:726:35] wire [1039:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [4159:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [4159:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [4159:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [4159:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [4159:0] _c_opcode_lookup_T_6 = {4156'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [4159:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [4159:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [4159:0] _c_size_lookup_T_6 = {4156'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [4159:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[4159:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [1039:0] d_clr_1; // @[Monitor.scala:774:34] wire [1039:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [4159:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [4159:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_709 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_709 & d_release_ack_1 ? _d_clr_wo_ready_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire _T_691 = _T_733 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_691 ? _d_clr_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35] wire [16398:0] _d_opcodes_clr_T_11 = 16399'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_691 ? _d_opcodes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [16398:0] _d_sizes_clr_T_11 = 16399'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_691 ? _d_sizes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 11'h0; // @[Monitor.scala:36:7, :795:113] wire [1039:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1039:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [4159:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [4159:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [4159:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [4159:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_223 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_407 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0	module AsyncResetSynchronizerShiftReg_w1_d3_i0_223( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_407 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module CaptureChain_JTAGIdcodeBundle : input clock : Clock input reset : Reset output io : { flip chainIn : { shift : UInt<1>, data : UInt<1>, capture : UInt<1>, update : UInt<1>}, chainOut : { shift : UInt<1>, data : UInt<1>, capture : UInt<1>, update : UInt<1>}, capture : { flip bits : { version : UInt<4>, partNumber : UInt<16>, mfrId : UInt<11>, always1 : UInt<1>}, capture : UInt<1>}} connect io.chainOut.shift, io.chainIn.shift connect io.chainOut.capture, io.chainIn.capture connect io.chainOut.update, io.chainIn.update reg regs_0 : UInt<1>, clock reg regs_1 : UInt<1>, clock reg regs_2 : UInt<1>, clock reg regs_3 : UInt<1>, clock reg regs_4 : UInt<1>, clock reg regs_5 : UInt<1>, clock reg regs_6 : UInt<1>, clock reg regs_7 : UInt<1>, clock reg regs_8 : UInt<1>, clock reg regs_9 : UInt<1>, clock reg regs_10 : UInt<1>, clock reg regs_11 : UInt<1>, clock reg regs_12 : UInt<1>, clock reg regs_13 : UInt<1>, clock reg regs_14 : UInt<1>, clock reg regs_15 : UInt<1>, clock reg regs_16 : UInt<1>, clock reg regs_17 : UInt<1>, clock reg regs_18 : UInt<1>, clock reg regs_19 : UInt<1>, clock reg regs_20 : UInt<1>, clock reg regs_21 : UInt<1>, clock reg regs_22 : UInt<1>, clock reg regs_23 : UInt<1>, clock reg regs_24 : UInt<1>, clock reg regs_25 : UInt<1>, clock reg regs_26 : UInt<1>, clock reg regs_27 : UInt<1>, clock reg regs_28 : UInt<1>, clock reg regs_29 : UInt<1>, clock reg regs_30 : UInt<1>, clock reg regs_31 : UInt<1>, clock connect io.chainOut.data, regs_0 when io.chainIn.capture : node regs_0_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_0_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_0_T = cat(regs_0_hi, regs_0_lo) node _regs_0_T_1 = bits(_regs_0_T, 0, 0) connect regs_0, _regs_0_T_1 node regs_1_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_1_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_1_T = cat(regs_1_hi, regs_1_lo) node _regs_1_T_1 = bits(_regs_1_T, 1, 1) connect regs_1, _regs_1_T_1 node regs_2_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_2_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_2_T = cat(regs_2_hi, regs_2_lo) node _regs_2_T_1 = bits(_regs_2_T, 2, 2) connect regs_2, _regs_2_T_1 node regs_3_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_3_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_3_T = cat(regs_3_hi, regs_3_lo) node _regs_3_T_1 = bits(_regs_3_T, 3, 3) connect regs_3, _regs_3_T_1 node regs_4_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_4_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_4_T = cat(regs_4_hi, regs_4_lo) node _regs_4_T_1 = bits(_regs_4_T, 4, 4) connect regs_4, _regs_4_T_1 node regs_5_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_5_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_5_T = cat(regs_5_hi, regs_5_lo) node _regs_5_T_1 = bits(_regs_5_T, 5, 5) connect regs_5, _regs_5_T_1 node regs_6_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_6_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_6_T = cat(regs_6_hi, regs_6_lo) node _regs_6_T_1 = bits(_regs_6_T, 6, 6) connect regs_6, _regs_6_T_1 node regs_7_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_7_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_7_T = cat(regs_7_hi, regs_7_lo) node _regs_7_T_1 = bits(_regs_7_T, 7, 7) connect regs_7, _regs_7_T_1 node regs_8_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_8_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_8_T = cat(regs_8_hi, regs_8_lo) node _regs_8_T_1 = bits(_regs_8_T, 8, 8) connect regs_8, _regs_8_T_1 node regs_9_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_9_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_9_T = cat(regs_9_hi, regs_9_lo) node _regs_9_T_1 = bits(_regs_9_T, 9, 9) connect regs_9, _regs_9_T_1 node regs_10_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_10_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_10_T = cat(regs_10_hi, regs_10_lo) node _regs_10_T_1 = bits(_regs_10_T, 10, 10) connect regs_10, _regs_10_T_1 node regs_11_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_11_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_11_T = cat(regs_11_hi, regs_11_lo) node _regs_11_T_1 = bits(_regs_11_T, 11, 11) connect regs_11, _regs_11_T_1 node regs_12_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_12_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_12_T = cat(regs_12_hi, regs_12_lo) node _regs_12_T_1 = bits(_regs_12_T, 12, 12) connect regs_12, _regs_12_T_1 node regs_13_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_13_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_13_T = cat(regs_13_hi, regs_13_lo) node _regs_13_T_1 = bits(_regs_13_T, 13, 13) connect regs_13, _regs_13_T_1 node regs_14_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_14_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_14_T = cat(regs_14_hi, regs_14_lo) node _regs_14_T_1 = bits(_regs_14_T, 14, 14) connect regs_14, _regs_14_T_1 node regs_15_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_15_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_15_T = cat(regs_15_hi, regs_15_lo) node _regs_15_T_1 = bits(_regs_15_T, 15, 15) connect regs_15, _regs_15_T_1 node regs_16_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_16_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_16_T = cat(regs_16_hi, regs_16_lo) node _regs_16_T_1 = bits(_regs_16_T, 16, 16) connect regs_16, _regs_16_T_1 node regs_17_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_17_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_17_T = cat(regs_17_hi, regs_17_lo) node _regs_17_T_1 = bits(_regs_17_T, 17, 17) connect regs_17, _regs_17_T_1 node regs_18_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_18_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_18_T = cat(regs_18_hi, regs_18_lo) node _regs_18_T_1 = bits(_regs_18_T, 18, 18) connect regs_18, _regs_18_T_1 node regs_19_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_19_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_19_T = cat(regs_19_hi, regs_19_lo) node _regs_19_T_1 = bits(_regs_19_T, 19, 19) connect regs_19, _regs_19_T_1 node regs_20_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_20_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_20_T = cat(regs_20_hi, regs_20_lo) node _regs_20_T_1 = bits(_regs_20_T, 20, 20) connect regs_20, _regs_20_T_1 node regs_21_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_21_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_21_T = cat(regs_21_hi, regs_21_lo) node _regs_21_T_1 = bits(_regs_21_T, 21, 21) connect regs_21, _regs_21_T_1 node regs_22_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_22_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_22_T = cat(regs_22_hi, regs_22_lo) node _regs_22_T_1 = bits(_regs_22_T, 22, 22) connect regs_22, _regs_22_T_1 node regs_23_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_23_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_23_T = cat(regs_23_hi, regs_23_lo) node _regs_23_T_1 = bits(_regs_23_T, 23, 23) connect regs_23, _regs_23_T_1 node regs_24_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_24_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_24_T = cat(regs_24_hi, regs_24_lo) node _regs_24_T_1 = bits(_regs_24_T, 24, 24) connect regs_24, _regs_24_T_1 node regs_25_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_25_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_25_T = cat(regs_25_hi, regs_25_lo) node _regs_25_T_1 = bits(_regs_25_T, 25, 25) connect regs_25, _regs_25_T_1 node regs_26_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_26_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_26_T = cat(regs_26_hi, regs_26_lo) node _regs_26_T_1 = bits(_regs_26_T, 26, 26) connect regs_26, _regs_26_T_1 node regs_27_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_27_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_27_T = cat(regs_27_hi, regs_27_lo) node _regs_27_T_1 = bits(_regs_27_T, 27, 27) connect regs_27, _regs_27_T_1 node regs_28_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_28_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_28_T = cat(regs_28_hi, regs_28_lo) node _regs_28_T_1 = bits(_regs_28_T, 28, 28) connect regs_28, _regs_28_T_1 node regs_29_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_29_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_29_T = cat(regs_29_hi, regs_29_lo) node _regs_29_T_1 = bits(_regs_29_T, 29, 29) connect regs_29, _regs_29_T_1 node regs_30_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_30_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_30_T = cat(regs_30_hi, regs_30_lo) node _regs_30_T_1 = bits(_regs_30_T, 30, 30) connect regs_30, _regs_30_T_1 node regs_31_lo = cat(io.capture.bits.mfrId, io.capture.bits.always1) node regs_31_hi = cat(io.capture.bits.version, io.capture.bits.partNumber) node _regs_31_T = cat(regs_31_hi, regs_31_lo) node _regs_31_T_1 = bits(_regs_31_T, 31, 31) connect regs_31, _regs_31_T_1 connect io.capture.capture, UInt<1>(0h1) else : when io.chainIn.shift : connect regs_31, io.chainIn.data connect regs_0, regs_1 connect regs_1, regs_2 connect regs_2, regs_3 connect regs_3, regs_4 connect regs_4, regs_5 connect regs_5, regs_6 connect regs_6, regs_7 connect regs_7, regs_8 connect regs_8, regs_9 connect regs_9, regs_10 connect regs_10, regs_11 connect regs_11, regs_12 connect regs_12, regs_13 connect regs_13, regs_14 connect regs_14, regs_15 connect regs_15, regs_16 connect regs_16, regs_17 connect regs_17, regs_18 connect regs_18, regs_19 connect regs_19, regs_20 connect regs_20, regs_21 connect regs_21, regs_22 connect regs_22, regs_23 connect regs_23, regs_24 connect regs_24, regs_25 connect regs_25, regs_26 connect regs_26, regs_27 connect regs_27, regs_28 connect regs_28, regs_29 connect regs_29, regs_30 connect regs_30, regs_31 connect io.capture.capture, UInt<1>(0h0) else : connect io.capture.capture, UInt<1>(0h0) node _T = and(io.chainIn.capture, io.chainIn.update) node _T_1 = eq(_T, UInt<1>(0h0)) node _T_2 = and(io.chainIn.capture, io.chainIn.shift) node _T_3 = eq(_T_2, UInt<1>(0h0)) node _T_4 = and(_T_1, _T_3) node _T_5 = and(io.chainIn.update, io.chainIn.shift) node _T_6 = eq(_T_5, UInt<1>(0h0)) node _T_7 = and(_T_4, _T_6) node _T_8 = asUInt(reset) node _T_9 = eq(_T_8, UInt<1>(0h0)) when _T_9 : node _T_10 = eq(_T_7, UInt<1>(0h0)) when _T_10 : printf(clock, UInt<1>(0h1), "Assertion failed\n at JtagShifter.scala:118 assert(!(io.chainIn.capture && io.chainIn.update)\n") : printf assert(clock, _T_7, UInt<1>(0h1), "") : assert	module CaptureChain_JTAGIdcodeBundle( // @[JtagShifter.scala:89:7] input clock, // @[JtagShifter.scala:89:7] input reset, // @[JtagShifter.scala:89:7] input io_chainIn_shift, // @[JtagShifter.scala:94:14] input io_chainIn_data, // @[JtagShifter.scala:94:14] input io_chainIn_capture, // @[JtagShifter.scala:94:14] input io_chainIn_update, // @[JtagShifter.scala:94:14] output io_chainOut_shift, // @[JtagShifter.scala:94:14] output io_chainOut_data, // @[JtagShifter.scala:94:14] output io_chainOut_capture, // @[JtagShifter.scala:94:14] output io_chainOut_update // @[JtagShifter.scala:94:14] ); wire io_chainIn_shift_0 = io_chainIn_shift; // @[JtagShifter.scala:89:7] wire io_chainIn_data_0 = io_chainIn_data; // @[JtagShifter.scala:89:7] wire io_chainIn_capture_0 = io_chainIn_capture; // @[JtagShifter.scala:89:7] wire io_chainIn_update_0 = io_chainIn_update; // @[JtagShifter.scala:89:7] wire [3:0] io_capture_bits_version = 4'h0; // @[JtagShifter.scala:89:7] wire [15:0] io_capture_bits_partNumber = 16'h0; // @[JtagShifter.scala:89:7] wire [10:0] io_capture_bits_mfrId = 11'h0; // @[JtagShifter.scala:89:7] wire io_capture_bits_always1 = 1'h1; // @[JtagShifter.scala:89:7] wire _regs_0_T_1 = 1'h1; // @[JtagShifter.scala:109:60] wire _regs_1_T_1 = 1'h0; // @[JtagShifter.scala:109:60] wire _regs_2_T_1 = 1'h0; // @[JtagShifter.scala:109:60] wire _regs_3_T_1 = 1'h0; // @[JtagShifter.scala:109:60] wire _regs_4_T_1 = 1'h0; // @[JtagShifter.scala:109:60] wire _regs_5_T_1 = 1'h0; // @[JtagShifter.scala:109:60] wire _regs_6_T_1 = 1'h0; // @[JtagShifter.scala:109:60] wire _regs_7_T_1 = 1'h0; // @[JtagShifter.scala:109:60] wire _regs_8_T_1 = 1'h0; // @[JtagShifter.scala:109:60] wire _regs_9_T_1 = 1'h0; // @[JtagShifter.scala:109:60] wire _regs_10_T_1 = 1'h0; // @[JtagShifter.scala:109:60] wire _regs_11_T_1 = 1'h0; // @[JtagShifter.scala:109:60] wire _regs_12_T_1 = 1'h0; // @[JtagShifter.scala:109:60] wire _regs_13_T_1 = 1'h0; // @[JtagShifter.scala:109:60] wire _regs_14_T_1 = 1'h0; // @[JtagShifter.scala:109:60] wire _regs_15_T_1 = 1'h0; // @[JtagShifter.scala:109:60] wire _regs_16_T_1 = 1'h0; // @[JtagShifter.scala:109:60] wire _regs_17_T_1 = 1'h0; // @[JtagShifter.scala:109:60] wire _regs_18_T_1 = 1'h0; // @[JtagShifter.scala:109:60] wire _regs_19_T_1 = 1'h0; // @[JtagShifter.scala:109:60] wire _regs_20_T_1 = 1'h0; // @[JtagShifter.scala:109:60] wire _regs_21_T_1 = 1'h0; // @[JtagShifter.scala:109:60] wire _regs_22_T_1 = 1'h0; // @[JtagShifter.scala:109:60] wire _regs_23_T_1 = 1'h0; // @[JtagShifter.scala:109:60] wire _regs_24_T_1 = 1'h0; // @[JtagShifter.scala:109:60] wire _regs_25_T_1 = 1'h0; // @[JtagShifter.scala:109:60] wire _regs_26_T_1 = 1'h0; // @[JtagShifter.scala:109:60] wire _regs_27_T_1 = 1'h0; // @[JtagShifter.scala:109:60] wire _regs_28_T_1 = 1'h0; // @[JtagShifter.scala:109:60] wire _regs_29_T_1 = 1'h0; // @[JtagShifter.scala:109:60] wire _regs_30_T_1 = 1'h0; // @[JtagShifter.scala:109:60] wire _regs_31_T_1 = 1'h0; // @[JtagShifter.scala:109:60] wire [31:0] _regs_0_T = 32'h1; // @[JtagShifter.scala:109:54] wire [31:0] _regs_1_T = 32'h1; // @[JtagShifter.scala:109:54] wire [31:0] _regs_2_T = 32'h1; // @[JtagShifter.scala:109:54] wire [31:0] _regs_3_T = 32'h1; // @[JtagShifter.scala:109:54] wire [31:0] _regs_4_T = 32'h1; // @[JtagShifter.scala:109:54] wire [31:0] _regs_5_T = 32'h1; // @[JtagShifter.scala:109:54] wire [31:0] _regs_6_T = 32'h1; // @[JtagShifter.scala:109:54] wire [31:0] _regs_7_T = 32'h1; // @[JtagShifter.scala:109:54] wire [31:0] _regs_8_T = 32'h1; // @[JtagShifter.scala:109:54] wire [31:0] _regs_9_T = 32'h1; // @[JtagShifter.scala:109:54] wire [31:0] _regs_10_T = 32'h1; // @[JtagShifter.scala:109:54] wire [31:0] _regs_11_T = 32'h1; // @[JtagShifter.scala:109:54] wire [31:0] _regs_12_T = 32'h1; // @[JtagShifter.scala:109:54] wire [31:0] _regs_13_T = 32'h1; // @[JtagShifter.scala:109:54] wire [31:0] _regs_14_T = 32'h1; // @[JtagShifter.scala:109:54] wire [31:0] _regs_15_T = 32'h1; // @[JtagShifter.scala:109:54] wire [31:0] _regs_16_T = 32'h1; // @[JtagShifter.scala:109:54] wire [31:0] _regs_17_T = 32'h1; // @[JtagShifter.scala:109:54] wire [31:0] _regs_18_T = 32'h1; // @[JtagShifter.scala:109:54] wire [31:0] _regs_19_T = 32'h1; // @[JtagShifter.scala:109:54] wire [31:0] _regs_20_T = 32'h1; // @[JtagShifter.scala:109:54] wire [31:0] _regs_21_T = 32'h1; // @[JtagShifter.scala:109:54] wire [31:0] _regs_22_T = 32'h1; // @[JtagShifter.scala:109:54] wire [31:0] _regs_23_T = 32'h1; // @[JtagShifter.scala:109:54] wire [31:0] _regs_24_T = 32'h1; // @[JtagShifter.scala:109:54] wire [31:0] _regs_25_T = 32'h1; // @[JtagShifter.scala:109:54] wire [31:0] _regs_26_T = 32'h1; // @[JtagShifter.scala:109:54] wire [31:0] _regs_27_T = 32'h1; // @[JtagShifter.scala:109:54] wire [31:0] _regs_28_T = 32'h1; // @[JtagShifter.scala:109:54] wire [31:0] _regs_29_T = 32'h1; // @[JtagShifter.scala:109:54] wire [31:0] _regs_30_T = 32'h1; // @[JtagShifter.scala:109:54] wire [31:0] _regs_31_T = 32'h1; // @[JtagShifter.scala:109:54] wire [19:0] regs_0_hi = 20'h0; // @[JtagShifter.scala:109:54] wire [19:0] regs_1_hi = 20'h0; // @[JtagShifter.scala:109:54] wire [19:0] regs_2_hi = 20'h0; // @[JtagShifter.scala:109:54] wire [19:0] regs_3_hi = 20'h0; // @[JtagShifter.scala:109:54] wire [19:0] regs_4_hi = 20'h0; // @[JtagShifter.scala:109:54] wire [19:0] regs_5_hi = 20'h0; // @[JtagShifter.scala:109:54] wire [19:0] regs_6_hi = 20'h0; // @[JtagShifter.scala:109:54] wire [19:0] regs_7_hi = 20'h0; // @[JtagShifter.scala:109:54] wire [19:0] regs_8_hi = 20'h0; // @[JtagShifter.scala:109:54] wire [19:0] regs_9_hi = 20'h0; // @[JtagShifter.scala:109:54] wire [19:0] regs_10_hi = 20'h0; // @[JtagShifter.scala:109:54] wire [19:0] regs_11_hi = 20'h0; // @[JtagShifter.scala:109:54] wire [19:0] regs_12_hi = 20'h0; // @[JtagShifter.scala:109:54] wire [19:0] regs_13_hi = 20'h0; // @[JtagShifter.scala:109:54] wire [19:0] regs_14_hi = 20'h0; // @[JtagShifter.scala:109:54] wire [19:0] regs_15_hi = 20'h0; // @[JtagShifter.scala:109:54] wire [19:0] regs_16_hi = 20'h0; // @[JtagShifter.scala:109:54] wire [19:0] regs_17_hi = 20'h0; // @[JtagShifter.scala:109:54] wire [19:0] regs_18_hi = 20'h0; // @[JtagShifter.scala:109:54] wire [19:0] regs_19_hi = 20'h0; // @[JtagShifter.scala:109:54] wire [19:0] regs_20_hi = 20'h0; // @[JtagShifter.scala:109:54] wire [19:0] regs_21_hi = 20'h0; // @[JtagShifter.scala:109:54] wire [19:0] regs_22_hi = 20'h0; // @[JtagShifter.scala:109:54] wire [19:0] regs_23_hi = 20'h0; // @[JtagShifter.scala:109:54] wire [19:0] regs_24_hi = 20'h0; // @[JtagShifter.scala:109:54] wire [19:0] regs_25_hi = 20'h0; // @[JtagShifter.scala:109:54] wire [19:0] regs_26_hi = 20'h0; // @[JtagShifter.scala:109:54] wire [19:0] regs_27_hi = 20'h0; // @[JtagShifter.scala:109:54] wire [19:0] regs_28_hi = 20'h0; // @[JtagShifter.scala:109:54] wire [19:0] regs_29_hi = 20'h0; // @[JtagShifter.scala:109:54] wire [19:0] regs_30_hi = 20'h0; // @[JtagShifter.scala:109:54] wire [19:0] regs_31_hi = 20'h0; // @[JtagShifter.scala:109:54] wire [11:0] regs_0_lo = 12'h1; // @[JtagShifter.scala:109:54] wire [11:0] regs_1_lo = 12'h1; // @[JtagShifter.scala:109:54] wire [11:0] regs_2_lo = 12'h1; // @[JtagShifter.scala:109:54] wire [11:0] regs_3_lo = 12'h1; // @[JtagShifter.scala:109:54] wire [11:0] regs_4_lo = 12'h1; // @[JtagShifter.scala:109:54] wire [11:0] regs_5_lo = 12'h1; // @[JtagShifter.scala:109:54] wire [11:0] regs_6_lo = 12'h1; // @[JtagShifter.scala:109:54] wire [11:0] regs_7_lo = 12'h1; // @[JtagShifter.scala:109:54] wire [11:0] regs_8_lo = 12'h1; // @[JtagShifter.scala:109:54] wire [11:0] regs_9_lo = 12'h1; // @[JtagShifter.scala:109:54] wire [11:0] regs_10_lo = 12'h1; // @[JtagShifter.scala:109:54] wire [11:0] regs_11_lo = 12'h1; // @[JtagShifter.scala:109:54] wire [11:0] regs_12_lo = 12'h1; // @[JtagShifter.scala:109:54] wire [11:0] regs_13_lo = 12'h1; // @[JtagShifter.scala:109:54] wire [11:0] regs_14_lo = 12'h1; // @[JtagShifter.scala:109:54] wire [11:0] regs_15_lo = 12'h1; // @[JtagShifter.scala:109:54] wire [11:0] regs_16_lo = 12'h1; // @[JtagShifter.scala:109:54] wire [11:0] regs_17_lo = 12'h1; // @[JtagShifter.scala:109:54] wire [11:0] regs_18_lo = 12'h1; // @[JtagShifter.scala:109:54] wire [11:0] regs_19_lo = 12'h1; // @[JtagShifter.scala:109:54] wire [11:0] regs_20_lo = 12'h1; // @[JtagShifter.scala:109:54] wire [11:0] regs_21_lo = 12'h1; // @[JtagShifter.scala:109:54] wire [11:0] regs_22_lo = 12'h1; // @[JtagShifter.scala:109:54] wire [11:0] regs_23_lo = 12'h1; // @[JtagShifter.scala:109:54] wire [11:0] regs_24_lo = 12'h1; // @[JtagShifter.scala:109:54] wire [11:0] regs_25_lo = 12'h1; // @[JtagShifter.scala:109:54] wire [11:0] regs_26_lo = 12'h1; // @[JtagShifter.scala:109:54] wire [11:0] regs_27_lo = 12'h1; // @[JtagShifter.scala:109:54] wire [11:0] regs_28_lo = 12'h1; // @[JtagShifter.scala:109:54] wire [11:0] regs_29_lo = 12'h1; // @[JtagShifter.scala:109:54] wire [11:0] regs_30_lo = 12'h1; // @[JtagShifter.scala:109:54] wire [11:0] regs_31_lo = 12'h1; // @[JtagShifter.scala:109:54] wire io_chainOut_shift_0 = io_chainIn_shift_0; // @[JtagShifter.scala:89:7] wire io_chainOut_capture_0 = io_chainIn_capture_0; // @[JtagShifter.scala:89:7] wire io_capture_capture = io_chainIn_capture_0; // @[JtagShifter.scala:89:7] wire io_chainOut_update_0 = io_chainIn_update_0; // @[JtagShifter.scala:89:7] wire io_chainOut_data_0; // @[JtagShifter.scala:89:7] reg regs_0; // @[JtagShifter.scala:102:39] assign io_chainOut_data_0 = regs_0; // @[JtagShifter.scala:89:7, :102:39] reg regs_1; // @[JtagShifter.scala:102:39] reg regs_2; // @[JtagShifter.scala:102:39] reg regs_3; // @[JtagShifter.scala:102:39] reg regs_4; // @[JtagShifter.scala:102:39] reg regs_5; // @[JtagShifter.scala:102:39] reg regs_6; // @[JtagShifter.scala:102:39] reg regs_7; // @[JtagShifter.scala:102:39] reg regs_8; // @[JtagShifter.scala:102:39] reg regs_9; // @[JtagShifter.scala:102:39] reg regs_10; // @[JtagShifter.scala:102:39] reg regs_11; // @[JtagShifter.scala:102:39] reg regs_12; // @[JtagShifter.scala:102:39] reg regs_13; // @[JtagShifter.scala:102:39] reg regs_14; // @[JtagShifter.scala:102:39] reg regs_15; // @[JtagShifter.scala:102:39] reg regs_16; // @[JtagShifter.scala:102:39] reg regs_17; // @[JtagShifter.scala:102:39] reg regs_18; // @[JtagShifter.scala:102:39] reg regs_19; // @[JtagShifter.scala:102:39] reg regs_20; // @[JtagShifter.scala:102:39] reg regs_21; // @[JtagShifter.scala:102:39] reg regs_22; // @[JtagShifter.scala:102:39] reg regs_23; // @[JtagShifter.scala:102:39] reg regs_24; // @[JtagShifter.scala:102:39] reg regs_25; // @[JtagShifter.scala:102:39] reg regs_26; // @[JtagShifter.scala:102:39] reg regs_27; // @[JtagShifter.scala:102:39] reg regs_28; // @[JtagShifter.scala:102:39] reg regs_29; // @[JtagShifter.scala:102:39] reg regs_30; // @[JtagShifter.scala:102:39] reg regs_31; // @[JtagShifter.scala:102:39]
Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_204 : output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node rawIn_exp = bits(io.in, 31, 23) node _rawIn_isZero_T = bits(rawIn_exp, 8, 6) node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0)) node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7) node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3)) wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T) connect rawIn.isNaN, _rawIn_out_isNaN_T_1 node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0)) node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1) connect rawIn.isInf, _rawIn_out_isInf_T_2 connect rawIn.isZero, rawIn_isZero node _rawIn_out_sign_T = bits(io.in, 32, 32) connect rawIn.sign, _rawIn_out_sign_T node _rawIn_out_sExp_T = cvt(rawIn_exp) connect rawIn.sExp, _rawIn_out_sExp_T node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0)) node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T) node _rawIn_out_sig_T_2 = bits(io.in, 22, 0) node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2) connect rawIn.sig, _rawIn_out_sig_T_3 node _io_out_T = shl(io.in, 0) connect io.out, _io_out_T node _io_exceptionFlags_T = bits(rawIn.sig, 22, 22) node _io_exceptionFlags_T_1 = eq(_io_exceptionFlags_T, UInt<1>(0h0)) node _io_exceptionFlags_T_2 = and(rawIn.isNaN, _io_exceptionFlags_T_1) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, UInt<4>(0h0)) connect io.exceptionFlags, _io_exceptionFlags_T_3	module RecFNToRecFN_204( // @[RecFNToRecFN.scala:44:5] input [32:0] io_in, // @[RecFNToRecFN.scala:48:16] output [32:0] io_out // @[RecFNToRecFN.scala:48:16] ); wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5] wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16] wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16] wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35] wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54] wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5] wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5] wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35] wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}] wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46] assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54] assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w4_d3_i0_9 : input clock : Clock input reset : Reset output io : { flip d : UInt<4>, q : UInt<4>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_107 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q node _output_T_2 = asAsyncReset(reset) node _output_T_3 = bits(io.d, 1, 1) inst output_chain_1 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_108 connect output_chain_1.clock, clock connect output_chain_1.reset, _output_T_2 connect output_chain_1.io.d, _output_T_3 wire output_1 : UInt<1> connect output_1, output_chain_1.io.q node _output_T_4 = asAsyncReset(reset) node _output_T_5 = bits(io.d, 2, 2) inst output_chain_2 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_109 connect output_chain_2.clock, clock connect output_chain_2.reset, _output_T_4 connect output_chain_2.io.d, _output_T_5 wire output_2 : UInt<1> connect output_2, output_chain_2.io.q node _output_T_6 = asAsyncReset(reset) node _output_T_7 = bits(io.d, 3, 3) inst output_chain_3 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_110 connect output_chain_3.clock, clock connect output_chain_3.reset, _output_T_6 connect output_chain_3.io.d, _output_T_7 wire output_3 : UInt<1> connect output_3, output_chain_3.io.q node io_q_lo = cat(output_1, output_0) node io_q_hi = cat(output_3, output_2) node _io_q_T = cat(io_q_hi, io_q_lo) connect io.q, _io_q_T	module AsyncResetSynchronizerShiftReg_w4_d3_i0_9( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input [3:0] io_d, // @[ShiftReg.scala:36:14] output [3:0] io_q // @[ShiftReg.scala:36:14] ); wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21] wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14] wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7] wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_1; // @[ShiftReg.scala:48:24] wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_2; // @[ShiftReg.scala:48:24] wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_3; // @[ShiftReg.scala:48:24] wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14] wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14] assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14] assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_107 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_108 output_chain_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_2), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_3), // @[SynchronizerReg.scala:87:41] .io_q (output_1) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_109 output_chain_2 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_4), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_5), // @[SynchronizerReg.scala:87:41] .io_q (output_2) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_110 output_chain_3 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_6), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_7), // @[SynchronizerReg.scala:87:41] .io_q (output_3) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module RoundRawFNToRecFN_e8_s24_4 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_4 connect roundAnyRawFNToRecFN.io.invalidExc, io.invalidExc connect roundAnyRawFNToRecFN.io.infiniteExc, io.infiniteExc connect roundAnyRawFNToRecFN.io.in.sig, io.in.sig connect roundAnyRawFNToRecFN.io.in.sExp, io.in.sExp connect roundAnyRawFNToRecFN.io.in.sign, io.in.sign connect roundAnyRawFNToRecFN.io.in.isZero, io.in.isZero connect roundAnyRawFNToRecFN.io.in.isInf, io.in.isInf connect roundAnyRawFNToRecFN.io.in.isNaN, io.in.isNaN connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess connect io.out, roundAnyRawFNToRecFN.io.out connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags	module RoundRawFNToRecFN_e8_s24_4( // @[RoundAnyRawFNToRecFN.scala:295:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:299:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:299:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:299:16] input [2:0] io_roundingMode, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_detectTininess, // @[RoundAnyRawFNToRecFN.scala:299:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:299:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:299:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_detectTininess_0 = io_detectTininess; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_4 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala:310:15] .io_invalidExc (io_invalidExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isNaN (io_in_isNaN_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isInf (io_in_isInf_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isZero (io_in_isZero_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sign (io_in_sign_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sExp (io_in_sExp_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sig (io_in_sig_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_roundingMode (io_roundingMode_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_detectTininess (io_detectTininess_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags_0) ); // @[RoundAnyRawFNToRecFN.scala:310:15] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_277 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_517 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0	module AsyncResetSynchronizerShiftReg_w1_d3_i0_277( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] output io_q // @[ShiftReg.scala:36:14] ); wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_517 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLUART : input clock : Clock input reset : Reset output auto : { int_xing_out : { sync : UInt<1>[1]}, flip control_xing_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, io_out : { txd : UInt<1>, flip rxd : UInt<1>}} inst buffer of TLBuffer_a29d64s11k1z2u connect buffer.clock, clock connect buffer.reset, reset inst intsource of IntSyncCrossingSource_n1x1_5 connect intsource.clock, clock connect intsource.reset, reset wire ioNodeOut : { txd : UInt<1>, flip rxd : UInt<1>} invalidate ioNodeOut.rxd invalidate ioNodeOut.txd wire intnodeOut : UInt<1>[1] invalidate intnodeOut[0] wire controlNodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate controlNodeIn.d.bits.corrupt invalidate controlNodeIn.d.bits.data invalidate controlNodeIn.d.bits.denied invalidate controlNodeIn.d.bits.sink invalidate controlNodeIn.d.bits.source invalidate controlNodeIn.d.bits.size invalidate controlNodeIn.d.bits.param invalidate controlNodeIn.d.bits.opcode invalidate controlNodeIn.d.valid invalidate controlNodeIn.d.ready invalidate controlNodeIn.a.bits.corrupt invalidate controlNodeIn.a.bits.data invalidate controlNodeIn.a.bits.mask invalidate controlNodeIn.a.bits.address invalidate controlNodeIn.a.bits.source invalidate controlNodeIn.a.bits.size invalidate controlNodeIn.a.bits.param invalidate controlNodeIn.a.bits.opcode invalidate controlNodeIn.a.valid invalidate controlNodeIn.a.ready inst monitor of TLMonitor_60 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, controlNodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, controlNodeIn.d.bits.data connect monitor.io.in.d.bits.denied, controlNodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, controlNodeIn.d.bits.sink connect monitor.io.in.d.bits.source, controlNodeIn.d.bits.source connect monitor.io.in.d.bits.size, controlNodeIn.d.bits.size connect monitor.io.in.d.bits.param, controlNodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, controlNodeIn.d.bits.opcode connect monitor.io.in.d.valid, controlNodeIn.d.valid connect monitor.io.in.d.ready, controlNodeIn.d.ready connect monitor.io.in.a.bits.corrupt, controlNodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, controlNodeIn.a.bits.data connect monitor.io.in.a.bits.mask, controlNodeIn.a.bits.mask connect monitor.io.in.a.bits.address, controlNodeIn.a.bits.address connect monitor.io.in.a.bits.source, controlNodeIn.a.bits.source connect monitor.io.in.a.bits.size, controlNodeIn.a.bits.size connect monitor.io.in.a.bits.param, controlNodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, controlNodeIn.a.bits.opcode connect monitor.io.in.a.valid, controlNodeIn.a.valid connect monitor.io.in.a.ready, controlNodeIn.a.ready wire controlXingOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate controlXingOut.d.bits.corrupt invalidate controlXingOut.d.bits.data invalidate controlXingOut.d.bits.denied invalidate controlXingOut.d.bits.sink invalidate controlXingOut.d.bits.source invalidate controlXingOut.d.bits.size invalidate controlXingOut.d.bits.param invalidate controlXingOut.d.bits.opcode invalidate controlXingOut.d.valid invalidate controlXingOut.d.ready invalidate controlXingOut.a.bits.corrupt invalidate controlXingOut.a.bits.data invalidate controlXingOut.a.bits.mask invalidate controlXingOut.a.bits.address invalidate controlXingOut.a.bits.source invalidate controlXingOut.a.bits.size invalidate controlXingOut.a.bits.param invalidate controlXingOut.a.bits.opcode invalidate controlXingOut.a.valid invalidate controlXingOut.a.ready wire controlXingIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate controlXingIn.d.bits.corrupt invalidate controlXingIn.d.bits.data invalidate controlXingIn.d.bits.denied invalidate controlXingIn.d.bits.sink invalidate controlXingIn.d.bits.source invalidate controlXingIn.d.bits.size invalidate controlXingIn.d.bits.param invalidate controlXingIn.d.bits.opcode invalidate controlXingIn.d.valid invalidate controlXingIn.d.ready invalidate controlXingIn.a.bits.corrupt invalidate controlXingIn.a.bits.data invalidate controlXingIn.a.bits.mask invalidate controlXingIn.a.bits.address invalidate controlXingIn.a.bits.source invalidate controlXingIn.a.bits.size invalidate controlXingIn.a.bits.param invalidate controlXingIn.a.bits.opcode invalidate controlXingIn.a.valid invalidate controlXingIn.a.ready connect controlXingOut, controlXingIn wire intXingOut : { sync : UInt<1>[1]} invalidate intXingOut.sync[0] wire intXingIn : { sync : UInt<1>[1]} invalidate intXingIn.sync[0] connect intXingOut, intXingIn connect intsource.auto.in[0], intnodeOut[0] connect buffer.auto.out.d, controlNodeIn.d connect controlNodeIn.a.bits, buffer.auto.out.a.bits connect controlNodeIn.a.valid, buffer.auto.out.a.valid connect buffer.auto.out.a.ready, controlNodeIn.a.ready connect buffer.auto.in, controlXingOut connect intXingIn, intsource.auto.out connect auto.io_out, ioNodeOut connect controlXingIn, auto.control_xing_in connect auto.int_xing_out, intXingOut inst txm of UARTTx connect txm.clock, clock connect txm.reset, reset inst txq of Queue8_UInt8 connect txq.clock, clock connect txq.reset, reset inst rxm of UARTRx connect rxm.clock, clock connect rxm.reset, reset inst rxq of Queue8_UInt8_1 connect rxq.clock, clock connect rxq.reset, reset regreset div : UInt<16>, clock, reset, UInt<16>(0h10f4) regreset txen : UInt<1>, clock, reset, UInt<1>(0h0) regreset rxen : UInt<1>, clock, reset, UInt<1>(0h0) regreset enwire4 : UInt<1>, clock, reset, UInt<1>(0h0) regreset invpol : UInt<1>, clock, reset, UInt<1>(0h0) regreset enparity : UInt<1>, clock, reset, UInt<1>(0h0) regreset parity : UInt<1>, clock, reset, UInt<1>(0h0) regreset errorparity : UInt<1>, clock, reset, UInt<1>(0h0) regreset errie : UInt<1>, clock, reset, UInt<1>(0h0) regreset txwm : UInt<4>, clock, reset, UInt<4>(0h0) regreset rxwm : UInt<4>, clock, reset, UInt<4>(0h0) regreset nstop : UInt<1>, clock, reset, UInt<1>(0h0) regreset data8or9 : UInt<1>, clock, reset, UInt<1>(0h1) connect txm.io.en, txen connect txm.io.in, txq.io.deq connect txm.io.div, div connect txm.io.nstop, nstop connect ioNodeOut.txd, txm.io.out connect rxm.io.en, rxen connect rxm.io.in, ioNodeOut.rxd connect rxq.io.enq.valid, rxm.io.out.valid connect rxq.io.enq.bits, rxm.io.out.bits connect rxm.io.div, div node _tx_busy_T = orr(txq.io.count) node _tx_busy_T_1 = or(txm.io.tx_busy, _tx_busy_T) node tx_busy = and(_tx_busy_T_1, txen) wire _ie_WIRE : { rxwm : UInt<1>, txwm : UInt<1>} connect _ie_WIRE.txwm, UInt<1>(0h0) connect _ie_WIRE.rxwm, UInt<1>(0h0) regreset ie : { rxwm : UInt<1>, txwm : UInt<1>}, clock, reset, _ie_WIRE wire ip : { rxwm : UInt<1>, txwm : UInt<1>} node _ip_txwm_T = lt(txq.io.count, txwm) connect ip.txwm, _ip_txwm_T node _ip_rxwm_T = gt(rxq.io.count, rxwm) connect ip.rxwm, _ip_rxwm_T node _intnodeOut_0_T = and(ip.txwm, ie.txwm) node _intnodeOut_0_T_1 = and(ip.rxwm, ie.rxwm) node _intnodeOut_0_T_2 = or(_intnodeOut_0_T, _intnodeOut_0_T_1) connect intnodeOut[0], _intnodeOut_0_T_2 wire quash : UInt<1> node _T = eq(txq.io.enq.ready, UInt<1>(0h0)) node _T_1 = eq(rxq.io.deq.valid, UInt<1>(0h0)) wire in : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}} node _in_bits_read_T = eq(controlNodeIn.a.bits.opcode, UInt<3>(0h4)) connect in.bits.read, _in_bits_read_T node _in_bits_index_T = shr(controlNodeIn.a.bits.address, 3) connect in.bits.index, _in_bits_index_T connect in.bits.data, controlNodeIn.a.bits.data connect in.bits.mask, controlNodeIn.a.bits.mask connect in.bits.extra.tlrr_extra.source, controlNodeIn.a.bits.source connect in.bits.extra.tlrr_extra.size, controlNodeIn.a.bits.size wire out : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, data : UInt<64>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}} wire out_front : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}} connect out_front.bits, in.bits node out_maskMatch = not(UInt<9>(0h3)) node out_findex = and(out_front.bits.index, out_maskMatch) node out_bindex = and(out_front.bits.index, out_maskMatch) node _out_T = eq(out_findex, UInt<9>(0h0)) node _out_T_1 = eq(out_bindex, UInt<9>(0h0)) node _out_T_2 = eq(out_findex, UInt<9>(0h0)) node _out_T_3 = eq(out_bindex, UInt<9>(0h0)) node _out_T_4 = eq(out_findex, UInt<9>(0h0)) node _out_T_5 = eq(out_bindex, UInt<9>(0h0)) node _out_T_6 = eq(out_findex, UInt<9>(0h0)) node _out_T_7 = eq(out_bindex, UInt<9>(0h0)) wire out_rivalid : UInt<1>[16] wire out_wivalid : UInt<1>[16] wire out_roready : UInt<1>[16] wire out_woready : UInt<1>[16] node _out_frontMask_T = bits(out_front.bits.mask, 0, 0) node _out_frontMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_frontMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_frontMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_frontMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_frontMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_frontMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_frontMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_frontMask_T_8 = mux(_out_frontMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_9 = mux(_out_frontMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_10 = mux(_out_frontMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_11 = mux(_out_frontMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_12 = mux(_out_frontMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_13 = mux(_out_frontMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_14 = mux(_out_frontMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_15 = mux(_out_frontMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_frontMask_lo_lo = cat(_out_frontMask_T_9, _out_frontMask_T_8) node out_frontMask_lo_hi = cat(_out_frontMask_T_11, _out_frontMask_T_10) node out_frontMask_lo = cat(out_frontMask_lo_hi, out_frontMask_lo_lo) node out_frontMask_hi_lo = cat(_out_frontMask_T_13, _out_frontMask_T_12) node out_frontMask_hi_hi = cat(_out_frontMask_T_15, _out_frontMask_T_14) node out_frontMask_hi = cat(out_frontMask_hi_hi, out_frontMask_hi_lo) node out_frontMask = cat(out_frontMask_hi, out_frontMask_lo) node _out_backMask_T = bits(out_front.bits.mask, 0, 0) node _out_backMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_backMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_backMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_backMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_backMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_backMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_backMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_backMask_T_8 = mux(_out_backMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_9 = mux(_out_backMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_10 = mux(_out_backMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_11 = mux(_out_backMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_12 = mux(_out_backMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_13 = mux(_out_backMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_14 = mux(_out_backMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_15 = mux(_out_backMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_backMask_lo_lo = cat(_out_backMask_T_9, _out_backMask_T_8) node out_backMask_lo_hi = cat(_out_backMask_T_11, _out_backMask_T_10) node out_backMask_lo = cat(out_backMask_lo_hi, out_backMask_lo_lo) node out_backMask_hi_lo = cat(_out_backMask_T_13, _out_backMask_T_12) node out_backMask_hi_hi = cat(_out_backMask_T_15, _out_backMask_T_14) node out_backMask_hi = cat(out_backMask_hi_hi, out_backMask_hi_lo) node out_backMask = cat(out_backMask_hi, out_backMask_lo) node _out_rimask_T = bits(out_frontMask, 7, 0) node out_rimask = orr(_out_rimask_T) node _out_wimask_T = bits(out_frontMask, 7, 0) node out_wimask = andr(_out_wimask_T) node _out_romask_T = bits(out_backMask, 7, 0) node out_romask = orr(_out_romask_T) node _out_womask_T = bits(out_backMask, 7, 0) node out_womask = andr(_out_womask_T) node out_f_rivalid = and(out_rivalid[0], out_rimask) node out_f_roready = and(out_roready[0], out_romask) node out_f_wivalid = and(out_wivalid[0], out_wimask) node out_f_woready = and(out_woready[0], out_womask) node _out_T_8 = bits(out_front.bits.data, 7, 0) node _out_txq_io_enq_valid_T = eq(quash, UInt<1>(0h0)) node _out_txq_io_enq_valid_T_1 = and(out_f_woready, _out_txq_io_enq_valid_T) connect txq.io.enq.valid, _out_txq_io_enq_valid_T_1 connect txq.io.enq.bits, _out_T_8 node _out_T_9 = and(out_f_wivalid, UInt<1>(0h1)) node _out_T_10 = and(UInt<1>(0h1), out_f_woready) node _out_T_11 = eq(out_rimask, UInt<1>(0h0)) node _out_T_12 = eq(out_wimask, UInt<1>(0h0)) node _out_T_13 = eq(out_romask, UInt<1>(0h0)) node _out_T_14 = eq(out_womask, UInt<1>(0h0)) node _out_T_15 = or(UInt<1>(0h0), UInt<8>(0h0)) node _out_T_16 = bits(_out_T_15, 7, 0) node _out_rimask_T_1 = bits(out_frontMask, 30, 8) node out_rimask_1 = orr(_out_rimask_T_1) node _out_wimask_T_1 = bits(out_frontMask, 30, 8) node out_wimask_1 = andr(_out_wimask_T_1) node _out_romask_T_1 = bits(out_backMask, 30, 8) node out_romask_1 = orr(_out_romask_T_1) node _out_womask_T_1 = bits(out_backMask, 30, 8) node out_womask_1 = andr(_out_womask_T_1) node out_f_rivalid_1 = and(out_rivalid[1], out_rimask_1) node out_f_roready_1 = and(out_roready[1], out_romask_1) node out_f_wivalid_1 = and(out_wivalid[1], out_wimask_1) node out_f_woready_1 = and(out_woready[1], out_womask_1) node _out_T_17 = bits(out_front.bits.data, 30, 8) node _out_T_18 = and(out_f_rivalid_1, UInt<1>(0h1)) node _out_T_19 = and(UInt<1>(0h1), out_f_roready_1) node _out_T_20 = eq(out_rimask_1, UInt<1>(0h0)) node _out_T_21 = eq(out_wimask_1, UInt<1>(0h0)) node _out_T_22 = eq(out_romask_1, UInt<1>(0h0)) node _out_T_23 = eq(out_womask_1, UInt<1>(0h0)) node _out_prepend_T = or(_out_T_16, UInt<8>(0h0)) node out_prepend = cat(UInt<1>(0h0), _out_prepend_T) node _out_T_24 = or(out_prepend, UInt<31>(0h0)) node _out_T_25 = bits(_out_T_24, 30, 0) node _out_rimask_T_2 = bits(out_frontMask, 31, 31) node out_rimask_2 = orr(_out_rimask_T_2) node _out_wimask_T_2 = bits(out_frontMask, 31, 31) node out_wimask_2 = andr(_out_wimask_T_2) node _out_romask_T_2 = bits(out_backMask, 31, 31) node out_romask_2 = orr(_out_romask_T_2) node _out_womask_T_2 = bits(out_backMask, 31, 31) node out_womask_2 = andr(_out_womask_T_2) node out_f_rivalid_2 = and(out_rivalid[2], out_rimask_2) node out_f_roready_2 = and(out_roready[2], out_romask_2) node out_f_wivalid_2 = and(out_wivalid[2], out_wimask_2) node out_f_woready_2 = and(out_woready[2], out_womask_2) node _out_T_26 = bits(out_front.bits.data, 31, 31) node _out_quash_T = bits(_out_T_26, 0, 0) node _out_quash_T_1 = and(out_f_woready_2, _out_quash_T) connect quash, _out_quash_T_1 node _out_T_27 = and(out_f_rivalid_2, UInt<1>(0h1)) node _out_T_28 = and(UInt<1>(0h1), out_f_roready_2) node _out_T_29 = eq(out_rimask_2, UInt<1>(0h0)) node _out_T_30 = eq(out_wimask_2, UInt<1>(0h0)) node _out_T_31 = eq(out_romask_2, UInt<1>(0h0)) node _out_T_32 = eq(out_womask_2, UInt<1>(0h0)) node _out_prepend_T_1 = or(_out_T_25, UInt<31>(0h0)) node out_prepend_1 = cat(_T, _out_prepend_T_1) node _out_T_33 = or(out_prepend_1, UInt<32>(0h0)) node _out_T_34 = bits(_out_T_33, 31, 0) node _out_rimask_T_3 = bits(out_frontMask, 39, 32) node out_rimask_3 = orr(_out_rimask_T_3) node _out_wimask_T_3 = bits(out_frontMask, 39, 32) node out_wimask_3 = andr(_out_wimask_T_3) node _out_romask_T_3 = bits(out_backMask, 39, 32) node out_romask_3 = orr(_out_romask_T_3) node _out_womask_T_3 = bits(out_backMask, 39, 32) node out_womask_3 = andr(_out_womask_T_3) node out_f_rivalid_3 = and(out_rivalid[3], out_rimask_3) node out_f_roready_3 = and(out_roready[3], out_romask_3) node out_f_wivalid_3 = and(out_wivalid[3], out_wimask_3) node out_f_woready_3 = and(out_woready[3], out_womask_3) connect rxq.io.deq.ready, out_f_roready_3 node _out_T_35 = bits(out_front.bits.data, 39, 32) node _out_T_36 = and(out_f_rivalid_3, UInt<1>(0h1)) node _out_T_37 = and(UInt<1>(0h1), out_f_roready_3) node _out_T_38 = eq(out_rimask_3, UInt<1>(0h0)) node _out_T_39 = eq(out_wimask_3, UInt<1>(0h0)) node _out_T_40 = eq(out_romask_3, UInt<1>(0h0)) node _out_T_41 = eq(out_womask_3, UInt<1>(0h0)) node _out_prepend_T_2 = or(_out_T_34, UInt<32>(0h0)) node out_prepend_2 = cat(rxq.io.deq.bits, _out_prepend_T_2) node _out_T_42 = or(out_prepend_2, UInt<40>(0h0)) node _out_T_43 = bits(_out_T_42, 39, 0) node _out_rimask_T_4 = bits(out_frontMask, 62, 40) node out_rimask_4 = orr(_out_rimask_T_4) node _out_wimask_T_4 = bits(out_frontMask, 62, 40) node out_wimask_4 = andr(_out_wimask_T_4) node _out_romask_T_4 = bits(out_backMask, 62, 40) node out_romask_4 = orr(_out_romask_T_4) node _out_womask_T_4 = bits(out_backMask, 62, 40) node out_womask_4 = andr(_out_womask_T_4) node out_f_rivalid_4 = and(out_rivalid[4], out_rimask_4) node out_f_roready_4 = and(out_roready[4], out_romask_4) node out_f_wivalid_4 = and(out_wivalid[4], out_wimask_4) node out_f_woready_4 = and(out_woready[4], out_womask_4) node _out_T_44 = bits(out_front.bits.data, 62, 40) node _out_T_45 = and(out_f_rivalid_4, UInt<1>(0h1)) node _out_T_46 = and(UInt<1>(0h1), out_f_roready_4) node _out_T_47 = eq(out_rimask_4, UInt<1>(0h0)) node _out_T_48 = eq(out_wimask_4, UInt<1>(0h0)) node _out_T_49 = eq(out_romask_4, UInt<1>(0h0)) node _out_T_50 = eq(out_womask_4, UInt<1>(0h0)) node _out_prepend_T_3 = or(_out_T_43, UInt<40>(0h0)) node out_prepend_3 = cat(UInt<1>(0h0), _out_prepend_T_3) node _out_T_51 = or(out_prepend_3, UInt<63>(0h0)) node _out_T_52 = bits(_out_T_51, 62, 0) node _out_rimask_T_5 = bits(out_frontMask, 63, 63) node out_rimask_5 = orr(_out_rimask_T_5) node _out_wimask_T_5 = bits(out_frontMask, 63, 63) node out_wimask_5 = andr(_out_wimask_T_5) node _out_romask_T_5 = bits(out_backMask, 63, 63) node out_romask_5 = orr(_out_romask_T_5) node _out_womask_T_5 = bits(out_backMask, 63, 63) node out_womask_5 = andr(_out_womask_T_5) node out_f_rivalid_5 = and(out_rivalid[5], out_rimask_5) node out_f_roready_5 = and(out_roready[5], out_romask_5) node out_f_wivalid_5 = and(out_wivalid[5], out_wimask_5) node out_f_woready_5 = and(out_woready[5], out_womask_5) node _out_T_53 = bits(out_front.bits.data, 63, 63) node _out_T_54 = and(out_f_rivalid_5, UInt<1>(0h1)) node _out_T_55 = and(UInt<1>(0h1), out_f_roready_5) node _out_T_56 = eq(out_rimask_5, UInt<1>(0h0)) node _out_T_57 = eq(out_wimask_5, UInt<1>(0h0)) node _out_T_58 = eq(out_romask_5, UInt<1>(0h0)) node _out_T_59 = eq(out_womask_5, UInt<1>(0h0)) node _out_prepend_T_4 = or(_out_T_52, UInt<63>(0h0)) node out_prepend_4 = cat(_T_1, _out_prepend_T_4) node _out_T_60 = or(out_prepend_4, UInt<64>(0h0)) node _out_T_61 = bits(_out_T_60, 63, 0) node _out_rimask_T_6 = bits(out_frontMask, 0, 0) node out_rimask_6 = orr(_out_rimask_T_6) node _out_wimask_T_6 = bits(out_frontMask, 0, 0) node out_wimask_6 = andr(_out_wimask_T_6) node _out_romask_T_6 = bits(out_backMask, 0, 0) node out_romask_6 = orr(_out_romask_T_6) node _out_womask_T_6 = bits(out_backMask, 0, 0) node out_womask_6 = andr(_out_womask_T_6) node out_f_rivalid_6 = and(out_rivalid[6], out_rimask_6) node out_f_roready_6 = and(out_roready[6], out_romask_6) node out_f_wivalid_6 = and(out_wivalid[6], out_wimask_6) node out_f_woready_6 = and(out_woready[6], out_womask_6) node _out_T_62 = bits(out_front.bits.data, 0, 0) when out_f_woready_6 : connect txen, _out_T_62 node _out_T_63 = and(out_f_rivalid_6, UInt<1>(0h1)) node _out_T_64 = and(UInt<1>(0h1), out_f_roready_6) node _out_T_65 = and(out_f_wivalid_6, UInt<1>(0h1)) node _out_T_66 = and(UInt<1>(0h1), out_f_woready_6) node _out_T_67 = eq(out_rimask_6, UInt<1>(0h0)) node _out_T_68 = eq(out_wimask_6, UInt<1>(0h0)) node _out_T_69 = eq(out_romask_6, UInt<1>(0h0)) node _out_T_70 = eq(out_womask_6, UInt<1>(0h0)) node _out_T_71 = or(txen, UInt<1>(0h0)) node _out_T_72 = bits(_out_T_71, 0, 0) node _out_rimask_T_7 = bits(out_frontMask, 1, 1) node out_rimask_7 = orr(_out_rimask_T_7) node _out_wimask_T_7 = bits(out_frontMask, 1, 1) node out_wimask_7 = andr(_out_wimask_T_7) node _out_romask_T_7 = bits(out_backMask, 1, 1) node out_romask_7 = orr(_out_romask_T_7) node _out_womask_T_7 = bits(out_backMask, 1, 1) node out_womask_7 = andr(_out_womask_T_7) node out_f_rivalid_7 = and(out_rivalid[7], out_rimask_7) node out_f_roready_7 = and(out_roready[7], out_romask_7) node out_f_wivalid_7 = and(out_wivalid[7], out_wimask_7) node out_f_woready_7 = and(out_woready[7], out_womask_7) node _out_T_73 = bits(out_front.bits.data, 1, 1) when out_f_woready_7 : connect nstop, _out_T_73 node _out_T_74 = and(out_f_rivalid_7, UInt<1>(0h1)) node _out_T_75 = and(UInt<1>(0h1), out_f_roready_7) node _out_T_76 = and(out_f_wivalid_7, UInt<1>(0h1)) node _out_T_77 = and(UInt<1>(0h1), out_f_woready_7) node _out_T_78 = eq(out_rimask_7, UInt<1>(0h0)) node _out_T_79 = eq(out_wimask_7, UInt<1>(0h0)) node _out_T_80 = eq(out_romask_7, UInt<1>(0h0)) node _out_T_81 = eq(out_womask_7, UInt<1>(0h0)) node _out_prepend_T_5 = or(_out_T_72, UInt<1>(0h0)) node out_prepend_5 = cat(nstop, _out_prepend_T_5) node _out_T_82 = or(out_prepend_5, UInt<2>(0h0)) node _out_T_83 = bits(_out_T_82, 1, 0) node _out_rimask_T_8 = bits(out_frontMask, 19, 16) node out_rimask_8 = orr(_out_rimask_T_8) node _out_wimask_T_8 = bits(out_frontMask, 19, 16) node out_wimask_8 = andr(_out_wimask_T_8) node _out_romask_T_8 = bits(out_backMask, 19, 16) node out_romask_8 = orr(_out_romask_T_8) node _out_womask_T_8 = bits(out_backMask, 19, 16) node out_womask_8 = andr(_out_womask_T_8) node out_f_rivalid_8 = and(out_rivalid[8], out_rimask_8) node out_f_roready_8 = and(out_roready[8], out_romask_8) node out_f_wivalid_8 = and(out_wivalid[8], out_wimask_8) node out_f_woready_8 = and(out_woready[8], out_womask_8) node _out_T_84 = bits(out_front.bits.data, 19, 16) when out_f_woready_8 : connect txwm, _out_T_84 node _out_T_85 = and(out_f_rivalid_8, UInt<1>(0h1)) node _out_T_86 = and(UInt<1>(0h1), out_f_roready_8) node _out_T_87 = and(out_f_wivalid_8, UInt<1>(0h1)) node _out_T_88 = and(UInt<1>(0h1), out_f_woready_8) node _out_T_89 = eq(out_rimask_8, UInt<1>(0h0)) node _out_T_90 = eq(out_wimask_8, UInt<1>(0h0)) node _out_T_91 = eq(out_romask_8, UInt<1>(0h0)) node _out_T_92 = eq(out_womask_8, UInt<1>(0h0)) node _out_prepend_T_6 = or(_out_T_83, UInt<16>(0h0)) node out_prepend_6 = cat(txwm, _out_prepend_T_6) node _out_T_93 = or(out_prepend_6, UInt<20>(0h0)) node _out_T_94 = bits(_out_T_93, 19, 0) node _out_rimask_T_9 = bits(out_frontMask, 32, 32) node out_rimask_9 = orr(_out_rimask_T_9) node _out_wimask_T_9 = bits(out_frontMask, 32, 32) node out_wimask_9 = andr(_out_wimask_T_9) node _out_romask_T_9 = bits(out_backMask, 32, 32) node out_romask_9 = orr(_out_romask_T_9) node _out_womask_T_9 = bits(out_backMask, 32, 32) node out_womask_9 = andr(_out_womask_T_9) node out_f_rivalid_9 = and(out_rivalid[9], out_rimask_9) node out_f_roready_9 = and(out_roready[9], out_romask_9) node out_f_wivalid_9 = and(out_wivalid[9], out_wimask_9) node out_f_woready_9 = and(out_woready[9], out_womask_9) node _out_T_95 = bits(out_front.bits.data, 32, 32) when out_f_woready_9 : connect rxen, _out_T_95 node _out_T_96 = and(out_f_rivalid_9, UInt<1>(0h1)) node _out_T_97 = and(UInt<1>(0h1), out_f_roready_9) node _out_T_98 = and(out_f_wivalid_9, UInt<1>(0h1)) node _out_T_99 = and(UInt<1>(0h1), out_f_woready_9) node _out_T_100 = eq(out_rimask_9, UInt<1>(0h0)) node _out_T_101 = eq(out_wimask_9, UInt<1>(0h0)) node _out_T_102 = eq(out_romask_9, UInt<1>(0h0)) node _out_T_103 = eq(out_womask_9, UInt<1>(0h0)) node _out_prepend_T_7 = or(_out_T_94, UInt<32>(0h0)) node out_prepend_7 = cat(rxen, _out_prepend_T_7) node _out_T_104 = or(out_prepend_7, UInt<33>(0h0)) node _out_T_105 = bits(_out_T_104, 32, 0) node _out_rimask_T_10 = bits(out_frontMask, 51, 48) node out_rimask_10 = orr(_out_rimask_T_10) node _out_wimask_T_10 = bits(out_frontMask, 51, 48) node out_wimask_10 = andr(_out_wimask_T_10) node _out_romask_T_10 = bits(out_backMask, 51, 48) node out_romask_10 = orr(_out_romask_T_10) node _out_womask_T_10 = bits(out_backMask, 51, 48) node out_womask_10 = andr(_out_womask_T_10) node out_f_rivalid_10 = and(out_rivalid[10], out_rimask_10) node out_f_roready_10 = and(out_roready[10], out_romask_10) node out_f_wivalid_10 = and(out_wivalid[10], out_wimask_10) node out_f_woready_10 = and(out_woready[10], out_womask_10) node _out_T_106 = bits(out_front.bits.data, 51, 48) when out_f_woready_10 : connect rxwm, _out_T_106 node _out_T_107 = and(out_f_rivalid_10, UInt<1>(0h1)) node _out_T_108 = and(UInt<1>(0h1), out_f_roready_10) node _out_T_109 = and(out_f_wivalid_10, UInt<1>(0h1)) node _out_T_110 = and(UInt<1>(0h1), out_f_woready_10) node _out_T_111 = eq(out_rimask_10, UInt<1>(0h0)) node _out_T_112 = eq(out_wimask_10, UInt<1>(0h0)) node _out_T_113 = eq(out_romask_10, UInt<1>(0h0)) node _out_T_114 = eq(out_womask_10, UInt<1>(0h0)) node _out_prepend_T_8 = or(_out_T_105, UInt<48>(0h0)) node out_prepend_8 = cat(rxwm, _out_prepend_T_8) node _out_T_115 = or(out_prepend_8, UInt<52>(0h0)) node _out_T_116 = bits(_out_T_115, 51, 0) node _out_rimask_T_11 = bits(out_frontMask, 0, 0) node out_rimask_11 = orr(_out_rimask_T_11) node _out_wimask_T_11 = bits(out_frontMask, 0, 0) node out_wimask_11 = andr(_out_wimask_T_11) node _out_romask_T_11 = bits(out_backMask, 0, 0) node out_romask_11 = orr(_out_romask_T_11) node _out_womask_T_11 = bits(out_backMask, 0, 0) node out_womask_11 = andr(_out_womask_T_11) node out_f_rivalid_11 = and(out_rivalid[11], out_rimask_11) node out_f_roready_11 = and(out_roready[11], out_romask_11) node out_f_wivalid_11 = and(out_wivalid[11], out_wimask_11) node out_f_woready_11 = and(out_woready[11], out_womask_11) node _out_T_117 = bits(out_front.bits.data, 0, 0) when out_f_woready_11 : connect ie.txwm, _out_T_117 node _out_T_118 = and(out_f_rivalid_11, UInt<1>(0h1)) node _out_T_119 = and(UInt<1>(0h1), out_f_roready_11) node _out_T_120 = and(out_f_wivalid_11, UInt<1>(0h1)) node _out_T_121 = and(UInt<1>(0h1), out_f_woready_11) node _out_T_122 = eq(out_rimask_11, UInt<1>(0h0)) node _out_T_123 = eq(out_wimask_11, UInt<1>(0h0)) node _out_T_124 = eq(out_romask_11, UInt<1>(0h0)) node _out_T_125 = eq(out_womask_11, UInt<1>(0h0)) node _out_T_126 = or(ie.txwm, UInt<1>(0h0)) node _out_T_127 = bits(_out_T_126, 0, 0) node _out_rimask_T_12 = bits(out_frontMask, 1, 1) node out_rimask_12 = orr(_out_rimask_T_12) node _out_wimask_T_12 = bits(out_frontMask, 1, 1) node out_wimask_12 = andr(_out_wimask_T_12) node _out_romask_T_12 = bits(out_backMask, 1, 1) node out_romask_12 = orr(_out_romask_T_12) node _out_womask_T_12 = bits(out_backMask, 1, 1) node out_womask_12 = andr(_out_womask_T_12) node out_f_rivalid_12 = and(out_rivalid[12], out_rimask_12) node out_f_roready_12 = and(out_roready[12], out_romask_12) node out_f_wivalid_12 = and(out_wivalid[12], out_wimask_12) node out_f_woready_12 = and(out_woready[12], out_womask_12) node _out_T_128 = bits(out_front.bits.data, 1, 1) when out_f_woready_12 : connect ie.rxwm, _out_T_128 node _out_T_129 = and(out_f_rivalid_12, UInt<1>(0h1)) node _out_T_130 = and(UInt<1>(0h1), out_f_roready_12) node _out_T_131 = and(out_f_wivalid_12, UInt<1>(0h1)) node _out_T_132 = and(UInt<1>(0h1), out_f_woready_12) node _out_T_133 = eq(out_rimask_12, UInt<1>(0h0)) node _out_T_134 = eq(out_wimask_12, UInt<1>(0h0)) node _out_T_135 = eq(out_romask_12, UInt<1>(0h0)) node _out_T_136 = eq(out_womask_12, UInt<1>(0h0)) node _out_prepend_T_9 = or(_out_T_127, UInt<1>(0h0)) node out_prepend_9 = cat(ie.rxwm, _out_prepend_T_9) node _out_T_137 = or(out_prepend_9, UInt<2>(0h0)) node _out_T_138 = bits(_out_T_137, 1, 0) node _out_rimask_T_13 = bits(out_frontMask, 32, 32) node out_rimask_13 = orr(_out_rimask_T_13) node _out_wimask_T_13 = bits(out_frontMask, 32, 32) node out_wimask_13 = andr(_out_wimask_T_13) node _out_romask_T_13 = bits(out_backMask, 32, 32) node out_romask_13 = orr(_out_romask_T_13) node _out_womask_T_13 = bits(out_backMask, 32, 32) node out_womask_13 = andr(_out_womask_T_13) node out_f_rivalid_13 = and(out_rivalid[13], out_rimask_13) node out_f_roready_13 = and(out_roready[13], out_romask_13) node out_f_wivalid_13 = and(out_wivalid[13], out_wimask_13) node out_f_woready_13 = and(out_woready[13], out_womask_13) node _out_T_139 = bits(out_front.bits.data, 32, 32) node _out_T_140 = and(out_f_rivalid_13, UInt<1>(0h1)) node _out_T_141 = and(UInt<1>(0h1), out_f_roready_13) node _out_T_142 = eq(out_rimask_13, UInt<1>(0h0)) node _out_T_143 = eq(out_wimask_13, UInt<1>(0h0)) node _out_T_144 = eq(out_romask_13, UInt<1>(0h0)) node _out_T_145 = eq(out_womask_13, UInt<1>(0h0)) node _out_prepend_T_10 = or(_out_T_138, UInt<32>(0h0)) node out_prepend_10 = cat(ip.txwm, _out_prepend_T_10) node _out_T_146 = or(out_prepend_10, UInt<33>(0h0)) node _out_T_147 = bits(_out_T_146, 32, 0) node _out_rimask_T_14 = bits(out_frontMask, 33, 33) node out_rimask_14 = orr(_out_rimask_T_14) node _out_wimask_T_14 = bits(out_frontMask, 33, 33) node out_wimask_14 = andr(_out_wimask_T_14) node _out_romask_T_14 = bits(out_backMask, 33, 33) node out_romask_14 = orr(_out_romask_T_14) node _out_womask_T_14 = bits(out_backMask, 33, 33) node out_womask_14 = andr(_out_womask_T_14) node out_f_rivalid_14 = and(out_rivalid[14], out_rimask_14) node out_f_roready_14 = and(out_roready[14], out_romask_14) node out_f_wivalid_14 = and(out_wivalid[14], out_wimask_14) node out_f_woready_14 = and(out_woready[14], out_womask_14) node _out_T_148 = bits(out_front.bits.data, 33, 33) node _out_T_149 = and(out_f_rivalid_14, UInt<1>(0h1)) node _out_T_150 = and(UInt<1>(0h1), out_f_roready_14) node _out_T_151 = eq(out_rimask_14, UInt<1>(0h0)) node _out_T_152 = eq(out_wimask_14, UInt<1>(0h0)) node _out_T_153 = eq(out_romask_14, UInt<1>(0h0)) node _out_T_154 = eq(out_womask_14, UInt<1>(0h0)) node _out_prepend_T_11 = or(_out_T_147, UInt<33>(0h0)) node out_prepend_11 = cat(ip.rxwm, _out_prepend_T_11) node _out_T_155 = or(out_prepend_11, UInt<34>(0h0)) node _out_T_156 = bits(_out_T_155, 33, 0) node _out_rimask_T_15 = bits(out_frontMask, 15, 0) node out_rimask_15 = orr(_out_rimask_T_15) node _out_wimask_T_15 = bits(out_frontMask, 15, 0) node out_wimask_15 = andr(_out_wimask_T_15) node _out_romask_T_15 = bits(out_backMask, 15, 0) node out_romask_15 = orr(_out_romask_T_15) node _out_womask_T_15 = bits(out_backMask, 15, 0) node out_womask_15 = andr(_out_womask_T_15) node out_f_rivalid_15 = and(out_rivalid[15], out_rimask_15) node out_f_roready_15 = and(out_roready[15], out_romask_15) node out_f_wivalid_15 = and(out_wivalid[15], out_wimask_15) node out_f_woready_15 = and(out_woready[15], out_womask_15) node _out_T_157 = bits(out_front.bits.data, 15, 0) when out_f_woready_15 : connect div, _out_T_157 node _out_T_158 = and(out_f_rivalid_15, UInt<1>(0h1)) node _out_T_159 = and(UInt<1>(0h1), out_f_roready_15) node _out_T_160 = and(out_f_wivalid_15, UInt<1>(0h1)) node _out_T_161 = and(UInt<1>(0h1), out_f_woready_15) node _out_T_162 = eq(out_rimask_15, UInt<1>(0h0)) node _out_T_163 = eq(out_wimask_15, UInt<1>(0h0)) node _out_T_164 = eq(out_romask_15, UInt<1>(0h0)) node _out_T_165 = eq(out_womask_15, UInt<1>(0h0)) node _out_T_166 = or(div, UInt<16>(0h0)) node _out_T_167 = bits(_out_T_166, 15, 0) node _out_iindex_T = bits(out_front.bits.index, 0, 0) node _out_iindex_T_1 = bits(out_front.bits.index, 1, 1) node _out_iindex_T_2 = bits(out_front.bits.index, 2, 2) node _out_iindex_T_3 = bits(out_front.bits.index, 3, 3) node _out_iindex_T_4 = bits(out_front.bits.index, 4, 4) node _out_iindex_T_5 = bits(out_front.bits.index, 5, 5) node _out_iindex_T_6 = bits(out_front.bits.index, 6, 6) node _out_iindex_T_7 = bits(out_front.bits.index, 7, 7) node _out_iindex_T_8 = bits(out_front.bits.index, 8, 8) node out_iindex = cat(_out_iindex_T_1, _out_iindex_T) node _out_oindex_T = bits(out_front.bits.index, 0, 0) node _out_oindex_T_1 = bits(out_front.bits.index, 1, 1) node _out_oindex_T_2 = bits(out_front.bits.index, 2, 2) node _out_oindex_T_3 = bits(out_front.bits.index, 3, 3) node _out_oindex_T_4 = bits(out_front.bits.index, 4, 4) node _out_oindex_T_5 = bits(out_front.bits.index, 5, 5) node _out_oindex_T_6 = bits(out_front.bits.index, 6, 6) node _out_oindex_T_7 = bits(out_front.bits.index, 7, 7) node _out_oindex_T_8 = bits(out_front.bits.index, 8, 8) node out_oindex = cat(_out_oindex_T_1, _out_oindex_T) node _out_frontSel_T = dshl(UInt<1>(0h1), out_iindex) node out_frontSel_0 = bits(_out_frontSel_T, 0, 0) node out_frontSel_1 = bits(_out_frontSel_T, 1, 1) node out_frontSel_2 = bits(_out_frontSel_T, 2, 2) node out_frontSel_3 = bits(_out_frontSel_T, 3, 3) node _out_backSel_T = dshl(UInt<1>(0h1), out_oindex) node out_backSel_0 = bits(_out_backSel_T, 0, 0) node out_backSel_1 = bits(_out_backSel_T, 1, 1) node out_backSel_2 = bits(_out_backSel_T, 2, 2) node out_backSel_3 = bits(_out_backSel_T, 3, 3) node _out_rifireMux_T = and(in.valid, out_front.ready) node _out_rifireMux_T_1 = and(_out_rifireMux_T, out_front.bits.read) wire out_rifireMux_out : UInt<1> node _out_rifireMux_T_2 = and(_out_rifireMux_T_1, out_frontSel_0) node _out_rifireMux_T_3 = and(_out_rifireMux_T_2, _out_T) connect out_rifireMux_out, UInt<1>(0h1) connect out_rivalid[5], _out_rifireMux_T_3 connect out_rivalid[4], _out_rifireMux_T_3 connect out_rivalid[3], _out_rifireMux_T_3 connect out_rivalid[2], _out_rifireMux_T_3 connect out_rivalid[1], _out_rifireMux_T_3 connect out_rivalid[0], _out_rifireMux_T_3 node _out_rifireMux_T_4 = eq(_out_T, UInt<1>(0h0)) node _out_rifireMux_T_5 = or(out_rifireMux_out, _out_rifireMux_T_4) wire out_rifireMux_out_1 : UInt<1> node _out_rifireMux_T_6 = and(_out_rifireMux_T_1, out_frontSel_1) node _out_rifireMux_T_7 = and(_out_rifireMux_T_6, _out_T_2) connect out_rifireMux_out_1, UInt<1>(0h1) connect out_rivalid[10], _out_rifireMux_T_7 connect out_rivalid[9], _out_rifireMux_T_7 connect out_rivalid[8], _out_rifireMux_T_7 connect out_rivalid[7], _out_rifireMux_T_7 connect out_rivalid[6], _out_rifireMux_T_7 node _out_rifireMux_T_8 = eq(_out_T_2, UInt<1>(0h0)) node _out_rifireMux_T_9 = or(out_rifireMux_out_1, _out_rifireMux_T_8) wire out_rifireMux_out_2 : UInt<1> node _out_rifireMux_T_10 = and(_out_rifireMux_T_1, out_frontSel_2) node _out_rifireMux_T_11 = and(_out_rifireMux_T_10, _out_T_4) connect out_rifireMux_out_2, UInt<1>(0h1) connect out_rivalid[14], _out_rifireMux_T_11 connect out_rivalid[13], _out_rifireMux_T_11 connect out_rivalid[12], _out_rifireMux_T_11 connect out_rivalid[11], _out_rifireMux_T_11 node _out_rifireMux_T_12 = eq(_out_T_4, UInt<1>(0h0)) node _out_rifireMux_T_13 = or(out_rifireMux_out_2, _out_rifireMux_T_12) wire out_rifireMux_out_3 : UInt<1> node _out_rifireMux_T_14 = and(_out_rifireMux_T_1, out_frontSel_3) node _out_rifireMux_T_15 = and(_out_rifireMux_T_14, _out_T_6) connect out_rifireMux_out_3, UInt<1>(0h1) connect out_rivalid[15], _out_rifireMux_T_15 node _out_rifireMux_T_16 = eq(_out_T_6, UInt<1>(0h0)) node _out_rifireMux_T_17 = or(out_rifireMux_out_3, _out_rifireMux_T_16) node _out_rifireMux_T_18 = geq(out_iindex, UInt<3>(0h4)) wire _out_rifireMux_WIRE : UInt<1>[4] connect _out_rifireMux_WIRE[0], _out_rifireMux_T_5 connect _out_rifireMux_WIRE[1], _out_rifireMux_T_9 connect _out_rifireMux_WIRE[2], _out_rifireMux_T_13 connect _out_rifireMux_WIRE[3], _out_rifireMux_T_17 node out_rifireMux = mux(_out_rifireMux_T_18, UInt<1>(0h1), _out_rifireMux_WIRE[out_iindex]) node _out_wifireMux_T = and(in.valid, out_front.ready) node _out_wifireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wifireMux_T_2 = and(_out_wifireMux_T, _out_wifireMux_T_1) wire out_wifireMux_out : UInt<1> node _out_wifireMux_T_3 = and(_out_wifireMux_T_2, out_frontSel_0) node _out_wifireMux_T_4 = and(_out_wifireMux_T_3, _out_T) connect out_wifireMux_out, UInt<1>(0h1) connect out_wivalid[5], _out_wifireMux_T_4 connect out_wivalid[4], _out_wifireMux_T_4 connect out_wivalid[3], _out_wifireMux_T_4 connect out_wivalid[2], _out_wifireMux_T_4 connect out_wivalid[1], _out_wifireMux_T_4 connect out_wivalid[0], _out_wifireMux_T_4 node _out_wifireMux_T_5 = eq(_out_T, UInt<1>(0h0)) node _out_wifireMux_T_6 = or(out_wifireMux_out, _out_wifireMux_T_5) wire out_wifireMux_out_1 : UInt<1> node _out_wifireMux_T_7 = and(_out_wifireMux_T_2, out_frontSel_1) node _out_wifireMux_T_8 = and(_out_wifireMux_T_7, _out_T_2) connect out_wifireMux_out_1, UInt<1>(0h1) connect out_wivalid[10], _out_wifireMux_T_8 connect out_wivalid[9], _out_wifireMux_T_8 connect out_wivalid[8], _out_wifireMux_T_8 connect out_wivalid[7], _out_wifireMux_T_8 connect out_wivalid[6], _out_wifireMux_T_8 node _out_wifireMux_T_9 = eq(_out_T_2, UInt<1>(0h0)) node _out_wifireMux_T_10 = or(out_wifireMux_out_1, _out_wifireMux_T_9) wire out_wifireMux_out_2 : UInt<1> node _out_wifireMux_T_11 = and(_out_wifireMux_T_2, out_frontSel_2) node _out_wifireMux_T_12 = and(_out_wifireMux_T_11, _out_T_4) connect out_wifireMux_out_2, UInt<1>(0h1) connect out_wivalid[14], _out_wifireMux_T_12 connect out_wivalid[13], _out_wifireMux_T_12 connect out_wivalid[12], _out_wifireMux_T_12 connect out_wivalid[11], _out_wifireMux_T_12 node _out_wifireMux_T_13 = eq(_out_T_4, UInt<1>(0h0)) node _out_wifireMux_T_14 = or(out_wifireMux_out_2, _out_wifireMux_T_13) wire out_wifireMux_out_3 : UInt<1> node _out_wifireMux_T_15 = and(_out_wifireMux_T_2, out_frontSel_3) node _out_wifireMux_T_16 = and(_out_wifireMux_T_15, _out_T_6) connect out_wifireMux_out_3, UInt<1>(0h1) connect out_wivalid[15], _out_wifireMux_T_16 node _out_wifireMux_T_17 = eq(_out_T_6, UInt<1>(0h0)) node _out_wifireMux_T_18 = or(out_wifireMux_out_3, _out_wifireMux_T_17) node _out_wifireMux_T_19 = geq(out_iindex, UInt<3>(0h4)) wire _out_wifireMux_WIRE : UInt<1>[4] connect _out_wifireMux_WIRE[0], _out_wifireMux_T_6 connect _out_wifireMux_WIRE[1], _out_wifireMux_T_10 connect _out_wifireMux_WIRE[2], _out_wifireMux_T_14 connect _out_wifireMux_WIRE[3], _out_wifireMux_T_18 node out_wifireMux = mux(_out_wifireMux_T_19, UInt<1>(0h1), _out_wifireMux_WIRE[out_iindex]) node _out_rofireMux_T = and(out_front.valid, out.ready) node _out_rofireMux_T_1 = and(_out_rofireMux_T, out_front.bits.read) wire out_rofireMux_out : UInt<1> node _out_rofireMux_T_2 = and(_out_rofireMux_T_1, out_backSel_0) node _out_rofireMux_T_3 = and(_out_rofireMux_T_2, _out_T_1) connect out_rofireMux_out, UInt<1>(0h1) connect out_roready[5], _out_rofireMux_T_3 connect out_roready[4], _out_rofireMux_T_3 connect out_roready[3], _out_rofireMux_T_3 connect out_roready[2], _out_rofireMux_T_3 connect out_roready[1], _out_rofireMux_T_3 connect out_roready[0], _out_rofireMux_T_3 node _out_rofireMux_T_4 = eq(_out_T_1, UInt<1>(0h0)) node _out_rofireMux_T_5 = or(out_rofireMux_out, _out_rofireMux_T_4) wire out_rofireMux_out_1 : UInt<1> node _out_rofireMux_T_6 = and(_out_rofireMux_T_1, out_backSel_1) node _out_rofireMux_T_7 = and(_out_rofireMux_T_6, _out_T_3) connect out_rofireMux_out_1, UInt<1>(0h1) connect out_roready[10], _out_rofireMux_T_7 connect out_roready[9], _out_rofireMux_T_7 connect out_roready[8], _out_rofireMux_T_7 connect out_roready[7], _out_rofireMux_T_7 connect out_roready[6], _out_rofireMux_T_7 node _out_rofireMux_T_8 = eq(_out_T_3, UInt<1>(0h0)) node _out_rofireMux_T_9 = or(out_rofireMux_out_1, _out_rofireMux_T_8) wire out_rofireMux_out_2 : UInt<1> node _out_rofireMux_T_10 = and(_out_rofireMux_T_1, out_backSel_2) node _out_rofireMux_T_11 = and(_out_rofireMux_T_10, _out_T_5) connect out_rofireMux_out_2, UInt<1>(0h1) connect out_roready[14], _out_rofireMux_T_11 connect out_roready[13], _out_rofireMux_T_11 connect out_roready[12], _out_rofireMux_T_11 connect out_roready[11], _out_rofireMux_T_11 node _out_rofireMux_T_12 = eq(_out_T_5, UInt<1>(0h0)) node _out_rofireMux_T_13 = or(out_rofireMux_out_2, _out_rofireMux_T_12) wire out_rofireMux_out_3 : UInt<1> node _out_rofireMux_T_14 = and(_out_rofireMux_T_1, out_backSel_3) node _out_rofireMux_T_15 = and(_out_rofireMux_T_14, _out_T_7) connect out_rofireMux_out_3, UInt<1>(0h1) connect out_roready[15], _out_rofireMux_T_15 node _out_rofireMux_T_16 = eq(_out_T_7, UInt<1>(0h0)) node _out_rofireMux_T_17 = or(out_rofireMux_out_3, _out_rofireMux_T_16) node _out_rofireMux_T_18 = geq(out_oindex, UInt<3>(0h4)) wire _out_rofireMux_WIRE : UInt<1>[4] connect _out_rofireMux_WIRE[0], _out_rofireMux_T_5 connect _out_rofireMux_WIRE[1], _out_rofireMux_T_9 connect _out_rofireMux_WIRE[2], _out_rofireMux_T_13 connect _out_rofireMux_WIRE[3], _out_rofireMux_T_17 node out_rofireMux = mux(_out_rofireMux_T_18, UInt<1>(0h1), _out_rofireMux_WIRE[out_oindex]) node _out_wofireMux_T = and(out_front.valid, out.ready) node _out_wofireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wofireMux_T_2 = and(_out_wofireMux_T, _out_wofireMux_T_1) wire out_wofireMux_out : UInt<1> node _out_wofireMux_T_3 = and(_out_wofireMux_T_2, out_backSel_0) node _out_wofireMux_T_4 = and(_out_wofireMux_T_3, _out_T_1) connect out_wofireMux_out, UInt<1>(0h1) connect out_woready[5], _out_wofireMux_T_4 connect out_woready[4], _out_wofireMux_T_4 connect out_woready[3], _out_wofireMux_T_4 connect out_woready[2], _out_wofireMux_T_4 connect out_woready[1], _out_wofireMux_T_4 connect out_woready[0], _out_wofireMux_T_4 node _out_wofireMux_T_5 = eq(_out_T_1, UInt<1>(0h0)) node _out_wofireMux_T_6 = or(out_wofireMux_out, _out_wofireMux_T_5) wire out_wofireMux_out_1 : UInt<1> node _out_wofireMux_T_7 = and(_out_wofireMux_T_2, out_backSel_1) node _out_wofireMux_T_8 = and(_out_wofireMux_T_7, _out_T_3) connect out_wofireMux_out_1, UInt<1>(0h1) connect out_woready[10], _out_wofireMux_T_8 connect out_woready[9], _out_wofireMux_T_8 connect out_woready[8], _out_wofireMux_T_8 connect out_woready[7], _out_wofireMux_T_8 connect out_woready[6], _out_wofireMux_T_8 node _out_wofireMux_T_9 = eq(_out_T_3, UInt<1>(0h0)) node _out_wofireMux_T_10 = or(out_wofireMux_out_1, _out_wofireMux_T_9) wire out_wofireMux_out_2 : UInt<1> node _out_wofireMux_T_11 = and(_out_wofireMux_T_2, out_backSel_2) node _out_wofireMux_T_12 = and(_out_wofireMux_T_11, _out_T_5) connect out_wofireMux_out_2, UInt<1>(0h1) connect out_woready[14], _out_wofireMux_T_12 connect out_woready[13], _out_wofireMux_T_12 connect out_woready[12], _out_wofireMux_T_12 connect out_woready[11], _out_wofireMux_T_12 node _out_wofireMux_T_13 = eq(_out_T_5, UInt<1>(0h0)) node _out_wofireMux_T_14 = or(out_wofireMux_out_2, _out_wofireMux_T_13) wire out_wofireMux_out_3 : UInt<1> node _out_wofireMux_T_15 = and(_out_wofireMux_T_2, out_backSel_3) node _out_wofireMux_T_16 = and(_out_wofireMux_T_15, _out_T_7) connect out_wofireMux_out_3, UInt<1>(0h1) connect out_woready[15], _out_wofireMux_T_16 node _out_wofireMux_T_17 = eq(_out_T_7, UInt<1>(0h0)) node _out_wofireMux_T_18 = or(out_wofireMux_out_3, _out_wofireMux_T_17) node _out_wofireMux_T_19 = geq(out_oindex, UInt<3>(0h4)) wire _out_wofireMux_WIRE : UInt<1>[4] connect _out_wofireMux_WIRE[0], _out_wofireMux_T_6 connect _out_wofireMux_WIRE[1], _out_wofireMux_T_10 connect _out_wofireMux_WIRE[2], _out_wofireMux_T_14 connect _out_wofireMux_WIRE[3], _out_wofireMux_T_18 node out_wofireMux = mux(_out_wofireMux_T_19, UInt<1>(0h1), _out_wofireMux_WIRE[out_oindex]) node out_iready = mux(out_front.bits.read, out_rifireMux, out_wifireMux) node out_oready = mux(out_front.bits.read, out_rofireMux, out_wofireMux) node _out_in_ready_T = and(out_front.ready, out_iready) connect in.ready, _out_in_ready_T node _out_front_valid_T = and(in.valid, out_iready) connect out_front.valid, _out_front_valid_T node _out_front_ready_T = and(out.ready, out_oready) connect out_front.ready, _out_front_ready_T node _out_out_valid_T = and(out_front.valid, out_oready) connect out.valid, _out_out_valid_T connect out.bits.read, out_front.bits.read node _out_out_bits_data_T = geq(out_oindex, UInt<3>(0h4)) wire _out_out_bits_data_WIRE : UInt<1>[4] connect _out_out_bits_data_WIRE[0], _out_T_1 connect _out_out_bits_data_WIRE[1], _out_T_3 connect _out_out_bits_data_WIRE[2], _out_T_5 connect _out_out_bits_data_WIRE[3], _out_T_7 node _out_out_bits_data_T_1 = mux(_out_out_bits_data_T, UInt<1>(0h1), _out_out_bits_data_WIRE[out_oindex]) node _out_out_bits_data_T_2 = geq(out_oindex, UInt<3>(0h4)) wire _out_out_bits_data_WIRE_1 : UInt<64>[4] connect _out_out_bits_data_WIRE_1[0], _out_T_61 connect _out_out_bits_data_WIRE_1[1], _out_T_116 connect _out_out_bits_data_WIRE_1[2], _out_T_156 connect _out_out_bits_data_WIRE_1[3], _out_T_167 node _out_out_bits_data_T_3 = mux(_out_out_bits_data_T_2, UInt<1>(0h0), _out_out_bits_data_WIRE_1[out_oindex]) node _out_out_bits_data_T_4 = mux(_out_out_bits_data_T_1, _out_out_bits_data_T_3, UInt<1>(0h0)) connect out.bits.data, _out_out_bits_data_T_4 connect out.bits.extra, out_front.bits.extra connect in.valid, controlNodeIn.a.valid connect controlNodeIn.a.ready, in.ready connect controlNodeIn.d.valid, out.valid connect out.ready, controlNodeIn.d.ready wire controlNodeIn_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} connect controlNodeIn_d_bits_d.opcode, UInt<1>(0h0) connect controlNodeIn_d_bits_d.param, UInt<1>(0h0) connect controlNodeIn_d_bits_d.size, out.bits.extra.tlrr_extra.size connect controlNodeIn_d_bits_d.source, out.bits.extra.tlrr_extra.source connect controlNodeIn_d_bits_d.sink, UInt<1>(0h0) connect controlNodeIn_d_bits_d.denied, UInt<1>(0h0) invalidate controlNodeIn_d_bits_d.data connect controlNodeIn_d_bits_d.corrupt, UInt<1>(0h0) connect controlNodeIn.d.bits.corrupt, controlNodeIn_d_bits_d.corrupt connect controlNodeIn.d.bits.data, controlNodeIn_d_bits_d.data connect controlNodeIn.d.bits.denied, controlNodeIn_d_bits_d.denied connect controlNodeIn.d.bits.sink, controlNodeIn_d_bits_d.sink connect controlNodeIn.d.bits.source, controlNodeIn_d_bits_d.source connect controlNodeIn.d.bits.size, controlNodeIn_d_bits_d.size connect controlNodeIn.d.bits.param, controlNodeIn_d_bits_d.param connect controlNodeIn.d.bits.opcode, controlNodeIn_d_bits_d.opcode connect controlNodeIn.d.bits.data, out.bits.data node _controlNodeIn_d_bits_opcode_T = mux(out.bits.read, UInt<1>(0h1), UInt<1>(0h0)) connect controlNodeIn.d.bits.opcode, _controlNodeIn_d_bits_opcode_T wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<29>(0h0) connect _WIRE.bits.source, UInt<11>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<29>(0h0) connect _WIRE_2.bits.source, UInt<11>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1)	module TLUART( // @[UART.scala:127:25] input clock, // @[UART.scala:127:25] input reset, // @[UART.scala:127:25] output auto_int_xing_out_sync_0, // @[LazyModuleImp.scala:107:25] output auto_control_xing_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_control_xing_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_control_xing_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_control_xing_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_control_xing_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_control_xing_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [28:0] auto_control_xing_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_control_xing_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_control_xing_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_control_xing_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_control_xing_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_control_xing_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_control_xing_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_control_xing_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_control_xing_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_control_xing_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_io_out_txd, // @[LazyModuleImp.scala:107:25] input auto_io_out_rxd // @[LazyModuleImp.scala:107:25] ); wire out_front_valid; // @[RegisterRouter.scala:87:24] wire out_front_ready; // @[RegisterRouter.scala:87:24] wire out_bits_read; // @[RegisterRouter.scala:87:24] wire [10:0] out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [8:0] in_bits_index; // @[RegisterRouter.scala:73:18] wire in_bits_read; // @[RegisterRouter.scala:73:18] wire buffer_auto_out_d_valid; // @[Buffer.scala:40:9] wire buffer_auto_out_d_ready; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_d_bits_data; // @[Buffer.scala:40:9] wire [10:0] buffer_auto_out_d_bits_source; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_out_a_valid; // @[Buffer.scala:40:9] wire buffer_auto_out_a_ready; // @[Buffer.scala:40:9] wire buffer_auto_out_a_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_out_a_bits_data; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_out_a_bits_mask; // @[Buffer.scala:40:9] wire [28:0] buffer_auto_out_a_bits_address; // @[Buffer.scala:40:9] wire [10:0] buffer_auto_out_a_bits_source; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_out_a_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_d_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_d_ready; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_d_bits_data; // @[Buffer.scala:40:9] wire [10:0] buffer_auto_in_d_bits_source; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_d_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_d_bits_opcode; // @[Buffer.scala:40:9] wire buffer_auto_in_a_valid; // @[Buffer.scala:40:9] wire buffer_auto_in_a_ready; // @[Buffer.scala:40:9] wire buffer_auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_auto_in_a_bits_data; // @[Buffer.scala:40:9] wire [7:0] buffer_auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [28:0] buffer_auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [10:0] buffer_auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire _rxq_io_deq_valid; // @[UART.scala:133:19] wire [7:0] _rxq_io_deq_bits; // @[UART.scala:133:19] wire [3:0] _rxq_io_count; // @[UART.scala:133:19] wire _rxm_io_out_valid; // @[UART.scala:132:19] wire [7:0] _rxm_io_out_bits; // @[UART.scala:132:19] wire _txq_io_enq_ready; // @[UART.scala:130:19] wire _txq_io_deq_valid; // @[UART.scala:130:19] wire [7:0] _txq_io_deq_bits; // @[UART.scala:130:19] wire [3:0] _txq_io_count; // @[UART.scala:130:19] wire _txm_io_in_ready; // @[UART.scala:129:19] wire _txm_io_tx_busy; // @[UART.scala:129:19] wire auto_control_xing_in_a_valid_0 = auto_control_xing_in_a_valid; // @[UART.scala:127:25] wire [2:0] auto_control_xing_in_a_bits_opcode_0 = auto_control_xing_in_a_bits_opcode; // @[UART.scala:127:25] wire [2:0] auto_control_xing_in_a_bits_param_0 = auto_control_xing_in_a_bits_param; // @[UART.scala:127:25] wire [1:0] auto_control_xing_in_a_bits_size_0 = auto_control_xing_in_a_bits_size; // @[UART.scala:127:25] wire [10:0] auto_control_xing_in_a_bits_source_0 = auto_control_xing_in_a_bits_source; // @[UART.scala:127:25] wire [28:0] auto_control_xing_in_a_bits_address_0 = auto_control_xing_in_a_bits_address; // @[UART.scala:127:25] wire [7:0] auto_control_xing_in_a_bits_mask_0 = auto_control_xing_in_a_bits_mask; // @[UART.scala:127:25] wire [63:0] auto_control_xing_in_a_bits_data_0 = auto_control_xing_in_a_bits_data; // @[UART.scala:127:25] wire auto_control_xing_in_a_bits_corrupt_0 = auto_control_xing_in_a_bits_corrupt; // @[UART.scala:127:25] wire auto_control_xing_in_d_ready_0 = auto_control_xing_in_d_ready; // @[UART.scala:127:25] wire auto_io_out_rxd_0 = auto_io_out_rxd; // @[UART.scala:127:25] wire [8:0] out_maskMatch = 9'h1FC; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_15 = 8'h0; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_16 = 8'h0; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T = 8'h0; // @[RegisterRouter.scala:87:24] wire [8:0] out_prepend = 9'h0; // @[RegisterRouter.scala:87:24] wire [30:0] _out_T_24 = 31'h0; // @[RegisterRouter.scala:87:24] wire [30:0] _out_T_25 = 31'h0; // @[RegisterRouter.scala:87:24] wire [30:0] _out_prepend_T_1 = 31'h0; // @[RegisterRouter.scala:87:24] wire [2:0] controlNodeIn_d_bits_d_opcode = 3'h0; // @[Edges.scala:792:17] wire [63:0] controlNodeIn_d_bits_d_data = 64'h0; // @[Edges.scala:792:17] wire auto_control_xing_in_d_bits_sink = 1'h0; // @[UART.scala:127:25] wire auto_control_xing_in_d_bits_denied = 1'h0; // @[UART.scala:127:25] wire auto_control_xing_in_d_bits_corrupt = 1'h0; // @[UART.scala:127:25] wire buffer_auto_in_d_bits_sink = 1'h0; // @[Buffer.scala:40:9] wire buffer_auto_in_d_bits_denied = 1'h0; // @[Buffer.scala:40:9] wire buffer_auto_in_d_bits_corrupt = 1'h0; // @[Buffer.scala:40:9] wire buffer_auto_out_d_bits_sink = 1'h0; // @[Buffer.scala:40:9] wire buffer_auto_out_d_bits_denied = 1'h0; // @[Buffer.scala:40:9] wire buffer_auto_out_d_bits_corrupt = 1'h0; // @[Buffer.scala:40:9] wire buffer_nodeOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17] wire buffer_nodeOut_d_bits_denied = 1'h0; // @[MixedNode.scala:542:17] wire buffer_nodeOut_d_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire buffer_nodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire buffer_nodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire buffer_nodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire controlNodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire controlNodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire controlNodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire controlXingOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17] wire controlXingOut_d_bits_denied = 1'h0; // @[MixedNode.scala:542:17] wire controlXingOut_d_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire controlXingIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire controlXingIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire controlXingIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire _ie_WIRE_rxwm = 1'h0; // @[UART.scala:186:32] wire _ie_WIRE_txwm = 1'h0; // @[UART.scala:186:32] wire _out_rifireMux_T_18 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wifireMux_T_19 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_rofireMux_T_18 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wofireMux_T_19 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T_2 = 1'h0; // @[MuxLiteral.scala:49:17] wire controlNodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:792:17] wire controlNodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:792:17] wire controlNodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:792:17] wire [1:0] auto_control_xing_in_d_bits_param = 2'h0; // @[UART.scala:127:25] wire [1:0] buffer_auto_in_d_bits_param = 2'h0; // @[Buffer.scala:40:9] wire [1:0] buffer_auto_out_d_bits_param = 2'h0; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeOut_d_bits_param = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] buffer_nodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] controlNodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] controlXingOut_d_bits_param = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] controlXingIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] controlNodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:792:17] wire intXingOut_sync_0; // @[MixedNode.scala:542:17] wire out_rifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_18 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_rofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_18 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_iready = 1'h1; // @[RegisterRouter.scala:87:24] wire out_oready = 1'h1; // @[RegisterRouter.scala:87:24] wire controlXingIn_a_ready; // @[MixedNode.scala:551:17] wire controlXingIn_a_valid = auto_control_xing_in_a_valid_0; // @[UART.scala:127:25] wire [2:0] controlXingIn_a_bits_opcode = auto_control_xing_in_a_bits_opcode_0; // @[UART.scala:127:25] wire [2:0] controlXingIn_a_bits_param = auto_control_xing_in_a_bits_param_0; // @[UART.scala:127:25] wire [1:0] controlXingIn_a_bits_size = auto_control_xing_in_a_bits_size_0; // @[UART.scala:127:25] wire [10:0] controlXingIn_a_bits_source = auto_control_xing_in_a_bits_source_0; // @[UART.scala:127:25] wire [28:0] controlXingIn_a_bits_address = auto_control_xing_in_a_bits_address_0; // @[UART.scala:127:25] wire [7:0] controlXingIn_a_bits_mask = auto_control_xing_in_a_bits_mask_0; // @[UART.scala:127:25] wire [63:0] controlXingIn_a_bits_data = auto_control_xing_in_a_bits_data_0; // @[UART.scala:127:25] wire controlXingIn_a_bits_corrupt = auto_control_xing_in_a_bits_corrupt_0; // @[UART.scala:127:25] wire controlXingIn_d_ready = auto_control_xing_in_d_ready_0; // @[UART.scala:127:25] wire controlXingIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] controlXingIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] controlXingIn_d_bits_size; // @[MixedNode.scala:551:17] wire [10:0] controlXingIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] controlXingIn_d_bits_data; // @[MixedNode.scala:551:17] wire ioNodeOut_txd; // @[MixedNode.scala:542:17] wire ioNodeOut_rxd = auto_io_out_rxd_0; // @[UART.scala:127:25] wire auto_int_xing_out_sync_0_0; // @[UART.scala:127:25] wire auto_control_xing_in_a_ready_0; // @[UART.scala:127:25] wire [2:0] auto_control_xing_in_d_bits_opcode_0; // @[UART.scala:127:25] wire [1:0] auto_control_xing_in_d_bits_size_0; // @[UART.scala:127:25] wire [10:0] auto_control_xing_in_d_bits_source_0; // @[UART.scala:127:25] wire [63:0] auto_control_xing_in_d_bits_data_0; // @[UART.scala:127:25] wire auto_control_xing_in_d_valid_0; // @[UART.scala:127:25] wire auto_io_out_txd_0; // @[UART.scala:127:25] wire buffer_nodeIn_a_ready; // @[MixedNode.scala:551:17] wire controlXingOut_a_ready = buffer_auto_in_a_ready; // @[Buffer.scala:40:9] wire controlXingOut_a_valid; // @[MixedNode.scala:542:17] wire buffer_nodeIn_a_valid = buffer_auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] controlXingOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] buffer_nodeIn_a_bits_opcode = buffer_auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] controlXingOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] buffer_nodeIn_a_bits_param = buffer_auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [1:0] controlXingOut_a_bits_size; // @[MixedNode.scala:542:17] wire [1:0] buffer_nodeIn_a_bits_size = buffer_auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [10:0] controlXingOut_a_bits_source; // @[MixedNode.scala:542:17] wire [10:0] buffer_nodeIn_a_bits_source = buffer_auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [28:0] controlXingOut_a_bits_address; // @[MixedNode.scala:542:17] wire [28:0] buffer_nodeIn_a_bits_address = buffer_auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] controlXingOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [7:0] buffer_nodeIn_a_bits_mask = buffer_auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] controlXingOut_a_bits_data; // @[MixedNode.scala:542:17] wire [63:0] buffer_nodeIn_a_bits_data = buffer_auto_in_a_bits_data; // @[Buffer.scala:40:9] wire controlXingOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire buffer_nodeIn_a_bits_corrupt = buffer_auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire controlXingOut_d_ready; // @[MixedNode.scala:542:17] wire buffer_nodeIn_d_ready = buffer_auto_in_d_ready; // @[Buffer.scala:40:9] wire buffer_nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] buffer_nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire controlXingOut_d_valid = buffer_auto_in_d_valid; // @[Buffer.scala:40:9] wire [2:0] controlXingOut_d_bits_opcode = buffer_auto_in_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [10:0] buffer_nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [1:0] controlXingOut_d_bits_size = buffer_auto_in_d_bits_size; // @[Buffer.scala:40:9] wire [10:0] controlXingOut_d_bits_source = buffer_auto_in_d_bits_source; // @[Buffer.scala:40:9] wire [63:0] buffer_nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire [63:0] controlXingOut_d_bits_data = buffer_auto_in_d_bits_data; // @[Buffer.scala:40:9] wire controlNodeIn_a_ready; // @[MixedNode.scala:551:17] wire buffer_nodeOut_a_ready = buffer_auto_out_a_ready; // @[Buffer.scala:40:9] wire buffer_nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] buffer_nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire controlNodeIn_a_valid = buffer_auto_out_a_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] controlNodeIn_a_bits_opcode = buffer_auto_out_a_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] buffer_nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [2:0] controlNodeIn_a_bits_param = buffer_auto_out_a_bits_param; // @[Buffer.scala:40:9] wire [10:0] buffer_nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [1:0] controlNodeIn_a_bits_size = buffer_auto_out_a_bits_size; // @[Buffer.scala:40:9] wire [28:0] buffer_nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [10:0] controlNodeIn_a_bits_source = buffer_auto_out_a_bits_source; // @[Buffer.scala:40:9] wire [7:0] buffer_nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [28:0] controlNodeIn_a_bits_address = buffer_auto_out_a_bits_address; // @[Buffer.scala:40:9] wire [63:0] buffer_nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire [7:0] controlNodeIn_a_bits_mask = buffer_auto_out_a_bits_mask; // @[Buffer.scala:40:9] wire buffer_nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire [63:0] controlNodeIn_a_bits_data = buffer_auto_out_a_bits_data; // @[Buffer.scala:40:9] wire buffer_nodeOut_d_ready; // @[MixedNode.scala:542:17] wire controlNodeIn_a_bits_corrupt = buffer_auto_out_a_bits_corrupt; // @[Buffer.scala:40:9] wire controlNodeIn_d_ready = buffer_auto_out_d_ready; // @[Buffer.scala:40:9] wire controlNodeIn_d_valid; // @[MixedNode.scala:551:17] wire buffer_nodeOut_d_valid = buffer_auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] controlNodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] buffer_nodeOut_d_bits_opcode = buffer_auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] controlNodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] buffer_nodeOut_d_bits_size = buffer_auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [10:0] controlNodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [10:0] buffer_nodeOut_d_bits_source = buffer_auto_out_d_bits_source; // @[Buffer.scala:40:9] wire [63:0] controlNodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire [63:0] buffer_nodeOut_d_bits_data = buffer_auto_out_d_bits_data; // @[Buffer.scala:40:9] assign buffer_nodeIn_a_ready = buffer_nodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_out_a_valid = buffer_nodeOut_a_valid; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_opcode = buffer_nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_param = buffer_nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_size = buffer_nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_source = buffer_nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_address = buffer_nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_mask = buffer_nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_data = buffer_nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_out_a_bits_corrupt = buffer_nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_out_d_ready = buffer_nodeOut_d_ready; // @[Buffer.scala:40:9] assign buffer_nodeIn_d_valid = buffer_nodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_opcode = buffer_nodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_size = buffer_nodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_source = buffer_nodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeIn_d_bits_data = buffer_nodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_in_a_ready = buffer_nodeIn_a_ready; // @[Buffer.scala:40:9] assign buffer_nodeOut_a_valid = buffer_nodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_opcode = buffer_nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_param = buffer_nodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_size = buffer_nodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_source = buffer_nodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_address = buffer_nodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_mask = buffer_nodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_data = buffer_nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_a_bits_corrupt = buffer_nodeIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_nodeOut_d_ready = buffer_nodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_in_d_valid = buffer_nodeIn_d_valid; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_opcode = buffer_nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_size = buffer_nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_source = buffer_nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_in_d_bits_data = buffer_nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign auto_io_out_txd_0 = ioNodeOut_txd; // @[UART.scala:127:25] wire _intnodeOut_0_T_2; // @[UART.scala:191:41] wire intnodeOut_0; // @[MixedNode.scala:542:17] wire in_ready; // @[RegisterRouter.scala:73:18] assign buffer_auto_out_a_ready = controlNodeIn_a_ready; // @[Buffer.scala:40:9] wire in_valid = controlNodeIn_a_valid; // @[RegisterRouter.scala:73:18] wire [1:0] in_bits_extra_tlrr_extra_size = controlNodeIn_a_bits_size; // @[RegisterRouter.scala:73:18] wire [10:0] in_bits_extra_tlrr_extra_source = controlNodeIn_a_bits_source; // @[RegisterRouter.scala:73:18] wire [7:0] in_bits_mask = controlNodeIn_a_bits_mask; // @[RegisterRouter.scala:73:18] wire [63:0] in_bits_data = controlNodeIn_a_bits_data; // @[RegisterRouter.scala:73:18] wire out_ready = controlNodeIn_d_ready; // @[RegisterRouter.scala:87:24] wire out_valid; // @[RegisterRouter.scala:87:24] assign buffer_auto_out_d_valid = controlNodeIn_d_valid; // @[Buffer.scala:40:9] assign buffer_auto_out_d_bits_opcode = controlNodeIn_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] controlNodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign buffer_auto_out_d_bits_size = controlNodeIn_d_bits_size; // @[Buffer.scala:40:9] wire [10:0] controlNodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign buffer_auto_out_d_bits_source = controlNodeIn_d_bits_source; // @[Buffer.scala:40:9] wire [63:0] out_bits_data; // @[RegisterRouter.scala:87:24] assign buffer_auto_out_d_bits_data = controlNodeIn_d_bits_data; // @[Buffer.scala:40:9] assign controlXingIn_a_ready = controlXingOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_auto_in_a_valid = controlXingOut_a_valid; // @[Buffer.scala:40:9] assign buffer_auto_in_a_bits_opcode = controlXingOut_a_bits_opcode; // @[Buffer.scala:40:9] assign buffer_auto_in_a_bits_param = controlXingOut_a_bits_param; // @[Buffer.scala:40:9] assign buffer_auto_in_a_bits_size = controlXingOut_a_bits_size; // @[Buffer.scala:40:9] assign buffer_auto_in_a_bits_source = controlXingOut_a_bits_source; // @[Buffer.scala:40:9] assign buffer_auto_in_a_bits_address = controlXingOut_a_bits_address; // @[Buffer.scala:40:9] assign buffer_auto_in_a_bits_mask = controlXingOut_a_bits_mask; // @[Buffer.scala:40:9] assign buffer_auto_in_a_bits_data = controlXingOut_a_bits_data; // @[Buffer.scala:40:9] assign buffer_auto_in_a_bits_corrupt = controlXingOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_auto_in_d_ready = controlXingOut_d_ready; // @[Buffer.scala:40:9] assign controlXingIn_d_valid = controlXingOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign controlXingIn_d_bits_opcode = controlXingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign controlXingIn_d_bits_size = controlXingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign controlXingIn_d_bits_source = controlXingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign controlXingIn_d_bits_data = controlXingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign auto_control_xing_in_a_ready_0 = controlXingIn_a_ready; // @[UART.scala:127:25] assign controlXingOut_a_valid = controlXingIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign controlXingOut_a_bits_opcode = controlXingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign controlXingOut_a_bits_param = controlXingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign controlXingOut_a_bits_size = controlXingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign controlXingOut_a_bits_source = controlXingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign controlXingOut_a_bits_address = controlXingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign controlXingOut_a_bits_mask = controlXingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign controlXingOut_a_bits_data = controlXingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign controlXingOut_a_bits_corrupt = controlXingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign controlXingOut_d_ready = controlXingIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_control_xing_in_d_valid_0 = controlXingIn_d_valid; // @[UART.scala:127:25] assign auto_control_xing_in_d_bits_opcode_0 = controlXingIn_d_bits_opcode; // @[UART.scala:127:25] assign auto_control_xing_in_d_bits_size_0 = controlXingIn_d_bits_size; // @[UART.scala:127:25] assign auto_control_xing_in_d_bits_source_0 = controlXingIn_d_bits_source; // @[UART.scala:127:25] assign auto_control_xing_in_d_bits_data_0 = controlXingIn_d_bits_data; // @[UART.scala:127:25] wire intXingIn_sync_0; // @[MixedNode.scala:551:17] assign auto_int_xing_out_sync_0_0 = intXingOut_sync_0; // @[UART.scala:127:25] assign intXingOut_sync_0 = intXingIn_sync_0; // @[MixedNode.scala:542:17, :551:17] reg [15:0] div; // @[UART.scala:135:20] wire [15:0] _out_T_166 = div; // @[RegisterRouter.scala:87:24] reg txen; // @[UART.scala:141:21] wire _out_T_71 = txen; // @[RegisterRouter.scala:87:24] reg rxen; // @[UART.scala:142:21] reg [3:0] txwm; // @[UART.scala:149:21] reg [3:0] rxwm; // @[UART.scala:150:21] reg nstop; // @[UART.scala:151:22] wire _tx_busy_T = \|_txq_io_count; // @[UART.scala:130:19, :175:49] wire _tx_busy_T_1 = _txm_io_tx_busy \| _tx_busy_T; // @[UART.scala:129:19, :175:{33,49}] wire tx_busy = _tx_busy_T_1 & txen; // @[UART.scala:141:21, :175:{33,54}] reg ie_rxwm; // @[UART.scala:186:19] reg ie_txwm; // @[UART.scala:186:19] wire _out_T_126 = ie_txwm; // @[RegisterRouter.scala:87:24] wire _ip_rxwm_T; // @[UART.scala:190:28] wire _ip_txwm_T; // @[UART.scala:189:28] wire ip_rxwm; // @[UART.scala:187:16] wire ip_txwm; // @[UART.scala:187:16] assign _ip_txwm_T = _txq_io_count < txwm; // @[UART.scala:130:19, :149:21, :189:28] assign ip_txwm = _ip_txwm_T; // @[UART.scala:187:16, :189:28] assign _ip_rxwm_T = _rxq_io_count > rxwm; // @[UART.scala:133:19, :150:21, :190:28] assign ip_rxwm = _ip_rxwm_T; // @[UART.scala:187:16, :190:28] wire _intnodeOut_0_T = ip_txwm & ie_txwm; // @[UART.scala:186:19, :187:16, :191:29] wire _intnodeOut_0_T_1 = ip_rxwm & ie_rxwm; // @[UART.scala:186:19, :187:16, :191:53] assign _intnodeOut_0_T_2 = _intnodeOut_0_T \| _intnodeOut_0_T_1; // @[UART.scala:191:{29,41,53}] assign intnodeOut_0 = _intnodeOut_0_T_2; // @[UART.scala:191:41] wire _out_quash_T_1; // @[RegMapFIFO.scala:26:26] wire quash; // @[RegMapFIFO.scala:11:21] wire _out_in_ready_T; // @[RegisterRouter.scala:87:24] assign controlNodeIn_a_ready = in_ready; // @[RegisterRouter.scala:73:18] wire _in_bits_read_T; // @[RegisterRouter.scala:74:36] wire _out_front_valid_T = in_valid; // @[RegisterRouter.scala:73:18, :87:24] wire out_front_bits_read = in_bits_read; // @[RegisterRouter.scala:73:18, :87:24] wire [8:0] out_front_bits_index = in_bits_index; // @[RegisterRouter.scala:73:18, :87:24] wire [63:0] out_front_bits_data = in_bits_data; // @[RegisterRouter.scala:73:18, :87:24] wire [7:0] out_front_bits_mask = in_bits_mask; // @[RegisterRouter.scala:73:18, :87:24] wire [10:0] out_front_bits_extra_tlrr_extra_source = in_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:73:18, :87:24] wire [1:0] out_front_bits_extra_tlrr_extra_size = in_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:73:18, :87:24] assign _in_bits_read_T = controlNodeIn_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36] assign in_bits_read = _in_bits_read_T; // @[RegisterRouter.scala:73:18, :74:36] wire [25:0] _in_bits_index_T = controlNodeIn_a_bits_address[28:3]; // @[Edges.scala:192:34] assign in_bits_index = _in_bits_index_T[8:0]; // @[RegisterRouter.scala:73:18, :75:19] wire _out_front_ready_T = out_ready; // @[RegisterRouter.scala:87:24] wire _out_out_valid_T; // @[RegisterRouter.scala:87:24] assign controlNodeIn_d_valid = out_valid; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24] wire _controlNodeIn_d_bits_opcode_T = out_bits_read; // @[RegisterRouter.scala:87:24, :105:25] assign controlNodeIn_d_bits_data = out_bits_data; // @[RegisterRouter.scala:87:24] assign controlNodeIn_d_bits_d_source = out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [1:0] out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign controlNodeIn_d_bits_d_size = out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign _out_in_ready_T = out_front_ready; // @[RegisterRouter.scala:87:24] assign _out_out_valid_T = out_front_valid; // @[RegisterRouter.scala:87:24] assign out_bits_read = out_front_bits_read; // @[RegisterRouter.scala:87:24] assign out_bits_extra_tlrr_extra_source = out_front_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] assign out_bits_extra_tlrr_extra_size = out_front_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] wire [8:0] _GEN = out_front_bits_index & 9'h1FC; // @[RegisterRouter.scala:87:24] wire [8:0] out_findex; // @[RegisterRouter.scala:87:24] assign out_findex = _GEN; // @[RegisterRouter.scala:87:24] wire [8:0] out_bindex; // @[RegisterRouter.scala:87:24] assign out_bindex = _GEN; // @[RegisterRouter.scala:87:24] wire _GEN_0 = out_findex == 9'h0; // @[RegisterRouter.scala:87:24] wire _out_T; // @[RegisterRouter.scala:87:24] assign _out_T = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_T_2; // @[RegisterRouter.scala:87:24] assign _out_T_2 = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_T_4; // @[RegisterRouter.scala:87:24] assign _out_T_4 = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_T_6; // @[RegisterRouter.scala:87:24] assign _out_T_6 = _GEN_0; // @[RegisterRouter.scala:87:24] wire _GEN_1 = out_bindex == 9'h0; // @[RegisterRouter.scala:87:24] wire _out_T_1; // @[RegisterRouter.scala:87:24] assign _out_T_1 = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_T_3; // @[RegisterRouter.scala:87:24] assign _out_T_3 = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_T_5; // @[RegisterRouter.scala:87:24] assign _out_T_5 = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_T_7; // @[RegisterRouter.scala:87:24] assign _out_T_7 = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_0 = _out_T_1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_1 = _out_T_3; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2 = _out_T_5; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_3 = _out_T_7; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_15; // @[RegisterRouter.scala:87:24] wire out_rivalid_0; // @[RegisterRouter.scala:87:24] wire out_rivalid_1; // @[RegisterRouter.scala:87:24] wire out_rivalid_2; // @[RegisterRouter.scala:87:24] wire out_rivalid_3; // @[RegisterRouter.scala:87:24] wire out_rivalid_4; // @[RegisterRouter.scala:87:24] wire out_rivalid_5; // @[RegisterRouter.scala:87:24] wire out_rivalid_6; // @[RegisterRouter.scala:87:24] wire out_rivalid_7; // @[RegisterRouter.scala:87:24] wire out_rivalid_8; // @[RegisterRouter.scala:87:24] wire out_rivalid_9; // @[RegisterRouter.scala:87:24] wire out_rivalid_10; // @[RegisterRouter.scala:87:24] wire out_rivalid_11; // @[RegisterRouter.scala:87:24] wire out_rivalid_12; // @[RegisterRouter.scala:87:24] wire out_rivalid_13; // @[RegisterRouter.scala:87:24] wire out_rivalid_14; // @[RegisterRouter.scala:87:24] wire out_rivalid_15; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_16; // @[RegisterRouter.scala:87:24] wire out_wivalid_0; // @[RegisterRouter.scala:87:24] wire out_wivalid_1; // @[RegisterRouter.scala:87:24] wire out_wivalid_2; // @[RegisterRouter.scala:87:24] wire out_wivalid_3; // @[RegisterRouter.scala:87:24] wire out_wivalid_4; // @[RegisterRouter.scala:87:24] wire out_wivalid_5; // @[RegisterRouter.scala:87:24] wire out_wivalid_6; // @[RegisterRouter.scala:87:24] wire out_wivalid_7; // @[RegisterRouter.scala:87:24] wire out_wivalid_8; // @[RegisterRouter.scala:87:24] wire out_wivalid_9; // @[RegisterRouter.scala:87:24] wire out_wivalid_10; // @[RegisterRouter.scala:87:24] wire out_wivalid_11; // @[RegisterRouter.scala:87:24] wire out_wivalid_12; // @[RegisterRouter.scala:87:24] wire out_wivalid_13; // @[RegisterRouter.scala:87:24] wire out_wivalid_14; // @[RegisterRouter.scala:87:24] wire out_wivalid_15; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_15; // @[RegisterRouter.scala:87:24] wire out_roready_0; // @[RegisterRouter.scala:87:24] wire out_roready_1; // @[RegisterRouter.scala:87:24] wire out_roready_2; // @[RegisterRouter.scala:87:24] wire out_roready_3; // @[RegisterRouter.scala:87:24] wire out_roready_4; // @[RegisterRouter.scala:87:24] wire out_roready_5; // @[RegisterRouter.scala:87:24] wire out_roready_6; // @[RegisterRouter.scala:87:24] wire out_roready_7; // @[RegisterRouter.scala:87:24] wire out_roready_8; // @[RegisterRouter.scala:87:24] wire out_roready_9; // @[RegisterRouter.scala:87:24] wire out_roready_10; // @[RegisterRouter.scala:87:24] wire out_roready_11; // @[RegisterRouter.scala:87:24] wire out_roready_12; // @[RegisterRouter.scala:87:24] wire out_roready_13; // @[RegisterRouter.scala:87:24] wire out_roready_14; // @[RegisterRouter.scala:87:24] wire out_roready_15; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_16; // @[RegisterRouter.scala:87:24] wire out_woready_0; // @[RegisterRouter.scala:87:24] wire out_woready_1; // @[RegisterRouter.scala:87:24] wire out_woready_2; // @[RegisterRouter.scala:87:24] wire out_woready_3; // @[RegisterRouter.scala:87:24] wire out_woready_4; // @[RegisterRouter.scala:87:24] wire out_woready_5; // @[RegisterRouter.scala:87:24] wire out_woready_6; // @[RegisterRouter.scala:87:24] wire out_woready_7; // @[RegisterRouter.scala:87:24] wire out_woready_8; // @[RegisterRouter.scala:87:24] wire out_woready_9; // @[RegisterRouter.scala:87:24] wire out_woready_10; // @[RegisterRouter.scala:87:24] wire out_woready_11; // @[RegisterRouter.scala:87:24] wire out_woready_12; // @[RegisterRouter.scala:87:24] wire out_woready_13; // @[RegisterRouter.scala:87:24] wire out_woready_14; // @[RegisterRouter.scala:87:24] wire out_woready_15; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_8 = {8{_out_frontMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_9 = {8{_out_frontMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_10 = {8{_out_frontMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_11 = {8{_out_frontMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_12 = {8{_out_frontMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_13 = {8{_out_frontMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_14 = {8{_out_frontMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_15 = {8{_out_frontMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_lo = {_out_frontMask_T_9, _out_frontMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_hi = {_out_frontMask_T_11, _out_frontMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_lo = {out_frontMask_lo_hi, out_frontMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_lo = {_out_frontMask_T_13, _out_frontMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_hi = {_out_frontMask_T_15, _out_frontMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_hi = {out_frontMask_hi_hi, out_frontMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_frontMask = {out_frontMask_hi, out_frontMask_lo}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_8 = {8{_out_backMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_9 = {8{_out_backMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_10 = {8{_out_backMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_11 = {8{_out_backMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_12 = {8{_out_backMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_13 = {8{_out_backMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_14 = {8{_out_backMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_15 = {8{_out_backMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_lo = {_out_backMask_T_9, _out_backMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_hi = {_out_backMask_T_11, _out_backMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_lo = {out_backMask_lo_hi, out_backMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_lo = {_out_backMask_T_13, _out_backMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_hi = {_out_backMask_T_15, _out_backMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_hi = {out_backMask_hi_hi, out_backMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_backMask = {out_backMask_hi, out_backMask_lo}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire out_rimask = \|_out_rimask_T; // @[RegisterRouter.scala:87:24] wire out_wimask = &_out_wimask_T; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire out_romask = \|_out_romask_T; // @[RegisterRouter.scala:87:24] wire out_womask = &_out_womask_T; // @[RegisterRouter.scala:87:24] wire out_f_rivalid = out_rivalid_0 & out_rimask; // @[RegisterRouter.scala:87:24] wire out_f_roready = out_roready_0 & out_romask; // @[RegisterRouter.scala:87:24] wire out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala:87:24] wire _out_T_9 = out_f_wivalid; // @[RegisterRouter.scala:87:24] wire out_f_woready = out_woready_0 & out_womask; // @[RegisterRouter.scala:87:24] wire _out_T_10 = out_f_woready; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_8 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire _out_txq_io_enq_valid_T = ~quash; // @[RegMapFIFO.scala:11:21, :18:33] wire _out_txq_io_enq_valid_T_1 = out_f_woready & _out_txq_io_enq_valid_T; // @[RegisterRouter.scala:87:24] wire _out_T_11 = ~out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_12 = ~out_wimask; // @[RegisterRouter.scala:87:24] wire _out_T_13 = ~out_romask; // @[RegisterRouter.scala:87:24] wire _out_T_14 = ~out_womask; // @[RegisterRouter.scala:87:24] wire [22:0] _out_rimask_T_1 = out_frontMask[30:8]; // @[RegisterRouter.scala:87:24] wire [22:0] _out_wimask_T_1 = out_frontMask[30:8]; // @[RegisterRouter.scala:87:24] wire out_rimask_1 = \|_out_rimask_T_1; // @[RegisterRouter.scala:87:24] wire out_wimask_1 = &_out_wimask_T_1; // @[RegisterRouter.scala:87:24] wire [22:0] _out_romask_T_1 = out_backMask[30:8]; // @[RegisterRouter.scala:87:24] wire [22:0] _out_womask_T_1 = out_backMask[30:8]; // @[RegisterRouter.scala:87:24] wire out_romask_1 = \|_out_romask_T_1; // @[RegisterRouter.scala:87:24] wire out_womask_1 = &_out_womask_T_1; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1 = out_rivalid_1 & out_rimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_18 = out_f_rivalid_1; // @[RegisterRouter.scala:87:24] wire out_f_roready_1 = out_roready_1 & out_romask_1; // @[RegisterRouter.scala:87:24] wire _out_T_19 = out_f_roready_1; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1 = out_wivalid_1 & out_wimask_1; // @[RegisterRouter.scala:87:24] wire out_f_woready_1 = out_woready_1 & out_womask_1; // @[RegisterRouter.scala:87:24] wire [22:0] _out_T_17 = out_front_bits_data[30:8]; // @[RegisterRouter.scala:87:24] wire _out_T_20 = ~out_rimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_21 = ~out_wimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_22 = ~out_romask_1; // @[RegisterRouter.scala:87:24] wire _out_T_23 = ~out_womask_1; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_2 = out_frontMask[31]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_2 = out_frontMask[31]; // @[RegisterRouter.scala:87:24] wire out_rimask_2 = _out_rimask_T_2; // @[RegisterRouter.scala:87:24] wire out_wimask_2 = _out_wimask_T_2; // @[RegisterRouter.scala:87:24] wire _out_romask_T_2 = out_backMask[31]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_2 = out_backMask[31]; // @[RegisterRouter.scala:87:24] wire out_romask_2 = _out_romask_T_2; // @[RegisterRouter.scala:87:24] wire out_womask_2 = _out_womask_T_2; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_2 = out_rivalid_2 & out_rimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_27 = out_f_rivalid_2; // @[RegisterRouter.scala:87:24] wire out_f_roready_2 = out_roready_2 & out_romask_2; // @[RegisterRouter.scala:87:24] wire _out_T_28 = out_f_roready_2; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_2 = out_wivalid_2 & out_wimask_2; // @[RegisterRouter.scala:87:24] wire out_f_woready_2 = out_woready_2 & out_womask_2; // @[RegisterRouter.scala:87:24] wire _out_T_26 = out_front_bits_data[31]; // @[RegisterRouter.scala:87:24] wire _out_quash_T = _out_T_26; // @[RegisterRouter.scala:87:24] assign _out_quash_T_1 = out_f_woready_2 & _out_quash_T; // @[RegisterRouter.scala:87:24] assign quash = _out_quash_T_1; // @[RegMapFIFO.scala:11:21, :26:26] wire _out_T_29 = ~out_rimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_30 = ~out_wimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_31 = ~out_romask_2; // @[RegisterRouter.scala:87:24] wire _out_T_32 = ~out_womask_2; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_1 = {~_txq_io_enq_ready, 31'h0}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_33 = out_prepend_1; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_34 = _out_T_33; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_2 = _out_T_34; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_3 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_3 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24] wire out_rimask_3 = \|_out_rimask_T_3; // @[RegisterRouter.scala:87:24] wire out_wimask_3 = &_out_wimask_T_3; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_3 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_3 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24] wire out_romask_3 = \|_out_romask_T_3; // @[RegisterRouter.scala:87:24] wire out_womask_3 = &_out_womask_T_3; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_3 = out_rivalid_3 & out_rimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_36 = out_f_rivalid_3; // @[RegisterRouter.scala:87:24] wire out_f_roready_3 = out_roready_3 & out_romask_3; // @[RegisterRouter.scala:87:24] wire _out_T_37 = out_f_roready_3; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_3 = out_wivalid_3 & out_wimask_3; // @[RegisterRouter.scala:87:24] wire out_f_woready_3 = out_woready_3 & out_womask_3; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_35 = out_front_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire _out_T_38 = ~out_rimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_39 = ~out_wimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_40 = ~out_romask_3; // @[RegisterRouter.scala:87:24] wire _out_T_41 = ~out_womask_3; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_2 = {_rxq_io_deq_bits, _out_prepend_T_2}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_42 = out_prepend_2; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_43 = _out_T_42; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_3 = _out_T_43; // @[RegisterRouter.scala:87:24] wire [22:0] _out_rimask_T_4 = out_frontMask[62:40]; // @[RegisterRouter.scala:87:24] wire [22:0] _out_wimask_T_4 = out_frontMask[62:40]; // @[RegisterRouter.scala:87:24] wire out_rimask_4 = \|_out_rimask_T_4; // @[RegisterRouter.scala:87:24] wire out_wimask_4 = &_out_wimask_T_4; // @[RegisterRouter.scala:87:24] wire [22:0] _out_romask_T_4 = out_backMask[62:40]; // @[RegisterRouter.scala:87:24] wire [22:0] _out_womask_T_4 = out_backMask[62:40]; // @[RegisterRouter.scala:87:24] wire out_romask_4 = \|_out_romask_T_4; // @[RegisterRouter.scala:87:24] wire out_womask_4 = &_out_womask_T_4; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_4 = out_rivalid_4 & out_rimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_45 = out_f_rivalid_4; // @[RegisterRouter.scala:87:24] wire out_f_roready_4 = out_roready_4 & out_romask_4; // @[RegisterRouter.scala:87:24] wire _out_T_46 = out_f_roready_4; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_4 = out_wivalid_4 & out_wimask_4; // @[RegisterRouter.scala:87:24] wire out_f_woready_4 = out_woready_4 & out_womask_4; // @[RegisterRouter.scala:87:24] wire [22:0] _out_T_44 = out_front_bits_data[62:40]; // @[RegisterRouter.scala:87:24] wire _out_T_47 = ~out_rimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_48 = ~out_wimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_49 = ~out_romask_4; // @[RegisterRouter.scala:87:24] wire _out_T_50 = ~out_womask_4; // @[RegisterRouter.scala:87:24] wire [40:0] out_prepend_3 = {1'h0, _out_prepend_T_3}; // @[RegisterRouter.scala:87:24] wire [62:0] _out_T_51 = {22'h0, out_prepend_3}; // @[RegisterRouter.scala:87:24] wire [62:0] _out_T_52 = _out_T_51; // @[RegisterRouter.scala:87:24] wire [62:0] _out_prepend_T_4 = _out_T_52; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_5 = out_frontMask[63]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_5 = out_frontMask[63]; // @[RegisterRouter.scala:87:24] wire out_rimask_5 = _out_rimask_T_5; // @[RegisterRouter.scala:87:24] wire out_wimask_5 = _out_wimask_T_5; // @[RegisterRouter.scala:87:24] wire _out_romask_T_5 = out_backMask[63]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_5 = out_backMask[63]; // @[RegisterRouter.scala:87:24] wire out_romask_5 = _out_romask_T_5; // @[RegisterRouter.scala:87:24] wire out_womask_5 = _out_womask_T_5; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_5 = out_rivalid_5 & out_rimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_54 = out_f_rivalid_5; // @[RegisterRouter.scala:87:24] wire out_f_roready_5 = out_roready_5 & out_romask_5; // @[RegisterRouter.scala:87:24] wire _out_T_55 = out_f_roready_5; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_5 = out_wivalid_5 & out_wimask_5; // @[RegisterRouter.scala:87:24] wire out_f_woready_5 = out_woready_5 & out_womask_5; // @[RegisterRouter.scala:87:24] wire _out_T_53 = out_front_bits_data[63]; // @[RegisterRouter.scala:87:24] wire _out_T_56 = ~out_rimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_57 = ~out_wimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_58 = ~out_romask_5; // @[RegisterRouter.scala:87:24] wire _out_T_59 = ~out_womask_5; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_4 = {~_rxq_io_deq_valid, _out_prepend_T_4}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_60 = out_prepend_4; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_61 = _out_T_60; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_1_0 = _out_T_61; // @[MuxLiteral.scala:49:48] wire _out_rimask_T_6 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_6 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_11 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_11 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire out_rimask_6 = _out_rimask_T_6; // @[RegisterRouter.scala:87:24] wire out_wimask_6 = _out_wimask_T_6; // @[RegisterRouter.scala:87:24] wire _out_romask_T_6 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_6 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_11 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_11 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire out_romask_6 = _out_romask_T_6; // @[RegisterRouter.scala:87:24] wire out_womask_6 = _out_womask_T_6; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_6 = out_rivalid_6 & out_rimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_63 = out_f_rivalid_6; // @[RegisterRouter.scala:87:24] wire out_f_roready_6 = out_roready_6 & out_romask_6; // @[RegisterRouter.scala:87:24] wire _out_T_64 = out_f_roready_6; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_6 = out_wivalid_6 & out_wimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_65 = out_f_wivalid_6; // @[RegisterRouter.scala:87:24] wire out_f_woready_6 = out_woready_6 & out_womask_6; // @[RegisterRouter.scala:87:24] wire _out_T_66 = out_f_woready_6; // @[RegisterRouter.scala:87:24] wire _out_T_62 = out_front_bits_data[0]; // @[RegisterRouter.scala:87:24] wire _out_T_117 = out_front_bits_data[0]; // @[RegisterRouter.scala:87:24] wire _out_T_67 = ~out_rimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_68 = ~out_wimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_69 = ~out_romask_6; // @[RegisterRouter.scala:87:24] wire _out_T_70 = ~out_womask_6; // @[RegisterRouter.scala:87:24] wire _out_T_72 = _out_T_71; // @[RegisterRouter.scala:87:24] wire _out_prepend_T_5 = _out_T_72; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_7 = out_frontMask[1]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_7 = out_frontMask[1]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_12 = out_frontMask[1]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_12 = out_frontMask[1]; // @[RegisterRouter.scala:87:24] wire out_rimask_7 = _out_rimask_T_7; // @[RegisterRouter.scala:87:24] wire out_wimask_7 = _out_wimask_T_7; // @[RegisterRouter.scala:87:24] wire _out_romask_T_7 = out_backMask[1]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_7 = out_backMask[1]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_12 = out_backMask[1]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_12 = out_backMask[1]; // @[RegisterRouter.scala:87:24] wire out_romask_7 = _out_romask_T_7; // @[RegisterRouter.scala:87:24] wire out_womask_7 = _out_womask_T_7; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_7 = out_rivalid_7 & out_rimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_74 = out_f_rivalid_7; // @[RegisterRouter.scala:87:24] wire out_f_roready_7 = out_roready_7 & out_romask_7; // @[RegisterRouter.scala:87:24] wire _out_T_75 = out_f_roready_7; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_7 = out_wivalid_7 & out_wimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_76 = out_f_wivalid_7; // @[RegisterRouter.scala:87:24] wire out_f_woready_7 = out_woready_7 & out_womask_7; // @[RegisterRouter.scala:87:24] wire _out_T_77 = out_f_woready_7; // @[RegisterRouter.scala:87:24] wire _out_T_73 = out_front_bits_data[1]; // @[RegisterRouter.scala:87:24] wire _out_T_128 = out_front_bits_data[1]; // @[RegisterRouter.scala:87:24] wire _out_T_78 = ~out_rimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_79 = ~out_wimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_80 = ~out_romask_7; // @[RegisterRouter.scala:87:24] wire _out_T_81 = ~out_womask_7; // @[RegisterRouter.scala:87:24] wire [1:0] out_prepend_5 = {nstop, _out_prepend_T_5}; // @[RegisterRouter.scala:87:24] wire [1:0] _out_T_82 = out_prepend_5; // @[RegisterRouter.scala:87:24] wire [1:0] _out_T_83 = _out_T_82; // @[RegisterRouter.scala:87:24] wire [3:0] _out_rimask_T_8 = out_frontMask[19:16]; // @[RegisterRouter.scala:87:24] wire [3:0] _out_wimask_T_8 = out_frontMask[19:16]; // @[RegisterRouter.scala:87:24] wire out_rimask_8 = \|_out_rimask_T_8; // @[RegisterRouter.scala:87:24] wire out_wimask_8 = &_out_wimask_T_8; // @[RegisterRouter.scala:87:24] wire [3:0] _out_romask_T_8 = out_backMask[19:16]; // @[RegisterRouter.scala:87:24] wire [3:0] _out_womask_T_8 = out_backMask[19:16]; // @[RegisterRouter.scala:87:24] wire out_romask_8 = \|_out_romask_T_8; // @[RegisterRouter.scala:87:24] wire out_womask_8 = &_out_womask_T_8; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_8 = out_rivalid_8 & out_rimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_85 = out_f_rivalid_8; // @[RegisterRouter.scala:87:24] wire out_f_roready_8 = out_roready_8 & out_romask_8; // @[RegisterRouter.scala:87:24] wire _out_T_86 = out_f_roready_8; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_8 = out_wivalid_8 & out_wimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_87 = out_f_wivalid_8; // @[RegisterRouter.scala:87:24] wire out_f_woready_8 = out_woready_8 & out_womask_8; // @[RegisterRouter.scala:87:24] wire _out_T_88 = out_f_woready_8; // @[RegisterRouter.scala:87:24] wire [3:0] _out_T_84 = out_front_bits_data[19:16]; // @[RegisterRouter.scala:87:24] wire _out_T_89 = ~out_rimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_90 = ~out_wimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_91 = ~out_romask_8; // @[RegisterRouter.scala:87:24] wire _out_T_92 = ~out_womask_8; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_6 = {14'h0, _out_T_83}; // @[RegisterRouter.scala:87:24] wire [19:0] out_prepend_6 = {txwm, _out_prepend_T_6}; // @[RegisterRouter.scala:87:24] wire [19:0] _out_T_93 = out_prepend_6; // @[RegisterRouter.scala:87:24] wire [19:0] _out_T_94 = _out_T_93; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_9 = out_frontMask[32]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_9 = out_frontMask[32]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_13 = out_frontMask[32]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_13 = out_frontMask[32]; // @[RegisterRouter.scala:87:24] wire out_rimask_9 = _out_rimask_T_9; // @[RegisterRouter.scala:87:24] wire out_wimask_9 = _out_wimask_T_9; // @[RegisterRouter.scala:87:24] wire _out_romask_T_9 = out_backMask[32]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_9 = out_backMask[32]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_13 = out_backMask[32]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_13 = out_backMask[32]; // @[RegisterRouter.scala:87:24] wire out_romask_9 = _out_romask_T_9; // @[RegisterRouter.scala:87:24] wire out_womask_9 = _out_womask_T_9; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_9 = out_rivalid_9 & out_rimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_96 = out_f_rivalid_9; // @[RegisterRouter.scala:87:24] wire out_f_roready_9 = out_roready_9 & out_romask_9; // @[RegisterRouter.scala:87:24] wire _out_T_97 = out_f_roready_9; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_9 = out_wivalid_9 & out_wimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_98 = out_f_wivalid_9; // @[RegisterRouter.scala:87:24] wire out_f_woready_9 = out_woready_9 & out_womask_9; // @[RegisterRouter.scala:87:24] wire _out_T_99 = out_f_woready_9; // @[RegisterRouter.scala:87:24] wire _out_T_95 = out_front_bits_data[32]; // @[RegisterRouter.scala:87:24] wire _out_T_139 = out_front_bits_data[32]; // @[RegisterRouter.scala:87:24] wire _out_T_100 = ~out_rimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_101 = ~out_wimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_102 = ~out_romask_9; // @[RegisterRouter.scala:87:24] wire _out_T_103 = ~out_womask_9; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_7 = {12'h0, _out_T_94}; // @[RegisterRouter.scala:87:24] wire [32:0] out_prepend_7 = {rxen, _out_prepend_T_7}; // @[RegisterRouter.scala:87:24] wire [32:0] _out_T_104 = out_prepend_7; // @[RegisterRouter.scala:87:24] wire [32:0] _out_T_105 = _out_T_104; // @[RegisterRouter.scala:87:24] wire [3:0] _out_rimask_T_10 = out_frontMask[51:48]; // @[RegisterRouter.scala:87:24] wire [3:0] _out_wimask_T_10 = out_frontMask[51:48]; // @[RegisterRouter.scala:87:24] wire out_rimask_10 = \|_out_rimask_T_10; // @[RegisterRouter.scala:87:24] wire out_wimask_10 = &_out_wimask_T_10; // @[RegisterRouter.scala:87:24] wire [3:0] _out_romask_T_10 = out_backMask[51:48]; // @[RegisterRouter.scala:87:24] wire [3:0] _out_womask_T_10 = out_backMask[51:48]; // @[RegisterRouter.scala:87:24] wire out_romask_10 = \|_out_romask_T_10; // @[RegisterRouter.scala:87:24] wire out_womask_10 = &_out_womask_T_10; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_10 = out_rivalid_10 & out_rimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_107 = out_f_rivalid_10; // @[RegisterRouter.scala:87:24] wire out_f_roready_10 = out_roready_10 & out_romask_10; // @[RegisterRouter.scala:87:24] wire _out_T_108 = out_f_roready_10; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_10 = out_wivalid_10 & out_wimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_109 = out_f_wivalid_10; // @[RegisterRouter.scala:87:24] wire out_f_woready_10 = out_woready_10 & out_womask_10; // @[RegisterRouter.scala:87:24] wire _out_T_110 = out_f_woready_10; // @[RegisterRouter.scala:87:24] wire [3:0] _out_T_106 = out_front_bits_data[51:48]; // @[RegisterRouter.scala:87:24] wire _out_T_111 = ~out_rimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_112 = ~out_wimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_113 = ~out_romask_10; // @[RegisterRouter.scala:87:24] wire _out_T_114 = ~out_womask_10; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_8 = {15'h0, _out_T_105}; // @[RegisterRouter.scala:87:24] wire [51:0] out_prepend_8 = {rxwm, _out_prepend_T_8}; // @[RegisterRouter.scala:87:24] wire [51:0] _out_T_115 = out_prepend_8; // @[RegisterRouter.scala:87:24] wire [51:0] _out_T_116 = _out_T_115; // @[RegisterRouter.scala:87:24] wire out_rimask_11 = _out_rimask_T_11; // @[RegisterRouter.scala:87:24] wire out_wimask_11 = _out_wimask_T_11; // @[RegisterRouter.scala:87:24] wire out_romask_11 = _out_romask_T_11; // @[RegisterRouter.scala:87:24] wire out_womask_11 = _out_womask_T_11; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_11 = out_rivalid_11 & out_rimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_118 = out_f_rivalid_11; // @[RegisterRouter.scala:87:24] wire out_f_roready_11 = out_roready_11 & out_romask_11; // @[RegisterRouter.scala:87:24] wire _out_T_119 = out_f_roready_11; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_11 = out_wivalid_11 & out_wimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_120 = out_f_wivalid_11; // @[RegisterRouter.scala:87:24] wire out_f_woready_11 = out_woready_11 & out_womask_11; // @[RegisterRouter.scala:87:24] wire _out_T_121 = out_f_woready_11; // @[RegisterRouter.scala:87:24] wire _out_T_122 = ~out_rimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_123 = ~out_wimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_124 = ~out_romask_11; // @[RegisterRouter.scala:87:24] wire _out_T_125 = ~out_womask_11; // @[RegisterRouter.scala:87:24] wire _out_T_127 = _out_T_126; // @[RegisterRouter.scala:87:24] wire _out_prepend_T_9 = _out_T_127; // @[RegisterRouter.scala:87:24] wire out_rimask_12 = _out_rimask_T_12; // @[RegisterRouter.scala:87:24] wire out_wimask_12 = _out_wimask_T_12; // @[RegisterRouter.scala:87:24] wire out_romask_12 = _out_romask_T_12; // @[RegisterRouter.scala:87:24] wire out_womask_12 = _out_womask_T_12; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_12 = out_rivalid_12 & out_rimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_129 = out_f_rivalid_12; // @[RegisterRouter.scala:87:24] wire out_f_roready_12 = out_roready_12 & out_romask_12; // @[RegisterRouter.scala:87:24] wire _out_T_130 = out_f_roready_12; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_12 = out_wivalid_12 & out_wimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_131 = out_f_wivalid_12; // @[RegisterRouter.scala:87:24] wire out_f_woready_12 = out_woready_12 & out_womask_12; // @[RegisterRouter.scala:87:24] wire _out_T_132 = out_f_woready_12; // @[RegisterRouter.scala:87:24] wire _out_T_133 = ~out_rimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_134 = ~out_wimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_135 = ~out_romask_12; // @[RegisterRouter.scala:87:24] wire _out_T_136 = ~out_womask_12; // @[RegisterRouter.scala:87:24] wire [1:0] out_prepend_9 = {ie_rxwm, _out_prepend_T_9}; // @[RegisterRouter.scala:87:24] wire [1:0] _out_T_137 = out_prepend_9; // @[RegisterRouter.scala:87:24] wire [1:0] _out_T_138 = _out_T_137; // @[RegisterRouter.scala:87:24] wire out_rimask_13 = _out_rimask_T_13; // @[RegisterRouter.scala:87:24] wire out_wimask_13 = _out_wimask_T_13; // @[RegisterRouter.scala:87:24] wire out_romask_13 = _out_romask_T_13; // @[RegisterRouter.scala:87:24] wire out_womask_13 = _out_womask_T_13; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_13 = out_rivalid_13 & out_rimask_13; // @[RegisterRouter.scala:87:24] wire _out_T_140 = out_f_rivalid_13; // @[RegisterRouter.scala:87:24] wire out_f_roready_13 = out_roready_13 & out_romask_13; // @[RegisterRouter.scala:87:24] wire _out_T_141 = out_f_roready_13; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_13 = out_wivalid_13 & out_wimask_13; // @[RegisterRouter.scala:87:24] wire out_f_woready_13 = out_woready_13 & out_womask_13; // @[RegisterRouter.scala:87:24] wire _out_T_142 = ~out_rimask_13; // @[RegisterRouter.scala:87:24] wire _out_T_143 = ~out_wimask_13; // @[RegisterRouter.scala:87:24] wire _out_T_144 = ~out_romask_13; // @[RegisterRouter.scala:87:24] wire _out_T_145 = ~out_womask_13; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_10 = {30'h0, _out_T_138}; // @[RegisterRouter.scala:87:24] wire [32:0] out_prepend_10 = {ip_txwm, _out_prepend_T_10}; // @[RegisterRouter.scala:87:24] wire [32:0] _out_T_146 = out_prepend_10; // @[RegisterRouter.scala:87:24] wire [32:0] _out_T_147 = _out_T_146; // @[RegisterRouter.scala:87:24] wire [32:0] _out_prepend_T_11 = _out_T_147; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_14 = out_frontMask[33]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_14 = out_frontMask[33]; // @[RegisterRouter.scala:87:24] wire out_rimask_14 = _out_rimask_T_14; // @[RegisterRouter.scala:87:24] wire out_wimask_14 = _out_wimask_T_14; // @[RegisterRouter.scala:87:24] wire _out_romask_T_14 = out_backMask[33]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_14 = out_backMask[33]; // @[RegisterRouter.scala:87:24] wire out_romask_14 = _out_romask_T_14; // @[RegisterRouter.scala:87:24] wire out_womask_14 = _out_womask_T_14; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_14 = out_rivalid_14 & out_rimask_14; // @[RegisterRouter.scala:87:24] wire _out_T_149 = out_f_rivalid_14; // @[RegisterRouter.scala:87:24] wire out_f_roready_14 = out_roready_14 & out_romask_14; // @[RegisterRouter.scala:87:24] wire _out_T_150 = out_f_roready_14; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_14 = out_wivalid_14 & out_wimask_14; // @[RegisterRouter.scala:87:24] wire out_f_woready_14 = out_woready_14 & out_womask_14; // @[RegisterRouter.scala:87:24] wire _out_T_148 = out_front_bits_data[33]; // @[RegisterRouter.scala:87:24] wire _out_T_151 = ~out_rimask_14; // @[RegisterRouter.scala:87:24] wire _out_T_152 = ~out_wimask_14; // @[RegisterRouter.scala:87:24] wire _out_T_153 = ~out_romask_14; // @[RegisterRouter.scala:87:24] wire _out_T_154 = ~out_womask_14; // @[RegisterRouter.scala:87:24] wire [33:0] out_prepend_11 = {ip_rxwm, _out_prepend_T_11}; // @[RegisterRouter.scala:87:24] wire [33:0] _out_T_155 = out_prepend_11; // @[RegisterRouter.scala:87:24] wire [33:0] _out_T_156 = _out_T_155; // @[RegisterRouter.scala:87:24] wire [15:0] _out_rimask_T_15 = out_frontMask[15:0]; // @[RegisterRouter.scala:87:24] wire [15:0] _out_wimask_T_15 = out_frontMask[15:0]; // @[RegisterRouter.scala:87:24] wire out_rimask_15 = \|_out_rimask_T_15; // @[RegisterRouter.scala:87:24] wire out_wimask_15 = &_out_wimask_T_15; // @[RegisterRouter.scala:87:24] wire [15:0] _out_romask_T_15 = out_backMask[15:0]; // @[RegisterRouter.scala:87:24] wire [15:0] _out_womask_T_15 = out_backMask[15:0]; // @[RegisterRouter.scala:87:24] wire out_romask_15 = \|_out_romask_T_15; // @[RegisterRouter.scala:87:24] wire out_womask_15 = &_out_womask_T_15; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_15 = out_rivalid_15 & out_rimask_15; // @[RegisterRouter.scala:87:24] wire _out_T_158 = out_f_rivalid_15; // @[RegisterRouter.scala:87:24] wire out_f_roready_15 = out_roready_15 & out_romask_15; // @[RegisterRouter.scala:87:24] wire _out_T_159 = out_f_roready_15; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_15 = out_wivalid_15 & out_wimask_15; // @[RegisterRouter.scala:87:24] wire _out_T_160 = out_f_wivalid_15; // @[RegisterRouter.scala:87:24] wire out_f_woready_15 = out_woready_15 & out_womask_15; // @[RegisterRouter.scala:87:24] wire _out_T_161 = out_f_woready_15; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_157 = out_front_bits_data[15:0]; // @[RegisterRouter.scala:87:24] wire _out_T_162 = ~out_rimask_15; // @[RegisterRouter.scala:87:24] wire _out_T_163 = ~out_wimask_15; // @[RegisterRouter.scala:87:24] wire _out_T_164 = ~out_romask_15; // @[RegisterRouter.scala:87:24] wire _out_T_165 = ~out_womask_15; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_167 = _out_T_166; // @[RegisterRouter.scala:87:24] wire _out_iindex_T = out_front_bits_index[0]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T = out_front_bits_index[0]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_1 = out_front_bits_index[1]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_1 = out_front_bits_index[1]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_2 = out_front_bits_index[2]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_2 = out_front_bits_index[2]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_3 = out_front_bits_index[3]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_3 = out_front_bits_index[3]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_4 = out_front_bits_index[4]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_4 = out_front_bits_index[4]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_5 = out_front_bits_index[5]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_5 = out_front_bits_index[5]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_6 = out_front_bits_index[6]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_6 = out_front_bits_index[6]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_7 = out_front_bits_index[7]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_7 = out_front_bits_index[7]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_8 = out_front_bits_index[8]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_8 = out_front_bits_index[8]; // @[RegisterRouter.scala:87:24] wire [1:0] out_iindex = {_out_iindex_T_1, _out_iindex_T}; // @[RegisterRouter.scala:87:24] wire [1:0] out_oindex = {_out_oindex_T_1, _out_oindex_T}; // @[RegisterRouter.scala:87:24] wire [3:0] _out_frontSel_T = 4'h1 << out_iindex; // @[OneHot.scala:58:35] wire out_frontSel_0 = _out_frontSel_T[0]; // @[OneHot.scala:58:35] wire out_frontSel_1 = _out_frontSel_T[1]; // @[OneHot.scala:58:35] wire out_frontSel_2 = _out_frontSel_T[2]; // @[OneHot.scala:58:35] wire out_frontSel_3 = _out_frontSel_T[3]; // @[OneHot.scala:58:35] wire [3:0] _out_backSel_T = 4'h1 << out_oindex; // @[OneHot.scala:58:35] wire out_backSel_0 = _out_backSel_T[0]; // @[OneHot.scala:58:35] wire out_backSel_1 = _out_backSel_T[1]; // @[OneHot.scala:58:35] wire out_backSel_2 = _out_backSel_T[2]; // @[OneHot.scala:58:35] wire out_backSel_3 = _out_backSel_T[3]; // @[OneHot.scala:58:35] wire _GEN_2 = in_valid & out_front_ready; // @[RegisterRouter.scala:73:18, :87:24] wire _out_rifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T = _GEN_2; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T = _GEN_2; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1 = _out_rifireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_2 = _out_rifireMux_T_1 & out_frontSel_0; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_3 = _out_rifireMux_T_2 & _out_T; // @[RegisterRouter.scala:87:24] assign out_rivalid_0 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_1 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_2 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_3 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_4 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_5 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_4 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_6 = _out_rifireMux_T_1 & out_frontSel_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_7 = _out_rifireMux_T_6 & _out_T_2; // @[RegisterRouter.scala:87:24] assign out_rivalid_6 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_7 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_8 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_9 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_10 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_8 = ~_out_T_2; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_10 = _out_rifireMux_T_1 & out_frontSel_2; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_11 = _out_rifireMux_T_10 & _out_T_4; // @[RegisterRouter.scala:87:24] assign out_rivalid_11 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_12 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_13 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_14 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_12 = ~_out_T_4; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_14 = _out_rifireMux_T_1 & out_frontSel_3; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_15 = _out_rifireMux_T_14 & _out_T_6; // @[RegisterRouter.scala:87:24] assign out_rivalid_15 = _out_rifireMux_T_15; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_16 = ~_out_T_6; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_2 = _out_wifireMux_T & _out_wifireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_3 = _out_wifireMux_T_2 & out_frontSel_0; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_4 = _out_wifireMux_T_3 & _out_T; // @[RegisterRouter.scala:87:24] assign out_wivalid_0 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_1 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_2 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_3 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_4 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_5 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_5 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_7 = _out_wifireMux_T_2 & out_frontSel_1; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_8 = _out_wifireMux_T_7 & _out_T_2; // @[RegisterRouter.scala:87:24] assign out_wivalid_6 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_7 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_8 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_9 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_10 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_9 = ~_out_T_2; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_11 = _out_wifireMux_T_2 & out_frontSel_2; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_12 = _out_wifireMux_T_11 & _out_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_11 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_12 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_13 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_14 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_13 = ~_out_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_15 = _out_wifireMux_T_2 & out_frontSel_3; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_16 = _out_wifireMux_T_15 & _out_T_6; // @[RegisterRouter.scala:87:24] assign out_wivalid_15 = _out_wifireMux_T_16; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_17 = ~_out_T_6; // @[RegisterRouter.scala:87:24] wire _GEN_3 = out_front_valid & out_ready; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T = _GEN_3; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T = _GEN_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1 = _out_rofireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_2 = _out_rofireMux_T_1 & out_backSel_0; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_3 = _out_rofireMux_T_2 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_roready_0 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_1 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_2 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_3 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_4 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_5 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_4 = ~_out_T_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_6 = _out_rofireMux_T_1 & out_backSel_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_7 = _out_rofireMux_T_6 & _out_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_6 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_7 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_8 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_9 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_10 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_8 = ~_out_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_10 = _out_rofireMux_T_1 & out_backSel_2; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_11 = _out_rofireMux_T_10 & _out_T_5; // @[RegisterRouter.scala:87:24] assign out_roready_11 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_12 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_13 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_14 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_12 = ~_out_T_5; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_14 = _out_rofireMux_T_1 & out_backSel_3; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_15 = _out_rofireMux_T_14 & _out_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_15 = _out_rofireMux_T_15; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_16 = ~_out_T_7; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_2 = _out_wofireMux_T & _out_wofireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_3 = _out_wofireMux_T_2 & out_backSel_0; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_4 = _out_wofireMux_T_3 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_woready_0 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_1 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_2 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_3 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_4 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_5 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_5 = ~_out_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_7 = _out_wofireMux_T_2 & out_backSel_1; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_8 = _out_wofireMux_T_7 & _out_T_3; // @[RegisterRouter.scala:87:24] assign out_woready_6 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_7 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_8 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_9 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_10 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_9 = ~_out_T_3; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_11 = _out_wofireMux_T_2 & out_backSel_2; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_12 = _out_wofireMux_T_11 & _out_T_5; // @[RegisterRouter.scala:87:24] assign out_woready_11 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_12 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_13 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_14 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_13 = ~_out_T_5; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_15 = _out_wofireMux_T_2 & out_backSel_3; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_16 = _out_wofireMux_T_15 & _out_T_7; // @[RegisterRouter.scala:87:24] assign out_woready_15 = _out_wofireMux_T_16; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_17 = ~_out_T_7; // @[RegisterRouter.scala:87:24] assign in_ready = _out_in_ready_T; // @[RegisterRouter.scala:73:18, :87:24] assign out_front_valid = _out_front_valid_T; // @[RegisterRouter.scala:87:24] assign out_front_ready = _out_front_ready_T; // @[RegisterRouter.scala:87:24] assign out_valid = _out_out_valid_T; // @[RegisterRouter.scala:87:24] wire [3:0] _GEN_4 = {{_out_out_bits_data_WIRE_3}, {_out_out_bits_data_WIRE_2}, {_out_out_bits_data_WIRE_1}, {_out_out_bits_data_WIRE_0}}; // @[MuxLiteral.scala:49:{10,48}] wire _out_out_bits_data_T_1 = _GEN_4[out_oindex]; // @[MuxLiteral.scala:49:10] wire [63:0] _out_out_bits_data_WIRE_1_1 = {12'h0, _out_T_116}; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_1_2 = {30'h0, _out_T_156}; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_1_3 = {48'h0, _out_T_167}; // @[MuxLiteral.scala:49:48] wire [3:0][63:0] _GEN_5 = {{_out_out_bits_data_WIRE_1_3}, {_out_out_bits_data_WIRE_1_2}, {_out_out_bits_data_WIRE_1_1}, {_out_out_bits_data_WIRE_1_0}}; // @[MuxLiteral.scala:49:{10,48}] wire [63:0] _out_out_bits_data_T_3 = _GEN_5[out_oindex]; // @[MuxLiteral.scala:49:10] assign _out_out_bits_data_T_4 = _out_out_bits_data_T_1 ? _out_out_bits_data_T_3 : 64'h0; // @[MuxLiteral.scala:49:10] assign out_bits_data = _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24] assign controlNodeIn_d_bits_size = controlNodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign controlNodeIn_d_bits_source = controlNodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign controlNodeIn_d_bits_opcode = {2'h0, _controlNodeIn_d_bits_opcode_T}; // @[RegisterRouter.scala:105:{19,25}] always @(posedge clock) begin // @[UART.scala:127:25] if (reset) begin // @[UART.scala:127:25] div <= 16'h10F4; // @[UART.scala:135:20] txen <= 1'h0; // @[UART.scala:141:21] rxen <= 1'h0; // @[UART.scala:142:21] txwm <= 4'h0; // @[UART.scala:149:21] rxwm <= 4'h0; // @[UART.scala:150:21] nstop <= 1'h0; // @[UART.scala:151:22] ie_rxwm <= 1'h0; // @[UART.scala:186:19] ie_txwm <= 1'h0; // @[UART.scala:186:19] end else begin // @[UART.scala:127:25] if (out_f_woready_15) // @[RegisterRouter.scala:87:24] div <= _out_T_157; // @[RegisterRouter.scala:87:24] if (out_f_woready_6) // @[RegisterRouter.scala:87:24] txen <= _out_T_62; // @[RegisterRouter.scala:87:24] if (out_f_woready_9) // @[RegisterRouter.scala:87:24] rxen <= _out_T_95; // @[RegisterRouter.scala:87:24] if (out_f_woready_8) // @[RegisterRouter.scala:87:24] txwm <= _out_T_84; // @[RegisterRouter.scala:87:24] if (out_f_woready_10) // @[RegisterRouter.scala:87:24] rxwm <= _out_T_106; // @[RegisterRouter.scala:87:24] if (out_f_woready_7) // @[RegisterRouter.scala:87:24] nstop <= _out_T_73; // @[RegisterRouter.scala:87:24] if (out_f_woready_12) // @[RegisterRouter.scala:87:24] ie_rxwm <= _out_T_128; // @[RegisterRouter.scala:87:24] if (out_f_woready_11) // @[RegisterRouter.scala:87:24] ie_txwm <= _out_T_117; // @[RegisterRouter.scala:87:24] end always @(posedge) IntSyncCrossingSource_n1x1_5 intsource ( // @[Crossing.scala:29:31] .clock (clock), .reset (reset), .auto_in_0 (intnodeOut_0), // @[MixedNode.scala:542:17] .auto_out_sync_0 (intXingIn_sync_0) ); // @[Crossing.scala:29:31] TLMonitor_60 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (controlNodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (controlNodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (controlNodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (controlNodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (controlNodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (controlNodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (controlNodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (controlNodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (controlNodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (controlNodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (controlNodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (controlNodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (controlNodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_size (controlNodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (controlNodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_data (controlNodeIn_d_bits_data) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] UARTTx txm ( // @[UART.scala:129:19] .clock (clock), .reset (reset), .io_en (txen), // @[UART.scala:141:21] .io_in_ready (_txm_io_in_ready), .io_in_valid (_txq_io_deq_valid), // @[UART.scala:130:19] .io_in_bits (_txq_io_deq_bits), // @[UART.scala:130:19] .io_out (ioNodeOut_txd), .io_div (div), // @[UART.scala:135:20] .io_nstop (nstop), // @[UART.scala:151:22] .io_tx_busy (_txm_io_tx_busy) ); // @[UART.scala:129:19] Queue8_UInt8 txq ( // @[UART.scala:130:19] .clock (clock), .reset (reset), .io_enq_ready (_txq_io_enq_ready), .io_enq_valid (_out_txq_io_enq_valid_T_1), // @[RegMapFIFO.scala:18:30] .io_enq_bits (_out_T_8), // @[RegisterRouter.scala:87:24] .io_deq_ready (_txm_io_in_ready), // @[UART.scala:129:19] .io_deq_valid (_txq_io_deq_valid), .io_deq_bits (_txq_io_deq_bits), .io_count (_txq_io_count) ); // @[UART.scala:130:19] UARTRx rxm ( // @[UART.scala:132:19] .clock (clock), .reset (reset), .io_en (rxen), // @[UART.scala:142:21] .io_in (ioNodeOut_rxd), // @[MixedNode.scala:542:17] .io_out_valid (_rxm_io_out_valid), .io_out_bits (_rxm_io_out_bits), .io_div (div) // @[UART.scala:135:20] ); // @[UART.scala:132:19] Queue8_UInt8_1 rxq ( // @[UART.scala:133:19] .clock (clock), .reset (reset), .io_enq_valid (_rxm_io_out_valid), // @[UART.scala:132:19] .io_enq_bits (_rxm_io_out_bits), // @[UART.scala:132:19] .io_deq_ready (out_f_roready_3), // @[RegisterRouter.scala:87:24] .io_deq_valid (_rxq_io_deq_valid), .io_deq_bits (_rxq_io_deq_bits), .io_count (_rxq_io_count) ); // @[UART.scala:133:19] assign auto_int_xing_out_sync_0 = auto_int_xing_out_sync_0_0; // @[UART.scala:127:25] assign auto_control_xing_in_a_ready = auto_control_xing_in_a_ready_0; // @[UART.scala:127:25] assign auto_control_xing_in_d_valid = auto_control_xing_in_d_valid_0; // @[UART.scala:127:25] assign auto_control_xing_in_d_bits_opcode = auto_control_xing_in_d_bits_opcode_0; // @[UART.scala:127:25] assign auto_control_xing_in_d_bits_size = auto_control_xing_in_d_bits_size_0; // @[UART.scala:127:25] assign auto_control_xing_in_d_bits_source = auto_control_xing_in_d_bits_source_0; // @[UART.scala:127:25] assign auto_control_xing_in_d_bits_data = auto_control_xing_in_d_bits_data_0; // @[UART.scala:127:25] assign auto_io_out_txd = auto_io_out_txd_0; // @[UART.scala:127:25] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_45 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, b : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _source_ok_T_29 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _source_ok_T_30 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _source_ok_T_31 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_32 = eq(io.in.a.bits.source, UInt<6>(0h22)) wire _source_ok_WIRE : UInt<1>[13] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 connect _source_ok_WIRE[8], _source_ok_T_28 connect _source_ok_WIRE[9], _source_ok_T_29 connect _source_ok_WIRE[10], _source_ok_T_30 connect _source_ok_WIRE[11], _source_ok_T_31 connect _source_ok_WIRE[12], _source_ok_T_32 node _source_ok_T_33 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_34 = or(_source_ok_T_33, _source_ok_WIRE[2]) node _source_ok_T_35 = or(_source_ok_T_34, _source_ok_WIRE[3]) node _source_ok_T_36 = or(_source_ok_T_35, _source_ok_WIRE[4]) node _source_ok_T_37 = or(_source_ok_T_36, _source_ok_WIRE[5]) node _source_ok_T_38 = or(_source_ok_T_37, _source_ok_WIRE[6]) node _source_ok_T_39 = or(_source_ok_T_38, _source_ok_WIRE[7]) node _source_ok_T_40 = or(_source_ok_T_39, _source_ok_WIRE[8]) node _source_ok_T_41 = or(_source_ok_T_40, _source_ok_WIRE[9]) node _source_ok_T_42 = or(_source_ok_T_41, _source_ok_WIRE[10]) node _source_ok_T_43 = or(_source_ok_T_42, _source_ok_WIRE[11]) node source_ok = or(_source_ok_T_43, _source_ok_WIRE[12]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _T_88 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_89 = eq(_T_88, UInt<1>(0h0)) node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_89, _T_94) node _T_96 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_99 = cvt(_T_98) node _T_100 = and(_T_99, asSInt(UInt<1>(0h0))) node _T_101 = asSInt(_T_100) node _T_102 = eq(_T_101, asSInt(UInt<1>(0h0))) node _T_103 = or(_T_97, _T_102) node _T_104 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_105 = eq(_T_104, UInt<1>(0h0)) node _T_106 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_107 = cvt(_T_106) node _T_108 = and(_T_107, asSInt(UInt<1>(0h0))) node _T_109 = asSInt(_T_108) node _T_110 = eq(_T_109, asSInt(UInt<1>(0h0))) node _T_111 = or(_T_105, _T_110) node _T_112 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_113 = eq(_T_112, UInt<1>(0h0)) node _T_114 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_115 = cvt(_T_114) node _T_116 = and(_T_115, asSInt(UInt<1>(0h0))) node _T_117 = asSInt(_T_116) node _T_118 = eq(_T_117, asSInt(UInt<1>(0h0))) node _T_119 = or(_T_113, _T_118) node _T_120 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_121 = eq(_T_120, UInt<1>(0h0)) node _T_122 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_123 = cvt(_T_122) node _T_124 = and(_T_123, asSInt(UInt<1>(0h0))) node _T_125 = asSInt(_T_124) node _T_126 = eq(_T_125, asSInt(UInt<1>(0h0))) node _T_127 = or(_T_121, _T_126) node _T_128 = and(_T_11, _T_24) node _T_129 = and(_T_128, _T_37) node _T_130 = and(_T_129, _T_50) node _T_131 = and(_T_130, _T_63) node _T_132 = and(_T_131, _T_71) node _T_133 = and(_T_132, _T_79) node _T_134 = and(_T_133, _T_87) node _T_135 = and(_T_134, _T_95) node _T_136 = and(_T_135, _T_103) node _T_137 = and(_T_136, _T_111) node _T_138 = and(_T_137, _T_119) node _T_139 = and(_T_138, _T_127) node _T_140 = asUInt(reset) node _T_141 = eq(_T_140, UInt<1>(0h0)) when _T_141 : node _T_142 = eq(_T_139, UInt<1>(0h0)) when _T_142 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_139, UInt<1>(0h1), "") : assert_1 node _T_143 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_143 : node _T_144 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_145 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_146 = and(_T_144, _T_145) node _T_147 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_148 = shr(io.in.a.bits.source, 2) node _T_149 = eq(_T_148, UInt<1>(0h0)) node _T_150 = leq(UInt<1>(0h0), uncommonBits_4) node _T_151 = and(_T_149, _T_150) node _T_152 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_153 = and(_T_151, _T_152) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_154 = shr(io.in.a.bits.source, 2) node _T_155 = eq(_T_154, UInt<1>(0h1)) node _T_156 = leq(UInt<1>(0h0), uncommonBits_5) node _T_157 = and(_T_155, _T_156) node _T_158 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_159 = and(_T_157, _T_158) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_160 = shr(io.in.a.bits.source, 2) node _T_161 = eq(_T_160, UInt<2>(0h2)) node _T_162 = leq(UInt<1>(0h0), uncommonBits_6) node _T_163 = and(_T_161, _T_162) node _T_164 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_165 = and(_T_163, _T_164) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_166 = shr(io.in.a.bits.source, 2) node _T_167 = eq(_T_166, UInt<2>(0h3)) node _T_168 = leq(UInt<1>(0h0), uncommonBits_7) node _T_169 = and(_T_167, _T_168) node _T_170 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_171 = and(_T_169, _T_170) node _T_172 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_173 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_174 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_175 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_176 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_177 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_178 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_179 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_180 = or(_T_147, _T_153) node _T_181 = or(_T_180, _T_159) node _T_182 = or(_T_181, _T_165) node _T_183 = or(_T_182, _T_171) node _T_184 = or(_T_183, _T_172) node _T_185 = or(_T_184, _T_173) node _T_186 = or(_T_185, _T_174) node _T_187 = or(_T_186, _T_175) node _T_188 = or(_T_187, _T_176) node _T_189 = or(_T_188, _T_177) node _T_190 = or(_T_189, _T_178) node _T_191 = or(_T_190, _T_179) node _T_192 = and(_T_146, _T_191) node _T_193 = or(UInt<1>(0h0), _T_192) node _T_194 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_195 = or(UInt<1>(0h0), _T_194) node _T_196 = xor(io.in.a.bits.address, UInt<28>(0h8000040)) node _T_197 = cvt(_T_196) node _T_198 = and(_T_197, asSInt(UInt<17>(0h100c0))) node _T_199 = asSInt(_T_198) node _T_200 = eq(_T_199, asSInt(UInt<1>(0h0))) node _T_201 = xor(io.in.a.bits.address, UInt<32>(0h80000040)) node _T_202 = cvt(_T_201) node _T_203 = and(_T_202, asSInt(UInt<29>(0h100000c0))) node _T_204 = asSInt(_T_203) node _T_205 = eq(_T_204, asSInt(UInt<1>(0h0))) node _T_206 = or(_T_200, _T_205) node _T_207 = and(_T_195, _T_206) node _T_208 = or(UInt<1>(0h0), _T_207) node _T_209 = and(_T_193, _T_208) node _T_210 = asUInt(reset) node _T_211 = eq(_T_210, UInt<1>(0h0)) when _T_211 : node _T_212 = eq(_T_209, UInt<1>(0h0)) when _T_212 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_209, UInt<1>(0h1), "") : assert_2 node _T_213 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_214 = shr(io.in.a.bits.source, 2) node _T_215 = eq(_T_214, UInt<1>(0h0)) node _T_216 = leq(UInt<1>(0h0), uncommonBits_8) node _T_217 = and(_T_215, _T_216) node _T_218 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_219 = and(_T_217, _T_218) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_220 = shr(io.in.a.bits.source, 2) node _T_221 = eq(_T_220, UInt<1>(0h1)) node _T_222 = leq(UInt<1>(0h0), uncommonBits_9) node _T_223 = and(_T_221, _T_222) node _T_224 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_225 = and(_T_223, _T_224) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_226 = shr(io.in.a.bits.source, 2) node _T_227 = eq(_T_226, UInt<2>(0h2)) node _T_228 = leq(UInt<1>(0h0), uncommonBits_10) node _T_229 = and(_T_227, _T_228) node _T_230 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_231 = and(_T_229, _T_230) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_232 = shr(io.in.a.bits.source, 2) node _T_233 = eq(_T_232, UInt<2>(0h3)) node _T_234 = leq(UInt<1>(0h0), uncommonBits_11) node _T_235 = and(_T_233, _T_234) node _T_236 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_237 = and(_T_235, _T_236) node _T_238 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_239 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_240 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_241 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_242 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_243 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_244 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_245 = eq(io.in.a.bits.source, UInt<6>(0h22)) wire _WIRE : UInt<1>[13] connect _WIRE[0], _T_213 connect _WIRE[1], _T_219 connect _WIRE[2], _T_225 connect _WIRE[3], _T_231 connect _WIRE[4], _T_237 connect _WIRE[5], _T_238 connect _WIRE[6], _T_239 connect _WIRE[7], _T_240 connect _WIRE[8], _T_241 connect _WIRE[9], _T_242 connect _WIRE[10], _T_243 connect _WIRE[11], _T_244 connect _WIRE[12], _T_245 node _T_246 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_247 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_248 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_249 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_250 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_251 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_252 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_253 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_254 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_255 = mux(_WIRE[5], _T_246, UInt<1>(0h0)) node _T_256 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_257 = mux(_WIRE[7], _T_247, UInt<1>(0h0)) node _T_258 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_259 = mux(_WIRE[9], _T_248, UInt<1>(0h0)) node _T_260 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_261 = mux(_WIRE[11], _T_249, UInt<1>(0h0)) node _T_262 = mux(_WIRE[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_263 = or(_T_250, _T_251) node _T_264 = or(_T_263, _T_252) node _T_265 = or(_T_264, _T_253) node _T_266 = or(_T_265, _T_254) node _T_267 = or(_T_266, _T_255) node _T_268 = or(_T_267, _T_256) node _T_269 = or(_T_268, _T_257) node _T_270 = or(_T_269, _T_258) node _T_271 = or(_T_270, _T_259) node _T_272 = or(_T_271, _T_260) node _T_273 = or(_T_272, _T_261) node _T_274 = or(_T_273, _T_262) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_274 node _T_275 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_276 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_277 = and(_T_275, _T_276) node _T_278 = or(UInt<1>(0h0), _T_277) node _T_279 = xor(io.in.a.bits.address, UInt<28>(0h8000040)) node _T_280 = cvt(_T_279) node _T_281 = and(_T_280, asSInt(UInt<17>(0h100c0))) node _T_282 = asSInt(_T_281) node _T_283 = eq(_T_282, asSInt(UInt<1>(0h0))) node _T_284 = xor(io.in.a.bits.address, UInt<32>(0h80000040)) node _T_285 = cvt(_T_284) node _T_286 = and(_T_285, asSInt(UInt<29>(0h100000c0))) node _T_287 = asSInt(_T_286) node _T_288 = eq(_T_287, asSInt(UInt<1>(0h0))) node _T_289 = or(_T_283, _T_288) node _T_290 = and(_T_278, _T_289) node _T_291 = or(UInt<1>(0h0), _T_290) node _T_292 = and(_WIRE_1, _T_291) node _T_293 = asUInt(reset) node _T_294 = eq(_T_293, UInt<1>(0h0)) when _T_294 : node _T_295 = eq(_T_292, UInt<1>(0h0)) when _T_295 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_292, UInt<1>(0h1), "") : assert_3 node _T_296 = asUInt(reset) node _T_297 = eq(_T_296, UInt<1>(0h0)) when _T_297 : node _T_298 = eq(source_ok, UInt<1>(0h0)) when _T_298 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_299 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_T_299, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_299, UInt<1>(0h1), "") : assert_5 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(is_aligned, UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_306 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_307 = asUInt(reset) node _T_308 = eq(_T_307, UInt<1>(0h0)) when _T_308 : node _T_309 = eq(_T_306, UInt<1>(0h0)) when _T_309 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_306, UInt<1>(0h1), "") : assert_7 node _T_310 = not(io.in.a.bits.mask) node _T_311 = eq(_T_310, UInt<1>(0h0)) node _T_312 = asUInt(reset) node _T_313 = eq(_T_312, UInt<1>(0h0)) when _T_313 : node _T_314 = eq(_T_311, UInt<1>(0h0)) when _T_314 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_311, UInt<1>(0h1), "") : assert_8 node _T_315 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_316 = asUInt(reset) node _T_317 = eq(_T_316, UInt<1>(0h0)) when _T_317 : node _T_318 = eq(_T_315, UInt<1>(0h0)) when _T_318 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_315, UInt<1>(0h1), "") : assert_9 node _T_319 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_319 : node _T_320 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_321 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_322 = and(_T_320, _T_321) node _T_323 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_324 = shr(io.in.a.bits.source, 2) node _T_325 = eq(_T_324, UInt<1>(0h0)) node _T_326 = leq(UInt<1>(0h0), uncommonBits_12) node _T_327 = and(_T_325, _T_326) node _T_328 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_329 = and(_T_327, _T_328) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_330 = shr(io.in.a.bits.source, 2) node _T_331 = eq(_T_330, UInt<1>(0h1)) node _T_332 = leq(UInt<1>(0h0), uncommonBits_13) node _T_333 = and(_T_331, _T_332) node _T_334 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_335 = and(_T_333, _T_334) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_336 = shr(io.in.a.bits.source, 2) node _T_337 = eq(_T_336, UInt<2>(0h2)) node _T_338 = leq(UInt<1>(0h0), uncommonBits_14) node _T_339 = and(_T_337, _T_338) node _T_340 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_341 = and(_T_339, _T_340) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_342 = shr(io.in.a.bits.source, 2) node _T_343 = eq(_T_342, UInt<2>(0h3)) node _T_344 = leq(UInt<1>(0h0), uncommonBits_15) node _T_345 = and(_T_343, _T_344) node _T_346 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_347 = and(_T_345, _T_346) node _T_348 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_349 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_350 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_351 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_352 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_353 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_354 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_355 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_356 = or(_T_323, _T_329) node _T_357 = or(_T_356, _T_335) node _T_358 = or(_T_357, _T_341) node _T_359 = or(_T_358, _T_347) node _T_360 = or(_T_359, _T_348) node _T_361 = or(_T_360, _T_349) node _T_362 = or(_T_361, _T_350) node _T_363 = or(_T_362, _T_351) node _T_364 = or(_T_363, _T_352) node _T_365 = or(_T_364, _T_353) node _T_366 = or(_T_365, _T_354) node _T_367 = or(_T_366, _T_355) node _T_368 = and(_T_322, _T_367) node _T_369 = or(UInt<1>(0h0), _T_368) node _T_370 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_371 = or(UInt<1>(0h0), _T_370) node _T_372 = xor(io.in.a.bits.address, UInt<28>(0h8000040)) node _T_373 = cvt(_T_372) node _T_374 = and(_T_373, asSInt(UInt<17>(0h100c0))) node _T_375 = asSInt(_T_374) node _T_376 = eq(_T_375, asSInt(UInt<1>(0h0))) node _T_377 = xor(io.in.a.bits.address, UInt<32>(0h80000040)) node _T_378 = cvt(_T_377) node _T_379 = and(_T_378, asSInt(UInt<29>(0h100000c0))) node _T_380 = asSInt(_T_379) node _T_381 = eq(_T_380, asSInt(UInt<1>(0h0))) node _T_382 = or(_T_376, _T_381) node _T_383 = and(_T_371, _T_382) node _T_384 = or(UInt<1>(0h0), _T_383) node _T_385 = and(_T_369, _T_384) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_385, UInt<1>(0h1), "") : assert_10 node _T_389 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_390 = shr(io.in.a.bits.source, 2) node _T_391 = eq(_T_390, UInt<1>(0h0)) node _T_392 = leq(UInt<1>(0h0), uncommonBits_16) node _T_393 = and(_T_391, _T_392) node _T_394 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_395 = and(_T_393, _T_394) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_396 = shr(io.in.a.bits.source, 2) node _T_397 = eq(_T_396, UInt<1>(0h1)) node _T_398 = leq(UInt<1>(0h0), uncommonBits_17) node _T_399 = and(_T_397, _T_398) node _T_400 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_401 = and(_T_399, _T_400) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_402 = shr(io.in.a.bits.source, 2) node _T_403 = eq(_T_402, UInt<2>(0h2)) node _T_404 = leq(UInt<1>(0h0), uncommonBits_18) node _T_405 = and(_T_403, _T_404) node _T_406 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_407 = and(_T_405, _T_406) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_408 = shr(io.in.a.bits.source, 2) node _T_409 = eq(_T_408, UInt<2>(0h3)) node _T_410 = leq(UInt<1>(0h0), uncommonBits_19) node _T_411 = and(_T_409, _T_410) node _T_412 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_413 = and(_T_411, _T_412) node _T_414 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_415 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_416 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_417 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_418 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_419 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_420 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_421 = eq(io.in.a.bits.source, UInt<6>(0h22)) wire _WIRE_2 : UInt<1>[13] connect _WIRE_2[0], _T_389 connect _WIRE_2[1], _T_395 connect _WIRE_2[2], _T_401 connect _WIRE_2[3], _T_407 connect _WIRE_2[4], _T_413 connect _WIRE_2[5], _T_414 connect _WIRE_2[6], _T_415 connect _WIRE_2[7], _T_416 connect _WIRE_2[8], _T_417 connect _WIRE_2[9], _T_418 connect _WIRE_2[10], _T_419 connect _WIRE_2[11], _T_420 connect _WIRE_2[12], _T_421 node _T_422 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_423 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_424 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_425 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_426 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_427 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_428 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_429 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_430 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_431 = mux(_WIRE_2[5], _T_422, UInt<1>(0h0)) node _T_432 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_433 = mux(_WIRE_2[7], _T_423, UInt<1>(0h0)) node _T_434 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_435 = mux(_WIRE_2[9], _T_424, UInt<1>(0h0)) node _T_436 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_437 = mux(_WIRE_2[11], _T_425, UInt<1>(0h0)) node _T_438 = mux(_WIRE_2[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_439 = or(_T_426, _T_427) node _T_440 = or(_T_439, _T_428) node _T_441 = or(_T_440, _T_429) node _T_442 = or(_T_441, _T_430) node _T_443 = or(_T_442, _T_431) node _T_444 = or(_T_443, _T_432) node _T_445 = or(_T_444, _T_433) node _T_446 = or(_T_445, _T_434) node _T_447 = or(_T_446, _T_435) node _T_448 = or(_T_447, _T_436) node _T_449 = or(_T_448, _T_437) node _T_450 = or(_T_449, _T_438) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_450 node _T_451 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_452 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_453 = and(_T_451, _T_452) node _T_454 = or(UInt<1>(0h0), _T_453) node _T_455 = xor(io.in.a.bits.address, UInt<28>(0h8000040)) node _T_456 = cvt(_T_455) node _T_457 = and(_T_456, asSInt(UInt<17>(0h100c0))) node _T_458 = asSInt(_T_457) node _T_459 = eq(_T_458, asSInt(UInt<1>(0h0))) node _T_460 = xor(io.in.a.bits.address, UInt<32>(0h80000040)) node _T_461 = cvt(_T_460) node _T_462 = and(_T_461, asSInt(UInt<29>(0h100000c0))) node _T_463 = asSInt(_T_462) node _T_464 = eq(_T_463, asSInt(UInt<1>(0h0))) node _T_465 = or(_T_459, _T_464) node _T_466 = and(_T_454, _T_465) node _T_467 = or(UInt<1>(0h0), _T_466) node _T_468 = and(_WIRE_3, _T_467) node _T_469 = asUInt(reset) node _T_470 = eq(_T_469, UInt<1>(0h0)) when _T_470 : node _T_471 = eq(_T_468, UInt<1>(0h0)) when _T_471 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_468, UInt<1>(0h1), "") : assert_11 node _T_472 = asUInt(reset) node _T_473 = eq(_T_472, UInt<1>(0h0)) when _T_473 : node _T_474 = eq(source_ok, UInt<1>(0h0)) when _T_474 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_475 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_476 = asUInt(reset) node _T_477 = eq(_T_476, UInt<1>(0h0)) when _T_477 : node _T_478 = eq(_T_475, UInt<1>(0h0)) when _T_478 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_475, UInt<1>(0h1), "") : assert_13 node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(is_aligned, UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_482 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_482, UInt<1>(0h1), "") : assert_15 node _T_486 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_486, UInt<1>(0h1), "") : assert_16 node _T_490 = not(io.in.a.bits.mask) node _T_491 = eq(_T_490, UInt<1>(0h0)) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_491, UInt<1>(0h1), "") : assert_17 node _T_495 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_T_495, UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_495, UInt<1>(0h1), "") : assert_18 node _T_499 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_499 : node _T_500 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_501 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_502 = and(_T_500, _T_501) node _T_503 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_504 = shr(io.in.a.bits.source, 2) node _T_505 = eq(_T_504, UInt<1>(0h0)) node _T_506 = leq(UInt<1>(0h0), uncommonBits_20) node _T_507 = and(_T_505, _T_506) node _T_508 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_509 = and(_T_507, _T_508) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_510 = shr(io.in.a.bits.source, 2) node _T_511 = eq(_T_510, UInt<1>(0h1)) node _T_512 = leq(UInt<1>(0h0), uncommonBits_21) node _T_513 = and(_T_511, _T_512) node _T_514 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_515 = and(_T_513, _T_514) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_516 = shr(io.in.a.bits.source, 2) node _T_517 = eq(_T_516, UInt<2>(0h2)) node _T_518 = leq(UInt<1>(0h0), uncommonBits_22) node _T_519 = and(_T_517, _T_518) node _T_520 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_521 = and(_T_519, _T_520) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_522 = shr(io.in.a.bits.source, 2) node _T_523 = eq(_T_522, UInt<2>(0h3)) node _T_524 = leq(UInt<1>(0h0), uncommonBits_23) node _T_525 = and(_T_523, _T_524) node _T_526 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_527 = and(_T_525, _T_526) node _T_528 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_529 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_530 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_531 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_532 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_533 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_534 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_535 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_536 = or(_T_503, _T_509) node _T_537 = or(_T_536, _T_515) node _T_538 = or(_T_537, _T_521) node _T_539 = or(_T_538, _T_527) node _T_540 = or(_T_539, _T_528) node _T_541 = or(_T_540, _T_529) node _T_542 = or(_T_541, _T_530) node _T_543 = or(_T_542, _T_531) node _T_544 = or(_T_543, _T_532) node _T_545 = or(_T_544, _T_533) node _T_546 = or(_T_545, _T_534) node _T_547 = or(_T_546, _T_535) node _T_548 = and(_T_502, _T_547) node _T_549 = or(UInt<1>(0h0), _T_548) node _T_550 = asUInt(reset) node _T_551 = eq(_T_550, UInt<1>(0h0)) when _T_551 : node _T_552 = eq(_T_549, UInt<1>(0h0)) when _T_552 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_549, UInt<1>(0h1), "") : assert_19 node _T_553 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_554 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_555 = and(_T_553, _T_554) node _T_556 = or(UInt<1>(0h0), _T_555) node _T_557 = xor(io.in.a.bits.address, UInt<28>(0h8000040)) node _T_558 = cvt(_T_557) node _T_559 = and(_T_558, asSInt(UInt<17>(0h100c0))) node _T_560 = asSInt(_T_559) node _T_561 = eq(_T_560, asSInt(UInt<1>(0h0))) node _T_562 = xor(io.in.a.bits.address, UInt<32>(0h80000040)) node _T_563 = cvt(_T_562) node _T_564 = and(_T_563, asSInt(UInt<29>(0h100000c0))) node _T_565 = asSInt(_T_564) node _T_566 = eq(_T_565, asSInt(UInt<1>(0h0))) node _T_567 = or(_T_561, _T_566) node _T_568 = and(_T_556, _T_567) node _T_569 = or(UInt<1>(0h0), _T_568) node _T_570 = asUInt(reset) node _T_571 = eq(_T_570, UInt<1>(0h0)) when _T_571 : node _T_572 = eq(_T_569, UInt<1>(0h0)) when _T_572 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_569, UInt<1>(0h1), "") : assert_20 node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(source_ok, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_576 = asUInt(reset) node _T_577 = eq(_T_576, UInt<1>(0h0)) when _T_577 : node _T_578 = eq(is_aligned, UInt<1>(0h0)) when _T_578 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_579 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_580 = asUInt(reset) node _T_581 = eq(_T_580, UInt<1>(0h0)) when _T_581 : node _T_582 = eq(_T_579, UInt<1>(0h0)) when _T_582 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_579, UInt<1>(0h1), "") : assert_23 node _T_583 = eq(io.in.a.bits.mask, mask) node _T_584 = asUInt(reset) node _T_585 = eq(_T_584, UInt<1>(0h0)) when _T_585 : node _T_586 = eq(_T_583, UInt<1>(0h0)) when _T_586 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_583, UInt<1>(0h1), "") : assert_24 node _T_587 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_588 = asUInt(reset) node _T_589 = eq(_T_588, UInt<1>(0h0)) when _T_589 : node _T_590 = eq(_T_587, UInt<1>(0h0)) when _T_590 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_587, UInt<1>(0h1), "") : assert_25 node _T_591 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_591 : node _T_592 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_593 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_594 = and(_T_592, _T_593) node _T_595 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_596 = shr(io.in.a.bits.source, 2) node _T_597 = eq(_T_596, UInt<1>(0h0)) node _T_598 = leq(UInt<1>(0h0), uncommonBits_24) node _T_599 = and(_T_597, _T_598) node _T_600 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_601 = and(_T_599, _T_600) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_602 = shr(io.in.a.bits.source, 2) node _T_603 = eq(_T_602, UInt<1>(0h1)) node _T_604 = leq(UInt<1>(0h0), uncommonBits_25) node _T_605 = and(_T_603, _T_604) node _T_606 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_607 = and(_T_605, _T_606) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_608 = shr(io.in.a.bits.source, 2) node _T_609 = eq(_T_608, UInt<2>(0h2)) node _T_610 = leq(UInt<1>(0h0), uncommonBits_26) node _T_611 = and(_T_609, _T_610) node _T_612 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_613 = and(_T_611, _T_612) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_614 = shr(io.in.a.bits.source, 2) node _T_615 = eq(_T_614, UInt<2>(0h3)) node _T_616 = leq(UInt<1>(0h0), uncommonBits_27) node _T_617 = and(_T_615, _T_616) node _T_618 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_619 = and(_T_617, _T_618) node _T_620 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_621 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_622 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_623 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_624 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_625 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_626 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_627 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_628 = or(_T_595, _T_601) node _T_629 = or(_T_628, _T_607) node _T_630 = or(_T_629, _T_613) node _T_631 = or(_T_630, _T_619) node _T_632 = or(_T_631, _T_620) node _T_633 = or(_T_632, _T_621) node _T_634 = or(_T_633, _T_622) node _T_635 = or(_T_634, _T_623) node _T_636 = or(_T_635, _T_624) node _T_637 = or(_T_636, _T_625) node _T_638 = or(_T_637, _T_626) node _T_639 = or(_T_638, _T_627) node _T_640 = and(_T_594, _T_639) node _T_641 = or(UInt<1>(0h0), _T_640) node _T_642 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_643 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_644 = and(_T_642, _T_643) node _T_645 = or(UInt<1>(0h0), _T_644) node _T_646 = xor(io.in.a.bits.address, UInt<28>(0h8000040)) node _T_647 = cvt(_T_646) node _T_648 = and(_T_647, asSInt(UInt<17>(0h100c0))) node _T_649 = asSInt(_T_648) node _T_650 = eq(_T_649, asSInt(UInt<1>(0h0))) node _T_651 = xor(io.in.a.bits.address, UInt<32>(0h80000040)) node _T_652 = cvt(_T_651) node _T_653 = and(_T_652, asSInt(UInt<29>(0h100000c0))) node _T_654 = asSInt(_T_653) node _T_655 = eq(_T_654, asSInt(UInt<1>(0h0))) node _T_656 = or(_T_650, _T_655) node _T_657 = and(_T_645, _T_656) node _T_658 = or(UInt<1>(0h0), _T_657) node _T_659 = and(_T_641, _T_658) node _T_660 = asUInt(reset) node _T_661 = eq(_T_660, UInt<1>(0h0)) when _T_661 : node _T_662 = eq(_T_659, UInt<1>(0h0)) when _T_662 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_659, UInt<1>(0h1), "") : assert_26 node _T_663 = asUInt(reset) node _T_664 = eq(_T_663, UInt<1>(0h0)) when _T_664 : node _T_665 = eq(source_ok, UInt<1>(0h0)) when _T_665 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_666 = asUInt(reset) node _T_667 = eq(_T_666, UInt<1>(0h0)) when _T_667 : node _T_668 = eq(is_aligned, UInt<1>(0h0)) when _T_668 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_669 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_670 = asUInt(reset) node _T_671 = eq(_T_670, UInt<1>(0h0)) when _T_671 : node _T_672 = eq(_T_669, UInt<1>(0h0)) when _T_672 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_669, UInt<1>(0h1), "") : assert_29 node _T_673 = eq(io.in.a.bits.mask, mask) node _T_674 = asUInt(reset) node _T_675 = eq(_T_674, UInt<1>(0h0)) when _T_675 : node _T_676 = eq(_T_673, UInt<1>(0h0)) when _T_676 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_673, UInt<1>(0h1), "") : assert_30 node _T_677 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_677 : node _T_678 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_679 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_680 = and(_T_678, _T_679) node _T_681 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_682 = shr(io.in.a.bits.source, 2) node _T_683 = eq(_T_682, UInt<1>(0h0)) node _T_684 = leq(UInt<1>(0h0), uncommonBits_28) node _T_685 = and(_T_683, _T_684) node _T_686 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_687 = and(_T_685, _T_686) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_688 = shr(io.in.a.bits.source, 2) node _T_689 = eq(_T_688, UInt<1>(0h1)) node _T_690 = leq(UInt<1>(0h0), uncommonBits_29) node _T_691 = and(_T_689, _T_690) node _T_692 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_693 = and(_T_691, _T_692) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_694 = shr(io.in.a.bits.source, 2) node _T_695 = eq(_T_694, UInt<2>(0h2)) node _T_696 = leq(UInt<1>(0h0), uncommonBits_30) node _T_697 = and(_T_695, _T_696) node _T_698 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_699 = and(_T_697, _T_698) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_700 = shr(io.in.a.bits.source, 2) node _T_701 = eq(_T_700, UInt<2>(0h3)) node _T_702 = leq(UInt<1>(0h0), uncommonBits_31) node _T_703 = and(_T_701, _T_702) node _T_704 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_705 = and(_T_703, _T_704) node _T_706 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_707 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_708 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_709 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_710 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_711 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_712 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_713 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_714 = or(_T_681, _T_687) node _T_715 = or(_T_714, _T_693) node _T_716 = or(_T_715, _T_699) node _T_717 = or(_T_716, _T_705) node _T_718 = or(_T_717, _T_706) node _T_719 = or(_T_718, _T_707) node _T_720 = or(_T_719, _T_708) node _T_721 = or(_T_720, _T_709) node _T_722 = or(_T_721, _T_710) node _T_723 = or(_T_722, _T_711) node _T_724 = or(_T_723, _T_712) node _T_725 = or(_T_724, _T_713) node _T_726 = and(_T_680, _T_725) node _T_727 = or(UInt<1>(0h0), _T_726) node _T_728 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_729 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_730 = and(_T_728, _T_729) node _T_731 = or(UInt<1>(0h0), _T_730) node _T_732 = xor(io.in.a.bits.address, UInt<28>(0h8000040)) node _T_733 = cvt(_T_732) node _T_734 = and(_T_733, asSInt(UInt<17>(0h100c0))) node _T_735 = asSInt(_T_734) node _T_736 = eq(_T_735, asSInt(UInt<1>(0h0))) node _T_737 = xor(io.in.a.bits.address, UInt<32>(0h80000040)) node _T_738 = cvt(_T_737) node _T_739 = and(_T_738, asSInt(UInt<29>(0h100000c0))) node _T_740 = asSInt(_T_739) node _T_741 = eq(_T_740, asSInt(UInt<1>(0h0))) node _T_742 = or(_T_736, _T_741) node _T_743 = and(_T_731, _T_742) node _T_744 = or(UInt<1>(0h0), _T_743) node _T_745 = and(_T_727, _T_744) node _T_746 = asUInt(reset) node _T_747 = eq(_T_746, UInt<1>(0h0)) when _T_747 : node _T_748 = eq(_T_745, UInt<1>(0h0)) when _T_748 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_745, UInt<1>(0h1), "") : assert_31 node _T_749 = asUInt(reset) node _T_750 = eq(_T_749, UInt<1>(0h0)) when _T_750 : node _T_751 = eq(source_ok, UInt<1>(0h0)) when _T_751 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_752 = asUInt(reset) node _T_753 = eq(_T_752, UInt<1>(0h0)) when _T_753 : node _T_754 = eq(is_aligned, UInt<1>(0h0)) when _T_754 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_755 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_756 = asUInt(reset) node _T_757 = eq(_T_756, UInt<1>(0h0)) when _T_757 : node _T_758 = eq(_T_755, UInt<1>(0h0)) when _T_758 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_755, UInt<1>(0h1), "") : assert_34 node _T_759 = not(mask) node _T_760 = and(io.in.a.bits.mask, _T_759) node _T_761 = eq(_T_760, UInt<1>(0h0)) node _T_762 = asUInt(reset) node _T_763 = eq(_T_762, UInt<1>(0h0)) when _T_763 : node _T_764 = eq(_T_761, UInt<1>(0h0)) when _T_764 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_761, UInt<1>(0h1), "") : assert_35 node _T_765 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_765 : node _T_766 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_767 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_768 = and(_T_766, _T_767) node _T_769 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_770 = shr(io.in.a.bits.source, 2) node _T_771 = eq(_T_770, UInt<1>(0h0)) node _T_772 = leq(UInt<1>(0h0), uncommonBits_32) node _T_773 = and(_T_771, _T_772) node _T_774 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_775 = and(_T_773, _T_774) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_776 = shr(io.in.a.bits.source, 2) node _T_777 = eq(_T_776, UInt<1>(0h1)) node _T_778 = leq(UInt<1>(0h0), uncommonBits_33) node _T_779 = and(_T_777, _T_778) node _T_780 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_781 = and(_T_779, _T_780) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_782 = shr(io.in.a.bits.source, 2) node _T_783 = eq(_T_782, UInt<2>(0h2)) node _T_784 = leq(UInt<1>(0h0), uncommonBits_34) node _T_785 = and(_T_783, _T_784) node _T_786 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_787 = and(_T_785, _T_786) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_788 = shr(io.in.a.bits.source, 2) node _T_789 = eq(_T_788, UInt<2>(0h3)) node _T_790 = leq(UInt<1>(0h0), uncommonBits_35) node _T_791 = and(_T_789, _T_790) node _T_792 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_793 = and(_T_791, _T_792) node _T_794 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_795 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_796 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_797 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_798 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_799 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_800 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_801 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_802 = or(_T_769, _T_775) node _T_803 = or(_T_802, _T_781) node _T_804 = or(_T_803, _T_787) node _T_805 = or(_T_804, _T_793) node _T_806 = or(_T_805, _T_794) node _T_807 = or(_T_806, _T_795) node _T_808 = or(_T_807, _T_796) node _T_809 = or(_T_808, _T_797) node _T_810 = or(_T_809, _T_798) node _T_811 = or(_T_810, _T_799) node _T_812 = or(_T_811, _T_800) node _T_813 = or(_T_812, _T_801) node _T_814 = and(_T_768, _T_813) node _T_815 = or(UInt<1>(0h0), _T_814) node _T_816 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_817 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_818 = and(_T_816, _T_817) node _T_819 = or(UInt<1>(0h0), _T_818) node _T_820 = xor(io.in.a.bits.address, UInt<28>(0h8000040)) node _T_821 = cvt(_T_820) node _T_822 = and(_T_821, asSInt(UInt<17>(0h100c0))) node _T_823 = asSInt(_T_822) node _T_824 = eq(_T_823, asSInt(UInt<1>(0h0))) node _T_825 = xor(io.in.a.bits.address, UInt<32>(0h80000040)) node _T_826 = cvt(_T_825) node _T_827 = and(_T_826, asSInt(UInt<29>(0h100000c0))) node _T_828 = asSInt(_T_827) node _T_829 = eq(_T_828, asSInt(UInt<1>(0h0))) node _T_830 = or(_T_824, _T_829) node _T_831 = and(_T_819, _T_830) node _T_832 = or(UInt<1>(0h0), _T_831) node _T_833 = and(_T_815, _T_832) node _T_834 = asUInt(reset) node _T_835 = eq(_T_834, UInt<1>(0h0)) when _T_835 : node _T_836 = eq(_T_833, UInt<1>(0h0)) when _T_836 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_833, UInt<1>(0h1), "") : assert_36 node _T_837 = asUInt(reset) node _T_838 = eq(_T_837, UInt<1>(0h0)) when _T_838 : node _T_839 = eq(source_ok, UInt<1>(0h0)) when _T_839 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_840 = asUInt(reset) node _T_841 = eq(_T_840, UInt<1>(0h0)) when _T_841 : node _T_842 = eq(is_aligned, UInt<1>(0h0)) when _T_842 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_843 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_844 = asUInt(reset) node _T_845 = eq(_T_844, UInt<1>(0h0)) when _T_845 : node _T_846 = eq(_T_843, UInt<1>(0h0)) when _T_846 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_843, UInt<1>(0h1), "") : assert_39 node _T_847 = eq(io.in.a.bits.mask, mask) node _T_848 = asUInt(reset) node _T_849 = eq(_T_848, UInt<1>(0h0)) when _T_849 : node _T_850 = eq(_T_847, UInt<1>(0h0)) when _T_850 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_847, UInt<1>(0h1), "") : assert_40 node _T_851 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_851 : node _T_852 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_853 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_854 = and(_T_852, _T_853) node _T_855 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_856 = shr(io.in.a.bits.source, 2) node _T_857 = eq(_T_856, UInt<1>(0h0)) node _T_858 = leq(UInt<1>(0h0), uncommonBits_36) node _T_859 = and(_T_857, _T_858) node _T_860 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_861 = and(_T_859, _T_860) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_862 = shr(io.in.a.bits.source, 2) node _T_863 = eq(_T_862, UInt<1>(0h1)) node _T_864 = leq(UInt<1>(0h0), uncommonBits_37) node _T_865 = and(_T_863, _T_864) node _T_866 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_867 = and(_T_865, _T_866) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_868 = shr(io.in.a.bits.source, 2) node _T_869 = eq(_T_868, UInt<2>(0h2)) node _T_870 = leq(UInt<1>(0h0), uncommonBits_38) node _T_871 = and(_T_869, _T_870) node _T_872 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_873 = and(_T_871, _T_872) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_874 = shr(io.in.a.bits.source, 2) node _T_875 = eq(_T_874, UInt<2>(0h3)) node _T_876 = leq(UInt<1>(0h0), uncommonBits_39) node _T_877 = and(_T_875, _T_876) node _T_878 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_879 = and(_T_877, _T_878) node _T_880 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_881 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_882 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_883 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_884 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_885 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_886 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_887 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_888 = or(_T_855, _T_861) node _T_889 = or(_T_888, _T_867) node _T_890 = or(_T_889, _T_873) node _T_891 = or(_T_890, _T_879) node _T_892 = or(_T_891, _T_880) node _T_893 = or(_T_892, _T_881) node _T_894 = or(_T_893, _T_882) node _T_895 = or(_T_894, _T_883) node _T_896 = or(_T_895, _T_884) node _T_897 = or(_T_896, _T_885) node _T_898 = or(_T_897, _T_886) node _T_899 = or(_T_898, _T_887) node _T_900 = and(_T_854, _T_899) node _T_901 = or(UInt<1>(0h0), _T_900) node _T_902 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_903 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_904 = and(_T_902, _T_903) node _T_905 = or(UInt<1>(0h0), _T_904) node _T_906 = xor(io.in.a.bits.address, UInt<28>(0h8000040)) node _T_907 = cvt(_T_906) node _T_908 = and(_T_907, asSInt(UInt<17>(0h100c0))) node _T_909 = asSInt(_T_908) node _T_910 = eq(_T_909, asSInt(UInt<1>(0h0))) node _T_911 = xor(io.in.a.bits.address, UInt<32>(0h80000040)) node _T_912 = cvt(_T_911) node _T_913 = and(_T_912, asSInt(UInt<29>(0h100000c0))) node _T_914 = asSInt(_T_913) node _T_915 = eq(_T_914, asSInt(UInt<1>(0h0))) node _T_916 = or(_T_910, _T_915) node _T_917 = and(_T_905, _T_916) node _T_918 = or(UInt<1>(0h0), _T_917) node _T_919 = and(_T_901, _T_918) node _T_920 = asUInt(reset) node _T_921 = eq(_T_920, UInt<1>(0h0)) when _T_921 : node _T_922 = eq(_T_919, UInt<1>(0h0)) when _T_922 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_919, UInt<1>(0h1), "") : assert_41 node _T_923 = asUInt(reset) node _T_924 = eq(_T_923, UInt<1>(0h0)) when _T_924 : node _T_925 = eq(source_ok, UInt<1>(0h0)) when _T_925 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_926 = asUInt(reset) node _T_927 = eq(_T_926, UInt<1>(0h0)) when _T_927 : node _T_928 = eq(is_aligned, UInt<1>(0h0)) when _T_928 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_929 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_930 = asUInt(reset) node _T_931 = eq(_T_930, UInt<1>(0h0)) when _T_931 : node _T_932 = eq(_T_929, UInt<1>(0h0)) when _T_932 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_929, UInt<1>(0h1), "") : assert_44 node _T_933 = eq(io.in.a.bits.mask, mask) node _T_934 = asUInt(reset) node _T_935 = eq(_T_934, UInt<1>(0h0)) when _T_935 : node _T_936 = eq(_T_933, UInt<1>(0h0)) when _T_936 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_933, UInt<1>(0h1), "") : assert_45 node _T_937 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_937 : node _T_938 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_939 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_940 = and(_T_938, _T_939) node _T_941 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_942 = shr(io.in.a.bits.source, 2) node _T_943 = eq(_T_942, UInt<1>(0h0)) node _T_944 = leq(UInt<1>(0h0), uncommonBits_40) node _T_945 = and(_T_943, _T_944) node _T_946 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_947 = and(_T_945, _T_946) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_948 = shr(io.in.a.bits.source, 2) node _T_949 = eq(_T_948, UInt<1>(0h1)) node _T_950 = leq(UInt<1>(0h0), uncommonBits_41) node _T_951 = and(_T_949, _T_950) node _T_952 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_953 = and(_T_951, _T_952) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_954 = shr(io.in.a.bits.source, 2) node _T_955 = eq(_T_954, UInt<2>(0h2)) node _T_956 = leq(UInt<1>(0h0), uncommonBits_42) node _T_957 = and(_T_955, _T_956) node _T_958 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_959 = and(_T_957, _T_958) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_960 = shr(io.in.a.bits.source, 2) node _T_961 = eq(_T_960, UInt<2>(0h3)) node _T_962 = leq(UInt<1>(0h0), uncommonBits_43) node _T_963 = and(_T_961, _T_962) node _T_964 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_965 = and(_T_963, _T_964) node _T_966 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_967 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_968 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_969 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_970 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_971 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_972 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_973 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_974 = or(_T_941, _T_947) node _T_975 = or(_T_974, _T_953) node _T_976 = or(_T_975, _T_959) node _T_977 = or(_T_976, _T_965) node _T_978 = or(_T_977, _T_966) node _T_979 = or(_T_978, _T_967) node _T_980 = or(_T_979, _T_968) node _T_981 = or(_T_980, _T_969) node _T_982 = or(_T_981, _T_970) node _T_983 = or(_T_982, _T_971) node _T_984 = or(_T_983, _T_972) node _T_985 = or(_T_984, _T_973) node _T_986 = and(_T_940, _T_985) node _T_987 = or(UInt<1>(0h0), _T_986) node _T_988 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_989 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_990 = and(_T_988, _T_989) node _T_991 = or(UInt<1>(0h0), _T_990) node _T_992 = xor(io.in.a.bits.address, UInt<28>(0h8000040)) node _T_993 = cvt(_T_992) node _T_994 = and(_T_993, asSInt(UInt<17>(0h100c0))) node _T_995 = asSInt(_T_994) node _T_996 = eq(_T_995, asSInt(UInt<1>(0h0))) node _T_997 = xor(io.in.a.bits.address, UInt<32>(0h80000040)) node _T_998 = cvt(_T_997) node _T_999 = and(_T_998, asSInt(UInt<29>(0h100000c0))) node _T_1000 = asSInt(_T_999) node _T_1001 = eq(_T_1000, asSInt(UInt<1>(0h0))) node _T_1002 = or(_T_996, _T_1001) node _T_1003 = and(_T_991, _T_1002) node _T_1004 = or(UInt<1>(0h0), _T_1003) node _T_1005 = and(_T_987, _T_1004) node _T_1006 = asUInt(reset) node _T_1007 = eq(_T_1006, UInt<1>(0h0)) when _T_1007 : node _T_1008 = eq(_T_1005, UInt<1>(0h0)) when _T_1008 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1005, UInt<1>(0h1), "") : assert_46 node _T_1009 = asUInt(reset) node _T_1010 = eq(_T_1009, UInt<1>(0h0)) when _T_1010 : node _T_1011 = eq(source_ok, UInt<1>(0h0)) when _T_1011 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1012 = asUInt(reset) node _T_1013 = eq(_T_1012, UInt<1>(0h0)) when _T_1013 : node _T_1014 = eq(is_aligned, UInt<1>(0h0)) when _T_1014 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1015 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1016 = asUInt(reset) node _T_1017 = eq(_T_1016, UInt<1>(0h0)) when _T_1017 : node _T_1018 = eq(_T_1015, UInt<1>(0h0)) when _T_1018 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1015, UInt<1>(0h1), "") : assert_49 node _T_1019 = eq(io.in.a.bits.mask, mask) node _T_1020 = asUInt(reset) node _T_1021 = eq(_T_1020, UInt<1>(0h0)) when _T_1021 : node _T_1022 = eq(_T_1019, UInt<1>(0h0)) when _T_1022 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1019, UInt<1>(0h1), "") : assert_50 node _T_1023 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1024 = asUInt(reset) node _T_1025 = eq(_T_1024, UInt<1>(0h0)) when _T_1025 : node _T_1026 = eq(_T_1023, UInt<1>(0h0)) when _T_1026 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1023, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1027 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1028 = asUInt(reset) node _T_1029 = eq(_T_1028, UInt<1>(0h0)) when _T_1029 : node _T_1030 = eq(_T_1027, UInt<1>(0h0)) when _T_1030 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1027, UInt<1>(0h1), "") : assert_52 node _source_ok_T_44 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_45 = shr(io.in.d.bits.source, 2) node _source_ok_T_46 = eq(_source_ok_T_45, UInt<1>(0h0)) node _source_ok_T_47 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_48 = and(_source_ok_T_46, _source_ok_T_47) node _source_ok_T_49 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_50 = and(_source_ok_T_48, _source_ok_T_49) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_51 = shr(io.in.d.bits.source, 2) node _source_ok_T_52 = eq(_source_ok_T_51, UInt<1>(0h1)) node _source_ok_T_53 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53) node _source_ok_T_55 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_56 = and(_source_ok_T_54, _source_ok_T_55) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_57 = shr(io.in.d.bits.source, 2) node _source_ok_T_58 = eq(_source_ok_T_57, UInt<2>(0h2)) node _source_ok_T_59 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_60 = and(_source_ok_T_58, _source_ok_T_59) node _source_ok_T_61 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_62 = and(_source_ok_T_60, _source_ok_T_61) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_63 = shr(io.in.d.bits.source, 2) node _source_ok_T_64 = eq(_source_ok_T_63, UInt<2>(0h3)) node _source_ok_T_65 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_66 = and(_source_ok_T_64, _source_ok_T_65) node _source_ok_T_67 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_68 = and(_source_ok_T_66, _source_ok_T_67) node _source_ok_T_69 = eq(io.in.d.bits.source, UInt<6>(0h2c)) node _source_ok_T_70 = eq(io.in.d.bits.source, UInt<6>(0h2e)) node _source_ok_T_71 = eq(io.in.d.bits.source, UInt<6>(0h28)) node _source_ok_T_72 = eq(io.in.d.bits.source, UInt<6>(0h2a)) node _source_ok_T_73 = eq(io.in.d.bits.source, UInt<6>(0h24)) node _source_ok_T_74 = eq(io.in.d.bits.source, UInt<6>(0h26)) node _source_ok_T_75 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_76 = eq(io.in.d.bits.source, UInt<6>(0h22)) wire _source_ok_WIRE_1 : UInt<1>[13] connect _source_ok_WIRE_1[0], _source_ok_T_44 connect _source_ok_WIRE_1[1], _source_ok_T_50 connect _source_ok_WIRE_1[2], _source_ok_T_56 connect _source_ok_WIRE_1[3], _source_ok_T_62 connect _source_ok_WIRE_1[4], _source_ok_T_68 connect _source_ok_WIRE_1[5], _source_ok_T_69 connect _source_ok_WIRE_1[6], _source_ok_T_70 connect _source_ok_WIRE_1[7], _source_ok_T_71 connect _source_ok_WIRE_1[8], _source_ok_T_72 connect _source_ok_WIRE_1[9], _source_ok_T_73 connect _source_ok_WIRE_1[10], _source_ok_T_74 connect _source_ok_WIRE_1[11], _source_ok_T_75 connect _source_ok_WIRE_1[12], _source_ok_T_76 node _source_ok_T_77 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_78 = or(_source_ok_T_77, _source_ok_WIRE_1[2]) node _source_ok_T_79 = or(_source_ok_T_78, _source_ok_WIRE_1[3]) node _source_ok_T_80 = or(_source_ok_T_79, _source_ok_WIRE_1[4]) node _source_ok_T_81 = or(_source_ok_T_80, _source_ok_WIRE_1[5]) node _source_ok_T_82 = or(_source_ok_T_81, _source_ok_WIRE_1[6]) node _source_ok_T_83 = or(_source_ok_T_82, _source_ok_WIRE_1[7]) node _source_ok_T_84 = or(_source_ok_T_83, _source_ok_WIRE_1[8]) node _source_ok_T_85 = or(_source_ok_T_84, _source_ok_WIRE_1[9]) node _source_ok_T_86 = or(_source_ok_T_85, _source_ok_WIRE_1[10]) node _source_ok_T_87 = or(_source_ok_T_86, _source_ok_WIRE_1[11]) node source_ok_1 = or(_source_ok_T_87, _source_ok_WIRE_1[12]) node sink_ok = lt(io.in.d.bits.sink, UInt<3>(0h7)) node _T_1031 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1031 : node _T_1032 = asUInt(reset) node _T_1033 = eq(_T_1032, UInt<1>(0h0)) when _T_1033 : node _T_1034 = eq(source_ok_1, UInt<1>(0h0)) when _T_1034 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1035 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1036 = asUInt(reset) node _T_1037 = eq(_T_1036, UInt<1>(0h0)) when _T_1037 : node _T_1038 = eq(_T_1035, UInt<1>(0h0)) when _T_1038 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1035, UInt<1>(0h1), "") : assert_54 node _T_1039 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1040 = asUInt(reset) node _T_1041 = eq(_T_1040, UInt<1>(0h0)) when _T_1041 : node _T_1042 = eq(_T_1039, UInt<1>(0h0)) when _T_1042 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1039, UInt<1>(0h1), "") : assert_55 node _T_1043 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1044 = asUInt(reset) node _T_1045 = eq(_T_1044, UInt<1>(0h0)) when _T_1045 : node _T_1046 = eq(_T_1043, UInt<1>(0h0)) when _T_1046 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1043, UInt<1>(0h1), "") : assert_56 node _T_1047 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1048 = asUInt(reset) node _T_1049 = eq(_T_1048, UInt<1>(0h0)) when _T_1049 : node _T_1050 = eq(_T_1047, UInt<1>(0h0)) when _T_1050 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1047, UInt<1>(0h1), "") : assert_57 node _T_1051 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1051 : node _T_1052 = asUInt(reset) node _T_1053 = eq(_T_1052, UInt<1>(0h0)) when _T_1053 : node _T_1054 = eq(source_ok_1, UInt<1>(0h0)) when _T_1054 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1055 = asUInt(reset) node _T_1056 = eq(_T_1055, UInt<1>(0h0)) when _T_1056 : node _T_1057 = eq(sink_ok, UInt<1>(0h0)) when _T_1057 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1058 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1059 = asUInt(reset) node _T_1060 = eq(_T_1059, UInt<1>(0h0)) when _T_1060 : node _T_1061 = eq(_T_1058, UInt<1>(0h0)) when _T_1061 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1058, UInt<1>(0h1), "") : assert_60 node _T_1062 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1063 = asUInt(reset) node _T_1064 = eq(_T_1063, UInt<1>(0h0)) when _T_1064 : node _T_1065 = eq(_T_1062, UInt<1>(0h0)) when _T_1065 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1062, UInt<1>(0h1), "") : assert_61 node _T_1066 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1067 = asUInt(reset) node _T_1068 = eq(_T_1067, UInt<1>(0h0)) when _T_1068 : node _T_1069 = eq(_T_1066, UInt<1>(0h0)) when _T_1069 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1066, UInt<1>(0h1), "") : assert_62 node _T_1070 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1071 = asUInt(reset) node _T_1072 = eq(_T_1071, UInt<1>(0h0)) when _T_1072 : node _T_1073 = eq(_T_1070, UInt<1>(0h0)) when _T_1073 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1070, UInt<1>(0h1), "") : assert_63 node _T_1074 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1075 = or(UInt<1>(0h1), _T_1074) node _T_1076 = asUInt(reset) node _T_1077 = eq(_T_1076, UInt<1>(0h0)) when _T_1077 : node _T_1078 = eq(_T_1075, UInt<1>(0h0)) when _T_1078 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1075, UInt<1>(0h1), "") : assert_64 node _T_1079 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1079 : node _T_1080 = asUInt(reset) node _T_1081 = eq(_T_1080, UInt<1>(0h0)) when _T_1081 : node _T_1082 = eq(source_ok_1, UInt<1>(0h0)) when _T_1082 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1083 = asUInt(reset) node _T_1084 = eq(_T_1083, UInt<1>(0h0)) when _T_1084 : node _T_1085 = eq(sink_ok, UInt<1>(0h0)) when _T_1085 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1086 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1087 = asUInt(reset) node _T_1088 = eq(_T_1087, UInt<1>(0h0)) when _T_1088 : node _T_1089 = eq(_T_1086, UInt<1>(0h0)) when _T_1089 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1086, UInt<1>(0h1), "") : assert_67 node _T_1090 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1091 = asUInt(reset) node _T_1092 = eq(_T_1091, UInt<1>(0h0)) when _T_1092 : node _T_1093 = eq(_T_1090, UInt<1>(0h0)) when _T_1093 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1090, UInt<1>(0h1), "") : assert_68 node _T_1094 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1095 = asUInt(reset) node _T_1096 = eq(_T_1095, UInt<1>(0h0)) when _T_1096 : node _T_1097 = eq(_T_1094, UInt<1>(0h0)) when _T_1097 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1094, UInt<1>(0h1), "") : assert_69 node _T_1098 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1099 = or(_T_1098, io.in.d.bits.corrupt) node _T_1100 = asUInt(reset) node _T_1101 = eq(_T_1100, UInt<1>(0h0)) when _T_1101 : node _T_1102 = eq(_T_1099, UInt<1>(0h0)) when _T_1102 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1099, UInt<1>(0h1), "") : assert_70 node _T_1103 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1104 = or(UInt<1>(0h1), _T_1103) node _T_1105 = asUInt(reset) node _T_1106 = eq(_T_1105, UInt<1>(0h0)) when _T_1106 : node _T_1107 = eq(_T_1104, UInt<1>(0h0)) when _T_1107 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1104, UInt<1>(0h1), "") : assert_71 node _T_1108 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1108 : node _T_1109 = asUInt(reset) node _T_1110 = eq(_T_1109, UInt<1>(0h0)) when _T_1110 : node _T_1111 = eq(source_ok_1, UInt<1>(0h0)) when _T_1111 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1112 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1113 = asUInt(reset) node _T_1114 = eq(_T_1113, UInt<1>(0h0)) when _T_1114 : node _T_1115 = eq(_T_1112, UInt<1>(0h0)) when _T_1115 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1112, UInt<1>(0h1), "") : assert_73 node _T_1116 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1117 = asUInt(reset) node _T_1118 = eq(_T_1117, UInt<1>(0h0)) when _T_1118 : node _T_1119 = eq(_T_1116, UInt<1>(0h0)) when _T_1119 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1116, UInt<1>(0h1), "") : assert_74 node _T_1120 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1121 = or(UInt<1>(0h1), _T_1120) node _T_1122 = asUInt(reset) node _T_1123 = eq(_T_1122, UInt<1>(0h0)) when _T_1123 : node _T_1124 = eq(_T_1121, UInt<1>(0h0)) when _T_1124 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1121, UInt<1>(0h1), "") : assert_75 node _T_1125 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1125 : node _T_1126 = asUInt(reset) node _T_1127 = eq(_T_1126, UInt<1>(0h0)) when _T_1127 : node _T_1128 = eq(source_ok_1, UInt<1>(0h0)) when _T_1128 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1129 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1130 = asUInt(reset) node _T_1131 = eq(_T_1130, UInt<1>(0h0)) when _T_1131 : node _T_1132 = eq(_T_1129, UInt<1>(0h0)) when _T_1132 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1129, UInt<1>(0h1), "") : assert_77 node _T_1133 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1134 = or(_T_1133, io.in.d.bits.corrupt) node _T_1135 = asUInt(reset) node _T_1136 = eq(_T_1135, UInt<1>(0h0)) when _T_1136 : node _T_1137 = eq(_T_1134, UInt<1>(0h0)) when _T_1137 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1134, UInt<1>(0h1), "") : assert_78 node _T_1138 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1139 = or(UInt<1>(0h1), _T_1138) node _T_1140 = asUInt(reset) node _T_1141 = eq(_T_1140, UInt<1>(0h0)) when _T_1141 : node _T_1142 = eq(_T_1139, UInt<1>(0h0)) when _T_1142 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1139, UInt<1>(0h1), "") : assert_79 node _T_1143 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1143 : node _T_1144 = asUInt(reset) node _T_1145 = eq(_T_1144, UInt<1>(0h0)) when _T_1145 : node _T_1146 = eq(source_ok_1, UInt<1>(0h0)) when _T_1146 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1147 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1148 = asUInt(reset) node _T_1149 = eq(_T_1148, UInt<1>(0h0)) when _T_1149 : node _T_1150 = eq(_T_1147, UInt<1>(0h0)) when _T_1150 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1147, UInt<1>(0h1), "") : assert_81 node _T_1151 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1152 = asUInt(reset) node _T_1153 = eq(_T_1152, UInt<1>(0h0)) when _T_1153 : node _T_1154 = eq(_T_1151, UInt<1>(0h0)) when _T_1154 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1151, UInt<1>(0h1), "") : assert_82 node _T_1155 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1156 = or(UInt<1>(0h1), _T_1155) node _T_1157 = asUInt(reset) node _T_1158 = eq(_T_1157, UInt<1>(0h0)) when _T_1158 : node _T_1159 = eq(_T_1156, UInt<1>(0h0)) when _T_1159 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1156, UInt<1>(0h1), "") : assert_83 when io.in.b.valid : node _T_1160 = leq(io.in.b.bits.opcode, UInt<3>(0h6)) node _T_1161 = asUInt(reset) node _T_1162 = eq(_T_1161, UInt<1>(0h0)) when _T_1162 : node _T_1163 = eq(_T_1160, UInt<1>(0h0)) when _T_1163 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1160, UInt<1>(0h1), "") : assert_84 node _T_1164 = eq(io.in.b.bits.source, UInt<5>(0h10)) node _T_1165 = eq(_T_1164, UInt<1>(0h0)) node _T_1166 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1167 = cvt(_T_1166) node _T_1168 = and(_T_1167, asSInt(UInt<1>(0h0))) node _T_1169 = asSInt(_T_1168) node _T_1170 = eq(_T_1169, asSInt(UInt<1>(0h0))) node _T_1171 = or(_T_1165, _T_1170) node _uncommonBits_T_44 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_44 = bits(_uncommonBits_T_44, 1, 0) node _T_1172 = shr(io.in.b.bits.source, 2) node _T_1173 = eq(_T_1172, UInt<1>(0h0)) node _T_1174 = leq(UInt<1>(0h0), uncommonBits_44) node _T_1175 = and(_T_1173, _T_1174) node _T_1176 = leq(uncommonBits_44, UInt<2>(0h3)) node _T_1177 = and(_T_1175, _T_1176) node _T_1178 = eq(_T_1177, UInt<1>(0h0)) node _T_1179 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1180 = cvt(_T_1179) node _T_1181 = and(_T_1180, asSInt(UInt<1>(0h0))) node _T_1182 = asSInt(_T_1181) node _T_1183 = eq(_T_1182, asSInt(UInt<1>(0h0))) node _T_1184 = or(_T_1178, _T_1183) node _uncommonBits_T_45 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0) node _T_1185 = shr(io.in.b.bits.source, 2) node _T_1186 = eq(_T_1185, UInt<1>(0h1)) node _T_1187 = leq(UInt<1>(0h0), uncommonBits_45) node _T_1188 = and(_T_1186, _T_1187) node _T_1189 = leq(uncommonBits_45, UInt<2>(0h3)) node _T_1190 = and(_T_1188, _T_1189) node _T_1191 = eq(_T_1190, UInt<1>(0h0)) node _T_1192 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1193 = cvt(_T_1192) node _T_1194 = and(_T_1193, asSInt(UInt<1>(0h0))) node _T_1195 = asSInt(_T_1194) node _T_1196 = eq(_T_1195, asSInt(UInt<1>(0h0))) node _T_1197 = or(_T_1191, _T_1196) node _uncommonBits_T_46 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_46 = bits(_uncommonBits_T_46, 1, 0) node _T_1198 = shr(io.in.b.bits.source, 2) node _T_1199 = eq(_T_1198, UInt<2>(0h2)) node _T_1200 = leq(UInt<1>(0h0), uncommonBits_46) node _T_1201 = and(_T_1199, _T_1200) node _T_1202 = leq(uncommonBits_46, UInt<2>(0h3)) node _T_1203 = and(_T_1201, _T_1202) node _T_1204 = eq(_T_1203, UInt<1>(0h0)) node _T_1205 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1206 = cvt(_T_1205) node _T_1207 = and(_T_1206, asSInt(UInt<1>(0h0))) node _T_1208 = asSInt(_T_1207) node _T_1209 = eq(_T_1208, asSInt(UInt<1>(0h0))) node _T_1210 = or(_T_1204, _T_1209) node _uncommonBits_T_47 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_47 = bits(_uncommonBits_T_47, 1, 0) node _T_1211 = shr(io.in.b.bits.source, 2) node _T_1212 = eq(_T_1211, UInt<2>(0h3)) node _T_1213 = leq(UInt<1>(0h0), uncommonBits_47) node _T_1214 = and(_T_1212, _T_1213) node _T_1215 = leq(uncommonBits_47, UInt<2>(0h3)) node _T_1216 = and(_T_1214, _T_1215) node _T_1217 = eq(_T_1216, UInt<1>(0h0)) node _T_1218 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1219 = cvt(_T_1218) node _T_1220 = and(_T_1219, asSInt(UInt<1>(0h0))) node _T_1221 = asSInt(_T_1220) node _T_1222 = eq(_T_1221, asSInt(UInt<1>(0h0))) node _T_1223 = or(_T_1217, _T_1222) node _T_1224 = eq(io.in.b.bits.source, UInt<6>(0h2c)) node _T_1225 = eq(_T_1224, UInt<1>(0h0)) node _T_1226 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1227 = cvt(_T_1226) node _T_1228 = and(_T_1227, asSInt(UInt<1>(0h0))) node _T_1229 = asSInt(_T_1228) node _T_1230 = eq(_T_1229, asSInt(UInt<1>(0h0))) node _T_1231 = or(_T_1225, _T_1230) node _T_1232 = eq(io.in.b.bits.source, UInt<6>(0h2e)) node _T_1233 = eq(_T_1232, UInt<1>(0h0)) node _T_1234 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1235 = cvt(_T_1234) node _T_1236 = and(_T_1235, asSInt(UInt<1>(0h0))) node _T_1237 = asSInt(_T_1236) node _T_1238 = eq(_T_1237, asSInt(UInt<1>(0h0))) node _T_1239 = or(_T_1233, _T_1238) node _T_1240 = eq(io.in.b.bits.source, UInt<6>(0h28)) node _T_1241 = eq(_T_1240, UInt<1>(0h0)) node _T_1242 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1243 = cvt(_T_1242) node _T_1244 = and(_T_1243, asSInt(UInt<1>(0h0))) node _T_1245 = asSInt(_T_1244) node _T_1246 = eq(_T_1245, asSInt(UInt<1>(0h0))) node _T_1247 = or(_T_1241, _T_1246) node _T_1248 = eq(io.in.b.bits.source, UInt<6>(0h2a)) node _T_1249 = eq(_T_1248, UInt<1>(0h0)) node _T_1250 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1251 = cvt(_T_1250) node _T_1252 = and(_T_1251, asSInt(UInt<1>(0h0))) node _T_1253 = asSInt(_T_1252) node _T_1254 = eq(_T_1253, asSInt(UInt<1>(0h0))) node _T_1255 = or(_T_1249, _T_1254) node _T_1256 = eq(io.in.b.bits.source, UInt<6>(0h24)) node _T_1257 = eq(_T_1256, UInt<1>(0h0)) node _T_1258 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1259 = cvt(_T_1258) node _T_1260 = and(_T_1259, asSInt(UInt<1>(0h0))) node _T_1261 = asSInt(_T_1260) node _T_1262 = eq(_T_1261, asSInt(UInt<1>(0h0))) node _T_1263 = or(_T_1257, _T_1262) node _T_1264 = eq(io.in.b.bits.source, UInt<6>(0h26)) node _T_1265 = eq(_T_1264, UInt<1>(0h0)) node _T_1266 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1267 = cvt(_T_1266) node _T_1268 = and(_T_1267, asSInt(UInt<1>(0h0))) node _T_1269 = asSInt(_T_1268) node _T_1270 = eq(_T_1269, asSInt(UInt<1>(0h0))) node _T_1271 = or(_T_1265, _T_1270) node _T_1272 = eq(io.in.b.bits.source, UInt<6>(0h20)) node _T_1273 = eq(_T_1272, UInt<1>(0h0)) node _T_1274 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1275 = cvt(_T_1274) node _T_1276 = and(_T_1275, asSInt(UInt<1>(0h0))) node _T_1277 = asSInt(_T_1276) node _T_1278 = eq(_T_1277, asSInt(UInt<1>(0h0))) node _T_1279 = or(_T_1273, _T_1278) node _T_1280 = eq(io.in.b.bits.source, UInt<6>(0h22)) node _T_1281 = eq(_T_1280, UInt<1>(0h0)) node _T_1282 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1283 = cvt(_T_1282) node _T_1284 = and(_T_1283, asSInt(UInt<1>(0h0))) node _T_1285 = asSInt(_T_1284) node _T_1286 = eq(_T_1285, asSInt(UInt<1>(0h0))) node _T_1287 = or(_T_1281, _T_1286) node _T_1288 = and(_T_1171, _T_1184) node _T_1289 = and(_T_1288, _T_1197) node _T_1290 = and(_T_1289, _T_1210) node _T_1291 = and(_T_1290, _T_1223) node _T_1292 = and(_T_1291, _T_1231) node _T_1293 = and(_T_1292, _T_1239) node _T_1294 = and(_T_1293, _T_1247) node _T_1295 = and(_T_1294, _T_1255) node _T_1296 = and(_T_1295, _T_1263) node _T_1297 = and(_T_1296, _T_1271) node _T_1298 = and(_T_1297, _T_1279) node _T_1299 = and(_T_1298, _T_1287) node _T_1300 = asUInt(reset) node _T_1301 = eq(_T_1300, UInt<1>(0h0)) when _T_1301 : node _T_1302 = eq(_T_1299, UInt<1>(0h0)) when _T_1302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1299, UInt<1>(0h1), "") : assert_85 node _address_ok_T = xor(io.in.b.bits.address, UInt<28>(0h8000040)) node _address_ok_T_1 = cvt(_address_ok_T) node _address_ok_T_2 = and(_address_ok_T_1, asSInt(UInt<17>(0h100c0))) node _address_ok_T_3 = asSInt(_address_ok_T_2) node _address_ok_T_4 = eq(_address_ok_T_3, asSInt(UInt<1>(0h0))) node _address_ok_T_5 = xor(io.in.b.bits.address, UInt<32>(0h80000040)) node _address_ok_T_6 = cvt(_address_ok_T_5) node _address_ok_T_7 = and(_address_ok_T_6, asSInt(UInt<29>(0h100000c0))) node _address_ok_T_8 = asSInt(_address_ok_T_7) node _address_ok_T_9 = eq(_address_ok_T_8, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE : UInt<1>[2] connect _address_ok_WIRE[0], _address_ok_T_4 connect _address_ok_WIRE[1], _address_ok_T_9 node address_ok = or(_address_ok_WIRE[0], _address_ok_WIRE[1]) node _is_aligned_mask_T_2 = dshl(UInt<6>(0h3f), io.in.b.bits.size) node _is_aligned_mask_T_3 = bits(_is_aligned_mask_T_2, 5, 0) node is_aligned_mask_1 = not(_is_aligned_mask_T_3) node _is_aligned_T_1 = and(io.in.b.bits.address, is_aligned_mask_1) node is_aligned_1 = eq(_is_aligned_T_1, UInt<1>(0h0)) node _mask_sizeOH_T_3 = or(io.in.b.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount_1 = bits(_mask_sizeOH_T_3, 1, 0) node _mask_sizeOH_T_4 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount_1) node _mask_sizeOH_T_5 = bits(_mask_sizeOH_T_4, 2, 0) node mask_sizeOH_1 = or(_mask_sizeOH_T_5, UInt<1>(0h1)) node mask_sub_sub_sub_0_1_1 = geq(io.in.b.bits.size, UInt<2>(0h3)) node mask_sub_sub_size_1 = bits(mask_sizeOH_1, 2, 2) node mask_sub_sub_bit_1 = bits(io.in.b.bits.address, 2, 2) node mask_sub_sub_nbit_1 = eq(mask_sub_sub_bit_1, UInt<1>(0h0)) node mask_sub_sub_0_2_1 = and(UInt<1>(0h1), mask_sub_sub_nbit_1) node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size_1, mask_sub_sub_0_2_1) node mask_sub_sub_0_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_2) node mask_sub_sub_1_2_1 = and(UInt<1>(0h1), mask_sub_sub_bit_1) node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size_1, mask_sub_sub_1_2_1) node mask_sub_sub_1_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_3) node mask_sub_size_1 = bits(mask_sizeOH_1, 1, 1) node mask_sub_bit_1 = bits(io.in.b.bits.address, 1, 1) node mask_sub_nbit_1 = eq(mask_sub_bit_1, UInt<1>(0h0)) node mask_sub_0_2_1 = and(mask_sub_sub_0_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_4 = and(mask_sub_size_1, mask_sub_0_2_1) node mask_sub_0_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_4) node mask_sub_1_2_1 = and(mask_sub_sub_0_2_1, mask_sub_bit_1) node _mask_sub_acc_T_5 = and(mask_sub_size_1, mask_sub_1_2_1) node mask_sub_1_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_5) node mask_sub_2_2_1 = and(mask_sub_sub_1_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_6 = and(mask_sub_size_1, mask_sub_2_2_1) node mask_sub_2_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_6) node mask_sub_3_2_1 = and(mask_sub_sub_1_2_1, mask_sub_bit_1) node _mask_sub_acc_T_7 = and(mask_sub_size_1, mask_sub_3_2_1) node mask_sub_3_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_7) node mask_size_1 = bits(mask_sizeOH_1, 0, 0) node mask_bit_1 = bits(io.in.b.bits.address, 0, 0) node mask_nbit_1 = eq(mask_bit_1, UInt<1>(0h0)) node mask_eq_8 = and(mask_sub_0_2_1, mask_nbit_1) node _mask_acc_T_8 = and(mask_size_1, mask_eq_8) node mask_acc_8 = or(mask_sub_0_1_1, _mask_acc_T_8) node mask_eq_9 = and(mask_sub_0_2_1, mask_bit_1) node _mask_acc_T_9 = and(mask_size_1, mask_eq_9) node mask_acc_9 = or(mask_sub_0_1_1, _mask_acc_T_9) node mask_eq_10 = and(mask_sub_1_2_1, mask_nbit_1) node _mask_acc_T_10 = and(mask_size_1, mask_eq_10) node mask_acc_10 = or(mask_sub_1_1_1, _mask_acc_T_10) node mask_eq_11 = and(mask_sub_1_2_1, mask_bit_1) node _mask_acc_T_11 = and(mask_size_1, mask_eq_11) node mask_acc_11 = or(mask_sub_1_1_1, _mask_acc_T_11) node mask_eq_12 = and(mask_sub_2_2_1, mask_nbit_1) node _mask_acc_T_12 = and(mask_size_1, mask_eq_12) node mask_acc_12 = or(mask_sub_2_1_1, _mask_acc_T_12) node mask_eq_13 = and(mask_sub_2_2_1, mask_bit_1) node _mask_acc_T_13 = and(mask_size_1, mask_eq_13) node mask_acc_13 = or(mask_sub_2_1_1, _mask_acc_T_13) node mask_eq_14 = and(mask_sub_3_2_1, mask_nbit_1) node _mask_acc_T_14 = and(mask_size_1, mask_eq_14) node mask_acc_14 = or(mask_sub_3_1_1, _mask_acc_T_14) node mask_eq_15 = and(mask_sub_3_2_1, mask_bit_1) node _mask_acc_T_15 = and(mask_size_1, mask_eq_15) node mask_acc_15 = or(mask_sub_3_1_1, _mask_acc_T_15) node mask_lo_lo_1 = cat(mask_acc_9, mask_acc_8) node mask_lo_hi_1 = cat(mask_acc_11, mask_acc_10) node mask_lo_1 = cat(mask_lo_hi_1, mask_lo_lo_1) node mask_hi_lo_1 = cat(mask_acc_13, mask_acc_12) node mask_hi_hi_1 = cat(mask_acc_15, mask_acc_14) node mask_hi_1 = cat(mask_hi_hi_1, mask_hi_lo_1) node mask_1 = cat(mask_hi_1, mask_lo_1) node _legal_source_T = eq(io.in.b.bits.source, UInt<5>(0h10)) node _legal_source_uncommonBits_T = or(io.in.b.bits.source, UInt<2>(0h0)) node legal_source_uncommonBits = bits(_legal_source_uncommonBits_T, 1, 0) node _legal_source_T_1 = shr(io.in.b.bits.source, 2) node _legal_source_T_2 = eq(_legal_source_T_1, UInt<1>(0h0)) node _legal_source_T_3 = leq(UInt<1>(0h0), legal_source_uncommonBits) node _legal_source_T_4 = and(_legal_source_T_2, _legal_source_T_3) node _legal_source_T_5 = leq(legal_source_uncommonBits, UInt<2>(0h3)) node _legal_source_T_6 = and(_legal_source_T_4, _legal_source_T_5) node _legal_source_uncommonBits_T_1 = or(io.in.b.bits.source, UInt<2>(0h0)) node legal_source_uncommonBits_1 = bits(_legal_source_uncommonBits_T_1, 1, 0) node _legal_source_T_7 = shr(io.in.b.bits.source, 2) node _legal_source_T_8 = eq(_legal_source_T_7, UInt<1>(0h1)) node _legal_source_T_9 = leq(UInt<1>(0h0), legal_source_uncommonBits_1) node _legal_source_T_10 = and(_legal_source_T_8, _legal_source_T_9) node _legal_source_T_11 = leq(legal_source_uncommonBits_1, UInt<2>(0h3)) node _legal_source_T_12 = and(_legal_source_T_10, _legal_source_T_11) node _legal_source_uncommonBits_T_2 = or(io.in.b.bits.source, UInt<2>(0h0)) node legal_source_uncommonBits_2 = bits(_legal_source_uncommonBits_T_2, 1, 0) node _legal_source_T_13 = shr(io.in.b.bits.source, 2) node _legal_source_T_14 = eq(_legal_source_T_13, UInt<2>(0h2)) node _legal_source_T_15 = leq(UInt<1>(0h0), legal_source_uncommonBits_2) node _legal_source_T_16 = and(_legal_source_T_14, _legal_source_T_15) node _legal_source_T_17 = leq(legal_source_uncommonBits_2, UInt<2>(0h3)) node _legal_source_T_18 = and(_legal_source_T_16, _legal_source_T_17) node _legal_source_uncommonBits_T_3 = or(io.in.b.bits.source, UInt<2>(0h0)) node legal_source_uncommonBits_3 = bits(_legal_source_uncommonBits_T_3, 1, 0) node _legal_source_T_19 = shr(io.in.b.bits.source, 2) node _legal_source_T_20 = eq(_legal_source_T_19, UInt<2>(0h3)) node _legal_source_T_21 = leq(UInt<1>(0h0), legal_source_uncommonBits_3) node _legal_source_T_22 = and(_legal_source_T_20, _legal_source_T_21) node _legal_source_T_23 = leq(legal_source_uncommonBits_3, UInt<2>(0h3)) node _legal_source_T_24 = and(_legal_source_T_22, _legal_source_T_23) node _legal_source_T_25 = eq(io.in.b.bits.source, UInt<6>(0h2c)) node _legal_source_T_26 = eq(io.in.b.bits.source, UInt<6>(0h2e)) node _legal_source_T_27 = eq(io.in.b.bits.source, UInt<6>(0h28)) node _legal_source_T_28 = eq(io.in.b.bits.source, UInt<6>(0h2a)) node _legal_source_T_29 = eq(io.in.b.bits.source, UInt<6>(0h24)) node _legal_source_T_30 = eq(io.in.b.bits.source, UInt<6>(0h26)) node _legal_source_T_31 = eq(io.in.b.bits.source, UInt<6>(0h20)) node _legal_source_T_32 = eq(io.in.b.bits.source, UInt<6>(0h22)) wire _legal_source_WIRE : UInt<1>[13] connect _legal_source_WIRE[0], _legal_source_T connect _legal_source_WIRE[1], _legal_source_T_6 connect _legal_source_WIRE[2], _legal_source_T_12 connect _legal_source_WIRE[3], _legal_source_T_18 connect _legal_source_WIRE[4], _legal_source_T_24 connect _legal_source_WIRE[5], _legal_source_T_25 connect _legal_source_WIRE[6], _legal_source_T_26 connect _legal_source_WIRE[7], _legal_source_T_27 connect _legal_source_WIRE[8], _legal_source_T_28 connect _legal_source_WIRE[9], _legal_source_T_29 connect _legal_source_WIRE[10], _legal_source_T_30 connect _legal_source_WIRE[11], _legal_source_T_31 connect _legal_source_WIRE[12], _legal_source_T_32 node _legal_source_T_33 = mux(_legal_source_WIRE[0], UInt<5>(0h10), UInt<1>(0h0)) node _legal_source_T_34 = mux(_legal_source_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _legal_source_T_35 = mux(_legal_source_WIRE[2], UInt<3>(0h4), UInt<1>(0h0)) node _legal_source_T_36 = mux(_legal_source_WIRE[3], UInt<4>(0h8), UInt<1>(0h0)) node _legal_source_T_37 = mux(_legal_source_WIRE[4], UInt<4>(0hc), UInt<1>(0h0)) node _legal_source_T_38 = mux(_legal_source_WIRE[5], UInt<6>(0h2c), UInt<1>(0h0)) node _legal_source_T_39 = mux(_legal_source_WIRE[6], UInt<6>(0h2e), UInt<1>(0h0)) node _legal_source_T_40 = mux(_legal_source_WIRE[7], UInt<6>(0h28), UInt<1>(0h0)) node _legal_source_T_41 = mux(_legal_source_WIRE[8], UInt<6>(0h2a), UInt<1>(0h0)) node _legal_source_T_42 = mux(_legal_source_WIRE[9], UInt<6>(0h24), UInt<1>(0h0)) node _legal_source_T_43 = mux(_legal_source_WIRE[10], UInt<6>(0h26), UInt<1>(0h0)) node _legal_source_T_44 = mux(_legal_source_WIRE[11], UInt<6>(0h20), UInt<1>(0h0)) node _legal_source_T_45 = mux(_legal_source_WIRE[12], UInt<6>(0h22), UInt<1>(0h0)) node _legal_source_T_46 = or(_legal_source_T_33, _legal_source_T_34) node _legal_source_T_47 = or(_legal_source_T_46, _legal_source_T_35) node _legal_source_T_48 = or(_legal_source_T_47, _legal_source_T_36) node _legal_source_T_49 = or(_legal_source_T_48, _legal_source_T_37) node _legal_source_T_50 = or(_legal_source_T_49, _legal_source_T_38) node _legal_source_T_51 = or(_legal_source_T_50, _legal_source_T_39) node _legal_source_T_52 = or(_legal_source_T_51, _legal_source_T_40) node _legal_source_T_53 = or(_legal_source_T_52, _legal_source_T_41) node _legal_source_T_54 = or(_legal_source_T_53, _legal_source_T_42) node _legal_source_T_55 = or(_legal_source_T_54, _legal_source_T_43) node _legal_source_T_56 = or(_legal_source_T_55, _legal_source_T_44) node _legal_source_T_57 = or(_legal_source_T_56, _legal_source_T_45) wire _legal_source_WIRE_1 : UInt<6> connect _legal_source_WIRE_1, _legal_source_T_57 node legal_source = eq(_legal_source_WIRE_1, io.in.b.bits.source) node _T_1303 = eq(io.in.b.bits.opcode, UInt<3>(0h6)) when _T_1303 : node _T_1304 = eq(io.in.b.bits.source, UInt<5>(0h10)) node _uncommonBits_T_48 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0) node _T_1305 = shr(io.in.b.bits.source, 2) node _T_1306 = eq(_T_1305, UInt<1>(0h0)) node _T_1307 = leq(UInt<1>(0h0), uncommonBits_48) node _T_1308 = and(_T_1306, _T_1307) node _T_1309 = leq(uncommonBits_48, UInt<2>(0h3)) node _T_1310 = and(_T_1308, _T_1309) node _uncommonBits_T_49 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_49 = bits(_uncommonBits_T_49, 1, 0) node _T_1311 = shr(io.in.b.bits.source, 2) node _T_1312 = eq(_T_1311, UInt<1>(0h1)) node _T_1313 = leq(UInt<1>(0h0), uncommonBits_49) node _T_1314 = and(_T_1312, _T_1313) node _T_1315 = leq(uncommonBits_49, UInt<2>(0h3)) node _T_1316 = and(_T_1314, _T_1315) node _uncommonBits_T_50 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0) node _T_1317 = shr(io.in.b.bits.source, 2) node _T_1318 = eq(_T_1317, UInt<2>(0h2)) node _T_1319 = leq(UInt<1>(0h0), uncommonBits_50) node _T_1320 = and(_T_1318, _T_1319) node _T_1321 = leq(uncommonBits_50, UInt<2>(0h3)) node _T_1322 = and(_T_1320, _T_1321) node _uncommonBits_T_51 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0) node _T_1323 = shr(io.in.b.bits.source, 2) node _T_1324 = eq(_T_1323, UInt<2>(0h3)) node _T_1325 = leq(UInt<1>(0h0), uncommonBits_51) node _T_1326 = and(_T_1324, _T_1325) node _T_1327 = leq(uncommonBits_51, UInt<2>(0h3)) node _T_1328 = and(_T_1326, _T_1327) node _T_1329 = eq(io.in.b.bits.source, UInt<6>(0h2c)) node _T_1330 = eq(io.in.b.bits.source, UInt<6>(0h2e)) node _T_1331 = eq(io.in.b.bits.source, UInt<6>(0h28)) node _T_1332 = eq(io.in.b.bits.source, UInt<6>(0h2a)) node _T_1333 = eq(io.in.b.bits.source, UInt<6>(0h24)) node _T_1334 = eq(io.in.b.bits.source, UInt<6>(0h26)) node _T_1335 = eq(io.in.b.bits.source, UInt<6>(0h20)) node _T_1336 = eq(io.in.b.bits.source, UInt<6>(0h22)) wire _WIRE_4 : UInt<1>[13] connect _WIRE_4[0], _T_1304 connect _WIRE_4[1], _T_1310 connect _WIRE_4[2], _T_1316 connect _WIRE_4[3], _T_1322 connect _WIRE_4[4], _T_1328 connect _WIRE_4[5], _T_1329 connect _WIRE_4[6], _T_1330 connect _WIRE_4[7], _T_1331 connect _WIRE_4[8], _T_1332 connect _WIRE_4[9], _T_1333 connect _WIRE_4[10], _T_1334 connect _WIRE_4[11], _T_1335 connect _WIRE_4[12], _T_1336 node _T_1337 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1338 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1339 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1340 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1341 = mux(_WIRE_4[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_1342 = mux(_WIRE_4[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1343 = mux(_WIRE_4[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_1344 = mux(_WIRE_4[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_1345 = mux(_WIRE_4[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_1346 = mux(_WIRE_4[5], _T_1337, UInt<1>(0h0)) node _T_1347 = mux(_WIRE_4[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_1348 = mux(_WIRE_4[7], _T_1338, UInt<1>(0h0)) node _T_1349 = mux(_WIRE_4[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_1350 = mux(_WIRE_4[9], _T_1339, UInt<1>(0h0)) node _T_1351 = mux(_WIRE_4[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_1352 = mux(_WIRE_4[11], _T_1340, UInt<1>(0h0)) node _T_1353 = mux(_WIRE_4[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_1354 = or(_T_1341, _T_1342) node _T_1355 = or(_T_1354, _T_1343) node _T_1356 = or(_T_1355, _T_1344) node _T_1357 = or(_T_1356, _T_1345) node _T_1358 = or(_T_1357, _T_1346) node _T_1359 = or(_T_1358, _T_1347) node _T_1360 = or(_T_1359, _T_1348) node _T_1361 = or(_T_1360, _T_1349) node _T_1362 = or(_T_1361, _T_1350) node _T_1363 = or(_T_1362, _T_1351) node _T_1364 = or(_T_1363, _T_1352) node _T_1365 = or(_T_1364, _T_1353) wire _WIRE_5 : UInt<1> connect _WIRE_5, _T_1365 node _T_1366 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1367 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1368 = and(_T_1366, _T_1367) node _T_1369 = or(UInt<1>(0h0), _T_1368) node _T_1370 = xor(io.in.b.bits.address, UInt<28>(0h8000040)) node _T_1371 = cvt(_T_1370) node _T_1372 = and(_T_1371, asSInt(UInt<17>(0h100c0))) node _T_1373 = asSInt(_T_1372) node _T_1374 = eq(_T_1373, asSInt(UInt<1>(0h0))) node _T_1375 = xor(io.in.b.bits.address, UInt<32>(0h80000040)) node _T_1376 = cvt(_T_1375) node _T_1377 = and(_T_1376, asSInt(UInt<29>(0h100000c0))) node _T_1378 = asSInt(_T_1377) node _T_1379 = eq(_T_1378, asSInt(UInt<1>(0h0))) node _T_1380 = or(_T_1374, _T_1379) node _T_1381 = and(_T_1369, _T_1380) node _T_1382 = or(UInt<1>(0h0), _T_1381) node _T_1383 = and(_WIRE_5, _T_1382) node _T_1384 = asUInt(reset) node _T_1385 = eq(_T_1384, UInt<1>(0h0)) when _T_1385 : node _T_1386 = eq(_T_1383, UInt<1>(0h0)) when _T_1386 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_86 assert(clock, _T_1383, UInt<1>(0h1), "") : assert_86 node _T_1387 = asUInt(reset) node _T_1388 = eq(_T_1387, UInt<1>(0h0)) when _T_1388 : node _T_1389 = eq(address_ok, UInt<1>(0h0)) when _T_1389 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_87 assert(clock, address_ok, UInt<1>(0h1), "") : assert_87 node _T_1390 = asUInt(reset) node _T_1391 = eq(_T_1390, UInt<1>(0h0)) when _T_1391 : node _T_1392 = eq(legal_source, UInt<1>(0h0)) when _T_1392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_88 assert(clock, legal_source, UInt<1>(0h1), "") : assert_88 node _T_1393 = asUInt(reset) node _T_1394 = eq(_T_1393, UInt<1>(0h0)) when _T_1394 : node _T_1395 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1395 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_89 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_89 node _T_1396 = leq(io.in.b.bits.param, UInt<2>(0h2)) node _T_1397 = asUInt(reset) node _T_1398 = eq(_T_1397, UInt<1>(0h0)) when _T_1398 : node _T_1399 = eq(_T_1396, UInt<1>(0h0)) when _T_1399 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_90 assert(clock, _T_1396, UInt<1>(0h1), "") : assert_90 node _T_1400 = eq(io.in.b.bits.mask, mask_1) node _T_1401 = asUInt(reset) node _T_1402 = eq(_T_1401, UInt<1>(0h0)) when _T_1402 : node _T_1403 = eq(_T_1400, UInt<1>(0h0)) when _T_1403 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_91 assert(clock, _T_1400, UInt<1>(0h1), "") : assert_91 node _T_1404 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1405 = asUInt(reset) node _T_1406 = eq(_T_1405, UInt<1>(0h0)) when _T_1406 : node _T_1407 = eq(_T_1404, UInt<1>(0h0)) when _T_1407 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1404, UInt<1>(0h1), "") : assert_92 node _T_1408 = eq(io.in.b.bits.opcode, UInt<3>(0h4)) when _T_1408 : node _T_1409 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1410 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1411 = and(_T_1409, _T_1410) node _T_1412 = or(UInt<1>(0h0), _T_1411) node _T_1413 = xor(io.in.b.bits.address, UInt<28>(0h8000040)) node _T_1414 = cvt(_T_1413) node _T_1415 = and(_T_1414, asSInt(UInt<17>(0h100c0))) node _T_1416 = asSInt(_T_1415) node _T_1417 = eq(_T_1416, asSInt(UInt<1>(0h0))) node _T_1418 = xor(io.in.b.bits.address, UInt<32>(0h80000040)) node _T_1419 = cvt(_T_1418) node _T_1420 = and(_T_1419, asSInt(UInt<29>(0h100000c0))) node _T_1421 = asSInt(_T_1420) node _T_1422 = eq(_T_1421, asSInt(UInt<1>(0h0))) node _T_1423 = or(_T_1417, _T_1422) node _T_1424 = and(_T_1412, _T_1423) node _T_1425 = or(UInt<1>(0h0), _T_1424) node _T_1426 = and(UInt<1>(0h0), _T_1425) node _T_1427 = asUInt(reset) node _T_1428 = eq(_T_1427, UInt<1>(0h0)) when _T_1428 : node _T_1429 = eq(_T_1426, UInt<1>(0h0)) when _T_1429 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Get type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_93 assert(clock, _T_1426, UInt<1>(0h1), "") : assert_93 node _T_1430 = asUInt(reset) node _T_1431 = eq(_T_1430, UInt<1>(0h0)) when _T_1431 : node _T_1432 = eq(address_ok, UInt<1>(0h0)) when _T_1432 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_94 assert(clock, address_ok, UInt<1>(0h1), "") : assert_94 node _T_1433 = asUInt(reset) node _T_1434 = eq(_T_1433, UInt<1>(0h0)) when _T_1434 : node _T_1435 = eq(legal_source, UInt<1>(0h0)) when _T_1435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_95 assert(clock, legal_source, UInt<1>(0h1), "") : assert_95 node _T_1436 = asUInt(reset) node _T_1437 = eq(_T_1436, UInt<1>(0h0)) when _T_1437 : node _T_1438 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1438 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_96 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_96 node _T_1439 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1440 = asUInt(reset) node _T_1441 = eq(_T_1440, UInt<1>(0h0)) when _T_1441 : node _T_1442 = eq(_T_1439, UInt<1>(0h0)) when _T_1442 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_97 assert(clock, _T_1439, UInt<1>(0h1), "") : assert_97 node _T_1443 = eq(io.in.b.bits.mask, mask_1) node _T_1444 = asUInt(reset) node _T_1445 = eq(_T_1444, UInt<1>(0h0)) when _T_1445 : node _T_1446 = eq(_T_1443, UInt<1>(0h0)) when _T_1446 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1443, UInt<1>(0h1), "") : assert_98 node _T_1447 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1448 = asUInt(reset) node _T_1449 = eq(_T_1448, UInt<1>(0h0)) when _T_1449 : node _T_1450 = eq(_T_1447, UInt<1>(0h0)) when _T_1450 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_99 assert(clock, _T_1447, UInt<1>(0h1), "") : assert_99 node _T_1451 = eq(io.in.b.bits.opcode, UInt<1>(0h0)) when _T_1451 : node _T_1452 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1453 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1454 = and(_T_1452, _T_1453) node _T_1455 = or(UInt<1>(0h0), _T_1454) node _T_1456 = xor(io.in.b.bits.address, UInt<28>(0h8000040)) node _T_1457 = cvt(_T_1456) node _T_1458 = and(_T_1457, asSInt(UInt<17>(0h100c0))) node _T_1459 = asSInt(_T_1458) node _T_1460 = eq(_T_1459, asSInt(UInt<1>(0h0))) node _T_1461 = xor(io.in.b.bits.address, UInt<32>(0h80000040)) node _T_1462 = cvt(_T_1461) node _T_1463 = and(_T_1462, asSInt(UInt<29>(0h100000c0))) node _T_1464 = asSInt(_T_1463) node _T_1465 = eq(_T_1464, asSInt(UInt<1>(0h0))) node _T_1466 = or(_T_1460, _T_1465) node _T_1467 = and(_T_1455, _T_1466) node _T_1468 = or(UInt<1>(0h0), _T_1467) node _T_1469 = and(UInt<1>(0h0), _T_1468) node _T_1470 = asUInt(reset) node _T_1471 = eq(_T_1470, UInt<1>(0h0)) when _T_1471 : node _T_1472 = eq(_T_1469, UInt<1>(0h0)) when _T_1472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_100 assert(clock, _T_1469, UInt<1>(0h1), "") : assert_100 node _T_1473 = asUInt(reset) node _T_1474 = eq(_T_1473, UInt<1>(0h0)) when _T_1474 : node _T_1475 = eq(address_ok, UInt<1>(0h0)) when _T_1475 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_101 assert(clock, address_ok, UInt<1>(0h1), "") : assert_101 node _T_1476 = asUInt(reset) node _T_1477 = eq(_T_1476, UInt<1>(0h0)) when _T_1477 : node _T_1478 = eq(legal_source, UInt<1>(0h0)) when _T_1478 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_102 assert(clock, legal_source, UInt<1>(0h1), "") : assert_102 node _T_1479 = asUInt(reset) node _T_1480 = eq(_T_1479, UInt<1>(0h0)) when _T_1480 : node _T_1481 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_103 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_103 node _T_1482 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1483 = asUInt(reset) node _T_1484 = eq(_T_1483, UInt<1>(0h0)) when _T_1484 : node _T_1485 = eq(_T_1482, UInt<1>(0h0)) when _T_1485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_104 assert(clock, _T_1482, UInt<1>(0h1), "") : assert_104 node _T_1486 = eq(io.in.b.bits.mask, mask_1) node _T_1487 = asUInt(reset) node _T_1488 = eq(_T_1487, UInt<1>(0h0)) when _T_1488 : node _T_1489 = eq(_T_1486, UInt<1>(0h0)) when _T_1489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1486, UInt<1>(0h1), "") : assert_105 node _T_1490 = eq(io.in.b.bits.opcode, UInt<1>(0h1)) when _T_1490 : node _T_1491 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1492 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1493 = and(_T_1491, _T_1492) node _T_1494 = or(UInt<1>(0h0), _T_1493) node _T_1495 = xor(io.in.b.bits.address, UInt<28>(0h8000040)) node _T_1496 = cvt(_T_1495) node _T_1497 = and(_T_1496, asSInt(UInt<17>(0h100c0))) node _T_1498 = asSInt(_T_1497) node _T_1499 = eq(_T_1498, asSInt(UInt<1>(0h0))) node _T_1500 = xor(io.in.b.bits.address, UInt<32>(0h80000040)) node _T_1501 = cvt(_T_1500) node _T_1502 = and(_T_1501, asSInt(UInt<29>(0h100000c0))) node _T_1503 = asSInt(_T_1502) node _T_1504 = eq(_T_1503, asSInt(UInt<1>(0h0))) node _T_1505 = or(_T_1499, _T_1504) node _T_1506 = and(_T_1494, _T_1505) node _T_1507 = or(UInt<1>(0h0), _T_1506) node _T_1508 = and(UInt<1>(0h0), _T_1507) node _T_1509 = asUInt(reset) node _T_1510 = eq(_T_1509, UInt<1>(0h0)) when _T_1510 : node _T_1511 = eq(_T_1508, UInt<1>(0h0)) when _T_1511 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1508, UInt<1>(0h1), "") : assert_106 node _T_1512 = asUInt(reset) node _T_1513 = eq(_T_1512, UInt<1>(0h0)) when _T_1513 : node _T_1514 = eq(address_ok, UInt<1>(0h0)) when _T_1514 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, address_ok, UInt<1>(0h1), "") : assert_107 node _T_1515 = asUInt(reset) node _T_1516 = eq(_T_1515, UInt<1>(0h0)) when _T_1516 : node _T_1517 = eq(legal_source, UInt<1>(0h0)) when _T_1517 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_108 assert(clock, legal_source, UInt<1>(0h1), "") : assert_108 node _T_1518 = asUInt(reset) node _T_1519 = eq(_T_1518, UInt<1>(0h0)) when _T_1519 : node _T_1520 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_109 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_109 node _T_1521 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1522 = asUInt(reset) node _T_1523 = eq(_T_1522, UInt<1>(0h0)) when _T_1523 : node _T_1524 = eq(_T_1521, UInt<1>(0h0)) when _T_1524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_110 assert(clock, _T_1521, UInt<1>(0h1), "") : assert_110 node _T_1525 = not(mask_1) node _T_1526 = and(io.in.b.bits.mask, _T_1525) node _T_1527 = eq(_T_1526, UInt<1>(0h0)) node _T_1528 = asUInt(reset) node _T_1529 = eq(_T_1528, UInt<1>(0h0)) when _T_1529 : node _T_1530 = eq(_T_1527, UInt<1>(0h0)) when _T_1530 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1527, UInt<1>(0h1), "") : assert_111 node _T_1531 = eq(io.in.b.bits.opcode, UInt<2>(0h2)) when _T_1531 : node _T_1532 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1533 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1534 = and(_T_1532, _T_1533) node _T_1535 = or(UInt<1>(0h0), _T_1534) node _T_1536 = xor(io.in.b.bits.address, UInt<28>(0h8000040)) node _T_1537 = cvt(_T_1536) node _T_1538 = and(_T_1537, asSInt(UInt<17>(0h100c0))) node _T_1539 = asSInt(_T_1538) node _T_1540 = eq(_T_1539, asSInt(UInt<1>(0h0))) node _T_1541 = xor(io.in.b.bits.address, UInt<32>(0h80000040)) node _T_1542 = cvt(_T_1541) node _T_1543 = and(_T_1542, asSInt(UInt<29>(0h100000c0))) node _T_1544 = asSInt(_T_1543) node _T_1545 = eq(_T_1544, asSInt(UInt<1>(0h0))) node _T_1546 = or(_T_1540, _T_1545) node _T_1547 = and(_T_1535, _T_1546) node _T_1548 = or(UInt<1>(0h0), _T_1547) node _T_1549 = and(UInt<1>(0h0), _T_1548) node _T_1550 = asUInt(reset) node _T_1551 = eq(_T_1550, UInt<1>(0h0)) when _T_1551 : node _T_1552 = eq(_T_1549, UInt<1>(0h0)) when _T_1552 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by master (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_112 assert(clock, _T_1549, UInt<1>(0h1), "") : assert_112 node _T_1553 = asUInt(reset) node _T_1554 = eq(_T_1553, UInt<1>(0h0)) when _T_1554 : node _T_1555 = eq(address_ok, UInt<1>(0h0)) when _T_1555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, address_ok, UInt<1>(0h1), "") : assert_113 node _T_1556 = asUInt(reset) node _T_1557 = eq(_T_1556, UInt<1>(0h0)) when _T_1557 : node _T_1558 = eq(legal_source, UInt<1>(0h0)) when _T_1558 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_114 assert(clock, legal_source, UInt<1>(0h1), "") : assert_114 node _T_1559 = asUInt(reset) node _T_1560 = eq(_T_1559, UInt<1>(0h0)) when _T_1560 : node _T_1561 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1561 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_115 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_115 node _T_1562 = leq(io.in.b.bits.param, UInt<3>(0h4)) node _T_1563 = asUInt(reset) node _T_1564 = eq(_T_1563, UInt<1>(0h0)) when _T_1564 : node _T_1565 = eq(_T_1562, UInt<1>(0h0)) when _T_1565 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_116 assert(clock, _T_1562, UInt<1>(0h1), "") : assert_116 node _T_1566 = eq(io.in.b.bits.mask, mask_1) node _T_1567 = asUInt(reset) node _T_1568 = eq(_T_1567, UInt<1>(0h0)) when _T_1568 : node _T_1569 = eq(_T_1566, UInt<1>(0h0)) when _T_1569 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_117 assert(clock, _T_1566, UInt<1>(0h1), "") : assert_117 node _T_1570 = eq(io.in.b.bits.opcode, UInt<2>(0h3)) when _T_1570 : node _T_1571 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1572 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1573 = and(_T_1571, _T_1572) node _T_1574 = or(UInt<1>(0h0), _T_1573) node _T_1575 = xor(io.in.b.bits.address, UInt<28>(0h8000040)) node _T_1576 = cvt(_T_1575) node _T_1577 = and(_T_1576, asSInt(UInt<17>(0h100c0))) node _T_1578 = asSInt(_T_1577) node _T_1579 = eq(_T_1578, asSInt(UInt<1>(0h0))) node _T_1580 = xor(io.in.b.bits.address, UInt<32>(0h80000040)) node _T_1581 = cvt(_T_1580) node _T_1582 = and(_T_1581, asSInt(UInt<29>(0h100000c0))) node _T_1583 = asSInt(_T_1582) node _T_1584 = eq(_T_1583, asSInt(UInt<1>(0h0))) node _T_1585 = or(_T_1579, _T_1584) node _T_1586 = and(_T_1574, _T_1585) node _T_1587 = or(UInt<1>(0h0), _T_1586) node _T_1588 = and(UInt<1>(0h0), _T_1587) node _T_1589 = asUInt(reset) node _T_1590 = eq(_T_1589, UInt<1>(0h0)) when _T_1590 : node _T_1591 = eq(_T_1588, UInt<1>(0h0)) when _T_1591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_118 assert(clock, _T_1588, UInt<1>(0h1), "") : assert_118 node _T_1592 = asUInt(reset) node _T_1593 = eq(_T_1592, UInt<1>(0h0)) when _T_1593 : node _T_1594 = eq(address_ok, UInt<1>(0h0)) when _T_1594 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_119 assert(clock, address_ok, UInt<1>(0h1), "") : assert_119 node _T_1595 = asUInt(reset) node _T_1596 = eq(_T_1595, UInt<1>(0h0)) when _T_1596 : node _T_1597 = eq(legal_source, UInt<1>(0h0)) when _T_1597 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_120 assert(clock, legal_source, UInt<1>(0h1), "") : assert_120 node _T_1598 = asUInt(reset) node _T_1599 = eq(_T_1598, UInt<1>(0h0)) when _T_1599 : node _T_1600 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1600 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_121 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_121 node _T_1601 = leq(io.in.b.bits.param, UInt<3>(0h3)) node _T_1602 = asUInt(reset) node _T_1603 = eq(_T_1602, UInt<1>(0h0)) when _T_1603 : node _T_1604 = eq(_T_1601, UInt<1>(0h0)) when _T_1604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_122 assert(clock, _T_1601, UInt<1>(0h1), "") : assert_122 node _T_1605 = eq(io.in.b.bits.mask, mask_1) node _T_1606 = asUInt(reset) node _T_1607 = eq(_T_1606, UInt<1>(0h0)) when _T_1607 : node _T_1608 = eq(_T_1605, UInt<1>(0h0)) when _T_1608 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_123 assert(clock, _T_1605, UInt<1>(0h1), "") : assert_123 node _T_1609 = eq(io.in.b.bits.opcode, UInt<3>(0h5)) when _T_1609 : node _T_1610 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1611 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1612 = and(_T_1610, _T_1611) node _T_1613 = or(UInt<1>(0h0), _T_1612) node _T_1614 = xor(io.in.b.bits.address, UInt<28>(0h8000040)) node _T_1615 = cvt(_T_1614) node _T_1616 = and(_T_1615, asSInt(UInt<17>(0h100c0))) node _T_1617 = asSInt(_T_1616) node _T_1618 = eq(_T_1617, asSInt(UInt<1>(0h0))) node _T_1619 = xor(io.in.b.bits.address, UInt<32>(0h80000040)) node _T_1620 = cvt(_T_1619) node _T_1621 = and(_T_1620, asSInt(UInt<29>(0h100000c0))) node _T_1622 = asSInt(_T_1621) node _T_1623 = eq(_T_1622, asSInt(UInt<1>(0h0))) node _T_1624 = or(_T_1618, _T_1623) node _T_1625 = and(_T_1613, _T_1624) node _T_1626 = or(UInt<1>(0h0), _T_1625) node _T_1627 = and(UInt<1>(0h0), _T_1626) node _T_1628 = asUInt(reset) node _T_1629 = eq(_T_1628, UInt<1>(0h0)) when _T_1629 : node _T_1630 = eq(_T_1627, UInt<1>(0h0)) when _T_1630 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_124 assert(clock, _T_1627, UInt<1>(0h1), "") : assert_124 node _T_1631 = asUInt(reset) node _T_1632 = eq(_T_1631, UInt<1>(0h0)) when _T_1632 : node _T_1633 = eq(address_ok, UInt<1>(0h0)) when _T_1633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_125 assert(clock, address_ok, UInt<1>(0h1), "") : assert_125 node _T_1634 = asUInt(reset) node _T_1635 = eq(_T_1634, UInt<1>(0h0)) when _T_1635 : node _T_1636 = eq(legal_source, UInt<1>(0h0)) when _T_1636 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_126 assert(clock, legal_source, UInt<1>(0h1), "") : assert_126 node _T_1637 = asUInt(reset) node _T_1638 = eq(_T_1637, UInt<1>(0h0)) when _T_1638 : node _T_1639 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_127 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_127 node _T_1640 = eq(io.in.b.bits.mask, mask_1) node _T_1641 = asUInt(reset) node _T_1642 = eq(_T_1641, UInt<1>(0h0)) when _T_1642 : node _T_1643 = eq(_T_1640, UInt<1>(0h0)) when _T_1643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_128 assert(clock, _T_1640, UInt<1>(0h1), "") : assert_128 node _T_1644 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1645 = asUInt(reset) node _T_1646 = eq(_T_1645, UInt<1>(0h0)) when _T_1646 : node _T_1647 = eq(_T_1644, UInt<1>(0h0)) when _T_1647 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_129 assert(clock, _T_1644, UInt<1>(0h1), "") : assert_129 when io.in.c.valid : node _T_1648 = leq(io.in.c.bits.opcode, UInt<3>(0h7)) node _T_1649 = asUInt(reset) node _T_1650 = eq(_T_1649, UInt<1>(0h0)) when _T_1650 : node _T_1651 = eq(_T_1648, UInt<1>(0h0)) when _T_1651 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_130 assert(clock, _T_1648, UInt<1>(0h1), "") : assert_130 node _source_ok_T_88 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_8 = or(io.in.c.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0) node _source_ok_T_89 = shr(io.in.c.bits.source, 2) node _source_ok_T_90 = eq(_source_ok_T_89, UInt<1>(0h0)) node _source_ok_T_91 = leq(UInt<1>(0h0), source_ok_uncommonBits_8) node _source_ok_T_92 = and(_source_ok_T_90, _source_ok_T_91) node _source_ok_T_93 = leq(source_ok_uncommonBits_8, UInt<2>(0h3)) node _source_ok_T_94 = and(_source_ok_T_92, _source_ok_T_93) node _source_ok_uncommonBits_T_9 = or(io.in.c.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 1, 0) node _source_ok_T_95 = shr(io.in.c.bits.source, 2) node _source_ok_T_96 = eq(_source_ok_T_95, UInt<1>(0h1)) node _source_ok_T_97 = leq(UInt<1>(0h0), source_ok_uncommonBits_9) node _source_ok_T_98 = and(_source_ok_T_96, _source_ok_T_97) node _source_ok_T_99 = leq(source_ok_uncommonBits_9, UInt<2>(0h3)) node _source_ok_T_100 = and(_source_ok_T_98, _source_ok_T_99) node _source_ok_uncommonBits_T_10 = or(io.in.c.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 1, 0) node _source_ok_T_101 = shr(io.in.c.bits.source, 2) node _source_ok_T_102 = eq(_source_ok_T_101, UInt<2>(0h2)) node _source_ok_T_103 = leq(UInt<1>(0h0), source_ok_uncommonBits_10) node _source_ok_T_104 = and(_source_ok_T_102, _source_ok_T_103) node _source_ok_T_105 = leq(source_ok_uncommonBits_10, UInt<2>(0h3)) node _source_ok_T_106 = and(_source_ok_T_104, _source_ok_T_105) node _source_ok_uncommonBits_T_11 = or(io.in.c.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 1, 0) node _source_ok_T_107 = shr(io.in.c.bits.source, 2) node _source_ok_T_108 = eq(_source_ok_T_107, UInt<2>(0h3)) node _source_ok_T_109 = leq(UInt<1>(0h0), source_ok_uncommonBits_11) node _source_ok_T_110 = and(_source_ok_T_108, _source_ok_T_109) node _source_ok_T_111 = leq(source_ok_uncommonBits_11, UInt<2>(0h3)) node _source_ok_T_112 = and(_source_ok_T_110, _source_ok_T_111) node _source_ok_T_113 = eq(io.in.c.bits.source, UInt<6>(0h2c)) node _source_ok_T_114 = eq(io.in.c.bits.source, UInt<6>(0h2e)) node _source_ok_T_115 = eq(io.in.c.bits.source, UInt<6>(0h28)) node _source_ok_T_116 = eq(io.in.c.bits.source, UInt<6>(0h2a)) node _source_ok_T_117 = eq(io.in.c.bits.source, UInt<6>(0h24)) node _source_ok_T_118 = eq(io.in.c.bits.source, UInt<6>(0h26)) node _source_ok_T_119 = eq(io.in.c.bits.source, UInt<6>(0h20)) node _source_ok_T_120 = eq(io.in.c.bits.source, UInt<6>(0h22)) wire _source_ok_WIRE_2 : UInt<1>[13] connect _source_ok_WIRE_2[0], _source_ok_T_88 connect _source_ok_WIRE_2[1], _source_ok_T_94 connect _source_ok_WIRE_2[2], _source_ok_T_100 connect _source_ok_WIRE_2[3], _source_ok_T_106 connect _source_ok_WIRE_2[4], _source_ok_T_112 connect _source_ok_WIRE_2[5], _source_ok_T_113 connect _source_ok_WIRE_2[6], _source_ok_T_114 connect _source_ok_WIRE_2[7], _source_ok_T_115 connect _source_ok_WIRE_2[8], _source_ok_T_116 connect _source_ok_WIRE_2[9], _source_ok_T_117 connect _source_ok_WIRE_2[10], _source_ok_T_118 connect _source_ok_WIRE_2[11], _source_ok_T_119 connect _source_ok_WIRE_2[12], _source_ok_T_120 node _source_ok_T_121 = or(_source_ok_WIRE_2[0], _source_ok_WIRE_2[1]) node _source_ok_T_122 = or(_source_ok_T_121, _source_ok_WIRE_2[2]) node _source_ok_T_123 = or(_source_ok_T_122, _source_ok_WIRE_2[3]) node _source_ok_T_124 = or(_source_ok_T_123, _source_ok_WIRE_2[4]) node _source_ok_T_125 = or(_source_ok_T_124, _source_ok_WIRE_2[5]) node _source_ok_T_126 = or(_source_ok_T_125, _source_ok_WIRE_2[6]) node _source_ok_T_127 = or(_source_ok_T_126, _source_ok_WIRE_2[7]) node _source_ok_T_128 = or(_source_ok_T_127, _source_ok_WIRE_2[8]) node _source_ok_T_129 = or(_source_ok_T_128, _source_ok_WIRE_2[9]) node _source_ok_T_130 = or(_source_ok_T_129, _source_ok_WIRE_2[10]) node _source_ok_T_131 = or(_source_ok_T_130, _source_ok_WIRE_2[11]) node source_ok_2 = or(_source_ok_T_131, _source_ok_WIRE_2[12]) node _is_aligned_mask_T_4 = dshl(UInt<6>(0h3f), io.in.c.bits.size) node _is_aligned_mask_T_5 = bits(_is_aligned_mask_T_4, 5, 0) node is_aligned_mask_2 = not(_is_aligned_mask_T_5) node _is_aligned_T_2 = and(io.in.c.bits.address, is_aligned_mask_2) node is_aligned_2 = eq(_is_aligned_T_2, UInt<1>(0h0)) node _address_ok_T_10 = xor(io.in.c.bits.address, UInt<28>(0h8000040)) node _address_ok_T_11 = cvt(_address_ok_T_10) node _address_ok_T_12 = and(_address_ok_T_11, asSInt(UInt<17>(0h100c0))) node _address_ok_T_13 = asSInt(_address_ok_T_12) node _address_ok_T_14 = eq(_address_ok_T_13, asSInt(UInt<1>(0h0))) node _address_ok_T_15 = xor(io.in.c.bits.address, UInt<32>(0h80000040)) node _address_ok_T_16 = cvt(_address_ok_T_15) node _address_ok_T_17 = and(_address_ok_T_16, asSInt(UInt<29>(0h100000c0))) node _address_ok_T_18 = asSInt(_address_ok_T_17) node _address_ok_T_19 = eq(_address_ok_T_18, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE_1 : UInt<1>[2] connect _address_ok_WIRE_1[0], _address_ok_T_14 connect _address_ok_WIRE_1[1], _address_ok_T_19 node address_ok_1 = or(_address_ok_WIRE_1[0], _address_ok_WIRE_1[1]) node _T_1652 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _T_1653 = eq(_T_1652, UInt<1>(0h0)) node _T_1654 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1655 = cvt(_T_1654) node _T_1656 = and(_T_1655, asSInt(UInt<1>(0h0))) node _T_1657 = asSInt(_T_1656) node _T_1658 = eq(_T_1657, asSInt(UInt<1>(0h0))) node _T_1659 = or(_T_1653, _T_1658) node _uncommonBits_T_52 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_52 = bits(_uncommonBits_T_52, 1, 0) node _T_1660 = shr(io.in.c.bits.source, 2) node _T_1661 = eq(_T_1660, UInt<1>(0h0)) node _T_1662 = leq(UInt<1>(0h0), uncommonBits_52) node _T_1663 = and(_T_1661, _T_1662) node _T_1664 = leq(uncommonBits_52, UInt<2>(0h3)) node _T_1665 = and(_T_1663, _T_1664) node _T_1666 = eq(_T_1665, UInt<1>(0h0)) node _T_1667 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1668 = cvt(_T_1667) node _T_1669 = and(_T_1668, asSInt(UInt<1>(0h0))) node _T_1670 = asSInt(_T_1669) node _T_1671 = eq(_T_1670, asSInt(UInt<1>(0h0))) node _T_1672 = or(_T_1666, _T_1671) node _uncommonBits_T_53 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_53 = bits(_uncommonBits_T_53, 1, 0) node _T_1673 = shr(io.in.c.bits.source, 2) node _T_1674 = eq(_T_1673, UInt<1>(0h1)) node _T_1675 = leq(UInt<1>(0h0), uncommonBits_53) node _T_1676 = and(_T_1674, _T_1675) node _T_1677 = leq(uncommonBits_53, UInt<2>(0h3)) node _T_1678 = and(_T_1676, _T_1677) node _T_1679 = eq(_T_1678, UInt<1>(0h0)) node _T_1680 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1681 = cvt(_T_1680) node _T_1682 = and(_T_1681, asSInt(UInt<1>(0h0))) node _T_1683 = asSInt(_T_1682) node _T_1684 = eq(_T_1683, asSInt(UInt<1>(0h0))) node _T_1685 = or(_T_1679, _T_1684) node _uncommonBits_T_54 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_54 = bits(_uncommonBits_T_54, 1, 0) node _T_1686 = shr(io.in.c.bits.source, 2) node _T_1687 = eq(_T_1686, UInt<2>(0h2)) node _T_1688 = leq(UInt<1>(0h0), uncommonBits_54) node _T_1689 = and(_T_1687, _T_1688) node _T_1690 = leq(uncommonBits_54, UInt<2>(0h3)) node _T_1691 = and(_T_1689, _T_1690) node _T_1692 = eq(_T_1691, UInt<1>(0h0)) node _T_1693 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1694 = cvt(_T_1693) node _T_1695 = and(_T_1694, asSInt(UInt<1>(0h0))) node _T_1696 = asSInt(_T_1695) node _T_1697 = eq(_T_1696, asSInt(UInt<1>(0h0))) node _T_1698 = or(_T_1692, _T_1697) node _uncommonBits_T_55 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_55 = bits(_uncommonBits_T_55, 1, 0) node _T_1699 = shr(io.in.c.bits.source, 2) node _T_1700 = eq(_T_1699, UInt<2>(0h3)) node _T_1701 = leq(UInt<1>(0h0), uncommonBits_55) node _T_1702 = and(_T_1700, _T_1701) node _T_1703 = leq(uncommonBits_55, UInt<2>(0h3)) node _T_1704 = and(_T_1702, _T_1703) node _T_1705 = eq(_T_1704, UInt<1>(0h0)) node _T_1706 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1707 = cvt(_T_1706) node _T_1708 = and(_T_1707, asSInt(UInt<1>(0h0))) node _T_1709 = asSInt(_T_1708) node _T_1710 = eq(_T_1709, asSInt(UInt<1>(0h0))) node _T_1711 = or(_T_1705, _T_1710) node _T_1712 = eq(io.in.c.bits.source, UInt<6>(0h2c)) node _T_1713 = eq(_T_1712, UInt<1>(0h0)) node _T_1714 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1715 = cvt(_T_1714) node _T_1716 = and(_T_1715, asSInt(UInt<1>(0h0))) node _T_1717 = asSInt(_T_1716) node _T_1718 = eq(_T_1717, asSInt(UInt<1>(0h0))) node _T_1719 = or(_T_1713, _T_1718) node _T_1720 = eq(io.in.c.bits.source, UInt<6>(0h2e)) node _T_1721 = eq(_T_1720, UInt<1>(0h0)) node _T_1722 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1723 = cvt(_T_1722) node _T_1724 = and(_T_1723, asSInt(UInt<1>(0h0))) node _T_1725 = asSInt(_T_1724) node _T_1726 = eq(_T_1725, asSInt(UInt<1>(0h0))) node _T_1727 = or(_T_1721, _T_1726) node _T_1728 = eq(io.in.c.bits.source, UInt<6>(0h28)) node _T_1729 = eq(_T_1728, UInt<1>(0h0)) node _T_1730 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1731 = cvt(_T_1730) node _T_1732 = and(_T_1731, asSInt(UInt<1>(0h0))) node _T_1733 = asSInt(_T_1732) node _T_1734 = eq(_T_1733, asSInt(UInt<1>(0h0))) node _T_1735 = or(_T_1729, _T_1734) node _T_1736 = eq(io.in.c.bits.source, UInt<6>(0h2a)) node _T_1737 = eq(_T_1736, UInt<1>(0h0)) node _T_1738 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1739 = cvt(_T_1738) node _T_1740 = and(_T_1739, asSInt(UInt<1>(0h0))) node _T_1741 = asSInt(_T_1740) node _T_1742 = eq(_T_1741, asSInt(UInt<1>(0h0))) node _T_1743 = or(_T_1737, _T_1742) node _T_1744 = eq(io.in.c.bits.source, UInt<6>(0h24)) node _T_1745 = eq(_T_1744, UInt<1>(0h0)) node _T_1746 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1747 = cvt(_T_1746) node _T_1748 = and(_T_1747, asSInt(UInt<1>(0h0))) node _T_1749 = asSInt(_T_1748) node _T_1750 = eq(_T_1749, asSInt(UInt<1>(0h0))) node _T_1751 = or(_T_1745, _T_1750) node _T_1752 = eq(io.in.c.bits.source, UInt<6>(0h26)) node _T_1753 = eq(_T_1752, UInt<1>(0h0)) node _T_1754 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1755 = cvt(_T_1754) node _T_1756 = and(_T_1755, asSInt(UInt<1>(0h0))) node _T_1757 = asSInt(_T_1756) node _T_1758 = eq(_T_1757, asSInt(UInt<1>(0h0))) node _T_1759 = or(_T_1753, _T_1758) node _T_1760 = eq(io.in.c.bits.source, UInt<6>(0h20)) node _T_1761 = eq(_T_1760, UInt<1>(0h0)) node _T_1762 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1763 = cvt(_T_1762) node _T_1764 = and(_T_1763, asSInt(UInt<1>(0h0))) node _T_1765 = asSInt(_T_1764) node _T_1766 = eq(_T_1765, asSInt(UInt<1>(0h0))) node _T_1767 = or(_T_1761, _T_1766) node _T_1768 = eq(io.in.c.bits.source, UInt<6>(0h22)) node _T_1769 = eq(_T_1768, UInt<1>(0h0)) node _T_1770 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1771 = cvt(_T_1770) node _T_1772 = and(_T_1771, asSInt(UInt<1>(0h0))) node _T_1773 = asSInt(_T_1772) node _T_1774 = eq(_T_1773, asSInt(UInt<1>(0h0))) node _T_1775 = or(_T_1769, _T_1774) node _T_1776 = and(_T_1659, _T_1672) node _T_1777 = and(_T_1776, _T_1685) node _T_1778 = and(_T_1777, _T_1698) node _T_1779 = and(_T_1778, _T_1711) node _T_1780 = and(_T_1779, _T_1719) node _T_1781 = and(_T_1780, _T_1727) node _T_1782 = and(_T_1781, _T_1735) node _T_1783 = and(_T_1782, _T_1743) node _T_1784 = and(_T_1783, _T_1751) node _T_1785 = and(_T_1784, _T_1759) node _T_1786 = and(_T_1785, _T_1767) node _T_1787 = and(_T_1786, _T_1775) node _T_1788 = asUInt(reset) node _T_1789 = eq(_T_1788, UInt<1>(0h0)) when _T_1789 : node _T_1790 = eq(_T_1787, UInt<1>(0h0)) when _T_1790 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_131 assert(clock, _T_1787, UInt<1>(0h1), "") : assert_131 node _T_1791 = eq(io.in.c.bits.opcode, UInt<3>(0h4)) when _T_1791 : node _T_1792 = asUInt(reset) node _T_1793 = eq(_T_1792, UInt<1>(0h0)) when _T_1793 : node _T_1794 = eq(address_ok_1, UInt<1>(0h0)) when _T_1794 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_132 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_132 node _T_1795 = asUInt(reset) node _T_1796 = eq(_T_1795, UInt<1>(0h0)) when _T_1796 : node _T_1797 = eq(source_ok_2, UInt<1>(0h0)) when _T_1797 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_133 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_133 node _T_1798 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_1799 = asUInt(reset) node _T_1800 = eq(_T_1799, UInt<1>(0h0)) when _T_1800 : node _T_1801 = eq(_T_1798, UInt<1>(0h0)) when _T_1801 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_134 assert(clock, _T_1798, UInt<1>(0h1), "") : assert_134 node _T_1802 = asUInt(reset) node _T_1803 = eq(_T_1802, UInt<1>(0h0)) when _T_1803 : node _T_1804 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1804 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_135 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_135 node _T_1805 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1806 = asUInt(reset) node _T_1807 = eq(_T_1806, UInt<1>(0h0)) when _T_1807 : node _T_1808 = eq(_T_1805, UInt<1>(0h0)) when _T_1808 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_136 assert(clock, _T_1805, UInt<1>(0h1), "") : assert_136 node _T_1809 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1810 = asUInt(reset) node _T_1811 = eq(_T_1810, UInt<1>(0h0)) when _T_1811 : node _T_1812 = eq(_T_1809, UInt<1>(0h0)) when _T_1812 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_137 assert(clock, _T_1809, UInt<1>(0h1), "") : assert_137 node _T_1813 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) when _T_1813 : node _T_1814 = asUInt(reset) node _T_1815 = eq(_T_1814, UInt<1>(0h0)) when _T_1815 : node _T_1816 = eq(address_ok_1, UInt<1>(0h0)) when _T_1816 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_138 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_138 node _T_1817 = asUInt(reset) node _T_1818 = eq(_T_1817, UInt<1>(0h0)) when _T_1818 : node _T_1819 = eq(source_ok_2, UInt<1>(0h0)) when _T_1819 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_139 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_139 node _T_1820 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_1821 = asUInt(reset) node _T_1822 = eq(_T_1821, UInt<1>(0h0)) when _T_1822 : node _T_1823 = eq(_T_1820, UInt<1>(0h0)) when _T_1823 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_140 assert(clock, _T_1820, UInt<1>(0h1), "") : assert_140 node _T_1824 = asUInt(reset) node _T_1825 = eq(_T_1824, UInt<1>(0h0)) when _T_1825 : node _T_1826 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1826 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_141 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_141 node _T_1827 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1828 = asUInt(reset) node _T_1829 = eq(_T_1828, UInt<1>(0h0)) when _T_1829 : node _T_1830 = eq(_T_1827, UInt<1>(0h0)) when _T_1830 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_142 assert(clock, _T_1827, UInt<1>(0h1), "") : assert_142 node _T_1831 = eq(io.in.c.bits.opcode, UInt<3>(0h6)) when _T_1831 : node _T_1832 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1833 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1834 = and(_T_1832, _T_1833) node _T_1835 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _uncommonBits_T_56 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_56 = bits(_uncommonBits_T_56, 1, 0) node _T_1836 = shr(io.in.c.bits.source, 2) node _T_1837 = eq(_T_1836, UInt<1>(0h0)) node _T_1838 = leq(UInt<1>(0h0), uncommonBits_56) node _T_1839 = and(_T_1837, _T_1838) node _T_1840 = leq(uncommonBits_56, UInt<2>(0h3)) node _T_1841 = and(_T_1839, _T_1840) node _uncommonBits_T_57 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_57 = bits(_uncommonBits_T_57, 1, 0) node _T_1842 = shr(io.in.c.bits.source, 2) node _T_1843 = eq(_T_1842, UInt<1>(0h1)) node _T_1844 = leq(UInt<1>(0h0), uncommonBits_57) node _T_1845 = and(_T_1843, _T_1844) node _T_1846 = leq(uncommonBits_57, UInt<2>(0h3)) node _T_1847 = and(_T_1845, _T_1846) node _uncommonBits_T_58 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_58 = bits(_uncommonBits_T_58, 1, 0) node _T_1848 = shr(io.in.c.bits.source, 2) node _T_1849 = eq(_T_1848, UInt<2>(0h2)) node _T_1850 = leq(UInt<1>(0h0), uncommonBits_58) node _T_1851 = and(_T_1849, _T_1850) node _T_1852 = leq(uncommonBits_58, UInt<2>(0h3)) node _T_1853 = and(_T_1851, _T_1852) node _uncommonBits_T_59 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_59 = bits(_uncommonBits_T_59, 1, 0) node _T_1854 = shr(io.in.c.bits.source, 2) node _T_1855 = eq(_T_1854, UInt<2>(0h3)) node _T_1856 = leq(UInt<1>(0h0), uncommonBits_59) node _T_1857 = and(_T_1855, _T_1856) node _T_1858 = leq(uncommonBits_59, UInt<2>(0h3)) node _T_1859 = and(_T_1857, _T_1858) node _T_1860 = eq(io.in.c.bits.source, UInt<6>(0h2c)) node _T_1861 = eq(io.in.c.bits.source, UInt<6>(0h2e)) node _T_1862 = eq(io.in.c.bits.source, UInt<6>(0h28)) node _T_1863 = eq(io.in.c.bits.source, UInt<6>(0h2a)) node _T_1864 = eq(io.in.c.bits.source, UInt<6>(0h24)) node _T_1865 = eq(io.in.c.bits.source, UInt<6>(0h26)) node _T_1866 = eq(io.in.c.bits.source, UInt<6>(0h20)) node _T_1867 = eq(io.in.c.bits.source, UInt<6>(0h22)) node _T_1868 = or(_T_1835, _T_1841) node _T_1869 = or(_T_1868, _T_1847) node _T_1870 = or(_T_1869, _T_1853) node _T_1871 = or(_T_1870, _T_1859) node _T_1872 = or(_T_1871, _T_1860) node _T_1873 = or(_T_1872, _T_1861) node _T_1874 = or(_T_1873, _T_1862) node _T_1875 = or(_T_1874, _T_1863) node _T_1876 = or(_T_1875, _T_1864) node _T_1877 = or(_T_1876, _T_1865) node _T_1878 = or(_T_1877, _T_1866) node _T_1879 = or(_T_1878, _T_1867) node _T_1880 = and(_T_1834, _T_1879) node _T_1881 = or(UInt<1>(0h0), _T_1880) node _T_1882 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1883 = or(UInt<1>(0h0), _T_1882) node _T_1884 = xor(io.in.c.bits.address, UInt<28>(0h8000040)) node _T_1885 = cvt(_T_1884) node _T_1886 = and(_T_1885, asSInt(UInt<17>(0h100c0))) node _T_1887 = asSInt(_T_1886) node _T_1888 = eq(_T_1887, asSInt(UInt<1>(0h0))) node _T_1889 = xor(io.in.c.bits.address, UInt<32>(0h80000040)) node _T_1890 = cvt(_T_1889) node _T_1891 = and(_T_1890, asSInt(UInt<29>(0h100000c0))) node _T_1892 = asSInt(_T_1891) node _T_1893 = eq(_T_1892, asSInt(UInt<1>(0h0))) node _T_1894 = or(_T_1888, _T_1893) node _T_1895 = and(_T_1883, _T_1894) node _T_1896 = or(UInt<1>(0h0), _T_1895) node _T_1897 = and(_T_1881, _T_1896) node _T_1898 = asUInt(reset) node _T_1899 = eq(_T_1898, UInt<1>(0h0)) when _T_1899 : node _T_1900 = eq(_T_1897, UInt<1>(0h0)) when _T_1900 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_143 assert(clock, _T_1897, UInt<1>(0h1), "") : assert_143 node _T_1901 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _uncommonBits_T_60 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_60 = bits(_uncommonBits_T_60, 1, 0) node _T_1902 = shr(io.in.c.bits.source, 2) node _T_1903 = eq(_T_1902, UInt<1>(0h0)) node _T_1904 = leq(UInt<1>(0h0), uncommonBits_60) node _T_1905 = and(_T_1903, _T_1904) node _T_1906 = leq(uncommonBits_60, UInt<2>(0h3)) node _T_1907 = and(_T_1905, _T_1906) node _uncommonBits_T_61 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_61 = bits(_uncommonBits_T_61, 1, 0) node _T_1908 = shr(io.in.c.bits.source, 2) node _T_1909 = eq(_T_1908, UInt<1>(0h1)) node _T_1910 = leq(UInt<1>(0h0), uncommonBits_61) node _T_1911 = and(_T_1909, _T_1910) node _T_1912 = leq(uncommonBits_61, UInt<2>(0h3)) node _T_1913 = and(_T_1911, _T_1912) node _uncommonBits_T_62 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_62 = bits(_uncommonBits_T_62, 1, 0) node _T_1914 = shr(io.in.c.bits.source, 2) node _T_1915 = eq(_T_1914, UInt<2>(0h2)) node _T_1916 = leq(UInt<1>(0h0), uncommonBits_62) node _T_1917 = and(_T_1915, _T_1916) node _T_1918 = leq(uncommonBits_62, UInt<2>(0h3)) node _T_1919 = and(_T_1917, _T_1918) node _uncommonBits_T_63 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_63 = bits(_uncommonBits_T_63, 1, 0) node _T_1920 = shr(io.in.c.bits.source, 2) node _T_1921 = eq(_T_1920, UInt<2>(0h3)) node _T_1922 = leq(UInt<1>(0h0), uncommonBits_63) node _T_1923 = and(_T_1921, _T_1922) node _T_1924 = leq(uncommonBits_63, UInt<2>(0h3)) node _T_1925 = and(_T_1923, _T_1924) node _T_1926 = eq(io.in.c.bits.source, UInt<6>(0h2c)) node _T_1927 = eq(io.in.c.bits.source, UInt<6>(0h2e)) node _T_1928 = eq(io.in.c.bits.source, UInt<6>(0h28)) node _T_1929 = eq(io.in.c.bits.source, UInt<6>(0h2a)) node _T_1930 = eq(io.in.c.bits.source, UInt<6>(0h24)) node _T_1931 = eq(io.in.c.bits.source, UInt<6>(0h26)) node _T_1932 = eq(io.in.c.bits.source, UInt<6>(0h20)) node _T_1933 = eq(io.in.c.bits.source, UInt<6>(0h22)) wire _WIRE_6 : UInt<1>[13] connect _WIRE_6[0], _T_1901 connect _WIRE_6[1], _T_1907 connect _WIRE_6[2], _T_1913 connect _WIRE_6[3], _T_1919 connect _WIRE_6[4], _T_1925 connect _WIRE_6[5], _T_1926 connect _WIRE_6[6], _T_1927 connect _WIRE_6[7], _T_1928 connect _WIRE_6[8], _T_1929 connect _WIRE_6[9], _T_1930 connect _WIRE_6[10], _T_1931 connect _WIRE_6[11], _T_1932 connect _WIRE_6[12], _T_1933 node _T_1934 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1935 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1936 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1937 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1938 = mux(_WIRE_6[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_1939 = mux(_WIRE_6[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1940 = mux(_WIRE_6[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_1941 = mux(_WIRE_6[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_1942 = mux(_WIRE_6[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_1943 = mux(_WIRE_6[5], _T_1934, UInt<1>(0h0)) node _T_1944 = mux(_WIRE_6[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_1945 = mux(_WIRE_6[7], _T_1935, UInt<1>(0h0)) node _T_1946 = mux(_WIRE_6[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_1947 = mux(_WIRE_6[9], _T_1936, UInt<1>(0h0)) node _T_1948 = mux(_WIRE_6[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_1949 = mux(_WIRE_6[11], _T_1937, UInt<1>(0h0)) node _T_1950 = mux(_WIRE_6[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_1951 = or(_T_1938, _T_1939) node _T_1952 = or(_T_1951, _T_1940) node _T_1953 = or(_T_1952, _T_1941) node _T_1954 = or(_T_1953, _T_1942) node _T_1955 = or(_T_1954, _T_1943) node _T_1956 = or(_T_1955, _T_1944) node _T_1957 = or(_T_1956, _T_1945) node _T_1958 = or(_T_1957, _T_1946) node _T_1959 = or(_T_1958, _T_1947) node _T_1960 = or(_T_1959, _T_1948) node _T_1961 = or(_T_1960, _T_1949) node _T_1962 = or(_T_1961, _T_1950) wire _WIRE_7 : UInt<1> connect _WIRE_7, _T_1962 node _T_1963 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1964 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1965 = and(_T_1963, _T_1964) node _T_1966 = or(UInt<1>(0h0), _T_1965) node _T_1967 = xor(io.in.c.bits.address, UInt<28>(0h8000040)) node _T_1968 = cvt(_T_1967) node _T_1969 = and(_T_1968, asSInt(UInt<17>(0h100c0))) node _T_1970 = asSInt(_T_1969) node _T_1971 = eq(_T_1970, asSInt(UInt<1>(0h0))) node _T_1972 = xor(io.in.c.bits.address, UInt<32>(0h80000040)) node _T_1973 = cvt(_T_1972) node _T_1974 = and(_T_1973, asSInt(UInt<29>(0h100000c0))) node _T_1975 = asSInt(_T_1974) node _T_1976 = eq(_T_1975, asSInt(UInt<1>(0h0))) node _T_1977 = or(_T_1971, _T_1976) node _T_1978 = and(_T_1966, _T_1977) node _T_1979 = or(UInt<1>(0h0), _T_1978) node _T_1980 = and(_WIRE_7, _T_1979) node _T_1981 = asUInt(reset) node _T_1982 = eq(_T_1981, UInt<1>(0h0)) when _T_1982 : node _T_1983 = eq(_T_1980, UInt<1>(0h0)) when _T_1983 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_144 assert(clock, _T_1980, UInt<1>(0h1), "") : assert_144 node _T_1984 = asUInt(reset) node _T_1985 = eq(_T_1984, UInt<1>(0h0)) when _T_1985 : node _T_1986 = eq(source_ok_2, UInt<1>(0h0)) when _T_1986 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_145 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_145 node _T_1987 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_1988 = asUInt(reset) node _T_1989 = eq(_T_1988, UInt<1>(0h0)) when _T_1989 : node _T_1990 = eq(_T_1987, UInt<1>(0h0)) when _T_1990 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_146 assert(clock, _T_1987, UInt<1>(0h1), "") : assert_146 node _T_1991 = asUInt(reset) node _T_1992 = eq(_T_1991, UInt<1>(0h0)) when _T_1992 : node _T_1993 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1993 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_147 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_147 node _T_1994 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1995 = asUInt(reset) node _T_1996 = eq(_T_1995, UInt<1>(0h0)) when _T_1996 : node _T_1997 = eq(_T_1994, UInt<1>(0h0)) when _T_1997 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_148 assert(clock, _T_1994, UInt<1>(0h1), "") : assert_148 node _T_1998 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1999 = asUInt(reset) node _T_2000 = eq(_T_1999, UInt<1>(0h0)) when _T_2000 : node _T_2001 = eq(_T_1998, UInt<1>(0h0)) when _T_2001 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_149 assert(clock, _T_1998, UInt<1>(0h1), "") : assert_149 node _T_2002 = eq(io.in.c.bits.opcode, UInt<3>(0h7)) when _T_2002 : node _T_2003 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2004 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2005 = and(_T_2003, _T_2004) node _T_2006 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _uncommonBits_T_64 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_64 = bits(_uncommonBits_T_64, 1, 0) node _T_2007 = shr(io.in.c.bits.source, 2) node _T_2008 = eq(_T_2007, UInt<1>(0h0)) node _T_2009 = leq(UInt<1>(0h0), uncommonBits_64) node _T_2010 = and(_T_2008, _T_2009) node _T_2011 = leq(uncommonBits_64, UInt<2>(0h3)) node _T_2012 = and(_T_2010, _T_2011) node _uncommonBits_T_65 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_65 = bits(_uncommonBits_T_65, 1, 0) node _T_2013 = shr(io.in.c.bits.source, 2) node _T_2014 = eq(_T_2013, UInt<1>(0h1)) node _T_2015 = leq(UInt<1>(0h0), uncommonBits_65) node _T_2016 = and(_T_2014, _T_2015) node _T_2017 = leq(uncommonBits_65, UInt<2>(0h3)) node _T_2018 = and(_T_2016, _T_2017) node _uncommonBits_T_66 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_66 = bits(_uncommonBits_T_66, 1, 0) node _T_2019 = shr(io.in.c.bits.source, 2) node _T_2020 = eq(_T_2019, UInt<2>(0h2)) node _T_2021 = leq(UInt<1>(0h0), uncommonBits_66) node _T_2022 = and(_T_2020, _T_2021) node _T_2023 = leq(uncommonBits_66, UInt<2>(0h3)) node _T_2024 = and(_T_2022, _T_2023) node _uncommonBits_T_67 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_67 = bits(_uncommonBits_T_67, 1, 0) node _T_2025 = shr(io.in.c.bits.source, 2) node _T_2026 = eq(_T_2025, UInt<2>(0h3)) node _T_2027 = leq(UInt<1>(0h0), uncommonBits_67) node _T_2028 = and(_T_2026, _T_2027) node _T_2029 = leq(uncommonBits_67, UInt<2>(0h3)) node _T_2030 = and(_T_2028, _T_2029) node _T_2031 = eq(io.in.c.bits.source, UInt<6>(0h2c)) node _T_2032 = eq(io.in.c.bits.source, UInt<6>(0h2e)) node _T_2033 = eq(io.in.c.bits.source, UInt<6>(0h28)) node _T_2034 = eq(io.in.c.bits.source, UInt<6>(0h2a)) node _T_2035 = eq(io.in.c.bits.source, UInt<6>(0h24)) node _T_2036 = eq(io.in.c.bits.source, UInt<6>(0h26)) node _T_2037 = eq(io.in.c.bits.source, UInt<6>(0h20)) node _T_2038 = eq(io.in.c.bits.source, UInt<6>(0h22)) node _T_2039 = or(_T_2006, _T_2012) node _T_2040 = or(_T_2039, _T_2018) node _T_2041 = or(_T_2040, _T_2024) node _T_2042 = or(_T_2041, _T_2030) node _T_2043 = or(_T_2042, _T_2031) node _T_2044 = or(_T_2043, _T_2032) node _T_2045 = or(_T_2044, _T_2033) node _T_2046 = or(_T_2045, _T_2034) node _T_2047 = or(_T_2046, _T_2035) node _T_2048 = or(_T_2047, _T_2036) node _T_2049 = or(_T_2048, _T_2037) node _T_2050 = or(_T_2049, _T_2038) node _T_2051 = and(_T_2005, _T_2050) node _T_2052 = or(UInt<1>(0h0), _T_2051) node _T_2053 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2054 = or(UInt<1>(0h0), _T_2053) node _T_2055 = xor(io.in.c.bits.address, UInt<28>(0h8000040)) node _T_2056 = cvt(_T_2055) node _T_2057 = and(_T_2056, asSInt(UInt<17>(0h100c0))) node _T_2058 = asSInt(_T_2057) node _T_2059 = eq(_T_2058, asSInt(UInt<1>(0h0))) node _T_2060 = xor(io.in.c.bits.address, UInt<32>(0h80000040)) node _T_2061 = cvt(_T_2060) node _T_2062 = and(_T_2061, asSInt(UInt<29>(0h100000c0))) node _T_2063 = asSInt(_T_2062) node _T_2064 = eq(_T_2063, asSInt(UInt<1>(0h0))) node _T_2065 = or(_T_2059, _T_2064) node _T_2066 = and(_T_2054, _T_2065) node _T_2067 = or(UInt<1>(0h0), _T_2066) node _T_2068 = and(_T_2052, _T_2067) node _T_2069 = asUInt(reset) node _T_2070 = eq(_T_2069, UInt<1>(0h0)) when _T_2070 : node _T_2071 = eq(_T_2068, UInt<1>(0h0)) when _T_2071 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_150 assert(clock, _T_2068, UInt<1>(0h1), "") : assert_150 node _T_2072 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _uncommonBits_T_68 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_68 = bits(_uncommonBits_T_68, 1, 0) node _T_2073 = shr(io.in.c.bits.source, 2) node _T_2074 = eq(_T_2073, UInt<1>(0h0)) node _T_2075 = leq(UInt<1>(0h0), uncommonBits_68) node _T_2076 = and(_T_2074, _T_2075) node _T_2077 = leq(uncommonBits_68, UInt<2>(0h3)) node _T_2078 = and(_T_2076, _T_2077) node _uncommonBits_T_69 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_69 = bits(_uncommonBits_T_69, 1, 0) node _T_2079 = shr(io.in.c.bits.source, 2) node _T_2080 = eq(_T_2079, UInt<1>(0h1)) node _T_2081 = leq(UInt<1>(0h0), uncommonBits_69) node _T_2082 = and(_T_2080, _T_2081) node _T_2083 = leq(uncommonBits_69, UInt<2>(0h3)) node _T_2084 = and(_T_2082, _T_2083) node _uncommonBits_T_70 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_70 = bits(_uncommonBits_T_70, 1, 0) node _T_2085 = shr(io.in.c.bits.source, 2) node _T_2086 = eq(_T_2085, UInt<2>(0h2)) node _T_2087 = leq(UInt<1>(0h0), uncommonBits_70) node _T_2088 = and(_T_2086, _T_2087) node _T_2089 = leq(uncommonBits_70, UInt<2>(0h3)) node _T_2090 = and(_T_2088, _T_2089) node _uncommonBits_T_71 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_71 = bits(_uncommonBits_T_71, 1, 0) node _T_2091 = shr(io.in.c.bits.source, 2) node _T_2092 = eq(_T_2091, UInt<2>(0h3)) node _T_2093 = leq(UInt<1>(0h0), uncommonBits_71) node _T_2094 = and(_T_2092, _T_2093) node _T_2095 = leq(uncommonBits_71, UInt<2>(0h3)) node _T_2096 = and(_T_2094, _T_2095) node _T_2097 = eq(io.in.c.bits.source, UInt<6>(0h2c)) node _T_2098 = eq(io.in.c.bits.source, UInt<6>(0h2e)) node _T_2099 = eq(io.in.c.bits.source, UInt<6>(0h28)) node _T_2100 = eq(io.in.c.bits.source, UInt<6>(0h2a)) node _T_2101 = eq(io.in.c.bits.source, UInt<6>(0h24)) node _T_2102 = eq(io.in.c.bits.source, UInt<6>(0h26)) node _T_2103 = eq(io.in.c.bits.source, UInt<6>(0h20)) node _T_2104 = eq(io.in.c.bits.source, UInt<6>(0h22)) wire _WIRE_8 : UInt<1>[13] connect _WIRE_8[0], _T_2072 connect _WIRE_8[1], _T_2078 connect _WIRE_8[2], _T_2084 connect _WIRE_8[3], _T_2090 connect _WIRE_8[4], _T_2096 connect _WIRE_8[5], _T_2097 connect _WIRE_8[6], _T_2098 connect _WIRE_8[7], _T_2099 connect _WIRE_8[8], _T_2100 connect _WIRE_8[9], _T_2101 connect _WIRE_8[10], _T_2102 connect _WIRE_8[11], _T_2103 connect _WIRE_8[12], _T_2104 node _T_2105 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2106 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2107 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2108 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2109 = mux(_WIRE_8[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_2110 = mux(_WIRE_8[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_2111 = mux(_WIRE_8[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_2112 = mux(_WIRE_8[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_2113 = mux(_WIRE_8[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_2114 = mux(_WIRE_8[5], _T_2105, UInt<1>(0h0)) node _T_2115 = mux(_WIRE_8[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_2116 = mux(_WIRE_8[7], _T_2106, UInt<1>(0h0)) node _T_2117 = mux(_WIRE_8[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_2118 = mux(_WIRE_8[9], _T_2107, UInt<1>(0h0)) node _T_2119 = mux(_WIRE_8[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_2120 = mux(_WIRE_8[11], _T_2108, UInt<1>(0h0)) node _T_2121 = mux(_WIRE_8[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_2122 = or(_T_2109, _T_2110) node _T_2123 = or(_T_2122, _T_2111) node _T_2124 = or(_T_2123, _T_2112) node _T_2125 = or(_T_2124, _T_2113) node _T_2126 = or(_T_2125, _T_2114) node _T_2127 = or(_T_2126, _T_2115) node _T_2128 = or(_T_2127, _T_2116) node _T_2129 = or(_T_2128, _T_2117) node _T_2130 = or(_T_2129, _T_2118) node _T_2131 = or(_T_2130, _T_2119) node _T_2132 = or(_T_2131, _T_2120) node _T_2133 = or(_T_2132, _T_2121) wire _WIRE_9 : UInt<1> connect _WIRE_9, _T_2133 node _T_2134 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2135 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2136 = and(_T_2134, _T_2135) node _T_2137 = or(UInt<1>(0h0), _T_2136) node _T_2138 = xor(io.in.c.bits.address, UInt<28>(0h8000040)) node _T_2139 = cvt(_T_2138) node _T_2140 = and(_T_2139, asSInt(UInt<17>(0h100c0))) node _T_2141 = asSInt(_T_2140) node _T_2142 = eq(_T_2141, asSInt(UInt<1>(0h0))) node _T_2143 = xor(io.in.c.bits.address, UInt<32>(0h80000040)) node _T_2144 = cvt(_T_2143) node _T_2145 = and(_T_2144, asSInt(UInt<29>(0h100000c0))) node _T_2146 = asSInt(_T_2145) node _T_2147 = eq(_T_2146, asSInt(UInt<1>(0h0))) node _T_2148 = or(_T_2142, _T_2147) node _T_2149 = and(_T_2137, _T_2148) node _T_2150 = or(UInt<1>(0h0), _T_2149) node _T_2151 = and(_WIRE_9, _T_2150) node _T_2152 = asUInt(reset) node _T_2153 = eq(_T_2152, UInt<1>(0h0)) when _T_2153 : node _T_2154 = eq(_T_2151, UInt<1>(0h0)) when _T_2154 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_151 assert(clock, _T_2151, UInt<1>(0h1), "") : assert_151 node _T_2155 = asUInt(reset) node _T_2156 = eq(_T_2155, UInt<1>(0h0)) when _T_2156 : node _T_2157 = eq(source_ok_2, UInt<1>(0h0)) when _T_2157 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_152 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_152 node _T_2158 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_2159 = asUInt(reset) node _T_2160 = eq(_T_2159, UInt<1>(0h0)) when _T_2160 : node _T_2161 = eq(_T_2158, UInt<1>(0h0)) when _T_2161 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_153 assert(clock, _T_2158, UInt<1>(0h1), "") : assert_153 node _T_2162 = asUInt(reset) node _T_2163 = eq(_T_2162, UInt<1>(0h0)) when _T_2163 : node _T_2164 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2164 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_154 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_154 node _T_2165 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2166 = asUInt(reset) node _T_2167 = eq(_T_2166, UInt<1>(0h0)) when _T_2167 : node _T_2168 = eq(_T_2165, UInt<1>(0h0)) when _T_2168 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_155 assert(clock, _T_2165, UInt<1>(0h1), "") : assert_155 node _T_2169 = eq(io.in.c.bits.opcode, UInt<1>(0h0)) when _T_2169 : node _T_2170 = asUInt(reset) node _T_2171 = eq(_T_2170, UInt<1>(0h0)) when _T_2171 : node _T_2172 = eq(address_ok_1, UInt<1>(0h0)) when _T_2172 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_156 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_156 node _T_2173 = asUInt(reset) node _T_2174 = eq(_T_2173, UInt<1>(0h0)) when _T_2174 : node _T_2175 = eq(source_ok_2, UInt<1>(0h0)) when _T_2175 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_157 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_157 node _T_2176 = asUInt(reset) node _T_2177 = eq(_T_2176, UInt<1>(0h0)) when _T_2177 : node _T_2178 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2178 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_158 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_158 node _T_2179 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2180 = asUInt(reset) node _T_2181 = eq(_T_2180, UInt<1>(0h0)) when _T_2181 : node _T_2182 = eq(_T_2179, UInt<1>(0h0)) when _T_2182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_159 assert(clock, _T_2179, UInt<1>(0h1), "") : assert_159 node _T_2183 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2184 = asUInt(reset) node _T_2185 = eq(_T_2184, UInt<1>(0h0)) when _T_2185 : node _T_2186 = eq(_T_2183, UInt<1>(0h0)) when _T_2186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_160 assert(clock, _T_2183, UInt<1>(0h1), "") : assert_160 node _T_2187 = eq(io.in.c.bits.opcode, UInt<1>(0h1)) when _T_2187 : node _T_2188 = asUInt(reset) node _T_2189 = eq(_T_2188, UInt<1>(0h0)) when _T_2189 : node _T_2190 = eq(address_ok_1, UInt<1>(0h0)) when _T_2190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_161 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_161 node _T_2191 = asUInt(reset) node _T_2192 = eq(_T_2191, UInt<1>(0h0)) when _T_2192 : node _T_2193 = eq(source_ok_2, UInt<1>(0h0)) when _T_2193 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_162 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_162 node _T_2194 = asUInt(reset) node _T_2195 = eq(_T_2194, UInt<1>(0h0)) when _T_2195 : node _T_2196 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2196 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_163 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_163 node _T_2197 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2198 = asUInt(reset) node _T_2199 = eq(_T_2198, UInt<1>(0h0)) when _T_2199 : node _T_2200 = eq(_T_2197, UInt<1>(0h0)) when _T_2200 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_164 assert(clock, _T_2197, UInt<1>(0h1), "") : assert_164 node _T_2201 = eq(io.in.c.bits.opcode, UInt<2>(0h2)) when _T_2201 : node _T_2202 = asUInt(reset) node _T_2203 = eq(_T_2202, UInt<1>(0h0)) when _T_2203 : node _T_2204 = eq(address_ok_1, UInt<1>(0h0)) when _T_2204 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_165 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_165 node _T_2205 = asUInt(reset) node _T_2206 = eq(_T_2205, UInt<1>(0h0)) when _T_2206 : node _T_2207 = eq(source_ok_2, UInt<1>(0h0)) when _T_2207 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_166 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_166 node _T_2208 = asUInt(reset) node _T_2209 = eq(_T_2208, UInt<1>(0h0)) when _T_2209 : node _T_2210 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2210 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_167 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_167 node _T_2211 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2212 = asUInt(reset) node _T_2213 = eq(_T_2212, UInt<1>(0h0)) when _T_2213 : node _T_2214 = eq(_T_2211, UInt<1>(0h0)) when _T_2214 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_168 assert(clock, _T_2211, UInt<1>(0h1), "") : assert_168 node _T_2215 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2216 = asUInt(reset) node _T_2217 = eq(_T_2216, UInt<1>(0h0)) when _T_2217 : node _T_2218 = eq(_T_2215, UInt<1>(0h0)) when _T_2218 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_169 assert(clock, _T_2215, UInt<1>(0h1), "") : assert_169 when io.in.e.valid : node sink_ok_1 = lt(io.in.e.bits.sink, UInt<3>(0h7)) node _T_2219 = asUInt(reset) node _T_2220 = eq(_T_2219, UInt<1>(0h0)) when _T_2220 : node _T_2221 = eq(sink_ok_1, UInt<1>(0h0)) when _T_2221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channels carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_170 assert(clock, sink_ok_1, UInt<1>(0h1), "") : assert_170 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_2222 = eq(a_first, UInt<1>(0h0)) node _T_2223 = and(io.in.a.valid, _T_2222) when _T_2223 : node _T_2224 = eq(io.in.a.bits.opcode, opcode) node _T_2225 = asUInt(reset) node _T_2226 = eq(_T_2225, UInt<1>(0h0)) when _T_2226 : node _T_2227 = eq(_T_2224, UInt<1>(0h0)) when _T_2227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_171 assert(clock, _T_2224, UInt<1>(0h1), "") : assert_171 node _T_2228 = eq(io.in.a.bits.param, param) node _T_2229 = asUInt(reset) node _T_2230 = eq(_T_2229, UInt<1>(0h0)) when _T_2230 : node _T_2231 = eq(_T_2228, UInt<1>(0h0)) when _T_2231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_172 assert(clock, _T_2228, UInt<1>(0h1), "") : assert_172 node _T_2232 = eq(io.in.a.bits.size, size) node _T_2233 = asUInt(reset) node _T_2234 = eq(_T_2233, UInt<1>(0h0)) when _T_2234 : node _T_2235 = eq(_T_2232, UInt<1>(0h0)) when _T_2235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_173 assert(clock, _T_2232, UInt<1>(0h1), "") : assert_173 node _T_2236 = eq(io.in.a.bits.source, source) node _T_2237 = asUInt(reset) node _T_2238 = eq(_T_2237, UInt<1>(0h0)) when _T_2238 : node _T_2239 = eq(_T_2236, UInt<1>(0h0)) when _T_2239 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_174 assert(clock, _T_2236, UInt<1>(0h1), "") : assert_174 node _T_2240 = eq(io.in.a.bits.address, address) node _T_2241 = asUInt(reset) node _T_2242 = eq(_T_2241, UInt<1>(0h0)) when _T_2242 : node _T_2243 = eq(_T_2240, UInt<1>(0h0)) when _T_2243 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_175 assert(clock, _T_2240, UInt<1>(0h1), "") : assert_175 node _T_2244 = and(io.in.a.ready, io.in.a.valid) node _T_2245 = and(_T_2244, a_first) when _T_2245 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_2246 = eq(d_first, UInt<1>(0h0)) node _T_2247 = and(io.in.d.valid, _T_2246) when _T_2247 : node _T_2248 = eq(io.in.d.bits.opcode, opcode_1) node _T_2249 = asUInt(reset) node _T_2250 = eq(_T_2249, UInt<1>(0h0)) when _T_2250 : node _T_2251 = eq(_T_2248, UInt<1>(0h0)) when _T_2251 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_176 assert(clock, _T_2248, UInt<1>(0h1), "") : assert_176 node _T_2252 = eq(io.in.d.bits.param, param_1) node _T_2253 = asUInt(reset) node _T_2254 = eq(_T_2253, UInt<1>(0h0)) when _T_2254 : node _T_2255 = eq(_T_2252, UInt<1>(0h0)) when _T_2255 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_177 assert(clock, _T_2252, UInt<1>(0h1), "") : assert_177 node _T_2256 = eq(io.in.d.bits.size, size_1) node _T_2257 = asUInt(reset) node _T_2258 = eq(_T_2257, UInt<1>(0h0)) when _T_2258 : node _T_2259 = eq(_T_2256, UInt<1>(0h0)) when _T_2259 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_178 assert(clock, _T_2256, UInt<1>(0h1), "") : assert_178 node _T_2260 = eq(io.in.d.bits.source, source_1) node _T_2261 = asUInt(reset) node _T_2262 = eq(_T_2261, UInt<1>(0h0)) when _T_2262 : node _T_2263 = eq(_T_2260, UInt<1>(0h0)) when _T_2263 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_179 assert(clock, _T_2260, UInt<1>(0h1), "") : assert_179 node _T_2264 = eq(io.in.d.bits.sink, sink) node _T_2265 = asUInt(reset) node _T_2266 = eq(_T_2265, UInt<1>(0h0)) when _T_2266 : node _T_2267 = eq(_T_2264, UInt<1>(0h0)) when _T_2267 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_180 assert(clock, _T_2264, UInt<1>(0h1), "") : assert_180 node _T_2268 = eq(io.in.d.bits.denied, denied) node _T_2269 = asUInt(reset) node _T_2270 = eq(_T_2269, UInt<1>(0h0)) when _T_2270 : node _T_2271 = eq(_T_2268, UInt<1>(0h0)) when _T_2271 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_181 assert(clock, _T_2268, UInt<1>(0h1), "") : assert_181 node _T_2272 = and(io.in.d.ready, io.in.d.valid) node _T_2273 = and(_T_2272, d_first) when _T_2273 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied node _b_first_T = and(io.in.b.ready, io.in.b.valid) node _b_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.b.bits.size) node _b_first_beats1_decode_T_1 = bits(_b_first_beats1_decode_T, 5, 0) node _b_first_beats1_decode_T_2 = not(_b_first_beats1_decode_T_1) node b_first_beats1_decode = shr(_b_first_beats1_decode_T_2, 3) node _b_first_beats1_opdata_T = bits(io.in.b.bits.opcode, 2, 2) node b_first_beats1_opdata = eq(_b_first_beats1_opdata_T, UInt<1>(0h0)) node b_first_beats1 = mux(UInt<1>(0h0), b_first_beats1_decode, UInt<1>(0h0)) regreset b_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _b_first_counter1_T = sub(b_first_counter, UInt<1>(0h1)) node b_first_counter1 = tail(_b_first_counter1_T, 1) node b_first = eq(b_first_counter, UInt<1>(0h0)) node _b_first_last_T = eq(b_first_counter, UInt<1>(0h1)) node _b_first_last_T_1 = eq(b_first_beats1, UInt<1>(0h0)) node b_first_last = or(_b_first_last_T, _b_first_last_T_1) node b_first_done = and(b_first_last, _b_first_T) node _b_first_count_T = not(b_first_counter1) node b_first_count = and(b_first_beats1, _b_first_count_T) when _b_first_T : node _b_first_counter_T = mux(b_first, b_first_beats1, b_first_counter1) connect b_first_counter, _b_first_counter_T reg opcode_2 : UInt, clock reg param_2 : UInt, clock reg size_2 : UInt, clock reg source_2 : UInt, clock reg address_1 : UInt, clock node _T_2274 = eq(b_first, UInt<1>(0h0)) node _T_2275 = and(io.in.b.valid, _T_2274) when _T_2275 : node _T_2276 = eq(io.in.b.bits.opcode, opcode_2) node _T_2277 = asUInt(reset) node _T_2278 = eq(_T_2277, UInt<1>(0h0)) when _T_2278 : node _T_2279 = eq(_T_2276, UInt<1>(0h0)) when _T_2279 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_182 assert(clock, _T_2276, UInt<1>(0h1), "") : assert_182 node _T_2280 = eq(io.in.b.bits.param, param_2) node _T_2281 = asUInt(reset) node _T_2282 = eq(_T_2281, UInt<1>(0h0)) when _T_2282 : node _T_2283 = eq(_T_2280, UInt<1>(0h0)) when _T_2283 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_183 assert(clock, _T_2280, UInt<1>(0h1), "") : assert_183 node _T_2284 = eq(io.in.b.bits.size, size_2) node _T_2285 = asUInt(reset) node _T_2286 = eq(_T_2285, UInt<1>(0h0)) when _T_2286 : node _T_2287 = eq(_T_2284, UInt<1>(0h0)) when _T_2287 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_184 assert(clock, _T_2284, UInt<1>(0h1), "") : assert_184 node _T_2288 = eq(io.in.b.bits.source, source_2) node _T_2289 = asUInt(reset) node _T_2290 = eq(_T_2289, UInt<1>(0h0)) when _T_2290 : node _T_2291 = eq(_T_2288, UInt<1>(0h0)) when _T_2291 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_185 assert(clock, _T_2288, UInt<1>(0h1), "") : assert_185 node _T_2292 = eq(io.in.b.bits.address, address_1) node _T_2293 = asUInt(reset) node _T_2294 = eq(_T_2293, UInt<1>(0h0)) when _T_2294 : node _T_2295 = eq(_T_2292, UInt<1>(0h0)) when _T_2295 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_186 assert(clock, _T_2292, UInt<1>(0h1), "") : assert_186 node _T_2296 = and(io.in.b.ready, io.in.b.valid) node _T_2297 = and(_T_2296, b_first) when _T_2297 : connect opcode_2, io.in.b.bits.opcode connect param_2, io.in.b.bits.param connect size_2, io.in.b.bits.size connect source_2, io.in.b.bits.source connect address_1, io.in.b.bits.address node _c_first_T = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.c.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T reg opcode_3 : UInt, clock reg param_3 : UInt, clock reg size_3 : UInt, clock reg source_3 : UInt, clock reg address_2 : UInt, clock node _T_2298 = eq(c_first, UInt<1>(0h0)) node _T_2299 = and(io.in.c.valid, _T_2298) when _T_2299 : node _T_2300 = eq(io.in.c.bits.opcode, opcode_3) node _T_2301 = asUInt(reset) node _T_2302 = eq(_T_2301, UInt<1>(0h0)) when _T_2302 : node _T_2303 = eq(_T_2300, UInt<1>(0h0)) when _T_2303 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_187 assert(clock, _T_2300, UInt<1>(0h1), "") : assert_187 node _T_2304 = eq(io.in.c.bits.param, param_3) node _T_2305 = asUInt(reset) node _T_2306 = eq(_T_2305, UInt<1>(0h0)) when _T_2306 : node _T_2307 = eq(_T_2304, UInt<1>(0h0)) when _T_2307 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_188 assert(clock, _T_2304, UInt<1>(0h1), "") : assert_188 node _T_2308 = eq(io.in.c.bits.size, size_3) node _T_2309 = asUInt(reset) node _T_2310 = eq(_T_2309, UInt<1>(0h0)) when _T_2310 : node _T_2311 = eq(_T_2308, UInt<1>(0h0)) when _T_2311 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_189 assert(clock, _T_2308, UInt<1>(0h1), "") : assert_189 node _T_2312 = eq(io.in.c.bits.source, source_3) node _T_2313 = asUInt(reset) node _T_2314 = eq(_T_2313, UInt<1>(0h0)) when _T_2314 : node _T_2315 = eq(_T_2312, UInt<1>(0h0)) when _T_2315 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_190 assert(clock, _T_2312, UInt<1>(0h1), "") : assert_190 node _T_2316 = eq(io.in.c.bits.address, address_2) node _T_2317 = asUInt(reset) node _T_2318 = eq(_T_2317, UInt<1>(0h0)) when _T_2318 : node _T_2319 = eq(_T_2316, UInt<1>(0h0)) when _T_2319 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_191 assert(clock, _T_2316, UInt<1>(0h1), "") : assert_191 node _T_2320 = and(io.in.c.ready, io.in.c.valid) node _T_2321 = and(_T_2320, c_first) when _T_2321 : connect opcode_3, io.in.c.bits.opcode connect param_3, io.in.c.bits.param connect size_3, io.in.c.bits.size connect source_3, io.in.c.bits.source connect address_2, io.in.c.bits.address regreset inflight : UInt<47>, clock, reset, UInt<47>(0h0) regreset inflight_opcodes : UInt<188>, clock, reset, UInt<188>(0h0) regreset inflight_sizes : UInt<188>, clock, reset, UInt<188>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<47> connect a_set, UInt<47>(0h0) wire a_set_wo_ready : UInt<47> connect a_set_wo_ready, UInt<47>(0h0) wire a_opcodes_set : UInt<188> connect a_opcodes_set, UInt<188>(0h0) wire a_sizes_set : UInt<188> connect a_sizes_set, UInt<188>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_2322 = and(io.in.a.valid, a_first_1) node _T_2323 = and(_T_2322, UInt<1>(0h1)) when _T_2323 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_2324 = and(io.in.a.ready, io.in.a.valid) node _T_2325 = and(_T_2324, a_first_1) node _T_2326 = and(_T_2325, UInt<1>(0h1)) when _T_2326 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_2327 = dshr(inflight, io.in.a.bits.source) node _T_2328 = bits(_T_2327, 0, 0) node _T_2329 = eq(_T_2328, UInt<1>(0h0)) node _T_2330 = asUInt(reset) node _T_2331 = eq(_T_2330, UInt<1>(0h0)) when _T_2331 : node _T_2332 = eq(_T_2329, UInt<1>(0h0)) when _T_2332 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_192 assert(clock, _T_2329, UInt<1>(0h1), "") : assert_192 wire d_clr : UInt<47> connect d_clr, UInt<47>(0h0) wire d_clr_wo_ready : UInt<47> connect d_clr_wo_ready, UInt<47>(0h0) wire d_opcodes_clr : UInt<188> connect d_opcodes_clr, UInt<188>(0h0) wire d_sizes_clr : UInt<188> connect d_sizes_clr, UInt<188>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2333 = and(io.in.d.valid, d_first_1) node _T_2334 = and(_T_2333, UInt<1>(0h1)) node _T_2335 = eq(d_release_ack, UInt<1>(0h0)) node _T_2336 = and(_T_2334, _T_2335) when _T_2336 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_2337 = and(io.in.d.ready, io.in.d.valid) node _T_2338 = and(_T_2337, d_first_1) node _T_2339 = and(_T_2338, UInt<1>(0h1)) node _T_2340 = eq(d_release_ack, UInt<1>(0h0)) node _T_2341 = and(_T_2339, _T_2340) when _T_2341 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_2342 = and(io.in.d.valid, d_first_1) node _T_2343 = and(_T_2342, UInt<1>(0h1)) node _T_2344 = eq(d_release_ack, UInt<1>(0h0)) node _T_2345 = and(_T_2343, _T_2344) when _T_2345 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_2346 = dshr(inflight, io.in.d.bits.source) node _T_2347 = bits(_T_2346, 0, 0) node _T_2348 = or(_T_2347, same_cycle_resp) node _T_2349 = asUInt(reset) node _T_2350 = eq(_T_2349, UInt<1>(0h0)) when _T_2350 : node _T_2351 = eq(_T_2348, UInt<1>(0h0)) when _T_2351 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_193 assert(clock, _T_2348, UInt<1>(0h1), "") : assert_193 when same_cycle_resp : node _T_2352 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_2353 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_2354 = or(_T_2352, _T_2353) node _T_2355 = asUInt(reset) node _T_2356 = eq(_T_2355, UInt<1>(0h0)) when _T_2356 : node _T_2357 = eq(_T_2354, UInt<1>(0h0)) when _T_2357 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_194 assert(clock, _T_2354, UInt<1>(0h1), "") : assert_194 node _T_2358 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_2359 = asUInt(reset) node _T_2360 = eq(_T_2359, UInt<1>(0h0)) when _T_2360 : node _T_2361 = eq(_T_2358, UInt<1>(0h0)) when _T_2361 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_195 assert(clock, _T_2358, UInt<1>(0h1), "") : assert_195 else : node _T_2362 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_2363 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_2364 = or(_T_2362, _T_2363) node _T_2365 = asUInt(reset) node _T_2366 = eq(_T_2365, UInt<1>(0h0)) when _T_2366 : node _T_2367 = eq(_T_2364, UInt<1>(0h0)) when _T_2367 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_196 assert(clock, _T_2364, UInt<1>(0h1), "") : assert_196 node _T_2368 = eq(io.in.d.bits.size, a_size_lookup) node _T_2369 = asUInt(reset) node _T_2370 = eq(_T_2369, UInt<1>(0h0)) when _T_2370 : node _T_2371 = eq(_T_2368, UInt<1>(0h0)) when _T_2371 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_197 assert(clock, _T_2368, UInt<1>(0h1), "") : assert_197 node _T_2372 = and(io.in.d.valid, d_first_1) node _T_2373 = and(_T_2372, a_first_1) node _T_2374 = and(_T_2373, io.in.a.valid) node _T_2375 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_2376 = and(_T_2374, _T_2375) node _T_2377 = eq(d_release_ack, UInt<1>(0h0)) node _T_2378 = and(_T_2376, _T_2377) when _T_2378 : node _T_2379 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2380 = or(_T_2379, io.in.a.ready) node _T_2381 = asUInt(reset) node _T_2382 = eq(_T_2381, UInt<1>(0h0)) when _T_2382 : node _T_2383 = eq(_T_2380, UInt<1>(0h0)) when _T_2383 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_198 assert(clock, _T_2380, UInt<1>(0h1), "") : assert_198 node _T_2384 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_2385 = orr(a_set_wo_ready) node _T_2386 = eq(_T_2385, UInt<1>(0h0)) node _T_2387 = or(_T_2384, _T_2386) node _T_2388 = asUInt(reset) node _T_2389 = eq(_T_2388, UInt<1>(0h0)) when _T_2389 : node _T_2390 = eq(_T_2387, UInt<1>(0h0)) when _T_2390 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_199 assert(clock, _T_2387, UInt<1>(0h1), "") : assert_199 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_99 node _T_2391 = orr(inflight) node _T_2392 = eq(_T_2391, UInt<1>(0h0)) node _T_2393 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_2394 = or(_T_2392, _T_2393) node _T_2395 = lt(watchdog, plusarg_reader.out) node _T_2396 = or(_T_2394, _T_2395) node _T_2397 = asUInt(reset) node _T_2398 = eq(_T_2397, UInt<1>(0h0)) when _T_2398 : node _T_2399 = eq(_T_2396, UInt<1>(0h0)) when _T_2399 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_200 assert(clock, _T_2396, UInt<1>(0h1), "") : assert_200 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_2400 = and(io.in.a.ready, io.in.a.valid) node _T_2401 = and(io.in.d.ready, io.in.d.valid) node _T_2402 = or(_T_2400, _T_2401) when _T_2402 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<47>, clock, reset, UInt<47>(0h0) regreset inflight_opcodes_1 : UInt<188>, clock, reset, UInt<188>(0h0) regreset inflight_sizes_1 : UInt<188>, clock, reset, UInt<188>(0h0) node _c_first_T_1 = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.c.bits.size) node _c_first_beats1_decode_T_4 = bits(_c_first_beats1_decode_T_3, 5, 0) node _c_first_beats1_decode_T_5 = not(_c_first_beats1_decode_T_4) node c_first_beats1_decode_1 = shr(_c_first_beats1_decode_T_5, 3) node c_first_beats1_opdata_1 = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1_1 = mux(c_first_beats1_opdata_1, c_first_beats1_decode_1, UInt<1>(0h0)) regreset c_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T_1 = sub(c_first_counter_1, UInt<1>(0h1)) node c_first_counter1_1 = tail(_c_first_counter1_T_1, 1) node c_first_1 = eq(c_first_counter_1, UInt<1>(0h0)) node _c_first_last_T_2 = eq(c_first_counter_1, UInt<1>(0h1)) node _c_first_last_T_3 = eq(c_first_beats1_1, UInt<1>(0h0)) node c_first_last_1 = or(_c_first_last_T_2, _c_first_last_T_3) node c_first_done_1 = and(c_first_last_1, _c_first_T_1) node _c_first_count_T_1 = not(c_first_counter1_1) node c_first_count_1 = and(c_first_beats1_1, _c_first_count_T_1) when _c_first_T_1 : node _c_first_counter_T_1 = mux(c_first_1, c_first_beats1_1, c_first_counter1_1) connect c_first_counter_1, _c_first_counter_T_1 node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<47> connect c_set, UInt<47>(0h0) wire c_set_wo_ready : UInt<47> connect c_set_wo_ready, UInt<47>(0h0) wire c_opcodes_set : UInt<188> connect c_opcodes_set, UInt<188>(0h0) wire c_sizes_set : UInt<188> connect c_sizes_set, UInt<188>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) node _T_2403 = and(io.in.c.valid, c_first_1) node _T_2404 = bits(io.in.c.bits.opcode, 2, 2) node _T_2405 = bits(io.in.c.bits.opcode, 1, 1) node _T_2406 = and(_T_2404, _T_2405) node _T_2407 = and(_T_2403, _T_2406) when _T_2407 : node _c_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T node _T_2408 = and(io.in.c.ready, io.in.c.valid) node _T_2409 = and(_T_2408, c_first_1) node _T_2410 = bits(io.in.c.bits.opcode, 2, 2) node _T_2411 = bits(io.in.c.bits.opcode, 1, 1) node _T_2412 = and(_T_2410, _T_2411) node _T_2413 = and(_T_2409, _T_2412) when _T_2413 : node _c_set_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set, _c_set_T node _c_opcodes_set_interm_T = dshl(io.in.c.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 node _c_sizes_set_interm_T = dshl(io.in.c.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 node _c_opcodes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 node _c_sizes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 node _T_2414 = dshr(inflight_1, io.in.c.bits.source) node _T_2415 = bits(_T_2414, 0, 0) node _T_2416 = eq(_T_2415, UInt<1>(0h0)) node _T_2417 = asUInt(reset) node _T_2418 = eq(_T_2417, UInt<1>(0h0)) when _T_2418 : node _T_2419 = eq(_T_2416, UInt<1>(0h0)) when _T_2419 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_201 assert(clock, _T_2416, UInt<1>(0h1), "") : assert_201 node _c_probe_ack_T = eq(io.in.c.bits.opcode, UInt<3>(0h4)) node _c_probe_ack_T_1 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<47> connect d_clr_1, UInt<47>(0h0) wire d_clr_wo_ready_1 : UInt<47> connect d_clr_wo_ready_1, UInt<47>(0h0) wire d_opcodes_clr_1 : UInt<188> connect d_opcodes_clr_1, UInt<188>(0h0) wire d_sizes_clr_1 : UInt<188> connect d_sizes_clr_1, UInt<188>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2420 = and(io.in.d.valid, d_first_2) node _T_2421 = and(_T_2420, UInt<1>(0h1)) node _T_2422 = and(_T_2421, d_release_ack_1) when _T_2422 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_2423 = and(io.in.d.ready, io.in.d.valid) node _T_2424 = and(_T_2423, d_first_2) node _T_2425 = and(_T_2424, UInt<1>(0h1)) node _T_2426 = and(_T_2425, d_release_ack_1) when _T_2426 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_2427 = and(io.in.d.valid, d_first_2) node _T_2428 = and(_T_2427, UInt<1>(0h1)) node _T_2429 = and(_T_2428, d_release_ack_1) when _T_2429 : node _same_cycle_resp_T_3 = and(io.in.c.valid, c_first_1) node _same_cycle_resp_T_4 = bits(io.in.c.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(io.in.c.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) node _same_cycle_resp_T_8 = eq(io.in.c.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_2430 = dshr(inflight_1, io.in.d.bits.source) node _T_2431 = bits(_T_2430, 0, 0) node _T_2432 = or(_T_2431, same_cycle_resp_1) node _T_2433 = asUInt(reset) node _T_2434 = eq(_T_2433, UInt<1>(0h0)) when _T_2434 : node _T_2435 = eq(_T_2432, UInt<1>(0h0)) when _T_2435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_202 assert(clock, _T_2432, UInt<1>(0h1), "") : assert_202 when same_cycle_resp_1 : node _T_2436 = eq(io.in.d.bits.size, io.in.c.bits.size) node _T_2437 = asUInt(reset) node _T_2438 = eq(_T_2437, UInt<1>(0h0)) when _T_2438 : node _T_2439 = eq(_T_2436, UInt<1>(0h0)) when _T_2439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_203 assert(clock, _T_2436, UInt<1>(0h1), "") : assert_203 else : node _T_2440 = eq(io.in.d.bits.size, c_size_lookup) node _T_2441 = asUInt(reset) node _T_2442 = eq(_T_2441, UInt<1>(0h0)) when _T_2442 : node _T_2443 = eq(_T_2440, UInt<1>(0h0)) when _T_2443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_204 assert(clock, _T_2440, UInt<1>(0h1), "") : assert_204 node _T_2444 = and(io.in.d.valid, d_first_2) node _T_2445 = and(_T_2444, c_first_1) node _T_2446 = and(_T_2445, io.in.c.valid) node _T_2447 = eq(io.in.c.bits.source, io.in.d.bits.source) node _T_2448 = and(_T_2446, _T_2447) node _T_2449 = and(_T_2448, d_release_ack_1) node _T_2450 = eq(c_probe_ack, UInt<1>(0h0)) node _T_2451 = and(_T_2449, _T_2450) when _T_2451 : node _T_2452 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2453 = or(_T_2452, io.in.c.ready) node _T_2454 = asUInt(reset) node _T_2455 = eq(_T_2454, UInt<1>(0h0)) when _T_2455 : node _T_2456 = eq(_T_2453, UInt<1>(0h0)) when _T_2456 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_205 assert(clock, _T_2453, UInt<1>(0h1), "") : assert_205 node _T_2457 = orr(c_set_wo_ready) when _T_2457 : node _T_2458 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_2459 = asUInt(reset) node _T_2460 = eq(_T_2459, UInt<1>(0h0)) when _T_2460 : node _T_2461 = eq(_T_2458, UInt<1>(0h0)) when _T_2461 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_206 assert(clock, _T_2458, UInt<1>(0h1), "") : assert_206 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_100 node _T_2462 = orr(inflight_1) node _T_2463 = eq(_T_2462, UInt<1>(0h0)) node _T_2464 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_2465 = or(_T_2463, _T_2464) node _T_2466 = lt(watchdog_1, plusarg_reader_1.out) node _T_2467 = or(_T_2465, _T_2466) node _T_2468 = asUInt(reset) node _T_2469 = eq(_T_2468, UInt<1>(0h0)) when _T_2469 : node _T_2470 = eq(_T_2467, UInt<1>(0h0)) when _T_2470 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_207 assert(clock, _T_2467, UInt<1>(0h1), "") : assert_207 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 node _T_2471 = and(io.in.c.ready, io.in.c.valid) node _T_2472 = and(io.in.d.ready, io.in.d.valid) node _T_2473 = or(_T_2471, _T_2472) when _T_2473 : connect watchdog_1, UInt<1>(0h0) regreset inflight_2 : UInt<7>, clock, reset, UInt<7>(0h0) node _d_first_T_3 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_9 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_10 = bits(_d_first_beats1_decode_T_9, 5, 0) node _d_first_beats1_decode_T_11 = not(_d_first_beats1_decode_T_10) node d_first_beats1_decode_3 = shr(_d_first_beats1_decode_T_11, 3) node d_first_beats1_opdata_3 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_3 = mux(d_first_beats1_opdata_3, d_first_beats1_decode_3, UInt<1>(0h0)) regreset d_first_counter_3 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_3 = sub(d_first_counter_3, UInt<1>(0h1)) node d_first_counter1_3 = tail(_d_first_counter1_T_3, 1) node d_first_3 = eq(d_first_counter_3, UInt<1>(0h0)) node _d_first_last_T_6 = eq(d_first_counter_3, UInt<1>(0h1)) node _d_first_last_T_7 = eq(d_first_beats1_3, UInt<1>(0h0)) node d_first_last_3 = or(_d_first_last_T_6, _d_first_last_T_7) node d_first_done_3 = and(d_first_last_3, _d_first_T_3) node _d_first_count_T_3 = not(d_first_counter1_3) node d_first_count_3 = and(d_first_beats1_3, _d_first_count_T_3) when _d_first_T_3 : node _d_first_counter_T_3 = mux(d_first_3, d_first_beats1_3, d_first_counter1_3) connect d_first_counter_3, _d_first_counter_T_3 wire d_set : UInt<7> connect d_set, UInt<7>(0h0) node _T_2474 = and(io.in.d.ready, io.in.d.valid) node _T_2475 = and(_T_2474, d_first_3) node _T_2476 = bits(io.in.d.bits.opcode, 2, 2) node _T_2477 = bits(io.in.d.bits.opcode, 1, 1) node _T_2478 = eq(_T_2477, UInt<1>(0h0)) node _T_2479 = and(_T_2476, _T_2478) node _T_2480 = and(_T_2475, _T_2479) when _T_2480 : node _d_set_T = dshl(UInt<1>(0h1), io.in.d.bits.sink) connect d_set, _d_set_T node _T_2481 = dshr(inflight_2, io.in.d.bits.sink) node _T_2482 = bits(_T_2481, 0, 0) node _T_2483 = eq(_T_2482, UInt<1>(0h0)) node _T_2484 = asUInt(reset) node _T_2485 = eq(_T_2484, UInt<1>(0h0)) when _T_2485 : node _T_2486 = eq(_T_2483, UInt<1>(0h0)) when _T_2486 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel re-used a sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_208 assert(clock, _T_2483, UInt<1>(0h1), "") : assert_208 wire e_clr : UInt<7> connect e_clr, UInt<7>(0h0) node _T_2487 = and(io.in.e.ready, io.in.e.valid) node _T_2488 = and(_T_2487, UInt<1>(0h1)) node _T_2489 = and(_T_2488, UInt<1>(0h1)) when _T_2489 : node _e_clr_T = dshl(UInt<1>(0h1), io.in.e.bits.sink) connect e_clr, _e_clr_T node _T_2490 = or(d_set, inflight_2) node _T_2491 = dshr(_T_2490, io.in.e.bits.sink) node _T_2492 = bits(_T_2491, 0, 0) node _T_2493 = asUInt(reset) node _T_2494 = eq(_T_2493, UInt<1>(0h0)) when _T_2494 : node _T_2495 = eq(_T_2492, UInt<1>(0h0)) when _T_2495 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_209 assert(clock, _T_2492, UInt<1>(0h1), "") : assert_209 node _inflight_T_6 = or(inflight_2, d_set) node _inflight_T_7 = not(e_clr) node _inflight_T_8 = and(_inflight_T_6, _inflight_T_7) connect inflight_2, _inflight_T_8 extmodule plusarg_reader_101 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_102 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32	module TLMonitor_45( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_b_ready, // @[Monitor.scala:20:14] input io_in_b_valid, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14] input [5:0] io_in_b_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input io_in_c_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [2:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire [12:0] _GEN_0 = {10'h0, io_in_c_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [2:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [5:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _d_first_T_3 = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala:51:35] reg [2:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [5:0] source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [2:0] b_first_counter; // @[Edges.scala:229:27] reg [1:0] param_2; // @[Monitor.scala:411:22] reg [5:0] source_2; // @[Monitor.scala:413:22] reg [31:0] address_1; // @[Monitor.scala:414:22] wire _c_first_T_1 = io_in_c_ready & io_in_c_valid; // @[Decoupled.scala:51:35] reg [2:0] c_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [2:0] size_3; // @[Monitor.scala:517:22] reg [5:0] source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [46:0] inflight; // @[Monitor.scala:614:27] reg [187:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [187:0] inflight_sizes; // @[Monitor.scala:618:33] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire [63:0] _GEN_1 = {58'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35] wire _GEN_2 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_3 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] wire [63:0] _GEN_4 = {58'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [46:0] inflight_1; // @[Monitor.scala:726:35] reg [187:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [2:0] c_first_counter_1; // @[Edges.scala:229:27] wire c_first_1 = c_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _GEN_5 = io_in_c_bits_opcode[2] & io_in_c_bits_opcode[1]; // @[Edges.scala:68:{36,40,51}] wire [63:0] _GEN_6 = {58'h0, io_in_c_bits_source}; // @[OneHot.scala:58:35] wire _GEN_7 = _c_first_T_1 & c_first_1 & _GEN_5; // @[Decoupled.scala:51:35] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] reg [6:0] inflight_2; // @[Monitor.scala:828:27] reg [2:0] d_first_counter_3; // @[Edges.scala:229:27] wire d_first_3 = d_first_counter_3 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _GEN_8 = _d_first_T_3 & d_first_3 & io_in_d_bits_opcode[2] & ~(io_in_d_bits_opcode[1]); // @[Decoupled.scala:51:35] wire [7:0] _d_set_T = 8'h1 << io_in_d_bits_sink; // @[OneHot.scala:58:35] wire [6:0] d_set = _GEN_8 ? _d_set_T[6:0] : 7'h0; // @[OneHot.scala:58:35]
Generate the Verilog code corresponding to this FIRRTL code module PE_3 : input clock : Clock input reset : Reset output io : { flip inR : SInt<8>, flip inD : SInt<8>, outL : SInt<8>, outU : SInt<8>, flip dir : UInt<1>, flip en : UInt<1>} node _reg_T = eq(io.dir, UInt<1>(0h0)) node _reg_T_1 = mux(_reg_T, io.inR, io.inD) reg reg : SInt<8>, clock when io.en : connect reg, _reg_T_1 connect io.outU, reg connect io.outL, reg	module PE_3( // @[Transposer.scala:100:9] input clock, // @[Transposer.scala:100:9] input reset, // @[Transposer.scala:100:9] input [7:0] io_inR, // @[Transposer.scala:101:16] input [7:0] io_inD, // @[Transposer.scala:101:16] output [7:0] io_outL, // @[Transposer.scala:101:16] output [7:0] io_outU, // @[Transposer.scala:101:16] input io_dir, // @[Transposer.scala:101:16] input io_en // @[Transposer.scala:101:16] ); wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9] wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9] wire io_dir_0 = io_dir; // @[Transposer.scala:100:9] wire io_en_0 = io_en; // @[Transposer.scala:100:9] wire [7:0] io_outL_0; // @[Transposer.scala:100:9] wire [7:0] io_outU_0; // @[Transposer.scala:100:9] wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36] wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}] reg [7:0] reg_0; // @[Transposer.scala:110:24] assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24] assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24] always @(posedge clock) begin // @[Transposer.scala:100:9] if (io_en_0) // @[Transposer.scala:100:9] reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}] always @(posedge) assign io_outL = io_outL_0; // @[Transposer.scala:100:9] assign io_outU = io_outU_0; // @[Transposer.scala:100:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module BoomMSHR_12 : input clock : Clock input reset : Reset output io : { flip id : UInt, flip req_pri_val : UInt<1>, req_pri_rdy : UInt<1>, flip req_sec_val : UInt<1>, req_sec_rdy : UInt<1>, flip clear_prefetch : UInt<1>, flip brupdate : { b1 : { resolve_mask : UInt<4>, mispredict_mask : UInt<4>}, b2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<1>, iw_p2_speculative_child : UInt<1>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<5>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<34>, target_offset : SInt<21>}}, flip exception : UInt<1>, flip rob_pnr_idx : UInt<5>, flip rob_head_idx : UInt<5>, flip req : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<1>, iw_p2_speculative_child : UInt<1>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<5>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<22>}, way_en : UInt<2>, sdq_id : UInt<5>}, flip req_is_probe : UInt<1>, idx : { valid : UInt<1>, bits : UInt}, way : { valid : UInt<1>, bits : UInt}, tag : { valid : UInt<1>, bits : UInt}, mem_acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip mem_grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, mem_finish : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}, flip prober_state : { valid : UInt<1>, bits : UInt<34>}, refill : { flip ready : UInt<1>, valid : UInt<1>, bits : { way_en : UInt<2>, addr : UInt<10>, wmask : UInt<1>, data : UInt<64>}}, meta_write : { flip ready : UInt<1>, valid : UInt<1>, bits : { idx : UInt<4>, way_en : UInt<2>, tag : UInt<22>, data : { coh : { state : UInt<2>}, tag : UInt<22>}}}, meta_read : { flip ready : UInt<1>, valid : UInt<1>, bits : { idx : UInt<4>, way_en : UInt<2>, tag : UInt<22>}}, flip meta_resp : { valid : UInt<1>, bits : { coh : { state : UInt<2>}, tag : UInt<22>}}, wb_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { tag : UInt<22>, idx : UInt<4>, source : UInt<4>, param : UInt<3>, way_en : UInt<2>, voluntary : UInt<1>}}, commit_val : UInt<1>, commit_addr : UInt<34>, commit_coh : { state : UInt<2>}, lb_read : { offset : UInt<3>}, flip lb_resp : UInt<64>, lb_write : { valid : UInt<1>, bits : { offset : UInt<3>, data : UInt<64>}}, replay : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<1>, iw_p2_speculative_child : UInt<1>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<5>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<22>}, way_en : UInt<2>, sdq_id : UInt<5>}}, resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<1>, iw_p2_speculative_child : UInt<1>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<5>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, data : UInt<64>, is_hella : UInt<1>}}, flip wb_resp : UInt<1>, probe_rdy : UInt<1>} regreset state : UInt<5>, clock, reset, UInt<5>(0h0) reg req : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<1>, iw_p2_speculative_child : UInt<1>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<5>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<22>}, way_en : UInt<2>, sdq_id : UInt<5>}, clock node req_idx = bits(req.addr, 9, 6) node req_tag = shr(req.addr, 10) node _req_block_addr_T = shr(req.addr, 6) node req_block_addr = shl(_req_block_addr_T, 6) regreset req_needs_wb : UInt<1>, clock, reset, UInt<1>(0h0) wire new_coh_meta : { state : UInt<2>} connect new_coh_meta.state, UInt<2>(0h0) regreset new_coh : { state : UInt<2>}, clock, reset, new_coh_meta node _r_T = eq(UInt<5>(0h10), UInt<5>(0h10)) node _r_T_1 = mux(_r_T, UInt<2>(0h2), UInt<2>(0h2)) node _r_T_2 = eq(UInt<5>(0h12), UInt<5>(0h10)) node _r_T_3 = mux(_r_T_2, UInt<2>(0h1), _r_T_1) node _r_T_4 = eq(UInt<5>(0h13), UInt<5>(0h10)) node _r_T_5 = mux(_r_T_4, UInt<2>(0h0), _r_T_3) node _r_T_6 = cat(_r_T_5, req.old_meta.coh.state) node _r_T_7 = cat(UInt<2>(0h0), UInt<2>(0h3)) node _r_T_8 = cat(UInt<2>(0h0), UInt<2>(0h2)) node _r_T_9 = cat(UInt<2>(0h0), UInt<2>(0h1)) node _r_T_10 = cat(UInt<2>(0h0), UInt<2>(0h0)) node _r_T_11 = cat(UInt<2>(0h1), UInt<2>(0h3)) node _r_T_12 = cat(UInt<2>(0h1), UInt<2>(0h2)) node _r_T_13 = cat(UInt<2>(0h1), UInt<2>(0h1)) node _r_T_14 = cat(UInt<2>(0h1), UInt<2>(0h0)) node _r_T_15 = cat(UInt<2>(0h2), UInt<2>(0h3)) node _r_T_16 = cat(UInt<2>(0h2), UInt<2>(0h2)) node _r_T_17 = cat(UInt<2>(0h2), UInt<2>(0h1)) node _r_T_18 = cat(UInt<2>(0h2), UInt<2>(0h0)) node _r_T_19 = eq(_r_T_18, _r_T_6) node _r_T_20 = mux(_r_T_19, UInt<1>(0h0), UInt<1>(0h0)) node _r_T_21 = mux(_r_T_19, UInt<3>(0h5), UInt<1>(0h0)) node _r_T_22 = mux(_r_T_19, UInt<2>(0h0), UInt<1>(0h0)) node _r_T_23 = eq(_r_T_17, _r_T_6) node _r_T_24 = mux(_r_T_23, UInt<1>(0h0), _r_T_20) node _r_T_25 = mux(_r_T_23, UInt<3>(0h2), _r_T_21) node _r_T_26 = mux(_r_T_23, UInt<2>(0h0), _r_T_22) node _r_T_27 = eq(_r_T_16, _r_T_6) node _r_T_28 = mux(_r_T_27, UInt<1>(0h0), _r_T_24) node _r_T_29 = mux(_r_T_27, UInt<3>(0h1), _r_T_25) node _r_T_30 = mux(_r_T_27, UInt<2>(0h0), _r_T_26) node _r_T_31 = eq(_r_T_15, _r_T_6) node _r_T_32 = mux(_r_T_31, UInt<1>(0h1), _r_T_28) node _r_T_33 = mux(_r_T_31, UInt<3>(0h1), _r_T_29) node _r_T_34 = mux(_r_T_31, UInt<2>(0h0), _r_T_30) node _r_T_35 = eq(_r_T_14, _r_T_6) node _r_T_36 = mux(_r_T_35, UInt<1>(0h0), _r_T_32) node _r_T_37 = mux(_r_T_35, UInt<3>(0h5), _r_T_33) node _r_T_38 = mux(_r_T_35, UInt<2>(0h0), _r_T_34) node _r_T_39 = eq(_r_T_13, _r_T_6) node _r_T_40 = mux(_r_T_39, UInt<1>(0h0), _r_T_36) node _r_T_41 = mux(_r_T_39, UInt<3>(0h4), _r_T_37) node _r_T_42 = mux(_r_T_39, UInt<2>(0h1), _r_T_38) node _r_T_43 = eq(_r_T_12, _r_T_6) node _r_T_44 = mux(_r_T_43, UInt<1>(0h0), _r_T_40) node _r_T_45 = mux(_r_T_43, UInt<3>(0h0), _r_T_41) node _r_T_46 = mux(_r_T_43, UInt<2>(0h1), _r_T_42) node _r_T_47 = eq(_r_T_11, _r_T_6) node _r_T_48 = mux(_r_T_47, UInt<1>(0h1), _r_T_44) node _r_T_49 = mux(_r_T_47, UInt<3>(0h0), _r_T_45) node _r_T_50 = mux(_r_T_47, UInt<2>(0h1), _r_T_46) node _r_T_51 = eq(_r_T_10, _r_T_6) node _r_T_52 = mux(_r_T_51, UInt<1>(0h0), _r_T_48) node _r_T_53 = mux(_r_T_51, UInt<3>(0h5), _r_T_49) node _r_T_54 = mux(_r_T_51, UInt<2>(0h0), _r_T_50) node _r_T_55 = eq(_r_T_9, _r_T_6) node _r_T_56 = mux(_r_T_55, UInt<1>(0h0), _r_T_52) node _r_T_57 = mux(_r_T_55, UInt<3>(0h4), _r_T_53) node _r_T_58 = mux(_r_T_55, UInt<2>(0h1), _r_T_54) node _r_T_59 = eq(_r_T_8, _r_T_6) node _r_T_60 = mux(_r_T_59, UInt<1>(0h0), _r_T_56) node _r_T_61 = mux(_r_T_59, UInt<3>(0h3), _r_T_57) node _r_T_62 = mux(_r_T_59, UInt<2>(0h2), _r_T_58) node _r_T_63 = eq(_r_T_7, _r_T_6) node r_1 = mux(_r_T_63, UInt<1>(0h1), _r_T_60) node shrink_param = mux(_r_T_63, UInt<3>(0h3), _r_T_61) node r_3 = mux(_r_T_63, UInt<2>(0h2), _r_T_62) wire coh_on_clear : { state : UInt<2>} connect coh_on_clear.state, r_3 node _grow_param_r_c_cat_T = eq(req.uop.mem_cmd, UInt<1>(0h1)) node _grow_param_r_c_cat_T_1 = eq(req.uop.mem_cmd, UInt<5>(0h11)) node _grow_param_r_c_cat_T_2 = or(_grow_param_r_c_cat_T, _grow_param_r_c_cat_T_1) node _grow_param_r_c_cat_T_3 = eq(req.uop.mem_cmd, UInt<3>(0h7)) node _grow_param_r_c_cat_T_4 = or(_grow_param_r_c_cat_T_2, _grow_param_r_c_cat_T_3) node _grow_param_r_c_cat_T_5 = eq(req.uop.mem_cmd, UInt<3>(0h4)) node _grow_param_r_c_cat_T_6 = eq(req.uop.mem_cmd, UInt<4>(0h9)) node _grow_param_r_c_cat_T_7 = eq(req.uop.mem_cmd, UInt<4>(0ha)) node _grow_param_r_c_cat_T_8 = eq(req.uop.mem_cmd, UInt<4>(0hb)) node _grow_param_r_c_cat_T_9 = or(_grow_param_r_c_cat_T_5, _grow_param_r_c_cat_T_6) node _grow_param_r_c_cat_T_10 = or(_grow_param_r_c_cat_T_9, _grow_param_r_c_cat_T_7) node _grow_param_r_c_cat_T_11 = or(_grow_param_r_c_cat_T_10, _grow_param_r_c_cat_T_8) node _grow_param_r_c_cat_T_12 = eq(req.uop.mem_cmd, UInt<4>(0h8)) node _grow_param_r_c_cat_T_13 = eq(req.uop.mem_cmd, UInt<4>(0hc)) node _grow_param_r_c_cat_T_14 = eq(req.uop.mem_cmd, UInt<4>(0hd)) node _grow_param_r_c_cat_T_15 = eq(req.uop.mem_cmd, UInt<4>(0he)) node _grow_param_r_c_cat_T_16 = eq(req.uop.mem_cmd, UInt<4>(0hf)) node _grow_param_r_c_cat_T_17 = or(_grow_param_r_c_cat_T_12, _grow_param_r_c_cat_T_13) node _grow_param_r_c_cat_T_18 = or(_grow_param_r_c_cat_T_17, _grow_param_r_c_cat_T_14) node _grow_param_r_c_cat_T_19 = or(_grow_param_r_c_cat_T_18, _grow_param_r_c_cat_T_15) node _grow_param_r_c_cat_T_20 = or(_grow_param_r_c_cat_T_19, _grow_param_r_c_cat_T_16) node _grow_param_r_c_cat_T_21 = or(_grow_param_r_c_cat_T_11, _grow_param_r_c_cat_T_20) node _grow_param_r_c_cat_T_22 = or(_grow_param_r_c_cat_T_4, _grow_param_r_c_cat_T_21) node _grow_param_r_c_cat_T_23 = eq(req.uop.mem_cmd, UInt<1>(0h1)) node _grow_param_r_c_cat_T_24 = eq(req.uop.mem_cmd, UInt<5>(0h11)) node _grow_param_r_c_cat_T_25 = or(_grow_param_r_c_cat_T_23, _grow_param_r_c_cat_T_24) node _grow_param_r_c_cat_T_26 = eq(req.uop.mem_cmd, UInt<3>(0h7)) node _grow_param_r_c_cat_T_27 = or(_grow_param_r_c_cat_T_25, _grow_param_r_c_cat_T_26) node _grow_param_r_c_cat_T_28 = eq(req.uop.mem_cmd, UInt<3>(0h4)) node _grow_param_r_c_cat_T_29 = eq(req.uop.mem_cmd, UInt<4>(0h9)) node _grow_param_r_c_cat_T_30 = eq(req.uop.mem_cmd, UInt<4>(0ha)) node _grow_param_r_c_cat_T_31 = eq(req.uop.mem_cmd, UInt<4>(0hb)) node _grow_param_r_c_cat_T_32 = or(_grow_param_r_c_cat_T_28, _grow_param_r_c_cat_T_29) node _grow_param_r_c_cat_T_33 = or(_grow_param_r_c_cat_T_32, _grow_param_r_c_cat_T_30) node _grow_param_r_c_cat_T_34 = or(_grow_param_r_c_cat_T_33, _grow_param_r_c_cat_T_31) node _grow_param_r_c_cat_T_35 = eq(req.uop.mem_cmd, UInt<4>(0h8)) node _grow_param_r_c_cat_T_36 = eq(req.uop.mem_cmd, UInt<4>(0hc)) node _grow_param_r_c_cat_T_37 = eq(req.uop.mem_cmd, UInt<4>(0hd)) node _grow_param_r_c_cat_T_38 = eq(req.uop.mem_cmd, UInt<4>(0he)) node _grow_param_r_c_cat_T_39 = eq(req.uop.mem_cmd, UInt<4>(0hf)) node _grow_param_r_c_cat_T_40 = or(_grow_param_r_c_cat_T_35, _grow_param_r_c_cat_T_36) node _grow_param_r_c_cat_T_41 = or(_grow_param_r_c_cat_T_40, _grow_param_r_c_cat_T_37) node _grow_param_r_c_cat_T_42 = or(_grow_param_r_c_cat_T_41, _grow_param_r_c_cat_T_38) node _grow_param_r_c_cat_T_43 = or(_grow_param_r_c_cat_T_42, _grow_param_r_c_cat_T_39) node _grow_param_r_c_cat_T_44 = or(_grow_param_r_c_cat_T_34, _grow_param_r_c_cat_T_43) node _grow_param_r_c_cat_T_45 = or(_grow_param_r_c_cat_T_27, _grow_param_r_c_cat_T_44) node _grow_param_r_c_cat_T_46 = eq(req.uop.mem_cmd, UInt<2>(0h3)) node _grow_param_r_c_cat_T_47 = or(_grow_param_r_c_cat_T_45, _grow_param_r_c_cat_T_46) node _grow_param_r_c_cat_T_48 = eq(req.uop.mem_cmd, UInt<3>(0h6)) node _grow_param_r_c_cat_T_49 = or(_grow_param_r_c_cat_T_47, _grow_param_r_c_cat_T_48) node grow_param_r_c = cat(_grow_param_r_c_cat_T_22, _grow_param_r_c_cat_T_49) node _grow_param_r_T = cat(grow_param_r_c, new_coh.state) node _grow_param_r_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _grow_param_r_T_2 = cat(_grow_param_r_T_1, UInt<2>(0h3)) node _grow_param_r_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _grow_param_r_T_4 = cat(_grow_param_r_T_3, UInt<2>(0h2)) node _grow_param_r_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _grow_param_r_T_6 = cat(_grow_param_r_T_5, UInt<2>(0h1)) node _grow_param_r_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _grow_param_r_T_8 = cat(_grow_param_r_T_7, UInt<2>(0h3)) node _grow_param_r_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _grow_param_r_T_10 = cat(_grow_param_r_T_9, UInt<2>(0h2)) node _grow_param_r_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _grow_param_r_T_12 = cat(_grow_param_r_T_11, UInt<2>(0h3)) node _grow_param_r_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _grow_param_r_T_14 = cat(_grow_param_r_T_13, UInt<2>(0h2)) node _grow_param_r_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _grow_param_r_T_16 = cat(_grow_param_r_T_15, UInt<2>(0h0)) node _grow_param_r_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _grow_param_r_T_18 = cat(_grow_param_r_T_17, UInt<2>(0h1)) node _grow_param_r_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _grow_param_r_T_20 = cat(_grow_param_r_T_19, UInt<2>(0h0)) node _grow_param_r_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _grow_param_r_T_22 = cat(_grow_param_r_T_21, UInt<2>(0h1)) node _grow_param_r_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _grow_param_r_T_24 = cat(_grow_param_r_T_23, UInt<2>(0h0)) node _grow_param_r_T_25 = eq(_grow_param_r_T_24, _grow_param_r_T) node _grow_param_r_T_26 = mux(_grow_param_r_T_25, UInt<1>(0h0), UInt<1>(0h0)) node _grow_param_r_T_27 = mux(_grow_param_r_T_25, UInt<2>(0h1), UInt<1>(0h0)) node _grow_param_r_T_28 = eq(_grow_param_r_T_22, _grow_param_r_T) node _grow_param_r_T_29 = mux(_grow_param_r_T_28, UInt<1>(0h0), _grow_param_r_T_26) node _grow_param_r_T_30 = mux(_grow_param_r_T_28, UInt<2>(0h2), _grow_param_r_T_27) node _grow_param_r_T_31 = eq(_grow_param_r_T_20, _grow_param_r_T) node _grow_param_r_T_32 = mux(_grow_param_r_T_31, UInt<1>(0h0), _grow_param_r_T_29) node _grow_param_r_T_33 = mux(_grow_param_r_T_31, UInt<2>(0h1), _grow_param_r_T_30) node _grow_param_r_T_34 = eq(_grow_param_r_T_18, _grow_param_r_T) node _grow_param_r_T_35 = mux(_grow_param_r_T_34, UInt<1>(0h0), _grow_param_r_T_32) node _grow_param_r_T_36 = mux(_grow_param_r_T_34, UInt<2>(0h2), _grow_param_r_T_33) node _grow_param_r_T_37 = eq(_grow_param_r_T_16, _grow_param_r_T) node _grow_param_r_T_38 = mux(_grow_param_r_T_37, UInt<1>(0h0), _grow_param_r_T_35) node _grow_param_r_T_39 = mux(_grow_param_r_T_37, UInt<2>(0h0), _grow_param_r_T_36) node _grow_param_r_T_40 = eq(_grow_param_r_T_14, _grow_param_r_T) node _grow_param_r_T_41 = mux(_grow_param_r_T_40, UInt<1>(0h1), _grow_param_r_T_38) node _grow_param_r_T_42 = mux(_grow_param_r_T_40, UInt<2>(0h3), _grow_param_r_T_39) node _grow_param_r_T_43 = eq(_grow_param_r_T_12, _grow_param_r_T) node _grow_param_r_T_44 = mux(_grow_param_r_T_43, UInt<1>(0h1), _grow_param_r_T_41) node _grow_param_r_T_45 = mux(_grow_param_r_T_43, UInt<2>(0h3), _grow_param_r_T_42) node _grow_param_r_T_46 = eq(_grow_param_r_T_10, _grow_param_r_T) node _grow_param_r_T_47 = mux(_grow_param_r_T_46, UInt<1>(0h1), _grow_param_r_T_44) node _grow_param_r_T_48 = mux(_grow_param_r_T_46, UInt<2>(0h2), _grow_param_r_T_45) node _grow_param_r_T_49 = eq(_grow_param_r_T_8, _grow_param_r_T) node _grow_param_r_T_50 = mux(_grow_param_r_T_49, UInt<1>(0h1), _grow_param_r_T_47) node _grow_param_r_T_51 = mux(_grow_param_r_T_49, UInt<2>(0h3), _grow_param_r_T_48) node _grow_param_r_T_52 = eq(_grow_param_r_T_6, _grow_param_r_T) node _grow_param_r_T_53 = mux(_grow_param_r_T_52, UInt<1>(0h1), _grow_param_r_T_50) node _grow_param_r_T_54 = mux(_grow_param_r_T_52, UInt<2>(0h1), _grow_param_r_T_51) node _grow_param_r_T_55 = eq(_grow_param_r_T_4, _grow_param_r_T) node _grow_param_r_T_56 = mux(_grow_param_r_T_55, UInt<1>(0h1), _grow_param_r_T_53) node _grow_param_r_T_57 = mux(_grow_param_r_T_55, UInt<2>(0h2), _grow_param_r_T_54) node _grow_param_r_T_58 = eq(_grow_param_r_T_2, _grow_param_r_T) node grow_param_r_1 = mux(_grow_param_r_T_58, UInt<1>(0h1), _grow_param_r_T_56) node grow_param = mux(_grow_param_r_T_58, UInt<2>(0h3), _grow_param_r_T_57) wire grow_param_meta : { state : UInt<2>} connect grow_param_meta.state, grow_param node _coh_on_grant_c_cat_T = eq(req.uop.mem_cmd, UInt<1>(0h1)) node _coh_on_grant_c_cat_T_1 = eq(req.uop.mem_cmd, UInt<5>(0h11)) node _coh_on_grant_c_cat_T_2 = or(_coh_on_grant_c_cat_T, _coh_on_grant_c_cat_T_1) node _coh_on_grant_c_cat_T_3 = eq(req.uop.mem_cmd, UInt<3>(0h7)) node _coh_on_grant_c_cat_T_4 = or(_coh_on_grant_c_cat_T_2, _coh_on_grant_c_cat_T_3) node _coh_on_grant_c_cat_T_5 = eq(req.uop.mem_cmd, UInt<3>(0h4)) node _coh_on_grant_c_cat_T_6 = eq(req.uop.mem_cmd, UInt<4>(0h9)) node _coh_on_grant_c_cat_T_7 = eq(req.uop.mem_cmd, UInt<4>(0ha)) node _coh_on_grant_c_cat_T_8 = eq(req.uop.mem_cmd, UInt<4>(0hb)) node _coh_on_grant_c_cat_T_9 = or(_coh_on_grant_c_cat_T_5, _coh_on_grant_c_cat_T_6) node _coh_on_grant_c_cat_T_10 = or(_coh_on_grant_c_cat_T_9, _coh_on_grant_c_cat_T_7) node _coh_on_grant_c_cat_T_11 = or(_coh_on_grant_c_cat_T_10, _coh_on_grant_c_cat_T_8) node _coh_on_grant_c_cat_T_12 = eq(req.uop.mem_cmd, UInt<4>(0h8)) node _coh_on_grant_c_cat_T_13 = eq(req.uop.mem_cmd, UInt<4>(0hc)) node _coh_on_grant_c_cat_T_14 = eq(req.uop.mem_cmd, UInt<4>(0hd)) node _coh_on_grant_c_cat_T_15 = eq(req.uop.mem_cmd, UInt<4>(0he)) node _coh_on_grant_c_cat_T_16 = eq(req.uop.mem_cmd, UInt<4>(0hf)) node _coh_on_grant_c_cat_T_17 = or(_coh_on_grant_c_cat_T_12, _coh_on_grant_c_cat_T_13) node _coh_on_grant_c_cat_T_18 = or(_coh_on_grant_c_cat_T_17, _coh_on_grant_c_cat_T_14) node _coh_on_grant_c_cat_T_19 = or(_coh_on_grant_c_cat_T_18, _coh_on_grant_c_cat_T_15) node _coh_on_grant_c_cat_T_20 = or(_coh_on_grant_c_cat_T_19, _coh_on_grant_c_cat_T_16) node _coh_on_grant_c_cat_T_21 = or(_coh_on_grant_c_cat_T_11, _coh_on_grant_c_cat_T_20) node _coh_on_grant_c_cat_T_22 = or(_coh_on_grant_c_cat_T_4, _coh_on_grant_c_cat_T_21) node _coh_on_grant_c_cat_T_23 = eq(req.uop.mem_cmd, UInt<1>(0h1)) node _coh_on_grant_c_cat_T_24 = eq(req.uop.mem_cmd, UInt<5>(0h11)) node _coh_on_grant_c_cat_T_25 = or(_coh_on_grant_c_cat_T_23, _coh_on_grant_c_cat_T_24) node _coh_on_grant_c_cat_T_26 = eq(req.uop.mem_cmd, UInt<3>(0h7)) node _coh_on_grant_c_cat_T_27 = or(_coh_on_grant_c_cat_T_25, _coh_on_grant_c_cat_T_26) node _coh_on_grant_c_cat_T_28 = eq(req.uop.mem_cmd, UInt<3>(0h4)) node _coh_on_grant_c_cat_T_29 = eq(req.uop.mem_cmd, UInt<4>(0h9)) node _coh_on_grant_c_cat_T_30 = eq(req.uop.mem_cmd, UInt<4>(0ha)) node _coh_on_grant_c_cat_T_31 = eq(req.uop.mem_cmd, UInt<4>(0hb)) node _coh_on_grant_c_cat_T_32 = or(_coh_on_grant_c_cat_T_28, _coh_on_grant_c_cat_T_29) node _coh_on_grant_c_cat_T_33 = or(_coh_on_grant_c_cat_T_32, _coh_on_grant_c_cat_T_30) node _coh_on_grant_c_cat_T_34 = or(_coh_on_grant_c_cat_T_33, _coh_on_grant_c_cat_T_31) node _coh_on_grant_c_cat_T_35 = eq(req.uop.mem_cmd, UInt<4>(0h8)) node _coh_on_grant_c_cat_T_36 = eq(req.uop.mem_cmd, UInt<4>(0hc)) node _coh_on_grant_c_cat_T_37 = eq(req.uop.mem_cmd, UInt<4>(0hd)) node _coh_on_grant_c_cat_T_38 = eq(req.uop.mem_cmd, UInt<4>(0he)) node _coh_on_grant_c_cat_T_39 = eq(req.uop.mem_cmd, UInt<4>(0hf)) node _coh_on_grant_c_cat_T_40 = or(_coh_on_grant_c_cat_T_35, _coh_on_grant_c_cat_T_36) node _coh_on_grant_c_cat_T_41 = or(_coh_on_grant_c_cat_T_40, _coh_on_grant_c_cat_T_37) node _coh_on_grant_c_cat_T_42 = or(_coh_on_grant_c_cat_T_41, _coh_on_grant_c_cat_T_38) node _coh_on_grant_c_cat_T_43 = or(_coh_on_grant_c_cat_T_42, _coh_on_grant_c_cat_T_39) node _coh_on_grant_c_cat_T_44 = or(_coh_on_grant_c_cat_T_34, _coh_on_grant_c_cat_T_43) node _coh_on_grant_c_cat_T_45 = or(_coh_on_grant_c_cat_T_27, _coh_on_grant_c_cat_T_44) node _coh_on_grant_c_cat_T_46 = eq(req.uop.mem_cmd, UInt<2>(0h3)) node _coh_on_grant_c_cat_T_47 = or(_coh_on_grant_c_cat_T_45, _coh_on_grant_c_cat_T_46) node _coh_on_grant_c_cat_T_48 = eq(req.uop.mem_cmd, UInt<3>(0h6)) node _coh_on_grant_c_cat_T_49 = or(_coh_on_grant_c_cat_T_47, _coh_on_grant_c_cat_T_48) node coh_on_grant_c = cat(_coh_on_grant_c_cat_T_22, _coh_on_grant_c_cat_T_49) node _coh_on_grant_T = cat(coh_on_grant_c, io.mem_grant.bits.param) node _coh_on_grant_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _coh_on_grant_T_2 = cat(_coh_on_grant_T_1, UInt<2>(0h1)) node _coh_on_grant_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _coh_on_grant_T_4 = cat(_coh_on_grant_T_3, UInt<2>(0h0)) node _coh_on_grant_T_5 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _coh_on_grant_T_6 = cat(_coh_on_grant_T_5, UInt<2>(0h0)) node _coh_on_grant_T_7 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _coh_on_grant_T_8 = cat(_coh_on_grant_T_7, UInt<2>(0h0)) node _coh_on_grant_T_9 = eq(_coh_on_grant_T_2, _coh_on_grant_T) node _coh_on_grant_T_10 = mux(_coh_on_grant_T_9, UInt<2>(0h1), UInt<2>(0h0)) node _coh_on_grant_T_11 = eq(_coh_on_grant_T_4, _coh_on_grant_T) node _coh_on_grant_T_12 = mux(_coh_on_grant_T_11, UInt<2>(0h2), _coh_on_grant_T_10) node _coh_on_grant_T_13 = eq(_coh_on_grant_T_6, _coh_on_grant_T) node _coh_on_grant_T_14 = mux(_coh_on_grant_T_13, UInt<2>(0h2), _coh_on_grant_T_12) node _coh_on_grant_T_15 = eq(_coh_on_grant_T_8, _coh_on_grant_T) node _coh_on_grant_T_16 = mux(_coh_on_grant_T_15, UInt<2>(0h3), _coh_on_grant_T_14) wire coh_on_grant : { state : UInt<2>} connect coh_on_grant.state, _coh_on_grant_T_16 node _r1_c_cat_T = eq(req.uop.mem_cmd, UInt<1>(0h1)) node _r1_c_cat_T_1 = eq(req.uop.mem_cmd, UInt<5>(0h11)) node _r1_c_cat_T_2 = or(_r1_c_cat_T, _r1_c_cat_T_1) node _r1_c_cat_T_3 = eq(req.uop.mem_cmd, UInt<3>(0h7)) node _r1_c_cat_T_4 = or(_r1_c_cat_T_2, _r1_c_cat_T_3) node _r1_c_cat_T_5 = eq(req.uop.mem_cmd, UInt<3>(0h4)) node _r1_c_cat_T_6 = eq(req.uop.mem_cmd, UInt<4>(0h9)) node _r1_c_cat_T_7 = eq(req.uop.mem_cmd, UInt<4>(0ha)) node _r1_c_cat_T_8 = eq(req.uop.mem_cmd, UInt<4>(0hb)) node _r1_c_cat_T_9 = or(_r1_c_cat_T_5, _r1_c_cat_T_6) node _r1_c_cat_T_10 = or(_r1_c_cat_T_9, _r1_c_cat_T_7) node _r1_c_cat_T_11 = or(_r1_c_cat_T_10, _r1_c_cat_T_8) node _r1_c_cat_T_12 = eq(req.uop.mem_cmd, UInt<4>(0h8)) node _r1_c_cat_T_13 = eq(req.uop.mem_cmd, UInt<4>(0hc)) node _r1_c_cat_T_14 = eq(req.uop.mem_cmd, UInt<4>(0hd)) node _r1_c_cat_T_15 = eq(req.uop.mem_cmd, UInt<4>(0he)) node _r1_c_cat_T_16 = eq(req.uop.mem_cmd, UInt<4>(0hf)) node _r1_c_cat_T_17 = or(_r1_c_cat_T_12, _r1_c_cat_T_13) node _r1_c_cat_T_18 = or(_r1_c_cat_T_17, _r1_c_cat_T_14) node _r1_c_cat_T_19 = or(_r1_c_cat_T_18, _r1_c_cat_T_15) node _r1_c_cat_T_20 = or(_r1_c_cat_T_19, _r1_c_cat_T_16) node _r1_c_cat_T_21 = or(_r1_c_cat_T_11, _r1_c_cat_T_20) node _r1_c_cat_T_22 = or(_r1_c_cat_T_4, _r1_c_cat_T_21) node _r1_c_cat_T_23 = eq(req.uop.mem_cmd, UInt<1>(0h1)) node _r1_c_cat_T_24 = eq(req.uop.mem_cmd, UInt<5>(0h11)) node _r1_c_cat_T_25 = or(_r1_c_cat_T_23, _r1_c_cat_T_24) node _r1_c_cat_T_26 = eq(req.uop.mem_cmd, UInt<3>(0h7)) node _r1_c_cat_T_27 = or(_r1_c_cat_T_25, _r1_c_cat_T_26) node _r1_c_cat_T_28 = eq(req.uop.mem_cmd, UInt<3>(0h4)) node _r1_c_cat_T_29 = eq(req.uop.mem_cmd, UInt<4>(0h9)) node _r1_c_cat_T_30 = eq(req.uop.mem_cmd, UInt<4>(0ha)) node _r1_c_cat_T_31 = eq(req.uop.mem_cmd, UInt<4>(0hb)) node _r1_c_cat_T_32 = or(_r1_c_cat_T_28, _r1_c_cat_T_29) node _r1_c_cat_T_33 = or(_r1_c_cat_T_32, _r1_c_cat_T_30) node _r1_c_cat_T_34 = or(_r1_c_cat_T_33, _r1_c_cat_T_31) node _r1_c_cat_T_35 = eq(req.uop.mem_cmd, UInt<4>(0h8)) node _r1_c_cat_T_36 = eq(req.uop.mem_cmd, UInt<4>(0hc)) node _r1_c_cat_T_37 = eq(req.uop.mem_cmd, UInt<4>(0hd)) node _r1_c_cat_T_38 = eq(req.uop.mem_cmd, UInt<4>(0he)) node _r1_c_cat_T_39 = eq(req.uop.mem_cmd, UInt<4>(0hf)) node _r1_c_cat_T_40 = or(_r1_c_cat_T_35, _r1_c_cat_T_36) node _r1_c_cat_T_41 = or(_r1_c_cat_T_40, _r1_c_cat_T_37) node _r1_c_cat_T_42 = or(_r1_c_cat_T_41, _r1_c_cat_T_38) node _r1_c_cat_T_43 = or(_r1_c_cat_T_42, _r1_c_cat_T_39) node _r1_c_cat_T_44 = or(_r1_c_cat_T_34, _r1_c_cat_T_43) node _r1_c_cat_T_45 = or(_r1_c_cat_T_27, _r1_c_cat_T_44) node _r1_c_cat_T_46 = eq(req.uop.mem_cmd, UInt<2>(0h3)) node _r1_c_cat_T_47 = or(_r1_c_cat_T_45, _r1_c_cat_T_46) node _r1_c_cat_T_48 = eq(req.uop.mem_cmd, UInt<3>(0h6)) node _r1_c_cat_T_49 = or(_r1_c_cat_T_47, _r1_c_cat_T_48) node r1_c = cat(_r1_c_cat_T_22, _r1_c_cat_T_49) node _r1_T = cat(r1_c, new_coh.state) node _r1_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r1_T_2 = cat(_r1_T_1, UInt<2>(0h3)) node _r1_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r1_T_4 = cat(_r1_T_3, UInt<2>(0h2)) node _r1_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r1_T_6 = cat(_r1_T_5, UInt<2>(0h1)) node _r1_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r1_T_8 = cat(_r1_T_7, UInt<2>(0h3)) node _r1_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r1_T_10 = cat(_r1_T_9, UInt<2>(0h2)) node _r1_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r1_T_12 = cat(_r1_T_11, UInt<2>(0h3)) node _r1_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r1_T_14 = cat(_r1_T_13, UInt<2>(0h2)) node _r1_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r1_T_16 = cat(_r1_T_15, UInt<2>(0h0)) node _r1_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r1_T_18 = cat(_r1_T_17, UInt<2>(0h1)) node _r1_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r1_T_20 = cat(_r1_T_19, UInt<2>(0h0)) node _r1_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r1_T_22 = cat(_r1_T_21, UInt<2>(0h1)) node _r1_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r1_T_24 = cat(_r1_T_23, UInt<2>(0h0)) node _r1_T_25 = eq(_r1_T_24, _r1_T) node _r1_T_26 = mux(_r1_T_25, UInt<1>(0h0), UInt<1>(0h0)) node _r1_T_27 = mux(_r1_T_25, UInt<2>(0h1), UInt<1>(0h0)) node _r1_T_28 = eq(_r1_T_22, _r1_T) node _r1_T_29 = mux(_r1_T_28, UInt<1>(0h0), _r1_T_26) node _r1_T_30 = mux(_r1_T_28, UInt<2>(0h2), _r1_T_27) node _r1_T_31 = eq(_r1_T_20, _r1_T) node _r1_T_32 = mux(_r1_T_31, UInt<1>(0h0), _r1_T_29) node _r1_T_33 = mux(_r1_T_31, UInt<2>(0h1), _r1_T_30) node _r1_T_34 = eq(_r1_T_18, _r1_T) node _r1_T_35 = mux(_r1_T_34, UInt<1>(0h0), _r1_T_32) node _r1_T_36 = mux(_r1_T_34, UInt<2>(0h2), _r1_T_33) node _r1_T_37 = eq(_r1_T_16, _r1_T) node _r1_T_38 = mux(_r1_T_37, UInt<1>(0h0), _r1_T_35) node _r1_T_39 = mux(_r1_T_37, UInt<2>(0h0), _r1_T_36) node _r1_T_40 = eq(_r1_T_14, _r1_T) node _r1_T_41 = mux(_r1_T_40, UInt<1>(0h1), _r1_T_38) node _r1_T_42 = mux(_r1_T_40, UInt<2>(0h3), _r1_T_39) node _r1_T_43 = eq(_r1_T_12, _r1_T) node _r1_T_44 = mux(_r1_T_43, UInt<1>(0h1), _r1_T_41) node _r1_T_45 = mux(_r1_T_43, UInt<2>(0h3), _r1_T_42) node _r1_T_46 = eq(_r1_T_10, _r1_T) node _r1_T_47 = mux(_r1_T_46, UInt<1>(0h1), _r1_T_44) node _r1_T_48 = mux(_r1_T_46, UInt<2>(0h2), _r1_T_45) node _r1_T_49 = eq(_r1_T_8, _r1_T) node _r1_T_50 = mux(_r1_T_49, UInt<1>(0h1), _r1_T_47) node _r1_T_51 = mux(_r1_T_49, UInt<2>(0h3), _r1_T_48) node _r1_T_52 = eq(_r1_T_6, _r1_T) node _r1_T_53 = mux(_r1_T_52, UInt<1>(0h1), _r1_T_50) node _r1_T_54 = mux(_r1_T_52, UInt<2>(0h1), _r1_T_51) node _r1_T_55 = eq(_r1_T_4, _r1_T) node _r1_T_56 = mux(_r1_T_55, UInt<1>(0h1), _r1_T_53) node _r1_T_57 = mux(_r1_T_55, UInt<2>(0h2), _r1_T_54) node _r1_T_58 = eq(_r1_T_2, _r1_T) node r1_1 = mux(_r1_T_58, UInt<1>(0h1), _r1_T_56) node r1_2 = mux(_r1_T_58, UInt<2>(0h3), _r1_T_57) node _r2_c_cat_T = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _r2_c_cat_T_1 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _r2_c_cat_T_2 = or(_r2_c_cat_T, _r2_c_cat_T_1) node _r2_c_cat_T_3 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _r2_c_cat_T_4 = or(_r2_c_cat_T_2, _r2_c_cat_T_3) node _r2_c_cat_T_5 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _r2_c_cat_T_6 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _r2_c_cat_T_7 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _r2_c_cat_T_8 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _r2_c_cat_T_9 = or(_r2_c_cat_T_5, _r2_c_cat_T_6) node _r2_c_cat_T_10 = or(_r2_c_cat_T_9, _r2_c_cat_T_7) node _r2_c_cat_T_11 = or(_r2_c_cat_T_10, _r2_c_cat_T_8) node _r2_c_cat_T_12 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _r2_c_cat_T_13 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _r2_c_cat_T_14 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _r2_c_cat_T_15 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _r2_c_cat_T_16 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _r2_c_cat_T_17 = or(_r2_c_cat_T_12, _r2_c_cat_T_13) node _r2_c_cat_T_18 = or(_r2_c_cat_T_17, _r2_c_cat_T_14) node _r2_c_cat_T_19 = or(_r2_c_cat_T_18, _r2_c_cat_T_15) node _r2_c_cat_T_20 = or(_r2_c_cat_T_19, _r2_c_cat_T_16) node _r2_c_cat_T_21 = or(_r2_c_cat_T_11, _r2_c_cat_T_20) node _r2_c_cat_T_22 = or(_r2_c_cat_T_4, _r2_c_cat_T_21) node _r2_c_cat_T_23 = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _r2_c_cat_T_24 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _r2_c_cat_T_25 = or(_r2_c_cat_T_23, _r2_c_cat_T_24) node _r2_c_cat_T_26 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _r2_c_cat_T_27 = or(_r2_c_cat_T_25, _r2_c_cat_T_26) node _r2_c_cat_T_28 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _r2_c_cat_T_29 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _r2_c_cat_T_30 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _r2_c_cat_T_31 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _r2_c_cat_T_32 = or(_r2_c_cat_T_28, _r2_c_cat_T_29) node _r2_c_cat_T_33 = or(_r2_c_cat_T_32, _r2_c_cat_T_30) node _r2_c_cat_T_34 = or(_r2_c_cat_T_33, _r2_c_cat_T_31) node _r2_c_cat_T_35 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _r2_c_cat_T_36 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _r2_c_cat_T_37 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _r2_c_cat_T_38 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _r2_c_cat_T_39 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _r2_c_cat_T_40 = or(_r2_c_cat_T_35, _r2_c_cat_T_36) node _r2_c_cat_T_41 = or(_r2_c_cat_T_40, _r2_c_cat_T_37) node _r2_c_cat_T_42 = or(_r2_c_cat_T_41, _r2_c_cat_T_38) node _r2_c_cat_T_43 = or(_r2_c_cat_T_42, _r2_c_cat_T_39) node _r2_c_cat_T_44 = or(_r2_c_cat_T_34, _r2_c_cat_T_43) node _r2_c_cat_T_45 = or(_r2_c_cat_T_27, _r2_c_cat_T_44) node _r2_c_cat_T_46 = eq(io.req.uop.mem_cmd, UInt<2>(0h3)) node _r2_c_cat_T_47 = or(_r2_c_cat_T_45, _r2_c_cat_T_46) node _r2_c_cat_T_48 = eq(io.req.uop.mem_cmd, UInt<3>(0h6)) node _r2_c_cat_T_49 = or(_r2_c_cat_T_47, _r2_c_cat_T_48) node r2_c = cat(_r2_c_cat_T_22, _r2_c_cat_T_49) node _r2_T = cat(r2_c, new_coh.state) node _r2_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r2_T_2 = cat(_r2_T_1, UInt<2>(0h3)) node _r2_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r2_T_4 = cat(_r2_T_3, UInt<2>(0h2)) node _r2_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r2_T_6 = cat(_r2_T_5, UInt<2>(0h1)) node _r2_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r2_T_8 = cat(_r2_T_7, UInt<2>(0h3)) node _r2_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r2_T_10 = cat(_r2_T_9, UInt<2>(0h2)) node _r2_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r2_T_12 = cat(_r2_T_11, UInt<2>(0h3)) node _r2_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r2_T_14 = cat(_r2_T_13, UInt<2>(0h2)) node _r2_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r2_T_16 = cat(_r2_T_15, UInt<2>(0h0)) node _r2_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r2_T_18 = cat(_r2_T_17, UInt<2>(0h1)) node _r2_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r2_T_20 = cat(_r2_T_19, UInt<2>(0h0)) node _r2_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r2_T_22 = cat(_r2_T_21, UInt<2>(0h1)) node _r2_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r2_T_24 = cat(_r2_T_23, UInt<2>(0h0)) node _r2_T_25 = eq(_r2_T_24, _r2_T) node _r2_T_26 = mux(_r2_T_25, UInt<1>(0h0), UInt<1>(0h0)) node _r2_T_27 = mux(_r2_T_25, UInt<2>(0h1), UInt<1>(0h0)) node _r2_T_28 = eq(_r2_T_22, _r2_T) node _r2_T_29 = mux(_r2_T_28, UInt<1>(0h0), _r2_T_26) node _r2_T_30 = mux(_r2_T_28, UInt<2>(0h2), _r2_T_27) node _r2_T_31 = eq(_r2_T_20, _r2_T) node _r2_T_32 = mux(_r2_T_31, UInt<1>(0h0), _r2_T_29) node _r2_T_33 = mux(_r2_T_31, UInt<2>(0h1), _r2_T_30) node _r2_T_34 = eq(_r2_T_18, _r2_T) node _r2_T_35 = mux(_r2_T_34, UInt<1>(0h0), _r2_T_32) node _r2_T_36 = mux(_r2_T_34, UInt<2>(0h2), _r2_T_33) node _r2_T_37 = eq(_r2_T_16, _r2_T) node _r2_T_38 = mux(_r2_T_37, UInt<1>(0h0), _r2_T_35) node _r2_T_39 = mux(_r2_T_37, UInt<2>(0h0), _r2_T_36) node _r2_T_40 = eq(_r2_T_14, _r2_T) node _r2_T_41 = mux(_r2_T_40, UInt<1>(0h1), _r2_T_38) node _r2_T_42 = mux(_r2_T_40, UInt<2>(0h3), _r2_T_39) node _r2_T_43 = eq(_r2_T_12, _r2_T) node _r2_T_44 = mux(_r2_T_43, UInt<1>(0h1), _r2_T_41) node _r2_T_45 = mux(_r2_T_43, UInt<2>(0h3), _r2_T_42) node _r2_T_46 = eq(_r2_T_10, _r2_T) node _r2_T_47 = mux(_r2_T_46, UInt<1>(0h1), _r2_T_44) node _r2_T_48 = mux(_r2_T_46, UInt<2>(0h2), _r2_T_45) node _r2_T_49 = eq(_r2_T_8, _r2_T) node _r2_T_50 = mux(_r2_T_49, UInt<1>(0h1), _r2_T_47) node _r2_T_51 = mux(_r2_T_49, UInt<2>(0h3), _r2_T_48) node _r2_T_52 = eq(_r2_T_6, _r2_T) node _r2_T_53 = mux(_r2_T_52, UInt<1>(0h1), _r2_T_50) node _r2_T_54 = mux(_r2_T_52, UInt<2>(0h1), _r2_T_51) node _r2_T_55 = eq(_r2_T_4, _r2_T) node _r2_T_56 = mux(_r2_T_55, UInt<1>(0h1), _r2_T_53) node _r2_T_57 = mux(_r2_T_55, UInt<2>(0h2), _r2_T_54) node _r2_T_58 = eq(_r2_T_2, _r2_T) node r2_1 = mux(_r2_T_58, UInt<1>(0h1), _r2_T_56) node r2_2 = mux(_r2_T_58, UInt<2>(0h3), _r2_T_57) node _needs_second_acq_T = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _needs_second_acq_T_1 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _needs_second_acq_T_2 = or(_needs_second_acq_T, _needs_second_acq_T_1) node _needs_second_acq_T_3 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _needs_second_acq_T_4 = or(_needs_second_acq_T_2, _needs_second_acq_T_3) node _needs_second_acq_T_5 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _needs_second_acq_T_6 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _needs_second_acq_T_7 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _needs_second_acq_T_8 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _needs_second_acq_T_9 = or(_needs_second_acq_T_5, _needs_second_acq_T_6) node _needs_second_acq_T_10 = or(_needs_second_acq_T_9, _needs_second_acq_T_7) node _needs_second_acq_T_11 = or(_needs_second_acq_T_10, _needs_second_acq_T_8) node _needs_second_acq_T_12 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _needs_second_acq_T_13 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _needs_second_acq_T_14 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _needs_second_acq_T_15 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _needs_second_acq_T_16 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _needs_second_acq_T_17 = or(_needs_second_acq_T_12, _needs_second_acq_T_13) node _needs_second_acq_T_18 = or(_needs_second_acq_T_17, _needs_second_acq_T_14) node _needs_second_acq_T_19 = or(_needs_second_acq_T_18, _needs_second_acq_T_15) node _needs_second_acq_T_20 = or(_needs_second_acq_T_19, _needs_second_acq_T_16) node _needs_second_acq_T_21 = or(_needs_second_acq_T_11, _needs_second_acq_T_20) node _needs_second_acq_T_22 = or(_needs_second_acq_T_4, _needs_second_acq_T_21) node _needs_second_acq_T_23 = eq(io.req.uop.mem_cmd, UInt<2>(0h3)) node _needs_second_acq_T_24 = or(_needs_second_acq_T_22, _needs_second_acq_T_23) node _needs_second_acq_T_25 = eq(io.req.uop.mem_cmd, UInt<3>(0h6)) node _needs_second_acq_T_26 = or(_needs_second_acq_T_24, _needs_second_acq_T_25) node _needs_second_acq_T_27 = eq(req.uop.mem_cmd, UInt<1>(0h1)) node _needs_second_acq_T_28 = eq(req.uop.mem_cmd, UInt<5>(0h11)) node _needs_second_acq_T_29 = or(_needs_second_acq_T_27, _needs_second_acq_T_28) node _needs_second_acq_T_30 = eq(req.uop.mem_cmd, UInt<3>(0h7)) node _needs_second_acq_T_31 = or(_needs_second_acq_T_29, _needs_second_acq_T_30) node _needs_second_acq_T_32 = eq(req.uop.mem_cmd, UInt<3>(0h4)) node _needs_second_acq_T_33 = eq(req.uop.mem_cmd, UInt<4>(0h9)) node _needs_second_acq_T_34 = eq(req.uop.mem_cmd, UInt<4>(0ha)) node _needs_second_acq_T_35 = eq(req.uop.mem_cmd, UInt<4>(0hb)) node _needs_second_acq_T_36 = or(_needs_second_acq_T_32, _needs_second_acq_T_33) node _needs_second_acq_T_37 = or(_needs_second_acq_T_36, _needs_second_acq_T_34) node _needs_second_acq_T_38 = or(_needs_second_acq_T_37, _needs_second_acq_T_35) node _needs_second_acq_T_39 = eq(req.uop.mem_cmd, UInt<4>(0h8)) node _needs_second_acq_T_40 = eq(req.uop.mem_cmd, UInt<4>(0hc)) node _needs_second_acq_T_41 = eq(req.uop.mem_cmd, UInt<4>(0hd)) node _needs_second_acq_T_42 = eq(req.uop.mem_cmd, UInt<4>(0he)) node _needs_second_acq_T_43 = eq(req.uop.mem_cmd, UInt<4>(0hf)) node _needs_second_acq_T_44 = or(_needs_second_acq_T_39, _needs_second_acq_T_40) node _needs_second_acq_T_45 = or(_needs_second_acq_T_44, _needs_second_acq_T_41) node _needs_second_acq_T_46 = or(_needs_second_acq_T_45, _needs_second_acq_T_42) node _needs_second_acq_T_47 = or(_needs_second_acq_T_46, _needs_second_acq_T_43) node _needs_second_acq_T_48 = or(_needs_second_acq_T_38, _needs_second_acq_T_47) node _needs_second_acq_T_49 = or(_needs_second_acq_T_31, _needs_second_acq_T_48) node _needs_second_acq_T_50 = eq(req.uop.mem_cmd, UInt<2>(0h3)) node _needs_second_acq_T_51 = or(_needs_second_acq_T_49, _needs_second_acq_T_50) node _needs_second_acq_T_52 = eq(req.uop.mem_cmd, UInt<3>(0h6)) node _needs_second_acq_T_53 = or(_needs_second_acq_T_51, _needs_second_acq_T_52) node _needs_second_acq_T_54 = eq(_needs_second_acq_T_53, UInt<1>(0h0)) node cmd_requires_second_acquire = and(_needs_second_acq_T_26, _needs_second_acq_T_54) node is_hit_again = and(r1_1, r2_1) node _dirties_cat_T = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _dirties_cat_T_1 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _dirties_cat_T_2 = or(_dirties_cat_T, _dirties_cat_T_1) node _dirties_cat_T_3 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _dirties_cat_T_4 = or(_dirties_cat_T_2, _dirties_cat_T_3) node _dirties_cat_T_5 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _dirties_cat_T_6 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _dirties_cat_T_7 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _dirties_cat_T_8 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _dirties_cat_T_9 = or(_dirties_cat_T_5, _dirties_cat_T_6) node _dirties_cat_T_10 = or(_dirties_cat_T_9, _dirties_cat_T_7) node _dirties_cat_T_11 = or(_dirties_cat_T_10, _dirties_cat_T_8) node _dirties_cat_T_12 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _dirties_cat_T_13 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _dirties_cat_T_14 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _dirties_cat_T_15 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _dirties_cat_T_16 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _dirties_cat_T_17 = or(_dirties_cat_T_12, _dirties_cat_T_13) node _dirties_cat_T_18 = or(_dirties_cat_T_17, _dirties_cat_T_14) node _dirties_cat_T_19 = or(_dirties_cat_T_18, _dirties_cat_T_15) node _dirties_cat_T_20 = or(_dirties_cat_T_19, _dirties_cat_T_16) node _dirties_cat_T_21 = or(_dirties_cat_T_11, _dirties_cat_T_20) node _dirties_cat_T_22 = or(_dirties_cat_T_4, _dirties_cat_T_21) node _dirties_cat_T_23 = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _dirties_cat_T_24 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _dirties_cat_T_25 = or(_dirties_cat_T_23, _dirties_cat_T_24) node _dirties_cat_T_26 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _dirties_cat_T_27 = or(_dirties_cat_T_25, _dirties_cat_T_26) node _dirties_cat_T_28 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _dirties_cat_T_29 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _dirties_cat_T_30 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _dirties_cat_T_31 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _dirties_cat_T_32 = or(_dirties_cat_T_28, _dirties_cat_T_29) node _dirties_cat_T_33 = or(_dirties_cat_T_32, _dirties_cat_T_30) node _dirties_cat_T_34 = or(_dirties_cat_T_33, _dirties_cat_T_31) node _dirties_cat_T_35 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _dirties_cat_T_36 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _dirties_cat_T_37 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _dirties_cat_T_38 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _dirties_cat_T_39 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _dirties_cat_T_40 = or(_dirties_cat_T_35, _dirties_cat_T_36) node _dirties_cat_T_41 = or(_dirties_cat_T_40, _dirties_cat_T_37) node _dirties_cat_T_42 = or(_dirties_cat_T_41, _dirties_cat_T_38) node _dirties_cat_T_43 = or(_dirties_cat_T_42, _dirties_cat_T_39) node _dirties_cat_T_44 = or(_dirties_cat_T_34, _dirties_cat_T_43) node _dirties_cat_T_45 = or(_dirties_cat_T_27, _dirties_cat_T_44) node _dirties_cat_T_46 = eq(io.req.uop.mem_cmd, UInt<2>(0h3)) node _dirties_cat_T_47 = or(_dirties_cat_T_45, _dirties_cat_T_46) node _dirties_cat_T_48 = eq(io.req.uop.mem_cmd, UInt<3>(0h6)) node _dirties_cat_T_49 = or(_dirties_cat_T_47, _dirties_cat_T_48) node dirties_cat = cat(_dirties_cat_T_22, _dirties_cat_T_49) node _dirties_T = cat(UInt<1>(0h1), UInt<1>(0h1)) node dirties = eq(dirties_cat, _dirties_T) node biggest_grow_param = mux(dirties, r2_2, r1_2) wire dirtier_coh : { state : UInt<2>} connect dirtier_coh.state, biggest_grow_param node dirtier_cmd = mux(dirties, io.req.uop.mem_cmd, req.uop.mem_cmd) node _T = and(io.mem_grant.ready, io.mem_grant.valid) node _r_beats1_decode_T = dshl(UInt<12>(0hfff), io.mem_grant.bits.size) node _r_beats1_decode_T_1 = bits(_r_beats1_decode_T, 11, 0) node _r_beats1_decode_T_2 = not(_r_beats1_decode_T_1) node r_beats1_decode = shr(_r_beats1_decode_T_2, 3) node r_beats1_opdata = bits(io.mem_grant.bits.opcode, 0, 0) node r_beats1 = mux(r_beats1_opdata, r_beats1_decode, UInt<1>(0h0)) regreset r_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _r_counter1_T = sub(r_counter, UInt<1>(0h1)) node r_counter1 = tail(_r_counter1_T, 1) node r_1_1 = eq(r_counter, UInt<1>(0h0)) node _r_last_T = eq(r_counter, UInt<1>(0h1)) node _r_last_T_1 = eq(r_beats1, UInt<1>(0h0)) node r_2 = or(_r_last_T, _r_last_T_1) node refill_done = and(r_2, _T) node _r_count_T = not(r_counter1) node r_4 = and(r_beats1, _r_count_T) when _T : node _r_counter_T = mux(r_1_1, r_beats1, r_counter1) connect r_counter, _r_counter_T node refill_address_inc = shl(r_4, 3) node _sec_rdy_T = eq(cmd_requires_second_acquire, UInt<1>(0h0)) node _sec_rdy_T_1 = eq(io.req_is_probe, UInt<1>(0h0)) node _sec_rdy_T_2 = and(_sec_rdy_T, _sec_rdy_T_1) node _sec_rdy_T_3 = eq(state, UInt<5>(0h0)) node _sec_rdy_T_4 = eq(state, UInt<5>(0hd)) node _sec_rdy_T_5 = eq(state, UInt<5>(0he)) node _sec_rdy_T_6 = eq(state, UInt<5>(0hf)) node _sec_rdy_T_7 = or(_sec_rdy_T_3, _sec_rdy_T_4) node _sec_rdy_T_8 = or(_sec_rdy_T_7, _sec_rdy_T_5) node _sec_rdy_T_9 = or(_sec_rdy_T_8, _sec_rdy_T_6) node _sec_rdy_T_10 = eq(_sec_rdy_T_9, UInt<1>(0h0)) node sec_rdy = and(_sec_rdy_T_2, _sec_rdy_T_10) inst rpq of BranchKillableQueue_27 connect rpq.clock, clock connect rpq.reset, reset connect rpq.io.brupdate.b2.target_offset, io.brupdate.b2.target_offset connect rpq.io.brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect rpq.io.brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect rpq.io.brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect rpq.io.brupdate.b2.taken, io.brupdate.b2.taken connect rpq.io.brupdate.b2.mispredict, io.brupdate.b2.mispredict connect rpq.io.brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect rpq.io.brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect rpq.io.brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect rpq.io.brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect rpq.io.brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect rpq.io.brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect rpq.io.brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect rpq.io.brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ connect rpq.io.brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm connect rpq.io.brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect rpq.io.brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op connect rpq.io.brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw connect rpq.io.brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect rpq.io.brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect rpq.io.brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect rpq.io.brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect rpq.io.brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect rpq.io.brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect rpq.io.brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect rpq.io.brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect rpq.io.brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect rpq.io.brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd connect rpq.io.brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect rpq.io.brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect rpq.io.brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect rpq.io.brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect rpq.io.brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect rpq.io.brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect rpq.io.brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect rpq.io.brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect rpq.io.brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect rpq.io.brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect rpq.io.brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect rpq.io.brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect rpq.io.brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect rpq.io.brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect rpq.io.brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect rpq.io.brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect rpq.io.brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect rpq.io.brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect rpq.io.brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect rpq.io.brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect rpq.io.brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect rpq.io.brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect rpq.io.brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect rpq.io.brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec connect rpq.io.brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags connect rpq.io.brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt connect rpq.io.brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div connect rpq.io.brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma connect rpq.io.brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe connect rpq.io.brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint connect rpq.io.brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint connect rpq.io.brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut connect rpq.io.brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn connect rpq.io.brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23 connect rpq.io.brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12 connect rpq.io.brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3 connect rpq.io.brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2 connect rpq.io.brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1 connect rpq.io.brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen connect rpq.io.brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst connect rpq.io.brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel connect rpq.io.brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel connect rpq.io.brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect rpq.io.brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm connect rpq.io.brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel connect rpq.io.brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename connect rpq.io.brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect rpq.io.brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect rpq.io.brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect rpq.io.brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect rpq.io.brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov connect rpq.io.brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc connect rpq.io.brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect rpq.io.brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret connect rpq.io.brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect rpq.io.brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence connect rpq.io.brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect rpq.io.brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect rpq.io.brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect rpq.io.brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type connect rpq.io.brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect rpq.io.brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect rpq.io.brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel connect rpq.io.brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint connect rpq.io.brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint connect rpq.io.brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint connect rpq.io.brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child connect rpq.io.brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child connect rpq.io.brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen connect rpq.io.brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen connect rpq.io.brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued connect rpq.io.brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0] connect rpq.io.brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1] connect rpq.io.brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2] connect rpq.io.brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3] connect rpq.io.brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4] connect rpq.io.brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5] connect rpq.io.brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6] connect rpq.io.brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7] connect rpq.io.brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8] connect rpq.io.brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9] connect rpq.io.brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0] connect rpq.io.brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1] connect rpq.io.brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2] connect rpq.io.brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3] connect rpq.io.brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect rpq.io.brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect rpq.io.brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect rpq.io.brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect rpq.io.brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect rpq.io.brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect rpq.io.flush, io.exception node _T_1 = eq(state, UInt<5>(0h0)) node _T_2 = eq(rpq.io.empty, UInt<1>(0h0)) node _T_3 = and(_T_1, _T_2) node _T_4 = eq(_T_3, UInt<1>(0h0)) node _T_5 = asUInt(reset) node _T_6 = eq(_T_5, UInt<1>(0h0)) when _T_6 : node _T_7 = eq(_T_4, UInt<1>(0h0)) when _T_7 : printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:131 assert(!(state === s_invalid && !rpq.io.empty))\n") : printf assert(clock, _T_4, UInt<1>(0h1), "") : assert node _rpq_io_enq_valid_T = and(io.req_pri_val, io.req_pri_rdy) node _rpq_io_enq_valid_T_1 = and(io.req_sec_val, io.req_sec_rdy) node _rpq_io_enq_valid_T_2 = or(_rpq_io_enq_valid_T, _rpq_io_enq_valid_T_1) node _rpq_io_enq_valid_T_3 = eq(io.req.uop.mem_cmd, UInt<2>(0h2)) node _rpq_io_enq_valid_T_4 = eq(io.req.uop.mem_cmd, UInt<2>(0h3)) node _rpq_io_enq_valid_T_5 = or(_rpq_io_enq_valid_T_3, _rpq_io_enq_valid_T_4) node _rpq_io_enq_valid_T_6 = eq(_rpq_io_enq_valid_T_5, UInt<1>(0h0)) node _rpq_io_enq_valid_T_7 = and(_rpq_io_enq_valid_T_2, _rpq_io_enq_valid_T_6) connect rpq.io.enq.valid, _rpq_io_enq_valid_T_7 connect rpq.io.enq.bits.sdq_id, io.req.sdq_id connect rpq.io.enq.bits.way_en, io.req.way_en connect rpq.io.enq.bits.old_meta.tag, io.req.old_meta.tag connect rpq.io.enq.bits.old_meta.coh.state, io.req.old_meta.coh.state connect rpq.io.enq.bits.tag_match, io.req.tag_match connect rpq.io.enq.bits.is_hella, io.req.is_hella connect rpq.io.enq.bits.data, io.req.data connect rpq.io.enq.bits.addr, io.req.addr connect rpq.io.enq.bits.uop.debug_tsrc, io.req.uop.debug_tsrc connect rpq.io.enq.bits.uop.debug_fsrc, io.req.uop.debug_fsrc connect rpq.io.enq.bits.uop.bp_xcpt_if, io.req.uop.bp_xcpt_if connect rpq.io.enq.bits.uop.bp_debug_if, io.req.uop.bp_debug_if connect rpq.io.enq.bits.uop.xcpt_ma_if, io.req.uop.xcpt_ma_if connect rpq.io.enq.bits.uop.xcpt_ae_if, io.req.uop.xcpt_ae_if connect rpq.io.enq.bits.uop.xcpt_pf_if, io.req.uop.xcpt_pf_if connect rpq.io.enq.bits.uop.fp_typ, io.req.uop.fp_typ connect rpq.io.enq.bits.uop.fp_rm, io.req.uop.fp_rm connect rpq.io.enq.bits.uop.fp_val, io.req.uop.fp_val connect rpq.io.enq.bits.uop.fcn_op, io.req.uop.fcn_op connect rpq.io.enq.bits.uop.fcn_dw, io.req.uop.fcn_dw connect rpq.io.enq.bits.uop.frs3_en, io.req.uop.frs3_en connect rpq.io.enq.bits.uop.lrs2_rtype, io.req.uop.lrs2_rtype connect rpq.io.enq.bits.uop.lrs1_rtype, io.req.uop.lrs1_rtype connect rpq.io.enq.bits.uop.dst_rtype, io.req.uop.dst_rtype connect rpq.io.enq.bits.uop.lrs3, io.req.uop.lrs3 connect rpq.io.enq.bits.uop.lrs2, io.req.uop.lrs2 connect rpq.io.enq.bits.uop.lrs1, io.req.uop.lrs1 connect rpq.io.enq.bits.uop.ldst, io.req.uop.ldst connect rpq.io.enq.bits.uop.ldst_is_rs1, io.req.uop.ldst_is_rs1 connect rpq.io.enq.bits.uop.csr_cmd, io.req.uop.csr_cmd connect rpq.io.enq.bits.uop.flush_on_commit, io.req.uop.flush_on_commit connect rpq.io.enq.bits.uop.is_unique, io.req.uop.is_unique connect rpq.io.enq.bits.uop.uses_stq, io.req.uop.uses_stq connect rpq.io.enq.bits.uop.uses_ldq, io.req.uop.uses_ldq connect rpq.io.enq.bits.uop.mem_signed, io.req.uop.mem_signed connect rpq.io.enq.bits.uop.mem_size, io.req.uop.mem_size connect rpq.io.enq.bits.uop.mem_cmd, io.req.uop.mem_cmd connect rpq.io.enq.bits.uop.exc_cause, io.req.uop.exc_cause connect rpq.io.enq.bits.uop.exception, io.req.uop.exception connect rpq.io.enq.bits.uop.stale_pdst, io.req.uop.stale_pdst connect rpq.io.enq.bits.uop.ppred_busy, io.req.uop.ppred_busy connect rpq.io.enq.bits.uop.prs3_busy, io.req.uop.prs3_busy connect rpq.io.enq.bits.uop.prs2_busy, io.req.uop.prs2_busy connect rpq.io.enq.bits.uop.prs1_busy, io.req.uop.prs1_busy connect rpq.io.enq.bits.uop.ppred, io.req.uop.ppred connect rpq.io.enq.bits.uop.prs3, io.req.uop.prs3 connect rpq.io.enq.bits.uop.prs2, io.req.uop.prs2 connect rpq.io.enq.bits.uop.prs1, io.req.uop.prs1 connect rpq.io.enq.bits.uop.pdst, io.req.uop.pdst connect rpq.io.enq.bits.uop.rxq_idx, io.req.uop.rxq_idx connect rpq.io.enq.bits.uop.stq_idx, io.req.uop.stq_idx connect rpq.io.enq.bits.uop.ldq_idx, io.req.uop.ldq_idx connect rpq.io.enq.bits.uop.rob_idx, io.req.uop.rob_idx connect rpq.io.enq.bits.uop.fp_ctrl.vec, io.req.uop.fp_ctrl.vec connect rpq.io.enq.bits.uop.fp_ctrl.wflags, io.req.uop.fp_ctrl.wflags connect rpq.io.enq.bits.uop.fp_ctrl.sqrt, io.req.uop.fp_ctrl.sqrt connect rpq.io.enq.bits.uop.fp_ctrl.div, io.req.uop.fp_ctrl.div connect rpq.io.enq.bits.uop.fp_ctrl.fma, io.req.uop.fp_ctrl.fma connect rpq.io.enq.bits.uop.fp_ctrl.fastpipe, io.req.uop.fp_ctrl.fastpipe connect rpq.io.enq.bits.uop.fp_ctrl.toint, io.req.uop.fp_ctrl.toint connect rpq.io.enq.bits.uop.fp_ctrl.fromint, io.req.uop.fp_ctrl.fromint connect rpq.io.enq.bits.uop.fp_ctrl.typeTagOut, io.req.uop.fp_ctrl.typeTagOut connect rpq.io.enq.bits.uop.fp_ctrl.typeTagIn, io.req.uop.fp_ctrl.typeTagIn connect rpq.io.enq.bits.uop.fp_ctrl.swap23, io.req.uop.fp_ctrl.swap23 connect rpq.io.enq.bits.uop.fp_ctrl.swap12, io.req.uop.fp_ctrl.swap12 connect rpq.io.enq.bits.uop.fp_ctrl.ren3, io.req.uop.fp_ctrl.ren3 connect rpq.io.enq.bits.uop.fp_ctrl.ren2, io.req.uop.fp_ctrl.ren2 connect rpq.io.enq.bits.uop.fp_ctrl.ren1, io.req.uop.fp_ctrl.ren1 connect rpq.io.enq.bits.uop.fp_ctrl.wen, io.req.uop.fp_ctrl.wen connect rpq.io.enq.bits.uop.fp_ctrl.ldst, io.req.uop.fp_ctrl.ldst connect rpq.io.enq.bits.uop.op2_sel, io.req.uop.op2_sel connect rpq.io.enq.bits.uop.op1_sel, io.req.uop.op1_sel connect rpq.io.enq.bits.uop.imm_packed, io.req.uop.imm_packed connect rpq.io.enq.bits.uop.pimm, io.req.uop.pimm connect rpq.io.enq.bits.uop.imm_sel, io.req.uop.imm_sel connect rpq.io.enq.bits.uop.imm_rename, io.req.uop.imm_rename connect rpq.io.enq.bits.uop.taken, io.req.uop.taken connect rpq.io.enq.bits.uop.pc_lob, io.req.uop.pc_lob connect rpq.io.enq.bits.uop.edge_inst, io.req.uop.edge_inst connect rpq.io.enq.bits.uop.ftq_idx, io.req.uop.ftq_idx connect rpq.io.enq.bits.uop.is_mov, io.req.uop.is_mov connect rpq.io.enq.bits.uop.is_rocc, io.req.uop.is_rocc connect rpq.io.enq.bits.uop.is_sys_pc2epc, io.req.uop.is_sys_pc2epc connect rpq.io.enq.bits.uop.is_eret, io.req.uop.is_eret connect rpq.io.enq.bits.uop.is_amo, io.req.uop.is_amo connect rpq.io.enq.bits.uop.is_sfence, io.req.uop.is_sfence connect rpq.io.enq.bits.uop.is_fencei, io.req.uop.is_fencei connect rpq.io.enq.bits.uop.is_fence, io.req.uop.is_fence connect rpq.io.enq.bits.uop.is_sfb, io.req.uop.is_sfb connect rpq.io.enq.bits.uop.br_type, io.req.uop.br_type connect rpq.io.enq.bits.uop.br_tag, io.req.uop.br_tag connect rpq.io.enq.bits.uop.br_mask, io.req.uop.br_mask connect rpq.io.enq.bits.uop.dis_col_sel, io.req.uop.dis_col_sel connect rpq.io.enq.bits.uop.iw_p3_bypass_hint, io.req.uop.iw_p3_bypass_hint connect rpq.io.enq.bits.uop.iw_p2_bypass_hint, io.req.uop.iw_p2_bypass_hint connect rpq.io.enq.bits.uop.iw_p1_bypass_hint, io.req.uop.iw_p1_bypass_hint connect rpq.io.enq.bits.uop.iw_p2_speculative_child, io.req.uop.iw_p2_speculative_child connect rpq.io.enq.bits.uop.iw_p1_speculative_child, io.req.uop.iw_p1_speculative_child connect rpq.io.enq.bits.uop.iw_issued_partial_dgen, io.req.uop.iw_issued_partial_dgen connect rpq.io.enq.bits.uop.iw_issued_partial_agen, io.req.uop.iw_issued_partial_agen connect rpq.io.enq.bits.uop.iw_issued, io.req.uop.iw_issued connect rpq.io.enq.bits.uop.fu_code[0], io.req.uop.fu_code[0] connect rpq.io.enq.bits.uop.fu_code[1], io.req.uop.fu_code[1] connect rpq.io.enq.bits.uop.fu_code[2], io.req.uop.fu_code[2] connect rpq.io.enq.bits.uop.fu_code[3], io.req.uop.fu_code[3] connect rpq.io.enq.bits.uop.fu_code[4], io.req.uop.fu_code[4] connect rpq.io.enq.bits.uop.fu_code[5], io.req.uop.fu_code[5] connect rpq.io.enq.bits.uop.fu_code[6], io.req.uop.fu_code[6] connect rpq.io.enq.bits.uop.fu_code[7], io.req.uop.fu_code[7] connect rpq.io.enq.bits.uop.fu_code[8], io.req.uop.fu_code[8] connect rpq.io.enq.bits.uop.fu_code[9], io.req.uop.fu_code[9] connect rpq.io.enq.bits.uop.iq_type[0], io.req.uop.iq_type[0] connect rpq.io.enq.bits.uop.iq_type[1], io.req.uop.iq_type[1] connect rpq.io.enq.bits.uop.iq_type[2], io.req.uop.iq_type[2] connect rpq.io.enq.bits.uop.iq_type[3], io.req.uop.iq_type[3] connect rpq.io.enq.bits.uop.debug_pc, io.req.uop.debug_pc connect rpq.io.enq.bits.uop.is_rvc, io.req.uop.is_rvc connect rpq.io.enq.bits.uop.debug_inst, io.req.uop.debug_inst connect rpq.io.enq.bits.uop.inst, io.req.uop.inst connect rpq.io.deq.ready, UInt<1>(0h0) reg grantack : { valid : UInt<1>, bits : { sink : UInt<3>}}, clock reg refill_ctr : UInt<3>, clock reg commit_line : UInt<1>, clock reg grant_had_data : UInt<1>, clock reg finish_to_prefetch : UInt<1>, clock regreset meta_hazard : UInt<2>, clock, reset, UInt<2>(0h0) node _T_8 = neq(meta_hazard, UInt<1>(0h0)) when _T_8 : node _meta_hazard_T = add(meta_hazard, UInt<1>(0h1)) node _meta_hazard_T_1 = tail(_meta_hazard_T, 1) connect meta_hazard, _meta_hazard_T_1 node _T_9 = and(io.meta_write.ready, io.meta_write.valid) when _T_9 : connect meta_hazard, UInt<1>(0h1) node _io_probe_rdy_T = eq(meta_hazard, UInt<1>(0h0)) node _io_probe_rdy_T_1 = eq(state, UInt<5>(0h0)) node _io_probe_rdy_T_2 = eq(state, UInt<5>(0h1)) node _io_probe_rdy_T_3 = eq(state, UInt<5>(0h2)) node _io_probe_rdy_T_4 = eq(state, UInt<5>(0h3)) node _io_probe_rdy_T_5 = or(_io_probe_rdy_T_1, _io_probe_rdy_T_2) node _io_probe_rdy_T_6 = or(_io_probe_rdy_T_5, _io_probe_rdy_T_3) node _io_probe_rdy_T_7 = or(_io_probe_rdy_T_6, _io_probe_rdy_T_4) node _io_probe_rdy_T_8 = eq(state, UInt<5>(0h4)) node _io_probe_rdy_T_9 = and(_io_probe_rdy_T_8, grantack.valid) node _io_probe_rdy_T_10 = or(_io_probe_rdy_T_7, _io_probe_rdy_T_9) node _io_probe_rdy_T_11 = and(_io_probe_rdy_T, _io_probe_rdy_T_10) connect io.probe_rdy, _io_probe_rdy_T_11 node _io_idx_valid_T = neq(state, UInt<5>(0h0)) connect io.idx.valid, _io_idx_valid_T node _io_tag_valid_T = neq(state, UInt<5>(0h0)) connect io.tag.valid, _io_tag_valid_T node _io_way_valid_T = eq(state, UInt<5>(0h0)) node _io_way_valid_T_1 = eq(state, UInt<5>(0h11)) node _io_way_valid_T_2 = or(_io_way_valid_T, _io_way_valid_T_1) node _io_way_valid_T_3 = eq(_io_way_valid_T_2, UInt<1>(0h0)) connect io.way.valid, _io_way_valid_T_3 connect io.idx.bits, req_idx connect io.tag.bits, req_tag connect io.way.bits, req.way_en connect io.meta_write.valid, UInt<1>(0h0) connect io.meta_write.bits.idx, req_idx connect io.meta_write.bits.data.coh, coh_on_clear connect io.meta_write.bits.data.tag, req_tag connect io.meta_write.bits.way_en, req.way_en connect io.meta_write.bits.tag, req_tag connect io.req_pri_rdy, UInt<1>(0h0) node _io_req_sec_rdy_T = and(sec_rdy, rpq.io.enq.ready) connect io.req_sec_rdy, _io_req_sec_rdy_T connect io.mem_acquire.valid, UInt<1>(0h0) node _io_mem_acquire_bits_T = cat(req_tag, req_idx) node _io_mem_acquire_bits_T_1 = shl(_io_mem_acquire_bits_T, 6) node _io_mem_acquire_bits_legal_T = or(UInt<1>(0h0), UInt<1>(0h0)) node _io_mem_acquire_bits_legal_T_1 = xor(_io_mem_acquire_bits_T_1, UInt<1>(0h0)) node _io_mem_acquire_bits_legal_T_2 = cvt(_io_mem_acquire_bits_legal_T_1) node _io_mem_acquire_bits_legal_T_3 = and(_io_mem_acquire_bits_legal_T_2, asSInt(UInt<33>(0h80000000))) node _io_mem_acquire_bits_legal_T_4 = asSInt(_io_mem_acquire_bits_legal_T_3) node _io_mem_acquire_bits_legal_T_5 = eq(_io_mem_acquire_bits_legal_T_4, asSInt(UInt<1>(0h0))) node _io_mem_acquire_bits_legal_T_6 = and(_io_mem_acquire_bits_legal_T, _io_mem_acquire_bits_legal_T_5) node _io_mem_acquire_bits_legal_T_7 = eq(UInt<3>(0h6), UInt<3>(0h6)) node _io_mem_acquire_bits_legal_T_8 = or(UInt<1>(0h0), _io_mem_acquire_bits_legal_T_7) node _io_mem_acquire_bits_legal_T_9 = xor(_io_mem_acquire_bits_T_1, UInt<32>(0h80000000)) node _io_mem_acquire_bits_legal_T_10 = cvt(_io_mem_acquire_bits_legal_T_9) node _io_mem_acquire_bits_legal_T_11 = and(_io_mem_acquire_bits_legal_T_10, asSInt(UInt<33>(0h80000000))) node _io_mem_acquire_bits_legal_T_12 = asSInt(_io_mem_acquire_bits_legal_T_11) node _io_mem_acquire_bits_legal_T_13 = eq(_io_mem_acquire_bits_legal_T_12, asSInt(UInt<1>(0h0))) node _io_mem_acquire_bits_legal_T_14 = and(_io_mem_acquire_bits_legal_T_8, _io_mem_acquire_bits_legal_T_13) node _io_mem_acquire_bits_legal_T_15 = or(UInt<1>(0h0), _io_mem_acquire_bits_legal_T_6) node io_mem_acquire_bits_legal = or(_io_mem_acquire_bits_legal_T_15, _io_mem_acquire_bits_legal_T_14) wire io_mem_acquire_bits_a : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} connect io_mem_acquire_bits_a.opcode, UInt<3>(0h6) connect io_mem_acquire_bits_a.param, grow_param connect io_mem_acquire_bits_a.size, UInt<3>(0h6) connect io_mem_acquire_bits_a.source, io.id connect io_mem_acquire_bits_a.address, _io_mem_acquire_bits_T_1 node _io_mem_acquire_bits_a_mask_sizeOH_T = or(UInt<3>(0h6), UInt<3>(0h0)) node io_mem_acquire_bits_a_mask_sizeOH_shiftAmount = bits(_io_mem_acquire_bits_a_mask_sizeOH_T, 1, 0) node _io_mem_acquire_bits_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), io_mem_acquire_bits_a_mask_sizeOH_shiftAmount) node _io_mem_acquire_bits_a_mask_sizeOH_T_2 = bits(_io_mem_acquire_bits_a_mask_sizeOH_T_1, 2, 0) node io_mem_acquire_bits_a_mask_sizeOH = or(_io_mem_acquire_bits_a_mask_sizeOH_T_2, UInt<1>(0h1)) node io_mem_acquire_bits_a_mask_sub_sub_sub_0_1 = geq(UInt<3>(0h6), UInt<2>(0h3)) node io_mem_acquire_bits_a_mask_sub_sub_size = bits(io_mem_acquire_bits_a_mask_sizeOH, 2, 2) node io_mem_acquire_bits_a_mask_sub_sub_bit = bits(_io_mem_acquire_bits_T_1, 2, 2) node io_mem_acquire_bits_a_mask_sub_sub_nbit = eq(io_mem_acquire_bits_a_mask_sub_sub_bit, UInt<1>(0h0)) node io_mem_acquire_bits_a_mask_sub_sub_0_2 = and(UInt<1>(0h1), io_mem_acquire_bits_a_mask_sub_sub_nbit) node _io_mem_acquire_bits_a_mask_sub_sub_acc_T = and(io_mem_acquire_bits_a_mask_sub_sub_size, io_mem_acquire_bits_a_mask_sub_sub_0_2) node io_mem_acquire_bits_a_mask_sub_sub_0_1 = or(io_mem_acquire_bits_a_mask_sub_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_sub_acc_T) node io_mem_acquire_bits_a_mask_sub_sub_1_2 = and(UInt<1>(0h1), io_mem_acquire_bits_a_mask_sub_sub_bit) node _io_mem_acquire_bits_a_mask_sub_sub_acc_T_1 = and(io_mem_acquire_bits_a_mask_sub_sub_size, io_mem_acquire_bits_a_mask_sub_sub_1_2) node io_mem_acquire_bits_a_mask_sub_sub_1_1 = or(io_mem_acquire_bits_a_mask_sub_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_sub_acc_T_1) node io_mem_acquire_bits_a_mask_sub_size = bits(io_mem_acquire_bits_a_mask_sizeOH, 1, 1) node io_mem_acquire_bits_a_mask_sub_bit = bits(_io_mem_acquire_bits_T_1, 1, 1) node io_mem_acquire_bits_a_mask_sub_nbit = eq(io_mem_acquire_bits_a_mask_sub_bit, UInt<1>(0h0)) node io_mem_acquire_bits_a_mask_sub_0_2 = and(io_mem_acquire_bits_a_mask_sub_sub_0_2, io_mem_acquire_bits_a_mask_sub_nbit) node _io_mem_acquire_bits_a_mask_sub_acc_T = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_0_2) node io_mem_acquire_bits_a_mask_sub_0_1 = or(io_mem_acquire_bits_a_mask_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_acc_T) node io_mem_acquire_bits_a_mask_sub_1_2 = and(io_mem_acquire_bits_a_mask_sub_sub_0_2, io_mem_acquire_bits_a_mask_sub_bit) node _io_mem_acquire_bits_a_mask_sub_acc_T_1 = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_1_2) node io_mem_acquire_bits_a_mask_sub_1_1 = or(io_mem_acquire_bits_a_mask_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_acc_T_1) node io_mem_acquire_bits_a_mask_sub_2_2 = and(io_mem_acquire_bits_a_mask_sub_sub_1_2, io_mem_acquire_bits_a_mask_sub_nbit) node _io_mem_acquire_bits_a_mask_sub_acc_T_2 = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_2_2) node io_mem_acquire_bits_a_mask_sub_2_1 = or(io_mem_acquire_bits_a_mask_sub_sub_1_1, _io_mem_acquire_bits_a_mask_sub_acc_T_2) node io_mem_acquire_bits_a_mask_sub_3_2 = and(io_mem_acquire_bits_a_mask_sub_sub_1_2, io_mem_acquire_bits_a_mask_sub_bit) node _io_mem_acquire_bits_a_mask_sub_acc_T_3 = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_3_2) node io_mem_acquire_bits_a_mask_sub_3_1 = or(io_mem_acquire_bits_a_mask_sub_sub_1_1, _io_mem_acquire_bits_a_mask_sub_acc_T_3) node io_mem_acquire_bits_a_mask_size = bits(io_mem_acquire_bits_a_mask_sizeOH, 0, 0) node io_mem_acquire_bits_a_mask_bit = bits(_io_mem_acquire_bits_T_1, 0, 0) node io_mem_acquire_bits_a_mask_nbit = eq(io_mem_acquire_bits_a_mask_bit, UInt<1>(0h0)) node io_mem_acquire_bits_a_mask_eq = and(io_mem_acquire_bits_a_mask_sub_0_2, io_mem_acquire_bits_a_mask_nbit) node _io_mem_acquire_bits_a_mask_acc_T = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq) node io_mem_acquire_bits_a_mask_acc = or(io_mem_acquire_bits_a_mask_sub_0_1, _io_mem_acquire_bits_a_mask_acc_T) node io_mem_acquire_bits_a_mask_eq_1 = and(io_mem_acquire_bits_a_mask_sub_0_2, io_mem_acquire_bits_a_mask_bit) node _io_mem_acquire_bits_a_mask_acc_T_1 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_1) node io_mem_acquire_bits_a_mask_acc_1 = or(io_mem_acquire_bits_a_mask_sub_0_1, _io_mem_acquire_bits_a_mask_acc_T_1) node io_mem_acquire_bits_a_mask_eq_2 = and(io_mem_acquire_bits_a_mask_sub_1_2, io_mem_acquire_bits_a_mask_nbit) node _io_mem_acquire_bits_a_mask_acc_T_2 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_2) node io_mem_acquire_bits_a_mask_acc_2 = or(io_mem_acquire_bits_a_mask_sub_1_1, _io_mem_acquire_bits_a_mask_acc_T_2) node io_mem_acquire_bits_a_mask_eq_3 = and(io_mem_acquire_bits_a_mask_sub_1_2, io_mem_acquire_bits_a_mask_bit) node _io_mem_acquire_bits_a_mask_acc_T_3 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_3) node io_mem_acquire_bits_a_mask_acc_3 = or(io_mem_acquire_bits_a_mask_sub_1_1, _io_mem_acquire_bits_a_mask_acc_T_3) node io_mem_acquire_bits_a_mask_eq_4 = and(io_mem_acquire_bits_a_mask_sub_2_2, io_mem_acquire_bits_a_mask_nbit) node _io_mem_acquire_bits_a_mask_acc_T_4 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_4) node io_mem_acquire_bits_a_mask_acc_4 = or(io_mem_acquire_bits_a_mask_sub_2_1, _io_mem_acquire_bits_a_mask_acc_T_4) node io_mem_acquire_bits_a_mask_eq_5 = and(io_mem_acquire_bits_a_mask_sub_2_2, io_mem_acquire_bits_a_mask_bit) node _io_mem_acquire_bits_a_mask_acc_T_5 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_5) node io_mem_acquire_bits_a_mask_acc_5 = or(io_mem_acquire_bits_a_mask_sub_2_1, _io_mem_acquire_bits_a_mask_acc_T_5) node io_mem_acquire_bits_a_mask_eq_6 = and(io_mem_acquire_bits_a_mask_sub_3_2, io_mem_acquire_bits_a_mask_nbit) node _io_mem_acquire_bits_a_mask_acc_T_6 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_6) node io_mem_acquire_bits_a_mask_acc_6 = or(io_mem_acquire_bits_a_mask_sub_3_1, _io_mem_acquire_bits_a_mask_acc_T_6) node io_mem_acquire_bits_a_mask_eq_7 = and(io_mem_acquire_bits_a_mask_sub_3_2, io_mem_acquire_bits_a_mask_bit) node _io_mem_acquire_bits_a_mask_acc_T_7 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_7) node io_mem_acquire_bits_a_mask_acc_7 = or(io_mem_acquire_bits_a_mask_sub_3_1, _io_mem_acquire_bits_a_mask_acc_T_7) node io_mem_acquire_bits_a_mask_lo_lo = cat(io_mem_acquire_bits_a_mask_acc_1, io_mem_acquire_bits_a_mask_acc) node io_mem_acquire_bits_a_mask_lo_hi = cat(io_mem_acquire_bits_a_mask_acc_3, io_mem_acquire_bits_a_mask_acc_2) node io_mem_acquire_bits_a_mask_lo = cat(io_mem_acquire_bits_a_mask_lo_hi, io_mem_acquire_bits_a_mask_lo_lo) node io_mem_acquire_bits_a_mask_hi_lo = cat(io_mem_acquire_bits_a_mask_acc_5, io_mem_acquire_bits_a_mask_acc_4) node io_mem_acquire_bits_a_mask_hi_hi = cat(io_mem_acquire_bits_a_mask_acc_7, io_mem_acquire_bits_a_mask_acc_6) node io_mem_acquire_bits_a_mask_hi = cat(io_mem_acquire_bits_a_mask_hi_hi, io_mem_acquire_bits_a_mask_hi_lo) node _io_mem_acquire_bits_a_mask_T = cat(io_mem_acquire_bits_a_mask_hi, io_mem_acquire_bits_a_mask_lo) connect io_mem_acquire_bits_a.mask, _io_mem_acquire_bits_a_mask_T invalidate io_mem_acquire_bits_a.data connect io_mem_acquire_bits_a.corrupt, UInt<1>(0h0) connect io.mem_acquire.bits, io_mem_acquire_bits_a connect io.refill.valid, UInt<1>(0h0) node _io_refill_bits_addr_T = shl(refill_ctr, 3) node _io_refill_bits_addr_T_1 = or(req_block_addr, _io_refill_bits_addr_T) connect io.refill.bits.addr, _io_refill_bits_addr_T_1 connect io.refill.bits.way_en, req.way_en node _io_refill_bits_wmask_T = not(UInt<1>(0h0)) connect io.refill.bits.wmask, _io_refill_bits_wmask_T connect io.refill.bits.data, io.lb_resp connect io.replay.valid, UInt<1>(0h0) connect io.replay.bits, rpq.io.deq.bits connect io.wb_req.valid, UInt<1>(0h0) connect io.wb_req.bits.tag, req.old_meta.tag connect io.wb_req.bits.idx, req_idx connect io.wb_req.bits.param, shrink_param connect io.wb_req.bits.way_en, req.way_en connect io.wb_req.bits.source, io.id connect io.wb_req.bits.voluntary, UInt<1>(0h1) connect io.resp.valid, UInt<1>(0h0) connect io.resp.bits.is_hella, rpq.io.deq.bits.is_hella connect io.resp.bits.data, rpq.io.deq.bits.data connect io.resp.bits.uop, rpq.io.deq.bits.uop connect io.commit_val, UInt<1>(0h0) connect io.commit_addr, req.addr connect io.commit_coh, coh_on_grant connect io.meta_read.valid, UInt<1>(0h0) connect io.meta_read.bits.idx, req_idx connect io.meta_read.bits.tag, req_tag connect io.meta_read.bits.way_en, req.way_en connect io.mem_finish.valid, UInt<1>(0h0) connect io.mem_finish.bits, grantack.bits connect io.lb_write.valid, UInt<1>(0h0) node _io_lb_write_bits_offset_T = shr(refill_address_inc, 3) connect io.lb_write.bits.offset, _io_lb_write_bits_offset_T connect io.lb_write.bits.data, io.mem_grant.bits.data connect io.mem_grant.ready, UInt<1>(0h0) node _io_lb_read_offset_T = shr(rpq.io.deq.bits.addr, 3) connect io.lb_read.offset, _io_lb_read_offset_T node _T_10 = and(io.req_sec_val, io.req_sec_rdy) when _T_10 : connect req.uop.mem_cmd, dirtier_cmd when is_hit_again : connect new_coh, dirtier_coh node _T_11 = eq(state, UInt<5>(0h0)) when _T_11 : connect io.req_pri_rdy, UInt<1>(0h1) connect grant_had_data, UInt<1>(0h0) node _T_12 = and(io.req_pri_val, io.req_pri_rdy) when _T_12 : wire state_new_state : UInt connect state_new_state, state connect grantack.valid, UInt<1>(0h0) connect refill_ctr, UInt<1>(0h0) node _state_T = asUInt(reset) node _state_T_1 = eq(_state_T, UInt<1>(0h0)) when _state_T_1 : node _state_T_2 = eq(rpq.io.enq.ready, UInt<1>(0h0)) when _state_T_2 : printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:213 assert(rpq.io.enq.ready)\n") : state_printf assert(clock, rpq.io.enq.ready, UInt<1>(0h1), "") : state_assert connect req, io.req node _state_req_needs_wb_r_T = eq(UInt<5>(0h10), UInt<5>(0h10)) node _state_req_needs_wb_r_T_1 = mux(_state_req_needs_wb_r_T, UInt<2>(0h2), UInt<2>(0h2)) node _state_req_needs_wb_r_T_2 = eq(UInt<5>(0h12), UInt<5>(0h10)) node _state_req_needs_wb_r_T_3 = mux(_state_req_needs_wb_r_T_2, UInt<2>(0h1), _state_req_needs_wb_r_T_1) node _state_req_needs_wb_r_T_4 = eq(UInt<5>(0h13), UInt<5>(0h10)) node _state_req_needs_wb_r_T_5 = mux(_state_req_needs_wb_r_T_4, UInt<2>(0h0), _state_req_needs_wb_r_T_3) node _state_req_needs_wb_r_T_6 = cat(_state_req_needs_wb_r_T_5, io.req.old_meta.coh.state) node _state_req_needs_wb_r_T_7 = cat(UInt<2>(0h0), UInt<2>(0h3)) node _state_req_needs_wb_r_T_8 = cat(UInt<2>(0h0), UInt<2>(0h2)) node _state_req_needs_wb_r_T_9 = cat(UInt<2>(0h0), UInt<2>(0h1)) node _state_req_needs_wb_r_T_10 = cat(UInt<2>(0h0), UInt<2>(0h0)) node _state_req_needs_wb_r_T_11 = cat(UInt<2>(0h1), UInt<2>(0h3)) node _state_req_needs_wb_r_T_12 = cat(UInt<2>(0h1), UInt<2>(0h2)) node _state_req_needs_wb_r_T_13 = cat(UInt<2>(0h1), UInt<2>(0h1)) node _state_req_needs_wb_r_T_14 = cat(UInt<2>(0h1), UInt<2>(0h0)) node _state_req_needs_wb_r_T_15 = cat(UInt<2>(0h2), UInt<2>(0h3)) node _state_req_needs_wb_r_T_16 = cat(UInt<2>(0h2), UInt<2>(0h2)) node _state_req_needs_wb_r_T_17 = cat(UInt<2>(0h2), UInt<2>(0h1)) node _state_req_needs_wb_r_T_18 = cat(UInt<2>(0h2), UInt<2>(0h0)) node _state_req_needs_wb_r_T_19 = eq(_state_req_needs_wb_r_T_18, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_20 = mux(_state_req_needs_wb_r_T_19, UInt<1>(0h0), UInt<1>(0h0)) node _state_req_needs_wb_r_T_21 = mux(_state_req_needs_wb_r_T_19, UInt<3>(0h5), UInt<1>(0h0)) node _state_req_needs_wb_r_T_22 = mux(_state_req_needs_wb_r_T_19, UInt<2>(0h0), UInt<1>(0h0)) node _state_req_needs_wb_r_T_23 = eq(_state_req_needs_wb_r_T_17, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_24 = mux(_state_req_needs_wb_r_T_23, UInt<1>(0h0), _state_req_needs_wb_r_T_20) node _state_req_needs_wb_r_T_25 = mux(_state_req_needs_wb_r_T_23, UInt<3>(0h2), _state_req_needs_wb_r_T_21) node _state_req_needs_wb_r_T_26 = mux(_state_req_needs_wb_r_T_23, UInt<2>(0h0), _state_req_needs_wb_r_T_22) node _state_req_needs_wb_r_T_27 = eq(_state_req_needs_wb_r_T_16, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_28 = mux(_state_req_needs_wb_r_T_27, UInt<1>(0h0), _state_req_needs_wb_r_T_24) node _state_req_needs_wb_r_T_29 = mux(_state_req_needs_wb_r_T_27, UInt<3>(0h1), _state_req_needs_wb_r_T_25) node _state_req_needs_wb_r_T_30 = mux(_state_req_needs_wb_r_T_27, UInt<2>(0h0), _state_req_needs_wb_r_T_26) node _state_req_needs_wb_r_T_31 = eq(_state_req_needs_wb_r_T_15, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_32 = mux(_state_req_needs_wb_r_T_31, UInt<1>(0h1), _state_req_needs_wb_r_T_28) node _state_req_needs_wb_r_T_33 = mux(_state_req_needs_wb_r_T_31, UInt<3>(0h1), _state_req_needs_wb_r_T_29) node _state_req_needs_wb_r_T_34 = mux(_state_req_needs_wb_r_T_31, UInt<2>(0h0), _state_req_needs_wb_r_T_30) node _state_req_needs_wb_r_T_35 = eq(_state_req_needs_wb_r_T_14, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_36 = mux(_state_req_needs_wb_r_T_35, UInt<1>(0h0), _state_req_needs_wb_r_T_32) node _state_req_needs_wb_r_T_37 = mux(_state_req_needs_wb_r_T_35, UInt<3>(0h5), _state_req_needs_wb_r_T_33) node _state_req_needs_wb_r_T_38 = mux(_state_req_needs_wb_r_T_35, UInt<2>(0h0), _state_req_needs_wb_r_T_34) node _state_req_needs_wb_r_T_39 = eq(_state_req_needs_wb_r_T_13, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_40 = mux(_state_req_needs_wb_r_T_39, UInt<1>(0h0), _state_req_needs_wb_r_T_36) node _state_req_needs_wb_r_T_41 = mux(_state_req_needs_wb_r_T_39, UInt<3>(0h4), _state_req_needs_wb_r_T_37) node _state_req_needs_wb_r_T_42 = mux(_state_req_needs_wb_r_T_39, UInt<2>(0h1), _state_req_needs_wb_r_T_38) node _state_req_needs_wb_r_T_43 = eq(_state_req_needs_wb_r_T_12, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_44 = mux(_state_req_needs_wb_r_T_43, UInt<1>(0h0), _state_req_needs_wb_r_T_40) node _state_req_needs_wb_r_T_45 = mux(_state_req_needs_wb_r_T_43, UInt<3>(0h0), _state_req_needs_wb_r_T_41) node _state_req_needs_wb_r_T_46 = mux(_state_req_needs_wb_r_T_43, UInt<2>(0h1), _state_req_needs_wb_r_T_42) node _state_req_needs_wb_r_T_47 = eq(_state_req_needs_wb_r_T_11, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_48 = mux(_state_req_needs_wb_r_T_47, UInt<1>(0h1), _state_req_needs_wb_r_T_44) node _state_req_needs_wb_r_T_49 = mux(_state_req_needs_wb_r_T_47, UInt<3>(0h0), _state_req_needs_wb_r_T_45) node _state_req_needs_wb_r_T_50 = mux(_state_req_needs_wb_r_T_47, UInt<2>(0h1), _state_req_needs_wb_r_T_46) node _state_req_needs_wb_r_T_51 = eq(_state_req_needs_wb_r_T_10, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_52 = mux(_state_req_needs_wb_r_T_51, UInt<1>(0h0), _state_req_needs_wb_r_T_48) node _state_req_needs_wb_r_T_53 = mux(_state_req_needs_wb_r_T_51, UInt<3>(0h5), _state_req_needs_wb_r_T_49) node _state_req_needs_wb_r_T_54 = mux(_state_req_needs_wb_r_T_51, UInt<2>(0h0), _state_req_needs_wb_r_T_50) node _state_req_needs_wb_r_T_55 = eq(_state_req_needs_wb_r_T_9, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_56 = mux(_state_req_needs_wb_r_T_55, UInt<1>(0h0), _state_req_needs_wb_r_T_52) node _state_req_needs_wb_r_T_57 = mux(_state_req_needs_wb_r_T_55, UInt<3>(0h4), _state_req_needs_wb_r_T_53) node _state_req_needs_wb_r_T_58 = mux(_state_req_needs_wb_r_T_55, UInt<2>(0h1), _state_req_needs_wb_r_T_54) node _state_req_needs_wb_r_T_59 = eq(_state_req_needs_wb_r_T_8, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_60 = mux(_state_req_needs_wb_r_T_59, UInt<1>(0h0), _state_req_needs_wb_r_T_56) node _state_req_needs_wb_r_T_61 = mux(_state_req_needs_wb_r_T_59, UInt<3>(0h3), _state_req_needs_wb_r_T_57) node _state_req_needs_wb_r_T_62 = mux(_state_req_needs_wb_r_T_59, UInt<2>(0h2), _state_req_needs_wb_r_T_58) node _state_req_needs_wb_r_T_63 = eq(_state_req_needs_wb_r_T_7, _state_req_needs_wb_r_T_6) node state_req_needs_wb_r_1 = mux(_state_req_needs_wb_r_T_63, UInt<1>(0h1), _state_req_needs_wb_r_T_60) node state_req_needs_wb_r_2 = mux(_state_req_needs_wb_r_T_63, UInt<3>(0h3), _state_req_needs_wb_r_T_61) node state_req_needs_wb_r_3 = mux(_state_req_needs_wb_r_T_63, UInt<2>(0h2), _state_req_needs_wb_r_T_62) wire state_req_needs_wb_meta : { state : UInt<2>} connect state_req_needs_wb_meta.state, state_req_needs_wb_r_3 connect req_needs_wb, state_req_needs_wb_r_1 when io.req.tag_match : node _state_r_c_cat_T = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _state_r_c_cat_T_1 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _state_r_c_cat_T_2 = or(_state_r_c_cat_T, _state_r_c_cat_T_1) node _state_r_c_cat_T_3 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _state_r_c_cat_T_4 = or(_state_r_c_cat_T_2, _state_r_c_cat_T_3) node _state_r_c_cat_T_5 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _state_r_c_cat_T_6 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _state_r_c_cat_T_7 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _state_r_c_cat_T_8 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _state_r_c_cat_T_9 = or(_state_r_c_cat_T_5, _state_r_c_cat_T_6) node _state_r_c_cat_T_10 = or(_state_r_c_cat_T_9, _state_r_c_cat_T_7) node _state_r_c_cat_T_11 = or(_state_r_c_cat_T_10, _state_r_c_cat_T_8) node _state_r_c_cat_T_12 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _state_r_c_cat_T_13 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _state_r_c_cat_T_14 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _state_r_c_cat_T_15 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _state_r_c_cat_T_16 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _state_r_c_cat_T_17 = or(_state_r_c_cat_T_12, _state_r_c_cat_T_13) node _state_r_c_cat_T_18 = or(_state_r_c_cat_T_17, _state_r_c_cat_T_14) node _state_r_c_cat_T_19 = or(_state_r_c_cat_T_18, _state_r_c_cat_T_15) node _state_r_c_cat_T_20 = or(_state_r_c_cat_T_19, _state_r_c_cat_T_16) node _state_r_c_cat_T_21 = or(_state_r_c_cat_T_11, _state_r_c_cat_T_20) node _state_r_c_cat_T_22 = or(_state_r_c_cat_T_4, _state_r_c_cat_T_21) node _state_r_c_cat_T_23 = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _state_r_c_cat_T_24 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _state_r_c_cat_T_25 = or(_state_r_c_cat_T_23, _state_r_c_cat_T_24) node _state_r_c_cat_T_26 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _state_r_c_cat_T_27 = or(_state_r_c_cat_T_25, _state_r_c_cat_T_26) node _state_r_c_cat_T_28 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _state_r_c_cat_T_29 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _state_r_c_cat_T_30 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _state_r_c_cat_T_31 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _state_r_c_cat_T_32 = or(_state_r_c_cat_T_28, _state_r_c_cat_T_29) node _state_r_c_cat_T_33 = or(_state_r_c_cat_T_32, _state_r_c_cat_T_30) node _state_r_c_cat_T_34 = or(_state_r_c_cat_T_33, _state_r_c_cat_T_31) node _state_r_c_cat_T_35 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _state_r_c_cat_T_36 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _state_r_c_cat_T_37 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _state_r_c_cat_T_38 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _state_r_c_cat_T_39 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _state_r_c_cat_T_40 = or(_state_r_c_cat_T_35, _state_r_c_cat_T_36) node _state_r_c_cat_T_41 = or(_state_r_c_cat_T_40, _state_r_c_cat_T_37) node _state_r_c_cat_T_42 = or(_state_r_c_cat_T_41, _state_r_c_cat_T_38) node _state_r_c_cat_T_43 = or(_state_r_c_cat_T_42, _state_r_c_cat_T_39) node _state_r_c_cat_T_44 = or(_state_r_c_cat_T_34, _state_r_c_cat_T_43) node _state_r_c_cat_T_45 = or(_state_r_c_cat_T_27, _state_r_c_cat_T_44) node _state_r_c_cat_T_46 = eq(io.req.uop.mem_cmd, UInt<2>(0h3)) node _state_r_c_cat_T_47 = or(_state_r_c_cat_T_45, _state_r_c_cat_T_46) node _state_r_c_cat_T_48 = eq(io.req.uop.mem_cmd, UInt<3>(0h6)) node _state_r_c_cat_T_49 = or(_state_r_c_cat_T_47, _state_r_c_cat_T_48) node state_r_c = cat(_state_r_c_cat_T_22, _state_r_c_cat_T_49) node _state_r_T = cat(state_r_c, io.req.old_meta.coh.state) node _state_r_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_2 = cat(_state_r_T_1, UInt<2>(0h3)) node _state_r_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_4 = cat(_state_r_T_3, UInt<2>(0h2)) node _state_r_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_6 = cat(_state_r_T_5, UInt<2>(0h1)) node _state_r_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _state_r_T_8 = cat(_state_r_T_7, UInt<2>(0h3)) node _state_r_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _state_r_T_10 = cat(_state_r_T_9, UInt<2>(0h2)) node _state_r_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _state_r_T_12 = cat(_state_r_T_11, UInt<2>(0h3)) node _state_r_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _state_r_T_14 = cat(_state_r_T_13, UInt<2>(0h2)) node _state_r_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_16 = cat(_state_r_T_15, UInt<2>(0h0)) node _state_r_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _state_r_T_18 = cat(_state_r_T_17, UInt<2>(0h1)) node _state_r_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _state_r_T_20 = cat(_state_r_T_19, UInt<2>(0h0)) node _state_r_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _state_r_T_22 = cat(_state_r_T_21, UInt<2>(0h1)) node _state_r_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _state_r_T_24 = cat(_state_r_T_23, UInt<2>(0h0)) node _state_r_T_25 = eq(_state_r_T_24, _state_r_T) node _state_r_T_26 = mux(_state_r_T_25, UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_27 = mux(_state_r_T_25, UInt<2>(0h1), UInt<1>(0h0)) node _state_r_T_28 = eq(_state_r_T_22, _state_r_T) node _state_r_T_29 = mux(_state_r_T_28, UInt<1>(0h0), _state_r_T_26) node _state_r_T_30 = mux(_state_r_T_28, UInt<2>(0h2), _state_r_T_27) node _state_r_T_31 = eq(_state_r_T_20, _state_r_T) node _state_r_T_32 = mux(_state_r_T_31, UInt<1>(0h0), _state_r_T_29) node _state_r_T_33 = mux(_state_r_T_31, UInt<2>(0h1), _state_r_T_30) node _state_r_T_34 = eq(_state_r_T_18, _state_r_T) node _state_r_T_35 = mux(_state_r_T_34, UInt<1>(0h0), _state_r_T_32) node _state_r_T_36 = mux(_state_r_T_34, UInt<2>(0h2), _state_r_T_33) node _state_r_T_37 = eq(_state_r_T_16, _state_r_T) node _state_r_T_38 = mux(_state_r_T_37, UInt<1>(0h0), _state_r_T_35) node _state_r_T_39 = mux(_state_r_T_37, UInt<2>(0h0), _state_r_T_36) node _state_r_T_40 = eq(_state_r_T_14, _state_r_T) node _state_r_T_41 = mux(_state_r_T_40, UInt<1>(0h1), _state_r_T_38) node _state_r_T_42 = mux(_state_r_T_40, UInt<2>(0h3), _state_r_T_39) node _state_r_T_43 = eq(_state_r_T_12, _state_r_T) node _state_r_T_44 = mux(_state_r_T_43, UInt<1>(0h1), _state_r_T_41) node _state_r_T_45 = mux(_state_r_T_43, UInt<2>(0h3), _state_r_T_42) node _state_r_T_46 = eq(_state_r_T_10, _state_r_T) node _state_r_T_47 = mux(_state_r_T_46, UInt<1>(0h1), _state_r_T_44) node _state_r_T_48 = mux(_state_r_T_46, UInt<2>(0h2), _state_r_T_45) node _state_r_T_49 = eq(_state_r_T_8, _state_r_T) node _state_r_T_50 = mux(_state_r_T_49, UInt<1>(0h1), _state_r_T_47) node _state_r_T_51 = mux(_state_r_T_49, UInt<2>(0h3), _state_r_T_48) node _state_r_T_52 = eq(_state_r_T_6, _state_r_T) node _state_r_T_53 = mux(_state_r_T_52, UInt<1>(0h1), _state_r_T_50) node _state_r_T_54 = mux(_state_r_T_52, UInt<2>(0h1), _state_r_T_51) node _state_r_T_55 = eq(_state_r_T_4, _state_r_T) node _state_r_T_56 = mux(_state_r_T_55, UInt<1>(0h1), _state_r_T_53) node _state_r_T_57 = mux(_state_r_T_55, UInt<2>(0h2), _state_r_T_54) node _state_r_T_58 = eq(_state_r_T_2, _state_r_T) node state_is_hit = mux(_state_r_T_58, UInt<1>(0h1), _state_r_T_56) node state_r_2 = mux(_state_r_T_58, UInt<2>(0h3), _state_r_T_57) wire state_coh_on_hit : { state : UInt<2>} connect state_coh_on_hit.state, state_r_2 when state_is_hit : node _state_T_3 = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _state_T_4 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _state_T_5 = or(_state_T_3, _state_T_4) node _state_T_6 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _state_T_7 = or(_state_T_5, _state_T_6) node _state_T_8 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _state_T_9 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _state_T_10 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _state_T_11 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _state_T_12 = or(_state_T_8, _state_T_9) node _state_T_13 = or(_state_T_12, _state_T_10) node _state_T_14 = or(_state_T_13, _state_T_11) node _state_T_15 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _state_T_16 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _state_T_17 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _state_T_18 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _state_T_19 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _state_T_20 = or(_state_T_15, _state_T_16) node _state_T_21 = or(_state_T_20, _state_T_17) node _state_T_22 = or(_state_T_21, _state_T_18) node _state_T_23 = or(_state_T_22, _state_T_19) node _state_T_24 = or(_state_T_14, _state_T_23) node _state_T_25 = or(_state_T_7, _state_T_24) node _state_T_26 = asUInt(reset) node _state_T_27 = eq(_state_T_26, UInt<1>(0h0)) when _state_T_27 : node _state_T_28 = eq(_state_T_25, UInt<1>(0h0)) when _state_T_28 : printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:220 assert(isWrite(io.req.uop.mem_cmd))\n") : state_printf_1 assert(clock, _state_T_25, UInt<1>(0h1), "") : state_assert_1 connect new_coh, state_coh_on_hit connect state_new_state, UInt<5>(0hc) else : connect new_coh, io.req.old_meta.coh connect state_new_state, UInt<5>(0h1) else : wire state_new_coh_meta : { state : UInt<2>} connect state_new_coh_meta.state, UInt<2>(0h0) connect new_coh, state_new_coh_meta connect state_new_state, UInt<5>(0h1) connect state, state_new_state else : node _T_13 = eq(state, UInt<5>(0h1)) when _T_13 : connect io.mem_acquire.valid, UInt<1>(0h1) node _T_14 = and(io.mem_acquire.ready, io.mem_acquire.valid) when _T_14 : connect state, UInt<5>(0h2) else : node _T_15 = eq(state, UInt<5>(0h2)) when _T_15 : connect io.mem_grant.ready, UInt<1>(0h1) node opdata = bits(io.mem_grant.bits.opcode, 0, 0) when opdata : connect io.lb_write.valid, io.mem_grant.valid else : connect io.mem_grant.ready, UInt<1>(0h1) node _T_16 = and(io.mem_grant.ready, io.mem_grant.valid) when _T_16 : node grant_had_data_opdata = bits(io.mem_grant.bits.opcode, 0, 0) connect grant_had_data, grant_had_data_opdata when refill_done : node _grantack_valid_T = bits(io.mem_grant.bits.opcode, 2, 2) node _grantack_valid_T_1 = bits(io.mem_grant.bits.opcode, 1, 1) node _grantack_valid_T_2 = eq(_grantack_valid_T_1, UInt<1>(0h0)) node _grantack_valid_T_3 = and(_grantack_valid_T, _grantack_valid_T_2) connect grantack.valid, _grantack_valid_T_3 wire grantack_bits_e : { sink : UInt<3>} connect grantack_bits_e.sink, io.mem_grant.bits.sink connect grantack.bits, grantack_bits_e node _state_T_29 = mux(grant_had_data, UInt<5>(0h3), UInt<5>(0hc)) connect state, _state_T_29 node _T_17 = eq(grant_had_data, UInt<1>(0h0)) node _T_18 = and(_T_17, req_needs_wb) node _T_19 = eq(_T_18, UInt<1>(0h0)) node _T_20 = asUInt(reset) node _T_21 = eq(_T_20, UInt<1>(0h0)) when _T_21 : node _T_22 = eq(_T_19, UInt<1>(0h0)) when _T_22 : printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:261 assert(!(!grant_had_data && req_needs_wb))\n") : printf_1 assert(clock, _T_19, UInt<1>(0h1), "") : assert_1 connect commit_line, UInt<1>(0h0) connect new_coh, coh_on_grant else : node _T_23 = eq(state, UInt<5>(0h3)) when _T_23 : node _drain_load_T = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<1>(0h0)) node _drain_load_T_1 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<5>(0h10)) node _drain_load_T_2 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h6)) node _drain_load_T_3 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h7)) node _drain_load_T_4 = or(_drain_load_T, _drain_load_T_1) node _drain_load_T_5 = or(_drain_load_T_4, _drain_load_T_2) node _drain_load_T_6 = or(_drain_load_T_5, _drain_load_T_3) node _drain_load_T_7 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h4)) node _drain_load_T_8 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h9)) node _drain_load_T_9 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0ha)) node _drain_load_T_10 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hb)) node _drain_load_T_11 = or(_drain_load_T_7, _drain_load_T_8) node _drain_load_T_12 = or(_drain_load_T_11, _drain_load_T_9) node _drain_load_T_13 = or(_drain_load_T_12, _drain_load_T_10) node _drain_load_T_14 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h8)) node _drain_load_T_15 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hc)) node _drain_load_T_16 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hd)) node _drain_load_T_17 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0he)) node _drain_load_T_18 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hf)) node _drain_load_T_19 = or(_drain_load_T_14, _drain_load_T_15) node _drain_load_T_20 = or(_drain_load_T_19, _drain_load_T_16) node _drain_load_T_21 = or(_drain_load_T_20, _drain_load_T_17) node _drain_load_T_22 = or(_drain_load_T_21, _drain_load_T_18) node _drain_load_T_23 = or(_drain_load_T_13, _drain_load_T_22) node _drain_load_T_24 = or(_drain_load_T_6, _drain_load_T_23) node _drain_load_T_25 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<1>(0h1)) node _drain_load_T_26 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<5>(0h11)) node _drain_load_T_27 = or(_drain_load_T_25, _drain_load_T_26) node _drain_load_T_28 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h7)) node _drain_load_T_29 = or(_drain_load_T_27, _drain_load_T_28) node _drain_load_T_30 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h4)) node _drain_load_T_31 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h9)) node _drain_load_T_32 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0ha)) node _drain_load_T_33 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hb)) node _drain_load_T_34 = or(_drain_load_T_30, _drain_load_T_31) node _drain_load_T_35 = or(_drain_load_T_34, _drain_load_T_32) node _drain_load_T_36 = or(_drain_load_T_35, _drain_load_T_33) node _drain_load_T_37 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h8)) node _drain_load_T_38 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hc)) node _drain_load_T_39 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hd)) node _drain_load_T_40 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0he)) node _drain_load_T_41 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hf)) node _drain_load_T_42 = or(_drain_load_T_37, _drain_load_T_38) node _drain_load_T_43 = or(_drain_load_T_42, _drain_load_T_39) node _drain_load_T_44 = or(_drain_load_T_43, _drain_load_T_40) node _drain_load_T_45 = or(_drain_load_T_44, _drain_load_T_41) node _drain_load_T_46 = or(_drain_load_T_36, _drain_load_T_45) node _drain_load_T_47 = or(_drain_load_T_29, _drain_load_T_46) node _drain_load_T_48 = eq(_drain_load_T_47, UInt<1>(0h0)) node _drain_load_T_49 = and(_drain_load_T_24, _drain_load_T_48) node _drain_load_T_50 = neq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h6)) node drain_load = and(_drain_load_T_49, _drain_load_T_50) node _rp_addr_T = bits(rpq.io.deq.bits.addr, 5, 0) node rp_addr_hi = cat(req_tag, req_idx) node rp_addr = cat(rp_addr_hi, _rp_addr_T) node _data_word_T = cat(UInt<1>(0h0), UInt<6>(0h0)) node data_word = dshr(io.lb_resp, _data_word_T) node _T_24 = bits(rpq.io.deq.bits.addr, 5, 0) node hi = cat(req_tag, req_idx) node _T_25 = cat(hi, _T_24) wire size : UInt<2> connect size, rpq.io.deq.bits.uop.mem_size node _rpq_io_deq_ready_T = and(io.resp.ready, drain_load) connect rpq.io.deq.ready, _rpq_io_deq_ready_T node _io_lb_read_offset_T_1 = shr(rpq.io.deq.bits.addr, 3) connect io.lb_read.offset, _io_lb_read_offset_T_1 node _io_resp_valid_T = and(rpq.io.deq.valid, drain_load) connect io.resp.valid, _io_resp_valid_T node _io_resp_bits_data_shifted_T = bits(_T_25, 2, 2) node _io_resp_bits_data_shifted_T_1 = bits(data_word, 63, 32) node _io_resp_bits_data_shifted_T_2 = bits(data_word, 31, 0) node io_resp_bits_data_shifted = mux(_io_resp_bits_data_shifted_T, _io_resp_bits_data_shifted_T_1, _io_resp_bits_data_shifted_T_2) node io_resp_bits_data_doZero = and(UInt<1>(0h0), UInt<1>(0h0)) node io_resp_bits_data_zeroed = mux(io_resp_bits_data_doZero, UInt<1>(0h0), io_resp_bits_data_shifted) node _io_resp_bits_data_T = eq(size, UInt<2>(0h2)) node _io_resp_bits_data_T_1 = or(_io_resp_bits_data_T, io_resp_bits_data_doZero) node _io_resp_bits_data_T_2 = bits(io_resp_bits_data_zeroed, 31, 31) node _io_resp_bits_data_T_3 = and(rpq.io.deq.bits.uop.mem_signed, _io_resp_bits_data_T_2) node _io_resp_bits_data_T_4 = mux(_io_resp_bits_data_T_3, UInt<32>(0hffffffff), UInt<32>(0h0)) node _io_resp_bits_data_T_5 = bits(data_word, 63, 32) node _io_resp_bits_data_T_6 = mux(_io_resp_bits_data_T_1, _io_resp_bits_data_T_4, _io_resp_bits_data_T_5) node _io_resp_bits_data_T_7 = cat(_io_resp_bits_data_T_6, io_resp_bits_data_zeroed) node _io_resp_bits_data_shifted_T_3 = bits(_T_25, 1, 1) node _io_resp_bits_data_shifted_T_4 = bits(_io_resp_bits_data_T_7, 31, 16) node _io_resp_bits_data_shifted_T_5 = bits(_io_resp_bits_data_T_7, 15, 0) node io_resp_bits_data_shifted_1 = mux(_io_resp_bits_data_shifted_T_3, _io_resp_bits_data_shifted_T_4, _io_resp_bits_data_shifted_T_5) node io_resp_bits_data_doZero_1 = and(UInt<1>(0h0), UInt<1>(0h0)) node io_resp_bits_data_zeroed_1 = mux(io_resp_bits_data_doZero_1, UInt<1>(0h0), io_resp_bits_data_shifted_1) node _io_resp_bits_data_T_8 = eq(size, UInt<1>(0h1)) node _io_resp_bits_data_T_9 = or(_io_resp_bits_data_T_8, io_resp_bits_data_doZero_1) node _io_resp_bits_data_T_10 = bits(io_resp_bits_data_zeroed_1, 15, 15) node _io_resp_bits_data_T_11 = and(rpq.io.deq.bits.uop.mem_signed, _io_resp_bits_data_T_10) node _io_resp_bits_data_T_12 = mux(_io_resp_bits_data_T_11, UInt<48>(0hffffffffffff), UInt<48>(0h0)) node _io_resp_bits_data_T_13 = bits(_io_resp_bits_data_T_7, 63, 16) node _io_resp_bits_data_T_14 = mux(_io_resp_bits_data_T_9, _io_resp_bits_data_T_12, _io_resp_bits_data_T_13) node _io_resp_bits_data_T_15 = cat(_io_resp_bits_data_T_14, io_resp_bits_data_zeroed_1) node _io_resp_bits_data_shifted_T_6 = bits(_T_25, 0, 0) node _io_resp_bits_data_shifted_T_7 = bits(_io_resp_bits_data_T_15, 15, 8) node _io_resp_bits_data_shifted_T_8 = bits(_io_resp_bits_data_T_15, 7, 0) node io_resp_bits_data_shifted_2 = mux(_io_resp_bits_data_shifted_T_6, _io_resp_bits_data_shifted_T_7, _io_resp_bits_data_shifted_T_8) node io_resp_bits_data_doZero_2 = and(UInt<1>(0h1), UInt<1>(0h0)) node io_resp_bits_data_zeroed_2 = mux(io_resp_bits_data_doZero_2, UInt<1>(0h0), io_resp_bits_data_shifted_2) node _io_resp_bits_data_T_16 = eq(size, UInt<1>(0h0)) node _io_resp_bits_data_T_17 = or(_io_resp_bits_data_T_16, io_resp_bits_data_doZero_2) node _io_resp_bits_data_T_18 = bits(io_resp_bits_data_zeroed_2, 7, 7) node _io_resp_bits_data_T_19 = and(rpq.io.deq.bits.uop.mem_signed, _io_resp_bits_data_T_18) node _io_resp_bits_data_T_20 = mux(_io_resp_bits_data_T_19, UInt<56>(0hffffffffffffff), UInt<56>(0h0)) node _io_resp_bits_data_T_21 = bits(_io_resp_bits_data_T_15, 63, 8) node _io_resp_bits_data_T_22 = mux(_io_resp_bits_data_T_17, _io_resp_bits_data_T_20, _io_resp_bits_data_T_21) node _io_resp_bits_data_T_23 = cat(_io_resp_bits_data_T_22, io_resp_bits_data_zeroed_2) connect io.resp.bits.data, _io_resp_bits_data_T_23 connect io.resp.bits.is_hella, rpq.io.deq.bits.is_hella node _T_26 = and(rpq.io.deq.ready, rpq.io.deq.valid) when _T_26 : connect commit_line, UInt<1>(0h1) else : node _T_27 = eq(commit_line, UInt<1>(0h0)) node _T_28 = and(rpq.io.empty, _T_27) when _T_28 : node _T_29 = and(rpq.io.enq.ready, rpq.io.enq.valid) node _T_30 = eq(_T_29, UInt<1>(0h0)) when _T_30 : connect state, UInt<5>(0he) connect finish_to_prefetch, UInt<1>(0h0) else : node _T_31 = eq(drain_load, UInt<1>(0h0)) node _T_32 = and(rpq.io.deq.valid, _T_31) node _T_33 = or(rpq.io.empty, _T_32) when _T_33 : connect io.commit_val, UInt<1>(0h1) connect state, UInt<5>(0h4) else : node _T_34 = eq(state, UInt<5>(0h4)) when _T_34 : node _io_meta_read_valid_T = eq(io.prober_state.valid, UInt<1>(0h0)) node _io_meta_read_valid_T_1 = eq(grantack.valid, UInt<1>(0h0)) node _io_meta_read_valid_T_2 = or(_io_meta_read_valid_T, _io_meta_read_valid_T_1) node _io_meta_read_valid_T_3 = bits(io.prober_state.bits, 9, 6) node _io_meta_read_valid_T_4 = neq(_io_meta_read_valid_T_3, req_idx) node _io_meta_read_valid_T_5 = or(_io_meta_read_valid_T_2, _io_meta_read_valid_T_4) connect io.meta_read.valid, _io_meta_read_valid_T_5 node _T_35 = and(io.meta_read.ready, io.meta_read.valid) when _T_35 : connect state, UInt<5>(0h5) else : node _T_36 = eq(state, UInt<5>(0h5)) when _T_36 : connect state, UInt<5>(0h6) else : node _T_37 = eq(state, UInt<5>(0h6)) when _T_37 : node _needs_wb_r_T = eq(UInt<5>(0h10), UInt<5>(0h10)) node _needs_wb_r_T_1 = mux(_needs_wb_r_T, UInt<2>(0h2), UInt<2>(0h2)) node _needs_wb_r_T_2 = eq(UInt<5>(0h12), UInt<5>(0h10)) node _needs_wb_r_T_3 = mux(_needs_wb_r_T_2, UInt<2>(0h1), _needs_wb_r_T_1) node _needs_wb_r_T_4 = eq(UInt<5>(0h13), UInt<5>(0h10)) node _needs_wb_r_T_5 = mux(_needs_wb_r_T_4, UInt<2>(0h0), _needs_wb_r_T_3) node _needs_wb_r_T_6 = cat(_needs_wb_r_T_5, io.meta_resp.bits.coh.state) node _needs_wb_r_T_7 = cat(UInt<2>(0h0), UInt<2>(0h3)) node _needs_wb_r_T_8 = cat(UInt<2>(0h0), UInt<2>(0h2)) node _needs_wb_r_T_9 = cat(UInt<2>(0h0), UInt<2>(0h1)) node _needs_wb_r_T_10 = cat(UInt<2>(0h0), UInt<2>(0h0)) node _needs_wb_r_T_11 = cat(UInt<2>(0h1), UInt<2>(0h3)) node _needs_wb_r_T_12 = cat(UInt<2>(0h1), UInt<2>(0h2)) node _needs_wb_r_T_13 = cat(UInt<2>(0h1), UInt<2>(0h1)) node _needs_wb_r_T_14 = cat(UInt<2>(0h1), UInt<2>(0h0)) node _needs_wb_r_T_15 = cat(UInt<2>(0h2), UInt<2>(0h3)) node _needs_wb_r_T_16 = cat(UInt<2>(0h2), UInt<2>(0h2)) node _needs_wb_r_T_17 = cat(UInt<2>(0h2), UInt<2>(0h1)) node _needs_wb_r_T_18 = cat(UInt<2>(0h2), UInt<2>(0h0)) node _needs_wb_r_T_19 = eq(_needs_wb_r_T_18, _needs_wb_r_T_6) node _needs_wb_r_T_20 = mux(_needs_wb_r_T_19, UInt<1>(0h0), UInt<1>(0h0)) node _needs_wb_r_T_21 = mux(_needs_wb_r_T_19, UInt<3>(0h5), UInt<1>(0h0)) node _needs_wb_r_T_22 = mux(_needs_wb_r_T_19, UInt<2>(0h0), UInt<1>(0h0)) node _needs_wb_r_T_23 = eq(_needs_wb_r_T_17, _needs_wb_r_T_6) node _needs_wb_r_T_24 = mux(_needs_wb_r_T_23, UInt<1>(0h0), _needs_wb_r_T_20) node _needs_wb_r_T_25 = mux(_needs_wb_r_T_23, UInt<3>(0h2), _needs_wb_r_T_21) node _needs_wb_r_T_26 = mux(_needs_wb_r_T_23, UInt<2>(0h0), _needs_wb_r_T_22) node _needs_wb_r_T_27 = eq(_needs_wb_r_T_16, _needs_wb_r_T_6) node _needs_wb_r_T_28 = mux(_needs_wb_r_T_27, UInt<1>(0h0), _needs_wb_r_T_24) node _needs_wb_r_T_29 = mux(_needs_wb_r_T_27, UInt<3>(0h1), _needs_wb_r_T_25) node _needs_wb_r_T_30 = mux(_needs_wb_r_T_27, UInt<2>(0h0), _needs_wb_r_T_26) node _needs_wb_r_T_31 = eq(_needs_wb_r_T_15, _needs_wb_r_T_6) node _needs_wb_r_T_32 = mux(_needs_wb_r_T_31, UInt<1>(0h1), _needs_wb_r_T_28) node _needs_wb_r_T_33 = mux(_needs_wb_r_T_31, UInt<3>(0h1), _needs_wb_r_T_29) node _needs_wb_r_T_34 = mux(_needs_wb_r_T_31, UInt<2>(0h0), _needs_wb_r_T_30) node _needs_wb_r_T_35 = eq(_needs_wb_r_T_14, _needs_wb_r_T_6) node _needs_wb_r_T_36 = mux(_needs_wb_r_T_35, UInt<1>(0h0), _needs_wb_r_T_32) node _needs_wb_r_T_37 = mux(_needs_wb_r_T_35, UInt<3>(0h5), _needs_wb_r_T_33) node _needs_wb_r_T_38 = mux(_needs_wb_r_T_35, UInt<2>(0h0), _needs_wb_r_T_34) node _needs_wb_r_T_39 = eq(_needs_wb_r_T_13, _needs_wb_r_T_6) node _needs_wb_r_T_40 = mux(_needs_wb_r_T_39, UInt<1>(0h0), _needs_wb_r_T_36) node _needs_wb_r_T_41 = mux(_needs_wb_r_T_39, UInt<3>(0h4), _needs_wb_r_T_37) node _needs_wb_r_T_42 = mux(_needs_wb_r_T_39, UInt<2>(0h1), _needs_wb_r_T_38) node _needs_wb_r_T_43 = eq(_needs_wb_r_T_12, _needs_wb_r_T_6) node _needs_wb_r_T_44 = mux(_needs_wb_r_T_43, UInt<1>(0h0), _needs_wb_r_T_40) node _needs_wb_r_T_45 = mux(_needs_wb_r_T_43, UInt<3>(0h0), _needs_wb_r_T_41) node _needs_wb_r_T_46 = mux(_needs_wb_r_T_43, UInt<2>(0h1), _needs_wb_r_T_42) node _needs_wb_r_T_47 = eq(_needs_wb_r_T_11, _needs_wb_r_T_6) node _needs_wb_r_T_48 = mux(_needs_wb_r_T_47, UInt<1>(0h1), _needs_wb_r_T_44) node _needs_wb_r_T_49 = mux(_needs_wb_r_T_47, UInt<3>(0h0), _needs_wb_r_T_45) node _needs_wb_r_T_50 = mux(_needs_wb_r_T_47, UInt<2>(0h1), _needs_wb_r_T_46) node _needs_wb_r_T_51 = eq(_needs_wb_r_T_10, _needs_wb_r_T_6) node _needs_wb_r_T_52 = mux(_needs_wb_r_T_51, UInt<1>(0h0), _needs_wb_r_T_48) node _needs_wb_r_T_53 = mux(_needs_wb_r_T_51, UInt<3>(0h5), _needs_wb_r_T_49) node _needs_wb_r_T_54 = mux(_needs_wb_r_T_51, UInt<2>(0h0), _needs_wb_r_T_50) node _needs_wb_r_T_55 = eq(_needs_wb_r_T_9, _needs_wb_r_T_6) node _needs_wb_r_T_56 = mux(_needs_wb_r_T_55, UInt<1>(0h0), _needs_wb_r_T_52) node _needs_wb_r_T_57 = mux(_needs_wb_r_T_55, UInt<3>(0h4), _needs_wb_r_T_53) node _needs_wb_r_T_58 = mux(_needs_wb_r_T_55, UInt<2>(0h1), _needs_wb_r_T_54) node _needs_wb_r_T_59 = eq(_needs_wb_r_T_8, _needs_wb_r_T_6) node _needs_wb_r_T_60 = mux(_needs_wb_r_T_59, UInt<1>(0h0), _needs_wb_r_T_56) node _needs_wb_r_T_61 = mux(_needs_wb_r_T_59, UInt<3>(0h3), _needs_wb_r_T_57) node _needs_wb_r_T_62 = mux(_needs_wb_r_T_59, UInt<2>(0h2), _needs_wb_r_T_58) node _needs_wb_r_T_63 = eq(_needs_wb_r_T_7, _needs_wb_r_T_6) node needs_wb = mux(_needs_wb_r_T_63, UInt<1>(0h1), _needs_wb_r_T_60) node needs_wb_r_2 = mux(_needs_wb_r_T_63, UInt<3>(0h3), _needs_wb_r_T_61) node needs_wb_r_3 = mux(_needs_wb_r_T_63, UInt<2>(0h2), _needs_wb_r_T_62) wire needs_wb_meta : { state : UInt<2>} connect needs_wb_meta.state, needs_wb_r_3 node _state_T_30 = eq(io.meta_resp.valid, UInt<1>(0h0)) node _state_T_31 = mux(needs_wb, UInt<5>(0h7), UInt<5>(0hb)) node _state_T_32 = mux(_state_T_30, UInt<5>(0h4), _state_T_31) connect state, _state_T_32 else : node _T_38 = eq(state, UInt<5>(0h7)) when _T_38 : connect io.meta_write.valid, UInt<1>(0h1) node _T_39 = and(io.meta_write.ready, io.meta_write.valid) when _T_39 : connect state, UInt<5>(0h9) else : node _T_40 = eq(state, UInt<5>(0h9)) when _T_40 : connect io.wb_req.valid, UInt<1>(0h1) node _T_41 = and(io.wb_req.ready, io.wb_req.valid) when _T_41 : connect state, UInt<5>(0ha) else : node _T_42 = eq(state, UInt<5>(0ha)) when _T_42 : when io.wb_resp : connect state, UInt<5>(0hb) else : node _T_43 = eq(state, UInt<5>(0hb)) when _T_43 : connect io.lb_read.offset, refill_ctr connect io.refill.valid, UInt<1>(0h1) node _T_44 = and(io.refill.ready, io.refill.valid) when _T_44 : node _refill_ctr_T = add(refill_ctr, UInt<1>(0h1)) node _refill_ctr_T_1 = tail(_refill_ctr_T, 1) connect refill_ctr, _refill_ctr_T_1 node _T_45 = eq(refill_ctr, UInt<3>(0h7)) when _T_45 : connect state, UInt<5>(0hc) else : node _T_46 = eq(state, UInt<5>(0hc)) when _T_46 : connect io.replay.bits, rpq.io.deq.bits connect io.replay.valid, rpq.io.deq.valid connect rpq.io.deq.ready, io.replay.ready connect io.replay.bits.way_en, req.way_en node _io_replay_bits_addr_T = bits(rpq.io.deq.bits.addr, 5, 0) node io_replay_bits_addr_hi = cat(req_tag, req_idx) node _io_replay_bits_addr_T_1 = cat(io_replay_bits_addr_hi, _io_replay_bits_addr_T) connect io.replay.bits.addr, _io_replay_bits_addr_T_1 node _T_47 = and(io.replay.ready, io.replay.valid) node _T_48 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<1>(0h1)) node _T_49 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<5>(0h11)) node _T_50 = or(_T_48, _T_49) node _T_51 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h7)) node _T_52 = or(_T_50, _T_51) node _T_53 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h4)) node _T_54 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h9)) node _T_55 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0ha)) node _T_56 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hb)) node _T_57 = or(_T_53, _T_54) node _T_58 = or(_T_57, _T_55) node _T_59 = or(_T_58, _T_56) node _T_60 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h8)) node _T_61 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hc)) node _T_62 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hd)) node _T_63 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0he)) node _T_64 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hf)) node _T_65 = or(_T_60, _T_61) node _T_66 = or(_T_65, _T_62) node _T_67 = or(_T_66, _T_63) node _T_68 = or(_T_67, _T_64) node _T_69 = or(_T_59, _T_68) node _T_70 = or(_T_52, _T_69) node _T_71 = and(_T_47, _T_70) when _T_71 : node _r_c_cat_T = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<1>(0h1)) node _r_c_cat_T_1 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<5>(0h11)) node _r_c_cat_T_2 = or(_r_c_cat_T, _r_c_cat_T_1) node _r_c_cat_T_3 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h7)) node _r_c_cat_T_4 = or(_r_c_cat_T_2, _r_c_cat_T_3) node _r_c_cat_T_5 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h4)) node _r_c_cat_T_6 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h9)) node _r_c_cat_T_7 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0ha)) node _r_c_cat_T_8 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hb)) node _r_c_cat_T_9 = or(_r_c_cat_T_5, _r_c_cat_T_6) node _r_c_cat_T_10 = or(_r_c_cat_T_9, _r_c_cat_T_7) node _r_c_cat_T_11 = or(_r_c_cat_T_10, _r_c_cat_T_8) node _r_c_cat_T_12 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h8)) node _r_c_cat_T_13 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hc)) node _r_c_cat_T_14 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hd)) node _r_c_cat_T_15 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0he)) node _r_c_cat_T_16 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hf)) node _r_c_cat_T_17 = or(_r_c_cat_T_12, _r_c_cat_T_13) node _r_c_cat_T_18 = or(_r_c_cat_T_17, _r_c_cat_T_14) node _r_c_cat_T_19 = or(_r_c_cat_T_18, _r_c_cat_T_15) node _r_c_cat_T_20 = or(_r_c_cat_T_19, _r_c_cat_T_16) node _r_c_cat_T_21 = or(_r_c_cat_T_11, _r_c_cat_T_20) node _r_c_cat_T_22 = or(_r_c_cat_T_4, _r_c_cat_T_21) node _r_c_cat_T_23 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<1>(0h1)) node _r_c_cat_T_24 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<5>(0h11)) node _r_c_cat_T_25 = or(_r_c_cat_T_23, _r_c_cat_T_24) node _r_c_cat_T_26 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h7)) node _r_c_cat_T_27 = or(_r_c_cat_T_25, _r_c_cat_T_26) node _r_c_cat_T_28 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h4)) node _r_c_cat_T_29 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h9)) node _r_c_cat_T_30 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0ha)) node _r_c_cat_T_31 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hb)) node _r_c_cat_T_32 = or(_r_c_cat_T_28, _r_c_cat_T_29) node _r_c_cat_T_33 = or(_r_c_cat_T_32, _r_c_cat_T_30) node _r_c_cat_T_34 = or(_r_c_cat_T_33, _r_c_cat_T_31) node _r_c_cat_T_35 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h8)) node _r_c_cat_T_36 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hc)) node _r_c_cat_T_37 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hd)) node _r_c_cat_T_38 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0he)) node _r_c_cat_T_39 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hf)) node _r_c_cat_T_40 = or(_r_c_cat_T_35, _r_c_cat_T_36) node _r_c_cat_T_41 = or(_r_c_cat_T_40, _r_c_cat_T_37) node _r_c_cat_T_42 = or(_r_c_cat_T_41, _r_c_cat_T_38) node _r_c_cat_T_43 = or(_r_c_cat_T_42, _r_c_cat_T_39) node _r_c_cat_T_44 = or(_r_c_cat_T_34, _r_c_cat_T_43) node _r_c_cat_T_45 = or(_r_c_cat_T_27, _r_c_cat_T_44) node _r_c_cat_T_46 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<2>(0h3)) node _r_c_cat_T_47 = or(_r_c_cat_T_45, _r_c_cat_T_46) node _r_c_cat_T_48 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h6)) node _r_c_cat_T_49 = or(_r_c_cat_T_47, _r_c_cat_T_48) node r_c = cat(_r_c_cat_T_22, _r_c_cat_T_49) node _r_T_64 = cat(r_c, new_coh.state) node _r_T_65 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r_T_66 = cat(_r_T_65, UInt<2>(0h3)) node _r_T_67 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r_T_68 = cat(_r_T_67, UInt<2>(0h2)) node _r_T_69 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r_T_70 = cat(_r_T_69, UInt<2>(0h1)) node _r_T_71 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r_T_72 = cat(_r_T_71, UInt<2>(0h3)) node _r_T_73 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r_T_74 = cat(_r_T_73, UInt<2>(0h2)) node _r_T_75 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r_T_76 = cat(_r_T_75, UInt<2>(0h3)) node _r_T_77 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r_T_78 = cat(_r_T_77, UInt<2>(0h2)) node _r_T_79 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r_T_80 = cat(_r_T_79, UInt<2>(0h0)) node _r_T_81 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r_T_82 = cat(_r_T_81, UInt<2>(0h1)) node _r_T_83 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r_T_84 = cat(_r_T_83, UInt<2>(0h0)) node _r_T_85 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r_T_86 = cat(_r_T_85, UInt<2>(0h1)) node _r_T_87 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r_T_88 = cat(_r_T_87, UInt<2>(0h0)) node _r_T_89 = eq(_r_T_88, _r_T_64) node _r_T_90 = mux(_r_T_89, UInt<1>(0h0), UInt<1>(0h0)) node _r_T_91 = mux(_r_T_89, UInt<2>(0h1), UInt<1>(0h0)) node _r_T_92 = eq(_r_T_86, _r_T_64) node _r_T_93 = mux(_r_T_92, UInt<1>(0h0), _r_T_90) node _r_T_94 = mux(_r_T_92, UInt<2>(0h2), _r_T_91) node _r_T_95 = eq(_r_T_84, _r_T_64) node _r_T_96 = mux(_r_T_95, UInt<1>(0h0), _r_T_93) node _r_T_97 = mux(_r_T_95, UInt<2>(0h1), _r_T_94) node _r_T_98 = eq(_r_T_82, _r_T_64) node _r_T_99 = mux(_r_T_98, UInt<1>(0h0), _r_T_96) node _r_T_100 = mux(_r_T_98, UInt<2>(0h2), _r_T_97) node _r_T_101 = eq(_r_T_80, _r_T_64) node _r_T_102 = mux(_r_T_101, UInt<1>(0h0), _r_T_99) node _r_T_103 = mux(_r_T_101, UInt<2>(0h0), _r_T_100) node _r_T_104 = eq(_r_T_78, _r_T_64) node _r_T_105 = mux(_r_T_104, UInt<1>(0h1), _r_T_102) node _r_T_106 = mux(_r_T_104, UInt<2>(0h3), _r_T_103) node _r_T_107 = eq(_r_T_76, _r_T_64) node _r_T_108 = mux(_r_T_107, UInt<1>(0h1), _r_T_105) node _r_T_109 = mux(_r_T_107, UInt<2>(0h3), _r_T_106) node _r_T_110 = eq(_r_T_74, _r_T_64) node _r_T_111 = mux(_r_T_110, UInt<1>(0h1), _r_T_108) node _r_T_112 = mux(_r_T_110, UInt<2>(0h2), _r_T_109) node _r_T_113 = eq(_r_T_72, _r_T_64) node _r_T_114 = mux(_r_T_113, UInt<1>(0h1), _r_T_111) node _r_T_115 = mux(_r_T_113, UInt<2>(0h3), _r_T_112) node _r_T_116 = eq(_r_T_70, _r_T_64) node _r_T_117 = mux(_r_T_116, UInt<1>(0h1), _r_T_114) node _r_T_118 = mux(_r_T_116, UInt<2>(0h1), _r_T_115) node _r_T_119 = eq(_r_T_68, _r_T_64) node _r_T_120 = mux(_r_T_119, UInt<1>(0h1), _r_T_117) node _r_T_121 = mux(_r_T_119, UInt<2>(0h2), _r_T_118) node _r_T_122 = eq(_r_T_66, _r_T_64) node is_hit = mux(_r_T_122, UInt<1>(0h1), _r_T_120) node r_2_1 = mux(_r_T_122, UInt<2>(0h3), _r_T_121) wire coh_on_hit : { state : UInt<2>} connect coh_on_hit.state, r_2_1 node _T_72 = asUInt(reset) node _T_73 = eq(_T_72, UInt<1>(0h0)) when _T_73 : node _T_74 = eq(is_hit, UInt<1>(0h0)) when _T_74 : printf(clock, UInt<1>(0h1), "Assertion failed: We still don't have permissions for this store\n at mshrs.scala:345 assert(is_hit, \"We still don't have permissions for this store\")\n") : printf_2 assert(clock, is_hit, UInt<1>(0h1), "") : assert_2 connect new_coh, coh_on_hit node _T_75 = eq(rpq.io.enq.valid, UInt<1>(0h0)) node _T_76 = and(rpq.io.empty, _T_75) when _T_76 : connect state, UInt<5>(0hd) else : node _T_77 = eq(state, UInt<5>(0hd)) when _T_77 : connect io.meta_write.valid, UInt<1>(0h1) connect io.meta_write.bits.idx, req_idx connect io.meta_write.bits.data.coh, new_coh connect io.meta_write.bits.data.tag, req_tag connect io.meta_write.bits.way_en, req.way_en node _T_78 = and(io.meta_write.ready, io.meta_write.valid) when _T_78 : connect state, UInt<5>(0he) connect finish_to_prefetch, UInt<1>(0h0) else : node _T_79 = eq(state, UInt<5>(0he)) when _T_79 : connect io.mem_finish.valid, grantack.valid node _T_80 = and(io.mem_finish.ready, io.mem_finish.valid) node _T_81 = eq(grantack.valid, UInt<1>(0h0)) node _T_82 = or(_T_80, _T_81) when _T_82 : connect grantack.valid, UInt<1>(0h0) connect state, UInt<5>(0hf) else : node _T_83 = eq(state, UInt<5>(0hf)) when _T_83 : node _state_T_33 = mux(finish_to_prefetch, UInt<5>(0h11), UInt<5>(0h0)) connect state, _state_T_33 else : node _T_84 = eq(state, UInt<5>(0h11)) when _T_84 : connect io.req_pri_rdy, UInt<1>(0h1) node _T_85 = eq(io.req_sec_rdy, UInt<1>(0h0)) node _T_86 = and(io.req_sec_val, _T_85) node _T_87 = or(_T_86, io.clear_prefetch) when _T_87 : connect state, UInt<5>(0h0) else : node _T_88 = and(io.req_sec_val, io.req_sec_rdy) when _T_88 : node _r_c_cat_T_50 = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _r_c_cat_T_51 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _r_c_cat_T_52 = or(_r_c_cat_T_50, _r_c_cat_T_51) node _r_c_cat_T_53 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _r_c_cat_T_54 = or(_r_c_cat_T_52, _r_c_cat_T_53) node _r_c_cat_T_55 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _r_c_cat_T_56 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _r_c_cat_T_57 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _r_c_cat_T_58 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _r_c_cat_T_59 = or(_r_c_cat_T_55, _r_c_cat_T_56) node _r_c_cat_T_60 = or(_r_c_cat_T_59, _r_c_cat_T_57) node _r_c_cat_T_61 = or(_r_c_cat_T_60, _r_c_cat_T_58) node _r_c_cat_T_62 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _r_c_cat_T_63 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _r_c_cat_T_64 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _r_c_cat_T_65 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _r_c_cat_T_66 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _r_c_cat_T_67 = or(_r_c_cat_T_62, _r_c_cat_T_63) node _r_c_cat_T_68 = or(_r_c_cat_T_67, _r_c_cat_T_64) node _r_c_cat_T_69 = or(_r_c_cat_T_68, _r_c_cat_T_65) node _r_c_cat_T_70 = or(_r_c_cat_T_69, _r_c_cat_T_66) node _r_c_cat_T_71 = or(_r_c_cat_T_61, _r_c_cat_T_70) node _r_c_cat_T_72 = or(_r_c_cat_T_54, _r_c_cat_T_71) node _r_c_cat_T_73 = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _r_c_cat_T_74 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _r_c_cat_T_75 = or(_r_c_cat_T_73, _r_c_cat_T_74) node _r_c_cat_T_76 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _r_c_cat_T_77 = or(_r_c_cat_T_75, _r_c_cat_T_76) node _r_c_cat_T_78 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _r_c_cat_T_79 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _r_c_cat_T_80 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _r_c_cat_T_81 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _r_c_cat_T_82 = or(_r_c_cat_T_78, _r_c_cat_T_79) node _r_c_cat_T_83 = or(_r_c_cat_T_82, _r_c_cat_T_80) node _r_c_cat_T_84 = or(_r_c_cat_T_83, _r_c_cat_T_81) node _r_c_cat_T_85 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _r_c_cat_T_86 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _r_c_cat_T_87 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _r_c_cat_T_88 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _r_c_cat_T_89 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _r_c_cat_T_90 = or(_r_c_cat_T_85, _r_c_cat_T_86) node _r_c_cat_T_91 = or(_r_c_cat_T_90, _r_c_cat_T_87) node _r_c_cat_T_92 = or(_r_c_cat_T_91, _r_c_cat_T_88) node _r_c_cat_T_93 = or(_r_c_cat_T_92, _r_c_cat_T_89) node _r_c_cat_T_94 = or(_r_c_cat_T_84, _r_c_cat_T_93) node _r_c_cat_T_95 = or(_r_c_cat_T_77, _r_c_cat_T_94) node _r_c_cat_T_96 = eq(io.req.uop.mem_cmd, UInt<2>(0h3)) node _r_c_cat_T_97 = or(_r_c_cat_T_95, _r_c_cat_T_96) node _r_c_cat_T_98 = eq(io.req.uop.mem_cmd, UInt<3>(0h6)) node _r_c_cat_T_99 = or(_r_c_cat_T_97, _r_c_cat_T_98) node r_c_1 = cat(_r_c_cat_T_72, _r_c_cat_T_99) node _r_T_123 = cat(r_c_1, new_coh.state) node _r_T_124 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r_T_125 = cat(_r_T_124, UInt<2>(0h3)) node _r_T_126 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r_T_127 = cat(_r_T_126, UInt<2>(0h2)) node _r_T_128 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r_T_129 = cat(_r_T_128, UInt<2>(0h1)) node _r_T_130 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r_T_131 = cat(_r_T_130, UInt<2>(0h3)) node _r_T_132 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r_T_133 = cat(_r_T_132, UInt<2>(0h2)) node _r_T_134 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r_T_135 = cat(_r_T_134, UInt<2>(0h3)) node _r_T_136 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r_T_137 = cat(_r_T_136, UInt<2>(0h2)) node _r_T_138 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r_T_139 = cat(_r_T_138, UInt<2>(0h0)) node _r_T_140 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r_T_141 = cat(_r_T_140, UInt<2>(0h1)) node _r_T_142 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r_T_143 = cat(_r_T_142, UInt<2>(0h0)) node _r_T_144 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r_T_145 = cat(_r_T_144, UInt<2>(0h1)) node _r_T_146 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r_T_147 = cat(_r_T_146, UInt<2>(0h0)) node _r_T_148 = eq(_r_T_147, _r_T_123) node _r_T_149 = mux(_r_T_148, UInt<1>(0h0), UInt<1>(0h0)) node _r_T_150 = mux(_r_T_148, UInt<2>(0h1), UInt<1>(0h0)) node _r_T_151 = eq(_r_T_145, _r_T_123) node _r_T_152 = mux(_r_T_151, UInt<1>(0h0), _r_T_149) node _r_T_153 = mux(_r_T_151, UInt<2>(0h2), _r_T_150) node _r_T_154 = eq(_r_T_143, _r_T_123) node _r_T_155 = mux(_r_T_154, UInt<1>(0h0), _r_T_152) node _r_T_156 = mux(_r_T_154, UInt<2>(0h1), _r_T_153) node _r_T_157 = eq(_r_T_141, _r_T_123) node _r_T_158 = mux(_r_T_157, UInt<1>(0h0), _r_T_155) node _r_T_159 = mux(_r_T_157, UInt<2>(0h2), _r_T_156) node _r_T_160 = eq(_r_T_139, _r_T_123) node _r_T_161 = mux(_r_T_160, UInt<1>(0h0), _r_T_158) node _r_T_162 = mux(_r_T_160, UInt<2>(0h0), _r_T_159) node _r_T_163 = eq(_r_T_137, _r_T_123) node _r_T_164 = mux(_r_T_163, UInt<1>(0h1), _r_T_161) node _r_T_165 = mux(_r_T_163, UInt<2>(0h3), _r_T_162) node _r_T_166 = eq(_r_T_135, _r_T_123) node _r_T_167 = mux(_r_T_166, UInt<1>(0h1), _r_T_164) node _r_T_168 = mux(_r_T_166, UInt<2>(0h3), _r_T_165) node _r_T_169 = eq(_r_T_133, _r_T_123) node _r_T_170 = mux(_r_T_169, UInt<1>(0h1), _r_T_167) node _r_T_171 = mux(_r_T_169, UInt<2>(0h2), _r_T_168) node _r_T_172 = eq(_r_T_131, _r_T_123) node _r_T_173 = mux(_r_T_172, UInt<1>(0h1), _r_T_170) node _r_T_174 = mux(_r_T_172, UInt<2>(0h3), _r_T_171) node _r_T_175 = eq(_r_T_129, _r_T_123) node _r_T_176 = mux(_r_T_175, UInt<1>(0h1), _r_T_173) node _r_T_177 = mux(_r_T_175, UInt<2>(0h1), _r_T_174) node _r_T_178 = eq(_r_T_127, _r_T_123) node _r_T_179 = mux(_r_T_178, UInt<1>(0h1), _r_T_176) node _r_T_180 = mux(_r_T_178, UInt<2>(0h2), _r_T_177) node _r_T_181 = eq(_r_T_125, _r_T_123) node is_hit_1 = mux(_r_T_181, UInt<1>(0h1), _r_T_179) node r_2_2 = mux(_r_T_181, UInt<2>(0h3), _r_T_180) wire coh_on_hit_1 : { state : UInt<2>} connect coh_on_hit_1.state, r_2_2 when is_hit_1 : connect new_coh, coh_on_hit_1 connect state, UInt<5>(0h4) else : wire new_coh_meta_1 : { state : UInt<2>} connect new_coh_meta_1.state, UInt<2>(0h0) connect new_coh, new_coh_meta_1 connect state, UInt<5>(0h1) else : node _T_89 = and(io.req_pri_val, io.req_pri_rdy) when _T_89 : connect grant_had_data, UInt<1>(0h0) wire state_new_state_1 : UInt connect state_new_state_1, state connect grantack.valid, UInt<1>(0h0) connect refill_ctr, UInt<1>(0h0) node _state_T_34 = asUInt(reset) node _state_T_35 = eq(_state_T_34, UInt<1>(0h0)) when _state_T_35 : node _state_T_36 = eq(rpq.io.enq.ready, UInt<1>(0h0)) when _state_T_36 : printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:213 assert(rpq.io.enq.ready)\n") : state_printf_2 assert(clock, rpq.io.enq.ready, UInt<1>(0h1), "") : state_assert_2 connect req, io.req node _state_req_needs_wb_r_T_64 = eq(UInt<5>(0h10), UInt<5>(0h10)) node _state_req_needs_wb_r_T_65 = mux(_state_req_needs_wb_r_T_64, UInt<2>(0h2), UInt<2>(0h2)) node _state_req_needs_wb_r_T_66 = eq(UInt<5>(0h12), UInt<5>(0h10)) node _state_req_needs_wb_r_T_67 = mux(_state_req_needs_wb_r_T_66, UInt<2>(0h1), _state_req_needs_wb_r_T_65) node _state_req_needs_wb_r_T_68 = eq(UInt<5>(0h13), UInt<5>(0h10)) node _state_req_needs_wb_r_T_69 = mux(_state_req_needs_wb_r_T_68, UInt<2>(0h0), _state_req_needs_wb_r_T_67) node _state_req_needs_wb_r_T_70 = cat(_state_req_needs_wb_r_T_69, io.req.old_meta.coh.state) node _state_req_needs_wb_r_T_71 = cat(UInt<2>(0h0), UInt<2>(0h3)) node _state_req_needs_wb_r_T_72 = cat(UInt<2>(0h0), UInt<2>(0h2)) node _state_req_needs_wb_r_T_73 = cat(UInt<2>(0h0), UInt<2>(0h1)) node _state_req_needs_wb_r_T_74 = cat(UInt<2>(0h0), UInt<2>(0h0)) node _state_req_needs_wb_r_T_75 = cat(UInt<2>(0h1), UInt<2>(0h3)) node _state_req_needs_wb_r_T_76 = cat(UInt<2>(0h1), UInt<2>(0h2)) node _state_req_needs_wb_r_T_77 = cat(UInt<2>(0h1), UInt<2>(0h1)) node _state_req_needs_wb_r_T_78 = cat(UInt<2>(0h1), UInt<2>(0h0)) node _state_req_needs_wb_r_T_79 = cat(UInt<2>(0h2), UInt<2>(0h3)) node _state_req_needs_wb_r_T_80 = cat(UInt<2>(0h2), UInt<2>(0h2)) node _state_req_needs_wb_r_T_81 = cat(UInt<2>(0h2), UInt<2>(0h1)) node _state_req_needs_wb_r_T_82 = cat(UInt<2>(0h2), UInt<2>(0h0)) node _state_req_needs_wb_r_T_83 = eq(_state_req_needs_wb_r_T_82, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_84 = mux(_state_req_needs_wb_r_T_83, UInt<1>(0h0), UInt<1>(0h0)) node _state_req_needs_wb_r_T_85 = mux(_state_req_needs_wb_r_T_83, UInt<3>(0h5), UInt<1>(0h0)) node _state_req_needs_wb_r_T_86 = mux(_state_req_needs_wb_r_T_83, UInt<2>(0h0), UInt<1>(0h0)) node _state_req_needs_wb_r_T_87 = eq(_state_req_needs_wb_r_T_81, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_88 = mux(_state_req_needs_wb_r_T_87, UInt<1>(0h0), _state_req_needs_wb_r_T_84) node _state_req_needs_wb_r_T_89 = mux(_state_req_needs_wb_r_T_87, UInt<3>(0h2), _state_req_needs_wb_r_T_85) node _state_req_needs_wb_r_T_90 = mux(_state_req_needs_wb_r_T_87, UInt<2>(0h0), _state_req_needs_wb_r_T_86) node _state_req_needs_wb_r_T_91 = eq(_state_req_needs_wb_r_T_80, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_92 = mux(_state_req_needs_wb_r_T_91, UInt<1>(0h0), _state_req_needs_wb_r_T_88) node _state_req_needs_wb_r_T_93 = mux(_state_req_needs_wb_r_T_91, UInt<3>(0h1), _state_req_needs_wb_r_T_89) node _state_req_needs_wb_r_T_94 = mux(_state_req_needs_wb_r_T_91, UInt<2>(0h0), _state_req_needs_wb_r_T_90) node _state_req_needs_wb_r_T_95 = eq(_state_req_needs_wb_r_T_79, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_96 = mux(_state_req_needs_wb_r_T_95, UInt<1>(0h1), _state_req_needs_wb_r_T_92) node _state_req_needs_wb_r_T_97 = mux(_state_req_needs_wb_r_T_95, UInt<3>(0h1), _state_req_needs_wb_r_T_93) node _state_req_needs_wb_r_T_98 = mux(_state_req_needs_wb_r_T_95, UInt<2>(0h0), _state_req_needs_wb_r_T_94) node _state_req_needs_wb_r_T_99 = eq(_state_req_needs_wb_r_T_78, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_100 = mux(_state_req_needs_wb_r_T_99, UInt<1>(0h0), _state_req_needs_wb_r_T_96) node _state_req_needs_wb_r_T_101 = mux(_state_req_needs_wb_r_T_99, UInt<3>(0h5), _state_req_needs_wb_r_T_97) node _state_req_needs_wb_r_T_102 = mux(_state_req_needs_wb_r_T_99, UInt<2>(0h0), _state_req_needs_wb_r_T_98) node _state_req_needs_wb_r_T_103 = eq(_state_req_needs_wb_r_T_77, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_104 = mux(_state_req_needs_wb_r_T_103, UInt<1>(0h0), _state_req_needs_wb_r_T_100) node _state_req_needs_wb_r_T_105 = mux(_state_req_needs_wb_r_T_103, UInt<3>(0h4), _state_req_needs_wb_r_T_101) node _state_req_needs_wb_r_T_106 = mux(_state_req_needs_wb_r_T_103, UInt<2>(0h1), _state_req_needs_wb_r_T_102) node _state_req_needs_wb_r_T_107 = eq(_state_req_needs_wb_r_T_76, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_108 = mux(_state_req_needs_wb_r_T_107, UInt<1>(0h0), _state_req_needs_wb_r_T_104) node _state_req_needs_wb_r_T_109 = mux(_state_req_needs_wb_r_T_107, UInt<3>(0h0), _state_req_needs_wb_r_T_105) node _state_req_needs_wb_r_T_110 = mux(_state_req_needs_wb_r_T_107, UInt<2>(0h1), _state_req_needs_wb_r_T_106) node _state_req_needs_wb_r_T_111 = eq(_state_req_needs_wb_r_T_75, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_112 = mux(_state_req_needs_wb_r_T_111, UInt<1>(0h1), _state_req_needs_wb_r_T_108) node _state_req_needs_wb_r_T_113 = mux(_state_req_needs_wb_r_T_111, UInt<3>(0h0), _state_req_needs_wb_r_T_109) node _state_req_needs_wb_r_T_114 = mux(_state_req_needs_wb_r_T_111, UInt<2>(0h1), _state_req_needs_wb_r_T_110) node _state_req_needs_wb_r_T_115 = eq(_state_req_needs_wb_r_T_74, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_116 = mux(_state_req_needs_wb_r_T_115, UInt<1>(0h0), _state_req_needs_wb_r_T_112) node _state_req_needs_wb_r_T_117 = mux(_state_req_needs_wb_r_T_115, UInt<3>(0h5), _state_req_needs_wb_r_T_113) node _state_req_needs_wb_r_T_118 = mux(_state_req_needs_wb_r_T_115, UInt<2>(0h0), _state_req_needs_wb_r_T_114) node _state_req_needs_wb_r_T_119 = eq(_state_req_needs_wb_r_T_73, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_120 = mux(_state_req_needs_wb_r_T_119, UInt<1>(0h0), _state_req_needs_wb_r_T_116) node _state_req_needs_wb_r_T_121 = mux(_state_req_needs_wb_r_T_119, UInt<3>(0h4), _state_req_needs_wb_r_T_117) node _state_req_needs_wb_r_T_122 = mux(_state_req_needs_wb_r_T_119, UInt<2>(0h1), _state_req_needs_wb_r_T_118) node _state_req_needs_wb_r_T_123 = eq(_state_req_needs_wb_r_T_72, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_124 = mux(_state_req_needs_wb_r_T_123, UInt<1>(0h0), _state_req_needs_wb_r_T_120) node _state_req_needs_wb_r_T_125 = mux(_state_req_needs_wb_r_T_123, UInt<3>(0h3), _state_req_needs_wb_r_T_121) node _state_req_needs_wb_r_T_126 = mux(_state_req_needs_wb_r_T_123, UInt<2>(0h2), _state_req_needs_wb_r_T_122) node _state_req_needs_wb_r_T_127 = eq(_state_req_needs_wb_r_T_71, _state_req_needs_wb_r_T_70) node state_req_needs_wb_r_1_1 = mux(_state_req_needs_wb_r_T_127, UInt<1>(0h1), _state_req_needs_wb_r_T_124) node state_req_needs_wb_r_2_1 = mux(_state_req_needs_wb_r_T_127, UInt<3>(0h3), _state_req_needs_wb_r_T_125) node state_req_needs_wb_r_3_1 = mux(_state_req_needs_wb_r_T_127, UInt<2>(0h2), _state_req_needs_wb_r_T_126) wire state_req_needs_wb_meta_1 : { state : UInt<2>} connect state_req_needs_wb_meta_1.state, state_req_needs_wb_r_3_1 connect req_needs_wb, state_req_needs_wb_r_1_1 when io.req.tag_match : node _state_r_c_cat_T_50 = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _state_r_c_cat_T_51 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _state_r_c_cat_T_52 = or(_state_r_c_cat_T_50, _state_r_c_cat_T_51) node _state_r_c_cat_T_53 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _state_r_c_cat_T_54 = or(_state_r_c_cat_T_52, _state_r_c_cat_T_53) node _state_r_c_cat_T_55 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _state_r_c_cat_T_56 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _state_r_c_cat_T_57 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _state_r_c_cat_T_58 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _state_r_c_cat_T_59 = or(_state_r_c_cat_T_55, _state_r_c_cat_T_56) node _state_r_c_cat_T_60 = or(_state_r_c_cat_T_59, _state_r_c_cat_T_57) node _state_r_c_cat_T_61 = or(_state_r_c_cat_T_60, _state_r_c_cat_T_58) node _state_r_c_cat_T_62 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _state_r_c_cat_T_63 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _state_r_c_cat_T_64 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _state_r_c_cat_T_65 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _state_r_c_cat_T_66 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _state_r_c_cat_T_67 = or(_state_r_c_cat_T_62, _state_r_c_cat_T_63) node _state_r_c_cat_T_68 = or(_state_r_c_cat_T_67, _state_r_c_cat_T_64) node _state_r_c_cat_T_69 = or(_state_r_c_cat_T_68, _state_r_c_cat_T_65) node _state_r_c_cat_T_70 = or(_state_r_c_cat_T_69, _state_r_c_cat_T_66) node _state_r_c_cat_T_71 = or(_state_r_c_cat_T_61, _state_r_c_cat_T_70) node _state_r_c_cat_T_72 = or(_state_r_c_cat_T_54, _state_r_c_cat_T_71) node _state_r_c_cat_T_73 = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _state_r_c_cat_T_74 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _state_r_c_cat_T_75 = or(_state_r_c_cat_T_73, _state_r_c_cat_T_74) node _state_r_c_cat_T_76 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _state_r_c_cat_T_77 = or(_state_r_c_cat_T_75, _state_r_c_cat_T_76) node _state_r_c_cat_T_78 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _state_r_c_cat_T_79 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _state_r_c_cat_T_80 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _state_r_c_cat_T_81 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _state_r_c_cat_T_82 = or(_state_r_c_cat_T_78, _state_r_c_cat_T_79) node _state_r_c_cat_T_83 = or(_state_r_c_cat_T_82, _state_r_c_cat_T_80) node _state_r_c_cat_T_84 = or(_state_r_c_cat_T_83, _state_r_c_cat_T_81) node _state_r_c_cat_T_85 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _state_r_c_cat_T_86 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _state_r_c_cat_T_87 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _state_r_c_cat_T_88 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _state_r_c_cat_T_89 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _state_r_c_cat_T_90 = or(_state_r_c_cat_T_85, _state_r_c_cat_T_86) node _state_r_c_cat_T_91 = or(_state_r_c_cat_T_90, _state_r_c_cat_T_87) node _state_r_c_cat_T_92 = or(_state_r_c_cat_T_91, _state_r_c_cat_T_88) node _state_r_c_cat_T_93 = or(_state_r_c_cat_T_92, _state_r_c_cat_T_89) node _state_r_c_cat_T_94 = or(_state_r_c_cat_T_84, _state_r_c_cat_T_93) node _state_r_c_cat_T_95 = or(_state_r_c_cat_T_77, _state_r_c_cat_T_94) node _state_r_c_cat_T_96 = eq(io.req.uop.mem_cmd, UInt<2>(0h3)) node _state_r_c_cat_T_97 = or(_state_r_c_cat_T_95, _state_r_c_cat_T_96) node _state_r_c_cat_T_98 = eq(io.req.uop.mem_cmd, UInt<3>(0h6)) node _state_r_c_cat_T_99 = or(_state_r_c_cat_T_97, _state_r_c_cat_T_98) node state_r_c_1 = cat(_state_r_c_cat_T_72, _state_r_c_cat_T_99) node _state_r_T_59 = cat(state_r_c_1, io.req.old_meta.coh.state) node _state_r_T_60 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_61 = cat(_state_r_T_60, UInt<2>(0h3)) node _state_r_T_62 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_63 = cat(_state_r_T_62, UInt<2>(0h2)) node _state_r_T_64 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_65 = cat(_state_r_T_64, UInt<2>(0h1)) node _state_r_T_66 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _state_r_T_67 = cat(_state_r_T_66, UInt<2>(0h3)) node _state_r_T_68 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _state_r_T_69 = cat(_state_r_T_68, UInt<2>(0h2)) node _state_r_T_70 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _state_r_T_71 = cat(_state_r_T_70, UInt<2>(0h3)) node _state_r_T_72 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _state_r_T_73 = cat(_state_r_T_72, UInt<2>(0h2)) node _state_r_T_74 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_75 = cat(_state_r_T_74, UInt<2>(0h0)) node _state_r_T_76 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _state_r_T_77 = cat(_state_r_T_76, UInt<2>(0h1)) node _state_r_T_78 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _state_r_T_79 = cat(_state_r_T_78, UInt<2>(0h0)) node _state_r_T_80 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _state_r_T_81 = cat(_state_r_T_80, UInt<2>(0h1)) node _state_r_T_82 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _state_r_T_83 = cat(_state_r_T_82, UInt<2>(0h0)) node _state_r_T_84 = eq(_state_r_T_83, _state_r_T_59) node _state_r_T_85 = mux(_state_r_T_84, UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_86 = mux(_state_r_T_84, UInt<2>(0h1), UInt<1>(0h0)) node _state_r_T_87 = eq(_state_r_T_81, _state_r_T_59) node _state_r_T_88 = mux(_state_r_T_87, UInt<1>(0h0), _state_r_T_85) node _state_r_T_89 = mux(_state_r_T_87, UInt<2>(0h2), _state_r_T_86) node _state_r_T_90 = eq(_state_r_T_79, _state_r_T_59) node _state_r_T_91 = mux(_state_r_T_90, UInt<1>(0h0), _state_r_T_88) node _state_r_T_92 = mux(_state_r_T_90, UInt<2>(0h1), _state_r_T_89) node _state_r_T_93 = eq(_state_r_T_77, _state_r_T_59) node _state_r_T_94 = mux(_state_r_T_93, UInt<1>(0h0), _state_r_T_91) node _state_r_T_95 = mux(_state_r_T_93, UInt<2>(0h2), _state_r_T_92) node _state_r_T_96 = eq(_state_r_T_75, _state_r_T_59) node _state_r_T_97 = mux(_state_r_T_96, UInt<1>(0h0), _state_r_T_94) node _state_r_T_98 = mux(_state_r_T_96, UInt<2>(0h0), _state_r_T_95) node _state_r_T_99 = eq(_state_r_T_73, _state_r_T_59) node _state_r_T_100 = mux(_state_r_T_99, UInt<1>(0h1), _state_r_T_97) node _state_r_T_101 = mux(_state_r_T_99, UInt<2>(0h3), _state_r_T_98) node _state_r_T_102 = eq(_state_r_T_71, _state_r_T_59) node _state_r_T_103 = mux(_state_r_T_102, UInt<1>(0h1), _state_r_T_100) node _state_r_T_104 = mux(_state_r_T_102, UInt<2>(0h3), _state_r_T_101) node _state_r_T_105 = eq(_state_r_T_69, _state_r_T_59) node _state_r_T_106 = mux(_state_r_T_105, UInt<1>(0h1), _state_r_T_103) node _state_r_T_107 = mux(_state_r_T_105, UInt<2>(0h2), _state_r_T_104) node _state_r_T_108 = eq(_state_r_T_67, _state_r_T_59) node _state_r_T_109 = mux(_state_r_T_108, UInt<1>(0h1), _state_r_T_106) node _state_r_T_110 = mux(_state_r_T_108, UInt<2>(0h3), _state_r_T_107) node _state_r_T_111 = eq(_state_r_T_65, _state_r_T_59) node _state_r_T_112 = mux(_state_r_T_111, UInt<1>(0h1), _state_r_T_109) node _state_r_T_113 = mux(_state_r_T_111, UInt<2>(0h1), _state_r_T_110) node _state_r_T_114 = eq(_state_r_T_63, _state_r_T_59) node _state_r_T_115 = mux(_state_r_T_114, UInt<1>(0h1), _state_r_T_112) node _state_r_T_116 = mux(_state_r_T_114, UInt<2>(0h2), _state_r_T_113) node _state_r_T_117 = eq(_state_r_T_61, _state_r_T_59) node state_is_hit_1 = mux(_state_r_T_117, UInt<1>(0h1), _state_r_T_115) node state_r_2_1 = mux(_state_r_T_117, UInt<2>(0h3), _state_r_T_116) wire state_coh_on_hit_1 : { state : UInt<2>} connect state_coh_on_hit_1.state, state_r_2_1 when state_is_hit_1 : node _state_T_37 = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _state_T_38 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _state_T_39 = or(_state_T_37, _state_T_38) node _state_T_40 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _state_T_41 = or(_state_T_39, _state_T_40) node _state_T_42 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _state_T_43 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _state_T_44 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _state_T_45 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _state_T_46 = or(_state_T_42, _state_T_43) node _state_T_47 = or(_state_T_46, _state_T_44) node _state_T_48 = or(_state_T_47, _state_T_45) node _state_T_49 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _state_T_50 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _state_T_51 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _state_T_52 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _state_T_53 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _state_T_54 = or(_state_T_49, _state_T_50) node _state_T_55 = or(_state_T_54, _state_T_51) node _state_T_56 = or(_state_T_55, _state_T_52) node _state_T_57 = or(_state_T_56, _state_T_53) node _state_T_58 = or(_state_T_48, _state_T_57) node _state_T_59 = or(_state_T_41, _state_T_58) node _state_T_60 = asUInt(reset) node _state_T_61 = eq(_state_T_60, UInt<1>(0h0)) when _state_T_61 : node _state_T_62 = eq(_state_T_59, UInt<1>(0h0)) when _state_T_62 : printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:220 assert(isWrite(io.req.uop.mem_cmd))\n") : state_printf_3 assert(clock, _state_T_59, UInt<1>(0h1), "") : state_assert_3 connect new_coh, state_coh_on_hit_1 connect state_new_state_1, UInt<5>(0hc) else : connect new_coh, io.req.old_meta.coh connect state_new_state_1, UInt<5>(0h1) else : wire state_new_coh_meta_1 : { state : UInt<2>} connect state_new_coh_meta_1.state, UInt<2>(0h0) connect new_coh, state_new_coh_meta_1 connect state_new_state_1, UInt<5>(0h1) connect state, state_new_state_1	module BoomMSHR_12( // @[mshrs.scala:36:7] input clock, // @[mshrs.scala:36:7] input reset, // @[mshrs.scala:36:7] input io_req_pri_val, // @[mshrs.scala:39:14] output io_req_pri_rdy, // @[mshrs.scala:39:14] input io_req_sec_val, // @[mshrs.scala:39:14] output io_req_sec_rdy, // @[mshrs.scala:39:14] input io_clear_prefetch, // @[mshrs.scala:39:14] input [4:0] io_rob_pnr_idx, // @[mshrs.scala:39:14] input [4:0] io_rob_head_idx, // @[mshrs.scala:39:14] input [31:0] io_req_uop_inst, // @[mshrs.scala:39:14] input [31:0] io_req_uop_debug_inst, // @[mshrs.scala:39:14] input io_req_uop_is_rvc, // @[mshrs.scala:39:14] input [33:0] io_req_uop_debug_pc, // @[mshrs.scala:39:14] input io_req_uop_iq_type_0, // @[mshrs.scala:39:14] input io_req_uop_iq_type_1, // @[mshrs.scala:39:14] input io_req_uop_iq_type_2, // @[mshrs.scala:39:14] input io_req_uop_iq_type_3, // @[mshrs.scala:39:14] input io_req_uop_fu_code_0, // @[mshrs.scala:39:14] input io_req_uop_fu_code_1, // @[mshrs.scala:39:14] input io_req_uop_fu_code_2, // @[mshrs.scala:39:14] input io_req_uop_fu_code_3, // @[mshrs.scala:39:14] input io_req_uop_fu_code_4, // @[mshrs.scala:39:14] input io_req_uop_fu_code_5, // @[mshrs.scala:39:14] input io_req_uop_fu_code_6, // @[mshrs.scala:39:14] input io_req_uop_fu_code_7, // @[mshrs.scala:39:14] input io_req_uop_fu_code_8, // @[mshrs.scala:39:14] input io_req_uop_fu_code_9, // @[mshrs.scala:39:14] input io_req_uop_iw_issued, // @[mshrs.scala:39:14] input io_req_uop_iw_issued_partial_agen, // @[mshrs.scala:39:14] input io_req_uop_iw_issued_partial_dgen, // @[mshrs.scala:39:14] input io_req_uop_iw_p1_speculative_child, // @[mshrs.scala:39:14] input io_req_uop_iw_p2_speculative_child, // @[mshrs.scala:39:14] input io_req_uop_iw_p1_bypass_hint, // @[mshrs.scala:39:14] input io_req_uop_iw_p2_bypass_hint, // @[mshrs.scala:39:14] input io_req_uop_iw_p3_bypass_hint, // @[mshrs.scala:39:14] input io_req_uop_dis_col_sel, // @[mshrs.scala:39:14] input [3:0] io_req_uop_br_mask, // @[mshrs.scala:39:14] input [1:0] io_req_uop_br_tag, // @[mshrs.scala:39:14] input [3:0] io_req_uop_br_type, // @[mshrs.scala:39:14] input io_req_uop_is_sfb, // @[mshrs.scala:39:14] input io_req_uop_is_fence, // @[mshrs.scala:39:14] input io_req_uop_is_fencei, // @[mshrs.scala:39:14] input io_req_uop_is_sfence, // @[mshrs.scala:39:14] input io_req_uop_is_amo, // @[mshrs.scala:39:14] input io_req_uop_is_eret, // @[mshrs.scala:39:14] input io_req_uop_is_sys_pc2epc, // @[mshrs.scala:39:14] input io_req_uop_is_rocc, // @[mshrs.scala:39:14] input io_req_uop_is_mov, // @[mshrs.scala:39:14] input [3:0] io_req_uop_ftq_idx, // @[mshrs.scala:39:14] input io_req_uop_edge_inst, // @[mshrs.scala:39:14] input [5:0] io_req_uop_pc_lob, // @[mshrs.scala:39:14] input io_req_uop_taken, // @[mshrs.scala:39:14] input io_req_uop_imm_rename, // @[mshrs.scala:39:14] input [2:0] io_req_uop_imm_sel, // @[mshrs.scala:39:14] input [4:0] io_req_uop_pimm, // @[mshrs.scala:39:14] input [19:0] io_req_uop_imm_packed, // @[mshrs.scala:39:14] input [1:0] io_req_uop_op1_sel, // @[mshrs.scala:39:14] input [2:0] io_req_uop_op2_sel, // @[mshrs.scala:39:14] input io_req_uop_fp_ctrl_ldst, // @[mshrs.scala:39:14] input io_req_uop_fp_ctrl_wen, // @[mshrs.scala:39:14] input io_req_uop_fp_ctrl_ren1, // @[mshrs.scala:39:14] input io_req_uop_fp_ctrl_ren2, // @[mshrs.scala:39:14] input io_req_uop_fp_ctrl_ren3, // @[mshrs.scala:39:14] input io_req_uop_fp_ctrl_swap12, // @[mshrs.scala:39:14] input io_req_uop_fp_ctrl_swap23, // @[mshrs.scala:39:14] input [1:0] io_req_uop_fp_ctrl_typeTagIn, // @[mshrs.scala:39:14] input [1:0] io_req_uop_fp_ctrl_typeTagOut, // @[mshrs.scala:39:14] input io_req_uop_fp_ctrl_fromint, // @[mshrs.scala:39:14] input io_req_uop_fp_ctrl_toint, // @[mshrs.scala:39:14] input io_req_uop_fp_ctrl_fastpipe, // @[mshrs.scala:39:14] input io_req_uop_fp_ctrl_fma, // @[mshrs.scala:39:14] input io_req_uop_fp_ctrl_div, // @[mshrs.scala:39:14] input io_req_uop_fp_ctrl_sqrt, // @[mshrs.scala:39:14] input io_req_uop_fp_ctrl_wflags, // @[mshrs.scala:39:14] input io_req_uop_fp_ctrl_vec, // @[mshrs.scala:39:14] input [4:0] io_req_uop_rob_idx, // @[mshrs.scala:39:14] input [3:0] io_req_uop_ldq_idx, // @[mshrs.scala:39:14] input [3:0] io_req_uop_stq_idx, // @[mshrs.scala:39:14] input [1:0] io_req_uop_rxq_idx, // @[mshrs.scala:39:14] input [5:0] io_req_uop_pdst, // @[mshrs.scala:39:14] input [5:0] io_req_uop_prs1, // @[mshrs.scala:39:14] input [5:0] io_req_uop_prs2, // @[mshrs.scala:39:14] input [5:0] io_req_uop_prs3, // @[mshrs.scala:39:14] input [3:0] io_req_uop_ppred, // @[mshrs.scala:39:14] input io_req_uop_prs1_busy, // @[mshrs.scala:39:14] input io_req_uop_prs2_busy, // @[mshrs.scala:39:14] input io_req_uop_prs3_busy, // @[mshrs.scala:39:14] input io_req_uop_ppred_busy, // @[mshrs.scala:39:14] input [5:0] io_req_uop_stale_pdst, // @[mshrs.scala:39:14] input io_req_uop_exception, // @[mshrs.scala:39:14] input [63:0] io_req_uop_exc_cause, // @[mshrs.scala:39:14] input [4:0] io_req_uop_mem_cmd, // @[mshrs.scala:39:14] input [1:0] io_req_uop_mem_size, // @[mshrs.scala:39:14] input io_req_uop_mem_signed, // @[mshrs.scala:39:14] input io_req_uop_uses_ldq, // @[mshrs.scala:39:14] input io_req_uop_uses_stq, // @[mshrs.scala:39:14] input io_req_uop_is_unique, // @[mshrs.scala:39:14] input io_req_uop_flush_on_commit, // @[mshrs.scala:39:14] input [2:0] io_req_uop_csr_cmd, // @[mshrs.scala:39:14] input io_req_uop_ldst_is_rs1, // @[mshrs.scala:39:14] input [5:0] io_req_uop_ldst, // @[mshrs.scala:39:14] input [5:0] io_req_uop_lrs1, // @[mshrs.scala:39:14] input [5:0] io_req_uop_lrs2, // @[mshrs.scala:39:14] input [5:0] io_req_uop_lrs3, // @[mshrs.scala:39:14] input [1:0] io_req_uop_dst_rtype, // @[mshrs.scala:39:14] input [1:0] io_req_uop_lrs1_rtype, // @[mshrs.scala:39:14] input [1:0] io_req_uop_lrs2_rtype, // @[mshrs.scala:39:14] input io_req_uop_frs3_en, // @[mshrs.scala:39:14] input io_req_uop_fcn_dw, // @[mshrs.scala:39:14] input [4:0] io_req_uop_fcn_op, // @[mshrs.scala:39:14] input io_req_uop_fp_val, // @[mshrs.scala:39:14] input [2:0] io_req_uop_fp_rm, // @[mshrs.scala:39:14] input [1:0] io_req_uop_fp_typ, // @[mshrs.scala:39:14] input io_req_uop_xcpt_pf_if, // @[mshrs.scala:39:14] input io_req_uop_xcpt_ae_if, // @[mshrs.scala:39:14] input io_req_uop_xcpt_ma_if, // @[mshrs.scala:39:14] input io_req_uop_bp_debug_if, // @[mshrs.scala:39:14] input io_req_uop_bp_xcpt_if, // @[mshrs.scala:39:14] input [2:0] io_req_uop_debug_fsrc, // @[mshrs.scala:39:14] input [2:0] io_req_uop_debug_tsrc, // @[mshrs.scala:39:14] input [33:0] io_req_addr, // @[mshrs.scala:39:14] input [63:0] io_req_data, // @[mshrs.scala:39:14] input io_req_is_hella, // @[mshrs.scala:39:14] input io_req_tag_match, // @[mshrs.scala:39:14] input [1:0] io_req_old_meta_coh_state, // @[mshrs.scala:39:14] input [21:0] io_req_old_meta_tag, // @[mshrs.scala:39:14] input [1:0] io_req_way_en, // @[mshrs.scala:39:14] input [4:0] io_req_sdq_id, // @[mshrs.scala:39:14] input io_req_is_probe, // @[mshrs.scala:39:14] output io_idx_valid, // @[mshrs.scala:39:14] output [3:0] io_idx_bits, // @[mshrs.scala:39:14] output io_way_valid, // @[mshrs.scala:39:14] output [1:0] io_way_bits, // @[mshrs.scala:39:14] output io_tag_valid, // @[mshrs.scala:39:14] output [23:0] io_tag_bits, // @[mshrs.scala:39:14] input io_mem_acquire_ready, // @[mshrs.scala:39:14] output io_mem_acquire_valid, // @[mshrs.scala:39:14] output [2:0] io_mem_acquire_bits_param, // @[mshrs.scala:39:14] output [31:0] io_mem_acquire_bits_address, // @[mshrs.scala:39:14] output io_mem_grant_ready, // @[mshrs.scala:39:14] input io_mem_grant_valid, // @[mshrs.scala:39:14] input [2:0] io_mem_grant_bits_opcode, // @[mshrs.scala:39:14] input [1:0] io_mem_grant_bits_param, // @[mshrs.scala:39:14] input [3:0] io_mem_grant_bits_size, // @[mshrs.scala:39:14] input [3:0] io_mem_grant_bits_source, // @[mshrs.scala:39:14] input [2:0] io_mem_grant_bits_sink, // @[mshrs.scala:39:14] input io_mem_grant_bits_denied, // @[mshrs.scala:39:14] input [63:0] io_mem_grant_bits_data, // @[mshrs.scala:39:14] input io_mem_grant_bits_corrupt, // @[mshrs.scala:39:14] input io_mem_finish_ready, // @[mshrs.scala:39:14] output io_mem_finish_valid, // @[mshrs.scala:39:14] output [2:0] io_mem_finish_bits_sink, // @[mshrs.scala:39:14] input io_prober_state_valid, // @[mshrs.scala:39:14] input [33:0] io_prober_state_bits, // @[mshrs.scala:39:14] input io_refill_ready, // @[mshrs.scala:39:14] output io_refill_valid, // @[mshrs.scala:39:14] output [1:0] io_refill_bits_way_en, // @[mshrs.scala:39:14] output [9:0] io_refill_bits_addr, // @[mshrs.scala:39:14] output [63:0] io_refill_bits_data, // @[mshrs.scala:39:14] input io_meta_write_ready, // @[mshrs.scala:39:14] output io_meta_write_valid, // @[mshrs.scala:39:14] output [3:0] io_meta_write_bits_idx, // @[mshrs.scala:39:14] output [1:0] io_meta_write_bits_way_en, // @[mshrs.scala:39:14] output [21:0] io_meta_write_bits_tag, // @[mshrs.scala:39:14] output [1:0] io_meta_write_bits_data_coh_state, // @[mshrs.scala:39:14] output [21:0] io_meta_write_bits_data_tag, // @[mshrs.scala:39:14] input io_meta_read_ready, // @[mshrs.scala:39:14] output io_meta_read_valid, // @[mshrs.scala:39:14] output [3:0] io_meta_read_bits_idx, // @[mshrs.scala:39:14] output [1:0] io_meta_read_bits_way_en, // @[mshrs.scala:39:14] output [21:0] io_meta_read_bits_tag, // @[mshrs.scala:39:14] input io_meta_resp_valid, // @[mshrs.scala:39:14] input [1:0] io_meta_resp_bits_coh_state, // @[mshrs.scala:39:14] input [21:0] io_meta_resp_bits_tag, // @[mshrs.scala:39:14] input io_wb_req_ready, // @[mshrs.scala:39:14] output io_wb_req_valid, // @[mshrs.scala:39:14] output [21:0] io_wb_req_bits_tag, // @[mshrs.scala:39:14] output [3:0] io_wb_req_bits_idx, // @[mshrs.scala:39:14] output [2:0] io_wb_req_bits_param, // @[mshrs.scala:39:14] output [1:0] io_wb_req_bits_way_en, // @[mshrs.scala:39:14] output io_commit_val, // @[mshrs.scala:39:14] output [33:0] io_commit_addr, // @[mshrs.scala:39:14] output [1:0] io_commit_coh_state, // @[mshrs.scala:39:14] output [2:0] io_lb_read_offset, // @[mshrs.scala:39:14] input [63:0] io_lb_resp, // @[mshrs.scala:39:14] output io_lb_write_valid, // @[mshrs.scala:39:14] output [2:0] io_lb_write_bits_offset, // @[mshrs.scala:39:14] output [63:0] io_lb_write_bits_data, // @[mshrs.scala:39:14] input io_replay_ready, // @[mshrs.scala:39:14] output io_replay_valid, // @[mshrs.scala:39:14] output [31:0] io_replay_bits_uop_inst, // @[mshrs.scala:39:14] output [31:0] io_replay_bits_uop_debug_inst, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_rvc, // @[mshrs.scala:39:14] output [33:0] io_replay_bits_uop_debug_pc, // @[mshrs.scala:39:14] output io_replay_bits_uop_iq_type_0, // @[mshrs.scala:39:14] output io_replay_bits_uop_iq_type_1, // @[mshrs.scala:39:14] output io_replay_bits_uop_iq_type_2, // @[mshrs.scala:39:14] output io_replay_bits_uop_iq_type_3, // @[mshrs.scala:39:14] output io_replay_bits_uop_fu_code_0, // @[mshrs.scala:39:14] output io_replay_bits_uop_fu_code_1, // @[mshrs.scala:39:14] output io_replay_bits_uop_fu_code_2, // @[mshrs.scala:39:14] output io_replay_bits_uop_fu_code_3, // @[mshrs.scala:39:14] output io_replay_bits_uop_fu_code_4, // @[mshrs.scala:39:14] output io_replay_bits_uop_fu_code_5, // @[mshrs.scala:39:14] output io_replay_bits_uop_fu_code_6, // @[mshrs.scala:39:14] output io_replay_bits_uop_fu_code_7, // @[mshrs.scala:39:14] output io_replay_bits_uop_fu_code_8, // @[mshrs.scala:39:14] output io_replay_bits_uop_fu_code_9, // @[mshrs.scala:39:14] output io_replay_bits_uop_iw_issued, // @[mshrs.scala:39:14] output io_replay_bits_uop_iw_issued_partial_agen, // @[mshrs.scala:39:14] output io_replay_bits_uop_iw_issued_partial_dgen, // @[mshrs.scala:39:14] output io_replay_bits_uop_iw_p1_speculative_child, // @[mshrs.scala:39:14] output io_replay_bits_uop_iw_p2_speculative_child, // @[mshrs.scala:39:14] output io_replay_bits_uop_iw_p1_bypass_hint, // @[mshrs.scala:39:14] output io_replay_bits_uop_iw_p2_bypass_hint, // @[mshrs.scala:39:14] output io_replay_bits_uop_iw_p3_bypass_hint, // @[mshrs.scala:39:14] output io_replay_bits_uop_dis_col_sel, // @[mshrs.scala:39:14] output [3:0] io_replay_bits_uop_br_mask, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_br_tag, // @[mshrs.scala:39:14] output [3:0] io_replay_bits_uop_br_type, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_sfb, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_fence, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_fencei, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_sfence, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_amo, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_eret, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_sys_pc2epc, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_rocc, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_mov, // @[mshrs.scala:39:14] output [3:0] io_replay_bits_uop_ftq_idx, // @[mshrs.scala:39:14] output io_replay_bits_uop_edge_inst, // @[mshrs.scala:39:14] output [5:0] io_replay_bits_uop_pc_lob, // @[mshrs.scala:39:14] output io_replay_bits_uop_taken, // @[mshrs.scala:39:14] output io_replay_bits_uop_imm_rename, // @[mshrs.scala:39:14] output [2:0] io_replay_bits_uop_imm_sel, // @[mshrs.scala:39:14] output [4:0] io_replay_bits_uop_pimm, // @[mshrs.scala:39:14] output [19:0] io_replay_bits_uop_imm_packed, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_op1_sel, // @[mshrs.scala:39:14] output [2:0] io_replay_bits_uop_op2_sel, // @[mshrs.scala:39:14] output io_replay_bits_uop_fp_ctrl_ldst, // @[mshrs.scala:39:14] output io_replay_bits_uop_fp_ctrl_wen, // @[mshrs.scala:39:14] output io_replay_bits_uop_fp_ctrl_ren1, // @[mshrs.scala:39:14] output io_replay_bits_uop_fp_ctrl_ren2, // @[mshrs.scala:39:14] output io_replay_bits_uop_fp_ctrl_ren3, // @[mshrs.scala:39:14] output io_replay_bits_uop_fp_ctrl_swap12, // @[mshrs.scala:39:14] output io_replay_bits_uop_fp_ctrl_swap23, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_fp_ctrl_typeTagIn, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_fp_ctrl_typeTagOut, // @[mshrs.scala:39:14] output io_replay_bits_uop_fp_ctrl_fromint, // @[mshrs.scala:39:14] output io_replay_bits_uop_fp_ctrl_toint, // @[mshrs.scala:39:14] output io_replay_bits_uop_fp_ctrl_fastpipe, // @[mshrs.scala:39:14] output io_replay_bits_uop_fp_ctrl_fma, // @[mshrs.scala:39:14] output io_replay_bits_uop_fp_ctrl_div, // @[mshrs.scala:39:14] output io_replay_bits_uop_fp_ctrl_sqrt, // @[mshrs.scala:39:14] output io_replay_bits_uop_fp_ctrl_wflags, // @[mshrs.scala:39:14] output io_replay_bits_uop_fp_ctrl_vec, // @[mshrs.scala:39:14] output [4:0] io_replay_bits_uop_rob_idx, // @[mshrs.scala:39:14] output [3:0] io_replay_bits_uop_ldq_idx, // @[mshrs.scala:39:14] output [3:0] io_replay_bits_uop_stq_idx, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_rxq_idx, // @[mshrs.scala:39:14] output [5:0] io_replay_bits_uop_pdst, // @[mshrs.scala:39:14] output [5:0] io_replay_bits_uop_prs1, // @[mshrs.scala:39:14] output [5:0] io_replay_bits_uop_prs2, // @[mshrs.scala:39:14] output [5:0] io_replay_bits_uop_prs3, // @[mshrs.scala:39:14] output [3:0] io_replay_bits_uop_ppred, // @[mshrs.scala:39:14] output io_replay_bits_uop_prs1_busy, // @[mshrs.scala:39:14] output io_replay_bits_uop_prs2_busy, // @[mshrs.scala:39:14] output io_replay_bits_uop_prs3_busy, // @[mshrs.scala:39:14] output io_replay_bits_uop_ppred_busy, // @[mshrs.scala:39:14] output [5:0] io_replay_bits_uop_stale_pdst, // @[mshrs.scala:39:14] output io_replay_bits_uop_exception, // @[mshrs.scala:39:14] output [63:0] io_replay_bits_uop_exc_cause, // @[mshrs.scala:39:14] output [4:0] io_replay_bits_uop_mem_cmd, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_mem_size, // @[mshrs.scala:39:14] output io_replay_bits_uop_mem_signed, // @[mshrs.scala:39:14] output io_replay_bits_uop_uses_ldq, // @[mshrs.scala:39:14] output io_replay_bits_uop_uses_stq, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_unique, // @[mshrs.scala:39:14] output io_replay_bits_uop_flush_on_commit, // @[mshrs.scala:39:14] output [2:0] io_replay_bits_uop_csr_cmd, // @[mshrs.scala:39:14] output io_replay_bits_uop_ldst_is_rs1, // @[mshrs.scala:39:14] output [5:0] io_replay_bits_uop_ldst, // @[mshrs.scala:39:14] output [5:0] io_replay_bits_uop_lrs1, // @[mshrs.scala:39:14] output [5:0] io_replay_bits_uop_lrs2, // @[mshrs.scala:39:14] output [5:0] io_replay_bits_uop_lrs3, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_dst_rtype, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_lrs1_rtype, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_lrs2_rtype, // @[mshrs.scala:39:14] output io_replay_bits_uop_frs3_en, // @[mshrs.scala:39:14] output io_replay_bits_uop_fcn_dw, // @[mshrs.scala:39:14] output [4:0] io_replay_bits_uop_fcn_op, // @[mshrs.scala:39:14] output io_replay_bits_uop_fp_val, // @[mshrs.scala:39:14] output [2:0] io_replay_bits_uop_fp_rm, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_fp_typ, // @[mshrs.scala:39:14] output io_replay_bits_uop_xcpt_pf_if, // @[mshrs.scala:39:14] output io_replay_bits_uop_xcpt_ae_if, // @[mshrs.scala:39:14] output io_replay_bits_uop_xcpt_ma_if, // @[mshrs.scala:39:14] output io_replay_bits_uop_bp_debug_if, // @[mshrs.scala:39:14] output io_replay_bits_uop_bp_xcpt_if, // @[mshrs.scala:39:14] output [2:0] io_replay_bits_uop_debug_fsrc, // @[mshrs.scala:39:14] output [2:0] io_replay_bits_uop_debug_tsrc, // @[mshrs.scala:39:14] output [33:0] io_replay_bits_addr, // @[mshrs.scala:39:14] output [63:0] io_replay_bits_data, // @[mshrs.scala:39:14] output io_replay_bits_is_hella, // @[mshrs.scala:39:14] output io_replay_bits_tag_match, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_old_meta_coh_state, // @[mshrs.scala:39:14] output [21:0] io_replay_bits_old_meta_tag, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_way_en, // @[mshrs.scala:39:14] output [4:0] io_replay_bits_sdq_id, // @[mshrs.scala:39:14] input io_resp_ready, // @[mshrs.scala:39:14] output io_resp_valid, // @[mshrs.scala:39:14] output [31:0] io_resp_bits_uop_inst, // @[mshrs.scala:39:14] output [31:0] io_resp_bits_uop_debug_inst, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_rvc, // @[mshrs.scala:39:14] output [33:0] io_resp_bits_uop_debug_pc, // @[mshrs.scala:39:14] output io_resp_bits_uop_iq_type_0, // @[mshrs.scala:39:14] output io_resp_bits_uop_iq_type_1, // @[mshrs.scala:39:14] output io_resp_bits_uop_iq_type_2, // @[mshrs.scala:39:14] output io_resp_bits_uop_iq_type_3, // @[mshrs.scala:39:14] output io_resp_bits_uop_fu_code_0, // @[mshrs.scala:39:14] output io_resp_bits_uop_fu_code_1, // @[mshrs.scala:39:14] output io_resp_bits_uop_fu_code_2, // @[mshrs.scala:39:14] output io_resp_bits_uop_fu_code_3, // @[mshrs.scala:39:14] output io_resp_bits_uop_fu_code_4, // @[mshrs.scala:39:14] output io_resp_bits_uop_fu_code_5, // @[mshrs.scala:39:14] output io_resp_bits_uop_fu_code_6, // @[mshrs.scala:39:14] output io_resp_bits_uop_fu_code_7, // @[mshrs.scala:39:14] output io_resp_bits_uop_fu_code_8, // @[mshrs.scala:39:14] output io_resp_bits_uop_fu_code_9, // @[mshrs.scala:39:14] output io_resp_bits_uop_iw_issued, // @[mshrs.scala:39:14] output io_resp_bits_uop_iw_issued_partial_agen, // @[mshrs.scala:39:14] output io_resp_bits_uop_iw_issued_partial_dgen, // @[mshrs.scala:39:14] output io_resp_bits_uop_iw_p1_speculative_child, // @[mshrs.scala:39:14] output io_resp_bits_uop_iw_p2_speculative_child, // @[mshrs.scala:39:14] output io_resp_bits_uop_iw_p1_bypass_hint, // @[mshrs.scala:39:14] output io_resp_bits_uop_iw_p2_bypass_hint, // @[mshrs.scala:39:14] output io_resp_bits_uop_iw_p3_bypass_hint, // @[mshrs.scala:39:14] output io_resp_bits_uop_dis_col_sel, // @[mshrs.scala:39:14] output [3:0] io_resp_bits_uop_br_mask, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_br_tag, // @[mshrs.scala:39:14] output [3:0] io_resp_bits_uop_br_type, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_sfb, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_fence, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_fencei, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_sfence, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_amo, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_eret, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_sys_pc2epc, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_rocc, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_mov, // @[mshrs.scala:39:14] output [3:0] io_resp_bits_uop_ftq_idx, // @[mshrs.scala:39:14] output io_resp_bits_uop_edge_inst, // @[mshrs.scala:39:14] output [5:0] io_resp_bits_uop_pc_lob, // @[mshrs.scala:39:14] output io_resp_bits_uop_taken, // @[mshrs.scala:39:14] output io_resp_bits_uop_imm_rename, // @[mshrs.scala:39:14] output [2:0] io_resp_bits_uop_imm_sel, // @[mshrs.scala:39:14] output [4:0] io_resp_bits_uop_pimm, // @[mshrs.scala:39:14] output [19:0] io_resp_bits_uop_imm_packed, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_op1_sel, // @[mshrs.scala:39:14] output [2:0] io_resp_bits_uop_op2_sel, // @[mshrs.scala:39:14] output io_resp_bits_uop_fp_ctrl_ldst, // @[mshrs.scala:39:14] output io_resp_bits_uop_fp_ctrl_wen, // @[mshrs.scala:39:14] output io_resp_bits_uop_fp_ctrl_ren1, // @[mshrs.scala:39:14] output io_resp_bits_uop_fp_ctrl_ren2, // @[mshrs.scala:39:14] output io_resp_bits_uop_fp_ctrl_ren3, // @[mshrs.scala:39:14] output io_resp_bits_uop_fp_ctrl_swap12, // @[mshrs.scala:39:14] output io_resp_bits_uop_fp_ctrl_swap23, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_fp_ctrl_typeTagIn, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_fp_ctrl_typeTagOut, // @[mshrs.scala:39:14] output io_resp_bits_uop_fp_ctrl_fromint, // @[mshrs.scala:39:14] output io_resp_bits_uop_fp_ctrl_toint, // @[mshrs.scala:39:14] output io_resp_bits_uop_fp_ctrl_fastpipe, // @[mshrs.scala:39:14] output io_resp_bits_uop_fp_ctrl_fma, // @[mshrs.scala:39:14] output io_resp_bits_uop_fp_ctrl_div, // @[mshrs.scala:39:14] output io_resp_bits_uop_fp_ctrl_sqrt, // @[mshrs.scala:39:14] output io_resp_bits_uop_fp_ctrl_wflags, // @[mshrs.scala:39:14] output io_resp_bits_uop_fp_ctrl_vec, // @[mshrs.scala:39:14] output [4:0] io_resp_bits_uop_rob_idx, // @[mshrs.scala:39:14] output [3:0] io_resp_bits_uop_ldq_idx, // @[mshrs.scala:39:14] output [3:0] io_resp_bits_uop_stq_idx, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_rxq_idx, // @[mshrs.scala:39:14] output [5:0] io_resp_bits_uop_pdst, // @[mshrs.scala:39:14] output [5:0] io_resp_bits_uop_prs1, // @[mshrs.scala:39:14] output [5:0] io_resp_bits_uop_prs2, // @[mshrs.scala:39:14] output [5:0] io_resp_bits_uop_prs3, // @[mshrs.scala:39:14] output [3:0] io_resp_bits_uop_ppred, // @[mshrs.scala:39:14] output io_resp_bits_uop_prs1_busy, // @[mshrs.scala:39:14] output io_resp_bits_uop_prs2_busy, // @[mshrs.scala:39:14] output io_resp_bits_uop_prs3_busy, // @[mshrs.scala:39:14] output io_resp_bits_uop_ppred_busy, // @[mshrs.scala:39:14] output [5:0] io_resp_bits_uop_stale_pdst, // @[mshrs.scala:39:14] output io_resp_bits_uop_exception, // @[mshrs.scala:39:14] output [63:0] io_resp_bits_uop_exc_cause, // @[mshrs.scala:39:14] output [4:0] io_resp_bits_uop_mem_cmd, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_mem_size, // @[mshrs.scala:39:14] output io_resp_bits_uop_mem_signed, // @[mshrs.scala:39:14] output io_resp_bits_uop_uses_ldq, // @[mshrs.scala:39:14] output io_resp_bits_uop_uses_stq, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_unique, // @[mshrs.scala:39:14] output io_resp_bits_uop_flush_on_commit, // @[mshrs.scala:39:14] output [2:0] io_resp_bits_uop_csr_cmd, // @[mshrs.scala:39:14] output io_resp_bits_uop_ldst_is_rs1, // @[mshrs.scala:39:14] output [5:0] io_resp_bits_uop_ldst, // @[mshrs.scala:39:14] output [5:0] io_resp_bits_uop_lrs1, // @[mshrs.scala:39:14] output [5:0] io_resp_bits_uop_lrs2, // @[mshrs.scala:39:14] output [5:0] io_resp_bits_uop_lrs3, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_dst_rtype, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_lrs1_rtype, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_lrs2_rtype, // @[mshrs.scala:39:14] output io_resp_bits_uop_frs3_en, // @[mshrs.scala:39:14] output io_resp_bits_uop_fcn_dw, // @[mshrs.scala:39:14] output [4:0] io_resp_bits_uop_fcn_op, // @[mshrs.scala:39:14] output io_resp_bits_uop_fp_val, // @[mshrs.scala:39:14] output [2:0] io_resp_bits_uop_fp_rm, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_fp_typ, // @[mshrs.scala:39:14] output io_resp_bits_uop_xcpt_pf_if, // @[mshrs.scala:39:14] output io_resp_bits_uop_xcpt_ae_if, // @[mshrs.scala:39:14] output io_resp_bits_uop_xcpt_ma_if, // @[mshrs.scala:39:14] output io_resp_bits_uop_bp_debug_if, // @[mshrs.scala:39:14] output io_resp_bits_uop_bp_xcpt_if, // @[mshrs.scala:39:14] output [2:0] io_resp_bits_uop_debug_fsrc, // @[mshrs.scala:39:14] output [2:0] io_resp_bits_uop_debug_tsrc, // @[mshrs.scala:39:14] output [63:0] io_resp_bits_data, // @[mshrs.scala:39:14] output io_resp_bits_is_hella, // @[mshrs.scala:39:14] input io_wb_resp, // @[mshrs.scala:39:14] output io_probe_rdy // @[mshrs.scala:39:14] ); wire rpq_io_deq_ready; // @[mshrs.scala:135:20, :234:30, :241:40, :246:41, :266:45] wire _rpq_io_enq_ready; // @[mshrs.scala:128:19] wire _rpq_io_deq_valid; // @[mshrs.scala:128:19] wire [31:0] _rpq_io_deq_bits_uop_inst; // @[mshrs.scala:128:19] wire [31:0] _rpq_io_deq_bits_uop_debug_inst; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_rvc; // @[mshrs.scala:128:19] wire [33:0] _rpq_io_deq_bits_uop_debug_pc; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_iq_type_0; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_iq_type_1; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_iq_type_2; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_iq_type_3; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fu_code_0; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fu_code_1; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fu_code_2; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fu_code_3; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fu_code_4; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fu_code_5; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fu_code_6; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fu_code_7; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fu_code_8; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fu_code_9; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_iw_issued; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_iw_issued_partial_agen; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_iw_issued_partial_dgen; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_iw_p1_speculative_child; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_iw_p2_speculative_child; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_iw_p1_bypass_hint; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_iw_p2_bypass_hint; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_iw_p3_bypass_hint; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_dis_col_sel; // @[mshrs.scala:128:19] wire [3:0] _rpq_io_deq_bits_uop_br_mask; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_br_tag; // @[mshrs.scala:128:19] wire [3:0] _rpq_io_deq_bits_uop_br_type; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_sfb; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_fence; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_fencei; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_sfence; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_amo; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_eret; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_sys_pc2epc; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_rocc; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_mov; // @[mshrs.scala:128:19] wire [3:0] _rpq_io_deq_bits_uop_ftq_idx; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_edge_inst; // @[mshrs.scala:128:19] wire [5:0] _rpq_io_deq_bits_uop_pc_lob; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_taken; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_imm_rename; // @[mshrs.scala:128:19] wire [2:0] _rpq_io_deq_bits_uop_imm_sel; // @[mshrs.scala:128:19] wire [4:0] _rpq_io_deq_bits_uop_pimm; // @[mshrs.scala:128:19] wire [19:0] _rpq_io_deq_bits_uop_imm_packed; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_op1_sel; // @[mshrs.scala:128:19] wire [2:0] _rpq_io_deq_bits_uop_op2_sel; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fp_ctrl_ldst; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fp_ctrl_wen; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fp_ctrl_ren1; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fp_ctrl_ren2; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fp_ctrl_ren3; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fp_ctrl_swap12; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fp_ctrl_swap23; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_fp_ctrl_typeTagIn; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_fp_ctrl_typeTagOut; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fp_ctrl_fromint; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fp_ctrl_toint; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fp_ctrl_fastpipe; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fp_ctrl_fma; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fp_ctrl_div; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fp_ctrl_sqrt; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fp_ctrl_wflags; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fp_ctrl_vec; // @[mshrs.scala:128:19] wire [4:0] _rpq_io_deq_bits_uop_rob_idx; // @[mshrs.scala:128:19] wire [3:0] _rpq_io_deq_bits_uop_ldq_idx; // @[mshrs.scala:128:19] wire [3:0] _rpq_io_deq_bits_uop_stq_idx; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_rxq_idx; // @[mshrs.scala:128:19] wire [5:0] _rpq_io_deq_bits_uop_pdst; // @[mshrs.scala:128:19] wire [5:0] _rpq_io_deq_bits_uop_prs1; // @[mshrs.scala:128:19] wire [5:0] _rpq_io_deq_bits_uop_prs2; // @[mshrs.scala:128:19] wire [5:0] _rpq_io_deq_bits_uop_prs3; // @[mshrs.scala:128:19] wire [3:0] _rpq_io_deq_bits_uop_ppred; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_prs1_busy; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_prs2_busy; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_prs3_busy; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_ppred_busy; // @[mshrs.scala:128:19] wire [5:0] _rpq_io_deq_bits_uop_stale_pdst; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_exception; // @[mshrs.scala:128:19] wire [63:0] _rpq_io_deq_bits_uop_exc_cause; // @[mshrs.scala:128:19] wire [4:0] _rpq_io_deq_bits_uop_mem_cmd; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_mem_size; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_mem_signed; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_uses_ldq; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_uses_stq; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_unique; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_flush_on_commit; // @[mshrs.scala:128:19] wire [2:0] _rpq_io_deq_bits_uop_csr_cmd; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_ldst_is_rs1; // @[mshrs.scala:128:19] wire [5:0] _rpq_io_deq_bits_uop_ldst; // @[mshrs.scala:128:19] wire [5:0] _rpq_io_deq_bits_uop_lrs1; // @[mshrs.scala:128:19] wire [5:0] _rpq_io_deq_bits_uop_lrs2; // @[mshrs.scala:128:19] wire [5:0] _rpq_io_deq_bits_uop_lrs3; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_dst_rtype; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_lrs1_rtype; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_lrs2_rtype; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_frs3_en; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fcn_dw; // @[mshrs.scala:128:19] wire [4:0] _rpq_io_deq_bits_uop_fcn_op; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fp_val; // @[mshrs.scala:128:19] wire [2:0] _rpq_io_deq_bits_uop_fp_rm; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_fp_typ; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_xcpt_pf_if; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_xcpt_ae_if; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_xcpt_ma_if; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_bp_debug_if; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_bp_xcpt_if; // @[mshrs.scala:128:19] wire [2:0] _rpq_io_deq_bits_uop_debug_fsrc; // @[mshrs.scala:128:19] wire [2:0] _rpq_io_deq_bits_uop_debug_tsrc; // @[mshrs.scala:128:19] wire [33:0] _rpq_io_deq_bits_addr; // @[mshrs.scala:128:19] wire [63:0] _rpq_io_deq_bits_data; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_is_hella; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_way_en; // @[mshrs.scala:128:19] wire _rpq_io_empty; // @[mshrs.scala:128:19] wire io_req_pri_val_0 = io_req_pri_val; // @[mshrs.scala:36:7] wire io_req_sec_val_0 = io_req_sec_val; // @[mshrs.scala:36:7] wire io_clear_prefetch_0 = io_clear_prefetch; // @[mshrs.scala:36:7] wire [4:0] io_rob_pnr_idx_0 = io_rob_pnr_idx; // @[mshrs.scala:36:7] wire [4:0] io_rob_head_idx_0 = io_rob_head_idx; // @[mshrs.scala:36:7] wire [31:0] io_req_uop_inst_0 = io_req_uop_inst; // @[mshrs.scala:36:7] wire [31:0] io_req_uop_debug_inst_0 = io_req_uop_debug_inst; // @[mshrs.scala:36:7] wire io_req_uop_is_rvc_0 = io_req_uop_is_rvc; // @[mshrs.scala:36:7] wire [33:0] io_req_uop_debug_pc_0 = io_req_uop_debug_pc; // @[mshrs.scala:36:7] wire io_req_uop_iq_type_0_0 = io_req_uop_iq_type_0; // @[mshrs.scala:36:7] wire io_req_uop_iq_type_1_0 = io_req_uop_iq_type_1; // @[mshrs.scala:36:7] wire io_req_uop_iq_type_2_0 = io_req_uop_iq_type_2; // @[mshrs.scala:36:7] wire io_req_uop_iq_type_3_0 = io_req_uop_iq_type_3; // @[mshrs.scala:36:7] wire io_req_uop_fu_code_0_0 = io_req_uop_fu_code_0; // @[mshrs.scala:36:7] wire io_req_uop_fu_code_1_0 = io_req_uop_fu_code_1; // @[mshrs.scala:36:7] wire io_req_uop_fu_code_2_0 = io_req_uop_fu_code_2; // @[mshrs.scala:36:7] wire io_req_uop_fu_code_3_0 = io_req_uop_fu_code_3; // @[mshrs.scala:36:7] wire io_req_uop_fu_code_4_0 = io_req_uop_fu_code_4; // @[mshrs.scala:36:7] wire io_req_uop_fu_code_5_0 = io_req_uop_fu_code_5; // @[mshrs.scala:36:7] wire io_req_uop_fu_code_6_0 = io_req_uop_fu_code_6; // @[mshrs.scala:36:7] wire io_req_uop_fu_code_7_0 = io_req_uop_fu_code_7; // @[mshrs.scala:36:7] wire io_req_uop_fu_code_8_0 = io_req_uop_fu_code_8; // @[mshrs.scala:36:7] wire io_req_uop_fu_code_9_0 = io_req_uop_fu_code_9; // @[mshrs.scala:36:7] wire io_req_uop_iw_issued_0 = io_req_uop_iw_issued; // @[mshrs.scala:36:7] wire io_req_uop_iw_issued_partial_agen_0 = io_req_uop_iw_issued_partial_agen; // @[mshrs.scala:36:7] wire io_req_uop_iw_issued_partial_dgen_0 = io_req_uop_iw_issued_partial_dgen; // @[mshrs.scala:36:7] wire io_req_uop_iw_p1_speculative_child_0 = io_req_uop_iw_p1_speculative_child; // @[mshrs.scala:36:7] wire io_req_uop_iw_p2_speculative_child_0 = io_req_uop_iw_p2_speculative_child; // @[mshrs.scala:36:7] wire io_req_uop_iw_p1_bypass_hint_0 = io_req_uop_iw_p1_bypass_hint; // @[mshrs.scala:36:7] wire io_req_uop_iw_p2_bypass_hint_0 = io_req_uop_iw_p2_bypass_hint; // @[mshrs.scala:36:7] wire io_req_uop_iw_p3_bypass_hint_0 = io_req_uop_iw_p3_bypass_hint; // @[mshrs.scala:36:7] wire io_req_uop_dis_col_sel_0 = io_req_uop_dis_col_sel; // @[mshrs.scala:36:7] wire [3:0] io_req_uop_br_mask_0 = io_req_uop_br_mask; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_br_tag_0 = io_req_uop_br_tag; // @[mshrs.scala:36:7] wire [3:0] io_req_uop_br_type_0 = io_req_uop_br_type; // @[mshrs.scala:36:7] wire io_req_uop_is_sfb_0 = io_req_uop_is_sfb; // @[mshrs.scala:36:7] wire io_req_uop_is_fence_0 = io_req_uop_is_fence; // @[mshrs.scala:36:7] wire io_req_uop_is_fencei_0 = io_req_uop_is_fencei; // @[mshrs.scala:36:7] wire io_req_uop_is_sfence_0 = io_req_uop_is_sfence; // @[mshrs.scala:36:7] wire io_req_uop_is_amo_0 = io_req_uop_is_amo; // @[mshrs.scala:36:7] wire io_req_uop_is_eret_0 = io_req_uop_is_eret; // @[mshrs.scala:36:7] wire io_req_uop_is_sys_pc2epc_0 = io_req_uop_is_sys_pc2epc; // @[mshrs.scala:36:7] wire io_req_uop_is_rocc_0 = io_req_uop_is_rocc; // @[mshrs.scala:36:7] wire io_req_uop_is_mov_0 = io_req_uop_is_mov; // @[mshrs.scala:36:7] wire [3:0] io_req_uop_ftq_idx_0 = io_req_uop_ftq_idx; // @[mshrs.scala:36:7] wire io_req_uop_edge_inst_0 = io_req_uop_edge_inst; // @[mshrs.scala:36:7] wire [5:0] io_req_uop_pc_lob_0 = io_req_uop_pc_lob; // @[mshrs.scala:36:7] wire io_req_uop_taken_0 = io_req_uop_taken; // @[mshrs.scala:36:7] wire io_req_uop_imm_rename_0 = io_req_uop_imm_rename; // @[mshrs.scala:36:7] wire [2:0] io_req_uop_imm_sel_0 = io_req_uop_imm_sel; // @[mshrs.scala:36:7] wire [4:0] io_req_uop_pimm_0 = io_req_uop_pimm; // @[mshrs.scala:36:7] wire [19:0] io_req_uop_imm_packed_0 = io_req_uop_imm_packed; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_op1_sel_0 = io_req_uop_op1_sel; // @[mshrs.scala:36:7] wire [2:0] io_req_uop_op2_sel_0 = io_req_uop_op2_sel; // @[mshrs.scala:36:7] wire io_req_uop_fp_ctrl_ldst_0 = io_req_uop_fp_ctrl_ldst; // @[mshrs.scala:36:7] wire io_req_uop_fp_ctrl_wen_0 = io_req_uop_fp_ctrl_wen; // @[mshrs.scala:36:7] wire io_req_uop_fp_ctrl_ren1_0 = io_req_uop_fp_ctrl_ren1; // @[mshrs.scala:36:7] wire io_req_uop_fp_ctrl_ren2_0 = io_req_uop_fp_ctrl_ren2; // @[mshrs.scala:36:7] wire io_req_uop_fp_ctrl_ren3_0 = io_req_uop_fp_ctrl_ren3; // @[mshrs.scala:36:7] wire io_req_uop_fp_ctrl_swap12_0 = io_req_uop_fp_ctrl_swap12; // @[mshrs.scala:36:7] wire io_req_uop_fp_ctrl_swap23_0 = io_req_uop_fp_ctrl_swap23; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_fp_ctrl_typeTagIn_0 = io_req_uop_fp_ctrl_typeTagIn; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_fp_ctrl_typeTagOut_0 = io_req_uop_fp_ctrl_typeTagOut; // @[mshrs.scala:36:7] wire io_req_uop_fp_ctrl_fromint_0 = io_req_uop_fp_ctrl_fromint; // @[mshrs.scala:36:7] wire io_req_uop_fp_ctrl_toint_0 = io_req_uop_fp_ctrl_toint; // @[mshrs.scala:36:7] wire io_req_uop_fp_ctrl_fastpipe_0 = io_req_uop_fp_ctrl_fastpipe; // @[mshrs.scala:36:7] wire io_req_uop_fp_ctrl_fma_0 = io_req_uop_fp_ctrl_fma; // @[mshrs.scala:36:7] wire io_req_uop_fp_ctrl_div_0 = io_req_uop_fp_ctrl_div; // @[mshrs.scala:36:7] wire io_req_uop_fp_ctrl_sqrt_0 = io_req_uop_fp_ctrl_sqrt; // @[mshrs.scala:36:7] wire io_req_uop_fp_ctrl_wflags_0 = io_req_uop_fp_ctrl_wflags; // @[mshrs.scala:36:7] wire io_req_uop_fp_ctrl_vec_0 = io_req_uop_fp_ctrl_vec; // @[mshrs.scala:36:7] wire [4:0] io_req_uop_rob_idx_0 = io_req_uop_rob_idx; // @[mshrs.scala:36:7] wire [3:0] io_req_uop_ldq_idx_0 = io_req_uop_ldq_idx; // @[mshrs.scala:36:7] wire [3:0] io_req_uop_stq_idx_0 = io_req_uop_stq_idx; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_rxq_idx_0 = io_req_uop_rxq_idx; // @[mshrs.scala:36:7] wire [5:0] io_req_uop_pdst_0 = io_req_uop_pdst; // @[mshrs.scala:36:7] wire [5:0] io_req_uop_prs1_0 = io_req_uop_prs1; // @[mshrs.scala:36:7] wire [5:0] io_req_uop_prs2_0 = io_req_uop_prs2; // @[mshrs.scala:36:7] wire [5:0] io_req_uop_prs3_0 = io_req_uop_prs3; // @[mshrs.scala:36:7] wire [3:0] io_req_uop_ppred_0 = io_req_uop_ppred; // @[mshrs.scala:36:7] wire io_req_uop_prs1_busy_0 = io_req_uop_prs1_busy; // @[mshrs.scala:36:7] wire io_req_uop_prs2_busy_0 = io_req_uop_prs2_busy; // @[mshrs.scala:36:7] wire io_req_uop_prs3_busy_0 = io_req_uop_prs3_busy; // @[mshrs.scala:36:7] wire io_req_uop_ppred_busy_0 = io_req_uop_ppred_busy; // @[mshrs.scala:36:7] wire [5:0] io_req_uop_stale_pdst_0 = io_req_uop_stale_pdst; // @[mshrs.scala:36:7] wire io_req_uop_exception_0 = io_req_uop_exception; // @[mshrs.scala:36:7] wire [63:0] io_req_uop_exc_cause_0 = io_req_uop_exc_cause; // @[mshrs.scala:36:7] wire [4:0] io_req_uop_mem_cmd_0 = io_req_uop_mem_cmd; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_mem_size_0 = io_req_uop_mem_size; // @[mshrs.scala:36:7] wire io_req_uop_mem_signed_0 = io_req_uop_mem_signed; // @[mshrs.scala:36:7] wire io_req_uop_uses_ldq_0 = io_req_uop_uses_ldq; // @[mshrs.scala:36:7] wire io_req_uop_uses_stq_0 = io_req_uop_uses_stq; // @[mshrs.scala:36:7] wire io_req_uop_is_unique_0 = io_req_uop_is_unique; // @[mshrs.scala:36:7] wire io_req_uop_flush_on_commit_0 = io_req_uop_flush_on_commit; // @[mshrs.scala:36:7] wire [2:0] io_req_uop_csr_cmd_0 = io_req_uop_csr_cmd; // @[mshrs.scala:36:7] wire io_req_uop_ldst_is_rs1_0 = io_req_uop_ldst_is_rs1; // @[mshrs.scala:36:7] wire [5:0] io_req_uop_ldst_0 = io_req_uop_ldst; // @[mshrs.scala:36:7] wire [5:0] io_req_uop_lrs1_0 = io_req_uop_lrs1; // @[mshrs.scala:36:7] wire [5:0] io_req_uop_lrs2_0 = io_req_uop_lrs2; // @[mshrs.scala:36:7] wire [5:0] io_req_uop_lrs3_0 = io_req_uop_lrs3; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_dst_rtype_0 = io_req_uop_dst_rtype; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_lrs1_rtype_0 = io_req_uop_lrs1_rtype; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_lrs2_rtype_0 = io_req_uop_lrs2_rtype; // @[mshrs.scala:36:7] wire io_req_uop_frs3_en_0 = io_req_uop_frs3_en; // @[mshrs.scala:36:7] wire io_req_uop_fcn_dw_0 = io_req_uop_fcn_dw; // @[mshrs.scala:36:7] wire [4:0] io_req_uop_fcn_op_0 = io_req_uop_fcn_op; // @[mshrs.scala:36:7] wire io_req_uop_fp_val_0 = io_req_uop_fp_val; // @[mshrs.scala:36:7] wire [2:0] io_req_uop_fp_rm_0 = io_req_uop_fp_rm; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_fp_typ_0 = io_req_uop_fp_typ; // @[mshrs.scala:36:7] wire io_req_uop_xcpt_pf_if_0 = io_req_uop_xcpt_pf_if; // @[mshrs.scala:36:7] wire io_req_uop_xcpt_ae_if_0 = io_req_uop_xcpt_ae_if; // @[mshrs.scala:36:7] wire io_req_uop_xcpt_ma_if_0 = io_req_uop_xcpt_ma_if; // @[mshrs.scala:36:7] wire io_req_uop_bp_debug_if_0 = io_req_uop_bp_debug_if; // @[mshrs.scala:36:7] wire io_req_uop_bp_xcpt_if_0 = io_req_uop_bp_xcpt_if; // @[mshrs.scala:36:7] wire [2:0] io_req_uop_debug_fsrc_0 = io_req_uop_debug_fsrc; // @[mshrs.scala:36:7] wire [2:0] io_req_uop_debug_tsrc_0 = io_req_uop_debug_tsrc; // @[mshrs.scala:36:7] wire [33:0] io_req_addr_0 = io_req_addr; // @[mshrs.scala:36:7] wire [63:0] io_req_data_0 = io_req_data; // @[mshrs.scala:36:7] wire io_req_is_hella_0 = io_req_is_hella; // @[mshrs.scala:36:7] wire io_req_tag_match_0 = io_req_tag_match; // @[mshrs.scala:36:7] wire [1:0] io_req_old_meta_coh_state_0 = io_req_old_meta_coh_state; // @[mshrs.scala:36:7] wire [21:0] io_req_old_meta_tag_0 = io_req_old_meta_tag; // @[mshrs.scala:36:7] wire [1:0] io_req_way_en_0 = io_req_way_en; // @[mshrs.scala:36:7] wire [4:0] io_req_sdq_id_0 = io_req_sdq_id; // @[mshrs.scala:36:7] wire io_req_is_probe_0 = io_req_is_probe; // @[mshrs.scala:36:7] wire io_mem_acquire_ready_0 = io_mem_acquire_ready; // @[mshrs.scala:36:7] wire io_mem_grant_valid_0 = io_mem_grant_valid; // @[mshrs.scala:36:7] wire [2:0] io_mem_grant_bits_opcode_0 = io_mem_grant_bits_opcode; // @[mshrs.scala:36:7] wire [1:0] io_mem_grant_bits_param_0 = io_mem_grant_bits_param; // @[mshrs.scala:36:7] wire [3:0] io_mem_grant_bits_size_0 = io_mem_grant_bits_size; // @[mshrs.scala:36:7] wire [3:0] io_mem_grant_bits_source_0 = io_mem_grant_bits_source; // @[mshrs.scala:36:7] wire [2:0] io_mem_grant_bits_sink_0 = io_mem_grant_bits_sink; // @[mshrs.scala:36:7] wire io_mem_grant_bits_denied_0 = io_mem_grant_bits_denied; // @[mshrs.scala:36:7] wire [63:0] io_mem_grant_bits_data_0 = io_mem_grant_bits_data; // @[mshrs.scala:36:7] wire io_mem_grant_bits_corrupt_0 = io_mem_grant_bits_corrupt; // @[mshrs.scala:36:7] wire io_mem_finish_ready_0 = io_mem_finish_ready; // @[mshrs.scala:36:7] wire io_prober_state_valid_0 = io_prober_state_valid; // @[mshrs.scala:36:7] wire [33:0] io_prober_state_bits_0 = io_prober_state_bits; // @[mshrs.scala:36:7] wire io_refill_ready_0 = io_refill_ready; // @[mshrs.scala:36:7] wire io_meta_write_ready_0 = io_meta_write_ready; // @[mshrs.scala:36:7] wire io_meta_read_ready_0 = io_meta_read_ready; // @[mshrs.scala:36:7] wire io_meta_resp_valid_0 = io_meta_resp_valid; // @[mshrs.scala:36:7] wire [1:0] io_meta_resp_bits_coh_state_0 = io_meta_resp_bits_coh_state; // @[mshrs.scala:36:7] wire [21:0] io_meta_resp_bits_tag_0 = io_meta_resp_bits_tag; // @[mshrs.scala:36:7] wire io_wb_req_ready_0 = io_wb_req_ready; // @[mshrs.scala:36:7] wire [63:0] io_lb_resp_0 = io_lb_resp; // @[mshrs.scala:36:7] wire io_replay_ready_0 = io_replay_ready; // @[mshrs.scala:36:7] wire io_resp_ready_0 = io_resp_ready; // @[mshrs.scala:36:7] wire io_wb_resp_0 = io_wb_resp; // @[mshrs.scala:36:7] wire _state_T = reset; // @[mshrs.scala:213:11] wire _state_T_26 = reset; // @[mshrs.scala:220:15] wire _state_T_34 = reset; // @[mshrs.scala:213:11] wire _state_T_60 = reset; // @[mshrs.scala:220:15] wire [2:0] io_id = 3'h4; // @[mshrs.scala:36:7] wire [2:0] _io_mem_acquire_bits_a_mask_sizeOH_T_2 = 3'h4; // @[OneHot.scala:65:27] wire [3:0] io_brupdate_b1_resolve_mask = 4'h0; // @[mshrs.scala:36:7] wire [3:0] io_brupdate_b1_mispredict_mask = 4'h0; // @[mshrs.scala:36:7] wire [3:0] io_brupdate_b2_uop_br_mask = 4'h0; // @[mshrs.scala:36:7] wire [3:0] io_brupdate_b2_uop_br_type = 4'h0; // @[mshrs.scala:36:7] wire [3:0] io_brupdate_b2_uop_ftq_idx = 4'h0; // @[mshrs.scala:36:7] wire [3:0] io_brupdate_b2_uop_ldq_idx = 4'h0; // @[mshrs.scala:36:7] wire [3:0] io_brupdate_b2_uop_stq_idx = 4'h0; // @[mshrs.scala:36:7] wire [3:0] io_brupdate_b2_uop_ppred = 4'h0; // @[mshrs.scala:36:7] wire [3:0] _r_T_10 = 4'h0; // @[Metadata.scala:125:10] wire [3:0] _grow_param_r_T_16 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _coh_on_grant_T_4 = 4'h0; // @[Metadata.scala:87:10] wire [3:0] _r1_T_16 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _r2_T_16 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _state_req_needs_wb_r_T_10 = 4'h0; // @[Metadata.scala:125:10] wire [3:0] _state_r_T_16 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _needs_wb_r_T_10 = 4'h0; // @[Metadata.scala:125:10] wire [3:0] _r_T_80 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _r_T_139 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _state_req_needs_wb_r_T_74 = 4'h0; // @[Metadata.scala:125:10] wire [3:0] _state_r_T_75 = 4'h0; // @[Metadata.scala:68:10] wire [31:0] io_brupdate_b2_uop_inst = 32'h0; // @[mshrs.scala:36:7] wire [31:0] io_brupdate_b2_uop_debug_inst = 32'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_rvc = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_iq_type_0 = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_iq_type_1 = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_iq_type_2 = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_iq_type_3 = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fu_code_0 = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fu_code_1 = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fu_code_2 = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fu_code_3 = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fu_code_4 = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fu_code_5 = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fu_code_6 = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fu_code_7 = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fu_code_8 = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fu_code_9 = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_iw_issued = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_iw_issued_partial_agen = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_iw_issued_partial_dgen = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_iw_p1_speculative_child = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_iw_p2_speculative_child = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_iw_p1_bypass_hint = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_iw_p2_bypass_hint = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_iw_p3_bypass_hint = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_dis_col_sel = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_sfb = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_fence = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_fencei = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_sfence = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_amo = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_eret = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_sys_pc2epc = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_rocc = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_mov = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_edge_inst = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_taken = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_imm_rename = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fp_ctrl_ldst = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fp_ctrl_wen = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fp_ctrl_ren1 = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fp_ctrl_ren2 = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fp_ctrl_ren3 = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fp_ctrl_swap12 = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fp_ctrl_swap23 = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fp_ctrl_fromint = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fp_ctrl_toint = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fp_ctrl_fastpipe = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fp_ctrl_fma = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fp_ctrl_div = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fp_ctrl_sqrt = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fp_ctrl_wflags = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fp_ctrl_vec = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_prs1_busy = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_prs2_busy = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_prs3_busy = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_ppred_busy = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_exception = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_mem_signed = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_uses_ldq = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_uses_stq = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_unique = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_flush_on_commit = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_ldst_is_rs1 = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_frs3_en = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fcn_dw = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fp_val = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_xcpt_pf_if = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_xcpt_ae_if = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_xcpt_ma_if = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_bp_debug_if = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_bp_xcpt_if = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_mispredict = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_taken = 1'h0; // @[mshrs.scala:36:7] wire io_exception = 1'h0; // @[mshrs.scala:36:7] wire io_mem_acquire_bits_corrupt = 1'h0; // @[mshrs.scala:36:7] wire _r_T_2 = 1'h0; // @[Metadata.scala:140:24] wire _r_T_4 = 1'h0; // @[Metadata.scala:140:24] wire _r_T_20 = 1'h0; // @[Misc.scala:38:9] wire _r_T_24 = 1'h0; // @[Misc.scala:38:9] wire _r_T_28 = 1'h0; // @[Misc.scala:38:9] wire _grow_param_r_T_26 = 1'h0; // @[Misc.scala:35:9] wire _grow_param_r_T_29 = 1'h0; // @[Misc.scala:35:9] wire _grow_param_r_T_32 = 1'h0; // @[Misc.scala:35:9] wire _grow_param_r_T_35 = 1'h0; // @[Misc.scala:35:9] wire _grow_param_r_T_38 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_26 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_29 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_32 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_35 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_38 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_26 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_29 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_32 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_35 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_38 = 1'h0; // @[Misc.scala:35:9] wire _io_mem_acquire_bits_legal_T = 1'h0; // @[Parameters.scala:684:29] wire _io_mem_acquire_bits_legal_T_6 = 1'h0; // @[Parameters.scala:684:54] wire _io_mem_acquire_bits_legal_T_15 = 1'h0; // @[Parameters.scala:686:26] wire io_mem_acquire_bits_a_corrupt = 1'h0; // @[Edges.scala:346:17] wire io_mem_acquire_bits_a_mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _io_mem_acquire_bits_a_mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _io_mem_acquire_bits_a_mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire _io_mem_acquire_bits_a_mask_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _io_mem_acquire_bits_a_mask_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire _state_req_needs_wb_r_T_2 = 1'h0; // @[Metadata.scala:140:24] wire _state_req_needs_wb_r_T_4 = 1'h0; // @[Metadata.scala:140:24] wire _state_req_needs_wb_r_T_20 = 1'h0; // @[Misc.scala:38:9] wire _state_req_needs_wb_r_T_24 = 1'h0; // @[Misc.scala:38:9] wire _state_req_needs_wb_r_T_28 = 1'h0; // @[Misc.scala:38:9] wire _state_r_T_26 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_29 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_32 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_35 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_38 = 1'h0; // @[Misc.scala:35:9] wire io_resp_bits_data_doZero = 1'h0; // @[AMOALU.scala:43:31] wire io_resp_bits_data_doZero_1 = 1'h0; // @[AMOALU.scala:43:31] wire io_resp_bits_data_doZero_2 = 1'h0; // @[AMOALU.scala:43:31] wire _needs_wb_r_T_2 = 1'h0; // @[Metadata.scala:140:24] wire _needs_wb_r_T_4 = 1'h0; // @[Metadata.scala:140:24] wire _needs_wb_r_T_20 = 1'h0; // @[Misc.scala:38:9] wire _needs_wb_r_T_24 = 1'h0; // @[Misc.scala:38:9] wire _needs_wb_r_T_28 = 1'h0; // @[Misc.scala:38:9] wire _r_T_90 = 1'h0; // @[Misc.scala:35:9] wire _r_T_93 = 1'h0; // @[Misc.scala:35:9] wire _r_T_96 = 1'h0; // @[Misc.scala:35:9] wire _r_T_99 = 1'h0; // @[Misc.scala:35:9] wire _r_T_102 = 1'h0; // @[Misc.scala:35:9] wire _r_T_149 = 1'h0; // @[Misc.scala:35:9] wire _r_T_152 = 1'h0; // @[Misc.scala:35:9] wire _r_T_155 = 1'h0; // @[Misc.scala:35:9] wire _r_T_158 = 1'h0; // @[Misc.scala:35:9] wire _r_T_161 = 1'h0; // @[Misc.scala:35:9] wire _state_req_needs_wb_r_T_66 = 1'h0; // @[Metadata.scala:140:24] wire _state_req_needs_wb_r_T_68 = 1'h0; // @[Metadata.scala:140:24] wire _state_req_needs_wb_r_T_84 = 1'h0; // @[Misc.scala:38:9] wire _state_req_needs_wb_r_T_88 = 1'h0; // @[Misc.scala:38:9] wire _state_req_needs_wb_r_T_92 = 1'h0; // @[Misc.scala:38:9] wire _state_r_T_85 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_88 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_91 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_94 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_97 = 1'h0; // @[Misc.scala:35:9] wire [33:0] io_brupdate_b2_uop_debug_pc = 34'h0; // @[mshrs.scala:36:7] wire [33:0] io_brupdate_b2_jalr_target = 34'h0; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_br_tag = 2'h0; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_op1_sel = 2'h0; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn = 2'h0; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut = 2'h0; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_rxq_idx = 2'h0; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_mem_size = 2'h0; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_dst_rtype = 2'h0; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype = 2'h0; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype = 2'h0; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_fp_typ = 2'h0; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_pc_sel = 2'h0; // @[mshrs.scala:36:7] wire [1:0] new_coh_meta_state = 2'h0; // @[Metadata.scala:160:20] wire [1:0] _r_T_22 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_26 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_30 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_34 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_38 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _grow_param_r_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _grow_param_r_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _grow_param_r_T_5 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _grow_param_r_T_15 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _coh_on_grant_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _coh_on_grant_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r1_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r1_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r1_T_5 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r1_T_15 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r2_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r2_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r2_T_5 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r2_T_15 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_req_needs_wb_r_T_22 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_26 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_30 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_34 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_38 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_r_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_r_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_r_T_5 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_r_T_15 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] state_new_coh_meta_state = 2'h0; // @[Metadata.scala:160:20] wire [1:0] _needs_wb_r_T_22 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _needs_wb_r_T_26 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _needs_wb_r_T_30 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _needs_wb_r_T_34 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _needs_wb_r_T_38 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_65 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_67 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_69 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_79 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_124 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_126 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_128 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_138 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] new_coh_meta_1_state = 2'h0; // @[Metadata.scala:160:20] wire [1:0] _state_req_needs_wb_r_T_86 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_90 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_94 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_98 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_102 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_r_T_60 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_r_T_62 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_r_T_64 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_r_T_74 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] state_new_coh_meta_1_state = 2'h0; // @[Metadata.scala:160:20] wire [5:0] io_brupdate_b2_uop_pc_lob = 6'h0; // @[mshrs.scala:36:7] wire [5:0] io_brupdate_b2_uop_pdst = 6'h0; // @[mshrs.scala:36:7] wire [5:0] io_brupdate_b2_uop_prs1 = 6'h0; // @[mshrs.scala:36:7] wire [5:0] io_brupdate_b2_uop_prs2 = 6'h0; // @[mshrs.scala:36:7] wire [5:0] io_brupdate_b2_uop_prs3 = 6'h0; // @[mshrs.scala:36:7] wire [5:0] io_brupdate_b2_uop_stale_pdst = 6'h0; // @[mshrs.scala:36:7] wire [5:0] io_brupdate_b2_uop_ldst = 6'h0; // @[mshrs.scala:36:7] wire [5:0] io_brupdate_b2_uop_lrs1 = 6'h0; // @[mshrs.scala:36:7] wire [5:0] io_brupdate_b2_uop_lrs2 = 6'h0; // @[mshrs.scala:36:7] wire [5:0] io_brupdate_b2_uop_lrs3 = 6'h0; // @[mshrs.scala:36:7] wire [2:0] io_brupdate_b2_uop_imm_sel = 3'h0; // @[mshrs.scala:36:7] wire [2:0] io_brupdate_b2_uop_op2_sel = 3'h0; // @[mshrs.scala:36:7] wire [2:0] io_brupdate_b2_uop_csr_cmd = 3'h0; // @[mshrs.scala:36:7] wire [2:0] io_brupdate_b2_uop_fp_rm = 3'h0; // @[mshrs.scala:36:7] wire [2:0] io_brupdate_b2_uop_debug_fsrc = 3'h0; // @[mshrs.scala:36:7] wire [2:0] io_brupdate_b2_uop_debug_tsrc = 3'h0; // @[mshrs.scala:36:7] wire [2:0] io_brupdate_b2_cfi_type = 3'h0; // @[mshrs.scala:36:7] wire [4:0] io_brupdate_b2_uop_pimm = 5'h0; // @[mshrs.scala:36:7] wire [4:0] io_brupdate_b2_uop_rob_idx = 5'h0; // @[mshrs.scala:36:7] wire [4:0] io_brupdate_b2_uop_mem_cmd = 5'h0; // @[mshrs.scala:36:7] wire [4:0] io_brupdate_b2_uop_fcn_op = 5'h0; // @[mshrs.scala:36:7] wire [19:0] io_brupdate_b2_uop_imm_packed = 20'h0; // @[mshrs.scala:36:7] wire [63:0] io_brupdate_b2_uop_exc_cause = 64'h0; // @[mshrs.scala:36:7] wire [63:0] io_mem_acquire_bits_data = 64'h0; // @[mshrs.scala:36:7] wire [63:0] io_mem_acquire_bits_a_data = 64'h0; // @[Edges.scala:346:17] wire [20:0] io_brupdate_b2_target_offset = 21'h0; // @[mshrs.scala:36:7] wire [2:0] io_mem_acquire_bits_opcode = 3'h6; // @[mshrs.scala:36:7] wire [2:0] io_mem_acquire_bits_a_opcode = 3'h6; // @[Edges.scala:346:17] wire [2:0] _io_mem_acquire_bits_a_mask_sizeOH_T = 3'h6; // @[Misc.scala:202:34] wire [3:0] io_mem_acquire_bits_size = 4'h6; // @[mshrs.scala:36:7] wire [3:0] _r_T_12 = 4'h6; // @[Metadata.scala:127:10] wire [3:0] _grow_param_r_T_10 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _r1_T_10 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _r2_T_10 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] io_mem_acquire_bits_a_size = 4'h6; // @[Edges.scala:346:17] wire [3:0] _state_req_needs_wb_r_T_12 = 4'h6; // @[Metadata.scala:127:10] wire [3:0] _state_r_T_10 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _needs_wb_r_T_12 = 4'h6; // @[Metadata.scala:127:10] wire [3:0] _r_T_74 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _r_T_133 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _state_req_needs_wb_r_T_76 = 4'h6; // @[Metadata.scala:127:10] wire [3:0] _state_r_T_69 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] io_mem_acquire_bits_source = 4'h4; // @[mshrs.scala:36:7] wire [3:0] io_wb_req_bits_source = 4'h4; // @[mshrs.scala:36:7] wire [3:0] _r_T_14 = 4'h4; // @[Metadata.scala:129:10] wire [3:0] _grow_param_r_T_20 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _coh_on_grant_T_6 = 4'h4; // @[Metadata.scala:88:10] wire [3:0] _r1_T_20 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _r2_T_20 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] io_mem_acquire_bits_a_source = 4'h4; // @[Edges.scala:346:17] wire [3:0] _io_mem_acquire_bits_a_mask_sizeOH_T_1 = 4'h4; // @[OneHot.scala:65:12] wire [3:0] _state_req_needs_wb_r_T_14 = 4'h4; // @[Metadata.scala:129:10] wire [3:0] _state_r_T_20 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _needs_wb_r_T_14 = 4'h4; // @[Metadata.scala:129:10] wire [3:0] _r_T_84 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _r_T_143 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _state_req_needs_wb_r_T_78 = 4'h4; // @[Metadata.scala:129:10] wire [3:0] _state_r_T_79 = 4'h4; // @[Metadata.scala:70:10] wire [7:0] io_mem_acquire_bits_mask = 8'hFF; // @[mshrs.scala:36:7] wire [7:0] io_mem_acquire_bits_a_mask = 8'hFF; // @[Edges.scala:346:17] wire [7:0] _io_mem_acquire_bits_a_mask_T = 8'hFF; // @[Misc.scala:222:10] wire io_refill_bits_wmask = 1'h1; // @[mshrs.scala:36:7] wire io_wb_req_bits_voluntary = 1'h1; // @[mshrs.scala:36:7] wire _r_T = 1'h1; // @[Metadata.scala:140:24] wire _io_mem_acquire_bits_legal_T_7 = 1'h1; // @[Parameters.scala:91:44] wire _io_mem_acquire_bits_legal_T_8 = 1'h1; // @[Parameters.scala:684:29] wire io_mem_acquire_bits_a_mask_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21] wire io_mem_acquire_bits_a_mask_sub_sub_size = 1'h1; // @[Misc.scala:209:26] wire io_mem_acquire_bits_a_mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_2_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_3_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_size = 1'h1; // @[Misc.scala:209:26] wire io_mem_acquire_bits_a_mask_acc = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_2 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_3 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_4 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_5 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_6 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_7 = 1'h1; // @[Misc.scala:215:29] wire _io_refill_bits_wmask_T = 1'h1; // @[mshrs.scala:174:28] wire _state_req_needs_wb_r_T = 1'h1; // @[Metadata.scala:140:24] wire _needs_wb_r_T = 1'h1; // @[Metadata.scala:140:24] wire _state_req_needs_wb_r_T_64 = 1'h1; // @[Metadata.scala:140:24] wire [3:0] _grow_param_r_T_24 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _coh_on_grant_T_8 = 4'hC; // @[Metadata.scala:89:10] wire [3:0] _r1_T_24 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _r2_T_24 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _state_r_T_24 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _r_T_88 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _r_T_147 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _state_r_T_83 = 4'hC; // @[Metadata.scala:72:10] wire [1:0] _grow_param_r_T_11 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _grow_param_r_T_13 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _grow_param_r_T_21 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _grow_param_r_T_23 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _coh_on_grant_T_7 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r1_T_11 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r1_T_13 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r1_T_21 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r1_T_23 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r2_T_11 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r2_T_13 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r2_T_21 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r2_T_23 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _dirties_T = 2'h3; // @[Metadata.scala:24:15] wire [1:0] io_mem_acquire_bits_a_mask_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] io_mem_acquire_bits_a_mask_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] io_mem_acquire_bits_a_mask_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] io_mem_acquire_bits_a_mask_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] _state_r_T_11 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_13 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_21 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_23 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_75 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_77 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_85 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_87 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_134 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_136 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_144 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_146 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_70 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_72 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_80 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_82 = 2'h3; // @[Metadata.scala:24:15] wire [3:0] _grow_param_r_T_22 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r1_T_22 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r2_T_22 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _state_r_T_22 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r_T_86 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r_T_145 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _state_r_T_81 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r_T_13 = 4'h5; // @[Metadata.scala:128:10] wire [3:0] _grow_param_r_T_18 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _r1_T_18 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _r2_T_18 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _state_req_needs_wb_r_T_13 = 4'h5; // @[Metadata.scala:128:10] wire [3:0] _state_r_T_18 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _needs_wb_r_T_13 = 4'h5; // @[Metadata.scala:128:10] wire [3:0] _r_T_82 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _r_T_141 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _state_req_needs_wb_r_T_77 = 4'h5; // @[Metadata.scala:128:10] wire [3:0] _state_r_T_77 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _grow_param_r_T_14 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _r1_T_14 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _r2_T_14 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _state_r_T_14 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _r_T_78 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _r_T_137 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _state_r_T_73 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _grow_param_r_T_12 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _r1_T_12 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _r2_T_12 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] io_mem_acquire_bits_a_mask_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] io_mem_acquire_bits_a_mask_hi = 4'hF; // @[Misc.scala:222:10] wire [3:0] _state_r_T_12 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _r_T_76 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _r_T_135 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _state_r_T_71 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _r_T_11 = 4'h7; // @[Metadata.scala:126:10] wire [3:0] _grow_param_r_T_8 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _r1_T_8 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _r2_T_8 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _state_req_needs_wb_r_T_11 = 4'h7; // @[Metadata.scala:126:10] wire [3:0] _state_r_T_8 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _needs_wb_r_T_11 = 4'h7; // @[Metadata.scala:126:10] wire [3:0] _r_T_72 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _r_T_131 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _state_req_needs_wb_r_T_75 = 4'h7; // @[Metadata.scala:126:10] wire [3:0] _state_r_T_67 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _r_T_9 = 4'h1; // @[Metadata.scala:124:10] wire [3:0] _grow_param_r_T_6 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _coh_on_grant_T_2 = 4'h1; // @[Metadata.scala:86:10] wire [3:0] _r1_T_6 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _r2_T_6 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _state_req_needs_wb_r_T_9 = 4'h1; // @[Metadata.scala:124:10] wire [3:0] _state_r_T_6 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _needs_wb_r_T_9 = 4'h1; // @[Metadata.scala:124:10] wire [3:0] _r_T_70 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _r_T_129 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _state_req_needs_wb_r_T_73 = 4'h1; // @[Metadata.scala:124:10] wire [3:0] _state_r_T_65 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _r_T_8 = 4'h2; // @[Metadata.scala:123:10] wire [3:0] _grow_param_r_T_4 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _r1_T_4 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _r2_T_4 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _state_req_needs_wb_r_T_8 = 4'h2; // @[Metadata.scala:123:10] wire [3:0] _state_r_T_4 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _needs_wb_r_T_8 = 4'h2; // @[Metadata.scala:123:10] wire [3:0] _r_T_68 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _r_T_127 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _state_req_needs_wb_r_T_72 = 4'h2; // @[Metadata.scala:123:10] wire [3:0] _state_r_T_63 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _r_T_7 = 4'h3; // @[Metadata.scala:122:10] wire [3:0] _grow_param_r_T_2 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _r1_T_2 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _r2_T_2 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _state_req_needs_wb_r_T_7 = 4'h3; // @[Metadata.scala:122:10] wire [3:0] _state_r_T_2 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _needs_wb_r_T_7 = 4'h3; // @[Metadata.scala:122:10] wire [3:0] _r_T_66 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _r_T_125 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _state_req_needs_wb_r_T_71 = 4'h3; // @[Metadata.scala:122:10] wire [3:0] _state_r_T_61 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _r_T_18 = 4'h8; // @[Metadata.scala:133:10] wire [3:0] _state_req_needs_wb_r_T_18 = 4'h8; // @[Metadata.scala:133:10] wire [3:0] _needs_wb_r_T_18 = 4'h8; // @[Metadata.scala:133:10] wire [3:0] _state_req_needs_wb_r_T_82 = 4'h8; // @[Metadata.scala:133:10] wire [3:0] _r_T_17 = 4'h9; // @[Metadata.scala:132:10] wire [3:0] _state_req_needs_wb_r_T_17 = 4'h9; // @[Metadata.scala:132:10] wire [3:0] _needs_wb_r_T_17 = 4'h9; // @[Metadata.scala:132:10] wire [3:0] _state_req_needs_wb_r_T_81 = 4'h9; // @[Metadata.scala:132:10] wire [3:0] _r_T_16 = 4'hA; // @[Metadata.scala:131:10] wire [3:0] _state_req_needs_wb_r_T_16 = 4'hA; // @[Metadata.scala:131:10] wire [3:0] _needs_wb_r_T_16 = 4'hA; // @[Metadata.scala:131:10] wire [3:0] _state_req_needs_wb_r_T_80 = 4'hA; // @[Metadata.scala:131:10] wire [3:0] _r_T_15 = 4'hB; // @[Metadata.scala:130:10] wire [3:0] _state_req_needs_wb_r_T_15 = 4'hB; // @[Metadata.scala:130:10] wire [3:0] _needs_wb_r_T_15 = 4'hB; // @[Metadata.scala:130:10] wire [3:0] _state_req_needs_wb_r_T_79 = 4'hB; // @[Metadata.scala:130:10] wire [1:0] _r_T_1 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _r_T_3 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _r_T_5 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] io_mem_acquire_bits_a_mask_sizeOH_shiftAmount = 2'h2; // @[OneHot.scala:64:49] wire [1:0] _state_req_needs_wb_r_T_1 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _state_req_needs_wb_r_T_3 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _state_req_needs_wb_r_T_5 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _needs_wb_r_T_1 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _needs_wb_r_T_3 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _needs_wb_r_T_5 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _state_req_needs_wb_r_T_65 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _state_req_needs_wb_r_T_67 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _state_req_needs_wb_r_T_69 = 2'h2; // @[Metadata.scala:140:24] wire [6:0] _data_word_T = 7'h0; // @[mshrs.scala:274:32] wire [2:0] io_mem_acquire_bits_a_mask_sizeOH = 3'h5; // @[Misc.scala:202:81] wire [1:0] _grow_param_r_T_7 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _grow_param_r_T_9 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _grow_param_r_T_17 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _grow_param_r_T_19 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _coh_on_grant_T_5 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r1_T_7 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r1_T_9 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r1_T_17 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r1_T_19 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r2_T_7 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r2_T_9 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r2_T_17 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r2_T_19 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_7 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_9 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_17 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_19 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_71 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_73 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_81 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_83 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_130 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_132 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_140 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_142 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_66 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_68 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_76 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_78 = 2'h1; // @[Metadata.scala:25:15] wire _io_req_sec_rdy_T; // @[mshrs.scala:163:37] wire _io_idx_valid_T; // @[mshrs.scala:149:25] wire [3:0] req_idx; // @[mshrs.scala:110:25] wire _io_way_valid_T_3; // @[mshrs.scala:151:19] wire _io_tag_valid_T; // @[mshrs.scala:150:25] wire [23:0] req_tag; // @[mshrs.scala:111:26] wire [2:0] io_mem_acquire_bits_a_param; // @[Edges.scala:346:17] wire [31:0] io_mem_acquire_bits_a_address; // @[Edges.scala:346:17] wire [2:0] grantack_bits_e_sink = io_mem_grant_bits_sink_0; // @[Edges.scala:451:17] wire [63:0] io_lb_write_bits_data_0 = io_mem_grant_bits_data_0; // @[mshrs.scala:36:7] wire [2:0] shrink_param; // @[Misc.scala:38:36] wire [1:0] coh_on_grant_state; // @[Metadata.scala:160:20] wire [63:0] io_refill_bits_data_0 = io_lb_resp_0; // @[mshrs.scala:36:7] wire [63:0] data_word = io_lb_resp_0; // @[mshrs.scala:36:7, :274:26] wire _io_probe_rdy_T_11; // @[mshrs.scala:148:42] wire io_idx_valid_0; // @[mshrs.scala:36:7] wire [3:0] io_idx_bits_0; // @[mshrs.scala:36:7] wire io_way_valid_0; // @[mshrs.scala:36:7] wire [1:0] io_way_bits_0; // @[mshrs.scala:36:7] wire io_tag_valid_0; // @[mshrs.scala:36:7] wire [23:0] io_tag_bits_0; // @[mshrs.scala:36:7] wire [2:0] io_mem_acquire_bits_param_0; // @[mshrs.scala:36:7] wire [31:0] io_mem_acquire_bits_address_0; // @[mshrs.scala:36:7] wire io_mem_acquire_valid_0; // @[mshrs.scala:36:7] wire io_mem_grant_ready_0; // @[mshrs.scala:36:7] wire [2:0] io_mem_finish_bits_sink_0; // @[mshrs.scala:36:7] wire io_mem_finish_valid_0; // @[mshrs.scala:36:7] wire [1:0] io_refill_bits_way_en_0; // @[mshrs.scala:36:7] wire [9:0] io_refill_bits_addr_0; // @[mshrs.scala:36:7] wire io_refill_valid_0; // @[mshrs.scala:36:7] wire [1:0] io_meta_write_bits_data_coh_state_0; // @[mshrs.scala:36:7] wire [21:0] io_meta_write_bits_data_tag_0; // @[mshrs.scala:36:7] wire [3:0] io_meta_write_bits_idx_0; // @[mshrs.scala:36:7] wire [1:0] io_meta_write_bits_way_en_0; // @[mshrs.scala:36:7] wire [21:0] io_meta_write_bits_tag_0; // @[mshrs.scala:36:7] wire io_meta_write_valid_0; // @[mshrs.scala:36:7] wire [3:0] io_meta_read_bits_idx_0; // @[mshrs.scala:36:7] wire [1:0] io_meta_read_bits_way_en_0; // @[mshrs.scala:36:7] wire [21:0] io_meta_read_bits_tag_0; // @[mshrs.scala:36:7] wire io_meta_read_valid_0; // @[mshrs.scala:36:7] wire [21:0] io_wb_req_bits_tag_0; // @[mshrs.scala:36:7] wire [3:0] io_wb_req_bits_idx_0; // @[mshrs.scala:36:7] wire [2:0] io_wb_req_bits_param_0; // @[mshrs.scala:36:7] wire [1:0] io_wb_req_bits_way_en_0; // @[mshrs.scala:36:7] wire io_wb_req_valid_0; // @[mshrs.scala:36:7] wire [1:0] io_commit_coh_state_0; // @[mshrs.scala:36:7] wire [2:0] io_lb_read_offset_0; // @[mshrs.scala:36:7] wire [2:0] io_lb_write_bits_offset_0; // @[mshrs.scala:36:7] wire io_lb_write_valid_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_iq_type_0_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_iq_type_1_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_iq_type_2_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_iq_type_3_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fu_code_0_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fu_code_1_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fu_code_2_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fu_code_3_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fu_code_4_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fu_code_5_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fu_code_6_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fu_code_7_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fu_code_8_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fu_code_9_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fp_ctrl_ldst_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fp_ctrl_wen_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fp_ctrl_ren1_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fp_ctrl_ren2_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fp_ctrl_ren3_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fp_ctrl_swap12_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fp_ctrl_swap23_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_fp_ctrl_typeTagIn_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_fp_ctrl_typeTagOut_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fp_ctrl_fromint_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fp_ctrl_toint_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fp_ctrl_fastpipe_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fp_ctrl_fma_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fp_ctrl_div_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fp_ctrl_sqrt_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fp_ctrl_wflags_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fp_ctrl_vec_0; // @[mshrs.scala:36:7] wire [31:0] io_replay_bits_uop_inst_0; // @[mshrs.scala:36:7] wire [31:0] io_replay_bits_uop_debug_inst_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_rvc_0; // @[mshrs.scala:36:7] wire [33:0] io_replay_bits_uop_debug_pc_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_iw_issued_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_iw_issued_partial_agen_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_iw_issued_partial_dgen_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_iw_p1_speculative_child_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_iw_p2_speculative_child_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_iw_p1_bypass_hint_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_iw_p2_bypass_hint_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_iw_p3_bypass_hint_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_dis_col_sel_0; // @[mshrs.scala:36:7] wire [3:0] io_replay_bits_uop_br_mask_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_br_tag_0; // @[mshrs.scala:36:7] wire [3:0] io_replay_bits_uop_br_type_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_sfb_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_fence_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_fencei_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_sfence_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_amo_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_eret_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_sys_pc2epc_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_rocc_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_mov_0; // @[mshrs.scala:36:7] wire [3:0] io_replay_bits_uop_ftq_idx_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_edge_inst_0; // @[mshrs.scala:36:7] wire [5:0] io_replay_bits_uop_pc_lob_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_taken_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_imm_rename_0; // @[mshrs.scala:36:7] wire [2:0] io_replay_bits_uop_imm_sel_0; // @[mshrs.scala:36:7] wire [4:0] io_replay_bits_uop_pimm_0; // @[mshrs.scala:36:7] wire [19:0] io_replay_bits_uop_imm_packed_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_op1_sel_0; // @[mshrs.scala:36:7] wire [2:0] io_replay_bits_uop_op2_sel_0; // @[mshrs.scala:36:7] wire [4:0] io_replay_bits_uop_rob_idx_0; // @[mshrs.scala:36:7] wire [3:0] io_replay_bits_uop_ldq_idx_0; // @[mshrs.scala:36:7] wire [3:0] io_replay_bits_uop_stq_idx_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_rxq_idx_0; // @[mshrs.scala:36:7] wire [5:0] io_replay_bits_uop_pdst_0; // @[mshrs.scala:36:7] wire [5:0] io_replay_bits_uop_prs1_0; // @[mshrs.scala:36:7] wire [5:0] io_replay_bits_uop_prs2_0; // @[mshrs.scala:36:7] wire [5:0] io_replay_bits_uop_prs3_0; // @[mshrs.scala:36:7] wire [3:0] io_replay_bits_uop_ppred_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_prs1_busy_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_prs2_busy_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_prs3_busy_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_ppred_busy_0; // @[mshrs.scala:36:7] wire [5:0] io_replay_bits_uop_stale_pdst_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_exception_0; // @[mshrs.scala:36:7] wire [63:0] io_replay_bits_uop_exc_cause_0; // @[mshrs.scala:36:7] wire [4:0] io_replay_bits_uop_mem_cmd_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_mem_size_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_mem_signed_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_uses_ldq_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_uses_stq_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_unique_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_flush_on_commit_0; // @[mshrs.scala:36:7] wire [2:0] io_replay_bits_uop_csr_cmd_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_ldst_is_rs1_0; // @[mshrs.scala:36:7] wire [5:0] io_replay_bits_uop_ldst_0; // @[mshrs.scala:36:7] wire [5:0] io_replay_bits_uop_lrs1_0; // @[mshrs.scala:36:7] wire [5:0] io_replay_bits_uop_lrs2_0; // @[mshrs.scala:36:7] wire [5:0] io_replay_bits_uop_lrs3_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_dst_rtype_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_lrs1_rtype_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_lrs2_rtype_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_frs3_en_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fcn_dw_0; // @[mshrs.scala:36:7] wire [4:0] io_replay_bits_uop_fcn_op_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fp_val_0; // @[mshrs.scala:36:7] wire [2:0] io_replay_bits_uop_fp_rm_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_fp_typ_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_xcpt_pf_if_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_xcpt_ae_if_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_xcpt_ma_if_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_bp_debug_if_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_bp_xcpt_if_0; // @[mshrs.scala:36:7] wire [2:0] io_replay_bits_uop_debug_fsrc_0; // @[mshrs.scala:36:7] wire [2:0] io_replay_bits_uop_debug_tsrc_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_old_meta_coh_state_0; // @[mshrs.scala:36:7] wire [21:0] io_replay_bits_old_meta_tag_0; // @[mshrs.scala:36:7] wire [33:0] io_replay_bits_addr_0; // @[mshrs.scala:36:7] wire [63:0] io_replay_bits_data_0; // @[mshrs.scala:36:7] wire io_replay_bits_is_hella_0; // @[mshrs.scala:36:7] wire io_replay_bits_tag_match_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_way_en_0; // @[mshrs.scala:36:7] wire [4:0] io_replay_bits_sdq_id_0; // @[mshrs.scala:36:7] wire io_replay_valid_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_iq_type_0_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_iq_type_1_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_iq_type_2_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_iq_type_3_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fu_code_0_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fu_code_1_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fu_code_2_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fu_code_3_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fu_code_4_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fu_code_5_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fu_code_6_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fu_code_7_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fu_code_8_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fu_code_9_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fp_ctrl_ldst_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fp_ctrl_wen_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fp_ctrl_ren1_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fp_ctrl_ren2_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fp_ctrl_ren3_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fp_ctrl_swap12_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fp_ctrl_swap23_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_fp_ctrl_typeTagIn_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_fp_ctrl_typeTagOut_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fp_ctrl_fromint_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fp_ctrl_toint_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fp_ctrl_fastpipe_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fp_ctrl_fma_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fp_ctrl_div_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fp_ctrl_sqrt_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fp_ctrl_wflags_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fp_ctrl_vec_0; // @[mshrs.scala:36:7] wire [31:0] io_resp_bits_uop_inst_0; // @[mshrs.scala:36:7] wire [31:0] io_resp_bits_uop_debug_inst_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_rvc_0; // @[mshrs.scala:36:7] wire [33:0] io_resp_bits_uop_debug_pc_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_iw_issued_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_iw_issued_partial_agen_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_iw_issued_partial_dgen_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_iw_p1_speculative_child_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_iw_p2_speculative_child_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_iw_p1_bypass_hint_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_iw_p2_bypass_hint_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_iw_p3_bypass_hint_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_dis_col_sel_0; // @[mshrs.scala:36:7] wire [3:0] io_resp_bits_uop_br_mask_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_br_tag_0; // @[mshrs.scala:36:7] wire [3:0] io_resp_bits_uop_br_type_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_sfb_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_fence_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_fencei_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_sfence_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_amo_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_eret_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_sys_pc2epc_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_rocc_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_mov_0; // @[mshrs.scala:36:7] wire [3:0] io_resp_bits_uop_ftq_idx_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_edge_inst_0; // @[mshrs.scala:36:7] wire [5:0] io_resp_bits_uop_pc_lob_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_taken_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_imm_rename_0; // @[mshrs.scala:36:7] wire [2:0] io_resp_bits_uop_imm_sel_0; // @[mshrs.scala:36:7] wire [4:0] io_resp_bits_uop_pimm_0; // @[mshrs.scala:36:7] wire [19:0] io_resp_bits_uop_imm_packed_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_op1_sel_0; // @[mshrs.scala:36:7] wire [2:0] io_resp_bits_uop_op2_sel_0; // @[mshrs.scala:36:7] wire [4:0] io_resp_bits_uop_rob_idx_0; // @[mshrs.scala:36:7] wire [3:0] io_resp_bits_uop_ldq_idx_0; // @[mshrs.scala:36:7] wire [3:0] io_resp_bits_uop_stq_idx_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_rxq_idx_0; // @[mshrs.scala:36:7] wire [5:0] io_resp_bits_uop_pdst_0; // @[mshrs.scala:36:7] wire [5:0] io_resp_bits_uop_prs1_0; // @[mshrs.scala:36:7] wire [5:0] io_resp_bits_uop_prs2_0; // @[mshrs.scala:36:7] wire [5:0] io_resp_bits_uop_prs3_0; // @[mshrs.scala:36:7] wire [3:0] io_resp_bits_uop_ppred_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_prs1_busy_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_prs2_busy_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_prs3_busy_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_ppred_busy_0; // @[mshrs.scala:36:7] wire [5:0] io_resp_bits_uop_stale_pdst_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_exception_0; // @[mshrs.scala:36:7] wire [63:0] io_resp_bits_uop_exc_cause_0; // @[mshrs.scala:36:7] wire [4:0] io_resp_bits_uop_mem_cmd_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_mem_size_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_mem_signed_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_uses_ldq_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_uses_stq_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_unique_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_flush_on_commit_0; // @[mshrs.scala:36:7] wire [2:0] io_resp_bits_uop_csr_cmd_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_ldst_is_rs1_0; // @[mshrs.scala:36:7] wire [5:0] io_resp_bits_uop_ldst_0; // @[mshrs.scala:36:7] wire [5:0] io_resp_bits_uop_lrs1_0; // @[mshrs.scala:36:7] wire [5:0] io_resp_bits_uop_lrs2_0; // @[mshrs.scala:36:7] wire [5:0] io_resp_bits_uop_lrs3_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_dst_rtype_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_lrs1_rtype_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_lrs2_rtype_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_frs3_en_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fcn_dw_0; // @[mshrs.scala:36:7] wire [4:0] io_resp_bits_uop_fcn_op_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fp_val_0; // @[mshrs.scala:36:7] wire [2:0] io_resp_bits_uop_fp_rm_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_fp_typ_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_xcpt_pf_if_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_xcpt_ae_if_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_xcpt_ma_if_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_bp_debug_if_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_bp_xcpt_if_0; // @[mshrs.scala:36:7] wire [2:0] io_resp_bits_uop_debug_fsrc_0; // @[mshrs.scala:36:7] wire [2:0] io_resp_bits_uop_debug_tsrc_0; // @[mshrs.scala:36:7] wire [63:0] io_resp_bits_data_0; // @[mshrs.scala:36:7] wire io_resp_bits_is_hella_0; // @[mshrs.scala:36:7] wire io_resp_valid_0; // @[mshrs.scala:36:7] wire io_req_pri_rdy_0; // @[mshrs.scala:36:7] wire io_req_sec_rdy_0; // @[mshrs.scala:36:7] wire io_commit_val_0; // @[mshrs.scala:36:7] wire [33:0] io_commit_addr_0; // @[mshrs.scala:36:7] wire io_probe_rdy_0; // @[mshrs.scala:36:7] reg [4:0] state; // @[mshrs.scala:107:22] reg [31:0] req_uop_inst; // @[mshrs.scala:109:20] reg [31:0] req_uop_debug_inst; // @[mshrs.scala:109:20] reg req_uop_is_rvc; // @[mshrs.scala:109:20] reg [33:0] req_uop_debug_pc; // @[mshrs.scala:109:20] reg req_uop_iq_type_0; // @[mshrs.scala:109:20] reg req_uop_iq_type_1; // @[mshrs.scala:109:20] reg req_uop_iq_type_2; // @[mshrs.scala:109:20] reg req_uop_iq_type_3; // @[mshrs.scala:109:20] reg req_uop_fu_code_0; // @[mshrs.scala:109:20] reg req_uop_fu_code_1; // @[mshrs.scala:109:20] reg req_uop_fu_code_2; // @[mshrs.scala:109:20] reg req_uop_fu_code_3; // @[mshrs.scala:109:20] reg req_uop_fu_code_4; // @[mshrs.scala:109:20] reg req_uop_fu_code_5; // @[mshrs.scala:109:20] reg req_uop_fu_code_6; // @[mshrs.scala:109:20] reg req_uop_fu_code_7; // @[mshrs.scala:109:20] reg req_uop_fu_code_8; // @[mshrs.scala:109:20] reg req_uop_fu_code_9; // @[mshrs.scala:109:20] reg req_uop_iw_issued; // @[mshrs.scala:109:20] reg req_uop_iw_issued_partial_agen; // @[mshrs.scala:109:20] reg req_uop_iw_issued_partial_dgen; // @[mshrs.scala:109:20] reg req_uop_iw_p1_speculative_child; // @[mshrs.scala:109:20] reg req_uop_iw_p2_speculative_child; // @[mshrs.scala:109:20] reg req_uop_iw_p1_bypass_hint; // @[mshrs.scala:109:20] reg req_uop_iw_p2_bypass_hint; // @[mshrs.scala:109:20] reg req_uop_iw_p3_bypass_hint; // @[mshrs.scala:109:20] reg req_uop_dis_col_sel; // @[mshrs.scala:109:20] reg [3:0] req_uop_br_mask; // @[mshrs.scala:109:20] reg [1:0] req_uop_br_tag; // @[mshrs.scala:109:20] reg [3:0] req_uop_br_type; // @[mshrs.scala:109:20] reg req_uop_is_sfb; // @[mshrs.scala:109:20] reg req_uop_is_fence; // @[mshrs.scala:109:20] reg req_uop_is_fencei; // @[mshrs.scala:109:20] reg req_uop_is_sfence; // @[mshrs.scala:109:20] reg req_uop_is_amo; // @[mshrs.scala:109:20] reg req_uop_is_eret; // @[mshrs.scala:109:20] reg req_uop_is_sys_pc2epc; // @[mshrs.scala:109:20] reg req_uop_is_rocc; // @[mshrs.scala:109:20] reg req_uop_is_mov; // @[mshrs.scala:109:20] reg [3:0] req_uop_ftq_idx; // @[mshrs.scala:109:20] reg req_uop_edge_inst; // @[mshrs.scala:109:20] reg [5:0] req_uop_pc_lob; // @[mshrs.scala:109:20] reg req_uop_taken; // @[mshrs.scala:109:20] reg req_uop_imm_rename; // @[mshrs.scala:109:20] reg [2:0] req_uop_imm_sel; // @[mshrs.scala:109:20] reg [4:0] req_uop_pimm; // @[mshrs.scala:109:20] reg [19:0] req_uop_imm_packed; // @[mshrs.scala:109:20] reg [1:0] req_uop_op1_sel; // @[mshrs.scala:109:20] reg [2:0] req_uop_op2_sel; // @[mshrs.scala:109:20] reg req_uop_fp_ctrl_ldst; // @[mshrs.scala:109:20] reg req_uop_fp_ctrl_wen; // @[mshrs.scala:109:20] reg req_uop_fp_ctrl_ren1; // @[mshrs.scala:109:20] reg req_uop_fp_ctrl_ren2; // @[mshrs.scala:109:20] reg req_uop_fp_ctrl_ren3; // @[mshrs.scala:109:20] reg req_uop_fp_ctrl_swap12; // @[mshrs.scala:109:20] reg req_uop_fp_ctrl_swap23; // @[mshrs.scala:109:20] reg [1:0] req_uop_fp_ctrl_typeTagIn; // @[mshrs.scala:109:20] reg [1:0] req_uop_fp_ctrl_typeTagOut; // @[mshrs.scala:109:20] reg req_uop_fp_ctrl_fromint; // @[mshrs.scala:109:20] reg req_uop_fp_ctrl_toint; // @[mshrs.scala:109:20] reg req_uop_fp_ctrl_fastpipe; // @[mshrs.scala:109:20] reg req_uop_fp_ctrl_fma; // @[mshrs.scala:109:20] reg req_uop_fp_ctrl_div; // @[mshrs.scala:109:20] reg req_uop_fp_ctrl_sqrt; // @[mshrs.scala:109:20] reg req_uop_fp_ctrl_wflags; // @[mshrs.scala:109:20] reg req_uop_fp_ctrl_vec; // @[mshrs.scala:109:20] reg [4:0] req_uop_rob_idx; // @[mshrs.scala:109:20] reg [3:0] req_uop_ldq_idx; // @[mshrs.scala:109:20] reg [3:0] req_uop_stq_idx; // @[mshrs.scala:109:20] reg [1:0] req_uop_rxq_idx; // @[mshrs.scala:109:20] reg [5:0] req_uop_pdst; // @[mshrs.scala:109:20] reg [5:0] req_uop_prs1; // @[mshrs.scala:109:20] reg [5:0] req_uop_prs2; // @[mshrs.scala:109:20] reg [5:0] req_uop_prs3; // @[mshrs.scala:109:20] reg [3:0] req_uop_ppred; // @[mshrs.scala:109:20] reg req_uop_prs1_busy; // @[mshrs.scala:109:20] reg req_uop_prs2_busy; // @[mshrs.scala:109:20] reg req_uop_prs3_busy; // @[mshrs.scala:109:20] reg req_uop_ppred_busy; // @[mshrs.scala:109:20] reg [5:0] req_uop_stale_pdst; // @[mshrs.scala:109:20] reg req_uop_exception; // @[mshrs.scala:109:20] reg [63:0] req_uop_exc_cause; // @[mshrs.scala:109:20] reg [4:0] req_uop_mem_cmd; // @[mshrs.scala:109:20] reg [1:0] req_uop_mem_size; // @[mshrs.scala:109:20] reg req_uop_mem_signed; // @[mshrs.scala:109:20] reg req_uop_uses_ldq; // @[mshrs.scala:109:20] reg req_uop_uses_stq; // @[mshrs.scala:109:20] reg req_uop_is_unique; // @[mshrs.scala:109:20] reg req_uop_flush_on_commit; // @[mshrs.scala:109:20] reg [2:0] req_uop_csr_cmd; // @[mshrs.scala:109:20] reg req_uop_ldst_is_rs1; // @[mshrs.scala:109:20] reg [5:0] req_uop_ldst; // @[mshrs.scala:109:20] reg [5:0] req_uop_lrs1; // @[mshrs.scala:109:20] reg [5:0] req_uop_lrs2; // @[mshrs.scala:109:20] reg [5:0] req_uop_lrs3; // @[mshrs.scala:109:20] reg [1:0] req_uop_dst_rtype; // @[mshrs.scala:109:20] reg [1:0] req_uop_lrs1_rtype; // @[mshrs.scala:109:20] reg [1:0] req_uop_lrs2_rtype; // @[mshrs.scala:109:20] reg req_uop_frs3_en; // @[mshrs.scala:109:20] reg req_uop_fcn_dw; // @[mshrs.scala:109:20] reg [4:0] req_uop_fcn_op; // @[mshrs.scala:109:20] reg req_uop_fp_val; // @[mshrs.scala:109:20] reg [2:0] req_uop_fp_rm; // @[mshrs.scala:109:20] reg [1:0] req_uop_fp_typ; // @[mshrs.scala:109:20] reg req_uop_xcpt_pf_if; // @[mshrs.scala:109:20] reg req_uop_xcpt_ae_if; // @[mshrs.scala:109:20] reg req_uop_xcpt_ma_if; // @[mshrs.scala:109:20] reg req_uop_bp_debug_if; // @[mshrs.scala:109:20] reg req_uop_bp_xcpt_if; // @[mshrs.scala:109:20] reg [2:0] req_uop_debug_fsrc; // @[mshrs.scala:109:20] reg [2:0] req_uop_debug_tsrc; // @[mshrs.scala:109:20] reg [33:0] req_addr; // @[mshrs.scala:109:20] assign io_commit_addr_0 = req_addr; // @[mshrs.scala:36:7, :109:20] reg [63:0] req_data; // @[mshrs.scala:109:20] reg req_is_hella; // @[mshrs.scala:109:20] reg req_tag_match; // @[mshrs.scala:109:20] reg [1:0] req_old_meta_coh_state; // @[mshrs.scala:109:20] reg [21:0] req_old_meta_tag; // @[mshrs.scala:109:20] assign io_wb_req_bits_tag_0 = req_old_meta_tag; // @[mshrs.scala:36:7, :109:20] reg [1:0] req_way_en; // @[mshrs.scala:109:20] assign io_way_bits_0 = req_way_en; // @[mshrs.scala:36:7, :109:20] assign io_refill_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20] assign io_meta_write_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20] assign io_meta_read_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20] assign io_wb_req_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20] reg [4:0] req_sdq_id; // @[mshrs.scala:109:20] assign req_idx = req_addr[9:6]; // @[mshrs.scala:109:20, :110:25] assign io_idx_bits_0 = req_idx; // @[mshrs.scala:36:7, :110:25] assign io_meta_write_bits_idx_0 = req_idx; // @[mshrs.scala:36:7, :110:25] assign io_meta_read_bits_idx_0 = req_idx; // @[mshrs.scala:36:7, :110:25] assign io_wb_req_bits_idx_0 = req_idx; // @[mshrs.scala:36:7, :110:25] assign req_tag = req_addr[33:10]; // @[mshrs.scala:109:20, :111:26] assign io_tag_bits_0 = req_tag; // @[mshrs.scala:36:7, :111:26] wire [27:0] _req_block_addr_T = req_addr[33:6]; // @[mshrs.scala:109:20, :112:34] wire [33:0] req_block_addr = {_req_block_addr_T, 6'h0}; // @[mshrs.scala:112:{34,51}] reg req_needs_wb; // @[mshrs.scala:113:29] reg [1:0] new_coh_state; // @[mshrs.scala:115:24] wire [3:0] _r_T_6 = {2'h2, req_old_meta_coh_state}; // @[Metadata.scala:120:19] wire _r_T_19 = _r_T_6 == 4'h8; // @[Misc.scala:56:20] wire [2:0] _r_T_21 = _r_T_19 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20] wire _r_T_23 = _r_T_6 == 4'h9; // @[Misc.scala:56:20] wire [2:0] _r_T_25 = _r_T_23 ? 3'h2 : _r_T_21; // @[Misc.scala:38:36, :56:20] wire _r_T_27 = _r_T_6 == 4'hA; // @[Misc.scala:56:20] wire [2:0] _r_T_29 = _r_T_27 ? 3'h1 : _r_T_25; // @[Misc.scala:38:36, :56:20] wire _r_T_31 = _r_T_6 == 4'hB; // @[Misc.scala:56:20] wire _r_T_32 = _r_T_31; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_33 = _r_T_31 ? 3'h1 : _r_T_29; // @[Misc.scala:38:36, :56:20] wire _r_T_35 = _r_T_6 == 4'h4; // @[Misc.scala:56:20] wire _r_T_36 = ~_r_T_35 & _r_T_32; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_37 = _r_T_35 ? 3'h5 : _r_T_33; // @[Misc.scala:38:36, :56:20] wire _r_T_39 = _r_T_6 == 4'h5; // @[Misc.scala:56:20] wire _r_T_40 = ~_r_T_39 & _r_T_36; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_41 = _r_T_39 ? 3'h4 : _r_T_37; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_42 = {1'h0, _r_T_39}; // @[Misc.scala:38:63, :56:20] wire _r_T_43 = _r_T_6 == 4'h6; // @[Misc.scala:56:20] wire _r_T_44 = ~_r_T_43 & _r_T_40; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_45 = _r_T_43 ? 3'h0 : _r_T_41; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_46 = _r_T_43 ? 2'h1 : _r_T_42; // @[Misc.scala:38:63, :56:20] wire _r_T_47 = _r_T_6 == 4'h7; // @[Misc.scala:56:20] wire _r_T_48 = _r_T_47 \| _r_T_44; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_49 = _r_T_47 ? 3'h0 : _r_T_45; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_50 = _r_T_47 ? 2'h1 : _r_T_46; // @[Misc.scala:38:63, :56:20] wire _r_T_51 = _r_T_6 == 4'h0; // @[Misc.scala:56:20] wire _r_T_52 = ~_r_T_51 & _r_T_48; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_53 = _r_T_51 ? 3'h5 : _r_T_49; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_54 = _r_T_51 ? 2'h0 : _r_T_50; // @[Misc.scala:38:63, :56:20] wire _r_T_55 = _r_T_6 == 4'h1; // @[Misc.scala:56:20] wire _r_T_56 = ~_r_T_55 & _r_T_52; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_57 = _r_T_55 ? 3'h4 : _r_T_53; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_58 = _r_T_55 ? 2'h1 : _r_T_54; // @[Misc.scala:38:63, :56:20] wire _r_T_59 = _r_T_6 == 4'h2; // @[Misc.scala:56:20] wire _r_T_60 = ~_r_T_59 & _r_T_56; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_61 = _r_T_59 ? 3'h3 : _r_T_57; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_62 = _r_T_59 ? 2'h2 : _r_T_58; // @[Misc.scala:38:63, :56:20] wire _r_T_63 = _r_T_6 == 4'h3; // @[Misc.scala:56:20] wire r_1 = _r_T_63 \| _r_T_60; // @[Misc.scala:38:9, :56:20] assign shrink_param = _r_T_63 ? 3'h3 : _r_T_61; // @[Misc.scala:38:36, :56:20] assign io_wb_req_bits_param_0 = shrink_param; // @[Misc.scala:38:36] wire [1:0] r_3 = _r_T_63 ? 2'h2 : _r_T_62; // @[Misc.scala:38:63, :56:20] wire [1:0] coh_on_clear_state = r_3; // @[Misc.scala:38:63] wire _GEN = req_uop_mem_cmd == 5'h1; // @[Consts.scala:90:32] wire _grow_param_r_c_cat_T; // @[Consts.scala:90:32] assign _grow_param_r_c_cat_T = _GEN; // @[Consts.scala:90:32] wire _grow_param_r_c_cat_T_23; // @[Consts.scala:90:32] assign _grow_param_r_c_cat_T_23 = _GEN; // @[Consts.scala:90:32] wire _coh_on_grant_c_cat_T; // @[Consts.scala:90:32] assign _coh_on_grant_c_cat_T = _GEN; // @[Consts.scala:90:32] wire _coh_on_grant_c_cat_T_23; // @[Consts.scala:90:32] assign _coh_on_grant_c_cat_T_23 = _GEN; // @[Consts.scala:90:32] wire _r1_c_cat_T; // @[Consts.scala:90:32] assign _r1_c_cat_T = _GEN; // @[Consts.scala:90:32] wire _r1_c_cat_T_23; // @[Consts.scala:90:32] assign _r1_c_cat_T_23 = _GEN; // @[Consts.scala:90:32] wire _needs_second_acq_T_27; // @[Consts.scala:90:32] assign _needs_second_acq_T_27 = _GEN; // @[Consts.scala:90:32] wire _GEN_0 = req_uop_mem_cmd == 5'h11; // @[Consts.scala:90:49] wire _grow_param_r_c_cat_T_1; // @[Consts.scala:90:49] assign _grow_param_r_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49] wire _grow_param_r_c_cat_T_24; // @[Consts.scala:90:49] assign _grow_param_r_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49] wire _coh_on_grant_c_cat_T_1; // @[Consts.scala:90:49] assign _coh_on_grant_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49] wire _coh_on_grant_c_cat_T_24; // @[Consts.scala:90:49] assign _coh_on_grant_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49] wire _r1_c_cat_T_1; // @[Consts.scala:90:49] assign _r1_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49] wire _r1_c_cat_T_24; // @[Consts.scala:90:49] assign _r1_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49] wire _needs_second_acq_T_28; // @[Consts.scala:90:49] assign _needs_second_acq_T_28 = _GEN_0; // @[Consts.scala:90:49] wire _grow_param_r_c_cat_T_2 = _grow_param_r_c_cat_T \| _grow_param_r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _GEN_1 = req_uop_mem_cmd == 5'h7; // @[Consts.scala:90:66] wire _grow_param_r_c_cat_T_3; // @[Consts.scala:90:66] assign _grow_param_r_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66] wire _grow_param_r_c_cat_T_26; // @[Consts.scala:90:66] assign _grow_param_r_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66] wire _coh_on_grant_c_cat_T_3; // @[Consts.scala:90:66] assign _coh_on_grant_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66] wire _coh_on_grant_c_cat_T_26; // @[Consts.scala:90:66] assign _coh_on_grant_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66] wire _r1_c_cat_T_3; // @[Consts.scala:90:66] assign _r1_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66] wire _r1_c_cat_T_26; // @[Consts.scala:90:66] assign _r1_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66] wire _needs_second_acq_T_30; // @[Consts.scala:90:66] assign _needs_second_acq_T_30 = _GEN_1; // @[Consts.scala:90:66] wire _grow_param_r_c_cat_T_4 = _grow_param_r_c_cat_T_2 \| _grow_param_r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _GEN_2 = req_uop_mem_cmd == 5'h4; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_5; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_5 = _GEN_2; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_28; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_28 = _GEN_2; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_5; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_5 = _GEN_2; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_28; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_28 = _GEN_2; // @[package.scala:16:47] wire _r1_c_cat_T_5; // @[package.scala:16:47] assign _r1_c_cat_T_5 = _GEN_2; // @[package.scala:16:47] wire _r1_c_cat_T_28; // @[package.scala:16:47] assign _r1_c_cat_T_28 = _GEN_2; // @[package.scala:16:47] wire _needs_second_acq_T_32; // @[package.scala:16:47] assign _needs_second_acq_T_32 = _GEN_2; // @[package.scala:16:47] wire _GEN_3 = req_uop_mem_cmd == 5'h9; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_6; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_6 = _GEN_3; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_29; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_29 = _GEN_3; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_6; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_6 = _GEN_3; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_29; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_29 = _GEN_3; // @[package.scala:16:47] wire _r1_c_cat_T_6; // @[package.scala:16:47] assign _r1_c_cat_T_6 = _GEN_3; // @[package.scala:16:47] wire _r1_c_cat_T_29; // @[package.scala:16:47] assign _r1_c_cat_T_29 = _GEN_3; // @[package.scala:16:47] wire _needs_second_acq_T_33; // @[package.scala:16:47] assign _needs_second_acq_T_33 = _GEN_3; // @[package.scala:16:47] wire _GEN_4 = req_uop_mem_cmd == 5'hA; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_7; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_7 = _GEN_4; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_30; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_30 = _GEN_4; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_7; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_7 = _GEN_4; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_30; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_30 = _GEN_4; // @[package.scala:16:47] wire _r1_c_cat_T_7; // @[package.scala:16:47] assign _r1_c_cat_T_7 = _GEN_4; // @[package.scala:16:47] wire _r1_c_cat_T_30; // @[package.scala:16:47] assign _r1_c_cat_T_30 = _GEN_4; // @[package.scala:16:47] wire _needs_second_acq_T_34; // @[package.scala:16:47] assign _needs_second_acq_T_34 = _GEN_4; // @[package.scala:16:47] wire _GEN_5 = req_uop_mem_cmd == 5'hB; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_8; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_8 = _GEN_5; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_31; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_31 = _GEN_5; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_8; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_8 = _GEN_5; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_31; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_31 = _GEN_5; // @[package.scala:16:47] wire _r1_c_cat_T_8; // @[package.scala:16:47] assign _r1_c_cat_T_8 = _GEN_5; // @[package.scala:16:47] wire _r1_c_cat_T_31; // @[package.scala:16:47] assign _r1_c_cat_T_31 = _GEN_5; // @[package.scala:16:47] wire _needs_second_acq_T_35; // @[package.scala:16:47] assign _needs_second_acq_T_35 = _GEN_5; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_9 = _grow_param_r_c_cat_T_5 \| _grow_param_r_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_10 = _grow_param_r_c_cat_T_9 \| _grow_param_r_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_11 = _grow_param_r_c_cat_T_10 \| _grow_param_r_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _GEN_6 = req_uop_mem_cmd == 5'h8; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_12; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_12 = _GEN_6; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_35; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_35 = _GEN_6; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_12; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_12 = _GEN_6; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_35; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_35 = _GEN_6; // @[package.scala:16:47] wire _r1_c_cat_T_12; // @[package.scala:16:47] assign _r1_c_cat_T_12 = _GEN_6; // @[package.scala:16:47] wire _r1_c_cat_T_35; // @[package.scala:16:47] assign _r1_c_cat_T_35 = _GEN_6; // @[package.scala:16:47] wire _needs_second_acq_T_39; // @[package.scala:16:47] assign _needs_second_acq_T_39 = _GEN_6; // @[package.scala:16:47] wire _GEN_7 = req_uop_mem_cmd == 5'hC; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_13; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_13 = _GEN_7; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_36; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_36 = _GEN_7; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_13; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_13 = _GEN_7; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_36; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_36 = _GEN_7; // @[package.scala:16:47] wire _r1_c_cat_T_13; // @[package.scala:16:47] assign _r1_c_cat_T_13 = _GEN_7; // @[package.scala:16:47] wire _r1_c_cat_T_36; // @[package.scala:16:47] assign _r1_c_cat_T_36 = _GEN_7; // @[package.scala:16:47] wire _needs_second_acq_T_40; // @[package.scala:16:47] assign _needs_second_acq_T_40 = _GEN_7; // @[package.scala:16:47] wire _GEN_8 = req_uop_mem_cmd == 5'hD; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_14; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_14 = _GEN_8; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_37; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_37 = _GEN_8; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_14; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_14 = _GEN_8; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_37; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_37 = _GEN_8; // @[package.scala:16:47] wire _r1_c_cat_T_14; // @[package.scala:16:47] assign _r1_c_cat_T_14 = _GEN_8; // @[package.scala:16:47] wire _r1_c_cat_T_37; // @[package.scala:16:47] assign _r1_c_cat_T_37 = _GEN_8; // @[package.scala:16:47] wire _needs_second_acq_T_41; // @[package.scala:16:47] assign _needs_second_acq_T_41 = _GEN_8; // @[package.scala:16:47] wire _GEN_9 = req_uop_mem_cmd == 5'hE; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_15; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_15 = _GEN_9; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_38; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_38 = _GEN_9; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_15; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_15 = _GEN_9; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_38; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_38 = _GEN_9; // @[package.scala:16:47] wire _r1_c_cat_T_15; // @[package.scala:16:47] assign _r1_c_cat_T_15 = _GEN_9; // @[package.scala:16:47] wire _r1_c_cat_T_38; // @[package.scala:16:47] assign _r1_c_cat_T_38 = _GEN_9; // @[package.scala:16:47] wire _needs_second_acq_T_42; // @[package.scala:16:47] assign _needs_second_acq_T_42 = _GEN_9; // @[package.scala:16:47] wire _GEN_10 = req_uop_mem_cmd == 5'hF; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_16; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_16 = _GEN_10; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_39; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_39 = _GEN_10; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_16; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_16 = _GEN_10; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_39; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_39 = _GEN_10; // @[package.scala:16:47] wire _r1_c_cat_T_16; // @[package.scala:16:47] assign _r1_c_cat_T_16 = _GEN_10; // @[package.scala:16:47] wire _r1_c_cat_T_39; // @[package.scala:16:47] assign _r1_c_cat_T_39 = _GEN_10; // @[package.scala:16:47] wire _needs_second_acq_T_43; // @[package.scala:16:47] assign _needs_second_acq_T_43 = _GEN_10; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_17 = _grow_param_r_c_cat_T_12 \| _grow_param_r_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_18 = _grow_param_r_c_cat_T_17 \| _grow_param_r_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_19 = _grow_param_r_c_cat_T_18 \| _grow_param_r_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_20 = _grow_param_r_c_cat_T_19 \| _grow_param_r_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_21 = _grow_param_r_c_cat_T_11 \| _grow_param_r_c_cat_T_20; // @[package.scala:81:59] wire _grow_param_r_c_cat_T_22 = _grow_param_r_c_cat_T_4 \| _grow_param_r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _grow_param_r_c_cat_T_25 = _grow_param_r_c_cat_T_23 \| _grow_param_r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _grow_param_r_c_cat_T_27 = _grow_param_r_c_cat_T_25 \| _grow_param_r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _grow_param_r_c_cat_T_32 = _grow_param_r_c_cat_T_28 \| _grow_param_r_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_33 = _grow_param_r_c_cat_T_32 \| _grow_param_r_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_34 = _grow_param_r_c_cat_T_33 \| _grow_param_r_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_40 = _grow_param_r_c_cat_T_35 \| _grow_param_r_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_41 = _grow_param_r_c_cat_T_40 \| _grow_param_r_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_42 = _grow_param_r_c_cat_T_41 \| _grow_param_r_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_43 = _grow_param_r_c_cat_T_42 \| _grow_param_r_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_44 = _grow_param_r_c_cat_T_34 \| _grow_param_r_c_cat_T_43; // @[package.scala:81:59] wire _grow_param_r_c_cat_T_45 = _grow_param_r_c_cat_T_27 \| _grow_param_r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _GEN_11 = req_uop_mem_cmd == 5'h3; // @[Consts.scala:91:54] wire _grow_param_r_c_cat_T_46; // @[Consts.scala:91:54] assign _grow_param_r_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54] wire _coh_on_grant_c_cat_T_46; // @[Consts.scala:91:54] assign _coh_on_grant_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54] wire _r1_c_cat_T_46; // @[Consts.scala:91:54] assign _r1_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54] wire _needs_second_acq_T_50; // @[Consts.scala:91:54] assign _needs_second_acq_T_50 = _GEN_11; // @[Consts.scala:91:54] wire _grow_param_r_c_cat_T_47 = _grow_param_r_c_cat_T_45 \| _grow_param_r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _GEN_12 = req_uop_mem_cmd == 5'h6; // @[Consts.scala:91:71] wire _grow_param_r_c_cat_T_48; // @[Consts.scala:91:71] assign _grow_param_r_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71] wire _coh_on_grant_c_cat_T_48; // @[Consts.scala:91:71] assign _coh_on_grant_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71] wire _r1_c_cat_T_48; // @[Consts.scala:91:71] assign _r1_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71] wire _needs_second_acq_T_52; // @[Consts.scala:91:71] assign _needs_second_acq_T_52 = _GEN_12; // @[Consts.scala:91:71] wire _grow_param_r_c_cat_T_49 = _grow_param_r_c_cat_T_47 \| _grow_param_r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] grow_param_r_c = {_grow_param_r_c_cat_T_22, _grow_param_r_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _grow_param_r_T = {grow_param_r_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19] wire _grow_param_r_T_25 = _grow_param_r_T == 4'hC; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_27 = {1'h0, _grow_param_r_T_25}; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_28 = _grow_param_r_T == 4'hD; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_30 = _grow_param_r_T_28 ? 2'h2 : _grow_param_r_T_27; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_31 = _grow_param_r_T == 4'h4; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_33 = _grow_param_r_T_31 ? 2'h1 : _grow_param_r_T_30; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_34 = _grow_param_r_T == 4'h5; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_36 = _grow_param_r_T_34 ? 2'h2 : _grow_param_r_T_33; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_37 = _grow_param_r_T == 4'h0; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_39 = _grow_param_r_T_37 ? 2'h0 : _grow_param_r_T_36; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_40 = _grow_param_r_T == 4'hE; // @[Misc.scala:49:20] wire _grow_param_r_T_41 = _grow_param_r_T_40; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_42 = _grow_param_r_T_40 ? 2'h3 : _grow_param_r_T_39; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_43 = &_grow_param_r_T; // @[Misc.scala:49:20] wire _grow_param_r_T_44 = _grow_param_r_T_43 \| _grow_param_r_T_41; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_45 = _grow_param_r_T_43 ? 2'h3 : _grow_param_r_T_42; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_46 = _grow_param_r_T == 4'h6; // @[Misc.scala:49:20] wire _grow_param_r_T_47 = _grow_param_r_T_46 \| _grow_param_r_T_44; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_48 = _grow_param_r_T_46 ? 2'h2 : _grow_param_r_T_45; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_49 = _grow_param_r_T == 4'h7; // @[Misc.scala:49:20] wire _grow_param_r_T_50 = _grow_param_r_T_49 \| _grow_param_r_T_47; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_51 = _grow_param_r_T_49 ? 2'h3 : _grow_param_r_T_48; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_52 = _grow_param_r_T == 4'h1; // @[Misc.scala:49:20] wire _grow_param_r_T_53 = _grow_param_r_T_52 \| _grow_param_r_T_50; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_54 = _grow_param_r_T_52 ? 2'h1 : _grow_param_r_T_51; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_55 = _grow_param_r_T == 4'h2; // @[Misc.scala:49:20] wire _grow_param_r_T_56 = _grow_param_r_T_55 \| _grow_param_r_T_53; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_57 = _grow_param_r_T_55 ? 2'h2 : _grow_param_r_T_54; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_58 = _grow_param_r_T == 4'h3; // @[Misc.scala:49:20] wire grow_param_r_1 = _grow_param_r_T_58 \| _grow_param_r_T_56; // @[Misc.scala:35:9, :49:20] wire [1:0] grow_param = _grow_param_r_T_58 ? 2'h3 : _grow_param_r_T_57; // @[Misc.scala:35:36, :49:20] wire [1:0] grow_param_meta_state = grow_param; // @[Misc.scala:35:36] wire _coh_on_grant_c_cat_T_2 = _coh_on_grant_c_cat_T \| _coh_on_grant_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _coh_on_grant_c_cat_T_4 = _coh_on_grant_c_cat_T_2 \| _coh_on_grant_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _coh_on_grant_c_cat_T_9 = _coh_on_grant_c_cat_T_5 \| _coh_on_grant_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_10 = _coh_on_grant_c_cat_T_9 \| _coh_on_grant_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_11 = _coh_on_grant_c_cat_T_10 \| _coh_on_grant_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_17 = _coh_on_grant_c_cat_T_12 \| _coh_on_grant_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_18 = _coh_on_grant_c_cat_T_17 \| _coh_on_grant_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_19 = _coh_on_grant_c_cat_T_18 \| _coh_on_grant_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_20 = _coh_on_grant_c_cat_T_19 \| _coh_on_grant_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_21 = _coh_on_grant_c_cat_T_11 \| _coh_on_grant_c_cat_T_20; // @[package.scala:81:59] wire _coh_on_grant_c_cat_T_22 = _coh_on_grant_c_cat_T_4 \| _coh_on_grant_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _coh_on_grant_c_cat_T_25 = _coh_on_grant_c_cat_T_23 \| _coh_on_grant_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _coh_on_grant_c_cat_T_27 = _coh_on_grant_c_cat_T_25 \| _coh_on_grant_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _coh_on_grant_c_cat_T_32 = _coh_on_grant_c_cat_T_28 \| _coh_on_grant_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_33 = _coh_on_grant_c_cat_T_32 \| _coh_on_grant_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_34 = _coh_on_grant_c_cat_T_33 \| _coh_on_grant_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_40 = _coh_on_grant_c_cat_T_35 \| _coh_on_grant_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_41 = _coh_on_grant_c_cat_T_40 \| _coh_on_grant_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_42 = _coh_on_grant_c_cat_T_41 \| _coh_on_grant_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_43 = _coh_on_grant_c_cat_T_42 \| _coh_on_grant_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_44 = _coh_on_grant_c_cat_T_34 \| _coh_on_grant_c_cat_T_43; // @[package.scala:81:59] wire _coh_on_grant_c_cat_T_45 = _coh_on_grant_c_cat_T_27 \| _coh_on_grant_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _coh_on_grant_c_cat_T_47 = _coh_on_grant_c_cat_T_45 \| _coh_on_grant_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _coh_on_grant_c_cat_T_49 = _coh_on_grant_c_cat_T_47 \| _coh_on_grant_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] coh_on_grant_c = {_coh_on_grant_c_cat_T_22, _coh_on_grant_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _coh_on_grant_T = {coh_on_grant_c, io_mem_grant_bits_param_0}; // @[Metadata.scala:29:18, :84:18] wire _coh_on_grant_T_9 = _coh_on_grant_T == 4'h1; // @[Metadata.scala:84:{18,38}] wire [1:0] _coh_on_grant_T_10 = {1'h0, _coh_on_grant_T_9}; // @[Metadata.scala:84:38] wire _coh_on_grant_T_11 = _coh_on_grant_T == 4'h0; // @[Metadata.scala:84:{18,38}] wire [1:0] _coh_on_grant_T_12 = _coh_on_grant_T_11 ? 2'h2 : _coh_on_grant_T_10; // @[Metadata.scala:84:38] wire _coh_on_grant_T_13 = _coh_on_grant_T == 4'h4; // @[Metadata.scala:84:{18,38}] wire [1:0] _coh_on_grant_T_14 = _coh_on_grant_T_13 ? 2'h2 : _coh_on_grant_T_12; // @[Metadata.scala:84:38] wire _coh_on_grant_T_15 = _coh_on_grant_T == 4'hC; // @[Metadata.scala:84:{18,38}] wire [1:0] _coh_on_grant_T_16 = _coh_on_grant_T_15 ? 2'h3 : _coh_on_grant_T_14; // @[Metadata.scala:84:38] assign coh_on_grant_state = _coh_on_grant_T_16; // @[Metadata.scala:84:38, :160:20] assign io_commit_coh_state_0 = coh_on_grant_state; // @[Metadata.scala:160:20] wire _r1_c_cat_T_2 = _r1_c_cat_T \| _r1_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _r1_c_cat_T_4 = _r1_c_cat_T_2 \| _r1_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _r1_c_cat_T_9 = _r1_c_cat_T_5 \| _r1_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_10 = _r1_c_cat_T_9 \| _r1_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_11 = _r1_c_cat_T_10 \| _r1_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_17 = _r1_c_cat_T_12 \| _r1_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_18 = _r1_c_cat_T_17 \| _r1_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_19 = _r1_c_cat_T_18 \| _r1_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_20 = _r1_c_cat_T_19 \| _r1_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_21 = _r1_c_cat_T_11 \| _r1_c_cat_T_20; // @[package.scala:81:59] wire _r1_c_cat_T_22 = _r1_c_cat_T_4 \| _r1_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _r1_c_cat_T_25 = _r1_c_cat_T_23 \| _r1_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _r1_c_cat_T_27 = _r1_c_cat_T_25 \| _r1_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _r1_c_cat_T_32 = _r1_c_cat_T_28 \| _r1_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_33 = _r1_c_cat_T_32 \| _r1_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_34 = _r1_c_cat_T_33 \| _r1_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_40 = _r1_c_cat_T_35 \| _r1_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_41 = _r1_c_cat_T_40 \| _r1_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_42 = _r1_c_cat_T_41 \| _r1_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_43 = _r1_c_cat_T_42 \| _r1_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_44 = _r1_c_cat_T_34 \| _r1_c_cat_T_43; // @[package.scala:81:59] wire _r1_c_cat_T_45 = _r1_c_cat_T_27 \| _r1_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _r1_c_cat_T_47 = _r1_c_cat_T_45 \| _r1_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _r1_c_cat_T_49 = _r1_c_cat_T_47 \| _r1_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] r1_c = {_r1_c_cat_T_22, _r1_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _r1_T = {r1_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19] wire _r1_T_25 = _r1_T == 4'hC; // @[Misc.scala:49:20] wire [1:0] _r1_T_27 = {1'h0, _r1_T_25}; // @[Misc.scala:35:36, :49:20] wire _r1_T_28 = _r1_T == 4'hD; // @[Misc.scala:49:20] wire [1:0] _r1_T_30 = _r1_T_28 ? 2'h2 : _r1_T_27; // @[Misc.scala:35:36, :49:20] wire _r1_T_31 = _r1_T == 4'h4; // @[Misc.scala:49:20] wire [1:0] _r1_T_33 = _r1_T_31 ? 2'h1 : _r1_T_30; // @[Misc.scala:35:36, :49:20] wire _r1_T_34 = _r1_T == 4'h5; // @[Misc.scala:49:20] wire [1:0] _r1_T_36 = _r1_T_34 ? 2'h2 : _r1_T_33; // @[Misc.scala:35:36, :49:20] wire _r1_T_37 = _r1_T == 4'h0; // @[Misc.scala:49:20] wire [1:0] _r1_T_39 = _r1_T_37 ? 2'h0 : _r1_T_36; // @[Misc.scala:35:36, :49:20] wire _r1_T_40 = _r1_T == 4'hE; // @[Misc.scala:49:20] wire _r1_T_41 = _r1_T_40; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_42 = _r1_T_40 ? 2'h3 : _r1_T_39; // @[Misc.scala:35:36, :49:20] wire _r1_T_43 = &_r1_T; // @[Misc.scala:49:20] wire _r1_T_44 = _r1_T_43 \| _r1_T_41; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_45 = _r1_T_43 ? 2'h3 : _r1_T_42; // @[Misc.scala:35:36, :49:20] wire _r1_T_46 = _r1_T == 4'h6; // @[Misc.scala:49:20] wire _r1_T_47 = _r1_T_46 \| _r1_T_44; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_48 = _r1_T_46 ? 2'h2 : _r1_T_45; // @[Misc.scala:35:36, :49:20] wire _r1_T_49 = _r1_T == 4'h7; // @[Misc.scala:49:20] wire _r1_T_50 = _r1_T_49 \| _r1_T_47; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_51 = _r1_T_49 ? 2'h3 : _r1_T_48; // @[Misc.scala:35:36, :49:20] wire _r1_T_52 = _r1_T == 4'h1; // @[Misc.scala:49:20] wire _r1_T_53 = _r1_T_52 \| _r1_T_50; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_54 = _r1_T_52 ? 2'h1 : _r1_T_51; // @[Misc.scala:35:36, :49:20] wire _r1_T_55 = _r1_T == 4'h2; // @[Misc.scala:49:20] wire _r1_T_56 = _r1_T_55 \| _r1_T_53; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_57 = _r1_T_55 ? 2'h2 : _r1_T_54; // @[Misc.scala:35:36, :49:20] wire _r1_T_58 = _r1_T == 4'h3; // @[Misc.scala:49:20] wire r1_1 = _r1_T_58 \| _r1_T_56; // @[Misc.scala:35:9, :49:20] wire [1:0] r1_2 = _r1_T_58 ? 2'h3 : _r1_T_57; // @[Misc.scala:35:36, :49:20] wire _GEN_13 = io_req_uop_mem_cmd_0 == 5'h1; // @[Consts.scala:90:32] wire _r2_c_cat_T; // @[Consts.scala:90:32] assign _r2_c_cat_T = _GEN_13; // @[Consts.scala:90:32] wire _r2_c_cat_T_23; // @[Consts.scala:90:32] assign _r2_c_cat_T_23 = _GEN_13; // @[Consts.scala:90:32] wire _needs_second_acq_T; // @[Consts.scala:90:32] assign _needs_second_acq_T = _GEN_13; // @[Consts.scala:90:32] wire _dirties_cat_T; // @[Consts.scala:90:32] assign _dirties_cat_T = _GEN_13; // @[Consts.scala:90:32] wire _dirties_cat_T_23; // @[Consts.scala:90:32] assign _dirties_cat_T_23 = _GEN_13; // @[Consts.scala:90:32] wire _state_r_c_cat_T; // @[Consts.scala:90:32] assign _state_r_c_cat_T = _GEN_13; // @[Consts.scala:90:32] wire _state_r_c_cat_T_23; // @[Consts.scala:90:32] assign _state_r_c_cat_T_23 = _GEN_13; // @[Consts.scala:90:32] wire _state_T_3; // @[Consts.scala:90:32] assign _state_T_3 = _GEN_13; // @[Consts.scala:90:32] wire _r_c_cat_T_50; // @[Consts.scala:90:32] assign _r_c_cat_T_50 = _GEN_13; // @[Consts.scala:90:32] wire _r_c_cat_T_73; // @[Consts.scala:90:32] assign _r_c_cat_T_73 = _GEN_13; // @[Consts.scala:90:32] wire _state_r_c_cat_T_50; // @[Consts.scala:90:32] assign _state_r_c_cat_T_50 = _GEN_13; // @[Consts.scala:90:32] wire _state_r_c_cat_T_73; // @[Consts.scala:90:32] assign _state_r_c_cat_T_73 = _GEN_13; // @[Consts.scala:90:32] wire _state_T_37; // @[Consts.scala:90:32] assign _state_T_37 = _GEN_13; // @[Consts.scala:90:32] wire _GEN_14 = io_req_uop_mem_cmd_0 == 5'h11; // @[Consts.scala:90:49] wire _r2_c_cat_T_1; // @[Consts.scala:90:49] assign _r2_c_cat_T_1 = _GEN_14; // @[Consts.scala:90:49] wire _r2_c_cat_T_24; // @[Consts.scala:90:49] assign _r2_c_cat_T_24 = _GEN_14; // @[Consts.scala:90:49] wire _needs_second_acq_T_1; // @[Consts.scala:90:49] assign _needs_second_acq_T_1 = _GEN_14; // @[Consts.scala:90:49] wire _dirties_cat_T_1; // @[Consts.scala:90:49] assign _dirties_cat_T_1 = _GEN_14; // @[Consts.scala:90:49] wire _dirties_cat_T_24; // @[Consts.scala:90:49] assign _dirties_cat_T_24 = _GEN_14; // @[Consts.scala:90:49] wire _state_r_c_cat_T_1; // @[Consts.scala:90:49] assign _state_r_c_cat_T_1 = _GEN_14; // @[Consts.scala:90:49] wire _state_r_c_cat_T_24; // @[Consts.scala:90:49] assign _state_r_c_cat_T_24 = _GEN_14; // @[Consts.scala:90:49] wire _state_T_4; // @[Consts.scala:90:49] assign _state_T_4 = _GEN_14; // @[Consts.scala:90:49] wire _r_c_cat_T_51; // @[Consts.scala:90:49] assign _r_c_cat_T_51 = _GEN_14; // @[Consts.scala:90:49] wire _r_c_cat_T_74; // @[Consts.scala:90:49] assign _r_c_cat_T_74 = _GEN_14; // @[Consts.scala:90:49] wire _state_r_c_cat_T_51; // @[Consts.scala:90:49] assign _state_r_c_cat_T_51 = _GEN_14; // @[Consts.scala:90:49] wire _state_r_c_cat_T_74; // @[Consts.scala:90:49] assign _state_r_c_cat_T_74 = _GEN_14; // @[Consts.scala:90:49] wire _state_T_38; // @[Consts.scala:90:49] assign _state_T_38 = _GEN_14; // @[Consts.scala:90:49] wire _r2_c_cat_T_2 = _r2_c_cat_T \| _r2_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _GEN_15 = io_req_uop_mem_cmd_0 == 5'h7; // @[Consts.scala:90:66] wire _r2_c_cat_T_3; // @[Consts.scala:90:66] assign _r2_c_cat_T_3 = _GEN_15; // @[Consts.scala:90:66] wire _r2_c_cat_T_26; // @[Consts.scala:90:66] assign _r2_c_cat_T_26 = _GEN_15; // @[Consts.scala:90:66] wire _needs_second_acq_T_3; // @[Consts.scala:90:66] assign _needs_second_acq_T_3 = _GEN_15; // @[Consts.scala:90:66] wire _dirties_cat_T_3; // @[Consts.scala:90:66] assign _dirties_cat_T_3 = _GEN_15; // @[Consts.scala:90:66] wire _dirties_cat_T_26; // @[Consts.scala:90:66] assign _dirties_cat_T_26 = _GEN_15; // @[Consts.scala:90:66] wire _state_r_c_cat_T_3; // @[Consts.scala:90:66] assign _state_r_c_cat_T_3 = _GEN_15; // @[Consts.scala:90:66] wire _state_r_c_cat_T_26; // @[Consts.scala:90:66] assign _state_r_c_cat_T_26 = _GEN_15; // @[Consts.scala:90:66] wire _state_T_6; // @[Consts.scala:90:66] assign _state_T_6 = _GEN_15; // @[Consts.scala:90:66] wire _r_c_cat_T_53; // @[Consts.scala:90:66] assign _r_c_cat_T_53 = _GEN_15; // @[Consts.scala:90:66] wire _r_c_cat_T_76; // @[Consts.scala:90:66] assign _r_c_cat_T_76 = _GEN_15; // @[Consts.scala:90:66] wire _state_r_c_cat_T_53; // @[Consts.scala:90:66] assign _state_r_c_cat_T_53 = _GEN_15; // @[Consts.scala:90:66] wire _state_r_c_cat_T_76; // @[Consts.scala:90:66] assign _state_r_c_cat_T_76 = _GEN_15; // @[Consts.scala:90:66] wire _state_T_40; // @[Consts.scala:90:66] assign _state_T_40 = _GEN_15; // @[Consts.scala:90:66] wire _r2_c_cat_T_4 = _r2_c_cat_T_2 \| _r2_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _GEN_16 = io_req_uop_mem_cmd_0 == 5'h4; // @[package.scala:16:47] wire _r2_c_cat_T_5; // @[package.scala:16:47] assign _r2_c_cat_T_5 = _GEN_16; // @[package.scala:16:47] wire _r2_c_cat_T_28; // @[package.scala:16:47] assign _r2_c_cat_T_28 = _GEN_16; // @[package.scala:16:47] wire _needs_second_acq_T_5; // @[package.scala:16:47] assign _needs_second_acq_T_5 = _GEN_16; // @[package.scala:16:47] wire _dirties_cat_T_5; // @[package.scala:16:47] assign _dirties_cat_T_5 = _GEN_16; // @[package.scala:16:47] wire _dirties_cat_T_28; // @[package.scala:16:47] assign _dirties_cat_T_28 = _GEN_16; // @[package.scala:16:47] wire _state_r_c_cat_T_5; // @[package.scala:16:47] assign _state_r_c_cat_T_5 = _GEN_16; // @[package.scala:16:47] wire _state_r_c_cat_T_28; // @[package.scala:16:47] assign _state_r_c_cat_T_28 = _GEN_16; // @[package.scala:16:47] wire _state_T_8; // @[package.scala:16:47] assign _state_T_8 = _GEN_16; // @[package.scala:16:47] wire _r_c_cat_T_55; // @[package.scala:16:47] assign _r_c_cat_T_55 = _GEN_16; // @[package.scala:16:47] wire _r_c_cat_T_78; // @[package.scala:16:47] assign _r_c_cat_T_78 = _GEN_16; // @[package.scala:16:47] wire _state_r_c_cat_T_55; // @[package.scala:16:47] assign _state_r_c_cat_T_55 = _GEN_16; // @[package.scala:16:47] wire _state_r_c_cat_T_78; // @[package.scala:16:47] assign _state_r_c_cat_T_78 = _GEN_16; // @[package.scala:16:47] wire _state_T_42; // @[package.scala:16:47] assign _state_T_42 = _GEN_16; // @[package.scala:16:47] wire _GEN_17 = io_req_uop_mem_cmd_0 == 5'h9; // @[package.scala:16:47] wire _r2_c_cat_T_6; // @[package.scala:16:47] assign _r2_c_cat_T_6 = _GEN_17; // @[package.scala:16:47] wire _r2_c_cat_T_29; // @[package.scala:16:47] assign _r2_c_cat_T_29 = _GEN_17; // @[package.scala:16:47] wire _needs_second_acq_T_6; // @[package.scala:16:47] assign _needs_second_acq_T_6 = _GEN_17; // @[package.scala:16:47] wire _dirties_cat_T_6; // @[package.scala:16:47] assign _dirties_cat_T_6 = _GEN_17; // @[package.scala:16:47] wire _dirties_cat_T_29; // @[package.scala:16:47] assign _dirties_cat_T_29 = _GEN_17; // @[package.scala:16:47] wire _state_r_c_cat_T_6; // @[package.scala:16:47] assign _state_r_c_cat_T_6 = _GEN_17; // @[package.scala:16:47] wire _state_r_c_cat_T_29; // @[package.scala:16:47] assign _state_r_c_cat_T_29 = _GEN_17; // @[package.scala:16:47] wire _state_T_9; // @[package.scala:16:47] assign _state_T_9 = _GEN_17; // @[package.scala:16:47] wire _r_c_cat_T_56; // @[package.scala:16:47] assign _r_c_cat_T_56 = _GEN_17; // @[package.scala:16:47] wire _r_c_cat_T_79; // @[package.scala:16:47] assign _r_c_cat_T_79 = _GEN_17; // @[package.scala:16:47] wire _state_r_c_cat_T_56; // @[package.scala:16:47] assign _state_r_c_cat_T_56 = _GEN_17; // @[package.scala:16:47] wire _state_r_c_cat_T_79; // @[package.scala:16:47] assign _state_r_c_cat_T_79 = _GEN_17; // @[package.scala:16:47] wire _state_T_43; // @[package.scala:16:47] assign _state_T_43 = _GEN_17; // @[package.scala:16:47] wire _GEN_18 = io_req_uop_mem_cmd_0 == 5'hA; // @[package.scala:16:47] wire _r2_c_cat_T_7; // @[package.scala:16:47] assign _r2_c_cat_T_7 = _GEN_18; // @[package.scala:16:47] wire _r2_c_cat_T_30; // @[package.scala:16:47] assign _r2_c_cat_T_30 = _GEN_18; // @[package.scala:16:47] wire _needs_second_acq_T_7; // @[package.scala:16:47] assign _needs_second_acq_T_7 = _GEN_18; // @[package.scala:16:47] wire _dirties_cat_T_7; // @[package.scala:16:47] assign _dirties_cat_T_7 = _GEN_18; // @[package.scala:16:47] wire _dirties_cat_T_30; // @[package.scala:16:47] assign _dirties_cat_T_30 = _GEN_18; // @[package.scala:16:47] wire _state_r_c_cat_T_7; // @[package.scala:16:47] assign _state_r_c_cat_T_7 = _GEN_18; // @[package.scala:16:47] wire _state_r_c_cat_T_30; // @[package.scala:16:47] assign _state_r_c_cat_T_30 = _GEN_18; // @[package.scala:16:47] wire _state_T_10; // @[package.scala:16:47] assign _state_T_10 = _GEN_18; // @[package.scala:16:47] wire _r_c_cat_T_57; // @[package.scala:16:47] assign _r_c_cat_T_57 = _GEN_18; // @[package.scala:16:47] wire _r_c_cat_T_80; // @[package.scala:16:47] assign _r_c_cat_T_80 = _GEN_18; // @[package.scala:16:47] wire _state_r_c_cat_T_57; // @[package.scala:16:47] assign _state_r_c_cat_T_57 = _GEN_18; // @[package.scala:16:47] wire _state_r_c_cat_T_80; // @[package.scala:16:47] assign _state_r_c_cat_T_80 = _GEN_18; // @[package.scala:16:47] wire _state_T_44; // @[package.scala:16:47] assign _state_T_44 = _GEN_18; // @[package.scala:16:47] wire _GEN_19 = io_req_uop_mem_cmd_0 == 5'hB; // @[package.scala:16:47] wire _r2_c_cat_T_8; // @[package.scala:16:47] assign _r2_c_cat_T_8 = _GEN_19; // @[package.scala:16:47] wire _r2_c_cat_T_31; // @[package.scala:16:47] assign _r2_c_cat_T_31 = _GEN_19; // @[package.scala:16:47] wire _needs_second_acq_T_8; // @[package.scala:16:47] assign _needs_second_acq_T_8 = _GEN_19; // @[package.scala:16:47] wire _dirties_cat_T_8; // @[package.scala:16:47] assign _dirties_cat_T_8 = _GEN_19; // @[package.scala:16:47] wire _dirties_cat_T_31; // @[package.scala:16:47] assign _dirties_cat_T_31 = _GEN_19; // @[package.scala:16:47] wire _state_r_c_cat_T_8; // @[package.scala:16:47] assign _state_r_c_cat_T_8 = _GEN_19; // @[package.scala:16:47] wire _state_r_c_cat_T_31; // @[package.scala:16:47] assign _state_r_c_cat_T_31 = _GEN_19; // @[package.scala:16:47] wire _state_T_11; // @[package.scala:16:47] assign _state_T_11 = _GEN_19; // @[package.scala:16:47] wire _r_c_cat_T_58; // @[package.scala:16:47] assign _r_c_cat_T_58 = _GEN_19; // @[package.scala:16:47] wire _r_c_cat_T_81; // @[package.scala:16:47] assign _r_c_cat_T_81 = _GEN_19; // @[package.scala:16:47] wire _state_r_c_cat_T_58; // @[package.scala:16:47] assign _state_r_c_cat_T_58 = _GEN_19; // @[package.scala:16:47] wire _state_r_c_cat_T_81; // @[package.scala:16:47] assign _state_r_c_cat_T_81 = _GEN_19; // @[package.scala:16:47] wire _state_T_45; // @[package.scala:16:47] assign _state_T_45 = _GEN_19; // @[package.scala:16:47] wire _r2_c_cat_T_9 = _r2_c_cat_T_5 \| _r2_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_10 = _r2_c_cat_T_9 \| _r2_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_11 = _r2_c_cat_T_10 \| _r2_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _GEN_20 = io_req_uop_mem_cmd_0 == 5'h8; // @[package.scala:16:47] wire _r2_c_cat_T_12; // @[package.scala:16:47] assign _r2_c_cat_T_12 = _GEN_20; // @[package.scala:16:47] wire _r2_c_cat_T_35; // @[package.scala:16:47] assign _r2_c_cat_T_35 = _GEN_20; // @[package.scala:16:47] wire _needs_second_acq_T_12; // @[package.scala:16:47] assign _needs_second_acq_T_12 = _GEN_20; // @[package.scala:16:47] wire _dirties_cat_T_12; // @[package.scala:16:47] assign _dirties_cat_T_12 = _GEN_20; // @[package.scala:16:47] wire _dirties_cat_T_35; // @[package.scala:16:47] assign _dirties_cat_T_35 = _GEN_20; // @[package.scala:16:47] wire _state_r_c_cat_T_12; // @[package.scala:16:47] assign _state_r_c_cat_T_12 = _GEN_20; // @[package.scala:16:47] wire _state_r_c_cat_T_35; // @[package.scala:16:47] assign _state_r_c_cat_T_35 = _GEN_20; // @[package.scala:16:47] wire _state_T_15; // @[package.scala:16:47] assign _state_T_15 = _GEN_20; // @[package.scala:16:47] wire _r_c_cat_T_62; // @[package.scala:16:47] assign _r_c_cat_T_62 = _GEN_20; // @[package.scala:16:47] wire _r_c_cat_T_85; // @[package.scala:16:47] assign _r_c_cat_T_85 = _GEN_20; // @[package.scala:16:47] wire _state_r_c_cat_T_62; // @[package.scala:16:47] assign _state_r_c_cat_T_62 = _GEN_20; // @[package.scala:16:47] wire _state_r_c_cat_T_85; // @[package.scala:16:47] assign _state_r_c_cat_T_85 = _GEN_20; // @[package.scala:16:47] wire _state_T_49; // @[package.scala:16:47] assign _state_T_49 = _GEN_20; // @[package.scala:16:47] wire _GEN_21 = io_req_uop_mem_cmd_0 == 5'hC; // @[package.scala:16:47] wire _r2_c_cat_T_13; // @[package.scala:16:47] assign _r2_c_cat_T_13 = _GEN_21; // @[package.scala:16:47] wire _r2_c_cat_T_36; // @[package.scala:16:47] assign _r2_c_cat_T_36 = _GEN_21; // @[package.scala:16:47] wire _needs_second_acq_T_13; // @[package.scala:16:47] assign _needs_second_acq_T_13 = _GEN_21; // @[package.scala:16:47] wire _dirties_cat_T_13; // @[package.scala:16:47] assign _dirties_cat_T_13 = _GEN_21; // @[package.scala:16:47] wire _dirties_cat_T_36; // @[package.scala:16:47] assign _dirties_cat_T_36 = _GEN_21; // @[package.scala:16:47] wire _state_r_c_cat_T_13; // @[package.scala:16:47] assign _state_r_c_cat_T_13 = _GEN_21; // @[package.scala:16:47] wire _state_r_c_cat_T_36; // @[package.scala:16:47] assign _state_r_c_cat_T_36 = _GEN_21; // @[package.scala:16:47] wire _state_T_16; // @[package.scala:16:47] assign _state_T_16 = _GEN_21; // @[package.scala:16:47] wire _r_c_cat_T_63; // @[package.scala:16:47] assign _r_c_cat_T_63 = _GEN_21; // @[package.scala:16:47] wire _r_c_cat_T_86; // @[package.scala:16:47] assign _r_c_cat_T_86 = _GEN_21; // @[package.scala:16:47] wire _state_r_c_cat_T_63; // @[package.scala:16:47] assign _state_r_c_cat_T_63 = _GEN_21; // @[package.scala:16:47] wire _state_r_c_cat_T_86; // @[package.scala:16:47] assign _state_r_c_cat_T_86 = _GEN_21; // @[package.scala:16:47] wire _state_T_50; // @[package.scala:16:47] assign _state_T_50 = _GEN_21; // @[package.scala:16:47] wire _GEN_22 = io_req_uop_mem_cmd_0 == 5'hD; // @[package.scala:16:47] wire _r2_c_cat_T_14; // @[package.scala:16:47] assign _r2_c_cat_T_14 = _GEN_22; // @[package.scala:16:47] wire _r2_c_cat_T_37; // @[package.scala:16:47] assign _r2_c_cat_T_37 = _GEN_22; // @[package.scala:16:47] wire _needs_second_acq_T_14; // @[package.scala:16:47] assign _needs_second_acq_T_14 = _GEN_22; // @[package.scala:16:47] wire _dirties_cat_T_14; // @[package.scala:16:47] assign _dirties_cat_T_14 = _GEN_22; // @[package.scala:16:47] wire _dirties_cat_T_37; // @[package.scala:16:47] assign _dirties_cat_T_37 = _GEN_22; // @[package.scala:16:47] wire _state_r_c_cat_T_14; // @[package.scala:16:47] assign _state_r_c_cat_T_14 = _GEN_22; // @[package.scala:16:47] wire _state_r_c_cat_T_37; // @[package.scala:16:47] assign _state_r_c_cat_T_37 = _GEN_22; // @[package.scala:16:47] wire _state_T_17; // @[package.scala:16:47] assign _state_T_17 = _GEN_22; // @[package.scala:16:47] wire _r_c_cat_T_64; // @[package.scala:16:47] assign _r_c_cat_T_64 = _GEN_22; // @[package.scala:16:47] wire _r_c_cat_T_87; // @[package.scala:16:47] assign _r_c_cat_T_87 = _GEN_22; // @[package.scala:16:47] wire _state_r_c_cat_T_64; // @[package.scala:16:47] assign _state_r_c_cat_T_64 = _GEN_22; // @[package.scala:16:47] wire _state_r_c_cat_T_87; // @[package.scala:16:47] assign _state_r_c_cat_T_87 = _GEN_22; // @[package.scala:16:47] wire _state_T_51; // @[package.scala:16:47] assign _state_T_51 = _GEN_22; // @[package.scala:16:47] wire _GEN_23 = io_req_uop_mem_cmd_0 == 5'hE; // @[package.scala:16:47] wire _r2_c_cat_T_15; // @[package.scala:16:47] assign _r2_c_cat_T_15 = _GEN_23; // @[package.scala:16:47] wire _r2_c_cat_T_38; // @[package.scala:16:47] assign _r2_c_cat_T_38 = _GEN_23; // @[package.scala:16:47] wire _needs_second_acq_T_15; // @[package.scala:16:47] assign _needs_second_acq_T_15 = _GEN_23; // @[package.scala:16:47] wire _dirties_cat_T_15; // @[package.scala:16:47] assign _dirties_cat_T_15 = _GEN_23; // @[package.scala:16:47] wire _dirties_cat_T_38; // @[package.scala:16:47] assign _dirties_cat_T_38 = _GEN_23; // @[package.scala:16:47] wire _state_r_c_cat_T_15; // @[package.scala:16:47] assign _state_r_c_cat_T_15 = _GEN_23; // @[package.scala:16:47] wire _state_r_c_cat_T_38; // @[package.scala:16:47] assign _state_r_c_cat_T_38 = _GEN_23; // @[package.scala:16:47] wire _state_T_18; // @[package.scala:16:47] assign _state_T_18 = _GEN_23; // @[package.scala:16:47] wire _r_c_cat_T_65; // @[package.scala:16:47] assign _r_c_cat_T_65 = _GEN_23; // @[package.scala:16:47] wire _r_c_cat_T_88; // @[package.scala:16:47] assign _r_c_cat_T_88 = _GEN_23; // @[package.scala:16:47] wire _state_r_c_cat_T_65; // @[package.scala:16:47] assign _state_r_c_cat_T_65 = _GEN_23; // @[package.scala:16:47] wire _state_r_c_cat_T_88; // @[package.scala:16:47] assign _state_r_c_cat_T_88 = _GEN_23; // @[package.scala:16:47] wire _state_T_52; // @[package.scala:16:47] assign _state_T_52 = _GEN_23; // @[package.scala:16:47] wire _GEN_24 = io_req_uop_mem_cmd_0 == 5'hF; // @[package.scala:16:47] wire _r2_c_cat_T_16; // @[package.scala:16:47] assign _r2_c_cat_T_16 = _GEN_24; // @[package.scala:16:47] wire _r2_c_cat_T_39; // @[package.scala:16:47] assign _r2_c_cat_T_39 = _GEN_24; // @[package.scala:16:47] wire _needs_second_acq_T_16; // @[package.scala:16:47] assign _needs_second_acq_T_16 = _GEN_24; // @[package.scala:16:47] wire _dirties_cat_T_16; // @[package.scala:16:47] assign _dirties_cat_T_16 = _GEN_24; // @[package.scala:16:47] wire _dirties_cat_T_39; // @[package.scala:16:47] assign _dirties_cat_T_39 = _GEN_24; // @[package.scala:16:47] wire _state_r_c_cat_T_16; // @[package.scala:16:47] assign _state_r_c_cat_T_16 = _GEN_24; // @[package.scala:16:47] wire _state_r_c_cat_T_39; // @[package.scala:16:47] assign _state_r_c_cat_T_39 = _GEN_24; // @[package.scala:16:47] wire _state_T_19; // @[package.scala:16:47] assign _state_T_19 = _GEN_24; // @[package.scala:16:47] wire _r_c_cat_T_66; // @[package.scala:16:47] assign _r_c_cat_T_66 = _GEN_24; // @[package.scala:16:47] wire _r_c_cat_T_89; // @[package.scala:16:47] assign _r_c_cat_T_89 = _GEN_24; // @[package.scala:16:47] wire _state_r_c_cat_T_66; // @[package.scala:16:47] assign _state_r_c_cat_T_66 = _GEN_24; // @[package.scala:16:47] wire _state_r_c_cat_T_89; // @[package.scala:16:47] assign _state_r_c_cat_T_89 = _GEN_24; // @[package.scala:16:47] wire _state_T_53; // @[package.scala:16:47] assign _state_T_53 = _GEN_24; // @[package.scala:16:47] wire _r2_c_cat_T_17 = _r2_c_cat_T_12 \| _r2_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_18 = _r2_c_cat_T_17 \| _r2_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_19 = _r2_c_cat_T_18 \| _r2_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_20 = _r2_c_cat_T_19 \| _r2_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_21 = _r2_c_cat_T_11 \| _r2_c_cat_T_20; // @[package.scala:81:59] wire _r2_c_cat_T_22 = _r2_c_cat_T_4 \| _r2_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _r2_c_cat_T_25 = _r2_c_cat_T_23 \| _r2_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _r2_c_cat_T_27 = _r2_c_cat_T_25 \| _r2_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _r2_c_cat_T_32 = _r2_c_cat_T_28 \| _r2_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_33 = _r2_c_cat_T_32 \| _r2_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_34 = _r2_c_cat_T_33 \| _r2_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_40 = _r2_c_cat_T_35 \| _r2_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_41 = _r2_c_cat_T_40 \| _r2_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_42 = _r2_c_cat_T_41 \| _r2_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_43 = _r2_c_cat_T_42 \| _r2_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_44 = _r2_c_cat_T_34 \| _r2_c_cat_T_43; // @[package.scala:81:59] wire _r2_c_cat_T_45 = _r2_c_cat_T_27 \| _r2_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _GEN_25 = io_req_uop_mem_cmd_0 == 5'h3; // @[Consts.scala:91:54] wire _r2_c_cat_T_46; // @[Consts.scala:91:54] assign _r2_c_cat_T_46 = _GEN_25; // @[Consts.scala:91:54] wire _needs_second_acq_T_23; // @[Consts.scala:91:54] assign _needs_second_acq_T_23 = _GEN_25; // @[Consts.scala:91:54] wire _dirties_cat_T_46; // @[Consts.scala:91:54] assign _dirties_cat_T_46 = _GEN_25; // @[Consts.scala:91:54] wire _rpq_io_enq_valid_T_4; // @[Consts.scala:88:52] assign _rpq_io_enq_valid_T_4 = _GEN_25; // @[Consts.scala:88:52, :91:54] wire _state_r_c_cat_T_46; // @[Consts.scala:91:54] assign _state_r_c_cat_T_46 = _GEN_25; // @[Consts.scala:91:54] wire _r_c_cat_T_96; // @[Consts.scala:91:54] assign _r_c_cat_T_96 = _GEN_25; // @[Consts.scala:91:54] wire _state_r_c_cat_T_96; // @[Consts.scala:91:54] assign _state_r_c_cat_T_96 = _GEN_25; // @[Consts.scala:91:54] wire _r2_c_cat_T_47 = _r2_c_cat_T_45 \| _r2_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _GEN_26 = io_req_uop_mem_cmd_0 == 5'h6; // @[Consts.scala:91:71] wire _r2_c_cat_T_48; // @[Consts.scala:91:71] assign _r2_c_cat_T_48 = _GEN_26; // @[Consts.scala:91:71] wire _needs_second_acq_T_25; // @[Consts.scala:91:71] assign _needs_second_acq_T_25 = _GEN_26; // @[Consts.scala:91:71] wire _dirties_cat_T_48; // @[Consts.scala:91:71] assign _dirties_cat_T_48 = _GEN_26; // @[Consts.scala:91:71] wire _state_r_c_cat_T_48; // @[Consts.scala:91:71] assign _state_r_c_cat_T_48 = _GEN_26; // @[Consts.scala:91:71] wire _r_c_cat_T_98; // @[Consts.scala:91:71] assign _r_c_cat_T_98 = _GEN_26; // @[Consts.scala:91:71] wire _state_r_c_cat_T_98; // @[Consts.scala:91:71] assign _state_r_c_cat_T_98 = _GEN_26; // @[Consts.scala:91:71] wire _r2_c_cat_T_49 = _r2_c_cat_T_47 \| _r2_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] r2_c = {_r2_c_cat_T_22, _r2_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _r2_T = {r2_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19] wire _r2_T_25 = _r2_T == 4'hC; // @[Misc.scala:49:20] wire [1:0] _r2_T_27 = {1'h0, _r2_T_25}; // @[Misc.scala:35:36, :49:20] wire _r2_T_28 = _r2_T == 4'hD; // @[Misc.scala:49:20] wire [1:0] _r2_T_30 = _r2_T_28 ? 2'h2 : _r2_T_27; // @[Misc.scala:35:36, :49:20] wire _r2_T_31 = _r2_T == 4'h4; // @[Misc.scala:49:20] wire [1:0] _r2_T_33 = _r2_T_31 ? 2'h1 : _r2_T_30; // @[Misc.scala:35:36, :49:20] wire _r2_T_34 = _r2_T == 4'h5; // @[Misc.scala:49:20] wire [1:0] _r2_T_36 = _r2_T_34 ? 2'h2 : _r2_T_33; // @[Misc.scala:35:36, :49:20] wire _r2_T_37 = _r2_T == 4'h0; // @[Misc.scala:49:20] wire [1:0] _r2_T_39 = _r2_T_37 ? 2'h0 : _r2_T_36; // @[Misc.scala:35:36, :49:20] wire _r2_T_40 = _r2_T == 4'hE; // @[Misc.scala:49:20] wire _r2_T_41 = _r2_T_40; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_42 = _r2_T_40 ? 2'h3 : _r2_T_39; // @[Misc.scala:35:36, :49:20] wire _r2_T_43 = &_r2_T; // @[Misc.scala:49:20] wire _r2_T_44 = _r2_T_43 \| _r2_T_41; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_45 = _r2_T_43 ? 2'h3 : _r2_T_42; // @[Misc.scala:35:36, :49:20] wire _r2_T_46 = _r2_T == 4'h6; // @[Misc.scala:49:20] wire _r2_T_47 = _r2_T_46 \| _r2_T_44; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_48 = _r2_T_46 ? 2'h2 : _r2_T_45; // @[Misc.scala:35:36, :49:20] wire _r2_T_49 = _r2_T == 4'h7; // @[Misc.scala:49:20] wire _r2_T_50 = _r2_T_49 \| _r2_T_47; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_51 = _r2_T_49 ? 2'h3 : _r2_T_48; // @[Misc.scala:35:36, :49:20] wire _r2_T_52 = _r2_T == 4'h1; // @[Misc.scala:49:20] wire _r2_T_53 = _r2_T_52 \| _r2_T_50; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_54 = _r2_T_52 ? 2'h1 : _r2_T_51; // @[Misc.scala:35:36, :49:20] wire _r2_T_55 = _r2_T == 4'h2; // @[Misc.scala:49:20] wire _r2_T_56 = _r2_T_55 \| _r2_T_53; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_57 = _r2_T_55 ? 2'h2 : _r2_T_54; // @[Misc.scala:35:36, :49:20] wire _r2_T_58 = _r2_T == 4'h3; // @[Misc.scala:49:20] wire r2_1 = _r2_T_58 \| _r2_T_56; // @[Misc.scala:35:9, :49:20] wire [1:0] r2_2 = _r2_T_58 ? 2'h3 : _r2_T_57; // @[Misc.scala:35:36, :49:20] wire _needs_second_acq_T_2 = _needs_second_acq_T \| _needs_second_acq_T_1; // @[Consts.scala:90:{32,42,49}] wire _needs_second_acq_T_4 = _needs_second_acq_T_2 \| _needs_second_acq_T_3; // @[Consts.scala:90:{42,59,66}] wire _needs_second_acq_T_9 = _needs_second_acq_T_5 \| _needs_second_acq_T_6; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_10 = _needs_second_acq_T_9 \| _needs_second_acq_T_7; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_11 = _needs_second_acq_T_10 \| _needs_second_acq_T_8; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_17 = _needs_second_acq_T_12 \| _needs_second_acq_T_13; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_18 = _needs_second_acq_T_17 \| _needs_second_acq_T_14; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_19 = _needs_second_acq_T_18 \| _needs_second_acq_T_15; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_20 = _needs_second_acq_T_19 \| _needs_second_acq_T_16; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_21 = _needs_second_acq_T_11 \| _needs_second_acq_T_20; // @[package.scala:81:59] wire _needs_second_acq_T_22 = _needs_second_acq_T_4 \| _needs_second_acq_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _needs_second_acq_T_24 = _needs_second_acq_T_22 \| _needs_second_acq_T_23; // @[Consts.scala:90:76, :91:{47,54}] wire _needs_second_acq_T_26 = _needs_second_acq_T_24 \| _needs_second_acq_T_25; // @[Consts.scala:91:{47,64,71}] wire _needs_second_acq_T_29 = _needs_second_acq_T_27 \| _needs_second_acq_T_28; // @[Consts.scala:90:{32,42,49}] wire _needs_second_acq_T_31 = _needs_second_acq_T_29 \| _needs_second_acq_T_30; // @[Consts.scala:90:{42,59,66}] wire _needs_second_acq_T_36 = _needs_second_acq_T_32 \| _needs_second_acq_T_33; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_37 = _needs_second_acq_T_36 \| _needs_second_acq_T_34; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_38 = _needs_second_acq_T_37 \| _needs_second_acq_T_35; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_44 = _needs_second_acq_T_39 \| _needs_second_acq_T_40; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_45 = _needs_second_acq_T_44 \| _needs_second_acq_T_41; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_46 = _needs_second_acq_T_45 \| _needs_second_acq_T_42; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_47 = _needs_second_acq_T_46 \| _needs_second_acq_T_43; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_48 = _needs_second_acq_T_38 \| _needs_second_acq_T_47; // @[package.scala:81:59] wire _needs_second_acq_T_49 = _needs_second_acq_T_31 \| _needs_second_acq_T_48; // @[Consts.scala:87:44, :90:{59,76}] wire _needs_second_acq_T_51 = _needs_second_acq_T_49 \| _needs_second_acq_T_50; // @[Consts.scala:90:76, :91:{47,54}] wire _needs_second_acq_T_53 = _needs_second_acq_T_51 \| _needs_second_acq_T_52; // @[Consts.scala:91:{47,64,71}] wire _needs_second_acq_T_54 = ~_needs_second_acq_T_53; // @[Metadata.scala:104:57] wire cmd_requires_second_acquire = _needs_second_acq_T_26 & _needs_second_acq_T_54; // @[Metadata.scala:104:{54,57}] wire is_hit_again = r1_1 & r2_1; // @[Misc.scala:35:9] wire _dirties_cat_T_2 = _dirties_cat_T \| _dirties_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _dirties_cat_T_4 = _dirties_cat_T_2 \| _dirties_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _dirties_cat_T_9 = _dirties_cat_T_5 \| _dirties_cat_T_6; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_10 = _dirties_cat_T_9 \| _dirties_cat_T_7; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_11 = _dirties_cat_T_10 \| _dirties_cat_T_8; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_17 = _dirties_cat_T_12 \| _dirties_cat_T_13; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_18 = _dirties_cat_T_17 \| _dirties_cat_T_14; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_19 = _dirties_cat_T_18 \| _dirties_cat_T_15; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_20 = _dirties_cat_T_19 \| _dirties_cat_T_16; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_21 = _dirties_cat_T_11 \| _dirties_cat_T_20; // @[package.scala:81:59] wire _dirties_cat_T_22 = _dirties_cat_T_4 \| _dirties_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _dirties_cat_T_25 = _dirties_cat_T_23 \| _dirties_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _dirties_cat_T_27 = _dirties_cat_T_25 \| _dirties_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _dirties_cat_T_32 = _dirties_cat_T_28 \| _dirties_cat_T_29; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_33 = _dirties_cat_T_32 \| _dirties_cat_T_30; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_34 = _dirties_cat_T_33 \| _dirties_cat_T_31; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_40 = _dirties_cat_T_35 \| _dirties_cat_T_36; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_41 = _dirties_cat_T_40 \| _dirties_cat_T_37; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_42 = _dirties_cat_T_41 \| _dirties_cat_T_38; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_43 = _dirties_cat_T_42 \| _dirties_cat_T_39; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_44 = _dirties_cat_T_34 \| _dirties_cat_T_43; // @[package.scala:81:59] wire _dirties_cat_T_45 = _dirties_cat_T_27 \| _dirties_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _dirties_cat_T_47 = _dirties_cat_T_45 \| _dirties_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _dirties_cat_T_49 = _dirties_cat_T_47 \| _dirties_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] dirties_cat = {_dirties_cat_T_22, _dirties_cat_T_49}; // @[Metadata.scala:29:18] wire dirties = &dirties_cat; // @[Metadata.scala:29:18, :106:42] wire [1:0] biggest_grow_param = dirties ? r2_2 : r1_2; // @[Misc.scala:35:36] wire [1:0] dirtier_coh_state = biggest_grow_param; // @[Metadata.scala:107:33, :160:20] wire [4:0] dirtier_cmd = dirties ? io_req_uop_mem_cmd_0 : req_uop_mem_cmd; // @[Metadata.scala:106:42, :109:27] wire _T_16 = io_mem_grant_ready_0 & io_mem_grant_valid_0; // @[Decoupled.scala:51:35] wire [26:0] _r_beats1_decode_T = 27'hFFF << io_mem_grant_bits_size_0; // @[package.scala:243:71] wire [11:0] _r_beats1_decode_T_1 = _r_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _r_beats1_decode_T_2 = ~_r_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] r_beats1_decode = _r_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire r_beats1_opdata = io_mem_grant_bits_opcode_0[0]; // @[Edges.scala:106:36] wire opdata = io_mem_grant_bits_opcode_0[0]; // @[Edges.scala:106:36] wire grant_had_data_opdata = io_mem_grant_bits_opcode_0[0]; // @[Edges.scala:106:36] wire [8:0] r_beats1 = r_beats1_opdata ? r_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] r_counter; // @[Edges.scala:229:27] wire [9:0] _r_counter1_T = {1'h0, r_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] r_counter1 = _r_counter1_T[8:0]; // @[Edges.scala:230:28] wire r_1_1 = r_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _r_last_T = r_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _r_last_T_1 = r_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire r_2 = _r_last_T \| _r_last_T_1; // @[Edges.scala:232:{25,33,43}] wire refill_done = r_2 & _T_16; // @[Decoupled.scala:51:35] wire [8:0] _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] r_4 = r_beats1 & _r_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _r_counter_T = r_1_1 ? r_beats1 : r_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] refill_address_inc = {r_4, 3'h0}; // @[Edges.scala:234:25, :269:29] wire _sec_rdy_T = ~cmd_requires_second_acquire; // @[Metadata.scala:104:54] wire _sec_rdy_T_1 = ~io_req_is_probe_0; // @[mshrs.scala:36:7, :125:50] wire _sec_rdy_T_2 = _sec_rdy_T & _sec_rdy_T_1; // @[mshrs.scala:125:{18,47,50}] wire _sec_rdy_T_3 = ~(\|state); // @[package.scala:16:47] wire _sec_rdy_T_4 = state == 5'hD; // @[package.scala:16:47] wire _sec_rdy_T_5 = state == 5'hE; // @[package.scala:16:47] wire _sec_rdy_T_6 = state == 5'hF; // @[package.scala:16:47] wire _sec_rdy_T_7 = _sec_rdy_T_3 \| _sec_rdy_T_4; // @[package.scala:16:47, :81:59] wire _sec_rdy_T_8 = _sec_rdy_T_7 \| _sec_rdy_T_5; // @[package.scala:16:47, :81:59] wire _sec_rdy_T_9 = _sec_rdy_T_8 \| _sec_rdy_T_6; // @[package.scala:16:47, :81:59] wire _sec_rdy_T_10 = ~_sec_rdy_T_9; // @[package.scala:81:59] wire sec_rdy = _sec_rdy_T_2 & _sec_rdy_T_10; // @[mshrs.scala:125:{47,67}, :126:18] wire _rpq_io_enq_valid_T = io_req_pri_val_0 & io_req_pri_rdy_0; // @[mshrs.scala:36:7, :133:40] wire _rpq_io_enq_valid_T_1 = io_req_sec_val_0 & io_req_sec_rdy_0; // @[mshrs.scala:36:7, :133:78] wire _rpq_io_enq_valid_T_2 = _rpq_io_enq_valid_T \| _rpq_io_enq_valid_T_1; // @[mshrs.scala:133:{40,59,78}] wire _rpq_io_enq_valid_T_3 = io_req_uop_mem_cmd_0 == 5'h2; // @[Consts.scala:88:35] wire _rpq_io_enq_valid_T_5 = _rpq_io_enq_valid_T_3 \| _rpq_io_enq_valid_T_4; // @[Consts.scala:88:{35,45,52}] wire _rpq_io_enq_valid_T_6 = ~_rpq_io_enq_valid_T_5; // @[Consts.scala:88:45] wire _rpq_io_enq_valid_T_7 = _rpq_io_enq_valid_T_2 & _rpq_io_enq_valid_T_6; // @[mshrs.scala:133:{59,98,101}] reg grantack_valid; // @[mshrs.scala:138:21] reg [2:0] grantack_bits_sink; // @[mshrs.scala:138:21] assign io_mem_finish_bits_sink_0 = grantack_bits_sink; // @[mshrs.scala:36:7, :138:21] reg [2:0] refill_ctr; // @[mshrs.scala:139:24] reg commit_line; // @[mshrs.scala:140:24] reg grant_had_data; // @[mshrs.scala:141:27] reg finish_to_prefetch; // @[mshrs.scala:142:31] reg [1:0] meta_hazard; // @[mshrs.scala:145:28] wire [2:0] _meta_hazard_T = {1'h0, meta_hazard} + 3'h1; // @[mshrs.scala:145:28, :146:59] wire [1:0] _meta_hazard_T_1 = _meta_hazard_T[1:0]; // @[mshrs.scala:146:59] wire _io_probe_rdy_T = meta_hazard == 2'h0; // @[mshrs.scala:145:28, :148:34] wire _io_probe_rdy_T_1 = ~(\|state); // @[package.scala:16:47] wire _io_probe_rdy_T_2 = state == 5'h1; // @[package.scala:16:47] wire _io_probe_rdy_T_3 = state == 5'h2; // @[package.scala:16:47] wire _io_probe_rdy_T_4 = state == 5'h3; // @[package.scala:16:47] wire _io_probe_rdy_T_5 = _io_probe_rdy_T_1 \| _io_probe_rdy_T_2; // @[package.scala:16:47, :81:59] wire _io_probe_rdy_T_6 = _io_probe_rdy_T_5 \| _io_probe_rdy_T_3; // @[package.scala:16:47, :81:59] wire _io_probe_rdy_T_7 = _io_probe_rdy_T_6 \| _io_probe_rdy_T_4; // @[package.scala:16:47, :81:59] wire _io_probe_rdy_T_8 = state == 5'h4; // @[mshrs.scala:107:22, :148:129] wire _io_probe_rdy_T_9 = _io_probe_rdy_T_8 & grantack_valid; // @[mshrs.scala:138:21, :148:{129,145}] wire _io_probe_rdy_T_10 = _io_probe_rdy_T_7 \| _io_probe_rdy_T_9; // @[package.scala:81:59] assign _io_probe_rdy_T_11 = _io_probe_rdy_T & _io_probe_rdy_T_10; // @[mshrs.scala:148:{34,42,119}] assign io_probe_rdy_0 = _io_probe_rdy_T_11; // @[mshrs.scala:36:7, :148:42] assign _io_idx_valid_T = \|state; // @[package.scala:16:47] assign io_idx_valid_0 = _io_idx_valid_T; // @[mshrs.scala:36:7, :149:25] assign _io_tag_valid_T = \|state; // @[package.scala:16:47] assign io_tag_valid_0 = _io_tag_valid_T; // @[mshrs.scala:36:7, :150:25] wire _io_way_valid_T = ~(\|state); // @[package.scala:16:47] wire _io_way_valid_T_1 = state == 5'h11; // @[package.scala:16:47] wire _io_way_valid_T_2 = _io_way_valid_T \| _io_way_valid_T_1; // @[package.scala:16:47, :81:59] assign _io_way_valid_T_3 = ~_io_way_valid_T_2; // @[package.scala:81:59] assign io_way_valid_0 = _io_way_valid_T_3; // @[mshrs.scala:36:7, :151:19] assign io_meta_write_bits_tag_0 = req_tag[21:0]; // @[mshrs.scala:36:7, :111:26, :159:31] assign io_meta_write_bits_data_tag_0 = req_tag[21:0]; // @[mshrs.scala:36:7, :111:26, :159:31] assign io_meta_read_bits_tag_0 = req_tag[21:0]; // @[mshrs.scala:36:7, :111:26, :159:31] assign _io_req_sec_rdy_T = sec_rdy & _rpq_io_enq_ready; // @[mshrs.scala:125:67, :128:19, :163:37] assign io_req_sec_rdy_0 = _io_req_sec_rdy_T; // @[mshrs.scala:36:7, :163:37] wire [27:0] _GEN_27 = {req_tag, req_idx}; // @[mshrs.scala:110:25, :111:26, :168:26] wire [27:0] _io_mem_acquire_bits_T; // @[mshrs.scala:168:26] assign _io_mem_acquire_bits_T = _GEN_27; // @[mshrs.scala:168:26] wire [27:0] rp_addr_hi; // @[mshrs.scala:271:22] assign rp_addr_hi = _GEN_27; // @[mshrs.scala:168:26, :271:22] wire [27:0] hi; // @[mshrs.scala:276:10] assign hi = _GEN_27; // @[mshrs.scala:168:26, :276:10] wire [27:0] io_replay_bits_addr_hi; // @[mshrs.scala:341:31] assign io_replay_bits_addr_hi = _GEN_27; // @[mshrs.scala:168:26, :341:31] wire [33:0] _io_mem_acquire_bits_T_1 = {_io_mem_acquire_bits_T, 6'h0}; // @[mshrs.scala:168:{26,45}] wire [33:0] _io_mem_acquire_bits_legal_T_1 = _io_mem_acquire_bits_T_1; // @[Parameters.scala:137:31] wire [34:0] _io_mem_acquire_bits_legal_T_2 = {1'h0, _io_mem_acquire_bits_legal_T_1}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_mem_acquire_bits_legal_T_3 = _io_mem_acquire_bits_legal_T_2 & 35'h80000000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_mem_acquire_bits_legal_T_4 = _io_mem_acquire_bits_legal_T_3; // @[Parameters.scala:137:46] wire _io_mem_acquire_bits_legal_T_5 = _io_mem_acquire_bits_legal_T_4 == 35'h0; // @[Parameters.scala:137:{46,59}] assign io_mem_acquire_bits_a_address = _io_mem_acquire_bits_T_1[31:0]; // @[Edges.scala:346:17] wire [33:0] _io_mem_acquire_bits_legal_T_9 = {_io_mem_acquire_bits_T_1[33:32], io_mem_acquire_bits_a_address ^ 32'h80000000}; // @[Edges.scala:346:17] wire [34:0] _io_mem_acquire_bits_legal_T_10 = {1'h0, _io_mem_acquire_bits_legal_T_9}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_mem_acquire_bits_legal_T_11 = _io_mem_acquire_bits_legal_T_10 & 35'h80000000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_mem_acquire_bits_legal_T_12 = _io_mem_acquire_bits_legal_T_11; // @[Parameters.scala:137:46] wire _io_mem_acquire_bits_legal_T_13 = _io_mem_acquire_bits_legal_T_12 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _io_mem_acquire_bits_legal_T_14 = _io_mem_acquire_bits_legal_T_13; // @[Parameters.scala:684:54] wire io_mem_acquire_bits_legal = _io_mem_acquire_bits_legal_T_14; // @[Parameters.scala:684:54, :686:26] assign io_mem_acquire_bits_param_0 = io_mem_acquire_bits_a_param; // @[Edges.scala:346:17] assign io_mem_acquire_bits_address_0 = io_mem_acquire_bits_a_address; // @[Edges.scala:346:17] assign io_mem_acquire_bits_a_param = {1'h0, grow_param}; // @[Misc.scala:35:36] wire io_mem_acquire_bits_a_mask_sub_sub_bit = _io_mem_acquire_bits_T_1[2]; // @[Misc.scala:210:26] wire io_mem_acquire_bits_a_mask_sub_sub_1_2 = io_mem_acquire_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire io_mem_acquire_bits_a_mask_sub_sub_nbit = ~io_mem_acquire_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire io_mem_acquire_bits_a_mask_sub_sub_0_2 = io_mem_acquire_bits_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_sub_sub_acc_T = io_mem_acquire_bits_a_mask_sub_sub_0_2; // @[Misc.scala:214:27, :215:38] wire _io_mem_acquire_bits_a_mask_sub_sub_acc_T_1 = io_mem_acquire_bits_a_mask_sub_sub_1_2; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_sub_bit = _io_mem_acquire_bits_T_1[1]; // @[Misc.scala:210:26] wire io_mem_acquire_bits_a_mask_sub_nbit = ~io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire io_mem_acquire_bits_a_mask_sub_0_2 = io_mem_acquire_bits_a_mask_sub_sub_0_2 & io_mem_acquire_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire io_mem_acquire_bits_a_mask_sub_1_2 = io_mem_acquire_bits_a_mask_sub_sub_0_2 & io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire io_mem_acquire_bits_a_mask_sub_2_2 = io_mem_acquire_bits_a_mask_sub_sub_1_2 & io_mem_acquire_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire io_mem_acquire_bits_a_mask_sub_3_2 = io_mem_acquire_bits_a_mask_sub_sub_1_2 & io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire io_mem_acquire_bits_a_mask_bit = _io_mem_acquire_bits_T_1[0]; // @[Misc.scala:210:26] wire io_mem_acquire_bits_a_mask_nbit = ~io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire io_mem_acquire_bits_a_mask_eq = io_mem_acquire_bits_a_mask_sub_0_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T = io_mem_acquire_bits_a_mask_eq; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_1 = io_mem_acquire_bits_a_mask_sub_0_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_1 = io_mem_acquire_bits_a_mask_eq_1; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_2 = io_mem_acquire_bits_a_mask_sub_1_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_2 = io_mem_acquire_bits_a_mask_eq_2; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_3 = io_mem_acquire_bits_a_mask_sub_1_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_3 = io_mem_acquire_bits_a_mask_eq_3; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_4 = io_mem_acquire_bits_a_mask_sub_2_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_4 = io_mem_acquire_bits_a_mask_eq_4; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_5 = io_mem_acquire_bits_a_mask_sub_2_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_5 = io_mem_acquire_bits_a_mask_eq_5; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_6 = io_mem_acquire_bits_a_mask_sub_3_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_6 = io_mem_acquire_bits_a_mask_eq_6; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_7 = io_mem_acquire_bits_a_mask_sub_3_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_7 = io_mem_acquire_bits_a_mask_eq_7; // @[Misc.scala:214:27, :215:38] wire [5:0] _io_refill_bits_addr_T = {refill_ctr, 3'h0}; // @[mshrs.scala:139:24, :172:57] wire [33:0] _io_refill_bits_addr_T_1 = {req_block_addr[33:6], req_block_addr[5:0] \| _io_refill_bits_addr_T}; // @[mshrs.scala:112:51, :172:{43,57}] assign io_refill_bits_addr_0 = _io_refill_bits_addr_T_1[9:0]; // @[mshrs.scala:36:7, :172:{25,43}] wire [8:0] _io_lb_write_bits_offset_T = refill_address_inc[11:3]; // @[Edges.scala:269:29] assign io_lb_write_bits_offset_0 = _io_lb_write_bits_offset_T[2:0]; // @[mshrs.scala:36:7, :197:{27,49}] wire [30:0] _io_lb_read_offset_T = _rpq_io_deq_bits_addr[33:3]; // @[mshrs.scala:128:19, :200:45] wire [30:0] _io_lb_read_offset_T_1 = _rpq_io_deq_bits_addr[33:3]; // @[mshrs.scala:128:19, :200:45, :282:47] wire [4:0] state_new_state; // @[mshrs.scala:210:29] wire _state_T_1 = ~_state_T; // @[mshrs.scala:213:11] wire _state_T_2 = ~_rpq_io_enq_ready; // @[mshrs.scala:128:19, :213:11] wire [3:0] _GEN_28 = {2'h2, io_req_old_meta_coh_state_0}; // @[Metadata.scala:120:19] wire [3:0] _state_req_needs_wb_r_T_6; // @[Metadata.scala:120:19] assign _state_req_needs_wb_r_T_6 = _GEN_28; // @[Metadata.scala:120:19] wire [3:0] _state_req_needs_wb_r_T_70; // @[Metadata.scala:120:19] assign _state_req_needs_wb_r_T_70 = _GEN_28; // @[Metadata.scala:120:19] wire _state_req_needs_wb_r_T_19 = _state_req_needs_wb_r_T_6 == 4'h8; // @[Misc.scala:56:20] wire [2:0] _state_req_needs_wb_r_T_21 = _state_req_needs_wb_r_T_19 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_23 = _state_req_needs_wb_r_T_6 == 4'h9; // @[Misc.scala:56:20] wire [2:0] _state_req_needs_wb_r_T_25 = _state_req_needs_wb_r_T_23 ? 3'h2 : _state_req_needs_wb_r_T_21; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_27 = _state_req_needs_wb_r_T_6 == 4'hA; // @[Misc.scala:56:20] wire [2:0] _state_req_needs_wb_r_T_29 = _state_req_needs_wb_r_T_27 ? 3'h1 : _state_req_needs_wb_r_T_25; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_31 = _state_req_needs_wb_r_T_6 == 4'hB; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_32 = _state_req_needs_wb_r_T_31; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_33 = _state_req_needs_wb_r_T_31 ? 3'h1 : _state_req_needs_wb_r_T_29; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_35 = _state_req_needs_wb_r_T_6 == 4'h4; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_36 = ~_state_req_needs_wb_r_T_35 & _state_req_needs_wb_r_T_32; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_37 = _state_req_needs_wb_r_T_35 ? 3'h5 : _state_req_needs_wb_r_T_33; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_39 = _state_req_needs_wb_r_T_6 == 4'h5; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_40 = ~_state_req_needs_wb_r_T_39 & _state_req_needs_wb_r_T_36; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_41 = _state_req_needs_wb_r_T_39 ? 3'h4 : _state_req_needs_wb_r_T_37; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_42 = {1'h0, _state_req_needs_wb_r_T_39}; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_43 = _state_req_needs_wb_r_T_6 == 4'h6; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_44 = ~_state_req_needs_wb_r_T_43 & _state_req_needs_wb_r_T_40; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_45 = _state_req_needs_wb_r_T_43 ? 3'h0 : _state_req_needs_wb_r_T_41; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_46 = _state_req_needs_wb_r_T_43 ? 2'h1 : _state_req_needs_wb_r_T_42; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_47 = _state_req_needs_wb_r_T_6 == 4'h7; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_48 = _state_req_needs_wb_r_T_47 \| _state_req_needs_wb_r_T_44; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_49 = _state_req_needs_wb_r_T_47 ? 3'h0 : _state_req_needs_wb_r_T_45; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_50 = _state_req_needs_wb_r_T_47 ? 2'h1 : _state_req_needs_wb_r_T_46; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_51 = _state_req_needs_wb_r_T_6 == 4'h0; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_52 = ~_state_req_needs_wb_r_T_51 & _state_req_needs_wb_r_T_48; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_53 = _state_req_needs_wb_r_T_51 ? 3'h5 : _state_req_needs_wb_r_T_49; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_54 = _state_req_needs_wb_r_T_51 ? 2'h0 : _state_req_needs_wb_r_T_50; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_55 = _state_req_needs_wb_r_T_6 == 4'h1; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_56 = ~_state_req_needs_wb_r_T_55 & _state_req_needs_wb_r_T_52; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_57 = _state_req_needs_wb_r_T_55 ? 3'h4 : _state_req_needs_wb_r_T_53; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_58 = _state_req_needs_wb_r_T_55 ? 2'h1 : _state_req_needs_wb_r_T_54; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_59 = _state_req_needs_wb_r_T_6 == 4'h2; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_60 = ~_state_req_needs_wb_r_T_59 & _state_req_needs_wb_r_T_56; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_61 = _state_req_needs_wb_r_T_59 ? 3'h3 : _state_req_needs_wb_r_T_57; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_62 = _state_req_needs_wb_r_T_59 ? 2'h2 : _state_req_needs_wb_r_T_58; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_63 = _state_req_needs_wb_r_T_6 == 4'h3; // @[Misc.scala:56:20] wire state_req_needs_wb_r_1 = _state_req_needs_wb_r_T_63 \| _state_req_needs_wb_r_T_60; // @[Misc.scala:38:9, :56:20] wire [2:0] state_req_needs_wb_r_2 = _state_req_needs_wb_r_T_63 ? 3'h3 : _state_req_needs_wb_r_T_61; // @[Misc.scala:38:36, :56:20] wire [1:0] state_req_needs_wb_r_3 = _state_req_needs_wb_r_T_63 ? 2'h2 : _state_req_needs_wb_r_T_62; // @[Misc.scala:38:63, :56:20] wire [1:0] state_req_needs_wb_meta_state = state_req_needs_wb_r_3; // @[Misc.scala:38:63] wire _state_r_c_cat_T_2 = _state_r_c_cat_T \| _state_r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _state_r_c_cat_T_4 = _state_r_c_cat_T_2 \| _state_r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _state_r_c_cat_T_9 = _state_r_c_cat_T_5 \| _state_r_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_10 = _state_r_c_cat_T_9 \| _state_r_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_11 = _state_r_c_cat_T_10 \| _state_r_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_17 = _state_r_c_cat_T_12 \| _state_r_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_18 = _state_r_c_cat_T_17 \| _state_r_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_19 = _state_r_c_cat_T_18 \| _state_r_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_20 = _state_r_c_cat_T_19 \| _state_r_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_21 = _state_r_c_cat_T_11 \| _state_r_c_cat_T_20; // @[package.scala:81:59] wire _state_r_c_cat_T_22 = _state_r_c_cat_T_4 \| _state_r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _state_r_c_cat_T_25 = _state_r_c_cat_T_23 \| _state_r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _state_r_c_cat_T_27 = _state_r_c_cat_T_25 \| _state_r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _state_r_c_cat_T_32 = _state_r_c_cat_T_28 \| _state_r_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_33 = _state_r_c_cat_T_32 \| _state_r_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_34 = _state_r_c_cat_T_33 \| _state_r_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_40 = _state_r_c_cat_T_35 \| _state_r_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_41 = _state_r_c_cat_T_40 \| _state_r_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_42 = _state_r_c_cat_T_41 \| _state_r_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_43 = _state_r_c_cat_T_42 \| _state_r_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_44 = _state_r_c_cat_T_34 \| _state_r_c_cat_T_43; // @[package.scala:81:59] wire _state_r_c_cat_T_45 = _state_r_c_cat_T_27 \| _state_r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _state_r_c_cat_T_47 = _state_r_c_cat_T_45 \| _state_r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _state_r_c_cat_T_49 = _state_r_c_cat_T_47 \| _state_r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] state_r_c = {_state_r_c_cat_T_22, _state_r_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _state_r_T = {state_r_c, io_req_old_meta_coh_state_0}; // @[Metadata.scala:29:18, :58:19] wire _state_r_T_25 = _state_r_T == 4'hC; // @[Misc.scala:49:20] wire [1:0] _state_r_T_27 = {1'h0, _state_r_T_25}; // @[Misc.scala:35:36, :49:20] wire _state_r_T_28 = _state_r_T == 4'hD; // @[Misc.scala:49:20] wire [1:0] _state_r_T_30 = _state_r_T_28 ? 2'h2 : _state_r_T_27; // @[Misc.scala:35:36, :49:20] wire _state_r_T_31 = _state_r_T == 4'h4; // @[Misc.scala:49:20] wire [1:0] _state_r_T_33 = _state_r_T_31 ? 2'h1 : _state_r_T_30; // @[Misc.scala:35:36, :49:20] wire _state_r_T_34 = _state_r_T == 4'h5; // @[Misc.scala:49:20] wire [1:0] _state_r_T_36 = _state_r_T_34 ? 2'h2 : _state_r_T_33; // @[Misc.scala:35:36, :49:20] wire _state_r_T_37 = _state_r_T == 4'h0; // @[Misc.scala:49:20] wire [1:0] _state_r_T_39 = _state_r_T_37 ? 2'h0 : _state_r_T_36; // @[Misc.scala:35:36, :49:20] wire _state_r_T_40 = _state_r_T == 4'hE; // @[Misc.scala:49:20] wire _state_r_T_41 = _state_r_T_40; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_42 = _state_r_T_40 ? 2'h3 : _state_r_T_39; // @[Misc.scala:35:36, :49:20] wire _state_r_T_43 = &_state_r_T; // @[Misc.scala:49:20] wire _state_r_T_44 = _state_r_T_43 \| _state_r_T_41; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_45 = _state_r_T_43 ? 2'h3 : _state_r_T_42; // @[Misc.scala:35:36, :49:20] wire _state_r_T_46 = _state_r_T == 4'h6; // @[Misc.scala:49:20] wire _state_r_T_47 = _state_r_T_46 \| _state_r_T_44; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_48 = _state_r_T_46 ? 2'h2 : _state_r_T_45; // @[Misc.scala:35:36, :49:20] wire _state_r_T_49 = _state_r_T == 4'h7; // @[Misc.scala:49:20] wire _state_r_T_50 = _state_r_T_49 \| _state_r_T_47; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_51 = _state_r_T_49 ? 2'h3 : _state_r_T_48; // @[Misc.scala:35:36, :49:20] wire _state_r_T_52 = _state_r_T == 4'h1; // @[Misc.scala:49:20] wire _state_r_T_53 = _state_r_T_52 \| _state_r_T_50; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_54 = _state_r_T_52 ? 2'h1 : _state_r_T_51; // @[Misc.scala:35:36, :49:20] wire _state_r_T_55 = _state_r_T == 4'h2; // @[Misc.scala:49:20] wire _state_r_T_56 = _state_r_T_55 \| _state_r_T_53; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_57 = _state_r_T_55 ? 2'h2 : _state_r_T_54; // @[Misc.scala:35:36, :49:20] wire _state_r_T_58 = _state_r_T == 4'h3; // @[Misc.scala:49:20] wire state_is_hit = _state_r_T_58 \| _state_r_T_56; // @[Misc.scala:35:9, :49:20] wire [1:0] state_r_2 = _state_r_T_58 ? 2'h3 : _state_r_T_57; // @[Misc.scala:35:36, :49:20] wire [1:0] state_coh_on_hit_state = state_r_2; // @[Misc.scala:35:36] wire _state_T_5 = _state_T_3 \| _state_T_4; // @[Consts.scala:90:{32,42,49}] wire _state_T_7 = _state_T_5 \| _state_T_6; // @[Consts.scala:90:{42,59,66}] wire _state_T_12 = _state_T_8 \| _state_T_9; // @[package.scala:16:47, :81:59] wire _state_T_13 = _state_T_12 \| _state_T_10; // @[package.scala:16:47, :81:59] wire _state_T_14 = _state_T_13 \| _state_T_11; // @[package.scala:16:47, :81:59] wire _state_T_20 = _state_T_15 \| _state_T_16; // @[package.scala:16:47, :81:59] wire _state_T_21 = _state_T_20 \| _state_T_17; // @[package.scala:16:47, :81:59] wire _state_T_22 = _state_T_21 \| _state_T_18; // @[package.scala:16:47, :81:59] wire _state_T_23 = _state_T_22 \| _state_T_19; // @[package.scala:16:47, :81:59] wire _state_T_24 = _state_T_14 \| _state_T_23; // @[package.scala:81:59] wire _state_T_25 = _state_T_7 \| _state_T_24; // @[Consts.scala:87:44, :90:{59,76}] wire _state_T_27 = ~_state_T_26; // @[mshrs.scala:220:15] wire _state_T_28 = ~_state_T_25; // @[Consts.scala:90:76] assign state_new_state = io_req_tag_match_0 & state_is_hit ? 5'hC : 5'h1; // @[Misc.scala:35:9] assign io_mem_acquire_valid_0 = (\|state) & _io_probe_rdy_T_2; // @[package.scala:16:47] wire _GEN_29 = ~(\|state) \| _io_probe_rdy_T_2; // @[package.scala:16:47] assign io_lb_write_valid_0 = ~_GEN_29 & _io_probe_rdy_T_3 & opdata & io_mem_grant_valid_0; // @[package.scala:16:47] assign io_mem_grant_ready_0 = ~_GEN_29 & _io_probe_rdy_T_3; // @[package.scala:16:47] wire _grantack_valid_T = io_mem_grant_bits_opcode_0[2]; // @[Edges.scala:71:36] wire _grantack_valid_T_1 = io_mem_grant_bits_opcode_0[1]; // @[Edges.scala:71:52] wire _grantack_valid_T_2 = ~_grantack_valid_T_1; // @[Edges.scala:71:{43,52}] wire _grantack_valid_T_3 = _grantack_valid_T & _grantack_valid_T_2; // @[Edges.scala:71:{36,40,43}] wire [4:0] _state_T_29 = grant_had_data ? 5'h3 : 5'hC; // @[mshrs.scala:141:27, :260:19] wire _drain_load_T = _rpq_io_deq_bits_uop_mem_cmd == 5'h0; // @[package.scala:16:47] wire _drain_load_T_1 = _rpq_io_deq_bits_uop_mem_cmd == 5'h10; // @[package.scala:16:47] wire _GEN_30 = _rpq_io_deq_bits_uop_mem_cmd == 5'h6; // @[package.scala:16:47] wire _drain_load_T_2; // @[package.scala:16:47] assign _drain_load_T_2 = _GEN_30; // @[package.scala:16:47] wire _r_c_cat_T_48; // @[Consts.scala:91:71] assign _r_c_cat_T_48 = _GEN_30; // @[package.scala:16:47] wire _GEN_31 = _rpq_io_deq_bits_uop_mem_cmd == 5'h7; // @[package.scala:16:47] wire _drain_load_T_3; // @[package.scala:16:47] assign _drain_load_T_3 = _GEN_31; // @[package.scala:16:47] wire _drain_load_T_28; // @[Consts.scala:90:66] assign _drain_load_T_28 = _GEN_31; // @[package.scala:16:47] wire _drain_load_T_4 = _drain_load_T \| _drain_load_T_1; // @[package.scala:16:47, :81:59] wire _drain_load_T_5 = _drain_load_T_4 \| _drain_load_T_2; // @[package.scala:16:47, :81:59] wire _drain_load_T_6 = _drain_load_T_5 \| _drain_load_T_3; // @[package.scala:16:47, :81:59] wire _GEN_32 = _rpq_io_deq_bits_uop_mem_cmd == 5'h4; // @[package.scala:16:47] wire _drain_load_T_7; // @[package.scala:16:47] assign _drain_load_T_7 = _GEN_32; // @[package.scala:16:47] wire _drain_load_T_30; // @[package.scala:16:47] assign _drain_load_T_30 = _GEN_32; // @[package.scala:16:47] wire _GEN_33 = _rpq_io_deq_bits_uop_mem_cmd == 5'h9; // @[package.scala:16:47] wire _drain_load_T_8; // @[package.scala:16:47] assign _drain_load_T_8 = _GEN_33; // @[package.scala:16:47] wire _drain_load_T_31; // @[package.scala:16:47] assign _drain_load_T_31 = _GEN_33; // @[package.scala:16:47] wire _GEN_34 = _rpq_io_deq_bits_uop_mem_cmd == 5'hA; // @[package.scala:16:47] wire _drain_load_T_9; // @[package.scala:16:47] assign _drain_load_T_9 = _GEN_34; // @[package.scala:16:47] wire _drain_load_T_32; // @[package.scala:16:47] assign _drain_load_T_32 = _GEN_34; // @[package.scala:16:47] wire _GEN_35 = _rpq_io_deq_bits_uop_mem_cmd == 5'hB; // @[package.scala:16:47] wire _drain_load_T_10; // @[package.scala:16:47] assign _drain_load_T_10 = _GEN_35; // @[package.scala:16:47] wire _drain_load_T_33; // @[package.scala:16:47] assign _drain_load_T_33 = _GEN_35; // @[package.scala:16:47] wire _drain_load_T_11 = _drain_load_T_7 \| _drain_load_T_8; // @[package.scala:16:47, :81:59] wire _drain_load_T_12 = _drain_load_T_11 \| _drain_load_T_9; // @[package.scala:16:47, :81:59] wire _drain_load_T_13 = _drain_load_T_12 \| _drain_load_T_10; // @[package.scala:16:47, :81:59] wire _GEN_36 = _rpq_io_deq_bits_uop_mem_cmd == 5'h8; // @[package.scala:16:47] wire _drain_load_T_14; // @[package.scala:16:47] assign _drain_load_T_14 = _GEN_36; // @[package.scala:16:47] wire _drain_load_T_37; // @[package.scala:16:47] assign _drain_load_T_37 = _GEN_36; // @[package.scala:16:47] wire _GEN_37 = _rpq_io_deq_bits_uop_mem_cmd == 5'hC; // @[package.scala:16:47] wire _drain_load_T_15; // @[package.scala:16:47] assign _drain_load_T_15 = _GEN_37; // @[package.scala:16:47] wire _drain_load_T_38; // @[package.scala:16:47] assign _drain_load_T_38 = _GEN_37; // @[package.scala:16:47] wire _GEN_38 = _rpq_io_deq_bits_uop_mem_cmd == 5'hD; // @[package.scala:16:47] wire _drain_load_T_16; // @[package.scala:16:47] assign _drain_load_T_16 = _GEN_38; // @[package.scala:16:47] wire _drain_load_T_39; // @[package.scala:16:47] assign _drain_load_T_39 = _GEN_38; // @[package.scala:16:47] wire _GEN_39 = _rpq_io_deq_bits_uop_mem_cmd == 5'hE; // @[package.scala:16:47] wire _drain_load_T_17; // @[package.scala:16:47] assign _drain_load_T_17 = _GEN_39; // @[package.scala:16:47] wire _drain_load_T_40; // @[package.scala:16:47] assign _drain_load_T_40 = _GEN_39; // @[package.scala:16:47] wire _GEN_40 = _rpq_io_deq_bits_uop_mem_cmd == 5'hF; // @[package.scala:16:47] wire _drain_load_T_18; // @[package.scala:16:47] assign _drain_load_T_18 = _GEN_40; // @[package.scala:16:47] wire _drain_load_T_41; // @[package.scala:16:47] assign _drain_load_T_41 = _GEN_40; // @[package.scala:16:47] wire _drain_load_T_19 = _drain_load_T_14 \| _drain_load_T_15; // @[package.scala:16:47, :81:59] wire _drain_load_T_20 = _drain_load_T_19 \| _drain_load_T_16; // @[package.scala:16:47, :81:59] wire _drain_load_T_21 = _drain_load_T_20 \| _drain_load_T_17; // @[package.scala:16:47, :81:59] wire _drain_load_T_22 = _drain_load_T_21 \| _drain_load_T_18; // @[package.scala:16:47, :81:59] wire _drain_load_T_23 = _drain_load_T_13 \| _drain_load_T_22; // @[package.scala:81:59] wire _drain_load_T_24 = _drain_load_T_6 \| _drain_load_T_23; // @[package.scala:81:59] wire _drain_load_T_25 = _rpq_io_deq_bits_uop_mem_cmd == 5'h1; // @[Consts.scala:90:32] wire _drain_load_T_26 = _rpq_io_deq_bits_uop_mem_cmd == 5'h11; // @[Consts.scala:90:49] wire _drain_load_T_27 = _drain_load_T_25 \| _drain_load_T_26; // @[Consts.scala:90:{32,42,49}] wire _drain_load_T_29 = _drain_load_T_27 \| _drain_load_T_28; // @[Consts.scala:90:{42,59,66}] wire _drain_load_T_34 = _drain_load_T_30 \| _drain_load_T_31; // @[package.scala:16:47, :81:59] wire _drain_load_T_35 = _drain_load_T_34 \| _drain_load_T_32; // @[package.scala:16:47, :81:59] wire _drain_load_T_36 = _drain_load_T_35 \| _drain_load_T_33; // @[package.scala:16:47, :81:59] wire _drain_load_T_42 = _drain_load_T_37 \| _drain_load_T_38; // @[package.scala:16:47, :81:59] wire _drain_load_T_43 = _drain_load_T_42 \| _drain_load_T_39; // @[package.scala:16:47, :81:59] wire _drain_load_T_44 = _drain_load_T_43 \| _drain_load_T_40; // @[package.scala:16:47, :81:59] wire _drain_load_T_45 = _drain_load_T_44 \| _drain_load_T_41; // @[package.scala:16:47, :81:59] wire _drain_load_T_46 = _drain_load_T_36 \| _drain_load_T_45; // @[package.scala:81:59] wire _drain_load_T_47 = _drain_load_T_29 \| _drain_load_T_46; // @[Consts.scala:87:44, :90:{59,76}] wire _drain_load_T_48 = ~_drain_load_T_47; // @[Consts.scala:90:76] wire _drain_load_T_49 = _drain_load_T_24 & _drain_load_T_48; // @[Consts.scala:89:68] wire _drain_load_T_50 = _rpq_io_deq_bits_uop_mem_cmd != 5'h6; // @[mshrs.scala:128:19, :269:51] wire drain_load = _drain_load_T_49 & _drain_load_T_50; // @[mshrs.scala:267:59, :268:60, :269:51] wire [5:0] _rp_addr_T = _rpq_io_deq_bits_addr[5:0]; // @[mshrs.scala:128:19, :271:61] wire [33:0] rp_addr = {rp_addr_hi, _rp_addr_T}; // @[mshrs.scala:271:{22,61}] wire [1:0] size; // @[AMOALU.scala:11:18] wire _rpq_io_deq_ready_T = io_resp_ready_0 & drain_load; // @[mshrs.scala:36:7, :268:60, :280:40] wire _io_resp_valid_T = _rpq_io_deq_valid & drain_load; // @[mshrs.scala:128:19, :268:60, :284:43] wire _GEN_41 = ~(\|state) \| _io_probe_rdy_T_2 \| _io_probe_rdy_T_3; // @[package.scala:16:47] assign io_resp_valid_0 = ~_GEN_41 & _io_probe_rdy_T_4 & _io_resp_valid_T; // @[package.scala:16:47] wire _io_resp_bits_data_shifted_T = _rpq_io_deq_bits_addr[2]; // @[AMOALU.scala:42:29] wire [31:0] _io_resp_bits_data_shifted_T_1 = data_word[63:32]; // @[AMOALU.scala:42:37] wire [31:0] _io_resp_bits_data_T_5 = data_word[63:32]; // @[AMOALU.scala:42:37, :45:94] wire [31:0] _io_resp_bits_data_shifted_T_2 = data_word[31:0]; // @[AMOALU.scala:42:55] wire [31:0] io_resp_bits_data_shifted = _io_resp_bits_data_shifted_T ? _io_resp_bits_data_shifted_T_1 : _io_resp_bits_data_shifted_T_2; // @[AMOALU.scala:42:{24,29,37,55}] wire [31:0] io_resp_bits_data_zeroed = io_resp_bits_data_shifted; // @[AMOALU.scala:42:24, :44:23] wire _io_resp_bits_data_T = size == 2'h2; // @[AMOALU.scala:11:18, :45:26] wire _io_resp_bits_data_T_1 = _io_resp_bits_data_T; // @[AMOALU.scala:45:{26,34}] wire _io_resp_bits_data_T_2 = io_resp_bits_data_zeroed[31]; // @[AMOALU.scala:44:23, :45:81] wire _io_resp_bits_data_T_3 = _rpq_io_deq_bits_uop_mem_signed & _io_resp_bits_data_T_2; // @[AMOALU.scala:45:{72,81}] wire [31:0] _io_resp_bits_data_T_4 = {32{_io_resp_bits_data_T_3}}; // @[AMOALU.scala:45:{49,72}] wire [31:0] _io_resp_bits_data_T_6 = _io_resp_bits_data_T_1 ? _io_resp_bits_data_T_4 : _io_resp_bits_data_T_5; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _io_resp_bits_data_T_7 = {_io_resp_bits_data_T_6, io_resp_bits_data_zeroed}; // @[AMOALU.scala:44:23, :45:{16,20}] wire _io_resp_bits_data_shifted_T_3 = _rpq_io_deq_bits_addr[1]; // @[AMOALU.scala:42:29] wire [15:0] _io_resp_bits_data_shifted_T_4 = _io_resp_bits_data_T_7[31:16]; // @[AMOALU.scala:42:37, :45:16] wire [15:0] _io_resp_bits_data_shifted_T_5 = _io_resp_bits_data_T_7[15:0]; // @[AMOALU.scala:42:55, :45:16] wire [15:0] io_resp_bits_data_shifted_1 = _io_resp_bits_data_shifted_T_3 ? _io_resp_bits_data_shifted_T_4 : _io_resp_bits_data_shifted_T_5; // @[AMOALU.scala:42:{24,29,37,55}] wire [15:0] io_resp_bits_data_zeroed_1 = io_resp_bits_data_shifted_1; // @[AMOALU.scala:42:24, :44:23] wire _io_resp_bits_data_T_8 = size == 2'h1; // @[AMOALU.scala:11:18, :45:26] wire _io_resp_bits_data_T_9 = _io_resp_bits_data_T_8; // @[AMOALU.scala:45:{26,34}] wire _io_resp_bits_data_T_10 = io_resp_bits_data_zeroed_1[15]; // @[AMOALU.scala:44:23, :45:81] wire _io_resp_bits_data_T_11 = _rpq_io_deq_bits_uop_mem_signed & _io_resp_bits_data_T_10; // @[AMOALU.scala:45:{72,81}] wire [47:0] _io_resp_bits_data_T_12 = {48{_io_resp_bits_data_T_11}}; // @[AMOALU.scala:45:{49,72}] wire [47:0] _io_resp_bits_data_T_13 = _io_resp_bits_data_T_7[63:16]; // @[AMOALU.scala:45:{16,94}] wire [47:0] _io_resp_bits_data_T_14 = _io_resp_bits_data_T_9 ? _io_resp_bits_data_T_12 : _io_resp_bits_data_T_13; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _io_resp_bits_data_T_15 = {_io_resp_bits_data_T_14, io_resp_bits_data_zeroed_1}; // @[AMOALU.scala:44:23, :45:{16,20}] wire _io_resp_bits_data_shifted_T_6 = _rpq_io_deq_bits_addr[0]; // @[AMOALU.scala:42:29] wire [7:0] _io_resp_bits_data_shifted_T_7 = _io_resp_bits_data_T_15[15:8]; // @[AMOALU.scala:42:37, :45:16] wire [7:0] _io_resp_bits_data_shifted_T_8 = _io_resp_bits_data_T_15[7:0]; // @[AMOALU.scala:42:55, :45:16] wire [7:0] io_resp_bits_data_shifted_2 = _io_resp_bits_data_shifted_T_6 ? _io_resp_bits_data_shifted_T_7 : _io_resp_bits_data_shifted_T_8; // @[AMOALU.scala:42:{24,29,37,55}] wire [7:0] io_resp_bits_data_zeroed_2 = io_resp_bits_data_shifted_2; // @[AMOALU.scala:42:24, :44:23] wire _io_resp_bits_data_T_16 = size == 2'h0; // @[AMOALU.scala:11:18, :45:26] wire _io_resp_bits_data_T_17 = _io_resp_bits_data_T_16; // @[AMOALU.scala:45:{26,34}] wire _io_resp_bits_data_T_18 = io_resp_bits_data_zeroed_2[7]; // @[AMOALU.scala:44:23, :45:81] wire _io_resp_bits_data_T_19 = _rpq_io_deq_bits_uop_mem_signed & _io_resp_bits_data_T_18; // @[AMOALU.scala:45:{72,81}] wire [55:0] _io_resp_bits_data_T_20 = {56{_io_resp_bits_data_T_19}}; // @[AMOALU.scala:45:{49,72}] wire [55:0] _io_resp_bits_data_T_21 = _io_resp_bits_data_T_15[63:8]; // @[AMOALU.scala:45:{16,94}] wire [55:0] _io_resp_bits_data_T_22 = _io_resp_bits_data_T_17 ? _io_resp_bits_data_T_20 : _io_resp_bits_data_T_21; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _io_resp_bits_data_T_23 = {_io_resp_bits_data_T_22, io_resp_bits_data_zeroed_2}; // @[AMOALU.scala:44:23, :45:{16,20}] assign io_resp_bits_data_0 = _GEN_41 \| ~_io_probe_rdy_T_4 ? _rpq_io_deq_bits_data : _io_resp_bits_data_T_23; // @[package.scala:16:47] wire _T_26 = rpq_io_deq_ready & _rpq_io_deq_valid; // @[Decoupled.scala:51:35] wire _T_28 = _rpq_io_empty & ~commit_line; // @[mshrs.scala:128:19, :140:24, :290:{31,34}] wire _T_33 = _rpq_io_empty \| _rpq_io_deq_valid & ~drain_load; // @[mshrs.scala:128:19, :268:60, :296:{31,52,55}] assign io_commit_val_0 = ~_GEN_41 & _io_probe_rdy_T_4 & ~(_T_26 \| _T_28) & _T_33; // @[Decoupled.scala:51:35] wire _io_meta_read_valid_T = ~io_prober_state_valid_0; // @[mshrs.scala:36:7, :303:27] wire _io_meta_read_valid_T_1 = ~grantack_valid; // @[mshrs.scala:138:21, :303:53] wire _io_meta_read_valid_T_2 = _io_meta_read_valid_T \| _io_meta_read_valid_T_1; // @[mshrs.scala:303:{27,50,53}] wire [3:0] _io_meta_read_valid_T_3 = io_prober_state_bits_0[9:6]; // @[mshrs.scala:36:7, :303:93] wire _io_meta_read_valid_T_4 = _io_meta_read_valid_T_3 != req_idx; // @[mshrs.scala:110:25, :303:{93,120}] wire _io_meta_read_valid_T_5 = _io_meta_read_valid_T_2 \| _io_meta_read_valid_T_4; // @[mshrs.scala:303:{50,69,120}] assign io_meta_read_valid_0 = ~(~(\|state) \| _io_probe_rdy_T_2 \| _io_probe_rdy_T_3 \| _io_probe_rdy_T_4) & _io_probe_rdy_T_8 & _io_meta_read_valid_T_5; // @[package.scala:16:47] wire _T_36 = state == 5'h5; // @[mshrs.scala:107:22, :307:22] wire _T_37 = state == 5'h6; // @[mshrs.scala:107:22, :309:22] wire [3:0] _needs_wb_r_T_6 = {2'h2, io_meta_resp_bits_coh_state_0}; // @[Metadata.scala:120:19] wire _needs_wb_r_T_19 = _needs_wb_r_T_6 == 4'h8; // @[Misc.scala:56:20] wire [2:0] _needs_wb_r_T_21 = _needs_wb_r_T_19 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20] wire _needs_wb_r_T_23 = _needs_wb_r_T_6 == 4'h9; // @[Misc.scala:56:20] wire [2:0] _needs_wb_r_T_25 = _needs_wb_r_T_23 ? 3'h2 : _needs_wb_r_T_21; // @[Misc.scala:38:36, :56:20] wire _needs_wb_r_T_27 = _needs_wb_r_T_6 == 4'hA; // @[Misc.scala:56:20] wire [2:0] _needs_wb_r_T_29 = _needs_wb_r_T_27 ? 3'h1 : _needs_wb_r_T_25; // @[Misc.scala:38:36, :56:20] wire _needs_wb_r_T_31 = _needs_wb_r_T_6 == 4'hB; // @[Misc.scala:56:20] wire _needs_wb_r_T_32 = _needs_wb_r_T_31; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_33 = _needs_wb_r_T_31 ? 3'h1 : _needs_wb_r_T_29; // @[Misc.scala:38:36, :56:20] wire _needs_wb_r_T_35 = _needs_wb_r_T_6 == 4'h4; // @[Misc.scala:56:20] wire _needs_wb_r_T_36 = ~_needs_wb_r_T_35 & _needs_wb_r_T_32; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_37 = _needs_wb_r_T_35 ? 3'h5 : _needs_wb_r_T_33; // @[Misc.scala:38:36, :56:20] wire _needs_wb_r_T_39 = _needs_wb_r_T_6 == 4'h5; // @[Misc.scala:56:20] wire _needs_wb_r_T_40 = ~_needs_wb_r_T_39 & _needs_wb_r_T_36; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_41 = _needs_wb_r_T_39 ? 3'h4 : _needs_wb_r_T_37; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_42 = {1'h0, _needs_wb_r_T_39}; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_43 = _needs_wb_r_T_6 == 4'h6; // @[Misc.scala:56:20] wire _needs_wb_r_T_44 = ~_needs_wb_r_T_43 & _needs_wb_r_T_40; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_45 = _needs_wb_r_T_43 ? 3'h0 : _needs_wb_r_T_41; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_46 = _needs_wb_r_T_43 ? 2'h1 : _needs_wb_r_T_42; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_47 = _needs_wb_r_T_6 == 4'h7; // @[Misc.scala:56:20] wire _needs_wb_r_T_48 = _needs_wb_r_T_47 \| _needs_wb_r_T_44; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_49 = _needs_wb_r_T_47 ? 3'h0 : _needs_wb_r_T_45; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_50 = _needs_wb_r_T_47 ? 2'h1 : _needs_wb_r_T_46; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_51 = _needs_wb_r_T_6 == 4'h0; // @[Misc.scala:56:20] wire _needs_wb_r_T_52 = ~_needs_wb_r_T_51 & _needs_wb_r_T_48; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_53 = _needs_wb_r_T_51 ? 3'h5 : _needs_wb_r_T_49; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_54 = _needs_wb_r_T_51 ? 2'h0 : _needs_wb_r_T_50; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_55 = _needs_wb_r_T_6 == 4'h1; // @[Misc.scala:56:20] wire _needs_wb_r_T_56 = ~_needs_wb_r_T_55 & _needs_wb_r_T_52; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_57 = _needs_wb_r_T_55 ? 3'h4 : _needs_wb_r_T_53; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_58 = _needs_wb_r_T_55 ? 2'h1 : _needs_wb_r_T_54; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_59 = _needs_wb_r_T_6 == 4'h2; // @[Misc.scala:56:20] wire _needs_wb_r_T_60 = ~_needs_wb_r_T_59 & _needs_wb_r_T_56; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_61 = _needs_wb_r_T_59 ? 3'h3 : _needs_wb_r_T_57; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_62 = _needs_wb_r_T_59 ? 2'h2 : _needs_wb_r_T_58; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_63 = _needs_wb_r_T_6 == 4'h3; // @[Misc.scala:56:20] wire needs_wb = _needs_wb_r_T_63 \| _needs_wb_r_T_60; // @[Misc.scala:38:9, :56:20] wire [2:0] needs_wb_r_2 = _needs_wb_r_T_63 ? 3'h3 : _needs_wb_r_T_61; // @[Misc.scala:38:36, :56:20] wire [1:0] needs_wb_r_3 = _needs_wb_r_T_63 ? 2'h2 : _needs_wb_r_T_62; // @[Misc.scala:38:63, :56:20] wire [1:0] needs_wb_meta_state = needs_wb_r_3; // @[Misc.scala:38:63] wire _state_T_30 = ~io_meta_resp_valid_0; // @[mshrs.scala:36:7, :311:18] wire [4:0] _state_T_31 = needs_wb ? 5'h7 : 5'hB; // @[Misc.scala:38:9] wire [4:0] _state_T_32 = _state_T_30 ? 5'h4 : _state_T_31; // @[mshrs.scala:311:{17,18}, :312:17] wire _T_38 = state == 5'h7; // @[mshrs.scala:107:22, :313:22] wire _T_40 = state == 5'h9; // @[mshrs.scala:107:22, :319:22] assign io_wb_req_valid_0 = ~(~(\|state) \| _io_probe_rdy_T_2 \| _io_probe_rdy_T_3 \| _io_probe_rdy_T_4 \| _io_probe_rdy_T_8 \| _T_36 \| _T_37 \| _T_38) & _T_40; // @[package.scala:16:47] wire _T_42 = state == 5'hA; // @[mshrs.scala:107:22, :324:22] wire _T_43 = state == 5'hB; // @[mshrs.scala:107:22, :328:22] wire _GEN_42 = _io_probe_rdy_T_8 \| _T_36 \| _T_37 \| _T_38 \| _T_40 \| _T_42; // @[mshrs.scala:148:129, :200:21, :302:39, :307:{22,41}, :309:{22,41}, :313:{22,40}, :319:{22,36}, :324:{22,37}, :328:41] assign io_lb_read_offset_0 = _GEN_41 ? _io_lb_read_offset_T[2:0] : _io_probe_rdy_T_4 ? _io_lb_read_offset_T_1[2:0] : _GEN_42 \| ~_T_43 ? _io_lb_read_offset_T[2:0] : refill_ctr; // @[package.scala:16:47] wire _GEN_43 = _io_probe_rdy_T_2 \| _io_probe_rdy_T_3 \| _io_probe_rdy_T_4 \| _GEN_42; // @[package.scala:16:47] assign io_refill_valid_0 = ~(~(\|state) \| _GEN_43) & _T_43; // @[package.scala:16:47] wire [3:0] _refill_ctr_T = {1'h0, refill_ctr} + 4'h1; // @[mshrs.scala:139:24, :333:32] wire [2:0] _refill_ctr_T_1 = _refill_ctr_T[2:0]; // @[mshrs.scala:333:32] wire _T_46 = state == 5'hC; // @[mshrs.scala:107:22, :338:22] wire _GEN_44 = _io_probe_rdy_T_8 \| _T_36 \| _T_37 \| _T_38 \| _T_40 \| _T_42 \| _T_43; // @[mshrs.scala:148:129, :176:26, :302:39, :307:{22,41}, :309:{22,41}, :313:{22,40}, :319:{22,36}, :324:{22,37}, :328:{22,41}, :338:39] wire _GEN_45 = _io_probe_rdy_T_4 \| _GEN_44; // @[package.scala:16:47] wire _GEN_46 = ~(\|state) \| _io_probe_rdy_T_2 \| _io_probe_rdy_T_3 \| _GEN_45; // @[package.scala:16:47] assign io_replay_valid_0 = ~_GEN_46 & _T_46 & _rpq_io_deq_valid; // @[mshrs.scala:36:7, :128:19, :176:26, :234:30, :241:40, :246:41, :266:45, :302:39, :307:41, :309:41, :313:40, :319:36, :324:37, :328:41, :338:{22,39}, :339:15] assign rpq_io_deq_ready = ~_GEN_41 & (_io_probe_rdy_T_4 ? _rpq_io_deq_ready_T : ~_GEN_44 & _T_46 & io_replay_ready_0); // @[package.scala:16:47] wire _GEN_47 = _GEN_46 \| ~_T_46; // @[mshrs.scala:176:26, :177:26, :234:30, :241:40, :246:41, :266:45, :302:39, :307:41, :309:41, :313:40, :319:36, :324:37, :328:41, :338:{22,39}] assign io_replay_bits_way_en_0 = _GEN_47 ? _rpq_io_deq_bits_way_en : req_way_en; // @[mshrs.scala:36:7, :109:20, :128:19, :177:26, :234:30, :241:40, :246:41, :266:45, :302:39, :307:41, :309:41, :313:40, :319:36, :324:37, :328:41, :338:39] wire [5:0] _io_replay_bits_addr_T = _rpq_io_deq_bits_addr[5:0]; // @[mshrs.scala:128:19, :341:70] wire [33:0] _io_replay_bits_addr_T_1 = {io_replay_bits_addr_hi, _io_replay_bits_addr_T}; // @[mshrs.scala:341:{31,70}] assign io_replay_bits_addr_0 = _GEN_47 ? _rpq_io_deq_bits_addr : _io_replay_bits_addr_T_1; // @[mshrs.scala:36:7, :128:19, :177:26, :234:30, :241:40, :246:41, :266:45, :302:39, :307:41, :309:41, :313:40, :319:36, :324:37, :328:41, :338:39, :341:31] wire _T_48 = _rpq_io_deq_bits_uop_mem_cmd == 5'h1; // @[Consts.scala:90:32] wire _r_c_cat_T; // @[Consts.scala:90:32] assign _r_c_cat_T = _T_48; // @[Consts.scala:90:32] wire _r_c_cat_T_23; // @[Consts.scala:90:32] assign _r_c_cat_T_23 = _T_48; // @[Consts.scala:90:32] wire _T_49 = _rpq_io_deq_bits_uop_mem_cmd == 5'h11; // @[Consts.scala:90:49] wire _r_c_cat_T_1; // @[Consts.scala:90:49] assign _r_c_cat_T_1 = _T_49; // @[Consts.scala:90:49] wire _r_c_cat_T_24; // @[Consts.scala:90:49] assign _r_c_cat_T_24 = _T_49; // @[Consts.scala:90:49] wire _T_51 = _rpq_io_deq_bits_uop_mem_cmd == 5'h7; // @[Consts.scala:90:66] wire _r_c_cat_T_3; // @[Consts.scala:90:66] assign _r_c_cat_T_3 = _T_51; // @[Consts.scala:90:66] wire _r_c_cat_T_26; // @[Consts.scala:90:66] assign _r_c_cat_T_26 = _T_51; // @[Consts.scala:90:66] wire _T_53 = _rpq_io_deq_bits_uop_mem_cmd == 5'h4; // @[package.scala:16:47] wire _r_c_cat_T_5; // @[package.scala:16:47] assign _r_c_cat_T_5 = _T_53; // @[package.scala:16:47] wire _r_c_cat_T_28; // @[package.scala:16:47] assign _r_c_cat_T_28 = _T_53; // @[package.scala:16:47] wire _T_54 = _rpq_io_deq_bits_uop_mem_cmd == 5'h9; // @[package.scala:16:47] wire _r_c_cat_T_6; // @[package.scala:16:47] assign _r_c_cat_T_6 = _T_54; // @[package.scala:16:47] wire _r_c_cat_T_29; // @[package.scala:16:47] assign _r_c_cat_T_29 = _T_54; // @[package.scala:16:47] wire _T_55 = _rpq_io_deq_bits_uop_mem_cmd == 5'hA; // @[package.scala:16:47] wire _r_c_cat_T_7; // @[package.scala:16:47] assign _r_c_cat_T_7 = _T_55; // @[package.scala:16:47] wire _r_c_cat_T_30; // @[package.scala:16:47] assign _r_c_cat_T_30 = _T_55; // @[package.scala:16:47] wire _T_56 = _rpq_io_deq_bits_uop_mem_cmd == 5'hB; // @[package.scala:16:47] wire _r_c_cat_T_8; // @[package.scala:16:47] assign _r_c_cat_T_8 = _T_56; // @[package.scala:16:47] wire _r_c_cat_T_31; // @[package.scala:16:47] assign _r_c_cat_T_31 = _T_56; // @[package.scala:16:47] wire _T_60 = _rpq_io_deq_bits_uop_mem_cmd == 5'h8; // @[package.scala:16:47] wire _r_c_cat_T_12; // @[package.scala:16:47] assign _r_c_cat_T_12 = _T_60; // @[package.scala:16:47] wire _r_c_cat_T_35; // @[package.scala:16:47] assign _r_c_cat_T_35 = _T_60; // @[package.scala:16:47] wire _T_61 = _rpq_io_deq_bits_uop_mem_cmd == 5'hC; // @[package.scala:16:47] wire _r_c_cat_T_13; // @[package.scala:16:47] assign _r_c_cat_T_13 = _T_61; // @[package.scala:16:47] wire _r_c_cat_T_36; // @[package.scala:16:47] assign _r_c_cat_T_36 = _T_61; // @[package.scala:16:47] wire _T_62 = _rpq_io_deq_bits_uop_mem_cmd == 5'hD; // @[package.scala:16:47] wire _r_c_cat_T_14; // @[package.scala:16:47] assign _r_c_cat_T_14 = _T_62; // @[package.scala:16:47] wire _r_c_cat_T_37; // @[package.scala:16:47] assign _r_c_cat_T_37 = _T_62; // @[package.scala:16:47] wire _T_63 = _rpq_io_deq_bits_uop_mem_cmd == 5'hE; // @[package.scala:16:47] wire _r_c_cat_T_15; // @[package.scala:16:47] assign _r_c_cat_T_15 = _T_63; // @[package.scala:16:47] wire _r_c_cat_T_38; // @[package.scala:16:47] assign _r_c_cat_T_38 = _T_63; // @[package.scala:16:47] wire _T_64 = _rpq_io_deq_bits_uop_mem_cmd == 5'hF; // @[package.scala:16:47] wire _r_c_cat_T_16; // @[package.scala:16:47] assign _r_c_cat_T_16 = _T_64; // @[package.scala:16:47] wire _r_c_cat_T_39; // @[package.scala:16:47] assign _r_c_cat_T_39 = _T_64; // @[package.scala:16:47] wire _T_71 = io_replay_ready_0 & io_replay_valid_0 & (_T_48 \| _T_49 \| _T_51 \| _T_53 \| _T_54 \| _T_55 \| _T_56 \| _T_60 \| _T_61 \| _T_62 \| _T_63 \| _T_64); // @[Decoupled.scala:51:35] wire _r_c_cat_T_2 = _r_c_cat_T \| _r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _r_c_cat_T_4 = _r_c_cat_T_2 \| _r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _r_c_cat_T_9 = _r_c_cat_T_5 \| _r_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_10 = _r_c_cat_T_9 \| _r_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_11 = _r_c_cat_T_10 \| _r_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_17 = _r_c_cat_T_12 \| _r_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_18 = _r_c_cat_T_17 \| _r_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_19 = _r_c_cat_T_18 \| _r_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_20 = _r_c_cat_T_19 \| _r_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_21 = _r_c_cat_T_11 \| _r_c_cat_T_20; // @[package.scala:81:59] wire _r_c_cat_T_22 = _r_c_cat_T_4 \| _r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _r_c_cat_T_25 = _r_c_cat_T_23 \| _r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _r_c_cat_T_27 = _r_c_cat_T_25 \| _r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _r_c_cat_T_32 = _r_c_cat_T_28 \| _r_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_33 = _r_c_cat_T_32 \| _r_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_34 = _r_c_cat_T_33 \| _r_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_40 = _r_c_cat_T_35 \| _r_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_41 = _r_c_cat_T_40 \| _r_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_42 = _r_c_cat_T_41 \| _r_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_43 = _r_c_cat_T_42 \| _r_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_44 = _r_c_cat_T_34 \| _r_c_cat_T_43; // @[package.scala:81:59] wire _r_c_cat_T_45 = _r_c_cat_T_27 \| _r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _r_c_cat_T_46 = _rpq_io_deq_bits_uop_mem_cmd == 5'h3; // @[Consts.scala:91:54] wire _r_c_cat_T_47 = _r_c_cat_T_45 \| _r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _r_c_cat_T_49 = _r_c_cat_T_47 \| _r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] r_c = {_r_c_cat_T_22, _r_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _r_T_64 = {r_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19] wire _r_T_89 = _r_T_64 == 4'hC; // @[Misc.scala:49:20] wire [1:0] _r_T_91 = {1'h0, _r_T_89}; // @[Misc.scala:35:36, :49:20] wire _r_T_92 = _r_T_64 == 4'hD; // @[Misc.scala:49:20] wire [1:0] _r_T_94 = _r_T_92 ? 2'h2 : _r_T_91; // @[Misc.scala:35:36, :49:20] wire _r_T_95 = _r_T_64 == 4'h4; // @[Misc.scala:49:20] wire [1:0] _r_T_97 = _r_T_95 ? 2'h1 : _r_T_94; // @[Misc.scala:35:36, :49:20] wire _r_T_98 = _r_T_64 == 4'h5; // @[Misc.scala:49:20] wire [1:0] _r_T_100 = _r_T_98 ? 2'h2 : _r_T_97; // @[Misc.scala:35:36, :49:20] wire _r_T_101 = _r_T_64 == 4'h0; // @[Misc.scala:49:20] wire [1:0] _r_T_103 = _r_T_101 ? 2'h0 : _r_T_100; // @[Misc.scala:35:36, :49:20] wire _r_T_104 = _r_T_64 == 4'hE; // @[Misc.scala:49:20] wire _r_T_105 = _r_T_104; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_106 = _r_T_104 ? 2'h3 : _r_T_103; // @[Misc.scala:35:36, :49:20] wire _r_T_107 = &_r_T_64; // @[Misc.scala:49:20] wire _r_T_108 = _r_T_107 \| _r_T_105; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_109 = _r_T_107 ? 2'h3 : _r_T_106; // @[Misc.scala:35:36, :49:20] wire _r_T_110 = _r_T_64 == 4'h6; // @[Misc.scala:49:20] wire _r_T_111 = _r_T_110 \| _r_T_108; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_112 = _r_T_110 ? 2'h2 : _r_T_109; // @[Misc.scala:35:36, :49:20] wire _r_T_113 = _r_T_64 == 4'h7; // @[Misc.scala:49:20] wire _r_T_114 = _r_T_113 \| _r_T_111; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_115 = _r_T_113 ? 2'h3 : _r_T_112; // @[Misc.scala:35:36, :49:20] wire _r_T_116 = _r_T_64 == 4'h1; // @[Misc.scala:49:20] wire _r_T_117 = _r_T_116 \| _r_T_114; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_118 = _r_T_116 ? 2'h1 : _r_T_115; // @[Misc.scala:35:36, :49:20] wire _r_T_119 = _r_T_64 == 4'h2; // @[Misc.scala:49:20] wire _r_T_120 = _r_T_119 \| _r_T_117; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_121 = _r_T_119 ? 2'h2 : _r_T_118; // @[Misc.scala:35:36, :49:20] wire _r_T_122 = _r_T_64 == 4'h3; // @[Misc.scala:49:20] wire is_hit = _r_T_122 \| _r_T_120; // @[Misc.scala:35:9, :49:20] wire [1:0] r_2_1 = _r_T_122 ? 2'h3 : _r_T_121; // @[Misc.scala:35:36, :49:20] wire [1:0] coh_on_hit_state = r_2_1; // @[Misc.scala:35:36] wire _GEN_48 = _T_40 \| _T_42 \| _T_43 \| _T_46; // @[mshrs.scala:156:26, :319:{22,36}, :324:{22,37}, :328:{22,41}, :338:{22,39}, :351:44] assign io_meta_write_valid_0 = ~(~(\|state) \| _io_probe_rdy_T_2 \| _io_probe_rdy_T_3 \| _io_probe_rdy_T_4 \| _io_probe_rdy_T_8 \| _T_36 \| _T_37) & (_T_38 \| ~_GEN_48 & _sec_rdy_T_4); // @[package.scala:16:47] wire _GEN_49 = _io_probe_rdy_T_8 \| _T_36 \| _T_37 \| _T_38 \| _GEN_48; // @[mshrs.scala:148:129, :156:26, :158:31, :302:39, :307:{22,41}, :309:{22,41}, :313:{22,40}, :319:36, :324:37, :328:41, :338:39, :351:44] assign io_meta_write_bits_data_coh_state_0 = ~(\|state) \| _io_probe_rdy_T_2 \| _io_probe_rdy_T_3 \| _io_probe_rdy_T_4 \| _GEN_49 \| ~_sec_rdy_T_4 ? coh_on_clear_state : new_coh_state; // @[package.scala:16:47] wire _GEN_50 = _io_probe_rdy_T_4 \| _io_probe_rdy_T_8 \| _T_36 \| _T_37 \| _T_38 \| _T_40 \| _T_42 \| _T_43 \| _T_46 \| _sec_rdy_T_4; // @[package.scala:16:47] assign io_mem_finish_valid_0 = ~(~(\|state) \| _io_probe_rdy_T_2 \| _io_probe_rdy_T_3 \| _GEN_50) & _sec_rdy_T_5 & grantack_valid; // @[package.scala:16:47] wire [4:0] _state_T_33 = finish_to_prefetch ? 5'h11 : 5'h0; // @[mshrs.scala:142:31, :368:17] wire _GEN_51 = _sec_rdy_T_4 \| _sec_rdy_T_5 \| _sec_rdy_T_6; // @[package.scala:16:47] wire _GEN_52 = _T_46 \| _GEN_51; // @[mshrs.scala:162:26, :338:{22,39}, :351:44, :361:42, :367:42, :369:38] wire _GEN_53 = _io_probe_rdy_T_4 \| _io_probe_rdy_T_8 \| _T_36 \| _T_37 \| _T_38 \| _T_40 \| _T_42 \| _T_43 \| _GEN_52; // @[package.scala:16:47] wire _GEN_54 = _io_probe_rdy_T_2 \| _io_probe_rdy_T_3 \| _GEN_53; // @[package.scala:16:47] assign io_req_pri_rdy_0 = ~(\|state) \| ~_GEN_54 & _io_way_valid_T_1; // @[package.scala:16:47] wire _T_87 = io_req_sec_val_0 & ~io_req_sec_rdy_0 \| io_clear_prefetch_0; // @[mshrs.scala:36:7, :371:{27,30,47}] wire _r_c_cat_T_52 = _r_c_cat_T_50 \| _r_c_cat_T_51; // @[Consts.scala:90:{32,42,49}] wire _r_c_cat_T_54 = _r_c_cat_T_52 \| _r_c_cat_T_53; // @[Consts.scala:90:{42,59,66}] wire _r_c_cat_T_59 = _r_c_cat_T_55 \| _r_c_cat_T_56; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_60 = _r_c_cat_T_59 \| _r_c_cat_T_57; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_61 = _r_c_cat_T_60 \| _r_c_cat_T_58; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_67 = _r_c_cat_T_62 \| _r_c_cat_T_63; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_68 = _r_c_cat_T_67 \| _r_c_cat_T_64; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_69 = _r_c_cat_T_68 \| _r_c_cat_T_65; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_70 = _r_c_cat_T_69 \| _r_c_cat_T_66; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_71 = _r_c_cat_T_61 \| _r_c_cat_T_70; // @[package.scala:81:59] wire _r_c_cat_T_72 = _r_c_cat_T_54 \| _r_c_cat_T_71; // @[Consts.scala:87:44, :90:{59,76}] wire _r_c_cat_T_75 = _r_c_cat_T_73 \| _r_c_cat_T_74; // @[Consts.scala:90:{32,42,49}] wire _r_c_cat_T_77 = _r_c_cat_T_75 \| _r_c_cat_T_76; // @[Consts.scala:90:{42,59,66}] wire _r_c_cat_T_82 = _r_c_cat_T_78 \| _r_c_cat_T_79; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_83 = _r_c_cat_T_82 \| _r_c_cat_T_80; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_84 = _r_c_cat_T_83 \| _r_c_cat_T_81; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_90 = _r_c_cat_T_85 \| _r_c_cat_T_86; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_91 = _r_c_cat_T_90 \| _r_c_cat_T_87; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_92 = _r_c_cat_T_91 \| _r_c_cat_T_88; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_93 = _r_c_cat_T_92 \| _r_c_cat_T_89; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_94 = _r_c_cat_T_84 \| _r_c_cat_T_93; // @[package.scala:81:59] wire _r_c_cat_T_95 = _r_c_cat_T_77 \| _r_c_cat_T_94; // @[Consts.scala:87:44, :90:{59,76}] wire _r_c_cat_T_97 = _r_c_cat_T_95 \| _r_c_cat_T_96; // @[Consts.scala:90:76, :91:{47,54}] wire _r_c_cat_T_99 = _r_c_cat_T_97 \| _r_c_cat_T_98; // @[Consts.scala:91:{47,64,71}] wire [1:0] r_c_1 = {_r_c_cat_T_72, _r_c_cat_T_99}; // @[Metadata.scala:29:18] wire [3:0] _r_T_123 = {r_c_1, new_coh_state}; // @[Metadata.scala:29:18, :58:19] wire _r_T_148 = _r_T_123 == 4'hC; // @[Misc.scala:49:20] wire [1:0] _r_T_150 = {1'h0, _r_T_148}; // @[Misc.scala:35:36, :49:20] wire _r_T_151 = _r_T_123 == 4'hD; // @[Misc.scala:49:20] wire [1:0] _r_T_153 = _r_T_151 ? 2'h2 : _r_T_150; // @[Misc.scala:35:36, :49:20] wire _r_T_154 = _r_T_123 == 4'h4; // @[Misc.scala:49:20] wire [1:0] _r_T_156 = _r_T_154 ? 2'h1 : _r_T_153; // @[Misc.scala:35:36, :49:20] wire _r_T_157 = _r_T_123 == 4'h5; // @[Misc.scala:49:20] wire [1:0] _r_T_159 = _r_T_157 ? 2'h2 : _r_T_156; // @[Misc.scala:35:36, :49:20] wire _r_T_160 = _r_T_123 == 4'h0; // @[Misc.scala:49:20] wire [1:0] _r_T_162 = _r_T_160 ? 2'h0 : _r_T_159; // @[Misc.scala:35:36, :49:20] wire _r_T_163 = _r_T_123 == 4'hE; // @[Misc.scala:49:20] wire _r_T_164 = _r_T_163; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_165 = _r_T_163 ? 2'h3 : _r_T_162; // @[Misc.scala:35:36, :49:20] wire _r_T_166 = &_r_T_123; // @[Misc.scala:49:20] wire _r_T_167 = _r_T_166 \| _r_T_164; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_168 = _r_T_166 ? 2'h3 : _r_T_165; // @[Misc.scala:35:36, :49:20] wire _r_T_169 = _r_T_123 == 4'h6; // @[Misc.scala:49:20] wire _r_T_170 = _r_T_169 \| _r_T_167; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_171 = _r_T_169 ? 2'h2 : _r_T_168; // @[Misc.scala:35:36, :49:20] wire _r_T_172 = _r_T_123 == 4'h7; // @[Misc.scala:49:20] wire _r_T_173 = _r_T_172 \| _r_T_170; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_174 = _r_T_172 ? 2'h3 : _r_T_171; // @[Misc.scala:35:36, :49:20] wire _r_T_175 = _r_T_123 == 4'h1; // @[Misc.scala:49:20] wire _r_T_176 = _r_T_175 \| _r_T_173; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_177 = _r_T_175 ? 2'h1 : _r_T_174; // @[Misc.scala:35:36, :49:20] wire _r_T_178 = _r_T_123 == 4'h2; // @[Misc.scala:49:20] wire _r_T_179 = _r_T_178 \| _r_T_176; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_180 = _r_T_178 ? 2'h2 : _r_T_177; // @[Misc.scala:35:36, :49:20] wire _r_T_181 = _r_T_123 == 4'h3; // @[Misc.scala:49:20] wire is_hit_1 = _r_T_181 \| _r_T_179; // @[Misc.scala:35:9, :49:20] wire [1:0] r_2_2 = _r_T_181 ? 2'h3 : _r_T_180; // @[Misc.scala:35:36, :49:20] wire [1:0] coh_on_hit_1_state = r_2_2; // @[Misc.scala:35:36] wire [4:0] state_new_state_1; // @[mshrs.scala:210:29] wire _state_T_35 = ~_state_T_34; // @[mshrs.scala:213:11] wire _state_T_36 = ~_rpq_io_enq_ready; // @[mshrs.scala:128:19, :213:11] wire _state_req_needs_wb_r_T_83 = _state_req_needs_wb_r_T_70 == 4'h8; // @[Misc.scala:56:20] wire [2:0] _state_req_needs_wb_r_T_85 = _state_req_needs_wb_r_T_83 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_87 = _state_req_needs_wb_r_T_70 == 4'h9; // @[Misc.scala:56:20] wire [2:0] _state_req_needs_wb_r_T_89 = _state_req_needs_wb_r_T_87 ? 3'h2 : _state_req_needs_wb_r_T_85; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_91 = _state_req_needs_wb_r_T_70 == 4'hA; // @[Misc.scala:56:20] wire [2:0] _state_req_needs_wb_r_T_93 = _state_req_needs_wb_r_T_91 ? 3'h1 : _state_req_needs_wb_r_T_89; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_95 = _state_req_needs_wb_r_T_70 == 4'hB; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_96 = _state_req_needs_wb_r_T_95; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_97 = _state_req_needs_wb_r_T_95 ? 3'h1 : _state_req_needs_wb_r_T_93; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_99 = _state_req_needs_wb_r_T_70 == 4'h4; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_100 = ~_state_req_needs_wb_r_T_99 & _state_req_needs_wb_r_T_96; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_101 = _state_req_needs_wb_r_T_99 ? 3'h5 : _state_req_needs_wb_r_T_97; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_103 = _state_req_needs_wb_r_T_70 == 4'h5; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_104 = ~_state_req_needs_wb_r_T_103 & _state_req_needs_wb_r_T_100; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_105 = _state_req_needs_wb_r_T_103 ? 3'h4 : _state_req_needs_wb_r_T_101; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_106 = {1'h0, _state_req_needs_wb_r_T_103}; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_107 = _state_req_needs_wb_r_T_70 == 4'h6; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_108 = ~_state_req_needs_wb_r_T_107 & _state_req_needs_wb_r_T_104; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_109 = _state_req_needs_wb_r_T_107 ? 3'h0 : _state_req_needs_wb_r_T_105; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_110 = _state_req_needs_wb_r_T_107 ? 2'h1 : _state_req_needs_wb_r_T_106; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_111 = _state_req_needs_wb_r_T_70 == 4'h7; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_112 = _state_req_needs_wb_r_T_111 \| _state_req_needs_wb_r_T_108; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_113 = _state_req_needs_wb_r_T_111 ? 3'h0 : _state_req_needs_wb_r_T_109; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_114 = _state_req_needs_wb_r_T_111 ? 2'h1 : _state_req_needs_wb_r_T_110; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_115 = _state_req_needs_wb_r_T_70 == 4'h0; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_116 = ~_state_req_needs_wb_r_T_115 & _state_req_needs_wb_r_T_112; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_117 = _state_req_needs_wb_r_T_115 ? 3'h5 : _state_req_needs_wb_r_T_113; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_118 = _state_req_needs_wb_r_T_115 ? 2'h0 : _state_req_needs_wb_r_T_114; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_119 = _state_req_needs_wb_r_T_70 == 4'h1; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_120 = ~_state_req_needs_wb_r_T_119 & _state_req_needs_wb_r_T_116; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_121 = _state_req_needs_wb_r_T_119 ? 3'h4 : _state_req_needs_wb_r_T_117; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_122 = _state_req_needs_wb_r_T_119 ? 2'h1 : _state_req_needs_wb_r_T_118; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_123 = _state_req_needs_wb_r_T_70 == 4'h2; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_124 = ~_state_req_needs_wb_r_T_123 & _state_req_needs_wb_r_T_120; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_125 = _state_req_needs_wb_r_T_123 ? 3'h3 : _state_req_needs_wb_r_T_121; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_126 = _state_req_needs_wb_r_T_123 ? 2'h2 : _state_req_needs_wb_r_T_122; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_127 = _state_req_needs_wb_r_T_70 == 4'h3; // @[Misc.scala:56:20] wire state_req_needs_wb_r_1_1 = _state_req_needs_wb_r_T_127 \| _state_req_needs_wb_r_T_124; // @[Misc.scala:38:9, :56:20] wire [2:0] state_req_needs_wb_r_2_1 = _state_req_needs_wb_r_T_127 ? 3'h3 : _state_req_needs_wb_r_T_125; // @[Misc.scala:38:36, :56:20] wire [1:0] state_req_needs_wb_r_3_1 = _state_req_needs_wb_r_T_127 ? 2'h2 : _state_req_needs_wb_r_T_126; // @[Misc.scala:38:63, :56:20] wire [1:0] state_req_needs_wb_meta_1_state = state_req_needs_wb_r_3_1; // @[Misc.scala:38:63] wire _state_r_c_cat_T_52 = _state_r_c_cat_T_50 \| _state_r_c_cat_T_51; // @[Consts.scala:90:{32,42,49}] wire _state_r_c_cat_T_54 = _state_r_c_cat_T_52 \| _state_r_c_cat_T_53; // @[Consts.scala:90:{42,59,66}] wire _state_r_c_cat_T_59 = _state_r_c_cat_T_55 \| _state_r_c_cat_T_56; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_60 = _state_r_c_cat_T_59 \| _state_r_c_cat_T_57; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_61 = _state_r_c_cat_T_60 \| _state_r_c_cat_T_58; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_67 = _state_r_c_cat_T_62 \| _state_r_c_cat_T_63; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_68 = _state_r_c_cat_T_67 \| _state_r_c_cat_T_64; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_69 = _state_r_c_cat_T_68 \| _state_r_c_cat_T_65; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_70 = _state_r_c_cat_T_69 \| _state_r_c_cat_T_66; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_71 = _state_r_c_cat_T_61 \| _state_r_c_cat_T_70; // @[package.scala:81:59] wire _state_r_c_cat_T_72 = _state_r_c_cat_T_54 \| _state_r_c_cat_T_71; // @[Consts.scala:87:44, :90:{59,76}] wire _state_r_c_cat_T_75 = _state_r_c_cat_T_73 \| _state_r_c_cat_T_74; // @[Consts.scala:90:{32,42,49}] wire _state_r_c_cat_T_77 = _state_r_c_cat_T_75 \| _state_r_c_cat_T_76; // @[Consts.scala:90:{42,59,66}] wire _state_r_c_cat_T_82 = _state_r_c_cat_T_78 \| _state_r_c_cat_T_79; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_83 = _state_r_c_cat_T_82 \| _state_r_c_cat_T_80; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_84 = _state_r_c_cat_T_83 \| _state_r_c_cat_T_81; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_90 = _state_r_c_cat_T_85 \| _state_r_c_cat_T_86; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_91 = _state_r_c_cat_T_90 \| _state_r_c_cat_T_87; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_92 = _state_r_c_cat_T_91 \| _state_r_c_cat_T_88; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_93 = _state_r_c_cat_T_92 \| _state_r_c_cat_T_89; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_94 = _state_r_c_cat_T_84 \| _state_r_c_cat_T_93; // @[package.scala:81:59] wire _state_r_c_cat_T_95 = _state_r_c_cat_T_77 \| _state_r_c_cat_T_94; // @[Consts.scala:87:44, :90:{59,76}] wire _state_r_c_cat_T_97 = _state_r_c_cat_T_95 \| _state_r_c_cat_T_96; // @[Consts.scala:90:76, :91:{47,54}] wire _state_r_c_cat_T_99 = _state_r_c_cat_T_97 \| _state_r_c_cat_T_98; // @[Consts.scala:91:{47,64,71}] wire [1:0] state_r_c_1 = {_state_r_c_cat_T_72, _state_r_c_cat_T_99}; // @[Metadata.scala:29:18] wire [3:0] _state_r_T_59 = {state_r_c_1, io_req_old_meta_coh_state_0}; // @[Metadata.scala:29:18, :58:19] wire _state_r_T_84 = _state_r_T_59 == 4'hC; // @[Misc.scala:49:20] wire [1:0] _state_r_T_86 = {1'h0, _state_r_T_84}; // @[Misc.scala:35:36, :49:20] wire _state_r_T_87 = _state_r_T_59 == 4'hD; // @[Misc.scala:49:20] wire [1:0] _state_r_T_89 = _state_r_T_87 ? 2'h2 : _state_r_T_86; // @[Misc.scala:35:36, :49:20] wire _state_r_T_90 = _state_r_T_59 == 4'h4; // @[Misc.scala:49:20] wire [1:0] _state_r_T_92 = _state_r_T_90 ? 2'h1 : _state_r_T_89; // @[Misc.scala:35:36, :49:20] wire _state_r_T_93 = _state_r_T_59 == 4'h5; // @[Misc.scala:49:20] wire [1:0] _state_r_T_95 = _state_r_T_93 ? 2'h2 : _state_r_T_92; // @[Misc.scala:35:36, :49:20] wire _state_r_T_96 = _state_r_T_59 == 4'h0; // @[Misc.scala:49:20] wire [1:0] _state_r_T_98 = _state_r_T_96 ? 2'h0 : _state_r_T_95; // @[Misc.scala:35:36, :49:20] wire _state_r_T_99 = _state_r_T_59 == 4'hE; // @[Misc.scala:49:20] wire _state_r_T_100 = _state_r_T_99; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_101 = _state_r_T_99 ? 2'h3 : _state_r_T_98; // @[Misc.scala:35:36, :49:20] wire _state_r_T_102 = &_state_r_T_59; // @[Misc.scala:49:20] wire _state_r_T_103 = _state_r_T_102 \| _state_r_T_100; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_104 = _state_r_T_102 ? 2'h3 : _state_r_T_101; // @[Misc.scala:35:36, :49:20] wire _state_r_T_105 = _state_r_T_59 == 4'h6; // @[Misc.scala:49:20] wire _state_r_T_106 = _state_r_T_105 \| _state_r_T_103; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_107 = _state_r_T_105 ? 2'h2 : _state_r_T_104; // @[Misc.scala:35:36, :49:20] wire _state_r_T_108 = _state_r_T_59 == 4'h7; // @[Misc.scala:49:20] wire _state_r_T_109 = _state_r_T_108 \| _state_r_T_106; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_110 = _state_r_T_108 ? 2'h3 : _state_r_T_107; // @[Misc.scala:35:36, :49:20] wire _state_r_T_111 = _state_r_T_59 == 4'h1; // @[Misc.scala:49:20] wire _state_r_T_112 = _state_r_T_111 \| _state_r_T_109; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_113 = _state_r_T_111 ? 2'h1 : _state_r_T_110; // @[Misc.scala:35:36, :49:20] wire _state_r_T_114 = _state_r_T_59 == 4'h2; // @[Misc.scala:49:20] wire _state_r_T_115 = _state_r_T_114 \| _state_r_T_112; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_116 = _state_r_T_114 ? 2'h2 : _state_r_T_113; // @[Misc.scala:35:36, :49:20] wire _state_r_T_117 = _state_r_T_59 == 4'h3; // @[Misc.scala:49:20] wire state_is_hit_1 = _state_r_T_117 \| _state_r_T_115; // @[Misc.scala:35:9, :49:20] wire [1:0] state_r_2_1 = _state_r_T_117 ? 2'h3 : _state_r_T_116; // @[Misc.scala:35:36, :49:20] wire [1:0] state_coh_on_hit_1_state = state_r_2_1; // @[Misc.scala:35:36] wire _state_T_39 = _state_T_37 \| _state_T_38; // @[Consts.scala:90:{32,42,49}] wire _state_T_41 = _state_T_39 \| _state_T_40; // @[Consts.scala:90:{42,59,66}] wire _state_T_46 = _state_T_42 \| _state_T_43; // @[package.scala:16:47, :81:59] wire _state_T_47 = _state_T_46 \| _state_T_44; // @[package.scala:16:47, :81:59] wire _state_T_48 = _state_T_47 \| _state_T_45; // @[package.scala:16:47, :81:59] wire _state_T_54 = _state_T_49 \| _state_T_50; // @[package.scala:16:47, :81:59] wire _state_T_55 = _state_T_54 \| _state_T_51; // @[package.scala:16:47, :81:59] wire _state_T_56 = _state_T_55 \| _state_T_52; // @[package.scala:16:47, :81:59] wire _state_T_57 = _state_T_56 \| _state_T_53; // @[package.scala:16:47, :81:59] wire _state_T_58 = _state_T_48 \| _state_T_57; // @[package.scala:81:59] wire _state_T_59 = _state_T_41 \| _state_T_58; // @[Consts.scala:87:44, :90:{59,76}] wire _state_T_61 = ~_state_T_60; // @[mshrs.scala:220:15] wire _state_T_62 = ~_state_T_59; // @[Consts.scala:90:76]
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_124 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_sink_valid_0 of AsyncResetSynchronizerShiftReg_w1_d3_i0_139 connect io_out_sink_valid_0.clock, clock connect io_out_sink_valid_0.reset, reset connect io_out_sink_valid_0.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_sink_valid_0.io.q connect io.out, _io_out_WIRE	module AsyncValidSync_124( // @[AsyncQueue.scala:58:7] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in = 1'h1; // @[ShiftReg.scala:45:23] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_139 io_out_sink_valid_0 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetRegVec_w1_i0_6 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>} node _reg_T = asAsyncReset(reset) regreset reg : UInt<1>, clock, _reg_T, UInt<1>(0h0) when io.en : connect reg, io.d connect io.q, reg	module AsyncResetRegVec_w1_i0_6( // @[AsyncResetReg.scala:56:7] input clock, // @[AsyncResetReg.scala:56:7] input io_d, // @[AsyncResetReg.scala:59:14] input io_en // @[AsyncResetReg.scala:59:14] ); wire io_d_0 = io_d; // @[AsyncResetReg.scala:56:7] wire io_en_0 = io_en; // @[AsyncResetReg.scala:56:7] wire _reg_T = 1'h1; // @[AsyncResetReg.scala:56:7, :61:29] wire io_q = 1'h0; // @[AsyncResetReg.scala:56:7] wire reg_0 = 1'h0; // @[AsyncResetReg.scala:61:50] endmodule
Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_123 : output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node rawIn_exp = bits(io.in, 31, 23) node _rawIn_isZero_T = bits(rawIn_exp, 8, 6) node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0)) node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7) node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3)) wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T) connect rawIn.isNaN, _rawIn_out_isNaN_T_1 node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0)) node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1) connect rawIn.isInf, _rawIn_out_isInf_T_2 connect rawIn.isZero, rawIn_isZero node _rawIn_out_sign_T = bits(io.in, 32, 32) connect rawIn.sign, _rawIn_out_sign_T node _rawIn_out_sExp_T = cvt(rawIn_exp) connect rawIn.sExp, _rawIn_out_sExp_T node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0)) node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T) node _rawIn_out_sig_T_2 = bits(io.in, 22, 0) node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2) connect rawIn.sig, _rawIn_out_sig_T_3 node _io_out_T = shl(io.in, 0) connect io.out, _io_out_T node _io_exceptionFlags_T = bits(rawIn.sig, 22, 22) node _io_exceptionFlags_T_1 = eq(_io_exceptionFlags_T, UInt<1>(0h0)) node _io_exceptionFlags_T_2 = and(rawIn.isNaN, _io_exceptionFlags_T_1) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, UInt<4>(0h0)) connect io.exceptionFlags, _io_exceptionFlags_T_3	module RecFNToRecFN_123(); // @[RecFNToRecFN.scala:44:5] wire [8:0] rawIn_exp = 9'h2B; // @[rawFloatFromRecFN.scala:51:21] wire [9:0] rawIn_sExp = 10'h2B; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [9:0] _rawIn_out_sExp_T = 10'h2B; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [1:0] _rawIn_isSpecial_T = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] _rawIn_out_sig_T_1 = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [22:0] _rawIn_out_sig_T_2 = 23'h0; // @[rawFloatFromRecFN.scala:61:49] wire [24:0] rawIn_sig = 25'h0; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [24:0] _rawIn_out_sig_T_3 = 25'h0; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire rawIn_isSpecial = 1'h0; // @[rawFloatFromRecFN.scala:53:53, :55:23, :56:{33,41}, :57:{33,41}, :61:35] wire rawIn_isNaN = 1'h0; // @[rawFloatFromRecFN.scala:53:53, :55:23, :56:{33,41}, :57:{33,41}, :61:35] wire rawIn_isInf = 1'h0; // @[rawFloatFromRecFN.scala:53:53, :55:23, :56:{33,41}, :57:{33,41}, :61:35] wire _rawIn_out_isNaN_T = 1'h0; // @[rawFloatFromRecFN.scala:53:53, :55:23, :56:{33,41}, :57:{33,41}, :61:35] wire _rawIn_out_isNaN_T_1 = 1'h0; // @[rawFloatFromRecFN.scala:53:53, :55:23, :56:{33,41}, :57:{33,41}, :61:35] wire _rawIn_out_isInf_T = 1'h0; // @[rawFloatFromRecFN.scala:53:53, :55:23, :56:{33,41}, :57:{33,41}, :61:35] wire _rawIn_out_isInf_T_2 = 1'h0; // @[rawFloatFromRecFN.scala:53:53, :55:23, :56:{33,41}, :57:{33,41}, :61:35] wire _rawIn_out_sig_T = 1'h0; // @[rawFloatFromRecFN.scala:53:53, :55:23, :56:{33,41}, :57:{33,41}, :61:35] wire _io_exceptionFlags_T = 1'h0; // @[rawFloatFromRecFN.scala:53:53, :55:23, :56:{33,41}, :57:{33,41}, :61:35] wire _io_exceptionFlags_T_2 = 1'h0; // @[rawFloatFromRecFN.scala:53:53, :55:23, :56:{33,41}, :57:{33,41}, :61:35] wire [4:0] io_exceptionFlags = 5'h0; // @[RecFNToRecFN.scala:44:5, :48:16, :65:54] wire [4:0] _io_exceptionFlags_T_3 = 5'h0; // @[RecFNToRecFN.scala:44:5, :48:16, :65:54] wire io_detectTininess = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25] wire rawIn_isZero = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25] wire rawIn_isZero_0 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25] wire rawIn_sign = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25] wire _rawIn_out_isInf_T_1 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25] wire _rawIn_out_sign_T = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25] wire _io_exceptionFlags_T_1 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25] wire [2:0] io_roundingMode = 3'h0; // @[rawFloatFromRecFN.scala:52:28] wire [2:0] _rawIn_isZero_T = 3'h0; // @[rawFloatFromRecFN.scala:52:28] wire [32:0] io_in = 33'h115800000; // @[RecFNToRecFN.scala:44:5, :48:16, :64:35] wire [32:0] io_out = 33'h115800000; // @[RecFNToRecFN.scala:44:5, :48:16, :64:35] wire [32:0] _io_out_T = 33'h115800000; // @[RecFNToRecFN.scala:44:5, :48:16, :64:35] endmodule
Generate the Verilog code corresponding to this FIRRTL code module ResetCatchAndSync_d3 : input clock : Clock input reset : Reset output io : { sync_reset : UInt<1>, flip psd : { test_mode : UInt<1>, test_mode_reset : UInt<1>}} node _post_psd_reset_T = asUInt(reset) node post_psd_reset = mux(io.psd.test_mode, io.psd.test_mode_reset, _post_psd_reset_T) inst io_sync_reset_chain of AsyncResetSynchronizerShiftReg_w1_d3_i0_121 connect io_sync_reset_chain.clock, clock connect io_sync_reset_chain.reset, post_psd_reset connect io_sync_reset_chain.io.d, UInt<1>(0h1) wire _io_sync_reset_WIRE : UInt<1> connect _io_sync_reset_WIRE, io_sync_reset_chain.io.q node _io_sync_reset_T = not(_io_sync_reset_WIRE) node _io_sync_reset_T_1 = mux(io.psd.test_mode, io.psd.test_mode_reset, _io_sync_reset_T) connect io.sync_reset, _io_sync_reset_T_1	module ResetCatchAndSync_d3( // @[ResetCatchAndSync.scala:13:7] input clock, // @[ResetCatchAndSync.scala:13:7] input reset // @[ResetCatchAndSync.scala:13:7] ); wire _post_psd_reset_T = reset; // @[ResetCatchAndSync.scala:26:76] wire io_psd_test_mode = 1'h0; // @[ResetCatchAndSync.scala:13:7, :17:14] wire io_psd_test_mode_reset = 1'h0; // @[ResetCatchAndSync.scala:13:7, :17:14] wire _io_sync_reset_T_1; // @[ResetCatchAndSync.scala:28:25] wire io_sync_reset; // @[ResetCatchAndSync.scala:13:7] wire post_psd_reset = _post_psd_reset_T; // @[ResetCatchAndSync.scala:26:{27,76}] wire _io_sync_reset_WIRE; // @[ShiftReg.scala:48:24] wire _io_sync_reset_T = ~_io_sync_reset_WIRE; // @[ShiftReg.scala:48:24] assign _io_sync_reset_T_1 = _io_sync_reset_T; // @[ResetCatchAndSync.scala:28:25, :29:7] assign io_sync_reset = _io_sync_reset_T_1; // @[ResetCatchAndSync.scala:13:7, :28:25] AsyncResetSynchronizerShiftReg_w1_d3_i0_121 io_sync_reset_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (post_psd_reset), // @[ResetCatchAndSync.scala:26:27] .io_q (_io_sync_reset_WIRE) ); // @[ShiftReg.scala:45:23] endmodule

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